A3
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16
A2/Detection_cercle/bugs.txt
Normal file
16
A2/Detection_cercle/bugs.txt
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launch_runs synth_1 -jobs 6
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To work around the issue Black box :
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Open the synthesized run from the Vivado IDE. The Tcl equivalent would be:
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open_run synth_1 -name synth_1 -pr_config [current_pr_configuration]
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Enter the following command in the Tcl console:
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setup_pr_configurations -v -use_netlist -force
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Close the synthesized design. This can also be done from the Tcl console:
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close_design
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Launch the implementation run.
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136
A2/Detection_cercle/circle_detect/circle_detect.cpp
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136
A2/Detection_cercle/circle_detect/circle_detect.cpp
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#include "circle_detect.h"
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void mysobel(rgb_img_t &src, rgb_img_t &dst, int dir)
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{
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int const rows = MAX_HEIGHT;
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int const cols = MAX_WIDTH;
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rgb_img_t img0(rows, cols);
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if (dir)
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{
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hls::Sobel<1,0,3>(src, img0);
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}
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else
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{
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hls::Sobel<0,1,3>(src, img0);
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}
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hls::ConvertScaleAbs(img0, dst);
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}
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void mysobelxy(rgb_img_t &src, rgb_img_t &dst)
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{
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int const rows = MAX_HEIGHT;
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int const cols = MAX_WIDTH;
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rgb_img_t img0(rows, cols);
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rgb_img_t img1(rows, cols);
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rgb_img_t img2(rows, cols);
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rgb_img_t img3(rows, cols);
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hls::Duplicate(src, img0, img1);
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mysobel(img0, img2, 1);
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mysobel(img1, img3, 0);
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hls::AddWeighted(img2, 1, img3, 1, 0, dst);
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}
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void circle(rgb_img_t &src, rgb_img_t &dst){
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int const rows = MAX_HEIGHT;
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int const cols = MAX_WIDTH;
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int const delta = 1;
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int const circles = N_CIRCLE;
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// 1/sqrt(2) pour un rayon aussi grand que le diametre d'image
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int const diag = (rows+cols)*0.5;
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uint16_t rho;
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typedef hls::Mat<diag, 180/delta, HLS_12U> M_M;
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typedef hls::Mat<circles, 2, HLS_16U> M_Max;
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M_M M;
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M_Max Max;
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rgb_pix_t red(255,0,0);
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for(int d=0; d<diag; d++){
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Max<d,0> = 0;
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Max<d,1> = 0;
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}
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rgb_img_t img0(rows, cols);
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hls::CvtColor<HLS_GRAY2RGB>(src, dst);
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for (uint16_t r=0; r<rows; r++){
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for (uint16_t c=0; c<cols; c++){
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if(src(r,c) != 0){
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for (uint16_t t=0; t<180; t+=delta){
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rho = ceil(r*hls::cos(t)+c*hls::sin(t));
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M(rho,t) = M(rho,t) + 1;
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}
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}
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}
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}
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uint8_t m = 0;
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uint16_t threshold = 50;
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uint16_t x0, y0;
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while(m<circles){
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for (uint16_t c=0; c<circles; c++){
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for (uint16_t r=0; r<diag; r++){
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for (uint16_t t=0; t<180; t+=delta){
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if(M(r,t) > threshold){
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m++;
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x0 = ceil(rho * cos(t));
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y0 = ceil(rho * sin(t));
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Max(m,0) = x0 + 1000 * (-sin(t));
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Max(m,1) = y0 + 1000 * (cos(t));
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dst(Max(m,0),Max(m,1)) = red;
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dst(Max(m,0)+1,Max(m,1)) = red;
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dst(Max(m,0),Max(m,1)+1) = red;
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dst(Max(m,0+1),Max(m,1)+1) = red;
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}
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}
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}
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}
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}
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}
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void sobelfoo(stream_t &stream_in, stream_t &stream_out)
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{
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int const rows = MAX_HEIGHT;
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int const cols = MAX_WIDTH;
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rgb_img_t img0(rows, cols);
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rgb_img_t img1(rows, cols);
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rgb_img_t img2(rows, cols);
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rgb_img_t img3(rows, cols);
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rgb_img_t img4(rows, cols);
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hls::AXIvideo2Mat(stream_in, img0);
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hls::CvtColor<HLS_RGB2GRAY>(img0, img1);
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hls::GaussianBlur<5,5>(img1, img2, (double)5, (double)5);
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mysobelxy(img2,img3);
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circle(img3, img4);
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hls::Mat2AXIvideo(img4, stream_out);
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}
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void circle_detect(stream_t &stream_in, stream_t &stream_out)
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{
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int const rows = MAX_HEIGHT;
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int const cols = MAX_WIDTH;
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sobelfoo(stream_in, stream_out);
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}
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17
A2/Detection_cercle/circle_detect/circle_detect.h
Normal file
17
A2/Detection_cercle/circle_detect/circle_detect.h
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#include "hls_video.h"
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typedef ap_axiu<24,1,1,1> interface_t;
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typedef ap_uint<3> interface_3_bits;
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typedef hls::stream<interface_t> stream_t;
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void edge_detect(stream_t &stream_in, stream_t &stream_out);
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#define MAX_WIDTH 1920
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#define MAX_HEIGHT 1080
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#define N_CIRCLE 2
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typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> rgb_img_t;
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typedef hls::Scalar<3, unsigned char> rgb_pix_t;
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#define INPUT_IMAGE "rover.bmp"
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#define OUTPUT_IMAGE "rover_out.bmp"
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@ -0,0 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<autopilotfilemapping:AutoPilotFileMapping xmlns:autopilotfilemapping="www.autoesl.com/autopilotfilemapping">
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<source>
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<originFiles name="circle_detect.cpp" path="C:\Users\Sasa\Documents\M2R\M2_SETI\A2\Detection_cercle\circle_detect\circle_detect.cpp"/>
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<originFiles name="circle_detect.h" path="C:\Users\Sasa\Documents\M2R\M2_SETI\A2\Detection_cercle\circle_detect\circle_detect.h"/>
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</source>
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<testbench>
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<originFiles name="circle_detect_test.cpp" path="C:\Users\Sasa\Documents\M2R\M2_SETI\A2\Detection_cercle\circle_detect\circle_detect_test.cpp"/>
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<originFiles name="rover.bmp" path="C:\Users\Sasa\Documents\M2R\M2_SETI\A2\Detection_cercle\circle_detect\rover.bmp"/>
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</testbench>
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</autopilotfilemapping:AutoPilotFileMapping>
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362
A2/Detection_cercle/circle_detect/circle_detect/.cproject
Normal file
362
A2/Detection_cercle/circle_detect/circle_detect/.cproject
Normal file
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@ -0,0 +1,362 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<builder buildPath="${workspace_loc:/circle_detect}/Debug" id="cdt.managedbuild.target.gnu.builder.exe.debug.1546085749" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.exe.debug"/>
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110
A2/Detection_cercle/circle_detect/circle_detect/.project
Normal file
110
A2/Detection_cercle/circle_detect/circle_detect/.project
Normal file
|
|
@ -0,0 +1,110 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<link>
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<name>source</name>
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<type>2</type>
|
||||
<location>C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/.apc/.src</location>
|
||||
</link>
|
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<link>
|
||||
<name>testbench</name>
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||||
<type>2</type>
|
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<location>C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/.apc/.tb</location>
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<link>
|
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<name>.reference/hls_math.h</name>
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<type>1</type>
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<link>
|
||||
<name>.reference/hls_video_arithm.h</name>
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|
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<location>C:/Xilinx/Vivado/2019.1/include/hls/hls_video_arithm.h</location>
|
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|
||||
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|
||||
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|
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|
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<location>C:/Xilinx/Vivado/2019.1/include/hls/hls_video_core.h</location>
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|
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|
||||
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|
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|
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|
||||
<name>.reference/hls_video_io.h</name>
|
||||
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||||
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|
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</link>
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<link>
|
||||
<name>.reference/hls_video_types.h</name>
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|
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|
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|
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<link>
|
||||
<name>solution1/constraints</name>
|
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<type>2</type>
|
||||
<location>C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1/.tcls</location>
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|
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|
||||
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|
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|
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|
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|
||||
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||||
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|
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|
||||
<link>
|
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|
||||
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||||
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|
||||
<name>solution1/constraints/script.tcl</name>
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|
|
@ -0,0 +1,12 @@
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<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/a.exe"/>
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<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="circle_detect"/>
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||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;directory nest=&quot;true&quot; path=&quot;C:\Xilinx\Vivado\2019.1\win64\tools\systemc&quot;/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.directory"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
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</launchConfiguration>
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||||
|
|
@ -0,0 +1,48 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project>
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|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1543514302395853231" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
|
||||
</provider>
|
||||
|
||||
</extension>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration id="cdt.managedbuild.config.gnu.exe.release.133009526" name="Release">
|
||||
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1543514302395853231" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
|
||||
</provider>
|
||||
|
||||
</extension>
|
||||
|
||||
</configuration>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<vivadoHLSLog:LogRoot xmlns:vivadoHLSLog="www.xilinx.com/vivadoHLSLog">
|
||||
<errorLogs>
|
||||
<logs>
|
||||
<csimLog>
|
||||
<logs message="ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s)." projectName="circle_detect" solutionName="solution1" date="2021-02-14T18:48:54.616+0100"/>
|
||||
<logs message="ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s)." projectName="circle_detect" solutionName="solution1" date="2021-02-14T18:45:44.532+0100"/>
|
||||
<logs message="ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s)." projectName="circle_detect" solutionName="solution1" date="2023-02-14T18:45:15.331+0100"/>
|
||||
</csimLog>
|
||||
</logs>
|
||||
</errorLogs>
|
||||
<warningLogs>
|
||||
<logs>
|
||||
<csimLog/>
|
||||
</logs>
|
||||
</warningLogs>
|
||||
</vivadoHLSLog:LogRoot>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
18:48:54
|
||||
02/14/2021
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Messages>
|
||||
<Message severity="INFO" prefix="[SIM 211-2]" key="SIM_2_1569" tag="" content="*************** CSIM start ***************"/>
|
||||
<Message severity="INFO" prefix="[SIM 211-4]" key="SIM_4_1577" tag="" content="CSIM will launch GCC as the compiler."/>
|
||||
<Message severity="ERROR" prefix="[SIM 211-100]" key="SIM_100_1589" tag="" content="'csim_design' failed: compilation error(s)."/>
|
||||
<Message severity="INFO" prefix="[SIM 211-3]" key="SIM_3_1588" tag="" content="*************** CSIM finish ***************"/>
|
||||
</Messages>
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Tue Feb 14 18:44:57 +0100 2023
|
||||
Execute config_clock -quiet -name default -period 10 -default=false
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Command import_lib done; 0.128 sec.
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
|
||||
Command ap_source done; 0.192 sec.
|
||||
Command ap_source done; 0.196 sec.
|
||||
Execute set_part xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
|
||||
Command ap_part_info done; 0.754 sec.
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
|
||||
Execute get_default_platform
|
||||
Execute license_isbetapart xc7z020
|
||||
Command license_isbetapart done; error code: 1;
|
||||
Execute ap_part_info -data single -name xc7z020-clg400-1
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Execute add_library xilinx/zynq/zynq_fpv6
|
||||
Execute get_default_platform
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute get_default_platform
|
||||
Command set_part done; 0.917 sec.
|
||||
Execute ap_part_info -data single -name xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Command open_solution done; 1.282 sec.
|
||||
Execute csim_design -quiet
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
Command csim_design done; error code: 2; 16.432 sec.
|
||||
Command ap_source done; error code: 1; 17.735 sec.
|
||||
Execute cleanup_all
|
||||
INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Sun Feb 14 18:45:36 +0100 2021
|
||||
Execute config_clock -quiet -name default -period 10 -default=false
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
|
||||
Command ap_source done; 0.121 sec.
|
||||
Command ap_source done; 0.121 sec.
|
||||
Execute set_part xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
|
||||
Command ap_part_info done; 0.749 sec.
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
|
||||
Execute get_default_platform
|
||||
Execute license_isbetapart xc7z020
|
||||
Command license_isbetapart done; error code: 1;
|
||||
Execute ap_part_info -data single -name xc7z020-clg400-1
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Execute add_library xilinx/zynq/zynq_fpv6
|
||||
Execute get_default_platform
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute get_default_platform
|
||||
Command set_part done; 0.866 sec.
|
||||
Execute ap_part_info -data single -name xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Command open_solution done; 1.032 sec.
|
||||
Execute csim_design -quiet
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
Execute source csim/.lst_opt.tcl
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
Command csim_design done; error code: 2; 7.141 sec.
|
||||
Command ap_source done; error code: 1; 8.18 sec.
|
||||
Execute cleanup_all
|
||||
INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Sun Feb 14 18:48:34 +0100 2021
|
||||
Execute config_clock -quiet -name default -period 10 -default=false
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
|
||||
Command ap_source done; 0.118 sec.
|
||||
Command ap_source done; 0.118 sec.
|
||||
Execute set_part xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
|
||||
Command ap_part_info done; 0.734 sec.
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
|
||||
Execute get_default_platform
|
||||
Execute license_isbetapart xc7z020
|
||||
Command license_isbetapart done; error code: 1;
|
||||
Execute ap_part_info -data single -name xc7z020-clg400-1
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Execute add_library xilinx/zynq/zynq_fpv6
|
||||
Execute get_default_platform
|
||||
Execute open_platform DefaultPlatform
|
||||
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
|
||||
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
Execute ap_part_info -name xc7z020-clg400-1 -data info
|
||||
Execute get_default_platform
|
||||
Command set_part done; 0.845 sec.
|
||||
Execute ap_part_info -data single -name xc7z020clg400-1
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data resources
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
Execute config_chip_info -quiet -speed slow
|
||||
Command open_solution done; 1.005 sec.
|
||||
Execute csim_design -clean -quiet
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
Execute source csim/.lst_opt.tcl
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
|
||||
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
|
||||
Execute ap_part_info -name xc7z020clg400-1 -data info
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
Command csim_design done; error code: 2; 18.709 sec.
|
||||
Command ap_source done; error code: 1; 19.735 sec.
|
||||
Execute cleanup_all
|
||||
|
|
@ -0,0 +1 @@
|
|||
DSP48E1
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
set useapcc 1
|
||||
set useclang 0
|
||||
set platform 2
|
||||
set opt 0
|
||||
set setup 0
|
||||
|
|
@ -0,0 +1,525 @@
|
|||
#===- Makefile.sysc.rules ----------------------------------*- Makefile -*--===#
|
||||
#
|
||||
# Makefile rules for autopilot SystemC simulation flow
|
||||
#
|
||||
#- (c) Copyright 2011-2019 Xilinx, Inc. All rights reserved.
|
||||
#-
|
||||
#- This file contains confidential and proprietary information
|
||||
#- of Xilinx, Inc. and is protected under U.S. and
|
||||
#- international copyright and other intellectual property
|
||||
#- laws.
|
||||
#-
|
||||
#- DISCLAIMER
|
||||
#- This disclaimer is not a license and does not grant any
|
||||
#- rights to the materials distributed herewith. Except as
|
||||
#- otherwise provided in a valid license issued to you by
|
||||
#- Xilinx, and to the maximum extent permitted by applicable
|
||||
#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
#- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
#- including negligence, or under any other theory of
|
||||
#- liability) for any loss or damage of any kind or nature
|
||||
#- related to, arising under or in connection with these
|
||||
#- materials, including for any direct, or any indirect,
|
||||
#- special, incidental, or consequential loss or damage
|
||||
#- (including loss of data, profits, goodwill, or any type of
|
||||
#- loss or damage suffered as a result of any action brought
|
||||
#- by a third party) even if such damage or loss was
|
||||
#- reasonably foreseeable or Xilinx had been advised of the
|
||||
#- possibility of the same.
|
||||
#-
|
||||
#- CRITICAL APPLICATIONS
|
||||
#- Xilinx products are not designed or intended to be fail-
|
||||
#- safe, or for use in any application requiring fail-safe
|
||||
#- performance, such as life-support or safety devices or
|
||||
#- systems, Class III medical devices, nuclear facilities,
|
||||
#- applications related to the deployment of airbags, or any
|
||||
#- other applications that could lead to death, personal
|
||||
#- injury, or severe property or environmental damage
|
||||
#- (individually and collectively, "Critical
|
||||
#- Applications"). Customer assumes the sole risk and
|
||||
#- liability of any use of Xilinx products in Critical
|
||||
#- Applications, subject only to applicable laws and
|
||||
#- regulations governing limitations on product liability.
|
||||
#-
|
||||
#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
#- PART OF THIS FILE AT ALL TIMES.
|
||||
#- ************************************************************************
|
||||
|
||||
#
|
||||
#===------------------------------------------------------------------------===#
|
||||
|
||||
|
||||
# Required user variables:
|
||||
#TARGET
|
||||
|
||||
# Optional variables:
|
||||
#ExtraCFlags
|
||||
#ExtraCXXFlags
|
||||
#ExtraLDFlags
|
||||
|
||||
# Users may have their own SystemC enviornments, by defineing the
|
||||
# following variables
|
||||
#HLS_SYSTEMC_HOME
|
||||
#HLS_SYSTEMC_LIB_PATH
|
||||
|
||||
### Common shell commands.
|
||||
Echo = @echo
|
||||
MKDIR = mkdir -p
|
||||
Make = make
|
||||
MV = mv
|
||||
RM = rm
|
||||
CP = cp
|
||||
CD = cd
|
||||
|
||||
### Directory for object files.
|
||||
ifndef ObjDir
|
||||
ObjDir := obj
|
||||
endif
|
||||
|
||||
### Switch for displaying detailed information.
|
||||
#VERBOSE = 1
|
||||
|
||||
|
||||
ifdef VERBOSE
|
||||
Verb :=
|
||||
else
|
||||
Verb := @
|
||||
endif
|
||||
|
||||
ifndef AUTOPILOT_TOOL
|
||||
AUTOPILOT_TOOL = "$(shell vivado_hls -proot)/tools"
|
||||
endif
|
||||
|
||||
ifndef AUTOPILOT_TECH
|
||||
AUTOPILOT_TECH = "$(AUTOPILOT_ROOT)/common/technology"
|
||||
endif
|
||||
|
||||
ifndef HLS_SYSTEMC_HOME
|
||||
HLS_SYSTEMC_HOME = $(AUTOPILOT_TOOL)/systemc
|
||||
endif
|
||||
|
||||
ifndef HLS_SYSTEMC_LIB_PATH
|
||||
ifeq ($(AUTOPILOT_MACH),win64)
|
||||
ifdef __USE_CLANG__
|
||||
HLS_SYSTEMC_LIB_PATH = $(AUTOPILOT_TOOL)/systemc/clang
|
||||
else
|
||||
HLS_SYSTEMC_LIB_PATH = $(AUTOPILOT_TOOL)/systemc/gcc
|
||||
endif
|
||||
else
|
||||
HLS_SYSTEMC_LIB_PATH = $(AUTOPILOT_TOOL)/systemc/lib
|
||||
endif
|
||||
endif
|
||||
|
||||
ifndef HLS_FPO_LIB_PATH
|
||||
HLS_FPO_LIB_PATH = $(AUTOPILOT_TOOL)/fpo_v7_0
|
||||
endif
|
||||
|
||||
ifndef HLS_OPENCV_LIB_PATH
|
||||
ifneq ($(AUTOPILOT_MACH),win64)
|
||||
#ifdef __USE_CLANG__
|
||||
# HLS_OPENCV_LIB_PATH = $(AUTOPILOT_TOOL)/opencv/opencv_clang
|
||||
#else
|
||||
HLS_OPENCV_LIB_PATH = $(AUTOPILOT_TOOL)/opencv/opencv_gcc
|
||||
#endif
|
||||
else
|
||||
HLS_OPENCV_LIB_PATH = $(AUTOPILOT_TOOL)/opencv
|
||||
endif
|
||||
endif
|
||||
|
||||
ifndef HLS_FFT_LIB_PATH
|
||||
HLS_FFT_LIB_PATH = $(AUTOPILOT_TOOL)/fft_v9_1
|
||||
endif
|
||||
|
||||
ifndef HLS_FIR_LIB_PATH
|
||||
HLS_FIR_LIB_PATH = $(AUTOPILOT_TOOL)/fir_v7_0
|
||||
endif
|
||||
|
||||
ifndef HLS_DDS_LIB_PATH
|
||||
HLS_DDS_LIB_PATH = $(AUTOPILOT_TOOL)/dds_v6_0
|
||||
endif
|
||||
|
||||
ifndef HLS_MATHHLS_LIB_PATH
|
||||
HLS_MATHHLS_LIB_PATH = $(AUTOPILOT_ROOT)/$(AUTOPILOT_MACH)/lib/csim
|
||||
endif
|
||||
|
||||
|
||||
ifdef __USE_CLANG__
|
||||
ifdef AP_CLANG_PATH
|
||||
CC = $(AP_CLANG_PATH)/clang
|
||||
CXX = $(AP_CLANG_PATH)/clang++
|
||||
else
|
||||
CC = clang
|
||||
CXX = clang++
|
||||
endif
|
||||
else
|
||||
ifdef AP_GCC_PATH
|
||||
CC = $(AP_GCC_PATH)/gcc
|
||||
CXX = $(AP_GCC_PATH)/g++
|
||||
else
|
||||
CC = gcc
|
||||
CXX = g++
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef __USE_CLANG_M32__
|
||||
CC += -m32
|
||||
CXX += -m32
|
||||
endif
|
||||
|
||||
LINUX =
|
||||
INCPATH = .
|
||||
SRCPATH = .
|
||||
BINPATH = .
|
||||
SYSC = $(HLS_SYSTEMC_HOME)
|
||||
SYSCINC = $(SYSC)/include
|
||||
SYSCLIB = $(HLS_SYSTEMC_LIB_PATH)
|
||||
FPOLIB = $(HLS_FPO_LIB_PATH)
|
||||
OPENCVLIB = $(HLS_OPENCV_LIB_PATH)
|
||||
FFTLIB = $(HLS_FFT_LIB_PATH)
|
||||
FIRLIB = $(HLS_FIR_LIB_PATH)
|
||||
DDSLIB = $(HLS_DDS_LIB_PATH)
|
||||
MATHHLSLIB = $(HLS_MATHHLS_LIB_PATH)
|
||||
DEFINE =
|
||||
ATBG_CFLAG = -DSST_SIM_ENABLE -DSST_ATBG_ENABLE
|
||||
IFLAG += -I $(INCPATH) -I "$(SYSCINC)"
|
||||
IFLAG += -I "$(AUTOPILOT_ROOT)/include"
|
||||
#IFLAG += -I "$(AUTOPILOT_TECH)/autopilot/sim"
|
||||
#IFLAG += -I "$(AUTOPILOT_TECH)/autopilot/etc"
|
||||
IFLAG += -I "$(AUTOPILOT_TECH)/generic/SystemC/AESL_comp"
|
||||
LFLAG += -Wl,--as-needed
|
||||
LFLAG += -Wl,-rpath,"$(SYSCLIB)" -L "$(SYSCLIB)" -lsystemc -lpthread
|
||||
|
||||
ifdef __SIM_MATHHLS__
|
||||
|
||||
ifdef __USE_CLANG__
|
||||
ifeq ($(AUTOPILOT_MACH),win64)
|
||||
LFLAG += -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsmc++-CLANG39-x64
|
||||
else
|
||||
LFLAG += -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsmc++-CLANG39
|
||||
endif
|
||||
else
|
||||
ifeq ($(AUTOPILOT_MACH),win64)
|
||||
LFLAG += -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsmc++-GCC62-x64
|
||||
else
|
||||
LFLAG += -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsmc++-GCC46
|
||||
endif
|
||||
endif
|
||||
|
||||
ifndef __SIM_MATHSTD__
|
||||
ifdef __USE_CLANG__
|
||||
ifeq ($(AUTOPILOT_MACH),win64)
|
||||
LFLAG += -fno-builtin -fno-inline -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsm-CLANG39-x64
|
||||
else
|
||||
LFLAG += -fno-builtin -fno-inline -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsm-CLANG39
|
||||
endif
|
||||
else
|
||||
ifeq ($(AUTOPILOT_MACH),win64)
|
||||
LFLAG += -fno-builtin -fno-inline -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsm-GCC62-x64
|
||||
else
|
||||
LFLAG += -fno-builtin -fno-inline -Wl,-rpath,"$(MATHHLSLIB)" -L "$(MATHHLSLIB)" -lhlsm-GCC46
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
export LD_LIBRARY_PATH := ${LD_LIBRARY_PATH}:$(MATHHLSLIB)
|
||||
endif
|
||||
|
||||
ifdef __SIM_FPO__
|
||||
LFLAG += -Wl,-rpath,"$(FPOLIB)" -L "$(FPOLIB)" -lgmp -lmpfr -lIp_floating_point_v7_0_bitacc_cmodel
|
||||
endif
|
||||
|
||||
ifdef __SIM_OPENCV__
|
||||
ifeq ($(shell uname -s), Linux)
|
||||
LFLAG += -Wl,-rpath,"$(OPENCVLIB)" -L "$(OPENCVLIB)" -lopencv_calib3d -lopencv_contrib -lopencv_core -lopencv_features2d -lopencv_flann -lopencv_gpu -lopencv_highgui -lopencv_imgproc -lopencv_legacy -lopencv_ml -lopencv_objdetect -lopencv_photo -lopencv_stitching -lopencv_superres -lopencv_ts -lopencv_video -lopencv_videostab
|
||||
else
|
||||
CV_VER = 245
|
||||
#delete lopencv_superres245 for win64
|
||||
LFLAG += -Wl,-rpath,"$(OPENCVLIB)" -L "$(OPENCVLIB)" -lopencv_calib3d$(CV_VER) -lopencv_contrib$(CV_VER) -lopencv_core$(CV_VER) -lopencv_features2d$(CV_VER) -lopencv_flann$(CV_VER) -lopencv_gpu$(CV_VER) -lopencv_highgui$(CV_VER) -lopencv_imgproc$(CV_VER) -lopencv_legacy$(CV_VER) -lopencv_ml$(CV_VER) -lopencv_objdetect$(CV_VER) -lopencv_photo$(CV_VER) -lopencv_stitching$(CV_VER) -lopencv_video$(CV_VER) -lopencv_videostab$(CV_VER)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef __SIM_FFT__
|
||||
LFLAG += -Wl,-rpath,"$(FFTLIB)" -L "$(FFTLIB)" -lIp_xfft_v9_1_bitacc_cmodel
|
||||
export LD_LIBRARY_PATH := ${LD_LIBRARY_PATH}:$(FFTLIB)
|
||||
endif
|
||||
|
||||
ifdef __SIM_FIR__
|
||||
LFLAG += -Wl,-rpath,"$(FIRLIB)" -L "$(FIRLIB)" -lgmp -lIp_fir_compiler_v7_2_bitacc_cmodel
|
||||
export LD_LIBRARY_PATH := ${LD_LIBRARY_PATH}:$(FIRLIB)
|
||||
endif
|
||||
|
||||
ifdef __SIM_DDS__
|
||||
LFLAG += -Wl,-rpath,"$(DDSLIB)" -L "$(DDSLIB)" -lIp_dds_compiler_v6_0_bitacc_cmodel
|
||||
export LD_LIBRARY_PATH := ${LD_LIBRARY_PATH}:$(DDSLIB)
|
||||
endif
|
||||
|
||||
CFLAG += $(DEBUG) $(DEFINE) -DC_TEST
|
||||
CFLAG += $(ATBG_CFLAG)
|
||||
|
||||
# Only for glibc2.12 bug, define __USE_XOPEN2K8, CR694034.
|
||||
RUNNING_LINUX := "$(shell uname | grep -i Linux)"
|
||||
ifeq ($(RUNNING_LINUX),"Linux")
|
||||
LDD_VERSION = "$(shell ldd --version | grep 2.12)"
|
||||
ifneq ($(LDD_VERSION), "")
|
||||
CFLAG += -D__USE_XOPEN2K8
|
||||
DFLAG += -D__USE_XOPEN2K8
|
||||
endif
|
||||
else
|
||||
CFLAG += -D__USE_XOPEN2K8
|
||||
DFLAG += -D__USE_XOPEN2K8
|
||||
endif
|
||||
|
||||
|
||||
ifndef HLS_SOURCES
|
||||
# Find all .cpp, .cp, .cxx, .cc, .c++, .c, .C in current directory and in $(HLS_RtlSCDir).
|
||||
SUFFIX_CPP = cpp
|
||||
SUFFIX_CP = cp
|
||||
SUFFIX_CXX = cxx
|
||||
SUFFIX_CC = cc
|
||||
SUFFIX_C++ = c++
|
||||
SUFFIX_c = c
|
||||
SUFFIX_C = C
|
||||
SOURCES_CPP = $(wildcard *.$(SUFFIX_CPP))
|
||||
SOURCES_CP = $(wildcard *.$(SUFFIX_CP))
|
||||
SOURCES_CXX = $(wildcard *.$(SUFFIX_CXX))
|
||||
SOURCES_CC = $(wildcard *.$(SUFFIX_CC))
|
||||
SOURCES_C++ = $(wildcard *.$(SUFFIX_C++))
|
||||
SOURCES_c = $(wildcard *.$(SUFFIX_c))
|
||||
SOURCES_C = $(wildcard *.$(SUFFIX_C))
|
||||
|
||||
ifdef HLS_RtlSCDir
|
||||
SOURCES_CPP += $(wildcard $(HLS_RtlSCDir)/*.cpp)
|
||||
SOURCES_CC += $(wildcard $(HLS_RtlSCDir)/*.cc)
|
||||
SOURCES_C += $(wildcard $(HLS_RtlSCDir)/*.c)
|
||||
endif
|
||||
|
||||
FILE_SOURCES_CPP = $(notdir $(SOURCES_CPP))
|
||||
FILE_SOURCES_CC = $(notdir $(SOURCES_CC))
|
||||
FILE_SOURCES_C = $(notdir $(SOURCES_C))
|
||||
|
||||
override HLS_SOURCES = $(SOURCES_CPP) $(SOURCES_CP) $(SOURCES_CXX) $(SOURCES_CC) $(SOURCES_C++) $(SOURCES_c) $(SOURCES_C)
|
||||
endif
|
||||
|
||||
OBJECTS := $(basename $(notdir $(HLS_SOURCES)))
|
||||
OBJECTS := $(OBJECTS:%=$(ObjDir)/%.o)
|
||||
|
||||
|
||||
ERR_FILE = err.log
|
||||
|
||||
ERRNO=`wc -l $(ERR_FILE) | sed "s/ $(ERR_FILE)//"`
|
||||
|
||||
.debug1::
|
||||
$(Echo) "2 src: $(HLS_SOURCES)"
|
||||
$(Echo) "2 obj: $(OBJECTS)"
|
||||
#--------------------------------------------------------------------
|
||||
# Set the VPATH so that we can find source files.
|
||||
#--------------------------------------------------------------------
|
||||
VPATH=$(HLS_RtlSCDir)
|
||||
|
||||
#--------------------------------------------------------------------
|
||||
# Reset the list of suffixes we know how to build
|
||||
#--------------------------------------------------------------------
|
||||
.SUFFIXES:
|
||||
.SUFFIXES: .c .cc .cpp .h
|
||||
|
||||
|
||||
#ENABLE_PROFILING :=
|
||||
#ENABLE_OPTIMIZED := 1
|
||||
|
||||
ifdef ENABLE_PROFILING
|
||||
BuildMode := profile
|
||||
CXX.Flags := -O3 -DNDEBUG -felide-constructors -finline-functions -pg
|
||||
C.Flags := -O3 -DNDEBUG -pg
|
||||
LD.Flags := -O3 -DNDEBUG -pg
|
||||
else
|
||||
ifdef AP_ENABLE_OPTIMIZED
|
||||
BuildMode := release
|
||||
#CXX.Flags := -O3 -DNDEBUG -finline-functions \
|
||||
# -felide-constructors -fomit-frame-pointer
|
||||
CXX.Flags := -O1 -DNDEBUG
|
||||
C.Flags := -O1 -DNDEBUG -fomit-frame-pointer
|
||||
LD.Flags := -O1 -DNDEBUG
|
||||
else
|
||||
BuildMode := debug
|
||||
CXX.Flags := -D_DEBUG
|
||||
C.Flags := -D_DEBUG
|
||||
ifdef __USE_CLANG__
|
||||
LD.Flags := -D_DEBUG -g -O1
|
||||
else
|
||||
LD.Flags := -D_DEBUG
|
||||
endif
|
||||
KEEP_SYMBOLS := 1
|
||||
endif
|
||||
endif
|
||||
|
||||
|
||||
CPPFLAGS += $(IFLAG) $(CFLAG)
|
||||
CFLAGS += $(IFLAG) $(CFLAG)
|
||||
LDFLAGS += $(LFLAG)
|
||||
|
||||
ifdef AP_GCC_M32
|
||||
CFLAGS += -m32
|
||||
CPPFLAGS += -m32
|
||||
LDFLAGS += -m32
|
||||
endif
|
||||
|
||||
ifdef __USE_CLANG__
|
||||
CXX.Flags += $(CXXFLAGS) -fpermissive $(ExtraCXXFlags) $(TOOLCHAIN)
|
||||
else
|
||||
CXX.Flags += $(CXXFLAGS) -fpermissive $(ExtraCXXFlags)
|
||||
endif
|
||||
C.Flags += $(CFLAGS) $(ExtraCFlags)
|
||||
CPP.Flags += $(CPPFLAGS)
|
||||
LD.Flags += $(LDFLAGS) $(ExtraLDFlags)
|
||||
AR.Flags := cru
|
||||
LibTool.Flags := --tag=CXX
|
||||
#CompileCommonOpts := -Wall -W -Wwrite-strings -Wno-unused
|
||||
CompileCommonOpts :=
|
||||
|
||||
ifdef __USE_CLANG__
|
||||
ifdef __COSIM_FLOW__
|
||||
#CompileCommonOpts += -D_GLIBCXX_USE_CXX11_ABI=0
|
||||
endif
|
||||
endif
|
||||
|
||||
#-------------- C/C++ to binary ----------------------------------------
|
||||
Compile.C = $(CC) $(CPP.Flags) $(CompileCommonOpts) -c $(C.Flags)
|
||||
Compile.CXX = $(CXX) $(CPP.Flags) $(CompileCommonOpts) $(CXX.Flags) -c
|
||||
|
||||
CXXPATH = $(shell which ${CXX})
|
||||
|
||||
ifndef CSIM_DESIGN
|
||||
$(TARGET)::
|
||||
$(Echo) " Build using \"${CXXPATH}\""
|
||||
endif
|
||||
|
||||
$(TARGET):: $(ObjDir)/.dir $(OBJECTS)
|
||||
$(Echo) " Generating $(TARGET)" $(AVE_DIR_DLOG)
|
||||
$(Verb)$(CXX) $(OBJECTS) $(LD.Flags) -o $@
|
||||
|
||||
# $(Echo) "[$(MSGH)] Done!" $(AVE_DIR_DLOG)
|
||||
|
||||
|
||||
#---------- Auto CPP/C Dependencies ----------
|
||||
$(ObjDir)/%.o: %.cpp $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.cpp" $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.CXX) $(DFLAG) -MD -MT $@ -MP -MF $(ObjDir)/$*.CXXd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.CXXd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.CXXd"; exit 1; fi
|
||||
|
||||
$(ObjDir)/%.o: %.cc $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.cc" $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.CXX) $(DFLAG) -MD -MT $@ -MP -MF $(ObjDir)/$*.CXXd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.CXXd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.CXXd"; exit 1; fi
|
||||
|
||||
$(ObjDir)/%.o: %.c $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.c" $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.C) $(DFLAG) -MD -MT $@ -MP -MF $(ObjDir)/$*.Cd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.Cd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.Cd"; exit 1; fi
|
||||
|
||||
|
||||
# This rules ensures that header files that are removed still have a rule for
|
||||
# which they can be "generated." This allows make to ignore them and
|
||||
# reproduce the dependency lists.
|
||||
%.h:: ;
|
||||
|
||||
|
||||
#-------------- C/C++ to virtual binary --------------------------------
|
||||
# You can use ExtraUserBCs to add additional BC object files to be linked.
|
||||
#
|
||||
# set CFLAGS "-DAESL_SYN -I${AUTOPILOT_INC} -I${MATH_INC} \
|
||||
# -O0 -c -emit-llvm $ExtCFlags"
|
||||
|
||||
Extra.BCCPP.Flags += -emit-llvm -DAUTOPILOT_BC_SIM
|
||||
BCC.Flags = $(CPP.Flags) $(CompileCommonOpts) $(C.Flags) $(Extra.BCCPP.Flags)
|
||||
BCCXX.Flags = $(CPP.Flags) $(CompileCommonOpts) $(CXX.Flags) $(Extra.BCCPP.Flags)
|
||||
Compile.BCC = $(AUTOPILOT_TOOL)/clang/bin/clang -hls $(BCC.Flags) -c -emit-llvm
|
||||
Compile.BCCXX = $(AUTOPILOT_TOOL)/clang/bin/clang++ -hls $(BCCXX.Flags) -c -emit-llvm
|
||||
Compile.BCLD = $(AUTOPILOT_TOOL)/clang/bin/llvm-ld -disable-inlining
|
||||
|
||||
#ifndef BCLibDir
|
||||
#BCLibDir = $(HLS_RtlSCDir)/../tmp
|
||||
#endif
|
||||
|
||||
#ExtraUserBCs := $(wildcard $(BCLibDir)/*.o.3.sim.bc)
|
||||
#ExtraUsers := $(notdir $(ExtraUsers))
|
||||
|
||||
#VPATH=$(BCLibDir):$(VPATH)
|
||||
|
||||
SOURCES_C.BC += $(wildcard *.c)
|
||||
OBJECTS_C.BC = $(SOURCES_C.BC:%.c=$(ObjDir)/%.bc)
|
||||
|
||||
OBJECTS.BC = $(ExtraUserBCs) $(OBJECTS_C.BC)
|
||||
|
||||
.debug2:
|
||||
$(Echo) "$(ExtraUsers)"
|
||||
$(Echo) "$(OBJECTS.BC)"
|
||||
|
||||
|
||||
$(TARGET.BC): $(OBJECTS.BC)
|
||||
$(Echo) " Generating BC $(TARGET.BC) from $(OBJECTS.BC)" $(AVE_DIR_DLOG)
|
||||
$(Verb)$(Compile.BCLD) $(OBJECTS.BC) $(BCLD.Flags) -o $@
|
||||
|
||||
# $(Echo) "[$(MSGH)] Done!" $(AVE_DIR_DLOG)
|
||||
|
||||
#---------- Auto CPP/C to BC Dependencies ----------
|
||||
$(ObjDir)/%.bc: %.cpp $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.cpp in bc." $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.BCCXX) -MD -MT $@ -MP -MF $(ObjDir)/$*.CXXd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.CXXd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.CXXd"; exit 1; fi
|
||||
|
||||
$(ObjDir)/%.bc: %.cc $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.cpp in bc." $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.BCCXX) -MD -MT $@ -MP -MF $(ObjDir)/$*.CXXd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.CXXd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.CXXd"; exit 1; fi
|
||||
|
||||
$(ObjDir)/%.bc: %.c $(ObjDir)/.dir
|
||||
$(Echo) " Compiling $*.c in bc" $(AVE_DIR_DLOG)
|
||||
$(Verb) if $(Compile.BCC) -MD -MT $@ -MP -MF $(ObjDir)/$*.Cd $< -o $@ ; \
|
||||
then $(MV) -f "$(ObjDir)/$*.Cd" "$(ObjDir)/$*.d"; \
|
||||
else $(RM) -f "$(ObjDir)/$*.Cd"; exit 1; fi
|
||||
|
||||
|
||||
#---------- Include CPP Dependencies
|
||||
Sources := $(HLS_SOURCES)
|
||||
DependFiles := $(basename $(filter %.cpp %.c %.cc, $(Sources)))
|
||||
DependFiles := $(patsubst %,$(ObjDir)/%.d,$(DependFiles))
|
||||
-include /dev/null $(DependFiles)
|
||||
|
||||
.debug:
|
||||
$(Echo) $(DependFiles)
|
||||
|
||||
#--- To create other directories, as needed, and timestamp their creation
|
||||
%/.dir:
|
||||
$(Verb) $(MKDIR) $* >/dev/null
|
||||
$(Verb) $(DATE) > $@
|
||||
|
||||
.PRECIOUS: $(ObjDir)/.dir
|
||||
|
||||
|
||||
debug:
|
||||
make DEBUG="-g -D_DEBUG" -f Makefile
|
||||
|
||||
clean:
|
||||
$(Echo) "[$(MSGH)] Removing $(OBJECTS) $(DependFiles) $(TARGET) .." $(AVE_DIR_DLOG)
|
||||
$(Verb)-rm -rf $(OBJECTS)
|
||||
$(Verb)-rm -rf $(OBJECTS_C.BC)
|
||||
$(Verb)-rm -rf $(DependFiles)
|
||||
$(Verb)-rm -rf $(TARGET)
|
||||
$(Echo) "[$(MSGH)] Done!" $(AVE_DIR_DLOG)
|
||||
|
||||
explain:
|
||||
$(Echo) "The following information represents your program:"
|
||||
$(Echo) "Final executable name: $(TARGET)"
|
||||
$(Echo) "Source files: $(HLS_SOURCES)"
|
||||
$(Echo) "Object files: $(OBJECTS)"
|
||||
$(Echo) "Dep files: $(DEPS)"
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
# ==============================================================
|
||||
# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
# ==============================================================
|
||||
CSIM_DESIGN = 1
|
||||
|
||||
__SIM_FPO__ = 1
|
||||
|
||||
__SIM_MATHHLS__ = 1
|
||||
|
||||
__SIM_OPENCV__ = 1
|
||||
|
||||
__SIM_FFT__ = 1
|
||||
|
||||
__SIM_FIR__ = 1
|
||||
|
||||
__SIM_DDS__ = 1
|
||||
|
||||
ObjDir = obj
|
||||
|
||||
HLS_SOURCES = ../../../../circle_detect_test.cpp ../../../../circle_detect.cpp
|
||||
|
||||
TARGET := csim.exe
|
||||
|
||||
AUTOPILOT_ROOT := C:/Xilinx/Vivado/2019.1
|
||||
AUTOPILOT_MACH := win64
|
||||
ifdef AP_GCC_M32
|
||||
AUTOPILOT_MACH := Linux_x86
|
||||
IFLAG += -m32
|
||||
endif
|
||||
ifndef AP_GCC_PATH
|
||||
AP_GCC_PATH := C:/Xilinx/Vivado/2019.1/msys64/mingw64/bin
|
||||
endif
|
||||
AUTOPILOT_TOOL := ${AUTOPILOT_ROOT}/${AUTOPILOT_MACH}/tools
|
||||
AP_CLANG_PATH := ${AUTOPILOT_ROOT}/msys64/mingw64/bin
|
||||
AUTOPILOT_TECH := ${AUTOPILOT_ROOT}/common/technology
|
||||
|
||||
|
||||
IFLAG += -I "${AUTOPILOT_TOOL}/systemc/include"
|
||||
IFLAG += -I "${AUTOPILOT_ROOT}/include"
|
||||
IFLAG += -I "${AUTOPILOT_ROOT}/include/opencv"
|
||||
IFLAG += -I "${AUTOPILOT_ROOT}/include/ap_sysc"
|
||||
IFLAG += -I "${AUTOPILOT_TECH}/generic/SystemC"
|
||||
IFLAG += -I "${AUTOPILOT_TECH}/generic/SystemC/AESL_FP_comp"
|
||||
IFLAG += -I "${AUTOPILOT_TECH}/generic/SystemC/AESL_comp"
|
||||
IFLAG += -I "${AUTOPILOT_TOOL}/auto_cc/include"
|
||||
IFLAG += -D__SIM_FPO__
|
||||
|
||||
IFLAG += -D__SIM_OPENCV__
|
||||
|
||||
IFLAG += -D__SIM_FFT__
|
||||
|
||||
IFLAG += -D__SIM_FIR__
|
||||
|
||||
IFLAG += -D__SIM_DDS__
|
||||
|
||||
IFLAG += -D__DSP48E1__
|
||||
IFLAG += -g
|
||||
IFLAG += -DNT
|
||||
LFLAG += -Wl,--enable-auto-import
|
||||
DFLAG += -D__xilinx_ip_top= -DAESL_TB
|
||||
CCFLAG +=
|
||||
TOOLCHAIN +=
|
||||
|
||||
|
||||
|
||||
include ./Makefile.rules
|
||||
|
||||
all: $(TARGET)
|
||||
|
||||
|
||||
|
||||
$(ObjDir)/circle_detect_test.o: ../../../../circle_detect_test.cpp $(ObjDir)/.dir
|
||||
$(Echo) " Compiling ../../../../circle_detect_test.cpp in $(BuildMode) mode" $(AVE_DIR_DLOG)
|
||||
$(Verb) $(CC) ${CCFLAG} -c -MMD $(IFLAG) $(DFLAG) $< -o $@ ; \
|
||||
|
||||
-include $(ObjDir)/circle_detect_test.d
|
||||
|
||||
$(ObjDir)/circle_detect.o: ../../../../circle_detect.cpp $(ObjDir)/.dir
|
||||
$(Echo) " Compiling ../../../../circle_detect.cpp in $(BuildMode) mode" $(AVE_DIR_DLOG)
|
||||
$(Verb) $(CC) ${CCFLAG} -c -MMD $(IFLAG) $(DFLAG) $< -o $@ ; \
|
||||
|
||||
-include $(ObjDir)/circle_detect.d
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
obj/circle_detect_test.o: ../../../../circle_detect_test.cpp \
|
||||
../../../../circle_detect.h C:/Xilinx/Vivado/2019.1/include/hls_video.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_axi_sdata.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_int.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_common.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_decl.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/etc/ap_private.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_half.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_fpo.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/floating_point_v7_0_bitacc_cmodel.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/gmp.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/mpfr.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/gmp.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/mpfr.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_decl.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_int_base.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_int_ref.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_int_special.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_fixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_fixed_base.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_int.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_fixed_ref.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_fixed_special.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_utils.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_math.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_half.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_hotbm_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/ap_fixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_defines.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_utils.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_cordic_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_exp_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_log_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_sqrt_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_round_copysign_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_pow_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_diff_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_comparison_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_frexp_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_modf_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_isequal_isnotequal_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_all_any_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_select_bitselect_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_erf_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_fmod_rem_quo_remainder_divide_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_lgamma_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_traits.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_utils.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/utils/x_hls_defines.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_tgamma_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_fract_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_mad_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_cbrt_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_hypot_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_ldexp_apfixed.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_stream.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_types.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_mem.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_core.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_imgbase.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_io.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_axi_io.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_arithm.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_imgproc.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_histogram.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_fast.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_undistort.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_hough.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_harris.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_haar.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls/hls_video_stereobm.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_opencv.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/opencv.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/core_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/types_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/core.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/version.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/operations.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/core/mat.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/flann/miniflann.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/flann/defines.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/flann/config.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/imgproc/imgproc_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/imgproc/types_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/imgproc/imgproc.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/photo/photo.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/photo/photo_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/video/video.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/video/tracking.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/video/background_segm.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/features2d/features2d.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/objdetect/objdetect.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/calib3d/calib3d.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/ml/ml.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/highgui/highgui_c.h \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/highgui/highgui.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/contrib/contrib.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/contrib/retina.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/opencv2/contrib/openfabmap.hpp \
|
||||
C:/Xilinx/Vivado/2019.1/include/hls_video.h
|
||||
Binary file not shown.
Binary file not shown.
|
After Width: | Height: | Size: 2.6 MiB |
|
|
@ -0,0 +1,45 @@
|
|||
# ==============================================================
|
||||
# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
# ==============================================================
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/tools/fpo_v7_0"
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/tools/opencv"
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/tools/fft_v9_1"
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/tools/fir_v7_0"
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/tools/dds_v6_0"
|
||||
set ::env(PATH) "$::env(PATH);C:/Xilinx/Vivado/2019.1/win64/csim"
|
||||
### C sim ###
|
||||
if {![file exists csim.exe]} {
|
||||
puts "@E C-simulation is not set up properly. Please re-run csim."
|
||||
return -code error
|
||||
}
|
||||
set ret [catch {eval exec ./csim.exe | tee temp0.log >&@ stdout} err]
|
||||
set logfile "temp0.log"
|
||||
if {$ret || $err != ""} {
|
||||
if { [lindex $::errorCode 0] eq "CHILDSTATUS"} {
|
||||
set status [lindex $::errorCode 2]
|
||||
if {$status != ""} {
|
||||
puts "@E Simulation failed: Function \'main\' returns nonzero value \'$status\'."
|
||||
set ::AESL_CSIM::gnonzeroRetErr 1
|
||||
return -code error
|
||||
} else {
|
||||
puts "@E Simulation failed."
|
||||
return -code error
|
||||
}
|
||||
} else {
|
||||
if { [regexp {segmentation violation} $err] } {
|
||||
puts "@E Simulation failed: SIGSEGV."
|
||||
} else {
|
||||
puts "@E Simulation failed."
|
||||
}
|
||||
return -code error
|
||||
}
|
||||
}
|
||||
if {[file exists $logfile]} {
|
||||
set cmdret [catch {eval exec "grep \"Error:\" $logfile"} err]
|
||||
if {$cmdret == 0} {
|
||||
puts "@E Simulation failed."
|
||||
return -code error
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
C:/Xilinx/Vivado/2019.1/bin/vivado_hls run_sim.tcl
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,5 @@
|
|||
############################################################
|
||||
## This file is generated automatically by Vivado HLS.
|
||||
## Please DO NOT edit it.
|
||||
## Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
############################################################
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
############################################################
|
||||
## This file is generated automatically by Vivado HLS.
|
||||
## Please DO NOT edit it.
|
||||
## Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
############################################################
|
||||
open_project circle_detect
|
||||
set_top circle_detect
|
||||
add_files circle_detect.cpp
|
||||
add_files circle_detect.h
|
||||
add_files -tb circle_detect_test.cpp
|
||||
add_files -tb rover.bmp
|
||||
open_solution "solution1"
|
||||
set_part {xc7z020clg400-1} -tool vivado
|
||||
create_clock -period 10 -name default
|
||||
#source "./circle_detect/solution1/directives.tcl"
|
||||
csim_design -clean
|
||||
csynth_design
|
||||
cosim_design
|
||||
export_design -format ip_catalog
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
<solution AutoPilot="com.autoesl.autopilot.solution">
|
||||
<checksum>
|
||||
<value string="false"/>
|
||||
</checksum>
|
||||
<downStreamTool>
|
||||
<DownStreamTool name="vivado"/>
|
||||
</downStreamTool>
|
||||
<clockList>
|
||||
<clock name="default" period="10"/>
|
||||
</clockList>
|
||||
<config/>
|
||||
<UIConfigurations>
|
||||
<UIAutosynConf boardInfo="Zybo Z7-20 (xc7z020clg400-1) " hideTrivialOp="true" isBasedOnBoard="true" isSolutionDirty="false" isStopAskAgain="false" showDetailDesignViewer="false">
|
||||
<Platform>xilinx/zynq/zynq</Platform>
|
||||
<customLibs/>
|
||||
</UIAutosynConf>
|
||||
<UIIPPackagerConf AskAgain="true" DescriptionButton="false" LibraryButton="false" RTLLanguage="verilog" UseNetList="none" VendorButton="false" VersionButton="false" evaluateRTL="false" setup="false">
|
||||
<RTLs>
|
||||
<Verilog method="IPXACT" selection="true"/>
|
||||
<Vhdl method="IPXACT" selection="false"/>
|
||||
</RTLs>
|
||||
</UIIPPackagerConf>
|
||||
<UIAutoMGConf AskAgain="true" Export="false" Xil_CoreGen="false" defaultCustomPorts="false">
|
||||
<UIAutoMGImpl add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false" register_retiming="off" setup="0" synplify_io_insertion="true" synplify_op_effort="high" synplify_pipelining="false" synplify_resource_sharing="true" synplify_retiming="false" synplify_verilogPar="false" synplify_vhdlPar="false" synthesis_combo_logic="off" synthesis_effort="normal" virtual_pins="off" xilinxInterconnectType="plb">
|
||||
<RTLs>
|
||||
<Verilog selection="true" tool="ISE"/>
|
||||
<Vhdl selection="false" tool="ISE"/>
|
||||
</RTLs>
|
||||
<verilogSynplifySettings synplify_invocation_command="synplify_pro -licensetype synplifypro_xilinx" synplify_io_insertion="false" synplify_op_effort="high" synplify_par="true" synplify_pipelining="true" synplify_resource_sharing="true" synplify_retiming="false"/>
|
||||
<vhdlSynplifySettings synplify_invocation_command="synplify_pro -licensetype synplifypro_xilinx" synplify_io_insertion="false" synplify_op_effort="high" synplify_par="true" synplify_pipelining="true" synplify_resource_sharing="true" synplify_retiming="false"/>
|
||||
<verilogISESettings add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false"/>
|
||||
<vhdlISESettings add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false"/>
|
||||
</UIAutoMGImpl>
|
||||
</UIAutoMGConf>
|
||||
<UIAutoSimConf ApIntSupport="false" AskAgain="true">
|
||||
<RTLs>
|
||||
<SystemC selection="true" tool="Auto"/>
|
||||
<Verilog selection="false" tool="Auto"/>
|
||||
<VHDL selection="false" tool="Auto"/>
|
||||
</RTLs>
|
||||
</UIAutoSimConf>
|
||||
</UIConfigurations>
|
||||
<ExportDesign askAgain="true" evaluate="false" flow="false" flowChoice="syn" formatName="ip_catalog" rtl="verilog" rtlButton="false" rtlCombo="verilog">
|
||||
<Format formatName="ip_catalog"/>
|
||||
<Format formatName="sysgen"/>
|
||||
<Format formatName="sysgen_ise"/>
|
||||
<Format formatName="syn_dcp"/>
|
||||
<Format formatName="pcore" use_netlist="none"/>
|
||||
</ExportDesign>
|
||||
<Simulation>
|
||||
<SimFlow askAgain="true" clangSanitizer="false" compile="false" compileChoice="gcc" disableDeadlockDetect="false" dumpTrace="none" name="cosim" optimizeCompile="false" reduce_diskspace="false" setup="false" toolName="Auto" waveDebug="false">
|
||||
<Rtl active="false" name="systemc"/>
|
||||
<Rtl active="true" name="verilog"/>
|
||||
<Rtl active="false" name="vhdl"/>
|
||||
</SimFlow>
|
||||
</Simulation>
|
||||
<name>
|
||||
<value string="solution1"/>
|
||||
</name>
|
||||
<project>
|
||||
<value string="circle_detect"/>
|
||||
</project>
|
||||
<targetInfo>
|
||||
<TargetInfo value="xc7z020:-clg400:-1"/>
|
||||
</targetInfo>
|
||||
<libraryList>
|
||||
<library name="DefaultPlatform" value="xilinx/zynq/zynq"/>
|
||||
<library value="xilinx/zynq/zynq_fpv6" name="DefaultPlatform"/>
|
||||
</libraryList>
|
||||
</solution>
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<AutoPilot:ProjectResources xmlns:AutoPilot="com.autoesl.autopilot.ui.directiveView">
|
||||
</AutoPilot:ProjectResources>
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
==============================================================
|
||||
Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
==============================================================
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
==============================================================
|
||||
Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
==============================================================
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
==============================================================
|
||||
Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
==============================================================
|
||||
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
||||
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
|
||||
INFO: [SIM 211-2] *************** CSIM start ***************
|
||||
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
|
||||
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
|
||||
INFO: [SIM 211-3] *************** CSIM finish ***************
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
<project xmlns="com.autoesl.autopilot.project" top="circle_detect" name="circle_detect">
|
||||
<files>
|
||||
<file name="../../circle_detect_test.cpp" sc="0" tb="1" cflags=""/>
|
||||
<file name="../../rover.bmp" sc="0" tb="1" cflags=""/>
|
||||
<file name="circle_detect.cpp" sc="0" tb="false" cflags="" blackbox="false"/>
|
||||
<file name="circle_detect.h" sc="0" tb="false" cflags="" blackbox="false"/>
|
||||
</files>
|
||||
<includePaths/>
|
||||
<libraryPaths/>
|
||||
<Simulation>
|
||||
<SimFlow name="csim" clean="true" csimMode="0" lastCsimMode="0"/>
|
||||
</Simulation>
|
||||
<solutions xmlns="">
|
||||
<solution name="solution1" status="active"/>
|
||||
</solutions>
|
||||
</project>
|
||||
|
||||
21
A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Normal file
21
A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
#include "circle_detect.h"
|
||||
#include "hls_opencv.h"
|
||||
|
||||
int main()
|
||||
{
|
||||
int const rows = MAX_HEIGHT;
|
||||
int const cols = MAX_WIDTH;
|
||||
|
||||
cv::Mat src = cv::imread(INPUT_IMAGE);
|
||||
cv::Mat dst = src;
|
||||
|
||||
stream_t stream_in, stream_out;
|
||||
|
||||
cvMat2AXIvideo(src, stream_in);
|
||||
edge_detect(stream_in, stream_out);
|
||||
AXIvideo2cvMat(stream_out, dst);
|
||||
|
||||
cv::imwrite(OUTPUT_IMAGE, dst);
|
||||
|
||||
return 0;
|
||||
}
|
||||
BIN
A2/Detection_cercle/circle_detect/rover.bmp
Normal file
BIN
A2/Detection_cercle/circle_detect/rover.bmp
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 2.6 MiB |
13003
A2/Detection_cercle/circle_detect/vivado_hls.log
Normal file
13003
A2/Detection_cercle/circle_detect/vivado_hls.log
Normal file
File diff suppressed because it is too large
Load diff
BIN
A2/Detection_cercle/edge.jpg
Normal file
BIN
A2/Detection_cercle/edge.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 327 KiB |
82
A2/Detection_cercle/edge_detect/edge_detect.cpp
Normal file
82
A2/Detection_cercle/edge_detect/edge_detect.cpp
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
#include "edge_detect.h"
|
||||
|
||||
|
||||
void mysobel(rgb_img_t &src, rgb_img_t &dst, int dir)
|
||||
{
|
||||
int const rows = MAX_HEIGHT;
|
||||
int const cols = MAX_WIDTH;
|
||||
|
||||
rgb_img_t img0(rows, cols);
|
||||
|
||||
if (dir)
|
||||
{
|
||||
hls::Sobel<1,0,3>(src, img0);
|
||||
}
|
||||
else
|
||||
{
|
||||
hls::Sobel<0,1,3>(src, img0);
|
||||
}
|
||||
|
||||
hls::ConvertScaleAbs(img0, dst);
|
||||
|
||||
}
|
||||
|
||||
void mysobelxy(rgb_img_t &src, rgb_img_t &dst)
|
||||
{
|
||||
int const rows = MAX_HEIGHT;
|
||||
int const cols = MAX_WIDTH;
|
||||
|
||||
rgb_img_t img0(rows, cols);
|
||||
rgb_img_t img1(rows, cols);
|
||||
rgb_img_t img2(rows, cols);
|
||||
rgb_img_t img3(rows, cols);
|
||||
|
||||
hls::Duplicate(src, img0, img1);
|
||||
mysobel(img0, img2, 1);
|
||||
mysobel(img1, img3, 0);
|
||||
hls::AddWeighted(img2, 1, img3, 1, 0, dst);
|
||||
}
|
||||
|
||||
void sobelfoo(stream_t &stream_in, stream_t &stream_out)
|
||||
{
|
||||
int const rows = MAX_HEIGHT;
|
||||
int const cols = MAX_WIDTH;
|
||||
|
||||
rgb_img_t img0(rows, cols);
|
||||
rgb_img_t img1(rows, cols);
|
||||
rgb_img_t img2(rows, cols);
|
||||
rgb_img_t img4(rows, cols);
|
||||
|
||||
hls::AXIvideo2Mat(stream_in, img0);
|
||||
|
||||
hls::CvtColor<HLS_RGB2GRAY>(img0, img1);
|
||||
mysobelxy(img1,img2);
|
||||
hls::CvtColor<HLS_GRAY2RGB>(img2, img4);
|
||||
|
||||
hls::Mat2AXIvideo(img4, stream_out);
|
||||
}
|
||||
//
|
||||
//void blurfoo(stream_t &stream_in, stream_t &stream_out)
|
||||
//{
|
||||
// int const rows = MAX_HEIGHT;
|
||||
// int const cols = MAX_WIDTH;
|
||||
//
|
||||
// rgb_img_t img0(rows, cols);
|
||||
// rgb_img_t img1(rows, cols);
|
||||
//
|
||||
// hls::AXIvideo2Mat(stream_in, img0);
|
||||
//
|
||||
// hls::GaussianBlur<5,5>(img0, img1, (double)5, (double)5);
|
||||
//
|
||||
// hls::Mat2AXIvideo(img1, stream_out);
|
||||
//
|
||||
//}
|
||||
|
||||
void edge_detect(stream_t &stream_in, stream_t &stream_out)
|
||||
{
|
||||
|
||||
int const rows = MAX_HEIGHT;
|
||||
int const cols = MAX_WIDTH;
|
||||
|
||||
sobelfoo(stream_in, stream_out);
|
||||
}
|
||||
16
A2/Detection_cercle/edge_detect/edge_detect.h
Normal file
16
A2/Detection_cercle/edge_detect/edge_detect.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#include "hls_video.h"
|
||||
|
||||
typedef ap_axiu<24,1,1,1> interface_t;
|
||||
typedef ap_uint<3> interface_3_bits;
|
||||
typedef hls::stream<interface_t> stream_t;
|
||||
|
||||
void edge_detect(stream_t &stream_in, stream_t &stream_out);
|
||||
|
||||
#define MAX_WIDTH 1920
|
||||
#define MAX_HEIGHT 1080
|
||||
|
||||
typedef hls::Mat<MAX_HEIGHT, MAX_WIDTH, HLS_8UC3> rgb_img_t;
|
||||
typedef hls::Scalar<3, unsigned char> rgb_pix_t;
|
||||
|
||||
#define INPUT_IMAGE "rover.bmp"
|
||||
#define OUTPUT_IMAGE "rover_out.bmp"
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<autopilotfilemapping:AutoPilotFileMapping xmlns:autopilotfilemapping="www.autoesl.com/autopilotfilemapping">
|
||||
<source>
|
||||
<originFiles name="edge_detect.h" path="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\edge_detect.h"/>
|
||||
<originFiles name="edge_detect.cpp" path="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\edge_detect.cpp"/>
|
||||
</source>
|
||||
<testbench>
|
||||
<originFiles name="rover.bmp" path="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\rover.bmp"/>
|
||||
<originFiles name="edge_detect_test.cpp" path="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\edge_detect_test.cpp"/>
|
||||
</testbench>
|
||||
</autopilotfilemapping:AutoPilotFileMapping>
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<autopilotfilemapping:AutoPilotFileMapping xmlns:autopilotfilemapping="www.autoesl.com/autopilotfilemapping">
|
||||
<source>
|
||||
<originFiles name="edge_detect.h" path="F:\Downloads\Zybo-Z7-20-pcam-5c_EW_Demo\Zybo-Z7-20-pcam-5c.git\repo\local\ip\hls\edge_detect\edge_detect.h"/>
|
||||
<originFiles name="edge_detect.cpp" path="F:\Downloads\Zybo-Z7-20-pcam-5c_EW_Demo\Zybo-Z7-20-pcam-5c.git\repo\local\ip\hls\edge_detect\edge_detect.cpp"/>
|
||||
</source>
|
||||
<testbench>
|
||||
<originFiles name="rover.bmp" path="F:\Downloads\Zybo-Z7-20-pcam-5c_EW_Demo\Zybo-Z7-20-pcam-5c.git\repo\local\ip\hls\edge_detect\rover.bmp"/>
|
||||
<originFiles name="edge_detect_test.cpp" path="F:\Downloads\Zybo-Z7-20-pcam-5c_EW_Demo\Zybo-Z7-20-pcam-5c.git\repo\local\ip\hls\edge_detect\edge_detect_test.cpp"/>
|
||||
</testbench>
|
||||
</autopilotfilemapping:AutoPilotFileMapping>
|
||||
434
A2/Detection_cercle/edge_detect/edge_detect/.cproject
Normal file
434
A2/Detection_cercle/edge_detect/edge_detect/.cproject
Normal file
|
|
@ -0,0 +1,434 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="cdt.managedbuild.config.gnu.exe.debug.984768198">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.debug.984768198" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.PE" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactName="a.exe" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.984768198" name="Debug" parent="cdt.managedbuild.config.gnu.exe.debug">
|
||||
|
||||
<folderInfo id="cdt.managedbuild.config.gnu.exe.debug.984768198." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="cdt.managedbuild.toolchain.gnu.exe.debug.298761314" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.debug">
|
||||
|
||||
<targetPlatform binaryParser="org.eclipse.cdt.core.PE;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.exe.debug.1300882201" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.debug"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/edge_detect}/Debug" id="cdt.managedbuild.target.gnu.builder.exe.debug.601268999" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.exe.debug"/>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1475200864" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1046748002" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
|
||||
|
||||
<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.374919737" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.cpp.compiler.exe.debug.option.debugging.level.287629481" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.cpp.compiler.option.include.paths.1653907125" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include/ap_sysc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="F:/Downloads/Zybo-Z7-20-pcam-5c_EW_Demo/Zybo-Z7-20-pcam-5c.git/repo/local/ip/hls/edge_detect"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/systemc/include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include/etc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/auto_cc/include"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="gnu.cpp.compiler.option.preprocessor.def.1087447165" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<listOptionValue builtIn="false" value="AESL_TB"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__llvm__"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__llvm__"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1872744032" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.compiler.exe.debug.699946671" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.exe.debug">
|
||||
|
||||
<option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.1563018510" name="Optimization Level" superClass="gnu.c.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.c.compiler.exe.debug.option.debugging.level.787074392" name="Debug Level" superClass="gnu.c.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.c.compiler.option.include.paths.567357028" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include/ap_sysc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="F:/Downloads/Zybo-Z7-20-pcam-5c_EW_Demo/Zybo-Z7-20-pcam-5c.git/repo/local/ip/hls/edge_detect"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/systemc/include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/include/etc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/auto_cc/include"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols.446713574" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<listOptionValue builtIn="false" value="AESL_TB"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__llvm__"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__llvm__"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.212296617" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.linker.exe.debug.1950750358" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.exe.debug">
|
||||
|
||||
<option id="gnu.c.link.option.paths.1102804337" name="Library search path (-L)" superClass="gnu.c.link.option.paths" valueType="libPaths">
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||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/systemc/lib"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="gnu.c.link.option.libs.698731509" name="Libraries (-l)" superClass="gnu.c.link.option.libs"/>
|
||||
|
||||
<option id="gnu.c.link.option.ldflags.26224328" name="Linker flags" superClass="gnu.c.link.option.ldflags"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.exe.debug.278627785" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.exe.debug">
|
||||
|
||||
<option id="gnu.cpp.link.option.paths.1404546218" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
|
||||
|
||||
<listOptionValue builtIn="false" value="C:/Xilinx/Vivado/2019.1/win64/tools/systemc/lib"/>
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|
||||
</option>
|
||||
|
||||
<option id="gnu.cpp.link.option.libs.1591965790" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs"/>
|
||||
|
||||
<option id="gnu.cpp.link.option.flags.1553058033" name="Linker flags" superClass="gnu.cpp.link.option.flags"/>
|
||||
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.96472341" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
|
||||
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
|
||||
</inputType>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.assembler.exe.debug.801139186" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.exe.debug">
|
||||
|
||||
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.2018751607" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<fileInfo id="cdt.managedbuild.config.gnu.exe.debug.984768198.364891610" name="rover.bmp" rcbsApplicability="disable" resourcePath="testbench/rover.bmp" toolsToInvoke=""/>
|
||||
|
||||
<fileInfo id="cdt.managedbuild.config.gnu.exe.debug.984768198.680978789" name="edge_detect_test.cpp" rcbsApplicability="disable" resourcePath="testbench/edge_detect_test.cpp" toolsToInvoke="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1046748002.1957075999">
|
||||
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1046748002.1957075999" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1046748002">
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||||
|
||||
<option id="gnu.cpp.compiler.option.preprocessor.def.1555496647" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def"/>
|
||||
|
||||
<option id="gnu.cpp.compiler.option.include.paths.1696915107" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
|
||||
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80
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|
||||
<location>C:/Users/Sasa/workspace/Zybo_Z7_Embedded_Vision_Demo_2019_1/repo/local/ip/hls/edge_detect/edge_detect/solution1/script.tcl</location>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/a.exe"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="edge_detect"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="cdt.managedbuild.config.gnu.exe.debug.984768198"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.WORKING_DIRECTORY" value="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\edge_detect"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;directory nest=&quot;true&quot; path=&quot;C:\Xilinx\Vivado\2019.1\win64\tools\systemc&quot;/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.directory"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Release/a.exe"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="edge_detect"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="cdt.managedbuild.config.gnu.exe.release.375266596"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.WORKING_DIRECTORY" value="C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect\edge_detect"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.use_terminal" value="true"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;directory nest=&quot;true&quot; path=&quot;C:\Xilinx\Vivado\2019.1\win64\tools\systemc&quot;/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.directory"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
</launchConfiguration>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
|
||||
<configuration id="cdt.managedbuild.config.gnu.exe.debug.984768198" name="Debug">
|
||||
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1543514302395853231" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
|
||||
</provider>
|
||||
|
||||
</extension>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration id="cdt.managedbuild.config.gnu.exe.release.375266596" name="Release">
|
||||
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1543514302395853231" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
|
||||
</provider>
|
||||
|
||||
</extension>
|
||||
|
||||
</configuration>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<vivadoHLSLog:LogRoot xmlns:vivadoHLSLog="www.xilinx.com/vivadoHLSLog">
|
||||
<errorLogs>
|
||||
<logs>
|
||||
<synLog/>
|
||||
<simLog/>
|
||||
<mgLog/>
|
||||
<packageLog>
|
||||
<logs message="ERROR: [IMPL 213-28] Failed to generate IP.
command 'ap_source' returned error code
 while executing
"source C:/Users/Sasa/workspace/Zybo_Z7_Embedded_Vision_Demo_2019_1/repo/local/ip/hls/edge_detect/edge_detect/solution1/export.tcl"
 invoked from within
"hls::main C:/Users/Sasa/workspace/Zybo_Z7_Embedded_Vision_Demo_2019_1/repo/local/ip/hls/edge_detect/edge_detect/solution1/export.tcl"
 ("uplevel" body line 1)
 invoked from within
"uplevel 1 hls::main {*}$args"
 (procedure "hls_proc" line 5)
 invoked from within
"hls_proc $argv"
" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:19:21.460+0100"/>
|
||||
</packageLog>
|
||||
<csimLog/>
|
||||
</logs>
|
||||
</errorLogs>
|
||||
<warningLogs>
|
||||
<logs>
|
||||
<synLog>
|
||||
<logs message="WARNING: [RTGEN 206-101] RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x1' due to conflict." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:49.342+0100" type="Warning"/>
|
||||
<logs message="WARNING: [RTGEN 206-101] RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x0' due to conflict." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:47.626+0100" type="Warning"/>
|
||||
<logs message="WARNING: [RTGEN 206-101] RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x' due to conflict." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:46.400+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] The critical path in module 'ConvertScaleAbs157' consists of the following:
	'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:32.007+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] Estimated clock period (6.562ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:31.994+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] The critical path in module 'ConvertScaleAbs155' consists of the following:
	'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:29.933+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] Estimated clock period (6.562ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:29.921+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] The critical path in module 'CvtColor' consists of the following:
	'mul' operation of DSP[49] ('mul_ln703_1', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1497->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [43] (3.36 ns)
	'add' operation of DSP[49] ('ret.V', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1497->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [49] (3.02 ns)
	'add' operation ('__Val2__', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:409->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1498->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [53] (1.92 ns)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:26.554+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SCHED 204-21] Estimated clock period (8.295ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:26.543+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SYN 201-103] Legalizing function name 'CvtColor.1' to 'CvtColor_1'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.822+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SYN 201-103] Legalizing function name 'operator().1' to 'operator_1'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.785+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobel152_Block__pr' to 'mysobel152_Block__pr.1' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.741+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobel153_Block__pr' to 'mysobel153_Block__pr.1' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.345+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobelxy_Block__pro' to 'mysobelxy_Block__pro.1' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.332+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'sobelfoo_Block__proc' to 'sobelfoo_Block__proc.1' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.322+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[0].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:25.309+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[2].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.149+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[2].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.137+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[1].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.124+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[1].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.110+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[2].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.097+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[1].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.085+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[0].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.074+0100" type="Warning"/>
|
||||
<logs message="WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'k_buf[0].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.061+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'AXIvideo2Mat'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:24.047+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'AXIvideo2Mat'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.882+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'ConvertScaleAbs155'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.869+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'ConvertScaleAbs155'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.855+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'ConvertScaleAbs157'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.840+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'ConvertScaleAbs157'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.828+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'CvtColor'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.817+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'CvtColor'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.806+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'CvtColor.1'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.793+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'CvtColor.1'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.780+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'Duplicate'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.769+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'Duplicate'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.759+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 9 to 1082 for loop 'loop_height' in function 'Filter2D'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.744+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop upper bound from 1083 to 1082 for loop 'loop_height' in function 'Filter2D'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.727+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 10 to 1922 for loop 'loop_width' in function 'Filter2D'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.714+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'Mat2AXIvideo'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.701+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'Mat2AXIvideo'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.688+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'arithm_pro'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.676+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-561] Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'arithm_pro'." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.665+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' to 'AXIvideo2Mat' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:49:9)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.653+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::AddWeighted<1080, 1920, 4096, 4096, 4096, int>' to 'AddWeighted' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879:1)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.451+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>155' to 'ConvertScaleAbs155' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:475:34)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.438+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>157' to 'ConvertScaleAbs157' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:475:34)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.428+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' to 'CvtColor.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:672:39)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.417+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' to 'CvtColor' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:409:39)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.406+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::Duplicate<1080, 1920, 4096, 4096>' to 'Duplicate' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:672:50)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.395+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' to 'Filter2D' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:118:33)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.384+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' to 'Mat2AXIvideo' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:78:50)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.374+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::Sobel<0, 1, 3, 4096, 4096, 1080, 1920, 1080, 1920>156' to 'Sobel156' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2619:1)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.363+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::Sobel<1, 0, 3, 4096, 4096, 1080, 1920, 1080, 1920>154' to 'Sobel154' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2619:1)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.352+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' to 'arithm_pro' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:280:50)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.341+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'hls::sr_cast_class<ap_uint<8> >::operator().1' to 'operator().1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:18:5)" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.330+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobel152_Block__proc' to 'mysobel152_Block__pr' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.318+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobel153_Block__proc' to 'mysobel153_Block__pr' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.306+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-631] Renaming function 'mysobelxy_Block__proc228' to 'mysobelxy_Block__pro' " projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:23.295+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img0.data_stream.V' (edge_detect.cpp:45)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.633+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img3.data_stream.V' (edge_detect.cpp:32)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.291+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img2.data_stream.V' (edge_detect.cpp:31)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.281+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img4.data_stream.V' (edge_detect.cpp:48)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.270+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img1.data_stream.V' (edge_detect.cpp:46)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.258+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img1.data_stream.V' (edge_detect.cpp:30)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.249+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img0.data_stream.V' (edge_detect.cpp:29)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.238+0100" type="Warning"/>
|
||||
<logs message="WARNING: [XFORM 203-1103] Ignored data pack directive on non-struct variable 'img2.data_stream.V' (edge_detect.cpp:47)." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:17.228+0100" type="Warning"/>
|
||||
<logs message="WARNING: [SYNCHK 200-23] C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:429: variable-indexed range selection may cause suboptimal QoR." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:16.672+0100" type="Warning"/>
|
||||
<logs message="WARNING: [HLS 200-471] Dataflow form checks found 1 issue(s) in file edge_detect.cpp" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:12.757+0100" type="Warning"/>
|
||||
<logs message="WARNING: [HLS 214-114] Only function calls and local variable declarations are allowed in a dataflow region: edge_detect.cpp:11:2" projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:18:02.843+0100" type="Warning"/>
|
||||
</synLog>
|
||||
<simLog/>
|
||||
<mgLog/>
|
||||
<packageLog>
|
||||
<logs message="WARNING: [IP_Flow 19-4832] The IP name 'edge_detect_ap_sitodp_6_no_dsp_32' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues." projectName="edge_detect" solutionName="solution1" date="2021-02-07T10:20:06.140+0100" type="Warning"/>
|
||||
<logs message="WARNING: [IP_Flow 19-4832] The IP name 'edge_detect_ap_sitodp_6_no_dsp_32' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues." projectName="edge_detect" solutionName="solution1" date="2023-02-07T10:19:21.051+0100" type="Warning"/>
|
||||
</packageLog>
|
||||
<csimLog/>
|
||||
</logs>
|
||||
</warningLogs>
|
||||
</vivadoHLSLog:LogRoot>
|
||||
|
|
@ -0,0 +1 @@
|
|||
Sun Feb 07 10:19:54 +0100 2021
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
10:20:08
|
||||
02/07/2021
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Messages>
|
||||
<Message severity="INFO" prefix="[IMPL 213-8]" key="IMPL_8_1776" tag="" content="Exporting RTL as a Vivado IP."/>
|
||||
</Messages>
|
||||
|
|
@ -0,0 +1,753 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<Messages>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_631" tag="SCHEDULE" content="Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1312" tag="" content="Analyzing design file 'edge_detect.cpp' ..."/>
|
||||
<Message severity="WARNING" prefix="[HLS 214-114]" key="HLS 214-114" tag="DATAFLOW,SDX_KERNEL" content="Only function calls and local variable declarations are allowed in a dataflow region: edge_detect.cpp:11:2"/>
|
||||
<Message severity="WARNING" prefix="[HLS 200-471]" key="HLS 200-471" tag="DATAFLOW,SDX_KERNEL" content="Dataflow form checks found 1 issue(s) in file edge_detect.cpp"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Linking Time (s): cpu = 00:00:01 ; elapsed = 00:00:24 . Memory (MB): peak = 184.090 ; gain = 92.645"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Checking Pragmas Time (s): cpu = 00:00:01 ; elapsed = 00:00:24 . Memory (MB): peak = 184.090 ; gain = 92.645"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1467" tag="" content="Starting code transformations ..."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::init' into 'hls::Mat<1080, 1920, 4096>::Mat.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:642)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::AXIGetBitFields<24, unsigned char>.1' into 'hls::AXIGetBitFields<24, unsigned char>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:71)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::AXIGetBitFields<24, unsigned char>' into 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:92)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::write' into 'hls::Mat<1080, 1920, 4096>::operator<<' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:363)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1973)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1973)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::Duplicate<1080, 1920, 4096, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:1563)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::Duplicate<1080, 1920, 4096, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:1562)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator<<' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::read' into 'hls::Mat<1080, 1920, 4096>::operator>>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:359)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:358)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:140)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1971)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1971)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::Duplicate<1080, 1920, 4096, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:1561)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Mat<1080, 1920, 4096>::operator>>' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::ColorConverter<unsigned char, unsigned char>::convert<3>' into 'hls::kernel_CvtColor<HLS_RGB2GRAY, unsigned char, unsigned char>::apply<3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<1, 3, ap_int<8> >::getval' into 'hls::Window<1, 3, ap_int<8> >::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:501)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<1, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<0, 1, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2591)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<1, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<0, 1, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<1, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<1, 0, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2591)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<1, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<1, 0, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, ap_int<8> >::getval' into 'hls::Window<3, 1, ap_int<8> >::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:501)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, ap_int<8> >::operator()' into 'hls::Sobel_kernel<0, 1, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2593)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, ap_int<8> >::operator()' into 'hls::Sobel_kernel<0, 1, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, ap_int<8> >::operator()' into 'hls::Sobel_kernel<1, 0, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2593)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, ap_int<8> >::operator()' into 'hls::Sobel_kernel<1, 0, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, ap_int<8> >::getval' into 'hls::Window<3, 3, ap_int<8> >::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:501)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<1, 0, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, ap_int<8> >::operator()' into 'hls::Sobel_kernel<0, 1, 3, ap_int<8> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2599)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::normalizeAnchor<int, int>' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:424)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::get_parameters<3, 3, int>' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:434)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::borderInterpolate' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:452)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::borderInterpolate' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:470)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::borderInterpolate' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:506)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::getval' into 'hls::Window<3, 3, unsigned char>::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:501)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:507)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:503)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:484)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:481)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:481)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:458)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::getval' into 'hls::Window<3, 1, unsigned char>::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:501)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:458)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:460)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:484)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:503)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 1, unsigned char>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:507)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::getval' into 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:843)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:493)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:489)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:489)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:472)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::LineBuffer<6, 1920, unsigned char, 0>::operator()' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:460)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::shift_pixels_right' into 'hls::Window<3, 3, unsigned char>::shift_right' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:543)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::Window<3, 3, unsigned char>::shift_right' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:499)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::filter2d_kernel::apply<unsigned char, ap_fixed<20, 20, (ap_q_mode)5, (ap_o_mode)3, 0>, ap_int<8>, 3, 3>' into 'hls::filter2d_kernel::apply<unsigned char, unsigned char, ap_int<8>, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:303)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::filter2d_kernel::apply<unsigned char, unsigned char, ap_int<8>, 3, 3>' into 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:514)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::filter_opr<hls::filter2d_kernel, hls::BORDER_DEFAULT>::filter<4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' into 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1289)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::kernel_addWeighted::apply<unsigned char, unsigned char, unsigned char, int>' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:361)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::kernel_CvtColor<HLS_GRAY2RGB, unsigned char, unsigned char>::apply<3, 3>' into 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::AXISetBitFields<24, unsigned char>.1' into 'hls::AXISetBitFields<24, unsigned char>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:100)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-603]" key="XFORM_INLINE_STATUS_221" tag="" content="Inlining function 'hls::AXISetBitFields<24, unsigned char>' into 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:143)."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Standard Transforms Time (s): cpu = 00:00:02 ; elapsed = 00:00:26 . Memory (MB): peak = 234.320 ; gain = 142.875"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1472" tag="" content="Checking synthesizability ..."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<35, 13, (ap_q_mode)5, (ap_o_mode)3>' into 'hls::sr_cast<unsigned char, ap_fixed<35, 13, (ap_q_mode)5, (ap_o_mode)3, 0> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_fixed<35, 13, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'hls::kernel_CvtColor<HLS_RGB2GRAY, unsigned char, unsigned char>::apply<3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1498->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<20, 20, (ap_q_mode)5, (ap_o_mode)3>' into 'hls::sr_cast<unsigned char, ap_fixed<20, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_fixed<20, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:304->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:514->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1289) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::Sobel<1, 0, 3, hls::BORDER_DEFAULT, 4096, 4096, 1080, 1920, 1080, 1920>' into 'hls::Sobel<1, 0, 3, 4096, 4096, 1080, 1920, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2627) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::Sobel<0, 1, 3, hls::BORDER_DEFAULT, 4096, 4096, 1080, 1920, 1080, 1920>' into 'hls::Sobel<0, 1, 3, 4096, 4096, 1080, 1920, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2627) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::data' into 'fp_struct<double>::to_double' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::to_double' into 'fp_struct<double>::to_ieee' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::to_ieee' into 'generic_copysign<double>' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_copysign<double>' into 'generic_fabs<double>' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_fabs<double>' into 'hls::abs' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_isnan<double>' into 'hls::isnan' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/isnandouble.cpp:7) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::isnan' into 'hls::__isnan' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/isnandouble.cpp:11) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::__isnan' into 'hls::sr_cast_class<ap_uint<8> >::operator().1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:428) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::abs' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, double>' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<41>' into 'hls::sr_cast<unsigned char, ap_int<41> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_int<41> >' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:282->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:361) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<8>' into 'hls::sr_cast_class<ap_uint<8> >::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:432) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()' into 'hls::sr_cast<unsigned char, unsigned char>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, unsigned char>' into 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1554->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) automatically."/>
|
||||
<Message severity="WARNING" prefix="[SYNCHK 200-23]" key="SYNCHK_VAR_INDEX_RANGE_359" tag="" content="C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:429: variable-indexed range selection may cause suboptimal QoR."/>
|
||||
<Message severity="INFO" prefix="[SYNCHK 200-10]" key="SYNCHK_SYNCHK_SUMMARY_377" tag="" content="0 error(s), 1 warning(s)."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Checking Synthesizability Time (s): cpu = 00:00:04 ; elapsed = 00:00:28 . Memory (MB): peak = 302.914 ; gain = 211.469"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img2.data_stream.V' (edge_detect.cpp:47)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img0.data_stream.V' (edge_detect.cpp:29)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img1.data_stream.V' (edge_detect.cpp:30)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img1.data_stream.V' (edge_detect.cpp:46)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img4.data_stream.V' (edge_detect.cpp:48)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img2.data_stream.V' (edge_detect.cpp:31)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img3.data_stream.V' (edge_detect.cpp:32)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-1103]" key="XFORM_DATA_PACK_INVALID_346" tag="" content="Ignored data pack directive on non-struct variable 'img0.data_stream.V' (edge_detect.cpp:45)."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:355) in function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:126) in function 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:444) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:1558) in function 'hls::Duplicate<1080, 1920, 4096, 4096>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1968) in function 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1968) in function 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527) in function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-502]" key="XFORM_AUTO_UNROLL_STATUS_246" tag="" content="Unrolling all sub-loops inside loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73) in function 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' for pipelining."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_channels' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:360) in function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.4' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_channels' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:142) in function 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'channelloop' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:450) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:456) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:469) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 6."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.3' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:478) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.3.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:479) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 2."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.4' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:487) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 5."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.5' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:161) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.5.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:163) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 2."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-5.1.1.6' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:501) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_height' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:285) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_width' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:286) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::Duplicate<1080, 1920, 4096, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::Duplicate<1080, 1920, 4096, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.3' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::Duplicate<1080, 1920, 4096, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:677) in function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_channels' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2532) in function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-1.1.3' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'loop_channels' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:91) in function 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-489]" key="HLS 200-489" tag="" content="Unrolling loop 'Loop-2.1.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:701) in function 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' completely with a factor of 3."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign.5' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign.3' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign.4' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign.6' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign.2' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_120" tag="" content="Partitioning array 's.val.assign' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:589) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img0.data_stream.V' (edge_detect.cpp:45) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img1.data_stream.V' (edge_detect.cpp:46) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img2.data_stream.V' (edge_detect.cpp:47) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img4.data_stream.V' (edge_detect.cpp:48) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img0.data_stream.V' (edge_detect.cpp:29) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img1.data_stream.V' (edge_detect.cpp:30) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img2.data_stream.V' (edge_detect.cpp:31) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img3.data_stream.V' (edge_detect.cpp:32) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img0.data_stream.V' (edge_detect.cpp:9) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-102]" key="XFORM_AUTO_PARTITION_STATUS_112" tag="" content="Automatically partitioning streamed array 'img0.data_stream.V' (edge_detect.cpp:9) ."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 's1.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:351) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 's2.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:352) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'd.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:353) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'kernel.val.V' in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'kernel.val.V135' in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'pix.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:115) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'src_kernel_win.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:398) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'k_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'right_border_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:403) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'col_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:405) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 's.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:1556) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'kernel_opr.par.val.V' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1960) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_s.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1965) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_d.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1966) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_s.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1965) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_d.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1966) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'pix.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:56) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_s.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2524) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_d.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2525) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_s.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2524) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array '_d.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2525) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'scl.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:670) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img0.data_stream.V' (edge_detect.cpp:45) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img1.data_stream.V' (edge_detect.cpp:46) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img2.data_stream.V' (edge_detect.cpp:47) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img4.data_stream.V' (edge_detect.cpp:48) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img0.data_stream.V' (edge_detect.cpp:29) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img1.data_stream.V' (edge_detect.cpp:30) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img2.data_stream.V' (edge_detect.cpp:31) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img3.data_stream.V' (edge_detect.cpp:32) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img0.data_stream.V' (edge_detect.cpp:9) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'img0.data_stream.V' (edge_detect.cpp:9) in dimension 1 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'kernel.val.V' in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'kernel.val.V135' in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'src_kernel_win.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:398) in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'k_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400) in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'right_border_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:403) in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'col_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:405) in dimension 2 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'src_kernel_win.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:398) in dimension 3 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'right_border_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:403) in dimension 3 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-101]" key="XFORM_PARTITION_STATUS_116" tag="" content="Partitioning array 'col_buf.val' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:405) in dimension 3 completely."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<35, 13, (ap_q_mode)5, (ap_o_mode)3>' into 'hls::sr_cast<unsigned char, ap_fixed<35, 13, (ap_q_mode)5, (ap_o_mode)3, 0> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_fixed<35, 13, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'hls::kernel_CvtColor<HLS_RGB2GRAY, unsigned char, unsigned char>::apply<3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1498->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::kernel_CvtColor<HLS_RGB2GRAY, unsigned char, unsigned char>::apply<3, 3>' into 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<20, 20, (ap_q_mode)5, (ap_o_mode)3>' into 'hls::sr_cast<unsigned char, ap_fixed<20, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_fixed<20, 20, (ap_q_mode)5, (ap_o_mode)3, 0> >' into 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:304->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:514->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1289) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::Sobel<1, 0, 3, hls::BORDER_DEFAULT, 4096, 4096, 1080, 1920, 1080, 1920>' into 'hls::Sobel<1, 0, 3, 4096, 4096, 1080, 1920, 1080, 1920>154' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2627) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::data' into 'fp_struct<double>::to_double' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::to_double' into 'fp_struct<double>::to_ieee' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'fp_struct<double>::to_ieee' into 'generic_copysign<double>' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_copysign<double>' into 'generic_fabs<double>' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_fabs<double>' into 'hls::abs' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'generic_isnan<double>' into 'hls::isnan' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/isnandouble.cpp:7) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::isnan' into 'hls::__isnan' (r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/isnandouble.cpp:11) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::__isnan' into 'hls::sr_cast_class<ap_uint<8> >::operator().1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:428) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::abs' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>155' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, double>' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>155' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::Sobel<0, 1, 3, hls::BORDER_DEFAULT, 4096, 4096, 1080, 1920, 1080, 1920>' into 'hls::Sobel<0, 1, 3, 4096, 4096, 1080, 1920, 1080, 1920>156' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2627) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::abs' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>157' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, double>' into 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>157' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<41>' into 'hls::sr_cast<unsigned char, ap_int<41> >' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, ap_int<41> >' into 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:282->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:361) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()<8>' into 'hls::sr_cast_class<ap_uint<8> >::operator()' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:432) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast_class<ap_uint<8> >::operator()' into 'hls::sr_cast<unsigned char, unsigned char>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-602]" key="XFORM_AUTO_INLINE_STATUS_223" tag="" content="Inlining function 'hls::sr_cast<unsigned char, unsigned char>' into 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1554->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) automatically."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-712]" key="XFORM_DATAFLOW_TRANSFORM_230" tag="DATAFLOW" content="Applying dataflow to function 'mysobel152', detected/extracted 3 process function(s):
|
||||
'mysobel152_Block__proc'
|
||||
'hls::Sobel<1, 0, 3, 4096, 4096, 1080, 1920, 1080, 1920>154'
|
||||
'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>155'."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-712]" key="XFORM_DATAFLOW_TRANSFORM_230" tag="DATAFLOW" content="Applying dataflow to function 'mysobel153', detected/extracted 3 process function(s):
|
||||
'mysobel153_Block__proc'
|
||||
'hls::Sobel<0, 1, 3, 4096, 4096, 1080, 1920, 1080, 1920>156'
|
||||
'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>157'."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-712]" key="XFORM_DATAFLOW_TRANSFORM_230" tag="DATAFLOW" content="Applying dataflow to function 'mysobelxy', detected/extracted 5 process function(s):
|
||||
'mysobelxy_Block__proc228'
|
||||
'hls::Duplicate<1080, 1920, 4096, 4096>'
|
||||
'mysobel152'
|
||||
'mysobel153'
|
||||
'hls::AddWeighted<1080, 1920, 4096, 4096, 4096, int>'."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-712]" key="XFORM_DATAFLOW_TRANSFORM_230" tag="DATAFLOW" content="Applying dataflow to function 'sobelfoo', detected/extracted 6 process function(s):
|
||||
'sobelfoo_Block__proc'
|
||||
'hls::AXIvideo2Mat<24, 1080, 1920, 4096>'
|
||||
'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>'
|
||||
'mysobelxy'
|
||||
'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>'
|
||||
'hls::Mat2AXIvideo<24, 1080, 1920, 4096>'."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-712]" key="XFORM_DATAFLOW_TRANSFORM_230" tag="DATAFLOW" content="Applying dataflow to function 'edge_detect', detected/extracted 1 process function(s):
|
||||
'sobelfoo'."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:427:42) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:430:5) in function 'hls::sr_cast_class<ap_uint<8> >::operator().1'... converting 30 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:444:57) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:465:21) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 12 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:165:17) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:512:24) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 13 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgbase.h:113:42) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:465:21) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 12 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:165:17) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:512:24) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 13 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgbase.h:113:42) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:465:21) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 12 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-401]" key="XFORM_IFCONV_STATUS_239" tag="" content="Performing if-conversion on hyperblock from (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_mem.h:165:17) to (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:512:24) in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>'... converting 13 basic blocks."/>
|
||||
<Message severity="INFO" prefix="[XFORM 203-11]" key="XFORM_EXPR_BALANCE_STATUS_178" tag="" content="Balancing expressions in function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1279)...30 expression(s) balanced."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Pre-synthesis Time (s): cpu = 00:00:09 ; elapsed = 00:00:33 . Memory (MB): peak = 400.914 ; gain = 309.469"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobelxy_Block__proc228' to 'mysobelxy_Block__pro'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobel153_Block__proc' to 'mysobel153_Block__pr'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobel152_Block__proc' to 'mysobel152_Block__pr'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::sr_cast_class<ap_uint<8> >::operator().1' to 'operator().1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:18:5)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::arithm_pro<hls::kernel_addWeighted, 1080, 1920, 4096, 4096, 4096, int, int, int>' to 'arithm_pro' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:280:50)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::Sobel<1, 0, 3, 4096, 4096, 1080, 1920, 1080, 1920>154' to 'Sobel154' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2619:1)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::Sobel<0, 1, 3, 4096, 4096, 1080, 1920, 1080, 1920>156' to 'Sobel156' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2619:1)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::Mat2AXIvideo<24, 1080, 1920, 4096>' to 'Mat2AXIvideo' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:78:50)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::Filter2D<hls::BORDER_DEFAULT, 4096, 4096, ap_int<8>, int, 1080, 1920, 3, 3>' to 'Filter2D' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:118:33)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::Duplicate<1080, 1920, 4096, 4096>' to 'Duplicate' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:672:50)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::CvtColor<HLS_RGB2GRAY, 4096, 4096, 1080, 1920>' to 'CvtColor' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:409:39)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::CvtColor<HLS_GRAY2RGB, 4096, 4096, 1080, 1920>' to 'CvtColor.1' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:672:39)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>157' to 'ConvertScaleAbs157' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:475:34)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::ConvertScaleAbs<4096, 4096, 1080, 1920>155' to 'ConvertScaleAbs155' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:475:34)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::AddWeighted<1080, 1920, 4096, 4096, 4096, int>' to 'AddWeighted' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879:1)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'hls::AXIvideo2Mat<24, 1080, 1920, 4096>' to 'AXIvideo2Mat' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:49:9)"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'arithm_pro'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'arithm_pro'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'Mat2AXIvideo'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'Mat2AXIvideo'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 10 to 1922 for loop 'loop_width' in function 'Filter2D'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_402" tag="" content="Updating loop upper bound from 1083 to 1082 for loop 'loop_height' in function 'Filter2D'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 9 to 1082 for loop 'loop_height' in function 'Filter2D'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'Duplicate'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'Duplicate'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'CvtColor.1'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'CvtColor.1'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'CvtColor'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'CvtColor'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'ConvertScaleAbs157'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'ConvertScaleAbs157'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'ConvertScaleAbs155'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'ConvertScaleAbs155'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1920 for loop 'loop_width' in function 'AXIvideo2Mat'."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-561]" key="XFORM_LOOPBOUND_INVALID_405" tag="" content="Updating loop lower bound from 0 to 1080 for loop 'loop_height' in function 'AXIvideo2Mat'."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[0].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[0].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[1].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[2].val[4]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[1].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[1].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[2].val[3]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[2].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[ANALYSIS 214-52]" key="ANALYSIS_USER_SET_DEP_242" tag="" content="Found false inter dependency for variable 'k_buf[0].val[5]' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:400)."/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'sobelfoo_Block__proc' to 'sobelfoo_Block__proc.1'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobelxy_Block__pro' to 'mysobelxy_Block__pro.1'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobel153_Block__pr' to 'mysobel153_Block__pr.1'"/>
|
||||
<Message severity="WARNING" prefix="[XFORM 203-631]" key="XFORM_FRN_STATUS_336" tag="" content="Renaming function 'mysobel152_Block__pr' to 'mysobel152_Block__pr.1'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished Architecture Synthesis Time (s): cpu = 00:00:12 ; elapsed = 00:00:37 . Memory (MB): peak = 578.906 ; gain = 487.461"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1317" tag="" content="Starting hardware synthesis ..."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1385" tag="" content="Synthesizing 'edge_detect' ..."/>
|
||||
<Message severity="WARNING" prefix="[SYN 201-103]" key="SYN_MODULE_NAME_ILLEGAL_445" tag="" content="Legalizing function name 'operator().1' to 'operator_1'."/>
|
||||
<Message severity="WARNING" prefix="[SYN 201-103]" key="SYN_MODULE_NAME_ILLEGAL_445" tag="" content="Legalizing function name 'CvtColor.1' to 'CvtColor_1'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'AXIvideo2Mat'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_wait_for_start'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 1."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 2."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_wait_for_eol'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 1."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 36.894 seconds; current allocated memory: 515.233 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-434]" key="HLS 200-434" tag="SDX" content="Only 3 loops out of a total 4 loops have been pipelined in this design."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.159 seconds; current allocated memory: 515.538 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'CvtColor'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 6."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_76" tag="SDX_KERNEL,SCHEDULE" content="Estimated clock period (8.295ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_74" tag="SDX_KERNEL,SCHEDULE" content="The critical path in module 'CvtColor' consists of the following:
|
||||
'mul' operation of DSP[49] ('mul_ln703_1', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1497->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [43] (3.36 ns)
|
||||
'add' operation of DSP[49] ('ret.V', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1497->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [49] (3.02 ns)
|
||||
'add' operation ('__Val2__', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:409->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1498->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1545->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:1972) [53] (1.92 ns)"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.37 seconds; current allocated memory: 515.789 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.149 seconds; current allocated memory: 516.006 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'Duplicate'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 2."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.406 seconds; current allocated memory: 516.120 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.137 seconds; current allocated memory: 516.334 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'Filter2D'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 9."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.614 seconds; current allocated memory: 518.028 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.428 seconds; current allocated memory: 519.589 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'Sobel154'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.476 seconds; current allocated memory: 519.781 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.157 seconds; current allocated memory: 519.902 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'operator_1'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_46" tag="" content="Pipelining function 'operator().1'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 6."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.31 seconds; current allocated memory: 520.423 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.2 seconds; current allocated memory: 520.890 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'ConvertScaleAbs155'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 18."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_76" tag="SDX_KERNEL,SCHEDULE" content="Estimated clock period (6.562ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_74" tag="SDX_KERNEL,SCHEDULE" content="The critical path in module 'ConvertScaleAbs155' consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.448 seconds; current allocated memory: 521.229 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.244 seconds; current allocated memory: 521.633 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'mysobel152'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.355 seconds; current allocated memory: 521.960 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.337 seconds; current allocated memory: 522.350 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'Sobel156'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.468 seconds; current allocated memory: 522.817 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.163 seconds; current allocated memory: 522.937 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'ConvertScaleAbs157'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 18."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_76" tag="SDX_KERNEL,SCHEDULE" content="Estimated clock period (6.562ns) exceeds the target (target clock period: 6.7ns, clock uncertainty: 0.8375ns, effective delay budget: 5.8625ns)."/>
|
||||
<Message severity="WARNING" prefix="[SCHED 204-21]" key="SCHED_DELAY_EXCEEDED_74" tag="SDX_KERNEL,SCHEDULE" content="The critical path in module 'ConvertScaleAbs157' consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.472 seconds; current allocated memory: 523.300 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.251 seconds; current allocated memory: 523.673 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'mysobel153'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.367 seconds; current allocated memory: 524.036 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.334 seconds; current allocated memory: 524.390 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'arithm_pro'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 3."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.706 seconds; current allocated memory: 525.007 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.161 seconds; current allocated memory: 525.282 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'AddWeighted'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.164 seconds; current allocated memory: 525.322 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.139 seconds; current allocated memory: 525.418 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'mysobelxy'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.144 seconds; current allocated memory: 525.502 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 1.172 seconds; current allocated memory: 527.189 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'CvtColor_1'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 2."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.95 seconds; current allocated memory: 528.177 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.152 seconds; current allocated memory: 528.321 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'Mat2AXIvideo'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_41" tag="" content="Pipelining loop 'loop_width'."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-61]" key="SCHED_PIPELINING_STATUS_44" tag="" content="Pipelining result : Target II = 1, Final II = 1, Depth = 3."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.262 seconds; current allocated memory: 528.414 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.151 seconds; current allocated memory: 528.583 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'sobelfoo'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.161 seconds; current allocated memory: 528.731 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.98 seconds; current allocated memory: 530.147 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1477" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-42]" key="HLS_42_1438" tag="" content="-- Implementing module 'edge_detect'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1478" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_597" tag="" content="Starting scheduling ..."/>
|
||||
<Message severity="INFO" prefix="[SCHED 204-11]" key="SCHED_SCHED_STATUS_596" tag="" content="Finished scheduling."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.776 seconds; current allocated memory: 531.089 MB."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_926" tag="" content="Starting micro-architecture generation ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_698" tag="" content="Performing variable lifetime analysis."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_697" tag="" content="Exploring resource sharing."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-101]" key="BIND_101_693" tag="" content="Binding ..."/>
|
||||
<Message severity="INFO" prefix="[BIND 205-100]" key="BIND_100_925" tag="" content="Finished micro-architecture generation."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.356 seconds; current allocated memory: 531.455 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'AXIvideo2Mat'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'AXIvideo2Mat'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.791 seconds; current allocated memory: 533.224 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'CvtColor'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'edge_detect_mul_mul_22ns_8ns_29_1_1' to 'edge_detect_mul_mbkb' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'edge_detect_mac_muladd_20ns_8ns_29ns_29_1_1' to 'edge_detect_mac_mcud' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'edge_detect_mac_muladd_23ns_8ns_29ns_30_1_1' to 'edge_detect_mac_mdEe' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_mac_mcud': 1 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_mac_mdEe': 1 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_mul_mbkb': 1 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'CvtColor'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.412 seconds; current allocated memory: 533.831 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'Duplicate'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'Duplicate'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.312 seconds; current allocated memory: 534.187 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'Filter2D'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_0_val_3' to 'Filter2D_k_buf_0_eOg' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_0_val_4' to 'Filter2D_k_buf_0_fYi' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_0_val_5' to 'Filter2D_k_buf_0_g8j' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_1_val_3' to 'Filter2D_k_buf_1_hbi' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_1_val_4' to 'Filter2D_k_buf_1_ibs' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_1_val_5' to 'Filter2D_k_buf_1_jbC' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_2_val_3' to 'Filter2D_k_buf_2_kbM' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_2_val_4' to 'Filter2D_k_buf_2_lbW' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'Filter2D_k_buf_2_val_5' to 'Filter2D_k_buf_2_mb6' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'edge_detect_mux_32_8_1_1' to 'edge_detect_mux_3ncg' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_mux_3ncg': 18 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'Filter2D'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.472 seconds; current allocated memory: 537.312 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'Sobel154'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'Sobel154'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 1.865 seconds; current allocated memory: 538.446 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'operator_1'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'operator_1'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.333 seconds; current allocated memory: 539.492 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'ConvertScaleAbs155'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'edge_detect_sitodp_32ns_64_8_1' to 'edge_detect_sitodocq' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_sitodocq': 3 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'ConvertScaleAbs155'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.767 seconds; current allocated memory: 540.601 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'mysobel152'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_ConvertScaleAbs155_U0' to 'start_for_ConvertpcA' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'mysobel152'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.554 seconds; current allocated memory: 541.257 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'Sobel156'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'Sobel156'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.553 seconds; current allocated memory: 541.970 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'ConvertScaleAbs157'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_855" tag="" content="Generating core module 'edge_detect_sitodocq': 3 instance(s)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'ConvertScaleAbs157'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.362 seconds; current allocated memory: 542.835 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'mysobel153'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="WARNING" prefix="[RTGEN 206-101]" key="RTGEN_101_751" tag="" content="RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x' due to conflict."/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_ConvertScaleAbs157_U0' to 'start_for_ConvertqcK' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'mysobel153'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.566 seconds; current allocated memory: 543.470 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'arithm_pro'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'arithm_pro'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.566 seconds; current allocated memory: 544.343 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'AddWeighted'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'AddWeighted'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.377 seconds; current allocated memory: 544.703 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'mysobelxy'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="WARNING" prefix="[RTGEN 206-101]" key="RTGEN_101_751" tag="" content="RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x0' due to conflict."/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_mysobel152_U0' to 'start_for_mysobelrcU' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_mysobel153_U0' to 'start_for_mysobelsc4' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_AddWeighted_U0' to 'start_for_AddWeigtde' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'mysobelxy'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.29 seconds; current allocated memory: 545.485 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'CvtColor_1'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'CvtColor_1'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 1.009 seconds; current allocated memory: 546.614 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'Mat2AXIvideo'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'Mat2AXIvideo'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.292 seconds; current allocated memory: 547.412 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'sobelfoo'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="WARNING" prefix="[RTGEN 206-101]" key="RTGEN_101_751" tag="" content="RTL name 'fifo_w8_d2_A' is changed to 'fifo_w8_d2_A_x1' due to conflict."/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_CvtColor_U0' to 'start_for_CvtColoudo' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_mysobelxy_U0' to 'start_for_mysobelvdy' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_CvtColor_1_U0' to 'start_for_CvtColowdI' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[SYN 201-210]" key="SYN_210_889" tag="" content="Renamed object name 'start_for_Mat2AXIvideo_U0' to 'start_for_Mat2AXIxdS' due to the length limit 20"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'sobelfoo'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 0.405 seconds; current allocated memory: 548.205 MB."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1483" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1484" tag="" content="-- Generating RTL for module 'edge_detect'"/>
|
||||
<Message severity="INFO" prefix="[HLS 200-10]" key="HLS_10_1485" tag="" content="----------------------------------------------------------------"/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_data_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_keep_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_strb_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_user_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_last_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_id_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_in_V_dest_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_data_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_keep_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_strb_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_user_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_last_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_id_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on port 'edge_detect/stream_out_V_dest_V' to 'axis' (register, both mode)."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-500]" key="PREPROC_IO_COMP_CONFLICT_1950" tag="" content="Setting interface mode on function 'edge_detect' to 'ap_ctrl_hs'."/>
|
||||
<Message severity="INFO" prefix="[RTGEN 206-100]" key="RTGEN_100_856" tag="" content="Finished creating RTL model for 'edge_detect'."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_966" tag="" content=" Elapsed time: 1.233 seconds; current allocated memory: 549.258 MB."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-278]" key="RTMG_278_1790" tag="" content="Implementing memory 'Filter2D_k_buf_0_eOg_ram (RAM)' using block RAMs."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_0_s_U(fifo_w8_d2_A)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_1_s_U(fifo_w8_d2_A)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_2_s_U(fifo_w8_d2_A)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_ConvertpcA_U(start_for_ConvertpcA)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_0_s_U(fifo_w8_d2_A_x)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_1_s_U(fifo_w8_d2_A_x)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_2_s_U(fifo_w8_d2_A_x)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_ConvertqcK_U(start_for_ConvertqcK)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_0_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_1_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_2_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_0_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_1_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_2_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_0_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_1_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_2_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img3_data_stream_0_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img3_data_stream_1_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img3_data_stream_2_s_U(fifo_w8_d2_A_x0)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_mysobelrcU_U(start_for_mysobelrcU)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_mysobelsc4_U(start_for_mysobelsc4)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_AddWeigtde_U(start_for_AddWeigtde)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_0_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_1_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img0_data_stream_2_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_0_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_1_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img1_data_stream_2_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_0_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_1_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img2_data_stream_2_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img4_data_stream_0_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img4_data_stream_1_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'img4_data_stream_2_s_U(fifo_w8_d2_A_x1)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_CvtColoudo_U(start_for_CvtColoudo)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_mysobelvdy_U(start_for_mysobelvdy)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_CvtColowdI_U(start_for_CvtColowdI)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[RTMG 210-285]" key="RTMG_285_1799" tag="" content="Implementing FIFO 'start_for_Mat2AXIxdS_U(start_for_Mat2AXIxdS)' using Shift Registers."/>
|
||||
<Message severity="INFO" prefix="[HLS 200-111]" key="HLS_111_965" tag="" content="Finished generating all RTL models Time (s): cpu = 00:00:37 ; elapsed = 00:01:07 . Memory (MB): peak = 649.840 ; gain = 558.395"/>
|
||||
<Message severity="INFO" prefix="[VHDL 208-304]" key="VHDL_304_1066" tag="" content="Generating VHDL RTL for edge_detect."/>
|
||||
<Message severity="INFO" prefix="[VLOG 209-307]" key="VLOG_307_1067" tag="" content="Generating Verilog RTL for edge_detect."/>
|
||||
</Messages>
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,2 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
# clear list
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_begin
|
||||
cg_default_interface_gen_bundle_begin
|
||||
AESL_LIB_XILADAPTER::native_axis_begin
|
||||
}
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 1 \
|
||||
name AXI_video_strm_V_data_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TDATA { I 24 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_data_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 2 \
|
||||
name AXI_video_strm_V_keep_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TKEEP { I 3 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_keep_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 3 \
|
||||
name AXI_video_strm_V_strb_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TSTRB { I 3 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_strb_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 4 \
|
||||
name AXI_video_strm_V_user_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TUSER { I 1 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_user_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 5 \
|
||||
name AXI_video_strm_V_last_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TLAST { I 1 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_last_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 6 \
|
||||
name AXI_video_strm_V_id_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TID { I 1 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_id_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Native AXIS:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc ::AESL_LIB_XILADAPTER::native_axis_add] == "::AESL_LIB_XILADAPTER::native_axis_add"} {
|
||||
eval "::AESL_LIB_XILADAPTER::native_axis_add { \
|
||||
id 7 \
|
||||
name AXI_video_strm_V_dest_V \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename {stream_in} \
|
||||
metadata { } \
|
||||
op interface \
|
||||
ports { stream_in_TVALID { I 1 bit } stream_in_TREADY { O 1 bit } stream_in_TDEST { I 1 vector } } \
|
||||
} "
|
||||
} else {
|
||||
puts "@W \[IMPL-110\] Cannot find bus interface model in the library. Ignored generation of bus interface for 'AXI_video_strm_V_dest_V'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 8 \
|
||||
name img_data_stream_0_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_img_data_stream_0_V \
|
||||
op interface \
|
||||
ports { img_data_stream_0_V_din { O 8 vector } img_data_stream_0_V_full_n { I 1 bit } img_data_stream_0_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 9 \
|
||||
name img_data_stream_1_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_img_data_stream_1_V \
|
||||
op interface \
|
||||
ports { img_data_stream_1_V_din { O 8 vector } img_data_stream_1_V_full_n { I 1 bit } img_data_stream_1_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 10 \
|
||||
name img_data_stream_2_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_img_data_stream_2_V \
|
||||
op interface \
|
||||
ports { img_data_stream_2_V_din { O 8 vector } img_data_stream_2_V_full_n { I 1 bit } img_data_stream_2_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id -1 \
|
||||
name ap_ctrl \
|
||||
type ap_ctrl \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename ap_ctrl \
|
||||
op interface \
|
||||
ports { ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_clk
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
|
||||
eval "cg_default_interface_gen_clock { \
|
||||
id -2 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_clk \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_rst
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
|
||||
eval "cg_default_interface_gen_reset { \
|
||||
id -3 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_rst \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
# merge
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_end
|
||||
cg_default_interface_gen_bundle_end
|
||||
AESL_LIB_XILADAPTER::native_axis_end
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,171 @@
|
|||
set moduleName AXIvideo2Mat
|
||||
set isTopModule 0
|
||||
set isTaskLevelControl 1
|
||||
set isCombinational 0
|
||||
set isDatapathOnly 0
|
||||
set isFreeRunPipelineModule 0
|
||||
set isPipelined 0
|
||||
set pipeline_type none
|
||||
set FunctionProtocol ap_ctrl_hs
|
||||
set isOneStateSeq 0
|
||||
set ProfileFlag 0
|
||||
set StallSigGenFlag 0
|
||||
set isEnableWaveformDebug 1
|
||||
set C_modelName {AXIvideo2Mat}
|
||||
set C_modelType { void 0 }
|
||||
set C_modelArgList {
|
||||
{ AXI_video_strm_V_data_V int 24 regular {axi_s 0 volatile { stream_in Data } } }
|
||||
{ AXI_video_strm_V_keep_V int 3 regular {axi_s 0 volatile { stream_in Keep } } }
|
||||
{ AXI_video_strm_V_strb_V int 3 regular {axi_s 0 volatile { stream_in Strb } } }
|
||||
{ AXI_video_strm_V_user_V int 1 regular {axi_s 0 volatile { stream_in User } } }
|
||||
{ AXI_video_strm_V_last_V int 1 regular {axi_s 0 volatile { stream_in Last } } }
|
||||
{ AXI_video_strm_V_id_V int 1 regular {axi_s 0 volatile { stream_in ID } } }
|
||||
{ AXI_video_strm_V_dest_V int 1 regular {axi_s 0 volatile { stream_in Dest } } }
|
||||
{ img_data_stream_0_V int 8 regular {fifo 1 volatile } }
|
||||
{ img_data_stream_1_V int 8 regular {fifo 1 volatile } }
|
||||
{ img_data_stream_2_V int 8 regular {fifo 1 volatile } }
|
||||
}
|
||||
set C_modelArgMapList {[
|
||||
{ "Name" : "AXI_video_strm_V_data_V", "interface" : "axis", "bitwidth" : 24, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_keep_V", "interface" : "axis", "bitwidth" : 3, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_strb_V", "interface" : "axis", "bitwidth" : 3, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_user_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_last_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_id_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
|
||||
{ "Name" : "AXI_video_strm_V_dest_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
|
||||
{ "Name" : "img_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "img_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "img_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ]}
|
||||
# RTL Port declarations:
|
||||
set portNum 28
|
||||
set portList {
|
||||
{ ap_clk sc_in sc_logic 1 clock -1 }
|
||||
{ ap_rst sc_in sc_logic 1 reset -1 active_high_sync }
|
||||
{ ap_start sc_in sc_logic 1 start -1 }
|
||||
{ start_full_n sc_in sc_logic 1 signal -1 }
|
||||
{ ap_done sc_out sc_logic 1 predone -1 }
|
||||
{ ap_continue sc_in sc_logic 1 continue -1 }
|
||||
{ ap_idle sc_out sc_logic 1 done -1 }
|
||||
{ ap_ready sc_out sc_logic 1 ready -1 }
|
||||
{ start_out sc_out sc_logic 1 signal -1 }
|
||||
{ start_write sc_out sc_logic 1 signal -1 }
|
||||
{ stream_in_TDATA sc_in sc_lv 24 signal 0 }
|
||||
{ stream_in_TVALID sc_in sc_logic 1 invld 6 }
|
||||
{ stream_in_TREADY sc_out sc_logic 1 inacc 6 }
|
||||
{ stream_in_TKEEP sc_in sc_lv 3 signal 1 }
|
||||
{ stream_in_TSTRB sc_in sc_lv 3 signal 2 }
|
||||
{ stream_in_TUSER sc_in sc_lv 1 signal 3 }
|
||||
{ stream_in_TLAST sc_in sc_lv 1 signal 4 }
|
||||
{ stream_in_TID sc_in sc_lv 1 signal 5 }
|
||||
{ stream_in_TDEST sc_in sc_lv 1 signal 6 }
|
||||
{ img_data_stream_0_V_din sc_out sc_lv 8 signal 7 }
|
||||
{ img_data_stream_0_V_full_n sc_in sc_logic 1 signal 7 }
|
||||
{ img_data_stream_0_V_write sc_out sc_logic 1 signal 7 }
|
||||
{ img_data_stream_1_V_din sc_out sc_lv 8 signal 8 }
|
||||
{ img_data_stream_1_V_full_n sc_in sc_logic 1 signal 8 }
|
||||
{ img_data_stream_1_V_write sc_out sc_logic 1 signal 8 }
|
||||
{ img_data_stream_2_V_din sc_out sc_lv 8 signal 9 }
|
||||
{ img_data_stream_2_V_full_n sc_in sc_logic 1 signal 9 }
|
||||
{ img_data_stream_2_V_write sc_out sc_logic 1 signal 9 }
|
||||
}
|
||||
set NewPortList {[
|
||||
{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
|
||||
{ "name": "ap_rst", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst", "role": "default" }} ,
|
||||
{ "name": "ap_start", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "start", "bundle":{"name": "ap_start", "role": "default" }} ,
|
||||
{ "name": "start_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_full_n", "role": "default" }} ,
|
||||
{ "name": "ap_done", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "predone", "bundle":{"name": "ap_done", "role": "default" }} ,
|
||||
{ "name": "ap_continue", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "continue", "bundle":{"name": "ap_continue", "role": "default" }} ,
|
||||
{ "name": "ap_idle", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "done", "bundle":{"name": "ap_idle", "role": "default" }} ,
|
||||
{ "name": "ap_ready", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "ready", "bundle":{"name": "ap_ready", "role": "default" }} ,
|
||||
{ "name": "start_out", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_out", "role": "default" }} ,
|
||||
{ "name": "start_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_write", "role": "default" }} ,
|
||||
{ "name": "stream_in_TDATA", "direction": "in", "datatype": "sc_lv", "bitwidth":24, "type": "signal", "bundle":{"name": "AXI_video_strm_V_data_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TVALID", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "invld", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TREADY", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "inacc", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TKEEP", "direction": "in", "datatype": "sc_lv", "bitwidth":3, "type": "signal", "bundle":{"name": "AXI_video_strm_V_keep_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TSTRB", "direction": "in", "datatype": "sc_lv", "bitwidth":3, "type": "signal", "bundle":{"name": "AXI_video_strm_V_strb_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TUSER", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_user_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TLAST", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_last_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TID", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_id_V", "role": "default" }} ,
|
||||
{ "name": "stream_in_TDEST", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
|
||||
{ "name": "img_data_stream_0_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "din" }} ,
|
||||
{ "name": "img_data_stream_0_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "full_n" }} ,
|
||||
{ "name": "img_data_stream_0_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "write" }} ,
|
||||
{ "name": "img_data_stream_1_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "din" }} ,
|
||||
{ "name": "img_data_stream_1_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "full_n" }} ,
|
||||
{ "name": "img_data_stream_1_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "write" }} ,
|
||||
{ "name": "img_data_stream_2_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "din" }} ,
|
||||
{ "name": "img_data_stream_2_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "full_n" }} ,
|
||||
{ "name": "img_data_stream_2_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "write" }} ]}
|
||||
|
||||
set RtlHierarchyInfo {[
|
||||
{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "",
|
||||
"CDFG" : "AXIvideo2Mat",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "1", "ap_idle" : "1",
|
||||
"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "0",
|
||||
"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2079003", "EstimateLatencyMax" : "2079003",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "0",
|
||||
"ClockEnable" : "0",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "1",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "AXI_video_strm_V_data_V", "Type" : "Axis", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "stream_in_TDATA_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "AXI_video_strm_V_keep_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "AXI_video_strm_V_strb_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "AXI_video_strm_V_user_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "AXI_video_strm_V_last_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "AXI_video_strm_V_id_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "AXI_video_strm_V_dest_V", "Type" : "Axis", "Direction" : "I"},
|
||||
{"Name" : "img_data_stream_0_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "img_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "img_data_stream_1_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "img_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "img_data_stream_2_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "img_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]}]}]}
|
||||
|
||||
|
||||
set ArgLastReadFirstWriteLatency {
|
||||
AXIvideo2Mat {
|
||||
AXI_video_strm_V_data_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_keep_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_strb_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_user_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_last_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_id_V {Type I LastRead 6 FirstWrite -1}
|
||||
AXI_video_strm_V_dest_V {Type I LastRead 6 FirstWrite -1}
|
||||
img_data_stream_0_V {Type O LastRead -1 FirstWrite 5}
|
||||
img_data_stream_1_V {Type O LastRead -1 FirstWrite 5}
|
||||
img_data_stream_2_V {Type O LastRead -1 FirstWrite 5}}}
|
||||
|
||||
set hasDtUnsupportedChannel 0
|
||||
|
||||
set PerformanceInfo {[
|
||||
{"Name" : "Latency", "Min" : "2079003", "Max" : "2079003"}
|
||||
, {"Name" : "Interval", "Min" : "2079003", "Max" : "2079003"}
|
||||
]}
|
||||
|
||||
set PipelineEnableSignalInfo {[
|
||||
{"Pipeline" : "1", "EnableSignal" : "ap_enable_pp1"}
|
||||
]}
|
||||
|
||||
set Spec2ImplPortList {
|
||||
AXI_video_strm_V_data_V { axis { { stream_in_TDATA in_data 0 24 } } }
|
||||
AXI_video_strm_V_keep_V { axis { { stream_in_TKEEP in_data 0 3 } } }
|
||||
AXI_video_strm_V_strb_V { axis { { stream_in_TSTRB in_data 0 3 } } }
|
||||
AXI_video_strm_V_user_V { axis { { stream_in_TUSER in_data 0 1 } } }
|
||||
AXI_video_strm_V_last_V { axis { { stream_in_TLAST in_data 0 1 } } }
|
||||
AXI_video_strm_V_id_V { axis { { stream_in_TID in_data 0 1 } } }
|
||||
AXI_video_strm_V_dest_V { axis { { stream_in_TVALID in_vld 0 1 } { stream_in_TREADY in_acc 1 1 } { stream_in_TDEST in_data 0 1 } } }
|
||||
img_data_stream_0_V { ap_fifo { { img_data_stream_0_V_din fifo_data 1 8 } { img_data_stream_0_V_full_n fifo_status 0 1 } { img_data_stream_0_V_write fifo_update 1 1 } } }
|
||||
img_data_stream_1_V { ap_fifo { { img_data_stream_1_V_din fifo_data 1 8 } { img_data_stream_1_V_full_n fifo_status 0 1 } { img_data_stream_1_V_write fifo_update 1 1 } } }
|
||||
img_data_stream_2_V { ap_fifo { { img_data_stream_2_V_din fifo_data 1 8 } { img_data_stream_2_V_full_n fifo_status 0 1 } { img_data_stream_2_V_write fifo_update 1 1 } } }
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,49 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AXIvideo2Mat'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:26 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 2.931, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2079003, 2079003, 2079003, 2079003, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_wait_for_start">0, 0, 1, 1, 1, 0, yes</column>
|
||||
<column name="- loop_height">2079000, 2079000, 1925, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1920, 1920, 2, 1, 1, 1920, yes</column>
|
||||
<column name=" + loop_wait_for_eol">0, 0, 1, 1, 1, 0, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,228 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AXIvideo2Mat'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:40 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 2.931, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2079003, 2079003, 2079003, 2079003, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_wait_for_start">0, 0, 1, 1, 1, 0, yes</column>
|
||||
<column name="- loop_height">2079000, 2079000, 1925, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1920, 1920, 2, 1, 1, 1920, yes</column>
|
||||
<column name=" + loop_wait_for_eol">0, 0, 1, 1, 1, 0, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Utilization Estimates" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="1">
|
||||
<keys size="6">Name, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
<column name="DSP">-, -, -, -, -</column>
|
||||
<column name="Expression">-, -, 0, 110, -</column>
|
||||
<column name="FIFO">-, -, -, -, -</column>
|
||||
<column name="Instance">-, -, -, -, -</column>
|
||||
<column name="Memory">-, -, -, -, -</column>
|
||||
<column name="Multiplexer">-, -, -, 362, -</column>
|
||||
<column name="Register">-, -, 264, -, -</column>
|
||||
<specialColumn name="Available">280, 220, 106400, 53200, 0</specialColumn>
|
||||
<specialColumn name="Utilization (%)">0, 0, ~0, ~0, 0</specialColumn>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="1">
|
||||
<keys size="7">Instance, Module, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "DSP48E"><table name="" hasTotal="0">
|
||||
<keys size="3">Instance, Module, Expression</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Memory"><table name="" hasTotal="1">
|
||||
<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "FIFO"><table name="" hasTotal="1">
|
||||
<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Expression"><table name="" hasTotal="1">
|
||||
<keys size="7">Variable Name, Operation, DSP48E, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
|
||||
<column name="i_V_fu_291_p2">+, 0, 0, 13, 11, 1</column>
|
||||
<column name="j_V_fu_303_p2">+, 0, 0, 13, 11, 1</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_load_A">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_load_B">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_load_A">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_load_B">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_load_A">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_load_B">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state5_pp1_stage0_iter0">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state8">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_condition_559">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_condition_633">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_predicate_op50_read_state5">and, 0, 0, 2, 1, 1</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_state_cmp_full">icmp, 0, 0, 8, 2, 1</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_state_cmp_full">icmp, 0, 0, 8, 2, 1</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_state_cmp_full">icmp, 0, 0, 8, 2, 1</column>
|
||||
<column name="icmp_ln71_fu_285_p2">icmp, 0, 0, 13, 11, 11</column>
|
||||
<column name="icmp_ln73_fu_297_p2">icmp, 0, 0, 13, 11, 9</column>
|
||||
<column name="ap_block_pp1_stage0_01001">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state1">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state6_pp1_stage0_iter1">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="or_ln76_fu_312_p2">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_enable_pp1">xor, 0, 0, 2, 1, 2</column>
|
||||
<column name="ap_enable_reg_pp1_iter1">xor, 0, 0, 2, 2, 1</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Multiplexer"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
|
||||
<column name="AXI_video_strm_V_data_V_0_data_out">9, 2, 24, 48</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_state">15, 3, 2, 6</column>
|
||||
<column name="AXI_video_strm_V_dest_V_0_state">15, 3, 2, 6</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_data_out">9, 2, 1, 2</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_state">15, 3, 2, 6</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_data_out">9, 2, 1, 2</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_state">15, 3, 2, 6</column>
|
||||
<column name="ap_NS_fsm">44, 9, 1, 9</column>
|
||||
<column name="ap_done">9, 2, 1, 2</column>
|
||||
<column name="ap_enable_reg_pp1_iter1">15, 3, 1, 3</column>
|
||||
<column name="ap_phi_mux_axi_data_V_1_phi_fu_176_p4">9, 2, 24, 48</column>
|
||||
<column name="ap_phi_mux_eol_0_phi_fu_199_p4">9, 2, 1, 2</column>
|
||||
<column name="ap_phi_mux_eol_phi_fu_165_p4">9, 2, 1, 2</column>
|
||||
<column name="ap_phi_mux_p_Val2_s_phi_fu_224_p4">15, 3, 24, 72</column>
|
||||
<column name="axi_data_V_0_reg_141">9, 2, 24, 48</column>
|
||||
<column name="axi_data_V_1_reg_173">9, 2, 24, 48</column>
|
||||
<column name="axi_data_V_3_reg_244">9, 2, 24, 48</column>
|
||||
<column name="axi_last_V_0_reg_131">9, 2, 1, 2</column>
|
||||
<column name="axi_last_V_2_reg_207">15, 3, 1, 3</column>
|
||||
<column name="axi_last_V_3_reg_232">9, 2, 1, 2</column>
|
||||
<column name="eol_0_reg_195">9, 2, 1, 2</column>
|
||||
<column name="eol_2_reg_256">9, 2, 1, 2</column>
|
||||
<column name="eol_reg_162">9, 2, 1, 2</column>
|
||||
<column name="img_data_stream_0_V_blk_n">9, 2, 1, 2</column>
|
||||
<column name="img_data_stream_1_V_blk_n">9, 2, 1, 2</column>
|
||||
<column name="img_data_stream_2_V_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_Val2_s_reg_220">15, 3, 24, 72</column>
|
||||
<column name="real_start">9, 2, 1, 2</column>
|
||||
<column name="stream_in_TDATA_blk_n">9, 2, 1, 2</column>
|
||||
<column name="t_V_5_reg_184">9, 2, 11, 22</column>
|
||||
<column name="t_V_reg_151">9, 2, 11, 22</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Register"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
|
||||
<column name="AXI_video_strm_V_data_V_0_payload_A">24, 0, 24, 0</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_payload_B">24, 0, 24, 0</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_sel_rd">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_sel_wr">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_data_V_0_state">2, 0, 2, 0</column>
|
||||
<column name="AXI_video_strm_V_dest_V_0_state">2, 0, 2, 0</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_payload_A">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_payload_B">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_sel_rd">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_sel_wr">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_last_V_0_state">2, 0, 2, 0</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_payload_A">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_payload_B">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_sel_rd">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_sel_wr">1, 0, 1, 0</column>
|
||||
<column name="AXI_video_strm_V_user_V_0_state">2, 0, 2, 0</column>
|
||||
<column name="ap_CS_fsm">8, 0, 8, 0</column>
|
||||
<column name="ap_done_reg">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp1_iter0">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp1_iter1">1, 0, 1, 0</column>
|
||||
<column name="axi_data_V_0_reg_141">24, 0, 24, 0</column>
|
||||
<column name="axi_data_V_1_reg_173">24, 0, 24, 0</column>
|
||||
<column name="axi_data_V_3_reg_244">24, 0, 24, 0</column>
|
||||
<column name="axi_last_V_0_reg_131">1, 0, 1, 0</column>
|
||||
<column name="axi_last_V_2_reg_207">1, 0, 1, 0</column>
|
||||
<column name="axi_last_V_3_reg_232">1, 0, 1, 0</column>
|
||||
<column name="eol_0_reg_195">1, 0, 1, 0</column>
|
||||
<column name="eol_2_reg_256">1, 0, 1, 0</column>
|
||||
<column name="eol_reg_162">1, 0, 1, 0</column>
|
||||
<column name="i_V_reg_371">11, 0, 11, 0</column>
|
||||
<column name="icmp_ln73_reg_376">1, 0, 1, 0</column>
|
||||
<column name="p_Val2_s_reg_220">24, 0, 24, 0</column>
|
||||
<column name="sof_1_fu_88">1, 0, 1, 0</column>
|
||||
<column name="start_once_reg">1, 0, 1, 0</column>
|
||||
<column name="t_V_5_reg_184">11, 0, 11, 0</column>
|
||||
<column name="t_V_reg_151">11, 0, 11, 0</column>
|
||||
<column name="tmp_28_reg_394">8, 0, 8, 0</column>
|
||||
<column name="tmp_29_reg_399">8, 0, 8, 0</column>
|
||||
<column name="tmp_data_V_reg_347">24, 0, 24, 0</column>
|
||||
<column name="tmp_last_V_reg_355">1, 0, 1, 0</column>
|
||||
<column name="tmp_reg_389">8, 0, 8, 0</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Interface" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
|
||||
<column name="ap_clk">in, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_rst">in, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_start">in, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="start_full_n">in, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_done">out, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_continue">in, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_idle">out, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="ap_ready">out, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="start_out">out, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="start_write">out, 1, ap_ctrl_hs, AXIvideo2Mat, return value</column>
|
||||
<column name="stream_in_TDATA">in, 24, axis, AXI_video_strm_V_data_V, pointer</column>
|
||||
<column name="stream_in_TVALID">in, 1, axis, AXI_video_strm_V_dest_V, pointer</column>
|
||||
<column name="stream_in_TREADY">out, 1, axis, AXI_video_strm_V_dest_V, pointer</column>
|
||||
<column name="stream_in_TDEST">in, 1, axis, AXI_video_strm_V_dest_V, pointer</column>
|
||||
<column name="stream_in_TKEEP">in, 3, axis, AXI_video_strm_V_keep_V, pointer</column>
|
||||
<column name="stream_in_TSTRB">in, 3, axis, AXI_video_strm_V_strb_V, pointer</column>
|
||||
<column name="stream_in_TUSER">in, 1, axis, AXI_video_strm_V_user_V, pointer</column>
|
||||
<column name="stream_in_TLAST">in, 1, axis, AXI_video_strm_V_last_V, pointer</column>
|
||||
<column name="stream_in_TID">in, 1, axis, AXI_video_strm_V_id_V, pointer</column>
|
||||
<column name="img_data_stream_0_V_din">out, 8, ap_fifo, img_data_stream_0_V, pointer</column>
|
||||
<column name="img_data_stream_0_V_full_n">in, 1, ap_fifo, img_data_stream_0_V, pointer</column>
|
||||
<column name="img_data_stream_0_V_write">out, 1, ap_fifo, img_data_stream_0_V, pointer</column>
|
||||
<column name="img_data_stream_1_V_din">out, 8, ap_fifo, img_data_stream_1_V, pointer</column>
|
||||
<column name="img_data_stream_1_V_full_n">in, 1, ap_fifo, img_data_stream_1_V, pointer</column>
|
||||
<column name="img_data_stream_1_V_write">out, 1, ap_fifo, img_data_stream_1_V, pointer</column>
|
||||
<column name="img_data_stream_2_V_din">out, 8, ap_fifo, img_data_stream_2_V, pointer</column>
|
||||
<column name="img_data_stream_2_V_full_n">in, 1, ap_fifo, img_data_stream_2_V, pointer</column>
|
||||
<column name="img_data_stream_2_V_write">out, 1, ap_fifo, img_data_stream_2_V, pointer</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
|
||||
|
||||
================================================================
|
||||
== Vivado HLS Report for 'AXIvideo2Mat'
|
||||
================================================================
|
||||
* Date: Tue Feb 7 10:18:26 2023
|
||||
|
||||
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
|
||||
* Project: edge_detect
|
||||
* Solution: solution1
|
||||
* Product family: zynq
|
||||
* Target device: xc7z020-clg400-1
|
||||
|
||||
|
||||
================================================================
|
||||
== Performance Estimates
|
||||
================================================================
|
||||
+ Timing (ns):
|
||||
* Summary:
|
||||
+--------+-------+----------+------------+
|
||||
| Clock | Target| Estimated| Uncertainty|
|
||||
+--------+-------+----------+------------+
|
||||
|ap_clk | 6.70| 2.931| 0.84|
|
||||
+--------+-------+----------+------------+
|
||||
|
||||
+ Latency (clock cycles):
|
||||
* Summary:
|
||||
+---------+---------+---------+---------+---------+
|
||||
| Latency | Interval | Pipeline|
|
||||
| min | max | min | max | Type |
|
||||
+---------+---------+---------+---------+---------+
|
||||
| 2079003| 2079003| 2079003| 2079003| none |
|
||||
+---------+---------+---------+---------+---------+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
N/A
|
||||
|
||||
* Loop:
|
||||
+-----------------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
| | Latency | Iteration| Initiation Interval | Trip | |
|
||||
| Loop Name | min | max | Latency | achieved | target | Count| Pipelined|
|
||||
+-----------------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
|- loop_wait_for_start | 0| 0| 1| 1| 1| 0| yes |
|
||||
|- loop_height | 2079000| 2079000| 1925| -| -| 1080| no |
|
||||
| + loop_width | 1920| 1920| 2| 1| 1| 1920| yes |
|
||||
| + loop_wait_for_eol | 0| 0| 1| 1| 1| 0| yes |
|
||||
+-----------------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Synthesis Manager
|
||||
============================================================
|
||||
InlineROM: 1
|
||||
ExposeGlobal: 0
|
||||
============================================================
|
||||
+ Verbose Summary: CDFG Model
|
||||
============================================================
|
||||
IsTopModel: 0
|
||||
ResetActiveHigh: 1
|
||||
IsCombinational: 2
|
||||
IsDatapathOnly: 0
|
||||
HasWiredReturn: 1
|
||||
HasMFsm: 0
|
||||
HasVarLatency: 1
|
||||
IsPipeline: 0
|
||||
IsRtlPipelined: 0
|
||||
IsInstanceOverlapped: 0
|
||||
IsDontTouch: 0
|
||||
HasImplIP: 0
|
||||
IsGatedGlobalClock: 0
|
||||
|
||||
+ Individual pipeline summary:
|
||||
* Pipeline-0: initiation interval (II) = 1, depth = 1
|
||||
* Pipeline-1: initiation interval (II) = 1, depth = 2
|
||||
* Pipeline-2: initiation interval (II) = 1, depth = 1
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Schedule
|
||||
============================================================
|
||||
* Number of FSM states : 9
|
||||
* Pipeline : 3
|
||||
Pipeline-0 : II = 1, D = 1, States = { 2 }
|
||||
Pipeline-1 : II = 1, D = 2, States = { 5 6 }
|
||||
Pipeline-2 : II = 1, D = 1, States = { 8 }
|
||||
* Dataflow Pipeline: 0
|
||||
|
||||
* FSM state transitions:
|
||||
1 --> 2
|
||||
2 --> 3 2
|
||||
3 --> 4
|
||||
4 --> 5
|
||||
5 --> 7 6
|
||||
6 --> 5
|
||||
7 --> 8
|
||||
8 --> 9 8
|
||||
9 --> 4
|
||||
|
||||
* FSM state operations:
|
||||
|
||||
State 1 <SV = 0> <Delay = 0.00>
|
||||
ST_1 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 13 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V, [5 x i8]* @p_str1, i32 1, i32 1, [5 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str) nounwind" ---> Operation 13 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 14 [1/1] (0.00ns) ---> "br label %loop_wait_for_start" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:63] ---> Operation 14 'br' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
State 2 <SV = 1> <Delay = 0.00>
|
||||
ST_2 : Operation 15 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([20 x i8]* @p_str18) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:65] ---> Operation 15 'specloopname' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 16 [1/1] (0.00ns) ---> "%tmp_s = call i32 (...)* @_ssdm_op_SpecRegionBegin([20 x i8]* @p_str18)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:65] ---> Operation 16 'specregionbegin' 'tmp_s' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 17 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:66] ---> Operation 17 'specpipeline' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 18 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:67] ---> Operation 18 'speclooptripcount' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 19 [1/1] (0.00ns) ---> "%empty = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:68] ---> Operation 19 'read' 'empty' <Predicate = true> <Delay = 0.00> <Core = "AXI4Stream"> ---> Core 5 'AXI4Stream' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : >
|
||||
ST_2 : Operation 20 [1/1] (0.00ns) ---> "%tmp_data_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:68] ---> Operation 20 'extractvalue' 'tmp_data_V' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 21 [1/1] (0.00ns) ---> "%tmp_user_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 3" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:68] ---> Operation 21 'extractvalue' 'tmp_user_V' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 22 [1/1] (0.00ns) ---> "%tmp_last_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 4" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:68] ---> Operation 22 'extractvalue' 'tmp_last_V' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 23 [1/1] (0.00ns) ---> "%empty_108 = call i32 (...)* @_ssdm_op_SpecRegionEnd([20 x i8]* @p_str18, i32 %tmp_s)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:70] ---> Operation 23 'specregionend' 'empty_108' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 24 [1/1] (0.00ns) ---> "br i1 %tmp_user_V, label %.preheader232.preheader, label %loop_wait_for_start" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:65] ---> Operation 24 'br' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
State 3 <SV = 2> <Delay = 1.76>
|
||||
ST_3 : Operation 25 [1/1] (0.00ns) ---> "%sof_1 = alloca i1" ---> Operation 25 'alloca' 'sof_1' <Predicate = true> <Delay = 0.00>
|
||||
ST_3 : Operation 26 [1/1] (1.76ns) ---> "store i1 true, i1* %sof_1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 26 'store' <Predicate = true> <Delay = 1.76>
|
||||
ST_3 : Operation 27 [1/1] (1.76ns) ---> "br label %.preheader232" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 27 'br' <Predicate = true> <Delay = 1.76>
|
||||
|
||||
State 4 <SV = 3> <Delay = 2.85>
|
||||
ST_4 : Operation 28 [1/1] (0.00ns) ---> "%axi_last_V_0 = phi i1 [ %axi_last_V_3, %loop_height_end ], [ %tmp_last_V, %.preheader232.preheader ]" ---> Operation 28 'phi' 'axi_last_V_0' <Predicate = true> <Delay = 0.00>
|
||||
ST_4 : Operation 29 [1/1] (0.00ns) ---> "%axi_data_V_0 = phi i24 [ %axi_data_V_3, %loop_height_end ], [ %tmp_data_V, %.preheader232.preheader ]" ---> Operation 29 'phi' 'axi_data_V_0' <Predicate = true> <Delay = 0.00>
|
||||
ST_4 : Operation 30 [1/1] (0.00ns) ---> "%t_V = phi i11 [ %i_V, %loop_height_end ], [ 0, %.preheader232.preheader ]" ---> Operation 30 'phi' 't_V' <Predicate = true> <Delay = 0.00>
|
||||
ST_4 : Operation 31 [1/1] (1.88ns) ---> "%icmp_ln71 = icmp eq i11 %t_V, -968" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 31 'icmp' 'icmp_ln71' <Predicate = true> <Delay = 1.88> <Core = "Cmp"> ---> Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.88> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_4 : Operation 32 [1/1] (1.63ns) ---> "%i_V = add i11 %t_V, 1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 32 'add' 'i_V' <Predicate = true> <Delay = 1.63> <Core = "AddSub"> ---> Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.63> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_4 : Operation 33 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1080, i64 1080, i64 1080)" ---> Operation 33 'speclooptripcount' <Predicate = true> <Delay = 0.00>
|
||||
ST_4 : Operation 34 [1/1] (0.00ns) ---> "br i1 %icmp_ln71, label %2, label %loop_height_begin" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 34 'br' <Predicate = true> <Delay = 0.00>
|
||||
ST_4 : Operation 35 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([12 x i8]* @p_str7) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 35 'specloopname' <Predicate = (!icmp_ln71)> <Delay = 0.00>
|
||||
ST_4 : Operation 36 [1/1] (0.00ns) ---> "%tmp_25 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str7)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 36 'specregionbegin' 'tmp_25' <Predicate = (!icmp_ln71)> <Delay = 0.00>
|
||||
ST_4 : Operation 37 [1/1] (1.76ns) ---> "br label %0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 37 'br' <Predicate = (!icmp_ln71)> <Delay = 1.76>
|
||||
ST_4 : Operation 38 [1/1] (0.00ns) ---> "ret void" ---> Operation 38 'ret' <Predicate = (icmp_ln71)> <Delay = 0.00>
|
||||
|
||||
State 5 <SV = 4> <Delay = 2.85>
|
||||
ST_5 : Operation 39 [1/1] (0.00ns) ---> "%eol = phi i1 [ %axi_last_V_0, %loop_height_begin ], [ %axi_last_V_2, %hls_label_4 ]" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:100] ---> Operation 39 'phi' 'eol' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 40 [1/1] (0.00ns) ---> "%axi_data_V_1 = phi i24 [ %axi_data_V_0, %loop_height_begin ], [ %p_Val2_s, %hls_label_4 ]" ---> Operation 40 'phi' 'axi_data_V_1' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 41 [1/1] (0.00ns) ---> "%t_V_5 = phi i11 [ 0, %loop_height_begin ], [ %j_V, %hls_label_4 ]" ---> Operation 41 'phi' 't_V_5' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 42 [1/1] (0.00ns) ---> "%eol_0 = phi i1 [ false, %loop_height_begin ], [ %axi_last_V_2, %hls_label_4 ]" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:81] ---> Operation 42 'phi' 'eol_0' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 43 [1/1] (1.88ns) ---> "%icmp_ln73 = icmp eq i11 %t_V_5, -128" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 43 'icmp' 'icmp_ln73' <Predicate = true> <Delay = 1.88> <Core = "Cmp"> ---> Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.88> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_5 : Operation 44 [1/1] (1.63ns) ---> "%j_V = add i11 %t_V_5, 1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 44 'add' 'j_V' <Predicate = true> <Delay = 1.63> <Core = "AddSub"> ---> Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.63> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_5 : Operation 45 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1920, i64 1920, i64 1920)" ---> Operation 45 'speclooptripcount' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 46 [1/1] (0.00ns) ---> "br i1 %icmp_ln73, label %.preheader.preheader, label %loop_width_begin" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 46 'br' <Predicate = true> <Delay = 0.00>
|
||||
ST_5 : Operation 47 [1/1] (0.00ns) ---> "%sof_1_load = load i1* %sof_1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:76] ---> Operation 47 'load' 'sof_1_load' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 48 [1/1] (0.97ns) ---> "%or_ln76 = or i1 %sof_1_load, %eol_0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:76] ---> Operation 48 'or' 'or_ln76' <Predicate = (!icmp_ln73)> <Delay = 0.97> <Core = "LogicGate"> ---> Core 27 'LogicGate' <Latency = 0> <II = 1> <Delay = 0.97> <FuncUnit> <Opcode : 'and' 'or' 'xor'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_5 : Operation 49 [1/1] (1.76ns) ---> "br i1 %or_ln76, label %hls_label_4, label %1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:76] ---> Operation 49 'br' <Predicate = (!icmp_ln73)> <Delay = 1.76>
|
||||
ST_5 : Operation 50 [1/1] (0.00ns) ---> "%empty_109 = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:81] ---> Operation 50 'read' 'empty_109' <Predicate = (!icmp_ln73 & !or_ln76)> <Delay = 0.00> <Core = "AXI4Stream"> ---> Core 5 'AXI4Stream' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : >
|
||||
ST_5 : Operation 51 [1/1] (0.00ns) ---> "%tmp_data_V_1 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_109, 0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:81] ---> Operation 51 'extractvalue' 'tmp_data_V_1' <Predicate = (!icmp_ln73 & !or_ln76)> <Delay = 0.00>
|
||||
ST_5 : Operation 52 [1/1] (0.00ns) ---> "%tmp_last_V_1 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_109, 4" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:81] ---> Operation 52 'extractvalue' 'tmp_last_V_1' <Predicate = (!icmp_ln73 & !or_ln76)> <Delay = 0.00>
|
||||
ST_5 : Operation 53 [1/1] (1.76ns) ---> "br label %hls_label_4" ---> Operation 53 'br' <Predicate = (!icmp_ln73 & !or_ln76)> <Delay = 1.76>
|
||||
ST_5 : Operation 54 [1/1] (0.00ns) ---> "%axi_last_V_2 = phi i1 [ %tmp_last_V_1, %1 ], [ %eol, %loop_width_begin ]" ---> Operation 54 'phi' 'axi_last_V_2' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 55 [1/1] (0.00ns) ---> "%p_Val2_s = phi i24 [ %tmp_data_V_1, %1 ], [ %axi_data_V_1, %loop_width_begin ]" ---> Operation 55 'phi' 'p_Val2_s' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 56 [1/1] (0.00ns) ---> "%tmp = trunc i24 %p_Val2_s to i8" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:49->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:71->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:92] ---> Operation 56 'trunc' 'tmp' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 57 [1/1] (0.00ns) ---> "%tmp_28 = call i8 @_ssdm_op_PartSelect.i8.i24.i32.i32(i24 %p_Val2_s, i32 8, i32 15)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:49->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:71->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:92] ---> Operation 57 'partselect' 'tmp_28' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 58 [1/1] (0.00ns) ---> "%tmp_29 = call i8 @_ssdm_op_PartSelect.i8.i24.i32.i32(i24 %p_Val2_s, i32 16, i32 23)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:49->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_axi_io.h:71->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:92] ---> Operation 58 'partselect' 'tmp_29' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_5 : Operation 59 [1/1] (1.76ns) ---> "store i1 false, i1* %sof_1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 59 'store' <Predicate = (!icmp_ln73)> <Delay = 1.76>
|
||||
|
||||
State 6 <SV = 5> <Delay = 2.93>
|
||||
ST_6 : Operation 60 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str8) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 60 'specloopname' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 61 [1/1] (0.00ns) ---> "%tmp_26 = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str8)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 61 'specregionbegin' 'tmp_26' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 62 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:75] ---> Operation 62 'specpipeline' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 63 [1/1] (0.00ns) ---> "%tmp_30 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str16)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:696->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 63 'specregionbegin' 'tmp_30' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 64 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:700->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 64 'specprotocol' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 65 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_0_V, i8 %tmp)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 65 'write' <Predicate = (!icmp_ln73)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_6 : Operation 66 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_1_V, i8 %tmp_28)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 66 'write' <Predicate = (!icmp_ln73)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_6 : Operation 67 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_2_V, i8 %tmp_29)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 67 'write' <Predicate = (!icmp_ln73)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_6 : Operation 68 [1/1] (0.00ns) ---> "%empty_110 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str16, i32 %tmp_30)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:705->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94] ---> Operation 68 'specregionend' 'empty_110' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 69 [1/1] (0.00ns) ---> "%empty_111 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str8, i32 %tmp_26)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:95] ---> Operation 69 'specregionend' 'empty_111' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
ST_6 : Operation 70 [1/1] (0.00ns) ---> "br label %0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73] ---> Operation 70 'br' <Predicate = (!icmp_ln73)> <Delay = 0.00>
|
||||
|
||||
State 7 <SV = 5> <Delay = 1.76>
|
||||
ST_7 : Operation 71 [1/1] (1.76ns) ---> "br label %.preheader" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:96] ---> Operation 71 'br' <Predicate = true> <Delay = 1.76>
|
||||
|
||||
State 8 <SV = 6> <Delay = 0.00>
|
||||
ST_8 : Operation 72 [1/1] (0.00ns) ---> "%axi_last_V_3 = phi i1 [ %tmp_last_V_2, %loop_wait_for_eol ], [ %eol, %.preheader.preheader ]" ---> Operation 72 'phi' 'axi_last_V_3' <Predicate = true> <Delay = 0.00>
|
||||
ST_8 : Operation 73 [1/1] (0.00ns) ---> "%axi_data_V_3 = phi i24 [ %tmp_data_V_2, %loop_wait_for_eol ], [ %axi_data_V_1, %.preheader.preheader ]" ---> Operation 73 'phi' 'axi_data_V_3' <Predicate = true> <Delay = 0.00>
|
||||
ST_8 : Operation 74 [1/1] (0.00ns) ---> "%eol_2 = phi i1 [ %tmp_last_V_2, %loop_wait_for_eol ], [ %eol_0, %.preheader.preheader ]" ---> Operation 74 'phi' 'eol_2' <Predicate = true> <Delay = 0.00>
|
||||
ST_8 : Operation 75 [1/1] (0.00ns) ---> "br i1 %eol_2, label %loop_height_end, label %loop_wait_for_eol" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:96] ---> Operation 75 'br' <Predicate = true> <Delay = 0.00>
|
||||
ST_8 : Operation 76 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([18 x i8]* @p_str19) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:96] ---> Operation 76 'specloopname' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 77 [1/1] (0.00ns) ---> "%tmp_27 = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @p_str19)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:96] ---> Operation 77 'specregionbegin' 'tmp_27' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 78 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:97] ---> Operation 78 'specpipeline' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 79 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:98] ---> Operation 79 'speclooptripcount' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 80 [1/1] (0.00ns) ---> "%empty_112 = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:100] ---> Operation 80 'read' 'empty_112' <Predicate = (!eol_2)> <Delay = 0.00> <Core = "AXI4Stream"> ---> Core 5 'AXI4Stream' <Latency = 0> <II = 1> <Delay = 1.00> <Adapter> <Opcode : >
|
||||
ST_8 : Operation 81 [1/1] (0.00ns) ---> "%tmp_data_V_2 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_112, 0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:100] ---> Operation 81 'extractvalue' 'tmp_data_V_2' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 82 [1/1] (0.00ns) ---> "%tmp_last_V_2 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_112, 4" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:100] ---> Operation 82 'extractvalue' 'tmp_last_V_2' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 83 [1/1] (0.00ns) ---> "%empty_113 = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @p_str19, i32 %tmp_27)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:103] ---> Operation 83 'specregionend' 'empty_113' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
ST_8 : Operation 84 [1/1] (0.00ns) ---> "br label %.preheader" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:103] ---> Operation 84 'br' <Predicate = (!eol_2)> <Delay = 0.00>
|
||||
|
||||
State 9 <SV = 7> <Delay = 0.00>
|
||||
ST_9 : Operation 85 [1/1] (0.00ns) ---> "%empty_114 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str7, i32 %tmp_25)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:104] ---> Operation 85 'specregionend' 'empty_114' <Predicate = true> <Delay = 0.00>
|
||||
ST_9 : Operation 86 [1/1] (0.00ns) ---> "br label %.preheader232" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71] ---> Operation 86 'br' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Timing violations
|
||||
============================================================
|
||||
Target clock period: 6.7ns, clock uncertainty: 0.837ns.
|
||||
|
||||
<State 1>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
<State 2>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
<State 3>: 1.77ns
|
||||
The critical path consists of the following:
|
||||
'alloca' operation ('sof_1') [28] (0 ns)
|
||||
'store' operation ('store_ln71', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71) of constant 1 on local variable 'sof_1' [29] (1.77 ns)
|
||||
|
||||
<State 4>: 2.86ns
|
||||
The critical path consists of the following:
|
||||
'icmp' operation ('icmp_ln71', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:71) [35] (1.88 ns)
|
||||
blocking operation 0.978 ns on control path)
|
||||
|
||||
<State 5>: 2.86ns
|
||||
The critical path consists of the following:
|
||||
'icmp' operation ('icmp_ln73', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:73) [48] (1.88 ns)
|
||||
blocking operation 0.978 ns on control path)
|
||||
|
||||
<State 6>: 2.93ns
|
||||
The critical path consists of the following:
|
||||
fifo write on port 'img_data_stream_0_V' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:94) [72] (2.93 ns)
|
||||
|
||||
<State 7>: 1.77ns
|
||||
The critical path consists of the following:
|
||||
multiplexor before 'phi' operation ('axi.last.V') with incoming values : ('tmp.last.V', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:68) ('tmp.last.V', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:81) ('tmp.last.V', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_io.h:100) [82] (1.77 ns)
|
||||
|
||||
<State 8>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
<State 9>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Binding
|
||||
============================================================
|
||||
N/A
|
||||
* FSMD analyzer results:
|
||||
- Output states:
|
||||
- Input state :
|
||||
- Chain level:
|
||||
State 1
|
||||
State 2
|
||||
State 3
|
||||
State 4
|
||||
State 5
|
||||
State 6
|
||||
State 7
|
||||
State 8
|
||||
State 9
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Datapath Resource usage
|
||||
============================================================
|
||||
N/A
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AXIvideo2Mat'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:26 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 2.931, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2079003, 2079003, 2079003, 2079003, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_wait_for_start">0, 0, 1, 1, 1, 0, yes</column>
|
||||
<column name="- loop_height">2079000, 2079000, 1925, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1920, 1920, 2, 1, 1, 1920, yes</column>
|
||||
<column name=" + loop_wait_for_eol">0, 0, 1, 1, 1, 0, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,586 @@
|
|||
<stg><name>AddWeighted</name>
|
||||
|
||||
|
||||
<trans_list>
|
||||
|
||||
<trans id="15" from="1" to="2">
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
</trans>
|
||||
</trans_list>
|
||||
|
||||
|
||||
|
||||
<state_list>
|
||||
|
||||
<state id="1" st_id="1">
|
||||
|
||||
<operation id="3" st_id="1" stage="2" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
|
||||
<state id="2" st_id="2">
|
||||
|
||||
<operation id="4" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="10" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:0 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="5" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="11" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:1 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="6" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="12" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:2 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="7" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="13" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:3 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="8" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="14" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:4 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="9" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="15" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:5 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="10" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="16" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:6 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="11" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="17" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:7 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="12" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="18" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:8 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="13" st_id="2" stage="1" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="14" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="20" bw="0">
|
||||
<![CDATA[
|
||||
:10 ret void
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="ret_ln880"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
</state_list>
|
||||
|
||||
|
||||
<ports>
|
||||
<port id="16" name="src1_data_stream_0_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="17" name="src1_data_stream_1_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="18" name="src1_data_stream_2_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
<port id="19" name="src2_data_stream_0_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="20" name="src2_data_stream_1_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="21" name="src2_data_stream_2_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
<port id="22" name="dst_data_stream_0_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="23" name="dst_data_stream_1_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="24" name="dst_data_stream_2_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
</ports>
|
||||
|
||||
|
||||
<dataflows>
|
||||
<dataflow id="26" from="arithm_pro" to="call_ln879" fromId="25" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="27" from="src1_data_stream_0_V" to="call_ln879" fromId="16" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="28" from="src1_data_stream_1_V" to="call_ln879" fromId="17" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="29" from="src1_data_stream_2_V" to="call_ln879" fromId="18" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="30" from="src2_data_stream_0_V" to="call_ln879" fromId="19" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="31" from="src2_data_stream_1_V" to="call_ln879" fromId="20" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="32" from="src2_data_stream_2_V" to="call_ln879" fromId="21" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="33" from="dst_data_stream_0_V" to="call_ln879" fromId="22" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="34" from="dst_data_stream_1_V" to="call_ln879" fromId="23" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="35" from="dst_data_stream_2_V" to="call_ln879" fromId="24" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="37" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="38" from="src2_data_stream_2_V" to="specinterface_ln0" fromId="21" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="40" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="42" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="43" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="45" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="46" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="47" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="48" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="49" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="50" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="52" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="53" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="55" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="56" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="57" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="58" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="59" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="60" from="src2_data_stream_1_V" to="specinterface_ln0" fromId="20" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="61" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="62" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="63" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="64" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="65" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="66" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="67" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="68" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="69" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="70" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="71" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="72" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="73" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="74" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="75" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="76" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="77" from="src2_data_stream_0_V" to="specinterface_ln0" fromId="19" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="78" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="79" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="80" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="81" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="82" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="83" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="84" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="85" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="86" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="87" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="88" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="89" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="90" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="91" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="92" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="93" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="94" from="src1_data_stream_2_V" to="specinterface_ln0" fromId="18" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="95" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="96" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="97" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="98" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="99" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="100" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="101" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="102" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="103" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="104" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="105" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="106" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="107" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="108" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="109" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="110" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="111" from="src1_data_stream_1_V" to="specinterface_ln0" fromId="17" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="112" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="113" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="114" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
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|
||||
<outState>2</outState>
|
||||
<condition class_id="31" tracking_level="0" version="0">
|
||||
<id>-1</id>
|
||||
<sop class_id="32" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="33" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</item>
|
||||
</sop>
|
||||
</condition>
|
||||
</item>
|
||||
</transitions>
|
||||
</fsm>
|
||||
<res class_id="-1"></res>
|
||||
<node_label_latency class_id="35" tracking_level="0" version="0">
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="36" tracking_level="0" version="0">
|
||||
<first>19</first>
|
||||
<second class_id="37" tracking_level="0" version="0">
|
||||
<first>0</first>
|
||||
<second>1</second>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>20</first>
|
||||
<second>
|
||||
<first>1</first>
|
||||
<second>0</second>
|
||||
</second>
|
||||
</item>
|
||||
</node_label_latency>
|
||||
<bblk_ent_exit class_id="38" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="39" tracking_level="0" version="0">
|
||||
<first>21</first>
|
||||
<second class_id="40" tracking_level="0" version="0">
|
||||
<first>0</first>
|
||||
<second>1</second>
|
||||
</second>
|
||||
</item>
|
||||
</bblk_ent_exit>
|
||||
<regions class_id="41" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</regions>
|
||||
<dp_fu_nodes class_id="42" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="43" tracking_level="0" version="0">
|
||||
<first>32</first>
|
||||
<second>
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</dp_fu_nodes>
|
||||
<dp_fu_nodes_expression class_id="45" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes_expression>
|
||||
<dp_fu_nodes_module>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="46" tracking_level="0" version="0">
|
||||
<first>grp_arithm_pro_fu_32</first>
|
||||
<second>
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</dp_fu_nodes_module>
|
||||
<dp_fu_nodes_io>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes_io>
|
||||
<return_ports>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</return_ports>
|
||||
<dp_mem_port_nodes class_id="47" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_mem_port_nodes>
|
||||
<dp_reg_nodes>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_reg_nodes>
|
||||
<dp_regname_nodes>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_regname_nodes>
|
||||
<dp_reg_phi>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_reg_phi>
|
||||
<dp_regname_phi>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_regname_phi>
|
||||
<dp_port_io_nodes class_id="48" tracking_level="0" version="0">
|
||||
<count>9</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="49" tracking_level="0" version="0">
|
||||
<first>dst_data_stream_0_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>dst_data_stream_1_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>dst_data_stream_2_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src1_data_stream_0_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src1_data_stream_1_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src1_data_stream_2_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src2_data_stream_0_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src2_data_stream_1_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>src2_data_stream_2_V</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>call</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
</dp_port_io_nodes>
|
||||
<port2core class_id="50" tracking_level="0" version="0">
|
||||
<count>9</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="51" tracking_level="0" version="0">
|
||||
<first>1</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>2</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>3</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>4</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>5</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>6</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>7</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>8</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>9</first>
|
||||
<second>FIFO</second>
|
||||
</item>
|
||||
</port2core>
|
||||
<node2core>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</node2core>
|
||||
</syndb>
|
||||
</boost_serialization>
|
||||
|
||||
|
|
@ -0,0 +1,586 @@
|
|||
<stg><name>AddWeighted</name>
|
||||
|
||||
|
||||
<trans_list>
|
||||
|
||||
<trans id="15" from="1" to="2">
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
</trans>
|
||||
</trans_list>
|
||||
|
||||
|
||||
|
||||
<state_list>
|
||||
|
||||
<state id="1" st_id="1">
|
||||
|
||||
<operation id="3" st_id="1" stage="2" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
|
||||
<state id="2" st_id="2">
|
||||
|
||||
<operation id="4" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="10" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:0 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="5" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="11" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:1 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="6" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="12" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:2 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="7" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="13" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:3 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="8" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="14" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:4 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="9" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="15" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:5 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="10" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="16" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:6 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="11" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="17" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:7 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="12" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="18" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:8 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="13" st_id="2" stage="1" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="14" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="20" bw="0">
|
||||
<![CDATA[
|
||||
:10 ret void
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="ret_ln880"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
</state_list>
|
||||
|
||||
|
||||
<ports>
|
||||
<port id="16" name="src1_data_stream_0_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="17" name="src1_data_stream_1_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="18" name="src1_data_stream_2_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
<port id="19" name="src2_data_stream_0_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="20" name="src2_data_stream_1_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="21" name="src2_data_stream_2_V" dir="0" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
<port id="22" name="dst_data_stream_0_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
|
||||
</port>
|
||||
<port id="23" name="dst_data_stream_1_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
|
||||
</port>
|
||||
<port id="24" name="dst_data_stream_2_V" dir="1" iftype="3">
|
||||
<core>FIFO</core><StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
|
||||
</port>
|
||||
</ports>
|
||||
|
||||
|
||||
<dataflows>
|
||||
<dataflow id="26" from="arithm_pro" to="call_ln879" fromId="25" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="27" from="src1_data_stream_0_V" to="call_ln879" fromId="16" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="28" from="src1_data_stream_1_V" to="call_ln879" fromId="17" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="29" from="src1_data_stream_2_V" to="call_ln879" fromId="18" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="30" from="src2_data_stream_0_V" to="call_ln879" fromId="19" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="31" from="src2_data_stream_1_V" to="call_ln879" fromId="20" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="32" from="src2_data_stream_2_V" to="call_ln879" fromId="21" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="33" from="dst_data_stream_0_V" to="call_ln879" fromId="22" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="34" from="dst_data_stream_1_V" to="call_ln879" fromId="23" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="35" from="dst_data_stream_2_V" to="call_ln879" fromId="24" toId="3">
|
||||
</dataflow>
|
||||
<dataflow id="37" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="38" from="src2_data_stream_2_V" to="specinterface_ln0" fromId="21" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="40" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="42" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="43" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="45" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="46" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="47" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="48" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="49" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="50" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="52" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="53" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="55" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="56" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="57" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="58" from="p_str" to="specinterface_ln0" fromId="44" toId="4">
|
||||
</dataflow>
|
||||
<dataflow id="59" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="60" from="src2_data_stream_1_V" to="specinterface_ln0" fromId="20" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="61" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="62" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="63" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="64" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="65" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="66" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="67" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="68" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="69" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="70" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="71" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="72" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="73" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="74" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="75" from="p_str" to="specinterface_ln0" fromId="44" toId="5">
|
||||
</dataflow>
|
||||
<dataflow id="76" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="77" from="src2_data_stream_0_V" to="specinterface_ln0" fromId="19" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="78" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="79" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="80" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="81" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="82" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="83" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="84" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="85" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="86" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="87" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="88" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="89" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="90" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="91" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="92" from="p_str" to="specinterface_ln0" fromId="44" toId="6">
|
||||
</dataflow>
|
||||
<dataflow id="93" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="94" from="src1_data_stream_2_V" to="specinterface_ln0" fromId="18" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="95" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="96" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="97" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="98" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="99" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="100" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="101" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="102" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="103" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="104" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="105" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="106" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="107" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="108" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="109" from="p_str" to="specinterface_ln0" fromId="44" toId="7">
|
||||
</dataflow>
|
||||
<dataflow id="110" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="111" from="src1_data_stream_1_V" to="specinterface_ln0" fromId="17" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="112" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="113" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="114" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="115" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="116" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="117" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="118" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="119" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="120" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="121" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="122" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="123" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="124" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="125" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="126" from="p_str" to="specinterface_ln0" fromId="44" toId="8">
|
||||
</dataflow>
|
||||
<dataflow id="127" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="128" from="src1_data_stream_0_V" to="specinterface_ln0" fromId="16" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="129" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="130" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="131" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="132" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="133" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="134" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="135" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="136" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="137" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="138" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="139" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="140" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="141" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="142" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="143" from="p_str" to="specinterface_ln0" fromId="44" toId="9">
|
||||
</dataflow>
|
||||
<dataflow id="144" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="145" from="dst_data_stream_0_V" to="specinterface_ln0" fromId="22" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="146" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="147" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="148" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="149" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="150" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="151" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="152" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="153" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="154" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="155" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="156" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="157" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="158" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="159" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="160" from="p_str" to="specinterface_ln0" fromId="44" toId="10">
|
||||
</dataflow>
|
||||
<dataflow id="161" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="162" from="dst_data_stream_1_V" to="specinterface_ln0" fromId="23" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="163" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="164" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="165" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="166" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="167" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="168" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="169" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="170" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="171" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="172" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="173" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="174" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="175" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="176" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="177" from="p_str" to="specinterface_ln0" fromId="44" toId="11">
|
||||
</dataflow>
|
||||
<dataflow id="178" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="36" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="179" from="dst_data_stream_2_V" to="specinterface_ln0" fromId="24" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="180" from="ap_fifo_str" to="specinterface_ln0" fromId="39" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="181" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="182" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="183" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="184" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="185" from="StgValue_41" to="specinterface_ln0" fromId="41" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="186" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="187" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="188" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="189" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="190" from="StgValue_51" to="specinterface_ln0" fromId="51" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="191" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="192" from="StgValue_54" to="specinterface_ln0" fromId="54" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="193" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="194" from="p_str" to="specinterface_ln0" fromId="44" toId="12">
|
||||
</dataflow>
|
||||
<dataflow id="195" from="arithm_pro" to="call_ln879" fromId="25" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="196" from="src1_data_stream_0_V" to="call_ln879" fromId="16" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="197" from="src1_data_stream_1_V" to="call_ln879" fromId="17" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="198" from="src1_data_stream_2_V" to="call_ln879" fromId="18" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="199" from="src2_data_stream_0_V" to="call_ln879" fromId="19" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="200" from="src2_data_stream_1_V" to="call_ln879" fromId="20" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="201" from="src2_data_stream_2_V" to="call_ln879" fromId="21" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="202" from="dst_data_stream_0_V" to="call_ln879" fromId="22" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="203" from="dst_data_stream_1_V" to="call_ln879" fromId="23" toId="13">
|
||||
</dataflow>
|
||||
<dataflow id="204" from="dst_data_stream_2_V" to="call_ln879" fromId="24" toId="13">
|
||||
</dataflow>
|
||||
</dataflows>
|
||||
|
||||
|
||||
</stg>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
# clear list
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_begin
|
||||
cg_default_interface_gen_bundle_begin
|
||||
AESL_LIB_XILADAPTER::native_axis_begin
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 125 \
|
||||
name src1_data_stream_0_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src1_data_stream_0_V \
|
||||
op interface \
|
||||
ports { src1_data_stream_0_V_dout { I 8 vector } src1_data_stream_0_V_empty_n { I 1 bit } src1_data_stream_0_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 126 \
|
||||
name src1_data_stream_1_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src1_data_stream_1_V \
|
||||
op interface \
|
||||
ports { src1_data_stream_1_V_dout { I 8 vector } src1_data_stream_1_V_empty_n { I 1 bit } src1_data_stream_1_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 127 \
|
||||
name src1_data_stream_2_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src1_data_stream_2_V \
|
||||
op interface \
|
||||
ports { src1_data_stream_2_V_dout { I 8 vector } src1_data_stream_2_V_empty_n { I 1 bit } src1_data_stream_2_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 128 \
|
||||
name src2_data_stream_0_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src2_data_stream_0_V \
|
||||
op interface \
|
||||
ports { src2_data_stream_0_V_dout { I 8 vector } src2_data_stream_0_V_empty_n { I 1 bit } src2_data_stream_0_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 129 \
|
||||
name src2_data_stream_1_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src2_data_stream_1_V \
|
||||
op interface \
|
||||
ports { src2_data_stream_1_V_dout { I 8 vector } src2_data_stream_1_V_empty_n { I 1 bit } src2_data_stream_1_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 130 \
|
||||
name src2_data_stream_2_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_src2_data_stream_2_V \
|
||||
op interface \
|
||||
ports { src2_data_stream_2_V_dout { I 8 vector } src2_data_stream_2_V_empty_n { I 1 bit } src2_data_stream_2_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 131 \
|
||||
name dst_data_stream_0_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_dst_data_stream_0_V \
|
||||
op interface \
|
||||
ports { dst_data_stream_0_V_din { O 8 vector } dst_data_stream_0_V_full_n { I 1 bit } dst_data_stream_0_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 132 \
|
||||
name dst_data_stream_1_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_dst_data_stream_1_V \
|
||||
op interface \
|
||||
ports { dst_data_stream_1_V_din { O 8 vector } dst_data_stream_1_V_full_n { I 1 bit } dst_data_stream_1_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 133 \
|
||||
name dst_data_stream_2_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_dst_data_stream_2_V \
|
||||
op interface \
|
||||
ports { dst_data_stream_2_V_din { O 8 vector } dst_data_stream_2_V_full_n { I 1 bit } dst_data_stream_2_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id -1 \
|
||||
name ap_ctrl \
|
||||
type ap_ctrl \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename ap_ctrl \
|
||||
op interface \
|
||||
ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_clk
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
|
||||
eval "cg_default_interface_gen_clock { \
|
||||
id -2 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_clk \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_rst
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
|
||||
eval "cg_default_interface_gen_reset { \
|
||||
id -3 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_rst \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
# merge
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_end
|
||||
cg_default_interface_gen_bundle_end
|
||||
AESL_LIB_XILADAPTER::native_axis_end
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,619 @@
|
|||
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<!DOCTYPE boost_serialization>
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|
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|
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<Value>
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|
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<type>1</type>
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<id>7</id>
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<name>dst_data_stream_0_V</name>
|
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<fileName></fileName>
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<fileDirectory></fileDirectory>
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</inlineStackInfo>
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<originalName>dst.data_stream[0].V</originalName>
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<rtlName></rtlName>
|
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<coreName></coreName>
|
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<bitwidth>8</bitwidth>
|
||||
</Value>
|
||||
<direction>1</direction>
|
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<if_type>3</if_type>
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</bit_vecs>
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|
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|
||||
<Value>
|
||||
<Obj>
|
||||
<type>1</type>
|
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<id>8</id>
|
||||
<name>dst_data_stream_1_V</name>
|
||||
<fileName></fileName>
|
||||
<fileDirectory></fileDirectory>
|
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|
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|
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|
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</inlineStackInfo>
|
||||
<originalName>dst.data_stream[1].V</originalName>
|
||||
<rtlName></rtlName>
|
||||
<coreName></coreName>
|
||||
</Obj>
|
||||
<bitwidth>8</bitwidth>
|
||||
</Value>
|
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<direction>1</direction>
|
||||
<if_type>3</if_type>
|
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|
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<bit_vecs>
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|
||||
<Value>
|
||||
<Obj>
|
||||
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|
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<id>9</id>
|
||||
<name>dst_data_stream_2_V</name>
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|
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<fileDirectory></fileDirectory>
|
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<originalName>dst.data_stream[2].V</originalName>
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|
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<coreName></coreName>
|
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|
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|
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|
||||
</ports>
|
||||
<nodes class_id="8" tracking_level="0" version="0">
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
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|
||||
<Value>
|
||||
<Obj>
|
||||
<type>0</type>
|
||||
<id>19</id>
|
||||
<name>_ln879</name>
|
||||
<fileName>C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h</fileName>
|
||||
<fileDirectory>C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect</fileDirectory>
|
||||
<lineNumber>879</lineNumber>
|
||||
<contextFuncName>AddWeighted&lt;1080, 1920, 4096, 4096, 4096, int&gt;</contextFuncName>
|
||||
<inlineStackInfo>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="10" tracking_level="0" version="0">
|
||||
<first>C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect</first>
|
||||
<second class_id="11" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="12" tracking_level="0" version="0">
|
||||
<first class_id="13" tracking_level="0" version="0">
|
||||
<first>C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h</first>
|
||||
<second>AddWeighted&lt;1080, 1920, 4096, 4096, 4096, int&gt;</second>
|
||||
</first>
|
||||
<second>879</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
</inlineStackInfo>
|
||||
<originalName></originalName>
|
||||
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|
||||
<coreName></coreName>
|
||||
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|
||||
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|
||||
</Value>
|
||||
<oprand_edges>
|
||||
<count>10</count>
|
||||
<item_version>0</item_version>
|
||||
<item>23</item>
|
||||
<item>24</item>
|
||||
<item>25</item>
|
||||
<item>26</item>
|
||||
<item>27</item>
|
||||
<item>28</item>
|
||||
<item>29</item>
|
||||
<item>30</item>
|
||||
<item>31</item>
|
||||
<item>32</item>
|
||||
</oprand_edges>
|
||||
<opcode>call</opcode>
|
||||
<m_Display>0</m_Display>
|
||||
<m_isOnCriticalPath>0</m_isOnCriticalPath>
|
||||
<m_isLCDNode>0</m_isLCDNode>
|
||||
<m_isStartOfPath>0</m_isStartOfPath>
|
||||
<m_delay>0.00</m_delay>
|
||||
<m_topoIndex>1</m_topoIndex>
|
||||
<m_clusterGroupNumber>-1</m_clusterGroupNumber>
|
||||
</item>
|
||||
<item class_id_reference="9" object_id="_11">
|
||||
<Value>
|
||||
<Obj>
|
||||
<type>0</type>
|
||||
<id>20</id>
|
||||
<name>_ln880</name>
|
||||
<fileName>C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h</fileName>
|
||||
<fileDirectory>C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect</fileDirectory>
|
||||
<lineNumber>880</lineNumber>
|
||||
<contextFuncName>AddWeighted&lt;1080, 1920, 4096, 4096, 4096, int&gt;</contextFuncName>
|
||||
<inlineStackInfo>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>C:\Users\Sasa\workspace\Zybo_Z7_Embedded_Vision_Demo_2019_1\repo\local\ip\hls\edge_detect</first>
|
||||
<second>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>
|
||||
<first>
|
||||
<first>C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h</first>
|
||||
<second>AddWeighted&lt;1080, 1920, 4096, 4096, 4096, int&gt;</second>
|
||||
</first>
|
||||
<second>880</second>
|
||||
</item>
|
||||
</second>
|
||||
</item>
|
||||
</inlineStackInfo>
|
||||
<originalName></originalName>
|
||||
<rtlName></rtlName>
|
||||
<coreName></coreName>
|
||||
</Obj>
|
||||
<bitwidth>0</bitwidth>
|
||||
</Value>
|
||||
<oprand_edges>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</oprand_edges>
|
||||
<opcode>ret</opcode>
|
||||
<m_Display>0</m_Display>
|
||||
<m_isOnCriticalPath>0</m_isOnCriticalPath>
|
||||
<m_isLCDNode>0</m_isLCDNode>
|
||||
<m_isStartOfPath>0</m_isStartOfPath>
|
||||
<m_delay>0.00</m_delay>
|
||||
<m_topoIndex>2</m_topoIndex>
|
||||
<m_clusterGroupNumber>-1</m_clusterGroupNumber>
|
||||
</item>
|
||||
</nodes>
|
||||
<consts class_id="15" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="16" tracking_level="1" version="0" object_id="_12">
|
||||
<Value>
|
||||
<Obj>
|
||||
<type>2</type>
|
||||
<id>22</id>
|
||||
<name>arithm_pro</name>
|
||||
<fileName></fileName>
|
||||
<fileDirectory></fileDirectory>
|
||||
<lineNumber>0</lineNumber>
|
||||
<contextFuncName></contextFuncName>
|
||||
<inlineStackInfo>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</inlineStackInfo>
|
||||
<originalName></originalName>
|
||||
<rtlName></rtlName>
|
||||
<coreName></coreName>
|
||||
</Obj>
|
||||
<bitwidth>0</bitwidth>
|
||||
</Value>
|
||||
<const_type>6</const_type>
|
||||
<content><constant:arithm_pro></content>
|
||||
</item>
|
||||
</consts>
|
||||
<blocks class_id="17" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="18" tracking_level="1" version="0" object_id="_13">
|
||||
<Obj>
|
||||
<type>3</type>
|
||||
<id>21</id>
|
||||
<name>AddWeighted</name>
|
||||
<fileName></fileName>
|
||||
<fileDirectory></fileDirectory>
|
||||
<lineNumber>0</lineNumber>
|
||||
<contextFuncName></contextFuncName>
|
||||
<inlineStackInfo>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</inlineStackInfo>
|
||||
<originalName></originalName>
|
||||
<rtlName></rtlName>
|
||||
<coreName></coreName>
|
||||
</Obj>
|
||||
<node_objs>
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
<item>19</item>
|
||||
<item>20</item>
|
||||
</node_objs>
|
||||
</item>
|
||||
</blocks>
|
||||
<edges class_id="19" tracking_level="0" version="0">
|
||||
<count>10</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="20" tracking_level="1" version="0" object_id="_14">
|
||||
<id>23</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>22</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_15">
|
||||
<id>24</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>1</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_16">
|
||||
<id>25</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>2</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_17">
|
||||
<id>26</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>3</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_18">
|
||||
<id>27</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>4</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_19">
|
||||
<id>28</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>5</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_20">
|
||||
<id>29</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>6</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_21">
|
||||
<id>30</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>7</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_22">
|
||||
<id>31</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>8</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
<item class_id_reference="20" object_id="_23">
|
||||
<id>32</id>
|
||||
<edge_type>1</edge_type>
|
||||
<source_obj>9</source_obj>
|
||||
<sink_obj>19</sink_obj>
|
||||
<is_back_edge>0</is_back_edge>
|
||||
</item>
|
||||
</edges>
|
||||
</cdfg>
|
||||
<cdfg_regions class_id="21" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="22" tracking_level="1" version="0" object_id="_24">
|
||||
<mId>1</mId>
|
||||
<mTag>AddWeighted</mTag>
|
||||
<mType>0</mType>
|
||||
<sub_regions>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</sub_regions>
|
||||
<basic_blocks>
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item>21</item>
|
||||
</basic_blocks>
|
||||
<mII>-1</mII>
|
||||
<mDepth>-1</mDepth>
|
||||
<mMinTripCount>-1</mMinTripCount>
|
||||
<mMaxTripCount>-1</mMaxTripCount>
|
||||
<mMinLatency>2077922</mMinLatency>
|
||||
<mMaxLatency>2077922</mMaxLatency>
|
||||
<mIsDfPipe>0</mIsDfPipe>
|
||||
<mDfPipe class_id="-1"></mDfPipe>
|
||||
</item>
|
||||
</cdfg_regions>
|
||||
<fsm class_id="-1"></fsm>
|
||||
<res class_id="-1"></res>
|
||||
<node_label_latency class_id="26" tracking_level="0" version="0">
|
||||
<count>2</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="27" tracking_level="0" version="0">
|
||||
<first>19</first>
|
||||
<second class_id="28" tracking_level="0" version="0">
|
||||
<first>0</first>
|
||||
<second>1</second>
|
||||
</second>
|
||||
</item>
|
||||
<item>
|
||||
<first>20</first>
|
||||
<second>
|
||||
<first>1</first>
|
||||
<second>0</second>
|
||||
</second>
|
||||
</item>
|
||||
</node_label_latency>
|
||||
<bblk_ent_exit class_id="29" tracking_level="0" version="0">
|
||||
<count>1</count>
|
||||
<item_version>0</item_version>
|
||||
<item class_id="30" tracking_level="0" version="0">
|
||||
<first>21</first>
|
||||
<second class_id="31" tracking_level="0" version="0">
|
||||
<first>0</first>
|
||||
<second>1</second>
|
||||
</second>
|
||||
</item>
|
||||
</bblk_ent_exit>
|
||||
<regions class_id="32" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</regions>
|
||||
<dp_fu_nodes class_id="33" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes>
|
||||
<dp_fu_nodes_expression class_id="34" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes_expression>
|
||||
<dp_fu_nodes_module>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes_module>
|
||||
<dp_fu_nodes_io>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_fu_nodes_io>
|
||||
<return_ports>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</return_ports>
|
||||
<dp_mem_port_nodes class_id="35" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_mem_port_nodes>
|
||||
<dp_reg_nodes>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_reg_nodes>
|
||||
<dp_regname_nodes>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_regname_nodes>
|
||||
<dp_reg_phi>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_reg_phi>
|
||||
<dp_regname_phi>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_regname_phi>
|
||||
<dp_port_io_nodes class_id="36" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</dp_port_io_nodes>
|
||||
<port2core class_id="37" tracking_level="0" version="0">
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</port2core>
|
||||
<node2core>
|
||||
<count>0</count>
|
||||
<item_version>0</item_version>
|
||||
</node2core>
|
||||
</syndb>
|
||||
</boost_serialization>
|
||||
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
<stg><name>AddWeighted</name>
|
||||
|
||||
|
||||
<trans_list>
|
||||
|
||||
<trans id="15" from="1" to="2">
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
</trans>
|
||||
</trans_list>
|
||||
|
||||
|
||||
|
||||
<state_list>
|
||||
|
||||
<state id="1" st_id="1">
|
||||
|
||||
<operation id="3" st_id="1" stage="2" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
|
||||
<state id="2" st_id="2">
|
||||
|
||||
<operation id="4" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="10" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:0 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="5" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="11" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:1 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="6" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="12" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:2 call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="7" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="13" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:3 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="8" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="14" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:4 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="9" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="15" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:5 call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="10" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="16" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:6 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="11" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="17" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:7 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="12" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="18" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
|
||||
<![CDATA[
|
||||
:8 call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="13" st_id="2" stage="1" lat="2">
|
||||
<core></core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="19" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
|
||||
<![CDATA[
|
||||
:9 call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="call_ln879"/></StgValue>
|
||||
</operation>
|
||||
|
||||
<operation id="14" st_id="2" stage="1" lat="1">
|
||||
<core>NULL</core>
|
||||
<MemPortIdVec></MemPortIdVec>
|
||||
<condition id="-1">
|
||||
<or_exp><and_exp></and_exp></or_exp>
|
||||
</condition>
|
||||
|
||||
<Node id="20" bw="0">
|
||||
<![CDATA[
|
||||
:10 ret void
|
||||
|
||||
]]></Node>
|
||||
<StgValue><ssdm name="ret_ln880"/></StgValue>
|
||||
</operation>
|
||||
</state>
|
||||
</state_list>
|
||||
|
||||
|
||||
<ports>
|
||||
</ports>
|
||||
|
||||
|
||||
<dataflows>
|
||||
</dataflows>
|
||||
|
||||
|
||||
</stg>
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
set moduleName AddWeighted
|
||||
set isTopModule 0
|
||||
set isTaskLevelControl 1
|
||||
set isCombinational 0
|
||||
set isDatapathOnly 0
|
||||
set isFreeRunPipelineModule 0
|
||||
set isPipelined 0
|
||||
set pipeline_type none
|
||||
set FunctionProtocol ap_ctrl_hs
|
||||
set isOneStateSeq 0
|
||||
set ProfileFlag 0
|
||||
set StallSigGenFlag 0
|
||||
set isEnableWaveformDebug 1
|
||||
set C_modelName {AddWeighted}
|
||||
set C_modelType { void 0 }
|
||||
set C_modelArgList {
|
||||
{ src1_data_stream_0_V int 8 regular {fifo 0 volatile } }
|
||||
{ src1_data_stream_1_V int 8 regular {fifo 0 volatile } }
|
||||
{ src1_data_stream_2_V int 8 regular {fifo 0 volatile } }
|
||||
{ src2_data_stream_0_V int 8 regular {fifo 0 volatile } }
|
||||
{ src2_data_stream_1_V int 8 regular {fifo 0 volatile } }
|
||||
{ src2_data_stream_2_V int 8 regular {fifo 0 volatile } }
|
||||
{ dst_data_stream_0_V int 8 regular {fifo 1 volatile } }
|
||||
{ dst_data_stream_1_V int 8 regular {fifo 1 volatile } }
|
||||
{ dst_data_stream_2_V int 8 regular {fifo 1 volatile } }
|
||||
}
|
||||
set C_modelArgMapList {[
|
||||
{ "Name" : "src1_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "src1_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "src1_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "src2_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "src2_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "src2_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "dst_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "dst_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "dst_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ]}
|
||||
# RTL Port declarations:
|
||||
set portNum 34
|
||||
set portList {
|
||||
{ ap_clk sc_in sc_logic 1 clock -1 }
|
||||
{ ap_rst sc_in sc_logic 1 reset -1 active_high_sync }
|
||||
{ ap_start sc_in sc_logic 1 start -1 }
|
||||
{ ap_done sc_out sc_logic 1 predone -1 }
|
||||
{ ap_continue sc_in sc_logic 1 continue -1 }
|
||||
{ ap_idle sc_out sc_logic 1 done -1 }
|
||||
{ ap_ready sc_out sc_logic 1 ready -1 }
|
||||
{ src1_data_stream_0_V_dout sc_in sc_lv 8 signal 0 }
|
||||
{ src1_data_stream_0_V_empty_n sc_in sc_logic 1 signal 0 }
|
||||
{ src1_data_stream_0_V_read sc_out sc_logic 1 signal 0 }
|
||||
{ src1_data_stream_1_V_dout sc_in sc_lv 8 signal 1 }
|
||||
{ src1_data_stream_1_V_empty_n sc_in sc_logic 1 signal 1 }
|
||||
{ src1_data_stream_1_V_read sc_out sc_logic 1 signal 1 }
|
||||
{ src1_data_stream_2_V_dout sc_in sc_lv 8 signal 2 }
|
||||
{ src1_data_stream_2_V_empty_n sc_in sc_logic 1 signal 2 }
|
||||
{ src1_data_stream_2_V_read sc_out sc_logic 1 signal 2 }
|
||||
{ src2_data_stream_0_V_dout sc_in sc_lv 8 signal 3 }
|
||||
{ src2_data_stream_0_V_empty_n sc_in sc_logic 1 signal 3 }
|
||||
{ src2_data_stream_0_V_read sc_out sc_logic 1 signal 3 }
|
||||
{ src2_data_stream_1_V_dout sc_in sc_lv 8 signal 4 }
|
||||
{ src2_data_stream_1_V_empty_n sc_in sc_logic 1 signal 4 }
|
||||
{ src2_data_stream_1_V_read sc_out sc_logic 1 signal 4 }
|
||||
{ src2_data_stream_2_V_dout sc_in sc_lv 8 signal 5 }
|
||||
{ src2_data_stream_2_V_empty_n sc_in sc_logic 1 signal 5 }
|
||||
{ src2_data_stream_2_V_read sc_out sc_logic 1 signal 5 }
|
||||
{ dst_data_stream_0_V_din sc_out sc_lv 8 signal 6 }
|
||||
{ dst_data_stream_0_V_full_n sc_in sc_logic 1 signal 6 }
|
||||
{ dst_data_stream_0_V_write sc_out sc_logic 1 signal 6 }
|
||||
{ dst_data_stream_1_V_din sc_out sc_lv 8 signal 7 }
|
||||
{ dst_data_stream_1_V_full_n sc_in sc_logic 1 signal 7 }
|
||||
{ dst_data_stream_1_V_write sc_out sc_logic 1 signal 7 }
|
||||
{ dst_data_stream_2_V_din sc_out sc_lv 8 signal 8 }
|
||||
{ dst_data_stream_2_V_full_n sc_in sc_logic 1 signal 8 }
|
||||
{ dst_data_stream_2_V_write sc_out sc_logic 1 signal 8 }
|
||||
}
|
||||
set NewPortList {[
|
||||
{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
|
||||
{ "name": "ap_rst", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst", "role": "default" }} ,
|
||||
{ "name": "ap_start", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "start", "bundle":{"name": "ap_start", "role": "default" }} ,
|
||||
{ "name": "ap_done", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "predone", "bundle":{"name": "ap_done", "role": "default" }} ,
|
||||
{ "name": "ap_continue", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "continue", "bundle":{"name": "ap_continue", "role": "default" }} ,
|
||||
{ "name": "ap_idle", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "done", "bundle":{"name": "ap_idle", "role": "default" }} ,
|
||||
{ "name": "ap_ready", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "ready", "bundle":{"name": "ap_ready", "role": "default" }} ,
|
||||
{ "name": "src1_data_stream_0_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "dout" }} ,
|
||||
{ "name": "src1_data_stream_0_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "empty_n" }} ,
|
||||
{ "name": "src1_data_stream_0_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "read" }} ,
|
||||
{ "name": "src1_data_stream_1_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "dout" }} ,
|
||||
{ "name": "src1_data_stream_1_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "empty_n" }} ,
|
||||
{ "name": "src1_data_stream_1_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "read" }} ,
|
||||
{ "name": "src1_data_stream_2_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "dout" }} ,
|
||||
{ "name": "src1_data_stream_2_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "empty_n" }} ,
|
||||
{ "name": "src1_data_stream_2_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "read" }} ,
|
||||
{ "name": "src2_data_stream_0_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "dout" }} ,
|
||||
{ "name": "src2_data_stream_0_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "empty_n" }} ,
|
||||
{ "name": "src2_data_stream_0_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "read" }} ,
|
||||
{ "name": "src2_data_stream_1_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "dout" }} ,
|
||||
{ "name": "src2_data_stream_1_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "empty_n" }} ,
|
||||
{ "name": "src2_data_stream_1_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "read" }} ,
|
||||
{ "name": "src2_data_stream_2_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "dout" }} ,
|
||||
{ "name": "src2_data_stream_2_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "empty_n" }} ,
|
||||
{ "name": "src2_data_stream_2_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "read" }} ,
|
||||
{ "name": "dst_data_stream_0_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "din" }} ,
|
||||
{ "name": "dst_data_stream_0_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "full_n" }} ,
|
||||
{ "name": "dst_data_stream_0_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "write" }} ,
|
||||
{ "name": "dst_data_stream_1_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "din" }} ,
|
||||
{ "name": "dst_data_stream_1_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "full_n" }} ,
|
||||
{ "name": "dst_data_stream_1_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "write" }} ,
|
||||
{ "name": "dst_data_stream_2_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "din" }} ,
|
||||
{ "name": "dst_data_stream_2_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "full_n" }} ,
|
||||
{ "name": "dst_data_stream_2_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "write" }} ]}
|
||||
|
||||
set RtlHierarchyInfo {[
|
||||
{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "", "Child" : ["1"],
|
||||
"CDFG" : "AddWeighted",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "1", "ap_idle" : "1",
|
||||
"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "0",
|
||||
"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2077922", "EstimateLatencyMax" : "2077922",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "0",
|
||||
"ClockEnable" : "0",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "1",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"WaitState" : [
|
||||
{"State" : "ap_ST_fsm_state2", "FSM" : "ap_CS_fsm", "SubInstance" : "grp_arithm_pro_fu_32"}],
|
||||
"Port" : [
|
||||
{"Name" : "src1_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_0_V"}]},
|
||||
{"Name" : "src1_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_1_V"}]},
|
||||
{"Name" : "src1_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_2_V"}]},
|
||||
{"Name" : "src2_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_0_V"}]},
|
||||
{"Name" : "src2_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_1_V"}]},
|
||||
{"Name" : "src2_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_2_V"}]},
|
||||
{"Name" : "dst_data_stream_0_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_0_V"}]},
|
||||
{"Name" : "dst_data_stream_1_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_1_V"}]},
|
||||
{"Name" : "dst_data_stream_2_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"SubConnect" : [
|
||||
{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_2_V"}]}]},
|
||||
{"ID" : "1", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.grp_arithm_pro_fu_32", "Parent" : "0",
|
||||
"CDFG" : "arithm_pro",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "0", "ap_idle" : "1",
|
||||
"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "0",
|
||||
"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2077921", "EstimateLatencyMax" : "2077921",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "0",
|
||||
"ClockEnable" : "0",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "0",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "src1_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src1_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "src1_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src1_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "src1_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src1_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "src2_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src2_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "src2_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src2_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "src2_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "src2_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "dst_data_stream_0_V", "Type" : "Fifo", "Direction" : "O",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "dst_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "dst_data_stream_1_V", "Type" : "Fifo", "Direction" : "O",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "dst_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "dst_data_stream_2_V", "Type" : "Fifo", "Direction" : "O",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "dst_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]}]}]}
|
||||
|
||||
|
||||
set ArgLastReadFirstWriteLatency {
|
||||
AddWeighted {
|
||||
src1_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
|
||||
src1_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
|
||||
src1_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
|
||||
dst_data_stream_0_V {Type O LastRead -1 FirstWrite 4}
|
||||
dst_data_stream_1_V {Type O LastRead -1 FirstWrite 4}
|
||||
dst_data_stream_2_V {Type O LastRead -1 FirstWrite 4}}
|
||||
arithm_pro {
|
||||
src1_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
|
||||
src1_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
|
||||
src1_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
|
||||
src2_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
|
||||
dst_data_stream_0_V {Type O LastRead -1 FirstWrite 4}
|
||||
dst_data_stream_1_V {Type O LastRead -1 FirstWrite 4}
|
||||
dst_data_stream_2_V {Type O LastRead -1 FirstWrite 4}}}
|
||||
|
||||
set hasDtUnsupportedChannel 0
|
||||
|
||||
set PerformanceInfo {[
|
||||
{"Name" : "Latency", "Min" : "2077922", "Max" : "2077922"}
|
||||
, {"Name" : "Interval", "Min" : "2077922", "Max" : "2077922"}
|
||||
]}
|
||||
|
||||
set PipelineEnableSignalInfo {[
|
||||
]}
|
||||
|
||||
set Spec2ImplPortList {
|
||||
src1_data_stream_0_V { ap_fifo { { src1_data_stream_0_V_dout fifo_data 0 8 } { src1_data_stream_0_V_empty_n fifo_status 0 1 } { src1_data_stream_0_V_read fifo_update 1 1 } } }
|
||||
src1_data_stream_1_V { ap_fifo { { src1_data_stream_1_V_dout fifo_data 0 8 } { src1_data_stream_1_V_empty_n fifo_status 0 1 } { src1_data_stream_1_V_read fifo_update 1 1 } } }
|
||||
src1_data_stream_2_V { ap_fifo { { src1_data_stream_2_V_dout fifo_data 0 8 } { src1_data_stream_2_V_empty_n fifo_status 0 1 } { src1_data_stream_2_V_read fifo_update 1 1 } } }
|
||||
src2_data_stream_0_V { ap_fifo { { src2_data_stream_0_V_dout fifo_data 0 8 } { src2_data_stream_0_V_empty_n fifo_status 0 1 } { src2_data_stream_0_V_read fifo_update 1 1 } } }
|
||||
src2_data_stream_1_V { ap_fifo { { src2_data_stream_1_V_dout fifo_data 0 8 } { src2_data_stream_1_V_empty_n fifo_status 0 1 } { src2_data_stream_1_V_read fifo_update 1 1 } } }
|
||||
src2_data_stream_2_V { ap_fifo { { src2_data_stream_2_V_dout fifo_data 0 8 } { src2_data_stream_2_V_empty_n fifo_status 0 1 } { src2_data_stream_2_V_read fifo_update 1 1 } } }
|
||||
dst_data_stream_0_V { ap_fifo { { dst_data_stream_0_V_din fifo_data 1 8 } { dst_data_stream_0_V_full_n fifo_status 0 1 } { dst_data_stream_0_V_write fifo_update 1 1 } } }
|
||||
dst_data_stream_1_V { ap_fifo { { dst_data_stream_1_V_din fifo_data 1 8 } { dst_data_stream_1_V_full_n fifo_status 0 1 } { dst_data_stream_1_V_write fifo_update 1 1 } } }
|
||||
dst_data_stream_2_V { ap_fifo { { dst_data_stream_2_V_din fifo_data 1 8 } { dst_data_stream_2_V_full_n fifo_status 0 1 } { dst_data_stream_2_V_write fifo_update 1 1 } } }
|
||||
}
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
|
||||
|
||||
================================================================
|
||||
== Vivado HLS Report for 'AddWeighted'
|
||||
================================================================
|
||||
* Date: Tue Feb 7 10:18:34 2023
|
||||
|
||||
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
|
||||
* Project: edge_detect
|
||||
* Solution: solution1
|
||||
* Product family: zynq
|
||||
* Target device: xc7z020-clg400-1
|
||||
|
||||
|
||||
================================================================
|
||||
== Performance Estimates
|
||||
================================================================
|
||||
+ Timing (ns):
|
||||
* Summary:
|
||||
+--------+-------+----------+------------+
|
||||
| Clock | Target| Estimated| Uncertainty|
|
||||
+--------+-------+----------+------------+
|
||||
|ap_clk | 6.70| 4.846| 0.84|
|
||||
+--------+-------+----------+------------+
|
||||
|
||||
+ Latency (clock cycles):
|
||||
* Summary:
|
||||
+---------+---------+---------+---------+---------+
|
||||
| Latency | Interval | Pipeline|
|
||||
| min | max | min | max | Type |
|
||||
+---------+---------+---------+---------+---------+
|
||||
| 2077922| 2077922| 2077922| 2077922| none |
|
||||
+---------+---------+---------+---------+---------+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
| | | Latency | Interval | Pipeline|
|
||||
| Instance | Module | min | max | min | max | Type |
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
|grp_arithm_pro_fu_32 |arithm_pro | 2077921| 2077921| 2077921| 2077921| none |
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
|
||||
* Loop:
|
||||
N/A
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Synthesis Manager
|
||||
============================================================
|
||||
InlineROM: 1
|
||||
ExposeGlobal: 0
|
||||
============================================================
|
||||
+ Verbose Summary: CDFG Model
|
||||
============================================================
|
||||
IsTopModel: 0
|
||||
ResetActiveHigh: 1
|
||||
IsCombinational: 2
|
||||
IsDatapathOnly: 0
|
||||
HasWiredReturn: 1
|
||||
HasMFsm: 0
|
||||
HasVarLatency: 1
|
||||
IsPipeline: 0
|
||||
IsRtlPipelined: 0
|
||||
IsInstanceOverlapped: 0
|
||||
IsDontTouch: 0
|
||||
HasImplIP: 0
|
||||
IsGatedGlobalClock: 0
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Schedule
|
||||
============================================================
|
||||
* Number of FSM states : 2
|
||||
* Pipeline : 0
|
||||
* Dataflow Pipeline: 0
|
||||
|
||||
* FSM state transitions:
|
||||
1 --> 2
|
||||
2 -->
|
||||
|
||||
* FSM state operations:
|
||||
|
||||
State 1 <SV = 0> <Delay = 0.00>
|
||||
ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 2 <SV = 1> <Delay = 0.00>
|
||||
ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Binding
|
||||
============================================================
|
||||
STG Binding:
|
||||
---------------- STG Properties BEGIN ----------------
|
||||
- Is combinational: 0
|
||||
- Is one-state seq: 0
|
||||
- Is datapath-only: 0
|
||||
- Is pipelined: 0
|
||||
- Is top level: 0
|
||||
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
|
||||
Port [ src1_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src1_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src1_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
---------------- STG Properties END ------------------
|
||||
|
||||
---------------- Datapath Model BEGIN ----------------
|
||||
|
||||
<LifeTime>
|
||||
<method=bitvector/>
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
call_ln879 (call ) [ 000]
|
||||
ret_ln880 (ret ) [ 000]
|
||||
</LifeTime>
|
||||
|
||||
<model>
|
||||
|
||||
<comp_list>
|
||||
<comp id="0" class="1000" name="src1_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="2" class="1000" name="src1_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="4" class="1000" name="src1_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="6" class="1000" name="src2_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="8" class="1000" name="src2_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="10" class="1000" name="src2_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="12" class="1000" name="dst_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="14" class="1000" name="dst_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="16" class="1000" name="dst_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="18" class="1001" name="const_18">
|
||||
<pin_list>
|
||||
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="arithm_pro"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="20" class="1001" name="const_20">
|
||||
<pin_list>
|
||||
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="22" class="1001" name="const_22">
|
||||
<pin_list>
|
||||
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="24" class="1001" name="const_24">
|
||||
<pin_list>
|
||||
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="26" class="1001" name="const_26">
|
||||
<pin_list>
|
||||
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="p_str"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="28" class="1001" name="const_28">
|
||||
<pin_list>
|
||||
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="30" class="1001" name="const_30">
|
||||
<pin_list>
|
||||
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="32" class="1004" name="grp_arithm_pro_fu_32">
|
||||
<pin_list>
|
||||
<pin id="33" dir="0" index="0" bw="0" slack="0"/>
|
||||
<pin id="34" dir="0" index="1" bw="8" slack="0"/>
|
||||
<pin id="35" dir="0" index="2" bw="8" slack="0"/>
|
||||
<pin id="36" dir="0" index="3" bw="8" slack="0"/>
|
||||
<pin id="37" dir="0" index="4" bw="8" slack="0"/>
|
||||
<pin id="38" dir="0" index="5" bw="8" slack="0"/>
|
||||
<pin id="39" dir="0" index="6" bw="8" slack="0"/>
|
||||
<pin id="40" dir="0" index="7" bw="8" slack="0"/>
|
||||
<pin id="41" dir="0" index="8" bw="8" slack="0"/>
|
||||
<pin id="42" dir="0" index="9" bw="8" slack="0"/>
|
||||
<pin id="43" dir="1" index="10" bw="0" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<opcode="call(48) " fcode="call"/>
|
||||
<opset="call_ln879/1 "/>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
</comp_list>
|
||||
|
||||
<net_list>
|
||||
<net id="44"><net_src comp="18" pin="0"/><net_sink comp="32" pin=0"/></net>
|
||||
|
||||
<net id="45"><net_src comp="0" pin="0"/><net_sink comp="32" pin=1"/></net>
|
||||
|
||||
<net id="46"><net_src comp="2" pin="0"/><net_sink comp="32" pin=2"/></net>
|
||||
|
||||
<net id="47"><net_src comp="4" pin="0"/><net_sink comp="32" pin=3"/></net>
|
||||
|
||||
<net id="48"><net_src comp="6" pin="0"/><net_sink comp="32" pin=4"/></net>
|
||||
|
||||
<net id="49"><net_src comp="8" pin="0"/><net_sink comp="32" pin=5"/></net>
|
||||
|
||||
<net id="50"><net_src comp="10" pin="0"/><net_sink comp="32" pin=6"/></net>
|
||||
|
||||
<net id="51"><net_src comp="12" pin="0"/><net_sink comp="32" pin=7"/></net>
|
||||
|
||||
<net id="52"><net_src comp="14" pin="0"/><net_sink comp="32" pin=8"/></net>
|
||||
|
||||
<net id="53"><net_src comp="16" pin="0"/><net_sink comp="32" pin=9"/></net>
|
||||
|
||||
</net_list>
|
||||
|
||||
</model>
|
||||
---------------- Datapath Model END ------------------
|
||||
|
||||
* FSMD analyzer results:
|
||||
- Output states:
|
||||
Port: dst_data_stream_0_V | {1 2 }
|
||||
Port: dst_data_stream_1_V | {1 2 }
|
||||
Port: dst_data_stream_2_V | {1 2 }
|
||||
- Input state :
|
||||
Port: AddWeighted : src1_data_stream_0_V | {1 2 }
|
||||
Port: AddWeighted : src1_data_stream_1_V | {1 2 }
|
||||
Port: AddWeighted : src1_data_stream_2_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_0_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_1_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_2_V | {1 2 }
|
||||
- Chain level:
|
||||
State 1
|
||||
State 2
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Datapath Resource usage
|
||||
============================================================
|
||||
|
||||
* Functional unit list:
|
||||
|----------|----------------------|---------|---------|
|
||||
| Operation| Functional Unit | FF | LUT |
|
||||
|----------|----------------------|---------|---------|
|
||||
| call | grp_arithm_pro_fu_32 | 73 | 166 |
|
||||
|----------|----------------------|---------|---------|
|
||||
| Total | | 73 | 166 |
|
||||
|----------|----------------------|---------|---------|
|
||||
|
||||
Memories:
|
||||
N/A
|
||||
|
||||
* Register list:
|
||||
N/A
|
||||
|
||||
* Multiplexer (MUX) list:
|
||||
|--------|------|------|------|--------|
|
||||
| Comp | Pin | Size | BW | S x BW |
|
||||
|--------|------|------|------|--------|
|
||||
| Total | | | | 0 |
|
||||
|--------|------|------|------|--------|
|
||||
|
||||
|
||||
|
||||
* Summary:
|
||||
+-----------+--------+--------+
|
||||
| | FF | LUT |
|
||||
+-----------+--------+--------+
|
||||
| Function | 73 | 166 |
|
||||
| Memory | - | - |
|
||||
|Multiplexer| - | - |
|
||||
| Register | - | - |
|
||||
+-----------+--------+--------+
|
||||
| Total | 73 | 166 |
|
||||
+-----------+--------+--------+
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AddWeighted'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:34 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 4.846, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2077922, 2077922, 2077922, 2077922, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
<column name="grp_arithm_pro_fu_32">arithm_pro, 2077921, 2077921, 2077921, 2077921, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
|
|
@ -0,0 +1,519 @@
|
|||
|
||||
|
||||
================================================================
|
||||
== Vivado HLS Report for 'AddWeighted'
|
||||
================================================================
|
||||
* Date: Tue Feb 7 10:18:47 2023
|
||||
|
||||
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
|
||||
* Project: edge_detect
|
||||
* Solution: solution1
|
||||
* Product family: zynq
|
||||
* Target device: xc7z020-clg400-1
|
||||
|
||||
|
||||
================================================================
|
||||
== Performance Estimates
|
||||
================================================================
|
||||
+ Timing (ns):
|
||||
* Summary:
|
||||
+--------+-------+----------+------------+
|
||||
| Clock | Target| Estimated| Uncertainty|
|
||||
+--------+-------+----------+------------+
|
||||
|ap_clk | 6.70| 4.846| 0.84|
|
||||
+--------+-------+----------+------------+
|
||||
|
||||
+ Latency (clock cycles):
|
||||
* Summary:
|
||||
+---------+---------+---------+---------+---------+
|
||||
| Latency | Interval | Pipeline|
|
||||
| min | max | min | max | Type |
|
||||
+---------+---------+---------+---------+---------+
|
||||
| 2077922| 2077922| 2077922| 2077922| none |
|
||||
+---------+---------+---------+---------+---------+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
| | | Latency | Interval | Pipeline|
|
||||
| Instance | Module | min | max | min | max | Type |
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
|grp_arithm_pro_fu_32 |arithm_pro | 2077921| 2077921| 2077921| 2077921| none |
|
||||
+----------------------+------------+---------+---------+---------+---------+---------+
|
||||
|
||||
* Loop:
|
||||
N/A
|
||||
|
||||
|
||||
|
||||
================================================================
|
||||
== Utilization Estimates
|
||||
================================================================
|
||||
* Summary:
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
| Name | BRAM_18K| DSP48E| FF | LUT | URAM|
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
|DSP | -| -| -| -| -|
|
||||
|Expression | -| -| 0| 2| -|
|
||||
|FIFO | -| -| -| -| -|
|
||||
|Instance | -| -| 69| 320| -|
|
||||
|Memory | -| -| -| -| -|
|
||||
|Multiplexer | -| -| -| 105| -|
|
||||
|Register | -| -| 4| -| -|
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
|Total | 0| 0| 73| 427| 0|
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
|Available | 280| 220| 106400| 53200| 0|
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
|Utilization (%) | 0| 0| ~0 | ~0 | 0|
|
||||
+-----------------+---------+-------+--------+-------+-----+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
+----------------------+------------+---------+-------+----+-----+-----+
|
||||
| Instance | Module | BRAM_18K| DSP48E| FF | LUT | URAM|
|
||||
+----------------------+------------+---------+-------+----+-----+-----+
|
||||
|grp_arithm_pro_fu_32 |arithm_pro | 0| 0| 69| 320| 0|
|
||||
+----------------------+------------+---------+-------+----+-----+-----+
|
||||
|Total | | 0| 0| 69| 320| 0|
|
||||
+----------------------+------------+---------+-------+----+-----+-----+
|
||||
|
||||
* DSP48E:
|
||||
N/A
|
||||
|
||||
* Memory:
|
||||
N/A
|
||||
|
||||
* FIFO:
|
||||
N/A
|
||||
|
||||
* Expression:
|
||||
+-----------------+----------+-------+---+----+------------+------------+
|
||||
| Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
|
||||
+-----------------+----------+-------+---+----+------------+------------+
|
||||
|ap_block_state1 | or | 0| 0| 2| 1| 1|
|
||||
+-----------------+----------+-------+---+----+------------+------------+
|
||||
|Total | | 0| 0| 2| 1| 1|
|
||||
+-----------------+----------+-------+---+----+------------+------------+
|
||||
|
||||
* Multiplexer:
|
||||
+---------------------------+----+-----------+-----+-----------+
|
||||
| Name | LUT| Input Size| Bits| Total Bits|
|
||||
+---------------------------+----+-----------+-----+-----------+
|
||||
|ap_NS_fsm | 15| 3| 1| 3|
|
||||
|ap_done | 9| 2| 1| 2|
|
||||
|dst_data_stream_0_V_write | 9| 2| 1| 2|
|
||||
|dst_data_stream_1_V_write | 9| 2| 1| 2|
|
||||
|dst_data_stream_2_V_write | 9| 2| 1| 2|
|
||||
|src1_data_stream_0_V_read | 9| 2| 1| 2|
|
||||
|src1_data_stream_1_V_read | 9| 2| 1| 2|
|
||||
|src1_data_stream_2_V_read | 9| 2| 1| 2|
|
||||
|src2_data_stream_0_V_read | 9| 2| 1| 2|
|
||||
|src2_data_stream_1_V_read | 9| 2| 1| 2|
|
||||
|src2_data_stream_2_V_read | 9| 2| 1| 2|
|
||||
+---------------------------+----+-----------+-----+-----------+
|
||||
|Total | 105| 23| 11| 23|
|
||||
+---------------------------+----+-----------+-----+-----------+
|
||||
|
||||
* Register:
|
||||
+-----------------------------------+---+----+-----+-----------+
|
||||
| Name | FF| LUT| Bits| Const Bits|
|
||||
+-----------------------------------+---+----+-----+-----------+
|
||||
|ap_CS_fsm | 2| 0| 2| 0|
|
||||
|ap_done_reg | 1| 0| 1| 0|
|
||||
|grp_arithm_pro_fu_32_ap_start_reg | 1| 0| 1| 0|
|
||||
+-----------------------------------+---+----+-----+-----------+
|
||||
|Total | 4| 0| 4| 0|
|
||||
+-----------------------------------+---+----+-----+-----------+
|
||||
|
||||
|
||||
|
||||
================================================================
|
||||
== Interface
|
||||
================================================================
|
||||
* Summary:
|
||||
+------------------------------+-----+-----+------------+----------------------+--------------+
|
||||
| RTL Ports | Dir | Bits| Protocol | Source Object | C Type |
|
||||
+------------------------------+-----+-----+------------+----------------------+--------------+
|
||||
|ap_clk | in | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_rst | in | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_start | in | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_done | out | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_continue | in | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_idle | out | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|ap_ready | out | 1| ap_ctrl_hs | AddWeighted | return value |
|
||||
|src1_data_stream_0_V_dout | in | 8| ap_fifo | src1_data_stream_0_V | pointer |
|
||||
|src1_data_stream_0_V_empty_n | in | 1| ap_fifo | src1_data_stream_0_V | pointer |
|
||||
|src1_data_stream_0_V_read | out | 1| ap_fifo | src1_data_stream_0_V | pointer |
|
||||
|src1_data_stream_1_V_dout | in | 8| ap_fifo | src1_data_stream_1_V | pointer |
|
||||
|src1_data_stream_1_V_empty_n | in | 1| ap_fifo | src1_data_stream_1_V | pointer |
|
||||
|src1_data_stream_1_V_read | out | 1| ap_fifo | src1_data_stream_1_V | pointer |
|
||||
|src1_data_stream_2_V_dout | in | 8| ap_fifo | src1_data_stream_2_V | pointer |
|
||||
|src1_data_stream_2_V_empty_n | in | 1| ap_fifo | src1_data_stream_2_V | pointer |
|
||||
|src1_data_stream_2_V_read | out | 1| ap_fifo | src1_data_stream_2_V | pointer |
|
||||
|src2_data_stream_0_V_dout | in | 8| ap_fifo | src2_data_stream_0_V | pointer |
|
||||
|src2_data_stream_0_V_empty_n | in | 1| ap_fifo | src2_data_stream_0_V | pointer |
|
||||
|src2_data_stream_0_V_read | out | 1| ap_fifo | src2_data_stream_0_V | pointer |
|
||||
|src2_data_stream_1_V_dout | in | 8| ap_fifo | src2_data_stream_1_V | pointer |
|
||||
|src2_data_stream_1_V_empty_n | in | 1| ap_fifo | src2_data_stream_1_V | pointer |
|
||||
|src2_data_stream_1_V_read | out | 1| ap_fifo | src2_data_stream_1_V | pointer |
|
||||
|src2_data_stream_2_V_dout | in | 8| ap_fifo | src2_data_stream_2_V | pointer |
|
||||
|src2_data_stream_2_V_empty_n | in | 1| ap_fifo | src2_data_stream_2_V | pointer |
|
||||
|src2_data_stream_2_V_read | out | 1| ap_fifo | src2_data_stream_2_V | pointer |
|
||||
|dst_data_stream_0_V_din | out | 8| ap_fifo | dst_data_stream_0_V | pointer |
|
||||
|dst_data_stream_0_V_full_n | in | 1| ap_fifo | dst_data_stream_0_V | pointer |
|
||||
|dst_data_stream_0_V_write | out | 1| ap_fifo | dst_data_stream_0_V | pointer |
|
||||
|dst_data_stream_1_V_din | out | 8| ap_fifo | dst_data_stream_1_V | pointer |
|
||||
|dst_data_stream_1_V_full_n | in | 1| ap_fifo | dst_data_stream_1_V | pointer |
|
||||
|dst_data_stream_1_V_write | out | 1| ap_fifo | dst_data_stream_1_V | pointer |
|
||||
|dst_data_stream_2_V_din | out | 8| ap_fifo | dst_data_stream_2_V | pointer |
|
||||
|dst_data_stream_2_V_full_n | in | 1| ap_fifo | dst_data_stream_2_V | pointer |
|
||||
|dst_data_stream_2_V_write | out | 1| ap_fifo | dst_data_stream_2_V | pointer |
|
||||
+------------------------------+-----+-----+------------+----------------------+--------------+
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Synthesis Manager
|
||||
============================================================
|
||||
InlineROM: 1
|
||||
ExposeGlobal: 0
|
||||
============================================================
|
||||
+ Verbose Summary: CDFG Model
|
||||
============================================================
|
||||
IsTopModel: 0
|
||||
ResetActiveHigh: 1
|
||||
IsCombinational: 2
|
||||
IsDatapathOnly: 0
|
||||
HasWiredReturn: 1
|
||||
HasMFsm: 0
|
||||
HasVarLatency: 1
|
||||
IsPipeline: 0
|
||||
IsRtlPipelined: 0
|
||||
IsInstanceOverlapped: 0
|
||||
IsDontTouch: 0
|
||||
HasImplIP: 0
|
||||
IsGatedGlobalClock: 0
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Schedule
|
||||
============================================================
|
||||
* Number of FSM states : 2
|
||||
* Pipeline : 0
|
||||
* Dataflow Pipeline: 0
|
||||
|
||||
* FSM state transitions:
|
||||
1 --> 2
|
||||
2 -->
|
||||
|
||||
* FSM state operations:
|
||||
|
||||
State 1 <SV = 0> <Delay = 0.00>
|
||||
ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 2 <SV = 1> <Delay = 0.00>
|
||||
ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Binding
|
||||
============================================================
|
||||
STG Binding:
|
||||
---------------- STG Properties BEGIN ----------------
|
||||
- Is combinational: 0
|
||||
- Is one-state seq: 0
|
||||
- Is datapath-only: 0
|
||||
- Is pipelined: 0
|
||||
- Is top level: 0
|
||||
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
|
||||
Port [ src1_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src1_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src1_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ src2_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
Port [ dst_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
|
||||
---------------- STG Properties END ------------------
|
||||
|
||||
---------------- Datapath Model BEGIN ----------------
|
||||
|
||||
<LifeTime>
|
||||
<method=bitvector/>
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
specinterface_ln0 (specinterface) [ 000]
|
||||
call_ln879 (call ) [ 000]
|
||||
ret_ln880 (ret ) [ 000]
|
||||
</LifeTime>
|
||||
|
||||
<model>
|
||||
|
||||
<comp_list>
|
||||
<comp id="0" class="1000" name="src1_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="2" class="1000" name="src1_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="4" class="1000" name="src1_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="6" class="1000" name="src2_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="8" class="1000" name="src2_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="10" class="1000" name="src2_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="12" class="1000" name="dst_data_stream_0_V">
|
||||
<pin_list>
|
||||
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="14" class="1000" name="dst_data_stream_1_V">
|
||||
<pin_list>
|
||||
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="16" class="1000" name="dst_data_stream_2_V">
|
||||
<pin_list>
|
||||
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="18" class="1001" name="const_18">
|
||||
<pin_list>
|
||||
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="arithm_pro"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="20" class="1001" name="const_20">
|
||||
<pin_list>
|
||||
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="22" class="1001" name="const_22">
|
||||
<pin_list>
|
||||
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="24" class="1001" name="const_24">
|
||||
<pin_list>
|
||||
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="26" class="1001" name="const_26">
|
||||
<pin_list>
|
||||
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name="p_str"/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="28" class="1001" name="const_28">
|
||||
<pin_list>
|
||||
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="30" class="1001" name="const_30">
|
||||
<pin_list>
|
||||
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<StgValue><ssdm name=""/></StgValue>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
<comp id="32" class="1004" name="grp_arithm_pro_fu_32">
|
||||
<pin_list>
|
||||
<pin id="33" dir="0" index="0" bw="0" slack="0"/>
|
||||
<pin id="34" dir="0" index="1" bw="8" slack="0"/>
|
||||
<pin id="35" dir="0" index="2" bw="8" slack="0"/>
|
||||
<pin id="36" dir="0" index="3" bw="8" slack="0"/>
|
||||
<pin id="37" dir="0" index="4" bw="8" slack="0"/>
|
||||
<pin id="38" dir="0" index="5" bw="8" slack="0"/>
|
||||
<pin id="39" dir="0" index="6" bw="8" slack="0"/>
|
||||
<pin id="40" dir="0" index="7" bw="8" slack="0"/>
|
||||
<pin id="41" dir="0" index="8" bw="8" slack="0"/>
|
||||
<pin id="42" dir="0" index="9" bw="8" slack="0"/>
|
||||
<pin id="43" dir="1" index="10" bw="0" slack="2147483647"/>
|
||||
</pin_list>
|
||||
<bind>
|
||||
<opcode="call(48) " fcode="call"/>
|
||||
<opset="call_ln879/1 "/>
|
||||
</bind>
|
||||
</comp>
|
||||
|
||||
</comp_list>
|
||||
|
||||
<net_list>
|
||||
<net id="44"><net_src comp="18" pin="0"/><net_sink comp="32" pin=0"/></net>
|
||||
|
||||
<net id="45"><net_src comp="0" pin="0"/><net_sink comp="32" pin=1"/></net>
|
||||
|
||||
<net id="46"><net_src comp="2" pin="0"/><net_sink comp="32" pin=2"/></net>
|
||||
|
||||
<net id="47"><net_src comp="4" pin="0"/><net_sink comp="32" pin=3"/></net>
|
||||
|
||||
<net id="48"><net_src comp="6" pin="0"/><net_sink comp="32" pin=4"/></net>
|
||||
|
||||
<net id="49"><net_src comp="8" pin="0"/><net_sink comp="32" pin=5"/></net>
|
||||
|
||||
<net id="50"><net_src comp="10" pin="0"/><net_sink comp="32" pin=6"/></net>
|
||||
|
||||
<net id="51"><net_src comp="12" pin="0"/><net_sink comp="32" pin=7"/></net>
|
||||
|
||||
<net id="52"><net_src comp="14" pin="0"/><net_sink comp="32" pin=8"/></net>
|
||||
|
||||
<net id="53"><net_src comp="16" pin="0"/><net_sink comp="32" pin=9"/></net>
|
||||
|
||||
</net_list>
|
||||
|
||||
</model>
|
||||
---------------- Datapath Model END ------------------
|
||||
|
||||
* FSMD analyzer results:
|
||||
- Output states:
|
||||
Port: dst_data_stream_0_V | {1 2 }
|
||||
Port: dst_data_stream_1_V | {1 2 }
|
||||
Port: dst_data_stream_2_V | {1 2 }
|
||||
- Input state :
|
||||
Port: AddWeighted : src1_data_stream_0_V | {1 2 }
|
||||
Port: AddWeighted : src1_data_stream_1_V | {1 2 }
|
||||
Port: AddWeighted : src1_data_stream_2_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_0_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_1_V | {1 2 }
|
||||
Port: AddWeighted : src2_data_stream_2_V | {1 2 }
|
||||
Port: AddWeighted : dst_data_stream_0_V | {}
|
||||
Port: AddWeighted : dst_data_stream_1_V | {}
|
||||
Port: AddWeighted : dst_data_stream_2_V | {}
|
||||
- Chain level:
|
||||
State 1
|
||||
State 2
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Datapath Resource usage
|
||||
============================================================
|
||||
|
||||
* Functional unit list:
|
||||
|----------|----------------------|---------|---------|
|
||||
| Operation| Functional Unit | FF | LUT |
|
||||
|----------|----------------------|---------|---------|
|
||||
| call | grp_arithm_pro_fu_32 | 73 | 166 |
|
||||
|----------|----------------------|---------|---------|
|
||||
| Total | | 73 | 166 |
|
||||
|----------|----------------------|---------|---------|
|
||||
|
||||
Memories:
|
||||
N/A
|
||||
|
||||
* Register list:
|
||||
N/A
|
||||
|
||||
* Multiplexer (MUX) list:
|
||||
|--------|------|------|------|--------|
|
||||
| Comp | Pin | Size | BW | S x BW |
|
||||
|--------|------|------|------|--------|
|
||||
| Total | | | | 0 |
|
||||
|--------|------|------|------|--------|
|
||||
|
||||
|
||||
|
||||
* Summary:
|
||||
+-----------+--------+--------+
|
||||
| | FF | LUT |
|
||||
+-----------+--------+--------+
|
||||
| Function | 73 | 166 |
|
||||
| Memory | - | - |
|
||||
|Multiplexer| - | - |
|
||||
| Register | - | - |
|
||||
+-----------+--------+--------+
|
||||
| Total | 73 | 166 |
|
||||
+-----------+--------+--------+
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AddWeighted'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:47 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 4.846, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2077922, 2077922, 2077922, 2077922, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
<column name="grp_arithm_pro_fu_32">arithm_pro, 2077921, 2077921, 2077921, 2077921, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Utilization Estimates" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="1">
|
||||
<keys size="6">Name, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
<column name="DSP">-, -, -, -, -</column>
|
||||
<column name="Expression">-, -, 0, 2, -</column>
|
||||
<column name="FIFO">-, -, -, -, -</column>
|
||||
<column name="Instance">-, -, 69, 320, -</column>
|
||||
<column name="Memory">-, -, -, -, -</column>
|
||||
<column name="Multiplexer">-, -, -, 105, -</column>
|
||||
<column name="Register">-, -, 4, -, -</column>
|
||||
<specialColumn name="Available">280, 220, 106400, 53200, 0</specialColumn>
|
||||
<specialColumn name="Utilization (%)">0, 0, ~0, ~0, 0</specialColumn>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="1">
|
||||
<keys size="7">Instance, Module, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
<column name="grp_arithm_pro_fu_32">arithm_pro, 0, 0, 69, 320, 0</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "DSP48E"><table name="" hasTotal="0">
|
||||
<keys size="3">Instance, Module, Expression</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Memory"><table name="" hasTotal="1">
|
||||
<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "FIFO"><table name="" hasTotal="1">
|
||||
<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Expression"><table name="" hasTotal="1">
|
||||
<keys size="7">Variable Name, Operation, DSP48E, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
|
||||
<column name="ap_block_state1">or, 0, 0, 2, 1, 1</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Multiplexer"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
|
||||
<column name="ap_NS_fsm">15, 3, 1, 3</column>
|
||||
<column name="ap_done">9, 2, 1, 2</column>
|
||||
<column name="dst_data_stream_0_V_write">9, 2, 1, 2</column>
|
||||
<column name="dst_data_stream_1_V_write">9, 2, 1, 2</column>
|
||||
<column name="dst_data_stream_2_V_write">9, 2, 1, 2</column>
|
||||
<column name="src1_data_stream_0_V_read">9, 2, 1, 2</column>
|
||||
<column name="src1_data_stream_1_V_read">9, 2, 1, 2</column>
|
||||
<column name="src1_data_stream_2_V_read">9, 2, 1, 2</column>
|
||||
<column name="src2_data_stream_0_V_read">9, 2, 1, 2</column>
|
||||
<column name="src2_data_stream_1_V_read">9, 2, 1, 2</column>
|
||||
<column name="src2_data_stream_2_V_read">9, 2, 1, 2</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Register"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
|
||||
<column name="ap_CS_fsm">2, 0, 2, 0</column>
|
||||
<column name="ap_done_reg">1, 0, 1, 0</column>
|
||||
<column name="grp_arithm_pro_fu_32_ap_start_reg">1, 0, 1, 0</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Interface" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
|
||||
<column name="ap_clk">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_rst">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_start">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_done">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_continue">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_idle">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="ap_ready">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
|
||||
<column name="src1_data_stream_0_V_dout">in, 8, ap_fifo, src1_data_stream_0_V, pointer</column>
|
||||
<column name="src1_data_stream_0_V_empty_n">in, 1, ap_fifo, src1_data_stream_0_V, pointer</column>
|
||||
<column name="src1_data_stream_0_V_read">out, 1, ap_fifo, src1_data_stream_0_V, pointer</column>
|
||||
<column name="src1_data_stream_1_V_dout">in, 8, ap_fifo, src1_data_stream_1_V, pointer</column>
|
||||
<column name="src1_data_stream_1_V_empty_n">in, 1, ap_fifo, src1_data_stream_1_V, pointer</column>
|
||||
<column name="src1_data_stream_1_V_read">out, 1, ap_fifo, src1_data_stream_1_V, pointer</column>
|
||||
<column name="src1_data_stream_2_V_dout">in, 8, ap_fifo, src1_data_stream_2_V, pointer</column>
|
||||
<column name="src1_data_stream_2_V_empty_n">in, 1, ap_fifo, src1_data_stream_2_V, pointer</column>
|
||||
<column name="src1_data_stream_2_V_read">out, 1, ap_fifo, src1_data_stream_2_V, pointer</column>
|
||||
<column name="src2_data_stream_0_V_dout">in, 8, ap_fifo, src2_data_stream_0_V, pointer</column>
|
||||
<column name="src2_data_stream_0_V_empty_n">in, 1, ap_fifo, src2_data_stream_0_V, pointer</column>
|
||||
<column name="src2_data_stream_0_V_read">out, 1, ap_fifo, src2_data_stream_0_V, pointer</column>
|
||||
<column name="src2_data_stream_1_V_dout">in, 8, ap_fifo, src2_data_stream_1_V, pointer</column>
|
||||
<column name="src2_data_stream_1_V_empty_n">in, 1, ap_fifo, src2_data_stream_1_V, pointer</column>
|
||||
<column name="src2_data_stream_1_V_read">out, 1, ap_fifo, src2_data_stream_1_V, pointer</column>
|
||||
<column name="src2_data_stream_2_V_dout">in, 8, ap_fifo, src2_data_stream_2_V, pointer</column>
|
||||
<column name="src2_data_stream_2_V_empty_n">in, 1, ap_fifo, src2_data_stream_2_V, pointer</column>
|
||||
<column name="src2_data_stream_2_V_read">out, 1, ap_fifo, src2_data_stream_2_V, pointer</column>
|
||||
<column name="dst_data_stream_0_V_din">out, 8, ap_fifo, dst_data_stream_0_V, pointer</column>
|
||||
<column name="dst_data_stream_0_V_full_n">in, 1, ap_fifo, dst_data_stream_0_V, pointer</column>
|
||||
<column name="dst_data_stream_0_V_write">out, 1, ap_fifo, dst_data_stream_0_V, pointer</column>
|
||||
<column name="dst_data_stream_1_V_din">out, 8, ap_fifo, dst_data_stream_1_V, pointer</column>
|
||||
<column name="dst_data_stream_1_V_full_n">in, 1, ap_fifo, dst_data_stream_1_V, pointer</column>
|
||||
<column name="dst_data_stream_1_V_write">out, 1, ap_fifo, dst_data_stream_1_V, pointer</column>
|
||||
<column name="dst_data_stream_2_V_din">out, 8, ap_fifo, dst_data_stream_2_V, pointer</column>
|
||||
<column name="dst_data_stream_2_V_full_n">in, 1, ap_fifo, dst_data_stream_2_V, pointer</column>
|
||||
<column name="dst_data_stream_2_V_write">out, 1, ap_fifo, dst_data_stream_2_V, pointer</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
|
||||
|
||||
================================================================
|
||||
== Vivado HLS Report for 'AddWeighted'
|
||||
================================================================
|
||||
* Date: Tue Feb 7 10:18:34 2023
|
||||
|
||||
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
|
||||
* Project: edge_detect
|
||||
* Solution: solution1
|
||||
* Product family: zynq
|
||||
* Target device: xc7z020-clg400-1
|
||||
|
||||
|
||||
================================================================
|
||||
== Performance Estimates
|
||||
================================================================
|
||||
+ Timing (ns):
|
||||
* Summary:
|
||||
+--------+-------+----------+------------+
|
||||
| Clock | Target| Estimated| Uncertainty|
|
||||
+--------+-------+----------+------------+
|
||||
|ap_clk | 6.70| 4.846| 0.84|
|
||||
+--------+-------+----------+------------+
|
||||
|
||||
+ Latency (clock cycles):
|
||||
* Summary:
|
||||
+---------+---------+---------+---------+---------+
|
||||
| Latency | Interval | Pipeline|
|
||||
| min | max | min | max | Type |
|
||||
+---------+---------+---------+---------+---------+
|
||||
| 2077922| 2077922| 2077922| 2077922| none |
|
||||
+---------+---------+---------+---------+---------+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
N/A
|
||||
|
||||
* Loop:
|
||||
N/A
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Synthesis Manager
|
||||
============================================================
|
||||
InlineROM: 1
|
||||
ExposeGlobal: 0
|
||||
============================================================
|
||||
+ Verbose Summary: CDFG Model
|
||||
============================================================
|
||||
IsTopModel: 0
|
||||
ResetActiveHigh: 1
|
||||
IsCombinational: 2
|
||||
IsDatapathOnly: 0
|
||||
HasWiredReturn: 1
|
||||
HasMFsm: 0
|
||||
HasVarLatency: 1
|
||||
IsPipeline: 0
|
||||
IsRtlPipelined: 0
|
||||
IsInstanceOverlapped: 0
|
||||
IsDontTouch: 0
|
||||
HasImplIP: 0
|
||||
IsGatedGlobalClock: 0
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Schedule
|
||||
============================================================
|
||||
* Number of FSM states : 2
|
||||
* Pipeline : 0
|
||||
* Dataflow Pipeline: 0
|
||||
|
||||
* FSM state transitions:
|
||||
1 --> 2
|
||||
2 -->
|
||||
|
||||
* FSM state operations:
|
||||
|
||||
State 1 <SV = 0> <Delay = 0.00>
|
||||
ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 2 <SV = 1> <Delay = 0.00>
|
||||
ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Timing violations
|
||||
============================================================
|
||||
Target clock period: 6.7ns, clock uncertainty: 0.837ns.
|
||||
|
||||
<State 1>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
<State 2>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Binding
|
||||
============================================================
|
||||
N/A
|
||||
* FSMD analyzer results:
|
||||
- Output states:
|
||||
- Input state :
|
||||
- Chain level:
|
||||
State 1
|
||||
State 2
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Datapath Resource usage
|
||||
============================================================
|
||||
N/A
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'AddWeighted'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:34 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 4.846, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2077922, 2077922, 2077922, 2077922, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,2 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
# This script segment is generated automatically by AutoPilot
|
||||
|
||||
set id 71
|
||||
set name edge_detect_sitodocq
|
||||
set corename simcore_sitodp
|
||||
set op sitodp
|
||||
set stage_num 8
|
||||
set max_latency -1
|
||||
set registered_input 1
|
||||
set Futype4reduceCEFanout 1
|
||||
set clk_width 1
|
||||
set clk_signed 0
|
||||
set reset_width 1
|
||||
set reset_signed 0
|
||||
set in0_width 32
|
||||
set in0_signed 0
|
||||
set ce_width 1
|
||||
set ce_signed 0
|
||||
set out_width 64
|
||||
if {${::AESL::PGuard_simmodel_gen}} {
|
||||
if {[info proc ap_gen_simcore_sitodp] == "ap_gen_simcore_sitodp"} {
|
||||
eval "ap_gen_simcore_sitodp { \
|
||||
id ${id} \
|
||||
name ${name} \
|
||||
corename ${corename} \
|
||||
op ${op} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
stage_num ${stage_num} \
|
||||
max_latency ${max_latency} \
|
||||
registered_input ${registered_input} \
|
||||
Futype4reduceCEFanout ${Futype4reduceCEFanout} \
|
||||
clk_width ${clk_width} \
|
||||
clk_signed ${clk_signed} \
|
||||
reset_width ${reset_width} \
|
||||
reset_signed ${reset_signed} \
|
||||
in0_width ${in0_width} \
|
||||
in0_signed ${in0_signed} \
|
||||
ce_width ${ce_width} \
|
||||
ce_signed ${ce_signed} \
|
||||
out_width ${out_width} \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-100\] Cannot find ap_gen_simcore_sitodp, check your AutoPilot builtin lib"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if {${::AESL::PGuard_rtl_comp_handler}} {
|
||||
::AP::rtl_comp_handler ${name}
|
||||
}
|
||||
|
||||
|
||||
set op sitodp
|
||||
set corename Int2Double
|
||||
if {${::AESL::PGuard_autocg_gen} && (${::AESL::PGuard_autocg_fpip} || ${::AESL::PGuard_autocg_fpv6en} || ${::AESL::PGuard_autocg_hpen})} {
|
||||
if {[info proc ::AESL_LIB_XILINX_FPV6::fpv6_gen] == "::AESL_LIB_XILINX_FPV6::fpv6_gen"} {
|
||||
eval "::AESL_LIB_XILINX_FPV6::fpv6_gen { \
|
||||
id ${id} \
|
||||
name ${name} \
|
||||
corename ${corename} \
|
||||
op ${op} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
stage_num ${stage_num} \
|
||||
max_latency ${max_latency} \
|
||||
registered_input ${registered_input} \
|
||||
Futype4reduceCEFanout ${Futype4reduceCEFanout} \
|
||||
clk_width ${clk_width} \
|
||||
clk_signed ${clk_signed} \
|
||||
reset_width ${reset_width} \
|
||||
reset_signed ${reset_signed} \
|
||||
in0_width ${in0_width} \
|
||||
in0_signed ${in0_signed} \
|
||||
ce_width ${ce_width} \
|
||||
ce_signed ${ce_signed} \
|
||||
out_width ${out_width} \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-101\] Cannot find ::AESL_LIB_XILINX_FPV6::fpv6_gen, check your platform lib"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# clear list
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_begin
|
||||
cg_default_interface_gen_bundle_begin
|
||||
AESL_LIB_XILADAPTER::native_axis_begin
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 75 \
|
||||
name p_src_data_stream_V \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_src_data_stream_V \
|
||||
op interface \
|
||||
ports { p_src_data_stream_V_dout { I 8 vector } p_src_data_stream_V_empty_n { I 1 bit } p_src_data_stream_V_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 76 \
|
||||
name p_src_data_stream_V1 \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_src_data_stream_V1 \
|
||||
op interface \
|
||||
ports { p_src_data_stream_V1_dout { I 8 vector } p_src_data_stream_V1_empty_n { I 1 bit } p_src_data_stream_V1_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 77 \
|
||||
name p_src_data_stream_V2 \
|
||||
type fifo \
|
||||
dir I \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_src_data_stream_V2 \
|
||||
op interface \
|
||||
ports { p_src_data_stream_V2_dout { I 8 vector } p_src_data_stream_V2_empty_n { I 1 bit } p_src_data_stream_V2_read { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 78 \
|
||||
name p_dst_data_stream_V \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_dst_data_stream_V \
|
||||
op interface \
|
||||
ports { p_dst_data_stream_V_din { O 8 vector } p_dst_data_stream_V_full_n { I 1 bit } p_dst_data_stream_V_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 79 \
|
||||
name p_dst_data_stream_V3 \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_dst_data_stream_V3 \
|
||||
op interface \
|
||||
ports { p_dst_data_stream_V3_din { O 8 vector } p_dst_data_stream_V3_full_n { I 1 bit } p_dst_data_stream_V3_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id 80 \
|
||||
name p_dst_data_stream_V4 \
|
||||
type fifo \
|
||||
dir O \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename dc_p_dst_data_stream_V4 \
|
||||
op interface \
|
||||
ports { p_dst_data_stream_V4_din { O 8 vector } p_dst_data_stream_V4_full_n { I 1 bit } p_dst_data_stream_V4_write { O 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
# Direct connection:
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
eval "cg_default_interface_gen_dc { \
|
||||
id -1 \
|
||||
name ap_ctrl \
|
||||
type ap_ctrl \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename ap_ctrl \
|
||||
op interface \
|
||||
ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
|
||||
} "
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_clk
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
|
||||
eval "cg_default_interface_gen_clock { \
|
||||
id -2 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_clk \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# Adapter definition:
|
||||
set PortName ap_rst
|
||||
set DataWd 1
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
|
||||
eval "cg_default_interface_gen_reset { \
|
||||
id -3 \
|
||||
name ${PortName} \
|
||||
reset_level 1 \
|
||||
sync_rst true \
|
||||
corename apif_ap_rst \
|
||||
data_wd ${DataWd} \
|
||||
op interface \
|
||||
}"
|
||||
} else {
|
||||
puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
# merge
|
||||
if {${::AESL::PGuard_autoexp_gen}} {
|
||||
cg_default_interface_gen_dc_end
|
||||
cg_default_interface_gen_bundle_end
|
||||
AESL_LIB_XILADAPTER::native_axis_end
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,203 @@
|
|||
set moduleName ConvertScaleAbs155
|
||||
set isTopModule 0
|
||||
set isTaskLevelControl 1
|
||||
set isCombinational 0
|
||||
set isDatapathOnly 0
|
||||
set isFreeRunPipelineModule 0
|
||||
set isPipelined 0
|
||||
set pipeline_type none
|
||||
set FunctionProtocol ap_ctrl_hs
|
||||
set isOneStateSeq 0
|
||||
set ProfileFlag 0
|
||||
set StallSigGenFlag 0
|
||||
set isEnableWaveformDebug 1
|
||||
set C_modelName {ConvertScaleAbs155}
|
||||
set C_modelType { void 0 }
|
||||
set C_modelArgList {
|
||||
{ p_src_data_stream_V int 8 regular {fifo 0 volatile } }
|
||||
{ p_src_data_stream_V1 int 8 regular {fifo 0 volatile } }
|
||||
{ p_src_data_stream_V2 int 8 regular {fifo 0 volatile } }
|
||||
{ p_dst_data_stream_V int 8 regular {fifo 1 volatile } }
|
||||
{ p_dst_data_stream_V3 int 8 regular {fifo 1 volatile } }
|
||||
{ p_dst_data_stream_V4 int 8 regular {fifo 1 volatile } }
|
||||
}
|
||||
set C_modelArgMapList {[
|
||||
{ "Name" : "p_src_data_stream_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "p_src_data_stream_V1", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "p_src_data_stream_V2", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
|
||||
{ "Name" : "p_dst_data_stream_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "p_dst_data_stream_V3", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
|
||||
{ "Name" : "p_dst_data_stream_V4", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ]}
|
||||
# RTL Port declarations:
|
||||
set portNum 25
|
||||
set portList {
|
||||
{ ap_clk sc_in sc_logic 1 clock -1 }
|
||||
{ ap_rst sc_in sc_logic 1 reset -1 active_high_sync }
|
||||
{ ap_start sc_in sc_logic 1 start -1 }
|
||||
{ ap_done sc_out sc_logic 1 predone -1 }
|
||||
{ ap_continue sc_in sc_logic 1 continue -1 }
|
||||
{ ap_idle sc_out sc_logic 1 done -1 }
|
||||
{ ap_ready sc_out sc_logic 1 ready -1 }
|
||||
{ p_src_data_stream_V_dout sc_in sc_lv 8 signal 0 }
|
||||
{ p_src_data_stream_V_empty_n sc_in sc_logic 1 signal 0 }
|
||||
{ p_src_data_stream_V_read sc_out sc_logic 1 signal 0 }
|
||||
{ p_src_data_stream_V1_dout sc_in sc_lv 8 signal 1 }
|
||||
{ p_src_data_stream_V1_empty_n sc_in sc_logic 1 signal 1 }
|
||||
{ p_src_data_stream_V1_read sc_out sc_logic 1 signal 1 }
|
||||
{ p_src_data_stream_V2_dout sc_in sc_lv 8 signal 2 }
|
||||
{ p_src_data_stream_V2_empty_n sc_in sc_logic 1 signal 2 }
|
||||
{ p_src_data_stream_V2_read sc_out sc_logic 1 signal 2 }
|
||||
{ p_dst_data_stream_V_din sc_out sc_lv 8 signal 3 }
|
||||
{ p_dst_data_stream_V_full_n sc_in sc_logic 1 signal 3 }
|
||||
{ p_dst_data_stream_V_write sc_out sc_logic 1 signal 3 }
|
||||
{ p_dst_data_stream_V3_din sc_out sc_lv 8 signal 4 }
|
||||
{ p_dst_data_stream_V3_full_n sc_in sc_logic 1 signal 4 }
|
||||
{ p_dst_data_stream_V3_write sc_out sc_logic 1 signal 4 }
|
||||
{ p_dst_data_stream_V4_din sc_out sc_lv 8 signal 5 }
|
||||
{ p_dst_data_stream_V4_full_n sc_in sc_logic 1 signal 5 }
|
||||
{ p_dst_data_stream_V4_write sc_out sc_logic 1 signal 5 }
|
||||
}
|
||||
set NewPortList {[
|
||||
{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
|
||||
{ "name": "ap_rst", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst", "role": "default" }} ,
|
||||
{ "name": "ap_start", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "start", "bundle":{"name": "ap_start", "role": "default" }} ,
|
||||
{ "name": "ap_done", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "predone", "bundle":{"name": "ap_done", "role": "default" }} ,
|
||||
{ "name": "ap_continue", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "continue", "bundle":{"name": "ap_continue", "role": "default" }} ,
|
||||
{ "name": "ap_idle", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "done", "bundle":{"name": "ap_idle", "role": "default" }} ,
|
||||
{ "name": "ap_ready", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "ready", "bundle":{"name": "ap_ready", "role": "default" }} ,
|
||||
{ "name": "p_src_data_stream_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_src_data_stream_V", "role": "dout" }} ,
|
||||
{ "name": "p_src_data_stream_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V", "role": "empty_n" }} ,
|
||||
{ "name": "p_src_data_stream_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V", "role": "read" }} ,
|
||||
{ "name": "p_src_data_stream_V1_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_src_data_stream_V1", "role": "dout" }} ,
|
||||
{ "name": "p_src_data_stream_V1_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V1", "role": "empty_n" }} ,
|
||||
{ "name": "p_src_data_stream_V1_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V1", "role": "read" }} ,
|
||||
{ "name": "p_src_data_stream_V2_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_src_data_stream_V2", "role": "dout" }} ,
|
||||
{ "name": "p_src_data_stream_V2_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V2", "role": "empty_n" }} ,
|
||||
{ "name": "p_src_data_stream_V2_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_src_data_stream_V2", "role": "read" }} ,
|
||||
{ "name": "p_dst_data_stream_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_dst_data_stream_V", "role": "din" }} ,
|
||||
{ "name": "p_dst_data_stream_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V", "role": "full_n" }} ,
|
||||
{ "name": "p_dst_data_stream_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V", "role": "write" }} ,
|
||||
{ "name": "p_dst_data_stream_V3_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_dst_data_stream_V3", "role": "din" }} ,
|
||||
{ "name": "p_dst_data_stream_V3_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V3", "role": "full_n" }} ,
|
||||
{ "name": "p_dst_data_stream_V3_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V3", "role": "write" }} ,
|
||||
{ "name": "p_dst_data_stream_V4_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "p_dst_data_stream_V4", "role": "din" }} ,
|
||||
{ "name": "p_dst_data_stream_V4_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V4", "role": "full_n" }} ,
|
||||
{ "name": "p_dst_data_stream_V4_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "p_dst_data_stream_V4", "role": "write" }} ]}
|
||||
|
||||
set RtlHierarchyInfo {[
|
||||
{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "", "Child" : ["1", "2", "3", "4", "5", "6"],
|
||||
"CDFG" : "ConvertScaleAbs155",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "1", "ap_idle" : "1",
|
||||
"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "0",
|
||||
"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2094121", "EstimateLatencyMax" : "2094121",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "0",
|
||||
"ClockEnable" : "0",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "1",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "p_src_data_stream_V", "Type" : "Fifo", "Direction" : "I", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_src_data_stream_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "p_src_data_stream_V1", "Type" : "Fifo", "Direction" : "I", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_src_data_stream_V1_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "p_src_data_stream_V2", "Type" : "Fifo", "Direction" : "I", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_src_data_stream_V2_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "p_dst_data_stream_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_dst_data_stream_V_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "p_dst_data_stream_V3", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_dst_data_stream_V3_blk_n", "Type" : "RtlSignal"}]},
|
||||
{"Name" : "p_dst_data_stream_V4", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
|
||||
"BlockSignal" : [
|
||||
{"Name" : "p_dst_data_stream_V4_blk_n", "Type" : "RtlSignal"}]}]},
|
||||
{"ID" : "1", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.grp_operator_1_fu_131", "Parent" : "0",
|
||||
"CDFG" : "operator_1",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "0", "ap_start" : "0", "ap_ready" : "0", "ap_done" : "0", "ap_continue" : "0", "ap_idle" : "0",
|
||||
"Pipeline" : "Aligned", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "1",
|
||||
"VariableLatency" : "0", "ExactLatency" : "5", "EstimateLatencyMin" : "5", "EstimateLatencyMax" : "5",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "1",
|
||||
"ClockEnable" : "1",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "0",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "v", "Type" : "None", "Direction" : "I"}]},
|
||||
{"ID" : "2", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.grp_operator_1_fu_136", "Parent" : "0",
|
||||
"CDFG" : "operator_1",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "0", "ap_start" : "0", "ap_ready" : "0", "ap_done" : "0", "ap_continue" : "0", "ap_idle" : "0",
|
||||
"Pipeline" : "Aligned", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "1",
|
||||
"VariableLatency" : "0", "ExactLatency" : "5", "EstimateLatencyMin" : "5", "EstimateLatencyMax" : "5",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "1",
|
||||
"ClockEnable" : "1",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "0",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "v", "Type" : "None", "Direction" : "I"}]},
|
||||
{"ID" : "3", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.grp_operator_1_fu_141", "Parent" : "0",
|
||||
"CDFG" : "operator_1",
|
||||
"Protocol" : "ap_ctrl_hs",
|
||||
"ControlExist" : "0", "ap_start" : "0", "ap_ready" : "0", "ap_done" : "0", "ap_continue" : "0", "ap_idle" : "0",
|
||||
"Pipeline" : "Aligned", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
|
||||
"II" : "1",
|
||||
"VariableLatency" : "0", "ExactLatency" : "5", "EstimateLatencyMin" : "5", "EstimateLatencyMax" : "5",
|
||||
"Combinational" : "0",
|
||||
"Datapath" : "1",
|
||||
"ClockEnable" : "1",
|
||||
"HasSubDataflow" : "0",
|
||||
"InDataflowNetwork" : "0",
|
||||
"HasNonBlockingOperation" : "0",
|
||||
"Port" : [
|
||||
{"Name" : "v", "Type" : "None", "Direction" : "I"}]},
|
||||
{"ID" : "4", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.edge_detect_sitodocq_U71", "Parent" : "0"},
|
||||
{"ID" : "5", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.edge_detect_sitodocq_U72", "Parent" : "0"},
|
||||
{"ID" : "6", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.edge_detect_sitodocq_U73", "Parent" : "0"}]}
|
||||
|
||||
|
||||
set ArgLastReadFirstWriteLatency {
|
||||
ConvertScaleAbs155 {
|
||||
p_src_data_stream_V {Type I LastRead 3 FirstWrite -1}
|
||||
p_src_data_stream_V1 {Type I LastRead 3 FirstWrite -1}
|
||||
p_src_data_stream_V2 {Type I LastRead 3 FirstWrite -1}
|
||||
p_dst_data_stream_V {Type O LastRead -1 FirstWrite 19}
|
||||
p_dst_data_stream_V3 {Type O LastRead -1 FirstWrite 19}
|
||||
p_dst_data_stream_V4 {Type O LastRead -1 FirstWrite 19}}
|
||||
operator_1 {
|
||||
v {Type I LastRead 0 FirstWrite -1}}
|
||||
operator_1 {
|
||||
v {Type I LastRead 0 FirstWrite -1}}
|
||||
operator_1 {
|
||||
v {Type I LastRead 0 FirstWrite -1}}}
|
||||
|
||||
set hasDtUnsupportedChannel 0
|
||||
|
||||
set PerformanceInfo {[
|
||||
{"Name" : "Latency", "Min" : "2094121", "Max" : "2094121"}
|
||||
, {"Name" : "Interval", "Min" : "2094121", "Max" : "2094121"}
|
||||
]}
|
||||
|
||||
set PipelineEnableSignalInfo {[
|
||||
{"Pipeline" : "0", "EnableSignal" : "ap_enable_pp0"}
|
||||
]}
|
||||
|
||||
set Spec2ImplPortList {
|
||||
p_src_data_stream_V { ap_fifo { { p_src_data_stream_V_dout fifo_data 0 8 } { p_src_data_stream_V_empty_n fifo_status 0 1 } { p_src_data_stream_V_read fifo_update 1 1 } } }
|
||||
p_src_data_stream_V1 { ap_fifo { { p_src_data_stream_V1_dout fifo_data 0 8 } { p_src_data_stream_V1_empty_n fifo_status 0 1 } { p_src_data_stream_V1_read fifo_update 1 1 } } }
|
||||
p_src_data_stream_V2 { ap_fifo { { p_src_data_stream_V2_dout fifo_data 0 8 } { p_src_data_stream_V2_empty_n fifo_status 0 1 } { p_src_data_stream_V2_read fifo_update 1 1 } } }
|
||||
p_dst_data_stream_V { ap_fifo { { p_dst_data_stream_V_din fifo_data 1 8 } { p_dst_data_stream_V_full_n fifo_status 0 1 } { p_dst_data_stream_V_write fifo_update 1 1 } } }
|
||||
p_dst_data_stream_V3 { ap_fifo { { p_dst_data_stream_V3_din fifo_data 1 8 } { p_dst_data_stream_V3_full_n fifo_status 0 1 } { p_dst_data_stream_V3_write fifo_update 1 1 } } }
|
||||
p_dst_data_stream_V4 { ap_fifo { { p_dst_data_stream_V4_din fifo_data 1 8 } { p_dst_data_stream_V4_full_n fifo_status 0 1 } { p_dst_data_stream_V4_write fifo_update 1 1 } } }
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,50 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'ConvertScaleAbs155'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:30 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 6.562, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2094121, 2094121, 2094121, 2094121, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
<column name="grp_operator_1_fu_131">operator_1, 5, 5, 1, 1, function</column>
|
||||
<column name="grp_operator_1_fu_136">operator_1, 5, 5, 1, 1, function</column>
|
||||
<column name="grp_operator_1_fu_141">operator_1, 5, 5, 1, 1, function</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_height">2094120, 2094120, 1939, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1936, 1936, 18, 1, 1, 1920, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,192 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'ConvertScaleAbs155'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:44 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 6.562, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2094121, 2094121, 2094121, 2094121, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
<column name="grp_operator_1_fu_131">operator_1, 5, 5, 1, 1, function</column>
|
||||
<column name="grp_operator_1_fu_136">operator_1, 5, 5, 1, 1, function</column>
|
||||
<column name="grp_operator_1_fu_141">operator_1, 5, 5, 1, 1, function</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_height">2094120, 2094120, 1939, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1936, 1936, 18, 1, 1, 1920, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Utilization Estimates" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="1">
|
||||
<keys size="6">Name, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
<column name="DSP">-, -, -, -, -</column>
|
||||
<column name="Expression">-, -, 0, 64, -</column>
|
||||
<column name="FIFO">-, -, -, -, -</column>
|
||||
<column name="Instance">0, 0, 4923, 6591, -</column>
|
||||
<column name="Memory">-, -, -, -, -</column>
|
||||
<column name="Multiplexer">-, -, -, 126, -</column>
|
||||
<column name="Register">0, -, 358, 32, -</column>
|
||||
<specialColumn name="Available">280, 220, 106400, 53200, 0</specialColumn>
|
||||
<specialColumn name="Utilization (%)">0, 0, 4, 12, 0</specialColumn>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="1">
|
||||
<keys size="7">Instance, Module, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
|
||||
<column name="edge_detect_sitodocq_U71">edge_detect_sitodocq, 0, 0, 549, 625, 0</column>
|
||||
<column name="edge_detect_sitodocq_U72">edge_detect_sitodocq, 0, 0, 549, 625, 0</column>
|
||||
<column name="edge_detect_sitodocq_U73">edge_detect_sitodocq, 0, 0, 549, 625, 0</column>
|
||||
<column name="grp_operator_1_fu_131">operator_1, 0, 0, 1092, 1572, 0</column>
|
||||
<column name="grp_operator_1_fu_136">operator_1, 0, 0, 1092, 1572, 0</column>
|
||||
<column name="grp_operator_1_fu_141">operator_1, 0, 0, 1092, 1572, 0</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "DSP48E"><table name="" hasTotal="0">
|
||||
<keys size="3">Instance, Module, Expression</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Memory"><table name="" hasTotal="1">
|
||||
<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "FIFO"><table name="" hasTotal="1">
|
||||
<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Expression"><table name="" hasTotal="1">
|
||||
<keys size="7">Variable Name, Operation, DSP48E, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
|
||||
<column name="i_fu_161_p2">+, 0, 0, 13, 11, 1</column>
|
||||
<column name="j_fu_173_p2">+, 0, 0, 13, 11, 1</column>
|
||||
<column name="icmp_ln2526_fu_155_p2">icmp, 0, 0, 13, 11, 11</column>
|
||||
<column name="icmp_ln2527_fu_167_p2">icmp, 0, 0, 13, 11, 9</column>
|
||||
<column name="ap_block_pp0_stage0_01001">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state1">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state20_pp0_stage0_iter17">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_block_state4_pp0_stage0_iter1">or, 0, 0, 2, 1, 1</column>
|
||||
<column name="ap_enable_pp0">xor, 0, 0, 2, 1, 2</column>
|
||||
<column name="ap_enable_reg_pp0_iter1">xor, 0, 0, 2, 2, 1</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Multiplexer"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
|
||||
<column name="ap_NS_fsm">27, 5, 1, 5</column>
|
||||
<column name="ap_done">9, 2, 1, 2</column>
|
||||
<column name="ap_enable_reg_pp0_iter1">9, 2, 1, 2</column>
|
||||
<column name="ap_enable_reg_pp0_iter17">9, 2, 1, 2</column>
|
||||
<column name="i_0_reg_109">9, 2, 11, 22</column>
|
||||
<column name="j_0_reg_120">9, 2, 11, 22</column>
|
||||
<column name="p_dst_data_stream_V3_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_dst_data_stream_V4_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_dst_data_stream_V_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_src_data_stream_V1_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_src_data_stream_V2_blk_n">9, 2, 1, 2</column>
|
||||
<column name="p_src_data_stream_V_blk_n">9, 2, 1, 2</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Register"><table name="" hasTotal="1">
|
||||
<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
|
||||
<column name="ap_CS_fsm">4, 0, 4, 0</column>
|
||||
<column name="ap_done_reg">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter0">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter1">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter10">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter11">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter12">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter13">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter14">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter15">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter16">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter17">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter2">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter3">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter4">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter5">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter6">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter7">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter8">1, 0, 1, 0</column>
|
||||
<column name="ap_enable_reg_pp0_iter9">1, 0, 1, 0</column>
|
||||
<column name="i_0_reg_109">11, 0, 11, 0</column>
|
||||
<column name="i_reg_255">11, 0, 11, 0</column>
|
||||
<column name="icmp_ln2527_reg_260">1, 0, 1, 0</column>
|
||||
<column name="j_0_reg_120">11, 0, 11, 0</column>
|
||||
<column name="p_d_val_0_reg_329">8, 0, 8, 0</column>
|
||||
<column name="p_d_val_1_reg_334">8, 0, 8, 0</column>
|
||||
<column name="tmp_24_reg_339">8, 0, 8, 0</column>
|
||||
<column name="tmp_63_reg_269">8, 0, 8, 0</column>
|
||||
<column name="tmp_64_reg_274">8, 0, 8, 0</column>
|
||||
<column name="tmp_65_reg_279">8, 0, 8, 0</column>
|
||||
<column name="trunc_ln368_3_reg_304">63, 0, 63, 0</column>
|
||||
<column name="trunc_ln368_4_reg_309">63, 0, 63, 0</column>
|
||||
<column name="trunc_ln368_reg_299">63, 0, 63, 0</column>
|
||||
<column name="icmp_ln2527_reg_260">64, 32, 1, 0</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
|
||||
<section name = "Interface" level="0">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
|
||||
<column name="ap_clk">in, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_rst">in, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_start">in, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_done">out, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_continue">in, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_idle">out, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="ap_ready">out, 1, ap_ctrl_hs, ConvertScaleAbs155, return value</column>
|
||||
<column name="p_src_data_stream_V_dout">in, 8, ap_fifo, p_src_data_stream_V, pointer</column>
|
||||
<column name="p_src_data_stream_V_empty_n">in, 1, ap_fifo, p_src_data_stream_V, pointer</column>
|
||||
<column name="p_src_data_stream_V_read">out, 1, ap_fifo, p_src_data_stream_V, pointer</column>
|
||||
<column name="p_src_data_stream_V1_dout">in, 8, ap_fifo, p_src_data_stream_V1, pointer</column>
|
||||
<column name="p_src_data_stream_V1_empty_n">in, 1, ap_fifo, p_src_data_stream_V1, pointer</column>
|
||||
<column name="p_src_data_stream_V1_read">out, 1, ap_fifo, p_src_data_stream_V1, pointer</column>
|
||||
<column name="p_src_data_stream_V2_dout">in, 8, ap_fifo, p_src_data_stream_V2, pointer</column>
|
||||
<column name="p_src_data_stream_V2_empty_n">in, 1, ap_fifo, p_src_data_stream_V2, pointer</column>
|
||||
<column name="p_src_data_stream_V2_read">out, 1, ap_fifo, p_src_data_stream_V2, pointer</column>
|
||||
<column name="p_dst_data_stream_V_din">out, 8, ap_fifo, p_dst_data_stream_V, pointer</column>
|
||||
<column name="p_dst_data_stream_V_full_n">in, 1, ap_fifo, p_dst_data_stream_V, pointer</column>
|
||||
<column name="p_dst_data_stream_V_write">out, 1, ap_fifo, p_dst_data_stream_V, pointer</column>
|
||||
<column name="p_dst_data_stream_V3_din">out, 8, ap_fifo, p_dst_data_stream_V3, pointer</column>
|
||||
<column name="p_dst_data_stream_V3_full_n">in, 1, ap_fifo, p_dst_data_stream_V3, pointer</column>
|
||||
<column name="p_dst_data_stream_V3_write">out, 1, ap_fifo, p_dst_data_stream_V3, pointer</column>
|
||||
<column name="p_dst_data_stream_V4_din">out, 8, ap_fifo, p_dst_data_stream_V4, pointer</column>
|
||||
<column name="p_dst_data_stream_V4_full_n">in, 1, ap_fifo, p_dst_data_stream_V4, pointer</column>
|
||||
<column name="p_dst_data_stream_V4_write">out, 1, ap_fifo, p_dst_data_stream_V4, pointer</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
|
|
@ -0,0 +1,375 @@
|
|||
|
||||
|
||||
================================================================
|
||||
== Vivado HLS Report for 'ConvertScaleAbs155'
|
||||
================================================================
|
||||
* Date: Tue Feb 7 10:18:30 2023
|
||||
|
||||
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
|
||||
* Project: edge_detect
|
||||
* Solution: solution1
|
||||
* Product family: zynq
|
||||
* Target device: xc7z020-clg400-1
|
||||
|
||||
|
||||
================================================================
|
||||
== Performance Estimates
|
||||
================================================================
|
||||
+ Timing (ns):
|
||||
* Summary:
|
||||
+--------+-------+----------+------------+
|
||||
| Clock | Target| Estimated| Uncertainty|
|
||||
+--------+-------+----------+------------+
|
||||
|ap_clk | 6.70| 6.562| 0.84|
|
||||
+--------+-------+----------+------------+
|
||||
|
||||
+ Latency (clock cycles):
|
||||
* Summary:
|
||||
+---------+---------+---------+---------+---------+
|
||||
| Latency | Interval | Pipeline|
|
||||
| min | max | min | max | Type |
|
||||
+---------+---------+---------+---------+---------+
|
||||
| 2094121| 2094121| 2094121| 2094121| none |
|
||||
+---------+---------+---------+---------+---------+
|
||||
|
||||
+ Detail:
|
||||
* Instance:
|
||||
N/A
|
||||
|
||||
* Loop:
|
||||
+---------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
| | Latency | Iteration| Initiation Interval | Trip | |
|
||||
| Loop Name | min | max | Latency | achieved | target | Count| Pipelined|
|
||||
+---------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
|- loop_height | 2094120| 2094120| 1939| -| -| 1080| no |
|
||||
| + loop_width | 1936| 1936| 18| 1| 1| 1920| yes |
|
||||
+---------------+---------+---------+----------+-----------+-----------+------+----------+
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Synthesis Manager
|
||||
============================================================
|
||||
InlineROM: 1
|
||||
ExposeGlobal: 0
|
||||
============================================================
|
||||
+ Verbose Summary: CDFG Model
|
||||
============================================================
|
||||
IsTopModel: 0
|
||||
ResetActiveHigh: 1
|
||||
IsCombinational: 2
|
||||
IsDatapathOnly: 0
|
||||
HasWiredReturn: 1
|
||||
HasMFsm: 0
|
||||
HasVarLatency: 1
|
||||
IsPipeline: 0
|
||||
IsRtlPipelined: 0
|
||||
IsInstanceOverlapped: 0
|
||||
IsDontTouch: 0
|
||||
HasImplIP: 0
|
||||
IsGatedGlobalClock: 0
|
||||
|
||||
+ Individual pipeline summary:
|
||||
* Pipeline-0: initiation interval (II) = 1, depth = 18
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Schedule
|
||||
============================================================
|
||||
* Number of FSM states : 21
|
||||
* Pipeline : 1
|
||||
Pipeline-0 : II = 1, D = 18, States = { 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 }
|
||||
* Dataflow Pipeline: 0
|
||||
|
||||
* FSM state transitions:
|
||||
1 --> 2
|
||||
2 --> 3
|
||||
3 --> 21 4
|
||||
4 --> 5
|
||||
5 --> 6
|
||||
6 --> 7
|
||||
7 --> 8
|
||||
8 --> 9
|
||||
9 --> 10
|
||||
10 --> 11
|
||||
11 --> 12
|
||||
12 --> 13
|
||||
13 --> 14
|
||||
14 --> 15
|
||||
15 --> 16
|
||||
16 --> 17
|
||||
17 --> 18
|
||||
18 --> 19
|
||||
19 --> 20
|
||||
20 --> 3
|
||||
21 --> 2
|
||||
|
||||
* FSM state operations:
|
||||
|
||||
State 1 <SV = 0> <Delay = 1.76>
|
||||
ST_1 : Operation 22 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V2, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 22 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 23 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V1, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 23 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 24 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 24 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 25 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 25 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 26 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V3, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 26 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 27 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V4, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 27 'specinterface' <Predicate = true> <Delay = 0.00>
|
||||
ST_1 : Operation 28 [1/1] (1.76ns) ---> "br label %0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 28 'br' <Predicate = true> <Delay = 1.76>
|
||||
|
||||
State 2 <SV = 1> <Delay = 2.85>
|
||||
ST_2 : Operation 29 [1/1] (0.00ns) ---> "%i_0 = phi i11 [ 0, %._crit_edge ], [ %i, %loop_height_end ]" ---> Operation 29 'phi' 'i_0' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 30 [1/1] (1.88ns) ---> "%icmp_ln2526 = icmp ult i11 %i_0, -968" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 30 'icmp' 'icmp_ln2526' <Predicate = true> <Delay = 1.88> <Core = "Cmp"> ---> Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.88> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_2 : Operation 31 [1/1] (1.63ns) ---> "%i = add i11 %i_0, 1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 31 'add' 'i' <Predicate = true> <Delay = 1.63> <Core = "AddSub"> ---> Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.63> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_2 : Operation 32 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1080, i64 1080, i64 1080)" ---> Operation 32 'speclooptripcount' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 33 [1/1] (0.00ns) ---> "br i1 %icmp_ln2526, label %loop_height_begin, label %2" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 33 'br' <Predicate = true> <Delay = 0.00>
|
||||
ST_2 : Operation 34 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([12 x i8]* @p_str7) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 34 'specloopname' <Predicate = (icmp_ln2526)> <Delay = 0.00>
|
||||
ST_2 : Operation 35 [1/1] (0.00ns) ---> "%tmp_18 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str7)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 35 'specregionbegin' 'tmp_18' <Predicate = (icmp_ln2526)> <Delay = 0.00>
|
||||
ST_2 : Operation 36 [1/1] (1.76ns) ---> "br label %1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 36 'br' <Predicate = (icmp_ln2526)> <Delay = 1.76>
|
||||
ST_2 : Operation 37 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2538] ---> Operation 37 'ret' <Predicate = (!icmp_ln2526)> <Delay = 0.00>
|
||||
|
||||
State 3 <SV = 2> <Delay = 1.88>
|
||||
ST_3 : Operation 38 [1/1] (0.00ns) ---> "%j_0 = phi i11 [ 0, %loop_height_begin ], [ %j, %loop_width_begin ]" ---> Operation 38 'phi' 'j_0' <Predicate = true> <Delay = 0.00>
|
||||
ST_3 : Operation 39 [1/1] (1.88ns) ---> "%icmp_ln2527 = icmp ult i11 %j_0, -128" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 39 'icmp' 'icmp_ln2527' <Predicate = true> <Delay = 1.88> <Core = "Cmp"> ---> Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.88> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_3 : Operation 40 [1/1] (1.63ns) ---> "%j = add i11 %j_0, 1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 40 'add' 'j' <Predicate = true> <Delay = 1.63> <Core = "AddSub"> ---> Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.63> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
|
||||
ST_3 : Operation 41 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1920, i64 1920, i64 1920)" ---> Operation 41 'speclooptripcount' <Predicate = true> <Delay = 0.00>
|
||||
ST_3 : Operation 42 [1/1] (0.00ns) ---> "br i1 %icmp_ln2527, label %loop_width_begin, label %loop_height_end" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 42 'br' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
State 4 <SV = 3> <Delay = 2.93>
|
||||
ST_4 : Operation 43 [1/1] (0.00ns) ---> "%tmp_20 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str12)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:672->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 43 'specregionbegin' 'tmp_20' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_4 : Operation 44 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:676->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 44 'specprotocol' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_4 : Operation 45 [1/1] (2.93ns) ---> "%tmp_63 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:679->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 45 'read' 'tmp_63' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_4 : Operation 46 [1/1] (2.93ns) ---> "%tmp_64 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V1)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:679->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 46 'read' 'tmp_64' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_4 : Operation 47 [1/1] (2.93ns) ---> "%tmp_65 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V2)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:679->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 47 'read' 'tmp_65' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_4 : Operation 48 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str12, i32 %tmp_20)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:681->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530] ---> Operation 48 'specregionend' 'empty' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
|
||||
State 5 <SV = 4> <Delay = 6.56>
|
||||
ST_5 : Operation 49 [1/1] (0.00ns) ---> "%zext_ln2533 = zext i8 %tmp_63 to i32" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 49 'zext' 'zext_ln2533' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_5 : Operation 50 [8/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 50 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_5 : Operation 51 [1/1] (0.00ns) ---> "%zext_ln2533_1 = zext i8 %tmp_64 to i32" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 51 'zext' 'zext_ln2533_1' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_5 : Operation 52 [8/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 52 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_5 : Operation 53 [1/1] (0.00ns) ---> "%zext_ln2533_2 = zext i8 %tmp_65 to i32" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 53 'zext' 'zext_ln2533_2' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_5 : Operation 54 [8/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 54 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 6 <SV = 5> <Delay = 6.56>
|
||||
ST_6 : Operation 55 [7/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 55 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_6 : Operation 56 [7/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 56 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_6 : Operation 57 [7/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 57 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 7 <SV = 6> <Delay = 6.56>
|
||||
ST_7 : Operation 58 [6/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 58 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_7 : Operation 59 [6/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 59 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_7 : Operation 60 [6/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 60 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 8 <SV = 7> <Delay = 6.56>
|
||||
ST_8 : Operation 61 [5/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 61 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_8 : Operation 62 [5/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 62 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_8 : Operation 63 [5/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 63 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 9 <SV = 8> <Delay = 6.56>
|
||||
ST_9 : Operation 64 [4/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 64 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_9 : Operation 65 [4/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 65 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_9 : Operation 66 [4/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 66 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 10 <SV = 9> <Delay = 6.56>
|
||||
ST_10 : Operation 67 [3/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 67 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_10 : Operation 68 [3/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 68 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_10 : Operation 69 [3/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 69 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 11 <SV = 10> <Delay = 6.56>
|
||||
ST_11 : Operation 70 [2/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 70 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_11 : Operation 71 [2/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 71 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_11 : Operation 72 [2/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 72 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
|
||||
State 12 <SV = 11> <Delay = 6.56>
|
||||
ST_12 : Operation 73 [1/8] (6.56ns) ---> "%x_assign = sitofp i32 %zext_ln2533 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 73 'sitodp' 'x_assign' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_12 : Operation 74 [1/1] (0.00ns) ---> "%p_Val2_s = bitcast double %x_assign to i64" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:475->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:479->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:12->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 74 'bitcast' 'p_Val2_s' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_12 : Operation 75 [1/1] (0.00ns) ---> "%trunc_ln368 = trunc i64 %p_Val2_s to i63" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 75 'trunc' 'trunc_ln368' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_12 : Operation 76 [1/8] (6.56ns) ---> "%x_assign_3 = sitofp i32 %zext_ln2533_1 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 76 'sitodp' 'x_assign_3' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_12 : Operation 77 [1/1] (0.00ns) ---> "%p_Val2_40 = bitcast double %x_assign_3 to i64" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:475->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:479->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:12->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 77 'bitcast' 'p_Val2_40' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_12 : Operation 78 [1/1] (0.00ns) ---> "%trunc_ln368_3 = trunc i64 %p_Val2_40 to i63" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 78 'trunc' 'trunc_ln368_3' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_12 : Operation 79 [1/8] (6.56ns) ---> "%x_assign_4 = sitofp i32 %zext_ln2533_2 to double" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 79 'sitodp' 'x_assign_4' <Predicate = (icmp_ln2527)> <Delay = 6.56> <Core = "Int2Double"> ---> Core 122 'Int2Double' <Latency = 7> <II = 1> <Delay = 6.56> <FuncUnit> <Opcode : 'sitodp' 'uitodp'> <InPorts = 1> <OutPorts = 1>
|
||||
ST_12 : Operation 80 [1/1] (0.00ns) ---> "%p_Val2_41 = bitcast double %x_assign_4 to i64" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:475->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:479->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:12->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 80 'bitcast' 'p_Val2_41' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_12 : Operation 81 [1/1] (0.00ns) ---> "%trunc_ln368_4 = trunc i64 %p_Val2_41 to i63" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 81 'trunc' 'trunc_ln368_4' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
|
||||
State 13 <SV = 12> <Delay = 2.78>
|
||||
ST_13 : Operation 82 [1/1] (0.00ns) ---> "%p_Result_s = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368)" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 82 'bitconcatenate' 'p_Result_s' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 83 [1/1] (0.00ns) ---> "%bitcast_ln512 = bitcast i64 %p_Result_s to double" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 83 'bitcast' 'bitcast_ln512' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 84 [7/7] (2.78ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 84 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 2.78> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_13 : Operation 85 [1/1] (0.00ns) ---> "%p_Result_15 = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368_3)" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 85 'bitconcatenate' 'p_Result_15' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 86 [1/1] (0.00ns) ---> "%bitcast_ln512_3 = bitcast i64 %p_Result_15 to double" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 86 'bitcast' 'bitcast_ln512_3' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 87 [7/7] (2.78ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 87 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 2.78> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_13 : Operation 88 [1/1] (0.00ns) ---> "%p_Result_16 = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368_4)" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:495->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 88 'bitconcatenate' 'p_Result_16' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 89 [1/1] (0.00ns) ---> "%bitcast_ln512_4 = bitcast i64 %p_Result_16 to double" [r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:512->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/src/hls\utils/x_hls_utils.h:526->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint/hls_copysign.h:14->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/include/FloatingPoint\hls_fabs.h:13->r:/builds/2019.1/continuous/2019_05_24_2552052/src/products/hls/hls_lib/hlsmath/src/c++/absdouble.cpp:7->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 89 'bitcast' 'bitcast_ln512_4' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_13 : Operation 90 [7/7] (2.78ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 90 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 2.78> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 14 <SV = 13> <Delay = 5.60>
|
||||
ST_14 : Operation 91 [6/7] (5.60ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 91 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_14 : Operation 92 [6/7] (5.60ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 92 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_14 : Operation 93 [6/7] (5.60ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 93 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 15 <SV = 14> <Delay = 5.60>
|
||||
ST_15 : Operation 94 [5/7] (5.60ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 94 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_15 : Operation 95 [5/7] (5.60ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 95 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_15 : Operation 96 [5/7] (5.60ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 96 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 16 <SV = 15> <Delay = 5.60>
|
||||
ST_16 : Operation 97 [4/7] (5.60ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 97 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_16 : Operation 98 [4/7] (5.60ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 98 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_16 : Operation 99 [4/7] (5.60ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 99 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 17 <SV = 16> <Delay = 5.60>
|
||||
ST_17 : Operation 100 [3/7] (5.60ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 100 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_17 : Operation 101 [3/7] (5.60ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 101 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_17 : Operation 102 [3/7] (5.60ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 102 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 18 <SV = 17> <Delay = 5.60>
|
||||
ST_18 : Operation 103 [2/7] (5.60ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 103 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_18 : Operation 104 [2/7] (5.60ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 104 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_18 : Operation 105 [2/7] (5.60ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 105 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 5.60> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 19 <SV = 18> <Delay = 3.47>
|
||||
ST_19 : Operation 106 [1/7] (3.47ns) ---> "%p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 106 'call' 'p_d_val_0' <Predicate = (icmp_ln2527)> <Delay = 3.47> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_19 : Operation 107 [1/7] (3.47ns) ---> "%p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 107 'call' 'p_d_val_1' <Predicate = (icmp_ln2527)> <Delay = 3.47> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
ST_19 : Operation 108 [1/7] (3.47ns) ---> "%tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533] ---> Operation 108 'call' 'tmp_24' <Predicate = (icmp_ln2527)> <Delay = 3.47> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
|
||||
|
||||
State 20 <SV = 19> <Delay = 2.93>
|
||||
ST_20 : Operation 109 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str8) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 109 'specloopname' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 110 [1/1] (0.00ns) ---> "%tmp_19 = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str8)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 110 'specregionbegin' 'tmp_19' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 111 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2529] ---> Operation 111 'specpipeline' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 112 [1/1] (0.00ns) ---> "%tmp_s = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str16)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:696->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 112 'specregionbegin' 'tmp_s' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 113 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:700->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 113 'specprotocol' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 114 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V, i8 %p_d_val_0)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 114 'write' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_20 : Operation 115 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V3, i8 %p_d_val_1)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 115 'write' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_20 : Operation 116 [1/1] (2.93ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V4, i8 %tmp_24)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 116 'write' <Predicate = (icmp_ln2527)> <Delay = 2.93> <Core = "FIFO"> ---> Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 8> <Depth = 2> <FIFO>
|
||||
ST_20 : Operation 117 [1/1] (0.00ns) ---> "%empty_105 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str16, i32 %tmp_s)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:705->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535] ---> Operation 117 'specregionend' 'empty_105' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 118 [1/1] (0.00ns) ---> "%empty_106 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str8, i32 %tmp_19)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2536] ---> Operation 118 'specregionend' 'empty_106' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
ST_20 : Operation 119 [1/1] (0.00ns) ---> "br label %1" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527] ---> Operation 119 'br' <Predicate = (icmp_ln2527)> <Delay = 0.00>
|
||||
|
||||
State 21 <SV = 3> <Delay = 0.00>
|
||||
ST_21 : Operation 120 [1/1] (0.00ns) ---> "%empty_107 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str7, i32 %tmp_18)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2537] ---> Operation 120 'specregionend' 'empty_107' <Predicate = true> <Delay = 0.00>
|
||||
ST_21 : Operation 121 [1/1] (0.00ns) ---> "br label %0" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526] ---> Operation 121 'br' <Predicate = true> <Delay = 0.00>
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Timing violations
|
||||
============================================================
|
||||
Target clock period: 6.7ns, clock uncertainty: 0.837ns.
|
||||
|
||||
<State 1>: 1.77ns
|
||||
The critical path consists of the following:
|
||||
multiplexor before 'phi' operation ('i') with incoming values : ('i', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526) [15] (1.77 ns)
|
||||
|
||||
<State 2>: 2.86ns
|
||||
The critical path consists of the following:
|
||||
'icmp' operation ('icmp_ln2526', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2526) [16] (1.88 ns)
|
||||
blocking operation 0.978 ns on control path)
|
||||
|
||||
<State 3>: 1.88ns
|
||||
The critical path consists of the following:
|
||||
'phi' operation ('j') with incoming values : ('j', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527) [25] (0 ns)
|
||||
'icmp' operation ('icmp_ln2527', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2527) [26] (1.88 ns)
|
||||
|
||||
<State 4>: 2.93ns
|
||||
The critical path consists of the following:
|
||||
fifo read on port 'p_src_data_stream_V' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:679->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:711->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2530) [36] (2.93 ns)
|
||||
|
||||
<State 5>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 6>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 7>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 8>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 9>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 10>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 11>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 12>: 6.56ns
|
||||
The critical path consists of the following:
|
||||
'sitodp' operation ('x', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) [41] (6.56 ns)
|
||||
|
||||
<State 13>: 2.79ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (2.79 ns)
|
||||
|
||||
<State 14>: 5.61ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (5.61 ns)
|
||||
|
||||
<State 15>: 5.61ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (5.61 ns)
|
||||
|
||||
<State 16>: 5.61ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (5.61 ns)
|
||||
|
||||
<State 17>: 5.61ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (5.61 ns)
|
||||
|
||||
<State 18>: 5.61ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (5.61 ns)
|
||||
|
||||
<State 19>: 3.47ns
|
||||
The critical path consists of the following:
|
||||
'call' operation ('_d.val[0]', C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_types.h:500->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2533) to 'operator().1' [46] (3.47 ns)
|
||||
|
||||
<State 20>: 2.93ns
|
||||
The critical path consists of the following:
|
||||
fifo write on port 'p_dst_data_stream_V' (C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:703->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_core.h:717->C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_imgproc.h:2535) [63] (2.93 ns)
|
||||
|
||||
<State 21>: 0ns
|
||||
The critical path consists of the following:
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Binding
|
||||
============================================================
|
||||
N/A
|
||||
* FSMD analyzer results:
|
||||
- Output states:
|
||||
- Input state :
|
||||
- Chain level:
|
||||
State 1
|
||||
State 2
|
||||
State 3
|
||||
State 4
|
||||
State 5
|
||||
State 6
|
||||
State 7
|
||||
State 8
|
||||
State 9
|
||||
State 10
|
||||
State 11
|
||||
State 12
|
||||
State 13
|
||||
State 14
|
||||
State 15
|
||||
State 16
|
||||
State 17
|
||||
State 18
|
||||
State 19
|
||||
State 20
|
||||
State 21
|
||||
|
||||
|
||||
============================================================
|
||||
+ Verbose Summary: Datapath Resource usage
|
||||
============================================================
|
||||
N/A
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
<profile>
|
||||
|
||||
<section name = "Vivado HLS Report for 'ConvertScaleAbs155'" level="0">
|
||||
<item name = "Date">Tue Feb 7 10:18:30 2023
|
||||
</item>
|
||||
<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
|
||||
<item name = "Project">edge_detect</item>
|
||||
<item name = "Solution">solution1</item>
|
||||
<item name = "Product family">zynq</item>
|
||||
<item name = "Target device">xc7z020-clg400-1</item>
|
||||
</section>
|
||||
|
||||
<section name = "Performance Estimates" level="0">
|
||||
<item name = "Timing (ns)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
|
||||
<column name="ap_clk">6.70, 6.562, 0.84</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
<item name = "Latency (clock cycles)">
|
||||
<section name = "" level="1">
|
||||
<item name = "Summary"><table name="" hasTotal="0">
|
||||
<keys size="6">, min, max, min, max, Type</keys>
|
||||
<column name="">2094121, 2094121, 2094121, 2094121, none</column>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Detail">
|
||||
<section name = "" level="1">
|
||||
<item name = "Instance"><table name="" hasTotal="0">
|
||||
<keys size="7">Instance, Module, min, max, min, max, Type</keys>
|
||||
</table>
|
||||
</item>
|
||||
<item name = "Loop"><table name="" hasTotal="0">
|
||||
<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
|
||||
<column name="- loop_height">2094120, 2094120, 1939, -, -, 1080, no</column>
|
||||
<column name=" + loop_width">1936, 1936, 18, 1, 1, 1920, yes</column>
|
||||
</table>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</item>
|
||||
</section>
|
||||
</profile>
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue