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31 lines
1.9 KiB
Plaintext
31 lines
1.9 KiB
Plaintext
==============================================================
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Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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==============================================================
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INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
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INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
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INFO: [SIM 211-2] *************** CSIM start ***************
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INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
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ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
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INFO: [SIM 211-3] *************** CSIM finish ***************
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==============================================================
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Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
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Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
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==============================================================
|
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INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
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INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
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INFO: [SIM 211-2] *************** CSIM start ***************
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INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
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ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
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INFO: [SIM 211-3] *************** CSIM finish ***************
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==============================================================
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Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2019.1 (64-bit)
|
|
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
|
==============================================================
|
|
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
|
|
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
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INFO: [SIM 211-2] *************** CSIM start ***************
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INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
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ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
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INFO: [SIM 211-3] *************** CSIM finish ***************
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