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72 lines
4.1 KiB
Plaintext
72 lines
4.1 KiB
Plaintext
<solution AutoPilot="com.autoesl.autopilot.solution">
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<checksum>
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<value string="false"/>
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</checksum>
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<downStreamTool>
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<DownStreamTool name="vivado"/>
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</downStreamTool>
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<clockList>
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<clock name="default" period="10"/>
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</clockList>
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<config/>
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<UIConfigurations>
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<UIAutosynConf boardInfo="Zybo Z7-20 (xc7z020clg400-1) " hideTrivialOp="true" isBasedOnBoard="true" isSolutionDirty="false" isStopAskAgain="false" showDetailDesignViewer="false">
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<Platform>xilinx/zynq/zynq</Platform>
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<customLibs/>
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</UIAutosynConf>
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<UIIPPackagerConf AskAgain="true" DescriptionButton="false" LibraryButton="false" RTLLanguage="verilog" UseNetList="none" VendorButton="false" VersionButton="false" evaluateRTL="false" setup="false">
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<RTLs>
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<Verilog method="IPXACT" selection="true"/>
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<Vhdl method="IPXACT" selection="false"/>
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</RTLs>
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</UIIPPackagerConf>
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<UIAutoMGConf AskAgain="true" Export="false" Xil_CoreGen="false" defaultCustomPorts="false">
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<UIAutoMGImpl add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false" register_retiming="off" setup="0" synplify_io_insertion="true" synplify_op_effort="high" synplify_pipelining="false" synplify_resource_sharing="true" synplify_retiming="false" synplify_verilogPar="false" synplify_vhdlPar="false" synthesis_combo_logic="off" synthesis_effort="normal" virtual_pins="off" xilinxInterconnectType="plb">
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<RTLs>
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<Verilog selection="true" tool="ISE"/>
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<Vhdl selection="false" tool="ISE"/>
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</RTLs>
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<verilogSynplifySettings synplify_invocation_command="synplify_pro -licensetype synplifypro_xilinx" synplify_io_insertion="false" synplify_op_effort="high" synplify_par="true" synplify_pipelining="true" synplify_resource_sharing="true" synplify_retiming="false"/>
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<vhdlSynplifySettings synplify_invocation_command="synplify_pro -licensetype synplifypro_xilinx" synplify_io_insertion="false" synplify_op_effort="high" synplify_par="true" synplify_pipelining="true" synplify_resource_sharing="true" synplify_retiming="false"/>
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<verilogISESettings add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false"/>
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<vhdlISESettings add_io_buffers="false" op_effort="high" op_goal="speed" par_effort="high" register_balancing="no" register_duplication="false"/>
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</UIAutoMGImpl>
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</UIAutoMGConf>
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<UIAutoSimConf ApIntSupport="false" AskAgain="true">
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<RTLs>
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<SystemC selection="true" tool="Auto"/>
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<Verilog selection="false" tool="Auto"/>
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<VHDL selection="false" tool="Auto"/>
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</RTLs>
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</UIAutoSimConf>
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</UIConfigurations>
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<ExportDesign askAgain="true" evaluate="false" flow="false" flowChoice="syn" formatName="ip_catalog" rtl="verilog" rtlButton="false" rtlCombo="verilog">
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<Format formatName="ip_catalog"/>
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<Format formatName="sysgen"/>
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<Format formatName="sysgen_ise"/>
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<Format formatName="syn_dcp"/>
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<Format formatName="pcore" use_netlist="none"/>
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</ExportDesign>
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<Simulation>
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<SimFlow askAgain="true" clangSanitizer="false" compile="false" compileChoice="gcc" disableDeadlockDetect="false" dumpTrace="none" name="cosim" optimizeCompile="false" reduce_diskspace="false" setup="false" toolName="Auto" waveDebug="false">
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<Rtl active="false" name="systemc"/>
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<Rtl active="true" name="verilog"/>
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<Rtl active="false" name="vhdl"/>
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</SimFlow>
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</Simulation>
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<name>
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<value string="solution1"/>
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</name>
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<project>
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<value string="circle_detect"/>
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</project>
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<targetInfo>
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<TargetInfo value="xc7z020:-clg400:-1"/>
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</targetInfo>
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<libraryList>
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<library name="DefaultPlatform" value="xilinx/zynq/zynq"/>
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<library value="xilinx/zynq/zynq_fpv6" name="DefaultPlatform"/>
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</libraryList>
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</solution>
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