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390 lines
16 KiB
Plaintext
390 lines
16 KiB
Plaintext
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================================================================
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== Vivado HLS Report for 'AddWeighted'
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================================================================
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* Date: Tue Feb 7 10:18:34 2023
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* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
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* Project: edge_detect
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* Solution: solution1
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* Product family: zynq
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* Target device: xc7z020-clg400-1
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================================================================
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== Performance Estimates
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================================================================
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+ Timing (ns):
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* Summary:
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+--------+-------+----------+------------+
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| Clock | Target| Estimated| Uncertainty|
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+--------+-------+----------+------------+
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|ap_clk | 6.70| 4.846| 0.84|
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+--------+-------+----------+------------+
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+ Latency (clock cycles):
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* Summary:
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+---------+---------+---------+---------+---------+
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| Latency | Interval | Pipeline|
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| min | max | min | max | Type |
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+---------+---------+---------+---------+---------+
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| 2077922| 2077922| 2077922| 2077922| none |
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+---------+---------+---------+---------+---------+
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+ Detail:
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* Instance:
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+----------------------+------------+---------+---------+---------+---------+---------+
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| | | Latency | Interval | Pipeline|
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| Instance | Module | min | max | min | max | Type |
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+----------------------+------------+---------+---------+---------+---------+---------+
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|grp_arithm_pro_fu_32 |arithm_pro | 2077921| 2077921| 2077921| 2077921| none |
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+----------------------+------------+---------+---------+---------+---------+---------+
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* Loop:
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N/A
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============================================================
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+ Verbose Summary: Synthesis Manager
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============================================================
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InlineROM: 1
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ExposeGlobal: 0
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============================================================
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+ Verbose Summary: CDFG Model
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============================================================
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IsTopModel: 0
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ResetActiveHigh: 1
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IsCombinational: 2
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IsDatapathOnly: 0
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HasWiredReturn: 1
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HasMFsm: 0
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HasVarLatency: 1
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IsPipeline: 0
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IsRtlPipelined: 0
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IsInstanceOverlapped: 0
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IsDontTouch: 0
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HasImplIP: 0
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IsGatedGlobalClock: 0
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============================================================
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+ Verbose Summary: Schedule
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============================================================
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* Number of FSM states : 2
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* Pipeline : 0
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* Dataflow Pipeline: 0
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* FSM state transitions:
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1 --> 2
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2 -->
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* FSM state operations:
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State 1 <SV = 0> <Delay = 0.00>
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ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
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State 2 <SV = 1> <Delay = 0.00>
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ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
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ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
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============================================================
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+ Verbose Summary: Binding
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============================================================
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STG Binding:
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---------------- STG Properties BEGIN ----------------
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- Is combinational: 0
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- Is one-state seq: 0
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- Is datapath-only: 0
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- Is pipelined: 0
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- Is top level: 0
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Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
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Port [ src1_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ src1_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ src1_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ src2_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ src2_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ src2_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ dst_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ dst_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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Port [ dst_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
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---------------- STG Properties END ------------------
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---------------- Datapath Model BEGIN ----------------
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<LifeTime>
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<method=bitvector/>
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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specinterface_ln0 (specinterface) [ 000]
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call_ln879 (call ) [ 000]
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ret_ln880 (ret ) [ 000]
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</LifeTime>
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<model>
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<comp_list>
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<comp id="0" class="1000" name="src1_data_stream_0_V">
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<pin_list>
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<pin id="1" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
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</bind>
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</comp>
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<comp id="2" class="1000" name="src1_data_stream_1_V">
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<pin_list>
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<pin id="3" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
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</bind>
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</comp>
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<comp id="4" class="1000" name="src1_data_stream_2_V">
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<pin_list>
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<pin id="5" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
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</bind>
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</comp>
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<comp id="6" class="1000" name="src2_data_stream_0_V">
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<pin_list>
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<pin id="7" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
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</bind>
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</comp>
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<comp id="8" class="1000" name="src2_data_stream_1_V">
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<pin_list>
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<pin id="9" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
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</bind>
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</comp>
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<comp id="10" class="1000" name="src2_data_stream_2_V">
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<pin_list>
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<pin id="11" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
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</bind>
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</comp>
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<comp id="12" class="1000" name="dst_data_stream_0_V">
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<pin_list>
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<pin id="13" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
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</bind>
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</comp>
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<comp id="14" class="1000" name="dst_data_stream_1_V">
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<pin_list>
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<pin id="15" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
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</bind>
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</comp>
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<comp id="16" class="1000" name="dst_data_stream_2_V">
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<pin_list>
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<pin id="17" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
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</bind>
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</comp>
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<comp id="18" class="1001" name="const_18">
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<pin_list>
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<pin id="19" dir="1" index="0" bw="1" slack="0"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="arithm_pro"/></StgValue>
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</bind>
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</comp>
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<comp id="20" class="1001" name="const_20">
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<pin_list>
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<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
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</bind>
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</comp>
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<comp id="22" class="1001" name="const_22">
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<pin_list>
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<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="ap_fifo_str"/></StgValue>
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</bind>
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</comp>
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<comp id="24" class="1001" name="const_24">
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<pin_list>
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<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name=""/></StgValue>
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</bind>
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</comp>
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<comp id="26" class="1001" name="const_26">
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<pin_list>
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<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name="p_str"/></StgValue>
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</bind>
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</comp>
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<comp id="28" class="1001" name="const_28">
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<pin_list>
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<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name=""/></StgValue>
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</bind>
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</comp>
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<comp id="30" class="1001" name="const_30">
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<pin_list>
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<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
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</pin_list>
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<bind>
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<StgValue><ssdm name=""/></StgValue>
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</bind>
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</comp>
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<comp id="32" class="1004" name="grp_arithm_pro_fu_32">
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<pin_list>
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<pin id="33" dir="0" index="0" bw="0" slack="0"/>
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<pin id="34" dir="0" index="1" bw="8" slack="0"/>
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<pin id="35" dir="0" index="2" bw="8" slack="0"/>
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<pin id="36" dir="0" index="3" bw="8" slack="0"/>
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<pin id="37" dir="0" index="4" bw="8" slack="0"/>
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<pin id="38" dir="0" index="5" bw="8" slack="0"/>
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<pin id="39" dir="0" index="6" bw="8" slack="0"/>
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<pin id="40" dir="0" index="7" bw="8" slack="0"/>
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<pin id="41" dir="0" index="8" bw="8" slack="0"/>
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<pin id="42" dir="0" index="9" bw="8" slack="0"/>
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<pin id="43" dir="1" index="10" bw="0" slack="2147483647"/>
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</pin_list>
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<bind>
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<opcode="call(48) " fcode="call"/>
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<opset="call_ln879/1 "/>
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</bind>
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</comp>
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</comp_list>
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<net_list>
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<net id="44"><net_src comp="18" pin="0"/><net_sink comp="32" pin=0"/></net>
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<net id="45"><net_src comp="0" pin="0"/><net_sink comp="32" pin=1"/></net>
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<net id="46"><net_src comp="2" pin="0"/><net_sink comp="32" pin=2"/></net>
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<net id="47"><net_src comp="4" pin="0"/><net_sink comp="32" pin=3"/></net>
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<net id="48"><net_src comp="6" pin="0"/><net_sink comp="32" pin=4"/></net>
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<net id="49"><net_src comp="8" pin="0"/><net_sink comp="32" pin=5"/></net>
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<net id="50"><net_src comp="10" pin="0"/><net_sink comp="32" pin=6"/></net>
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<net id="51"><net_src comp="12" pin="0"/><net_sink comp="32" pin=7"/></net>
|
|
|
|
<net id="52"><net_src comp="14" pin="0"/><net_sink comp="32" pin=8"/></net>
|
|
|
|
<net id="53"><net_src comp="16" pin="0"/><net_sink comp="32" pin=9"/></net>
|
|
|
|
</net_list>
|
|
|
|
</model>
|
|
---------------- Datapath Model END ------------------
|
|
|
|
* FSMD analyzer results:
|
|
- Output states:
|
|
Port: dst_data_stream_0_V | {1 2 }
|
|
Port: dst_data_stream_1_V | {1 2 }
|
|
Port: dst_data_stream_2_V | {1 2 }
|
|
- Input state :
|
|
Port: AddWeighted : src1_data_stream_0_V | {1 2 }
|
|
Port: AddWeighted : src1_data_stream_1_V | {1 2 }
|
|
Port: AddWeighted : src1_data_stream_2_V | {1 2 }
|
|
Port: AddWeighted : src2_data_stream_0_V | {1 2 }
|
|
Port: AddWeighted : src2_data_stream_1_V | {1 2 }
|
|
Port: AddWeighted : src2_data_stream_2_V | {1 2 }
|
|
- Chain level:
|
|
State 1
|
|
State 2
|
|
|
|
|
|
============================================================
|
|
+ Verbose Summary: Datapath Resource usage
|
|
============================================================
|
|
|
|
* Functional unit list:
|
|
|----------|----------------------|---------|---------|
|
|
| Operation| Functional Unit | FF | LUT |
|
|
|----------|----------------------|---------|---------|
|
|
| call | grp_arithm_pro_fu_32 | 73 | 166 |
|
|
|----------|----------------------|---------|---------|
|
|
| Total | | 73 | 166 |
|
|
|----------|----------------------|---------|---------|
|
|
|
|
Memories:
|
|
N/A
|
|
|
|
* Register list:
|
|
N/A
|
|
|
|
* Multiplexer (MUX) list:
|
|
|--------|------|------|------|--------|
|
|
| Comp | Pin | Size | BW | S x BW |
|
|
|--------|------|------|------|--------|
|
|
| Total | | | | 0 |
|
|
|--------|------|------|------|--------|
|
|
|
|
|
|
|
|
* Summary:
|
|
+-----------+--------+--------+
|
|
| | FF | LUT |
|
|
+-----------+--------+--------+
|
|
| Function | 73 | 166 |
|
|
| Memory | - | - |
|
|
|Multiplexer| - | - |
|
|
| Register | - | - |
|
|
+-----------+--------+--------+
|
|
| Total | 73 | 166 |
|
|
+-----------+--------+--------+
|