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123 lines
7.5 KiB
Plaintext
123 lines
7.5 KiB
Plaintext
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================================================================
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== Vivado HLS Report for 'AddWeighted'
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================================================================
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* Date: Tue Feb 7 10:18:34 2023
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* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
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* Project: edge_detect
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* Solution: solution1
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* Product family: zynq
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* Target device: xc7z020-clg400-1
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================================================================
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== Performance Estimates
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================================================================
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+ Timing (ns):
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* Summary:
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+--------+-------+----------+------------+
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| Clock | Target| Estimated| Uncertainty|
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+--------+-------+----------+------------+
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|ap_clk | 6.70| 4.846| 0.84|
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+--------+-------+----------+------------+
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+ Latency (clock cycles):
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* Summary:
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+---------+---------+---------+---------+---------+
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| Latency | Interval | Pipeline|
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| min | max | min | max | Type |
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+---------+---------+---------+---------+---------+
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| 2077922| 2077922| 2077922| 2077922| none |
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+---------+---------+---------+---------+---------+
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+ Detail:
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* Instance:
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N/A
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* Loop:
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N/A
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============================================================
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+ Verbose Summary: Synthesis Manager
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============================================================
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InlineROM: 1
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ExposeGlobal: 0
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============================================================
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+ Verbose Summary: CDFG Model
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============================================================
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IsTopModel: 0
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ResetActiveHigh: 1
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IsCombinational: 2
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IsDatapathOnly: 0
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HasWiredReturn: 1
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HasMFsm: 0
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HasVarLatency: 1
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IsPipeline: 0
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IsRtlPipelined: 0
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IsInstanceOverlapped: 0
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IsDontTouch: 0
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HasImplIP: 0
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IsGatedGlobalClock: 0
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============================================================
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+ Verbose Summary: Schedule
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============================================================
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* Number of FSM states : 2
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* Pipeline : 0
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* Dataflow Pipeline: 0
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* FSM state transitions:
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1 --> 2
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2 -->
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* FSM state operations:
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State 1 <SV = 0> <Delay = 0.00>
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ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
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State 2 <SV = 1> <Delay = 0.00>
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ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
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ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
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ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
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============================================================
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+ Verbose Summary: Timing violations
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============================================================
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Target clock period: 6.7ns, clock uncertainty: 0.837ns.
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<State 1>: 0ns
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The critical path consists of the following:
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<State 2>: 0ns
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The critical path consists of the following:
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============================================================
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+ Verbose Summary: Binding
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============================================================
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N/A
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* FSMD analyzer results:
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- Output states:
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- Input state :
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- Chain level:
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State 1
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State 2
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============================================================
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+ Verbose Summary: Datapath Resource usage
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============================================================
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N/A
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