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20 lines
662 B
Tcl
20 lines
662 B
Tcl
############################################################
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## This file is generated automatically by Vivado HLS.
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## Please DO NOT edit it.
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## Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
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############################################################
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open_project circle_detect
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set_top circle_detect
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add_files circle_detect.cpp
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add_files circle_detect.h
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add_files -tb circle_detect_test.cpp
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add_files -tb rover.bmp
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open_solution "solution1"
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set_part {xc7z020clg400-1} -tool vivado
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create_clock -period 10 -name default
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#source "./circle_detect/solution1/directives.tcl"
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csim_design -clean
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csynth_design
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cosim_design
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export_design -format ip_catalog
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