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241 lines
17 KiB
Tcl
241 lines
17 KiB
Tcl
set moduleName AddWeighted
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set isTopModule 0
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set isTaskLevelControl 1
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set isCombinational 0
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set isDatapathOnly 0
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set isFreeRunPipelineModule 0
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set isPipelined 0
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set pipeline_type none
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set FunctionProtocol ap_ctrl_hs
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set isOneStateSeq 0
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set ProfileFlag 0
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set StallSigGenFlag 0
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set isEnableWaveformDebug 1
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set C_modelName {AddWeighted}
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set C_modelType { void 0 }
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set C_modelArgList {
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{ src1_data_stream_0_V int 8 regular {fifo 0 volatile } }
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{ src1_data_stream_1_V int 8 regular {fifo 0 volatile } }
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{ src1_data_stream_2_V int 8 regular {fifo 0 volatile } }
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{ src2_data_stream_0_V int 8 regular {fifo 0 volatile } }
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{ src2_data_stream_1_V int 8 regular {fifo 0 volatile } }
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{ src2_data_stream_2_V int 8 regular {fifo 0 volatile } }
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{ dst_data_stream_0_V int 8 regular {fifo 1 volatile } }
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{ dst_data_stream_1_V int 8 regular {fifo 1 volatile } }
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{ dst_data_stream_2_V int 8 regular {fifo 1 volatile } }
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}
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set C_modelArgMapList {[
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{ "Name" : "src1_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "src1_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "src1_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "src2_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "src2_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "src2_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "READONLY"} ,
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{ "Name" : "dst_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
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{ "Name" : "dst_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
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{ "Name" : "dst_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ]}
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# RTL Port declarations:
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set portNum 34
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set portList {
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{ ap_clk sc_in sc_logic 1 clock -1 }
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{ ap_rst sc_in sc_logic 1 reset -1 active_high_sync }
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{ ap_start sc_in sc_logic 1 start -1 }
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{ ap_done sc_out sc_logic 1 predone -1 }
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{ ap_continue sc_in sc_logic 1 continue -1 }
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{ ap_idle sc_out sc_logic 1 done -1 }
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{ ap_ready sc_out sc_logic 1 ready -1 }
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{ src1_data_stream_0_V_dout sc_in sc_lv 8 signal 0 }
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{ src1_data_stream_0_V_empty_n sc_in sc_logic 1 signal 0 }
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{ src1_data_stream_0_V_read sc_out sc_logic 1 signal 0 }
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{ src1_data_stream_1_V_dout sc_in sc_lv 8 signal 1 }
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{ src1_data_stream_1_V_empty_n sc_in sc_logic 1 signal 1 }
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{ src1_data_stream_1_V_read sc_out sc_logic 1 signal 1 }
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{ src1_data_stream_2_V_dout sc_in sc_lv 8 signal 2 }
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{ src1_data_stream_2_V_empty_n sc_in sc_logic 1 signal 2 }
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{ src1_data_stream_2_V_read sc_out sc_logic 1 signal 2 }
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{ src2_data_stream_0_V_dout sc_in sc_lv 8 signal 3 }
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{ src2_data_stream_0_V_empty_n sc_in sc_logic 1 signal 3 }
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{ src2_data_stream_0_V_read sc_out sc_logic 1 signal 3 }
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{ src2_data_stream_1_V_dout sc_in sc_lv 8 signal 4 }
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{ src2_data_stream_1_V_empty_n sc_in sc_logic 1 signal 4 }
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{ src2_data_stream_1_V_read sc_out sc_logic 1 signal 4 }
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{ src2_data_stream_2_V_dout sc_in sc_lv 8 signal 5 }
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{ src2_data_stream_2_V_empty_n sc_in sc_logic 1 signal 5 }
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{ src2_data_stream_2_V_read sc_out sc_logic 1 signal 5 }
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{ dst_data_stream_0_V_din sc_out sc_lv 8 signal 6 }
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{ dst_data_stream_0_V_full_n sc_in sc_logic 1 signal 6 }
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{ dst_data_stream_0_V_write sc_out sc_logic 1 signal 6 }
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{ dst_data_stream_1_V_din sc_out sc_lv 8 signal 7 }
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{ dst_data_stream_1_V_full_n sc_in sc_logic 1 signal 7 }
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{ dst_data_stream_1_V_write sc_out sc_logic 1 signal 7 }
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{ dst_data_stream_2_V_din sc_out sc_lv 8 signal 8 }
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{ dst_data_stream_2_V_full_n sc_in sc_logic 1 signal 8 }
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{ dst_data_stream_2_V_write sc_out sc_logic 1 signal 8 }
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}
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set NewPortList {[
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{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
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{ "name": "ap_rst", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst", "role": "default" }} ,
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{ "name": "ap_start", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "start", "bundle":{"name": "ap_start", "role": "default" }} ,
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{ "name": "ap_done", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "predone", "bundle":{"name": "ap_done", "role": "default" }} ,
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{ "name": "ap_continue", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "continue", "bundle":{"name": "ap_continue", "role": "default" }} ,
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{ "name": "ap_idle", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "done", "bundle":{"name": "ap_idle", "role": "default" }} ,
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{ "name": "ap_ready", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "ready", "bundle":{"name": "ap_ready", "role": "default" }} ,
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{ "name": "src1_data_stream_0_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "dout" }} ,
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{ "name": "src1_data_stream_0_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "empty_n" }} ,
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{ "name": "src1_data_stream_0_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_0_V", "role": "read" }} ,
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{ "name": "src1_data_stream_1_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "dout" }} ,
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{ "name": "src1_data_stream_1_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "empty_n" }} ,
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{ "name": "src1_data_stream_1_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_1_V", "role": "read" }} ,
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{ "name": "src1_data_stream_2_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "dout" }} ,
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{ "name": "src1_data_stream_2_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "empty_n" }} ,
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{ "name": "src1_data_stream_2_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src1_data_stream_2_V", "role": "read" }} ,
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{ "name": "src2_data_stream_0_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "dout" }} ,
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{ "name": "src2_data_stream_0_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "empty_n" }} ,
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{ "name": "src2_data_stream_0_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_0_V", "role": "read" }} ,
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{ "name": "src2_data_stream_1_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "dout" }} ,
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{ "name": "src2_data_stream_1_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "empty_n" }} ,
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{ "name": "src2_data_stream_1_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_1_V", "role": "read" }} ,
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{ "name": "src2_data_stream_2_V_dout", "direction": "in", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "dout" }} ,
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{ "name": "src2_data_stream_2_V_empty_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "empty_n" }} ,
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{ "name": "src2_data_stream_2_V_read", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "src2_data_stream_2_V", "role": "read" }} ,
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{ "name": "dst_data_stream_0_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "din" }} ,
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{ "name": "dst_data_stream_0_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "full_n" }} ,
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{ "name": "dst_data_stream_0_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_0_V", "role": "write" }} ,
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{ "name": "dst_data_stream_1_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "din" }} ,
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{ "name": "dst_data_stream_1_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "full_n" }} ,
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{ "name": "dst_data_stream_1_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_1_V", "role": "write" }} ,
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{ "name": "dst_data_stream_2_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "din" }} ,
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{ "name": "dst_data_stream_2_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "full_n" }} ,
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{ "name": "dst_data_stream_2_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "dst_data_stream_2_V", "role": "write" }} ]}
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set RtlHierarchyInfo {[
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{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "", "Child" : ["1"],
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"CDFG" : "AddWeighted",
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"Protocol" : "ap_ctrl_hs",
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"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "1", "ap_idle" : "1",
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"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
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"II" : "0",
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"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2077922", "EstimateLatencyMax" : "2077922",
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"Combinational" : "0",
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"Datapath" : "0",
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"ClockEnable" : "0",
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"HasSubDataflow" : "0",
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"InDataflowNetwork" : "1",
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"HasNonBlockingOperation" : "0",
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"WaitState" : [
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{"State" : "ap_ST_fsm_state2", "FSM" : "ap_CS_fsm", "SubInstance" : "grp_arithm_pro_fu_32"}],
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"Port" : [
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{"Name" : "src1_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_0_V"}]},
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{"Name" : "src1_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_1_V"}]},
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{"Name" : "src1_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src1_data_stream_2_V"}]},
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{"Name" : "src2_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_0_V"}]},
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{"Name" : "src2_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_1_V"}]},
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{"Name" : "src2_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "src2_data_stream_2_V"}]},
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{"Name" : "dst_data_stream_0_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_0_V"}]},
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{"Name" : "dst_data_stream_1_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_1_V"}]},
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{"Name" : "dst_data_stream_2_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"SubConnect" : [
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{"ID" : "1", "SubInstance" : "grp_arithm_pro_fu_32", "Port" : "dst_data_stream_2_V"}]}]},
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{"ID" : "1", "Level" : "1", "Path" : "`AUTOTB_DUT_INST.grp_arithm_pro_fu_32", "Parent" : "0",
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"CDFG" : "arithm_pro",
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"Protocol" : "ap_ctrl_hs",
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"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "0", "ap_idle" : "1",
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"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
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"II" : "0",
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"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2077921", "EstimateLatencyMax" : "2077921",
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"Combinational" : "0",
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"Datapath" : "0",
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"ClockEnable" : "0",
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"HasSubDataflow" : "0",
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"InDataflowNetwork" : "0",
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"HasNonBlockingOperation" : "0",
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"Port" : [
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{"Name" : "src1_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src1_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "src1_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src1_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "src1_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src1_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "src2_data_stream_0_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src2_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "src2_data_stream_1_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src2_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "src2_data_stream_2_V", "Type" : "Fifo", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "src2_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "dst_data_stream_0_V", "Type" : "Fifo", "Direction" : "O",
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"BlockSignal" : [
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{"Name" : "dst_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "dst_data_stream_1_V", "Type" : "Fifo", "Direction" : "O",
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"BlockSignal" : [
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{"Name" : "dst_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "dst_data_stream_2_V", "Type" : "Fifo", "Direction" : "O",
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"BlockSignal" : [
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{"Name" : "dst_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]}]}]}
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set ArgLastReadFirstWriteLatency {
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AddWeighted {
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src1_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
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src1_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
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src1_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
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dst_data_stream_0_V {Type O LastRead -1 FirstWrite 4}
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dst_data_stream_1_V {Type O LastRead -1 FirstWrite 4}
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dst_data_stream_2_V {Type O LastRead -1 FirstWrite 4}}
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arithm_pro {
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src1_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
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src1_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
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src1_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_0_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_1_V {Type I LastRead 3 FirstWrite -1}
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src2_data_stream_2_V {Type I LastRead 3 FirstWrite -1}
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dst_data_stream_0_V {Type O LastRead -1 FirstWrite 4}
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dst_data_stream_1_V {Type O LastRead -1 FirstWrite 4}
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dst_data_stream_2_V {Type O LastRead -1 FirstWrite 4}}}
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set hasDtUnsupportedChannel 0
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set PerformanceInfo {[
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{"Name" : "Latency", "Min" : "2077922", "Max" : "2077922"}
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, {"Name" : "Interval", "Min" : "2077922", "Max" : "2077922"}
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]}
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set PipelineEnableSignalInfo {[
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]}
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set Spec2ImplPortList {
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src1_data_stream_0_V { ap_fifo { { src1_data_stream_0_V_dout fifo_data 0 8 } { src1_data_stream_0_V_empty_n fifo_status 0 1 } { src1_data_stream_0_V_read fifo_update 1 1 } } }
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src1_data_stream_1_V { ap_fifo { { src1_data_stream_1_V_dout fifo_data 0 8 } { src1_data_stream_1_V_empty_n fifo_status 0 1 } { src1_data_stream_1_V_read fifo_update 1 1 } } }
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src1_data_stream_2_V { ap_fifo { { src1_data_stream_2_V_dout fifo_data 0 8 } { src1_data_stream_2_V_empty_n fifo_status 0 1 } { src1_data_stream_2_V_read fifo_update 1 1 } } }
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src2_data_stream_0_V { ap_fifo { { src2_data_stream_0_V_dout fifo_data 0 8 } { src2_data_stream_0_V_empty_n fifo_status 0 1 } { src2_data_stream_0_V_read fifo_update 1 1 } } }
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src2_data_stream_1_V { ap_fifo { { src2_data_stream_1_V_dout fifo_data 0 8 } { src2_data_stream_1_V_empty_n fifo_status 0 1 } { src2_data_stream_1_V_read fifo_update 1 1 } } }
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src2_data_stream_2_V { ap_fifo { { src2_data_stream_2_V_dout fifo_data 0 8 } { src2_data_stream_2_V_empty_n fifo_status 0 1 } { src2_data_stream_2_V_read fifo_update 1 1 } } }
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dst_data_stream_0_V { ap_fifo { { dst_data_stream_0_V_din fifo_data 1 8 } { dst_data_stream_0_V_full_n fifo_status 0 1 } { dst_data_stream_0_V_write fifo_update 1 1 } } }
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dst_data_stream_1_V { ap_fifo { { dst_data_stream_1_V_din fifo_data 1 8 } { dst_data_stream_1_V_full_n fifo_status 0 1 } { dst_data_stream_1_V_write fifo_update 1 1 } } }
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dst_data_stream_2_V { ap_fifo { { dst_data_stream_2_V_din fifo_data 1 8 } { dst_data_stream_2_V_full_n fifo_status 0 1 } { dst_data_stream_2_V_write fifo_update 1 1 } } }
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}
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