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172 lines
12 KiB
Tcl
172 lines
12 KiB
Tcl
set moduleName AXIvideo2Mat
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set isTopModule 0
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set isTaskLevelControl 1
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set isCombinational 0
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set isDatapathOnly 0
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set isFreeRunPipelineModule 0
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set isPipelined 0
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set pipeline_type none
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set FunctionProtocol ap_ctrl_hs
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set isOneStateSeq 0
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set ProfileFlag 0
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set StallSigGenFlag 0
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set isEnableWaveformDebug 1
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set C_modelName {AXIvideo2Mat}
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set C_modelType { void 0 }
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set C_modelArgList {
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{ AXI_video_strm_V_data_V int 24 regular {axi_s 0 volatile { stream_in Data } } }
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{ AXI_video_strm_V_keep_V int 3 regular {axi_s 0 volatile { stream_in Keep } } }
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{ AXI_video_strm_V_strb_V int 3 regular {axi_s 0 volatile { stream_in Strb } } }
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{ AXI_video_strm_V_user_V int 1 regular {axi_s 0 volatile { stream_in User } } }
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{ AXI_video_strm_V_last_V int 1 regular {axi_s 0 volatile { stream_in Last } } }
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{ AXI_video_strm_V_id_V int 1 regular {axi_s 0 volatile { stream_in ID } } }
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{ AXI_video_strm_V_dest_V int 1 regular {axi_s 0 volatile { stream_in Dest } } }
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{ img_data_stream_0_V int 8 regular {fifo 1 volatile } }
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{ img_data_stream_1_V int 8 regular {fifo 1 volatile } }
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{ img_data_stream_2_V int 8 regular {fifo 1 volatile } }
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}
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set C_modelArgMapList {[
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{ "Name" : "AXI_video_strm_V_data_V", "interface" : "axis", "bitwidth" : 24, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_keep_V", "interface" : "axis", "bitwidth" : 3, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_strb_V", "interface" : "axis", "bitwidth" : 3, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_user_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_last_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_id_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
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{ "Name" : "AXI_video_strm_V_dest_V", "interface" : "axis", "bitwidth" : 1, "direction" : "READONLY"} ,
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{ "Name" : "img_data_stream_0_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
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{ "Name" : "img_data_stream_1_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ,
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{ "Name" : "img_data_stream_2_V", "interface" : "fifo", "bitwidth" : 8, "direction" : "WRITEONLY"} ]}
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# RTL Port declarations:
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set portNum 28
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set portList {
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{ ap_clk sc_in sc_logic 1 clock -1 }
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{ ap_rst sc_in sc_logic 1 reset -1 active_high_sync }
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{ ap_start sc_in sc_logic 1 start -1 }
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{ start_full_n sc_in sc_logic 1 signal -1 }
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{ ap_done sc_out sc_logic 1 predone -1 }
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{ ap_continue sc_in sc_logic 1 continue -1 }
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{ ap_idle sc_out sc_logic 1 done -1 }
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{ ap_ready sc_out sc_logic 1 ready -1 }
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{ start_out sc_out sc_logic 1 signal -1 }
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{ start_write sc_out sc_logic 1 signal -1 }
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{ stream_in_TDATA sc_in sc_lv 24 signal 0 }
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{ stream_in_TVALID sc_in sc_logic 1 invld 6 }
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{ stream_in_TREADY sc_out sc_logic 1 inacc 6 }
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{ stream_in_TKEEP sc_in sc_lv 3 signal 1 }
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{ stream_in_TSTRB sc_in sc_lv 3 signal 2 }
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{ stream_in_TUSER sc_in sc_lv 1 signal 3 }
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{ stream_in_TLAST sc_in sc_lv 1 signal 4 }
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{ stream_in_TID sc_in sc_lv 1 signal 5 }
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{ stream_in_TDEST sc_in sc_lv 1 signal 6 }
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{ img_data_stream_0_V_din sc_out sc_lv 8 signal 7 }
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{ img_data_stream_0_V_full_n sc_in sc_logic 1 signal 7 }
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{ img_data_stream_0_V_write sc_out sc_logic 1 signal 7 }
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{ img_data_stream_1_V_din sc_out sc_lv 8 signal 8 }
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{ img_data_stream_1_V_full_n sc_in sc_logic 1 signal 8 }
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{ img_data_stream_1_V_write sc_out sc_logic 1 signal 8 }
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{ img_data_stream_2_V_din sc_out sc_lv 8 signal 9 }
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{ img_data_stream_2_V_full_n sc_in sc_logic 1 signal 9 }
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{ img_data_stream_2_V_write sc_out sc_logic 1 signal 9 }
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}
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set NewPortList {[
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{ "name": "ap_clk", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "clock", "bundle":{"name": "ap_clk", "role": "default" }} ,
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{ "name": "ap_rst", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "reset", "bundle":{"name": "ap_rst", "role": "default" }} ,
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{ "name": "ap_start", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "start", "bundle":{"name": "ap_start", "role": "default" }} ,
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{ "name": "start_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_full_n", "role": "default" }} ,
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{ "name": "ap_done", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "predone", "bundle":{"name": "ap_done", "role": "default" }} ,
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{ "name": "ap_continue", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "continue", "bundle":{"name": "ap_continue", "role": "default" }} ,
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{ "name": "ap_idle", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "done", "bundle":{"name": "ap_idle", "role": "default" }} ,
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{ "name": "ap_ready", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "ready", "bundle":{"name": "ap_ready", "role": "default" }} ,
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{ "name": "start_out", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_out", "role": "default" }} ,
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{ "name": "start_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "start_write", "role": "default" }} ,
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{ "name": "stream_in_TDATA", "direction": "in", "datatype": "sc_lv", "bitwidth":24, "type": "signal", "bundle":{"name": "AXI_video_strm_V_data_V", "role": "default" }} ,
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{ "name": "stream_in_TVALID", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "invld", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
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{ "name": "stream_in_TREADY", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "inacc", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
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{ "name": "stream_in_TKEEP", "direction": "in", "datatype": "sc_lv", "bitwidth":3, "type": "signal", "bundle":{"name": "AXI_video_strm_V_keep_V", "role": "default" }} ,
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{ "name": "stream_in_TSTRB", "direction": "in", "datatype": "sc_lv", "bitwidth":3, "type": "signal", "bundle":{"name": "AXI_video_strm_V_strb_V", "role": "default" }} ,
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{ "name": "stream_in_TUSER", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_user_V", "role": "default" }} ,
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{ "name": "stream_in_TLAST", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_last_V", "role": "default" }} ,
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{ "name": "stream_in_TID", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_id_V", "role": "default" }} ,
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{ "name": "stream_in_TDEST", "direction": "in", "datatype": "sc_lv", "bitwidth":1, "type": "signal", "bundle":{"name": "AXI_video_strm_V_dest_V", "role": "default" }} ,
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{ "name": "img_data_stream_0_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "din" }} ,
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{ "name": "img_data_stream_0_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "full_n" }} ,
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{ "name": "img_data_stream_0_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_0_V", "role": "write" }} ,
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{ "name": "img_data_stream_1_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "din" }} ,
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{ "name": "img_data_stream_1_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "full_n" }} ,
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{ "name": "img_data_stream_1_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_1_V", "role": "write" }} ,
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{ "name": "img_data_stream_2_V_din", "direction": "out", "datatype": "sc_lv", "bitwidth":8, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "din" }} ,
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{ "name": "img_data_stream_2_V_full_n", "direction": "in", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "full_n" }} ,
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{ "name": "img_data_stream_2_V_write", "direction": "out", "datatype": "sc_logic", "bitwidth":1, "type": "signal", "bundle":{"name": "img_data_stream_2_V", "role": "write" }} ]}
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set RtlHierarchyInfo {[
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{"ID" : "0", "Level" : "0", "Path" : "`AUTOTB_DUT_INST", "Parent" : "",
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"CDFG" : "AXIvideo2Mat",
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"Protocol" : "ap_ctrl_hs",
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"ControlExist" : "1", "ap_start" : "1", "ap_ready" : "1", "ap_done" : "1", "ap_continue" : "1", "ap_idle" : "1",
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"Pipeline" : "None", "UnalignedPipeline" : "0", "RewindPipeline" : "0", "ProcessNetwork" : "0",
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"II" : "0",
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"VariableLatency" : "1", "ExactLatency" : "-1", "EstimateLatencyMin" : "2079003", "EstimateLatencyMax" : "2079003",
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"Combinational" : "0",
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"Datapath" : "0",
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"ClockEnable" : "0",
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"HasSubDataflow" : "0",
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"InDataflowNetwork" : "1",
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"HasNonBlockingOperation" : "0",
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"Port" : [
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{"Name" : "AXI_video_strm_V_data_V", "Type" : "Axis", "Direction" : "I",
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"BlockSignal" : [
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{"Name" : "stream_in_TDATA_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "AXI_video_strm_V_keep_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "AXI_video_strm_V_strb_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "AXI_video_strm_V_user_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "AXI_video_strm_V_last_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "AXI_video_strm_V_id_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "AXI_video_strm_V_dest_V", "Type" : "Axis", "Direction" : "I"},
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{"Name" : "img_data_stream_0_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"BlockSignal" : [
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{"Name" : "img_data_stream_0_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "img_data_stream_1_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"BlockSignal" : [
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{"Name" : "img_data_stream_1_V_blk_n", "Type" : "RtlSignal"}]},
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{"Name" : "img_data_stream_2_V", "Type" : "Fifo", "Direction" : "O", "DependentProc" : "0", "DependentChan" : "0",
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"BlockSignal" : [
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{"Name" : "img_data_stream_2_V_blk_n", "Type" : "RtlSignal"}]}]}]}
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set ArgLastReadFirstWriteLatency {
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AXIvideo2Mat {
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AXI_video_strm_V_data_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_keep_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_strb_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_user_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_last_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_id_V {Type I LastRead 6 FirstWrite -1}
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AXI_video_strm_V_dest_V {Type I LastRead 6 FirstWrite -1}
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img_data_stream_0_V {Type O LastRead -1 FirstWrite 5}
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img_data_stream_1_V {Type O LastRead -1 FirstWrite 5}
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img_data_stream_2_V {Type O LastRead -1 FirstWrite 5}}}
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set hasDtUnsupportedChannel 0
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set PerformanceInfo {[
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{"Name" : "Latency", "Min" : "2079003", "Max" : "2079003"}
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, {"Name" : "Interval", "Min" : "2079003", "Max" : "2079003"}
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]}
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set PipelineEnableSignalInfo {[
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{"Pipeline" : "1", "EnableSignal" : "ap_enable_pp1"}
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]}
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set Spec2ImplPortList {
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AXI_video_strm_V_data_V { axis { { stream_in_TDATA in_data 0 24 } } }
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AXI_video_strm_V_keep_V { axis { { stream_in_TKEEP in_data 0 3 } } }
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AXI_video_strm_V_strb_V { axis { { stream_in_TSTRB in_data 0 3 } } }
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AXI_video_strm_V_user_V { axis { { stream_in_TUSER in_data 0 1 } } }
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AXI_video_strm_V_last_V { axis { { stream_in_TLAST in_data 0 1 } } }
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AXI_video_strm_V_id_V { axis { { stream_in_TID in_data 0 1 } } }
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AXI_video_strm_V_dest_V { axis { { stream_in_TVALID in_vld 0 1 } { stream_in_TREADY in_acc 1 1 } { stream_in_TDEST in_data 0 1 } } }
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img_data_stream_0_V { ap_fifo { { img_data_stream_0_V_din fifo_data 1 8 } { img_data_stream_0_V_full_n fifo_status 0 1 } { img_data_stream_0_V_write fifo_update 1 1 } } }
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img_data_stream_1_V { ap_fifo { { img_data_stream_1_V_din fifo_data 1 8 } { img_data_stream_1_V_full_n fifo_status 0 1 } { img_data_stream_1_V_write fifo_update 1 1 } } }
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img_data_stream_2_V { ap_fifo { { img_data_stream_2_V_din fifo_data 1 8 } { img_data_stream_2_V_full_n fifo_status 0 1 } { img_data_stream_2_V_write fifo_update 1 1 } } }
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}
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