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M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1/.autopilot/db/autopilot.flow.log

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INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Tue Feb 14 18:44:57 +0100 2023
Execute config_clock -quiet -name default -period 10 -default=false
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Command import_lib done; 0.128 sec.
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
Command ap_source done; 0.192 sec.
Command ap_source done; 0.196 sec.
Execute set_part xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
Command ap_part_info done; 0.754 sec.
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
Execute get_default_platform
Execute license_isbetapart xc7z020
Command license_isbetapart done; error code: 1;
Execute ap_part_info -data single -name xc7z020-clg400-1
Execute ap_part_info -name xc7z020-clg400-1 -data resources
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Execute add_library xilinx/zynq/zynq_fpv6
Execute get_default_platform
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute get_default_platform
Command set_part done; 0.917 sec.
Execute ap_part_info -data single -name xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data resources
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Command open_solution done; 1.282 sec.
Execute csim_design -quiet
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute ap_part_info -name xc7z020clg400-1 -data info
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
Command csim_design done; error code: 2; 16.432 sec.
Command ap_source done; error code: 1; 17.735 sec.
Execute cleanup_all
INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Sun Feb 14 18:45:36 +0100 2021
Execute config_clock -quiet -name default -period 10 -default=false
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
Command ap_source done; 0.121 sec.
Command ap_source done; 0.121 sec.
Execute set_part xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
Command ap_part_info done; 0.749 sec.
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
Execute get_default_platform
Execute license_isbetapart xc7z020
Command license_isbetapart done; error code: 1;
Execute ap_part_info -data single -name xc7z020-clg400-1
Execute ap_part_info -name xc7z020-clg400-1 -data resources
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Execute add_library xilinx/zynq/zynq_fpv6
Execute get_default_platform
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute get_default_platform
Command set_part done; 0.866 sec.
Execute ap_part_info -data single -name xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data resources
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Command open_solution done; 1.032 sec.
Execute csim_design -quiet
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Execute source csim/.lst_opt.tcl
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute ap_part_info -name xc7z020clg400-1 -data info
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
Command csim_design done; error code: 2; 7.141 sec.
Command ap_source done; error code: 1; 8.18 sec.
Execute cleanup_all
INFO-FLOW: Workspace C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect/solution1 opened at Sun Feb 14 18:48:34 +0100 2021
Execute config_clock -quiet -name default -period 10 -default=false
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/dsp48e1.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/plb46.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/fsl.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/axi4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/nativeAXI4.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/scripts/xilinxcoregen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/XilEDKCoreGen.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/dds_compiler.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/util.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfft.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/ip/xfir.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.gen
Command ap_source done; 0.118 sec.
Command ap_source done; 0.118 sec.
Execute set_part xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data single -quiet
Command ap_part_info done; 0.734 sec.
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute add_library xilinx/zynq/zynq:xc7z020:-clg400:-1
Execute get_default_platform
Execute license_isbetapart xc7z020
Command license_isbetapart done; error code: 1;
Execute ap_part_info -data single -name xc7z020-clg400-1
Execute ap_part_info -name xc7z020-clg400-1 -data resources
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Execute add_library xilinx/zynq/zynq_fpv6
Execute get_default_platform
Execute open_platform DefaultPlatform
Execute import_lib C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.lib
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/target_info.tcl
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/xilinx_interface.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/maxi.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/interface/saxilite.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/dsp48.hlp
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/zynq/zynq_fpv6.gen
Execute source C:/Xilinx/Vivado/2019.1/common/technology/xilinx/common/xilinx_fp.gen
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg400-1'
Execute ap_part_info -name xc7z020-clg400-1 -data info
Execute get_default_platform
Command set_part done; 0.845 sec.
Execute ap_part_info -data single -name xc7z020clg400-1
Execute ap_part_info -name xc7z020clg400-1 -data resources
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -resource {SLICE 13300} {LUT 53200} {FF 106400} {DSP48E 220} {BRAM 280} {URAM 0}
Execute ap_part_info -name xc7z020clg400-1 -data info
Execute config_chip_info -quiet -speed slow
Command open_solution done; 1.005 sec.
Execute csim_design -clean -quiet
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Execute source csim/.lst_opt.tcl
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect_test.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/rover.bmp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.cpp
Execute is_encrypted C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute is_xip C:/Users/Sasa/Documents/M2R/M2_SETI/A2/Detection_cercle/circle_detect/circle_detect.h
Execute ap_part_info -name xc7z020clg400-1 -data info
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
Command csim_design done; error code: 2; 18.709 sec.
Command ap_source done; error code: 1; 19.735 sec.
Execute cleanup_all
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