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M2_SETI/A2/Detection_cercle/edge_detect/edge_detect/solution1/.autopilot/db/AddWeighted.verbose.rpt

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================================================================
== Vivado HLS Report for 'AddWeighted'
================================================================
* Date: Tue Feb 7 10:18:47 2023
* Version: 2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)
* Project: edge_detect
* Solution: solution1
* Product family: zynq
* Target device: xc7z020-clg400-1
================================================================
== Performance Estimates
================================================================
+ Timing (ns):
* Summary:
+--------+-------+----------+------------+
| Clock | Target| Estimated| Uncertainty|
+--------+-------+----------+------------+
|ap_clk | 6.70| 4.846| 0.84|
+--------+-------+----------+------------+
+ Latency (clock cycles):
* Summary:
+---------+---------+---------+---------+---------+
| Latency | Interval | Pipeline|
| min | max | min | max | Type |
+---------+---------+---------+---------+---------+
| 2077922| 2077922| 2077922| 2077922| none |
+---------+---------+---------+---------+---------+
+ Detail:
* Instance:
+----------------------+------------+---------+---------+---------+---------+---------+
| | | Latency | Interval | Pipeline|
| Instance | Module | min | max | min | max | Type |
+----------------------+------------+---------+---------+---------+---------+---------+
|grp_arithm_pro_fu_32 |arithm_pro | 2077921| 2077921| 2077921| 2077921| none |
+----------------------+------------+---------+---------+---------+---------+---------+
* Loop:
N/A
================================================================
== Utilization Estimates
================================================================
* Summary:
+-----------------+---------+-------+--------+-------+-----+
| Name | BRAM_18K| DSP48E| FF | LUT | URAM|
+-----------------+---------+-------+--------+-------+-----+
|DSP | -| -| -| -| -|
|Expression | -| -| 0| 2| -|
|FIFO | -| -| -| -| -|
|Instance | -| -| 69| 320| -|
|Memory | -| -| -| -| -|
|Multiplexer | -| -| -| 105| -|
|Register | -| -| 4| -| -|
+-----------------+---------+-------+--------+-------+-----+
|Total | 0| 0| 73| 427| 0|
+-----------------+---------+-------+--------+-------+-----+
|Available | 280| 220| 106400| 53200| 0|
+-----------------+---------+-------+--------+-------+-----+
|Utilization (%) | 0| 0| ~0 | ~0 | 0|
+-----------------+---------+-------+--------+-------+-----+
+ Detail:
* Instance:
+----------------------+------------+---------+-------+----+-----+-----+
| Instance | Module | BRAM_18K| DSP48E| FF | LUT | URAM|
+----------------------+------------+---------+-------+----+-----+-----+
|grp_arithm_pro_fu_32 |arithm_pro | 0| 0| 69| 320| 0|
+----------------------+------------+---------+-------+----+-----+-----+
|Total | | 0| 0| 69| 320| 0|
+----------------------+------------+---------+-------+----+-----+-----+
* DSP48E:
N/A
* Memory:
N/A
* FIFO:
N/A
* Expression:
+-----------------+----------+-------+---+----+------------+------------+
| Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
+-----------------+----------+-------+---+----+------------+------------+
|ap_block_state1 | or | 0| 0| 2| 1| 1|
+-----------------+----------+-------+---+----+------------+------------+
|Total | | 0| 0| 2| 1| 1|
+-----------------+----------+-------+---+----+------------+------------+
* Multiplexer:
+---------------------------+----+-----------+-----+-----------+
| Name | LUT| Input Size| Bits| Total Bits|
+---------------------------+----+-----------+-----+-----------+
|ap_NS_fsm | 15| 3| 1| 3|
|ap_done | 9| 2| 1| 2|
|dst_data_stream_0_V_write | 9| 2| 1| 2|
|dst_data_stream_1_V_write | 9| 2| 1| 2|
|dst_data_stream_2_V_write | 9| 2| 1| 2|
|src1_data_stream_0_V_read | 9| 2| 1| 2|
|src1_data_stream_1_V_read | 9| 2| 1| 2|
|src1_data_stream_2_V_read | 9| 2| 1| 2|
|src2_data_stream_0_V_read | 9| 2| 1| 2|
|src2_data_stream_1_V_read | 9| 2| 1| 2|
|src2_data_stream_2_V_read | 9| 2| 1| 2|
+---------------------------+----+-----------+-----+-----------+
|Total | 105| 23| 11| 23|
+---------------------------+----+-----------+-----+-----------+
* Register:
+-----------------------------------+---+----+-----+-----------+
| Name | FF| LUT| Bits| Const Bits|
+-----------------------------------+---+----+-----+-----------+
|ap_CS_fsm | 2| 0| 2| 0|
|ap_done_reg | 1| 0| 1| 0|
|grp_arithm_pro_fu_32_ap_start_reg | 1| 0| 1| 0|
+-----------------------------------+---+----+-----+-----------+
|Total | 4| 0| 4| 0|
+-----------------------------------+---+----+-----+-----------+
================================================================
== Interface
================================================================
* Summary:
+------------------------------+-----+-----+------------+----------------------+--------------+
| RTL Ports | Dir | Bits| Protocol | Source Object | C Type |
+------------------------------+-----+-----+------------+----------------------+--------------+
|ap_clk | in | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_rst | in | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_start | in | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_done | out | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_continue | in | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_idle | out | 1| ap_ctrl_hs | AddWeighted | return value |
|ap_ready | out | 1| ap_ctrl_hs | AddWeighted | return value |
|src1_data_stream_0_V_dout | in | 8| ap_fifo | src1_data_stream_0_V | pointer |
|src1_data_stream_0_V_empty_n | in | 1| ap_fifo | src1_data_stream_0_V | pointer |
|src1_data_stream_0_V_read | out | 1| ap_fifo | src1_data_stream_0_V | pointer |
|src1_data_stream_1_V_dout | in | 8| ap_fifo | src1_data_stream_1_V | pointer |
|src1_data_stream_1_V_empty_n | in | 1| ap_fifo | src1_data_stream_1_V | pointer |
|src1_data_stream_1_V_read | out | 1| ap_fifo | src1_data_stream_1_V | pointer |
|src1_data_stream_2_V_dout | in | 8| ap_fifo | src1_data_stream_2_V | pointer |
|src1_data_stream_2_V_empty_n | in | 1| ap_fifo | src1_data_stream_2_V | pointer |
|src1_data_stream_2_V_read | out | 1| ap_fifo | src1_data_stream_2_V | pointer |
|src2_data_stream_0_V_dout | in | 8| ap_fifo | src2_data_stream_0_V | pointer |
|src2_data_stream_0_V_empty_n | in | 1| ap_fifo | src2_data_stream_0_V | pointer |
|src2_data_stream_0_V_read | out | 1| ap_fifo | src2_data_stream_0_V | pointer |
|src2_data_stream_1_V_dout | in | 8| ap_fifo | src2_data_stream_1_V | pointer |
|src2_data_stream_1_V_empty_n | in | 1| ap_fifo | src2_data_stream_1_V | pointer |
|src2_data_stream_1_V_read | out | 1| ap_fifo | src2_data_stream_1_V | pointer |
|src2_data_stream_2_V_dout | in | 8| ap_fifo | src2_data_stream_2_V | pointer |
|src2_data_stream_2_V_empty_n | in | 1| ap_fifo | src2_data_stream_2_V | pointer |
|src2_data_stream_2_V_read | out | 1| ap_fifo | src2_data_stream_2_V | pointer |
|dst_data_stream_0_V_din | out | 8| ap_fifo | dst_data_stream_0_V | pointer |
|dst_data_stream_0_V_full_n | in | 1| ap_fifo | dst_data_stream_0_V | pointer |
|dst_data_stream_0_V_write | out | 1| ap_fifo | dst_data_stream_0_V | pointer |
|dst_data_stream_1_V_din | out | 8| ap_fifo | dst_data_stream_1_V | pointer |
|dst_data_stream_1_V_full_n | in | 1| ap_fifo | dst_data_stream_1_V | pointer |
|dst_data_stream_1_V_write | out | 1| ap_fifo | dst_data_stream_1_V | pointer |
|dst_data_stream_2_V_din | out | 8| ap_fifo | dst_data_stream_2_V | pointer |
|dst_data_stream_2_V_full_n | in | 1| ap_fifo | dst_data_stream_2_V | pointer |
|dst_data_stream_2_V_write | out | 1| ap_fifo | dst_data_stream_2_V | pointer |
+------------------------------+-----+-----+------------+----------------------+--------------+
============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0
============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 2
* Pipeline : 0
* Dataflow Pipeline: 0
* FSM state transitions:
1 --> 2
2 -->
* FSM state operations:
State 1 <SV = 0> <Delay = 0.00>
ST_1 : Operation 3 [2/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 3 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
State 2 <SV = 1> <Delay = 0.00>
ST_2 : Operation 4 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 4 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 5 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 5 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 6 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src2_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 6 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 7 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 7 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 8 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 8 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 9 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %src1_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 9 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 10 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 10 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 11 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 11 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 12 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i8* %dst_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)" ---> Operation 12 'specinterface' <Predicate = true> <Delay = 0.00>
ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @arithm_pro(i8* %src1_data_stream_0_V, i8* %src1_data_stream_1_V, i8* %src1_data_stream_2_V, i8* %src2_data_stream_0_V, i8* %src2_data_stream_1_V, i8* %src2_data_stream_2_V, i8* %dst_data_stream_0_V, i8* %dst_data_stream_1_V, i8* %dst_data_stream_2_V)" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:879] ---> Operation 13 'call' <Predicate = true> <Delay = 0.00> <CoreType = "Generic"> ---> Core 0 '' <Latency = 0> <II = 1> <Delay = 1.00> <Generic> <Opcode : >
ST_2 : Operation 14 [1/1] (0.00ns) ---> "ret void" [C:/Xilinx/Vivado/2019.1/common/technology/autopilot/hls/hls_video_arithm.h:880] ---> Operation 14 'ret' <Predicate = true> <Delay = 0.00>
============================================================
+ Verbose Summary: Binding
============================================================
STG Binding:
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 0
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ src1_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ src1_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ src1_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ src2_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ src2_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ src2_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ dst_data_stream_0_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ dst_data_stream_1_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ dst_data_stream_2_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
---------------- STG Properties END ------------------
---------------- Datapath Model BEGIN ----------------
<LifeTime>
<method=bitvector/>
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
specinterface_ln0 (specinterface) [ 000]
call_ln879 (call ) [ 000]
ret_ln880 (ret ) [ 000]
</LifeTime>
<model>
<comp_list>
<comp id="0" class="1000" name="src1_data_stream_0_V">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src1_data_stream_0_V"/></StgValue>
</bind>
</comp>
<comp id="2" class="1000" name="src1_data_stream_1_V">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src1_data_stream_1_V"/></StgValue>
</bind>
</comp>
<comp id="4" class="1000" name="src1_data_stream_2_V">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src1_data_stream_2_V"/></StgValue>
</bind>
</comp>
<comp id="6" class="1000" name="src2_data_stream_0_V">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src2_data_stream_0_V"/></StgValue>
</bind>
</comp>
<comp id="8" class="1000" name="src2_data_stream_1_V">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src2_data_stream_1_V"/></StgValue>
</bind>
</comp>
<comp id="10" class="1000" name="src2_data_stream_2_V">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="src2_data_stream_2_V"/></StgValue>
</bind>
</comp>
<comp id="12" class="1000" name="dst_data_stream_0_V">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="dst_data_stream_0_V"/></StgValue>
</bind>
</comp>
<comp id="14" class="1000" name="dst_data_stream_1_V">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="dst_data_stream_1_V"/></StgValue>
</bind>
</comp>
<comp id="16" class="1000" name="dst_data_stream_2_V">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="dst_data_stream_2_V"/></StgValue>
</bind>
</comp>
<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="arithm_pro"/></StgValue>
</bind>
</comp>
<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>
<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
</bind>
</comp>
<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>
<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>
<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>
<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>
<comp id="32" class="1004" name="grp_arithm_pro_fu_32">
<pin_list>
<pin id="33" dir="0" index="0" bw="0" slack="0"/>
<pin id="34" dir="0" index="1" bw="8" slack="0"/>
<pin id="35" dir="0" index="2" bw="8" slack="0"/>
<pin id="36" dir="0" index="3" bw="8" slack="0"/>
<pin id="37" dir="0" index="4" bw="8" slack="0"/>
<pin id="38" dir="0" index="5" bw="8" slack="0"/>
<pin id="39" dir="0" index="6" bw="8" slack="0"/>
<pin id="40" dir="0" index="7" bw="8" slack="0"/>
<pin id="41" dir="0" index="8" bw="8" slack="0"/>
<pin id="42" dir="0" index="9" bw="8" slack="0"/>
<pin id="43" dir="1" index="10" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="call(48) " fcode="call"/>
<opset="call_ln879/1 "/>
</bind>
</comp>
</comp_list>
<net_list>
<net id="44"><net_src comp="18" pin="0"/><net_sink comp="32" pin=0"/></net>
<net id="45"><net_src comp="0" pin="0"/><net_sink comp="32" pin=1"/></net>
<net id="46"><net_src comp="2" pin="0"/><net_sink comp="32" pin=2"/></net>
<net id="47"><net_src comp="4" pin="0"/><net_sink comp="32" pin=3"/></net>
<net id="48"><net_src comp="6" pin="0"/><net_sink comp="32" pin=4"/></net>
<net id="49"><net_src comp="8" pin="0"/><net_sink comp="32" pin=5"/></net>
<net id="50"><net_src comp="10" pin="0"/><net_sink comp="32" pin=6"/></net>
<net id="51"><net_src comp="12" pin="0"/><net_sink comp="32" pin=7"/></net>
<net id="52"><net_src comp="14" pin="0"/><net_sink comp="32" pin=8"/></net>
<net id="53"><net_src comp="16" pin="0"/><net_sink comp="32" pin=9"/></net>
</net_list>
</model>
---------------- Datapath Model END ------------------
* FSMD analyzer results:
- Output states:
Port: dst_data_stream_0_V | {1 2 }
Port: dst_data_stream_1_V | {1 2 }
Port: dst_data_stream_2_V | {1 2 }
- Input state :
Port: AddWeighted : src1_data_stream_0_V | {1 2 }
Port: AddWeighted : src1_data_stream_1_V | {1 2 }
Port: AddWeighted : src1_data_stream_2_V | {1 2 }
Port: AddWeighted : src2_data_stream_0_V | {1 2 }
Port: AddWeighted : src2_data_stream_1_V | {1 2 }
Port: AddWeighted : src2_data_stream_2_V | {1 2 }
Port: AddWeighted : dst_data_stream_0_V | {}
Port: AddWeighted : dst_data_stream_1_V | {}
Port: AddWeighted : dst_data_stream_2_V | {}
- Chain level:
State 1
State 2
============================================================
+ Verbose Summary: Datapath Resource usage
============================================================
* Functional unit list:
|----------|----------------------|---------|---------|
| Operation| Functional Unit | FF | LUT |
|----------|----------------------|---------|---------|
| call | grp_arithm_pro_fu_32 | 73 | 166 |
|----------|----------------------|---------|---------|
| Total | | 73 | 166 |
|----------|----------------------|---------|---------|
Memories:
N/A
* Register list:
N/A
* Multiplexer (MUX) list:
|--------|------|------|------|--------|
| Comp | Pin | Size | BW | S x BW |
|--------|------|------|------|--------|
| Total | | | | 0 |
|--------|------|------|------|--------|
* Summary:
+-----------+--------+--------+
| | FF | LUT |
+-----------+--------+--------+
| Function | 73 | 166 |
| Memory | - | - |
|Multiplexer| - | - |
| Register | - | - |
+-----------+--------+--------+
| Total | 73 | 166 |
+-----------+--------+--------+
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