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152 lines
7.3 KiB
XML
152 lines
7.3 KiB
XML
<profile>
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<section name = "Vivado HLS Report for 'AddWeighted'" level="0">
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<item name = "Date">Tue Feb 7 10:18:47 2023
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</item>
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<item name = "Version">2019.1 (Build 2552052 on Fri May 24 15:28:33 MDT 2019)</item>
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<item name = "Project">edge_detect</item>
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<item name = "Solution">solution1</item>
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<item name = "Product family">zynq</item>
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<item name = "Target device">xc7z020-clg400-1</item>
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</section>
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<section name = "Performance Estimates" level="0">
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<item name = "Timing (ns)">
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<section name = "" level="1">
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<item name = "Summary"><table name="" hasTotal="0">
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<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
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<column name="ap_clk">6.70, 4.846, 0.84</column>
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</table>
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</item>
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</section>
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</item>
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<item name = "Latency (clock cycles)">
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<section name = "" level="1">
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<item name = "Summary"><table name="" hasTotal="0">
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<keys size="6">, min, max, min, max, Type</keys>
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<column name="">2077922, 2077922, 2077922, 2077922, none</column>
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</table>
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</item>
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<item name = "Detail">
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<section name = "" level="1">
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<item name = "Instance"><table name="" hasTotal="0">
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<keys size="7">Instance, Module, min, max, min, max, Type</keys>
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<column name="grp_arithm_pro_fu_32">arithm_pro, 2077921, 2077921, 2077921, 2077921, none</column>
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</table>
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</item>
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<item name = "Loop"><table name="" hasTotal="0">
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<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
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</table>
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</item>
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</section>
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</item>
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</section>
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</item>
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</section>
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<section name = "Utilization Estimates" level="0">
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<item name = "Summary"><table name="" hasTotal="1">
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<keys size="6">Name, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
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<column name="DSP">-, -, -, -, -</column>
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<column name="Expression">-, -, 0, 2, -</column>
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<column name="FIFO">-, -, -, -, -</column>
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<column name="Instance">-, -, 69, 320, -</column>
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<column name="Memory">-, -, -, -, -</column>
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<column name="Multiplexer">-, -, -, 105, -</column>
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<column name="Register">-, -, 4, -, -</column>
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<specialColumn name="Available">280, 220, 106400, 53200, 0</specialColumn>
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<specialColumn name="Utilization (%)">0, 0, ~0, ~0, 0</specialColumn>
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</table>
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</item>
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<item name = "Detail">
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<section name = "" level="1">
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<item name = "Instance"><table name="" hasTotal="1">
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<keys size="7">Instance, Module, BRAM_18K, DSP48E, FF, LUT, URAM</keys>
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<column name="grp_arithm_pro_fu_32">arithm_pro, 0, 0, 69, 320, 0</column>
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</table>
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</item>
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<item name = "DSP48E"><table name="" hasTotal="0">
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<keys size="3">Instance, Module, Expression</keys>
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</table>
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</item>
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<item name = "Memory"><table name="" hasTotal="1">
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<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
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</table>
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</item>
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<item name = "FIFO"><table name="" hasTotal="1">
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<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
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</table>
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</item>
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<item name = "Expression"><table name="" hasTotal="1">
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<keys size="7">Variable Name, Operation, DSP48E, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
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<column name="ap_block_state1">or, 0, 0, 2, 1, 1</column>
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</table>
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</item>
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<item name = "Multiplexer"><table name="" hasTotal="1">
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<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
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<column name="ap_NS_fsm">15, 3, 1, 3</column>
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<column name="ap_done">9, 2, 1, 2</column>
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<column name="dst_data_stream_0_V_write">9, 2, 1, 2</column>
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<column name="dst_data_stream_1_V_write">9, 2, 1, 2</column>
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<column name="dst_data_stream_2_V_write">9, 2, 1, 2</column>
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<column name="src1_data_stream_0_V_read">9, 2, 1, 2</column>
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<column name="src1_data_stream_1_V_read">9, 2, 1, 2</column>
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<column name="src1_data_stream_2_V_read">9, 2, 1, 2</column>
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<column name="src2_data_stream_0_V_read">9, 2, 1, 2</column>
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<column name="src2_data_stream_1_V_read">9, 2, 1, 2</column>
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<column name="src2_data_stream_2_V_read">9, 2, 1, 2</column>
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</table>
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</item>
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<item name = "Register"><table name="" hasTotal="1">
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<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
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<column name="ap_CS_fsm">2, 0, 2, 0</column>
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<column name="ap_done_reg">1, 0, 1, 0</column>
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<column name="grp_arithm_pro_fu_32_ap_start_reg">1, 0, 1, 0</column>
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</table>
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</item>
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</section>
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</item>
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</section>
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<section name = "Interface" level="0">
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<item name = "Summary"><table name="" hasTotal="0">
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<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
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<column name="ap_clk">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_rst">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_start">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_done">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_continue">in, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_idle">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="ap_ready">out, 1, ap_ctrl_hs, AddWeighted, return value</column>
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<column name="src1_data_stream_0_V_dout">in, 8, ap_fifo, src1_data_stream_0_V, pointer</column>
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<column name="src1_data_stream_0_V_empty_n">in, 1, ap_fifo, src1_data_stream_0_V, pointer</column>
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<column name="src1_data_stream_0_V_read">out, 1, ap_fifo, src1_data_stream_0_V, pointer</column>
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<column name="src1_data_stream_1_V_dout">in, 8, ap_fifo, src1_data_stream_1_V, pointer</column>
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<column name="src1_data_stream_1_V_empty_n">in, 1, ap_fifo, src1_data_stream_1_V, pointer</column>
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<column name="src1_data_stream_1_V_read">out, 1, ap_fifo, src1_data_stream_1_V, pointer</column>
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<column name="src1_data_stream_2_V_dout">in, 8, ap_fifo, src1_data_stream_2_V, pointer</column>
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<column name="src1_data_stream_2_V_empty_n">in, 1, ap_fifo, src1_data_stream_2_V, pointer</column>
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<column name="src1_data_stream_2_V_read">out, 1, ap_fifo, src1_data_stream_2_V, pointer</column>
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<column name="src2_data_stream_0_V_dout">in, 8, ap_fifo, src2_data_stream_0_V, pointer</column>
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<column name="src2_data_stream_0_V_empty_n">in, 1, ap_fifo, src2_data_stream_0_V, pointer</column>
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<column name="src2_data_stream_0_V_read">out, 1, ap_fifo, src2_data_stream_0_V, pointer</column>
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<column name="src2_data_stream_1_V_dout">in, 8, ap_fifo, src2_data_stream_1_V, pointer</column>
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<column name="src2_data_stream_1_V_empty_n">in, 1, ap_fifo, src2_data_stream_1_V, pointer</column>
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<column name="src2_data_stream_1_V_read">out, 1, ap_fifo, src2_data_stream_1_V, pointer</column>
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<column name="src2_data_stream_2_V_dout">in, 8, ap_fifo, src2_data_stream_2_V, pointer</column>
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<column name="src2_data_stream_2_V_empty_n">in, 1, ap_fifo, src2_data_stream_2_V, pointer</column>
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<column name="src2_data_stream_2_V_read">out, 1, ap_fifo, src2_data_stream_2_V, pointer</column>
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<column name="dst_data_stream_0_V_din">out, 8, ap_fifo, dst_data_stream_0_V, pointer</column>
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<column name="dst_data_stream_0_V_full_n">in, 1, ap_fifo, dst_data_stream_0_V, pointer</column>
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<column name="dst_data_stream_0_V_write">out, 1, ap_fifo, dst_data_stream_0_V, pointer</column>
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<column name="dst_data_stream_1_V_din">out, 8, ap_fifo, dst_data_stream_1_V, pointer</column>
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<column name="dst_data_stream_1_V_full_n">in, 1, ap_fifo, dst_data_stream_1_V, pointer</column>
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<column name="dst_data_stream_1_V_write">out, 1, ap_fifo, dst_data_stream_1_V, pointer</column>
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<column name="dst_data_stream_2_V_din">out, 8, ap_fifo, dst_data_stream_2_V, pointer</column>
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<column name="dst_data_stream_2_V_full_n">in, 1, ap_fifo, dst_data_stream_2_V, pointer</column>
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<column name="dst_data_stream_2_V_write">out, 1, ap_fifo, dst_data_stream_2_V, pointer</column>
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</table>
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</item>
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</section>
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</profile>
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