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1801 lines
46 KiB
XML
1801 lines
46 KiB
XML
<stg><name>ConvertScaleAbs155</name>
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<trans_list>
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<trans id="122" from="1" to="2">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="123" from="2" to="3">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln2526" val="1"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="162" from="3" to="21">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln2527" val="0"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="163" from="3" to="4">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="145" from="4" to="5">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="146" from="5" to="6">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="147" from="6" to="7">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="148" from="7" to="8">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="149" from="8" to="9">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="150" from="9" to="10">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="151" from="10" to="11">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="152" from="11" to="12">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="153" from="12" to="13">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="154" from="13" to="14">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="155" from="14" to="15">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="156" from="15" to="16">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="157" from="16" to="17">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="158" from="17" to="18">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="159" from="18" to="19">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="160" from="19" to="20">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="161" from="20" to="3">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="143" from="21" to="2">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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</trans_list>
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<state_list>
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<state id="1" st_id="1">
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<operation id="22" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="7" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:0 call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V2, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="23" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="8" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:1 call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V1, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="24" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="9" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:2 call void (...)* @_ssdm_op_SpecInterface(i8* %p_src_data_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="25" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="10" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:3 call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="26" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="11" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:4 call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V3, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="27" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="12" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:5 call void (...)* @_ssdm_op_SpecInterface(i8* %p_dst_data_stream_V4, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="28" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="13" bw="0" op_0_bw="0">
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<![CDATA[
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._crit_edge:6 br label %0
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]]></Node>
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<StgValue><ssdm name="br_ln2526"/></StgValue>
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</operation>
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</state>
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<state id="2" st_id="2">
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<operation id="29" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="15" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
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<![CDATA[
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:0 %i_0 = phi i11 [ 0, %._crit_edge ], [ %i, %loop_height_end ]
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]]></Node>
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<StgValue><ssdm name="i_0"/></StgValue>
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</operation>
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<operation id="30" st_id="2" stage="1" lat="1">
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<core>Cmp</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="16" bw="1" op_0_bw="11" op_1_bw="11">
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<![CDATA[
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:1 %icmp_ln2526 = icmp ult i11 %i_0, -968
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]]></Node>
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<StgValue><ssdm name="icmp_ln2526"/></StgValue>
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</operation>
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<operation id="31" st_id="2" stage="1" lat="1">
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<core>AddSub</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="17" bw="11" op_0_bw="11" op_1_bw="11">
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<![CDATA[
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:2 %i = add i11 %i_0, 1
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]]></Node>
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<StgValue><ssdm name="i"/></StgValue>
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</operation>
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<operation id="32" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="18" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
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<![CDATA[
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:3 call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1080, i64 1080, i64 1080)
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]]></Node>
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<StgValue><ssdm name="speclooptripcount_ln0"/></StgValue>
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</operation>
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<operation id="33" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="19" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
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<![CDATA[
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:4 br i1 %icmp_ln2526, label %loop_height_begin, label %2
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]]></Node>
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<StgValue><ssdm name="br_ln2526"/></StgValue>
|
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</operation>
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<operation id="34" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2526" val="1"/>
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</and_exp></or_exp>
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</condition>
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<Node id="21" bw="0" op_0_bw="0" op_1_bw="0">
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<![CDATA[
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loop_height_begin:0 call void (...)* @_ssdm_op_SpecLoopName([12 x i8]* @p_str7) nounwind
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]]></Node>
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<StgValue><ssdm name="specloopname_ln2526"/></StgValue>
|
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</operation>
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<operation id="35" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
|
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<condition id="-1">
|
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<or_exp><and_exp><literal name="icmp_ln2526" val="1"/>
|
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</and_exp></or_exp>
|
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</condition>
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<Node id="22" bw="32" op_0_bw="32" op_1_bw="0">
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<![CDATA[
|
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loop_height_begin:1 %tmp_18 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str7)
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]]></Node>
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<StgValue><ssdm name="tmp_18"/></StgValue>
|
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</operation>
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<operation id="36" st_id="2" stage="1" lat="1">
|
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<core>NULL</core>
|
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<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2526" val="1"/>
|
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</and_exp></or_exp>
|
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</condition>
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<Node id="23" bw="0" op_0_bw="0">
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<![CDATA[
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loop_height_begin:2 br label %1
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]]></Node>
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<StgValue><ssdm name="br_ln2527"/></StgValue>
|
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</operation>
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<operation id="37" st_id="2" stage="1" lat="1">
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<core>NULL</core>
|
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<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2526" val="0"/>
|
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</and_exp></or_exp>
|
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</condition>
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<Node id="73" bw="0">
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<![CDATA[
|
|
:0 ret void
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]]></Node>
|
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<StgValue><ssdm name="ret_ln2538"/></StgValue>
|
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</operation>
|
|
</state>
|
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|
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<state id="3" st_id="3">
|
|
|
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<operation id="38" st_id="3" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="25" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
|
|
<![CDATA[
|
|
:0 %j_0 = phi i11 [ 0, %loop_height_begin ], [ %j, %loop_width_begin ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="j_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="39" st_id="3" stage="1" lat="1">
|
|
<core>Cmp</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="26" bw="1" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
:1 %icmp_ln2527 = icmp ult i11 %j_0, -128
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="icmp_ln2527"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="40" st_id="3" stage="1" lat="1">
|
|
<core>AddSub</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="27" bw="11" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
:2 %j = add i11 %j_0, 1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="j"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="41" st_id="3" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="28" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
|
|
<![CDATA[
|
|
:3 call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1920, i64 1920, i64 1920)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="speclooptripcount_ln0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="42" st_id="3" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="29" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
|
|
<![CDATA[
|
|
:4 br i1 %icmp_ln2527, label %loop_width_begin, label %loop_height_end
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln2527"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="4" st_id="4">
|
|
|
|
<operation id="43" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="34" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:3 %tmp_20 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str12)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_20"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="44" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="35" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:4 call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specprotocol_ln676"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="45" st_id="4" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="36" bw="8" op_0_bw="8" op_1_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:5 %tmp_63 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_63"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="46" st_id="4" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="37" bw="8" op_0_bw="8" op_1_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:6 %tmp_64 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V1)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_64"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="47" st_id="4" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="38" bw="8" op_0_bw="8" op_1_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:7 %tmp_65 = call i8 @_ssdm_op_Read.ap_fifo.volatile.i8P(i8* %p_src_data_stream_V2)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_65"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="48" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="39" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:8 %empty = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str12, i32 %tmp_20)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="5" st_id="5">
|
|
|
|
<operation id="49" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="40" bw="32" op_0_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:9 %zext_ln2533 = zext i8 %tmp_63 to i32
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="zext_ln2533"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="50" st_id="5" stage="8" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="51" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="47" bw="32" op_0_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:16 %zext_ln2533_1 = zext i8 %tmp_64 to i32
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="zext_ln2533_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="52" st_id="5" stage="8" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="53" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="54" bw="32" op_0_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:23 %zext_ln2533_2 = zext i8 %tmp_65 to i32
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="zext_ln2533_2"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="54" st_id="5" stage="8" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="6" st_id="6">
|
|
|
|
<operation id="55" st_id="6" stage="7" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="56" st_id="6" stage="7" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="57" st_id="6" stage="7" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="7" st_id="7">
|
|
|
|
<operation id="58" st_id="7" stage="6" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="59" st_id="7" stage="6" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="60" st_id="7" stage="6" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="8" st_id="8">
|
|
|
|
<operation id="61" st_id="8" stage="5" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="62" st_id="8" stage="5" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="63" st_id="8" stage="5" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="9" st_id="9">
|
|
|
|
<operation id="64" st_id="9" stage="4" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="65" st_id="9" stage="4" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="66" st_id="9" stage="4" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="10" st_id="10">
|
|
|
|
<operation id="67" st_id="10" stage="3" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="68" st_id="10" stage="3" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="69" st_id="10" stage="3" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="11" st_id="11">
|
|
|
|
<operation id="70" st_id="11" stage="2" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="71" st_id="11" stage="2" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="72" st_id="11" stage="2" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="12" st_id="12">
|
|
|
|
<operation id="73" st_id="12" stage="1" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:10 %x_assign = sitofp i32 %zext_ln2533 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="74" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="42" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:11 %p_Val2_s = bitcast double %x_assign to i64
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Val2_s"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="75" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="43" bw="63" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:12 %trunc_ln368 = trunc i64 %p_Val2_s to i63
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="trunc_ln368"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="76" st_id="12" stage="1" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:17 %x_assign_3 = sitofp i32 %zext_ln2533_1 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="77" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="49" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:18 %p_Val2_40 = bitcast double %x_assign_3 to i64
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Val2_40"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="78" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="50" bw="63" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:19 %trunc_ln368_3 = trunc i64 %p_Val2_40 to i63
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="trunc_ln368_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="79" st_id="12" stage="1" lat="8">
|
|
<core>Int2Double</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="64" op_0_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:24 %x_assign_4 = sitofp i32 %zext_ln2533_2 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="x_assign_4"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="80" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="56" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:25 %p_Val2_41 = bitcast double %x_assign_4 to i64
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Val2_41"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="81" st_id="12" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="57" bw="63" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:26 %trunc_ln368_4 = trunc i64 %p_Val2_41 to i63
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="trunc_ln368_4"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="13" st_id="13">
|
|
|
|
<operation id="82" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="44" bw="64" op_0_bw="64" op_1_bw="1" op_2_bw="63">
|
|
<![CDATA[
|
|
loop_width_begin:13 %p_Result_s = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Result_s"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="83" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="45" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:14 %bitcast_ln512 = bitcast i64 %p_Result_s to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="bitcast_ln512"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="84" st_id="13" stage="7" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="85" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="51" bw="64" op_0_bw="64" op_1_bw="1" op_2_bw="63">
|
|
<![CDATA[
|
|
loop_width_begin:20 %p_Result_15 = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368_3)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Result_15"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="86" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="52" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:21 %bitcast_ln512_3 = bitcast i64 %p_Result_15 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="bitcast_ln512_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="87" st_id="13" stage="7" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="88" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="58" bw="64" op_0_bw="64" op_1_bw="1" op_2_bw="63">
|
|
<![CDATA[
|
|
loop_width_begin:27 %p_Result_16 = call i64 @_ssdm_op_BitConcatenate.i64.i1.i63(i1 false, i63 %trunc_ln368_4)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Result_16"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="89" st_id="13" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="59" bw="64" op_0_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:28 %bitcast_ln512_4 = bitcast i64 %p_Result_16 to double
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="bitcast_ln512_4"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="90" st_id="13" stage="7" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="14" st_id="14">
|
|
|
|
<operation id="91" st_id="14" stage="6" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="92" st_id="14" stage="6" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="93" st_id="14" stage="6" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="15" st_id="15">
|
|
|
|
<operation id="94" st_id="15" stage="5" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="95" st_id="15" stage="5" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="96" st_id="15" stage="5" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="16" st_id="16">
|
|
|
|
<operation id="97" st_id="16" stage="4" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="98" st_id="16" stage="4" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="99" st_id="16" stage="4" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="17" st_id="17">
|
|
|
|
<operation id="100" st_id="17" stage="3" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="101" st_id="17" stage="3" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="102" st_id="17" stage="3" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="18" st_id="18">
|
|
|
|
<operation id="103" st_id="18" stage="2" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="104" st_id="18" stage="2" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="105" st_id="18" stage="2" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="19" st_id="19">
|
|
|
|
<operation id="106" st_id="19" stage="1" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:15 %p_d_val_0 = call fastcc i8 @"operator().1"(double %bitcast_ln512) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="107" st_id="19" stage="1" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:22 %p_d_val_1 = call fastcc i8 @"operator().1"(double %bitcast_ln512_3) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_d_val_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="108" st_id="19" stage="1" lat="7">
|
|
<core></core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="8" op_0_bw="8" op_1_bw="64">
|
|
<![CDATA[
|
|
loop_width_begin:29 %tmp_24 = call fastcc i8 @"operator().1"(double %bitcast_ln512_4) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_24"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="20" st_id="20">
|
|
|
|
<operation id="109" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="31" bw="0" op_0_bw="0" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:0 call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str8) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specloopname_ln2527"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="110" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="32" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:1 %tmp_19 = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str8)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_19"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="111" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="33" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:2 call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specpipeline_ln2529"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="112" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="61" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:30 %tmp_s = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str16)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_s"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="113" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="62" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:31 call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specprotocol_ln700"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="114" st_id="20" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="63" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:32 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V, i8 %p_d_val_0)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="115" st_id="20" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="64" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:33 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V3, i8 %p_d_val_1)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="116" st_id="20" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="65" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
loop_width_begin:34 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %p_dst_data_stream_V4, i8 %tmp_24)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="117" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="66" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:35 %empty_105 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str16, i32 %tmp_s)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_105"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="118" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="67" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_width_begin:36 %empty_106 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str8, i32 %tmp_19)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_106"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="119" st_id="20" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln2527" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="68" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:37 br label %1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln2527"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="21" st_id="21">
|
|
|
|
<operation id="120" st_id="21" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="70" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_height_end:0 %empty_107 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str7, i32 %tmp_18)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_107"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="121" st_id="21" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="71" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
loop_height_end:1 br label %0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln2526"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
</state_list>
|
|
|
|
|
|
<ports>
|
|
</ports>
|
|
|
|
|
|
<dataflows>
|
|
</dataflows>
|
|
|
|
|
|
</stg>
|