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1324 lines
35 KiB
XML
1324 lines
35 KiB
XML
<stg><name>AXIvideo2Mat</name>
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<trans_list>
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<trans id="87" from="1" to="2">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="103" from="2" to="3">
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<condition id="-1">
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<or_exp><and_exp><literal name="tmp_user_V" val="1"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="104" from="2" to="2">
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<condition id="-1">
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<or_exp><and_exp><literal name="tmp_user_V" val="0"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="90" from="3" to="4">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="91" from="4" to="5">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln71" val="0"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="107" from="5" to="7">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln73" val="1"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="108" from="5" to="6">
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<condition id="-1">
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<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="106" from="6" to="5">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="98" from="7" to="8">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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<trans id="110" from="8" to="9">
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<condition id="-1">
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<or_exp><and_exp><literal name="eol_2" val="1"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="111" from="8" to="8">
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<condition id="-1">
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<or_exp><and_exp><literal name="eol_2" val="0"/>
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</and_exp></or_exp>
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</condition>
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</trans>
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<trans id="101" from="9" to="4">
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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</trans>
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</trans_list>
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<state_list>
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<state id="1" st_id="1">
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<operation id="10" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="11" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:0 call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_2_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="11" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="12" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:1 call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_1_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="12" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="13" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
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<![CDATA[
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._crit_edge:2 call void (...)* @_ssdm_op_SpecInterface(i8* %img_data_stream_0_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="13" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="14" bw="0" op_0_bw="0" op_1_bw="24" op_2_bw="3" op_3_bw="3" op_4_bw="1" op_5_bw="1" op_6_bw="1" op_7_bw="1" op_8_bw="0" op_9_bw="32" op_10_bw="32" op_11_bw="0" op_12_bw="32" op_13_bw="32" op_14_bw="0" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32" op_19_bw="32" op_20_bw="32" op_21_bw="0" op_22_bw="0">
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<![CDATA[
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._crit_edge:3 call void (...)* @_ssdm_op_SpecInterface(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V, [5 x i8]* @p_str1, i32 1, i32 1, [5 x i8]* @p_str2, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str) nounwind
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]]></Node>
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<StgValue><ssdm name="specinterface_ln0"/></StgValue>
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</operation>
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<operation id="14" st_id="1" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="15" bw="0" op_0_bw="0">
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<![CDATA[
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._crit_edge:4 br label %loop_wait_for_start
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]]></Node>
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<StgValue><ssdm name="br_ln63"/></StgValue>
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</operation>
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</state>
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<state id="2" st_id="2">
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<operation id="15" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="17" bw="0" op_0_bw="0" op_1_bw="0">
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<![CDATA[
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loop_wait_for_start:0 call void (...)* @_ssdm_op_SpecLoopName([20 x i8]* @p_str18) nounwind
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]]></Node>
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<StgValue><ssdm name="specloopname_ln65"/></StgValue>
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</operation>
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<operation id="16" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="18" bw="32" op_0_bw="32" op_1_bw="0">
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<![CDATA[
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loop_wait_for_start:1 %tmp_s = call i32 (...)* @_ssdm_op_SpecRegionBegin([20 x i8]* @p_str18)
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]]></Node>
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<StgValue><ssdm name="tmp_s"/></StgValue>
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</operation>
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<operation id="17" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="19" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
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<![CDATA[
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loop_wait_for_start:2 call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind
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]]></Node>
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<StgValue><ssdm name="specpipeline_ln66"/></StgValue>
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</operation>
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<operation id="18" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
|
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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|
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<Node id="20" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="0">
|
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<![CDATA[
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loop_wait_for_start:3 call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
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]]></Node>
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<StgValue><ssdm name="speclooptripcount_ln67"/></StgValue>
|
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</operation>
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<operation id="19" st_id="2" stage="1" lat="1">
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<core>AXI4Stream</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
|
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="21" bw="34" op_0_bw="34" op_1_bw="24" op_2_bw="3" op_3_bw="3" op_4_bw="1" op_5_bw="1" op_6_bw="1" op_7_bw="1">
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<![CDATA[
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loop_wait_for_start:4 %empty = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)
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]]></Node>
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<StgValue><ssdm name="empty"/></StgValue>
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</operation>
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<operation id="20" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="22" bw="24" op_0_bw="34">
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<![CDATA[
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loop_wait_for_start:5 %tmp_data_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 0
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]]></Node>
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<StgValue><ssdm name="tmp_data_V"/></StgValue>
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</operation>
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<operation id="21" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="23" bw="1" op_0_bw="34">
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<![CDATA[
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loop_wait_for_start:6 %tmp_user_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 3
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]]></Node>
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<StgValue><ssdm name="tmp_user_V"/></StgValue>
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</operation>
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<operation id="22" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
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</condition>
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<Node id="24" bw="1" op_0_bw="34">
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<![CDATA[
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loop_wait_for_start:7 %tmp_last_V = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty, 4
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]]></Node>
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<StgValue><ssdm name="tmp_last_V"/></StgValue>
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</operation>
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<operation id="23" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="25" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
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<![CDATA[
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loop_wait_for_start:8 %empty_108 = call i32 (...)* @_ssdm_op_SpecRegionEnd([20 x i8]* @p_str18, i32 %tmp_s)
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]]></Node>
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<StgValue><ssdm name="empty_108"/></StgValue>
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</operation>
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<operation id="24" st_id="2" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
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<condition id="-1">
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="26" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
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<![CDATA[
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loop_wait_for_start:9 br i1 %tmp_user_V, label %.preheader232.preheader, label %loop_wait_for_start
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]]></Node>
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<StgValue><ssdm name="br_ln65"/></StgValue>
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</operation>
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</state>
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<state id="3" st_id="3">
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<operation id="25" st_id="3" stage="1" lat="1">
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<core>NULL</core>
|
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<MemPortIdVec></MemPortIdVec>
|
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<condition id="-1">
|
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="28" bw="1" op_0_bw="32">
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<![CDATA[
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.preheader232.preheader:0 %sof_1 = alloca i1
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]]></Node>
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<StgValue><ssdm name="sof_1"/></StgValue>
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</operation>
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<operation id="26" st_id="3" stage="1" lat="1">
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<core>NULL</core>
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<MemPortIdVec></MemPortIdVec>
|
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<condition id="-1">
|
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="29" bw="0" op_0_bw="1" op_1_bw="1">
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<![CDATA[
|
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.preheader232.preheader:1 store i1 true, i1* %sof_1
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]]></Node>
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<StgValue><ssdm name="store_ln71"/></StgValue>
|
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</operation>
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<operation id="27" st_id="3" stage="1" lat="1">
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<core>NULL</core>
|
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<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="30" bw="0" op_0_bw="0">
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<![CDATA[
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.preheader232.preheader:2 br label %.preheader232
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]]></Node>
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<StgValue><ssdm name="br_ln71"/></StgValue>
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</operation>
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</state>
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<state id="4" st_id="4">
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<operation id="28" st_id="4" stage="1" lat="1">
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<core>NULL</core>
|
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<MemPortIdVec></MemPortIdVec>
|
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<condition id="-1">
|
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<or_exp><and_exp></and_exp></or_exp>
|
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</condition>
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<Node id="32" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
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<![CDATA[
|
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.preheader232:0 %axi_last_V_0 = phi i1 [ %axi_last_V_3, %loop_height_end ], [ %tmp_last_V, %.preheader232.preheader ]
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]]></Node>
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<StgValue><ssdm name="axi_last_V_0"/></StgValue>
|
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</operation>
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<operation id="29" st_id="4" stage="1" lat="1">
|
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<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
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|
|
<Node id="33" bw="24" op_0_bw="24" op_1_bw="0" op_2_bw="24" op_3_bw="0">
|
|
<![CDATA[
|
|
.preheader232:1 %axi_data_V_0 = phi i24 [ %axi_data_V_3, %loop_height_end ], [ %tmp_data_V, %.preheader232.preheader ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="axi_data_V_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="30" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="34" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
|
|
<![CDATA[
|
|
.preheader232:2 %t_V = phi i11 [ %i_V, %loop_height_end ], [ 0, %.preheader232.preheader ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="t_V"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="31" st_id="4" stage="1" lat="1">
|
|
<core>Cmp</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="35" bw="1" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
.preheader232:3 %icmp_ln71 = icmp eq i11 %t_V, -968
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="icmp_ln71"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="32" st_id="4" stage="1" lat="1">
|
|
<core>AddSub</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="36" bw="11" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
.preheader232:4 %i_V = add i11 %t_V, 1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="i_V"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="33" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="37" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
|
|
<![CDATA[
|
|
.preheader232:5 call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1080, i64 1080, i64 1080)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="speclooptripcount_ln0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="34" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="38" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
|
|
<![CDATA[
|
|
.preheader232:6 br i1 %icmp_ln71, label %2, label %loop_height_begin
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln71"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="35" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln71" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="40" bw="0" op_0_bw="0" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_height_begin:0 call void (...)* @_ssdm_op_SpecLoopName([12 x i8]* @p_str7) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specloopname_ln71"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="36" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln71" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="41" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_height_begin:1 %tmp_25 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str7)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_25"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="37" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln71" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="42" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
loop_height_begin:2 br label %0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln73"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="38" st_id="4" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln71" val="1"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="100" bw="0">
|
|
<![CDATA[
|
|
:0 ret void
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="ret_ln0"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="5" st_id="5">
|
|
|
|
<operation id="39" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="44" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
|
<![CDATA[
|
|
:0 %eol = phi i1 [ %axi_last_V_0, %loop_height_begin ], [ %axi_last_V_2, %hls_label_4 ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="eol"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="40" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="45" bw="24" op_0_bw="24" op_1_bw="0" op_2_bw="24" op_3_bw="0">
|
|
<![CDATA[
|
|
:1 %axi_data_V_1 = phi i24 [ %axi_data_V_0, %loop_height_begin ], [ %p_Val2_s, %hls_label_4 ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="axi_data_V_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="41" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="46" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
|
|
<![CDATA[
|
|
:2 %t_V_5 = phi i11 [ 0, %loop_height_begin ], [ %j_V, %hls_label_4 ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="t_V_5"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="42" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="47" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
|
<![CDATA[
|
|
:3 %eol_0 = phi i1 [ false, %loop_height_begin ], [ %axi_last_V_2, %hls_label_4 ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="eol_0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="43" st_id="5" stage="1" lat="1">
|
|
<core>Cmp</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="48" bw="1" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
:4 %icmp_ln73 = icmp eq i11 %t_V_5, -128
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="icmp_ln73"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="44" st_id="5" stage="1" lat="1">
|
|
<core>AddSub</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="49" bw="11" op_0_bw="11" op_1_bw="11">
|
|
<![CDATA[
|
|
:5 %j_V = add i11 %t_V_5, 1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="j_V"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="45" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="50" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
|
|
<![CDATA[
|
|
:6 call void (...)* @_ssdm_op_SpecLoopTripCount(i64 1920, i64 1920, i64 1920)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="speclooptripcount_ln0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="46" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="51" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
|
|
<![CDATA[
|
|
:7 br i1 %icmp_ln73, label %.preheader.preheader, label %loop_width_begin
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln73"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="47" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="53" bw="1" op_0_bw="1" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:0 %sof_1_load = load i1* %sof_1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="sof_1_load"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="48" st_id="5" stage="1" lat="1">
|
|
<core>LogicGate</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="57" bw="1" op_0_bw="1" op_1_bw="1">
|
|
<![CDATA[
|
|
loop_width_begin:4 %or_ln76 = or i1 %sof_1_load, %eol_0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="or_ln76"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="49" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="58" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:5 br i1 %or_ln76, label %hls_label_4, label %1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln76"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="50" st_id="5" stage="1" lat="1">
|
|
<core>AXI4Stream</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
<literal name="or_ln76" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="60" bw="34" op_0_bw="34" op_1_bw="24" op_2_bw="3" op_3_bw="3" op_4_bw="1" op_5_bw="1" op_6_bw="1" op_7_bw="1" op_8_bw="34">
|
|
<![CDATA[
|
|
:0 %empty_109 = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_109"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="51" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
<literal name="or_ln76" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="61" bw="24" op_0_bw="34">
|
|
<![CDATA[
|
|
:1 %tmp_data_V_1 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_109, 0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_data_V_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="52" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
<literal name="or_ln76" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="62" bw="1" op_0_bw="34">
|
|
<![CDATA[
|
|
:2 %tmp_last_V_1 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_109, 4
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_last_V_1"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="53" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
<literal name="or_ln76" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="63" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
:3 br label %hls_label_4
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln0"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="54" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="65" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
|
<![CDATA[
|
|
hls_label_4:0 %axi_last_V_2 = phi i1 [ %tmp_last_V_1, %1 ], [ %eol, %loop_width_begin ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="axi_last_V_2"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="55" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="66" bw="24" op_0_bw="24" op_1_bw="0" op_2_bw="24" op_3_bw="0">
|
|
<![CDATA[
|
|
hls_label_4:1 %p_Val2_s = phi i24 [ %tmp_data_V_1, %1 ], [ %axi_data_V_1, %loop_width_begin ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="p_Val2_s"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="56" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="67" bw="8" op_0_bw="24">
|
|
<![CDATA[
|
|
hls_label_4:2 %tmp = trunc i24 %p_Val2_s to i8
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="57" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="68" bw="8" op_0_bw="8" op_1_bw="24" op_2_bw="32" op_3_bw="32">
|
|
<![CDATA[
|
|
hls_label_4:3 %tmp_28 = call i8 @_ssdm_op_PartSelect.i8.i24.i32.i32(i24 %p_Val2_s, i32 8, i32 15)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_28"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="58" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="69" bw="8" op_0_bw="8" op_1_bw="24" op_2_bw="32" op_3_bw="32">
|
|
<![CDATA[
|
|
hls_label_4:4 %tmp_29 = call i8 @_ssdm_op_PartSelect.i8.i24.i32.i32(i24 %p_Val2_s, i32 16, i32 23)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_29"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="59" st_id="5" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="77" bw="0" op_0_bw="1" op_1_bw="1" op_2_bw="0" op_3_bw="1">
|
|
<![CDATA[
|
|
hls_label_4:12 store i1 false, i1* %sof_1
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="store_ln73"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="6" st_id="6">
|
|
|
|
<operation id="60" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="54" bw="0" op_0_bw="0" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:1 call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str8) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specloopname_ln73"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="61" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="55" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:2 %tmp_26 = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str8)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_26"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="62" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="56" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
|
|
<![CDATA[
|
|
loop_width_begin:3 call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specpipeline_ln75"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="63" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="70" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
hls_label_4:5 %tmp_30 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str16)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_30"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="64" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="71" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0">
|
|
<![CDATA[
|
|
hls_label_4:6 call void (...)* @_ssdm_op_SpecProtocol(i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specprotocol_ln700"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="65" st_id="6" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="72" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
hls_label_4:7 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_0_V, i8 %tmp)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="66" st_id="6" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="73" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
hls_label_4:8 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_1_V, i8 %tmp_28)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="67" st_id="6" stage="1" lat="1">
|
|
<core>FIFO</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="74" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8">
|
|
<![CDATA[
|
|
hls_label_4:9 call void @_ssdm_op_Write.ap_fifo.volatile.i8P(i8* %img_data_stream_2_V, i8 %tmp_29)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="write_ln703"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="68" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="75" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
hls_label_4:10 %empty_110 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str16, i32 %tmp_30)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_110"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="69" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="76" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
hls_label_4:11 %empty_111 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str8, i32 %tmp_26)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_111"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="70" st_id="6" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="icmp_ln73" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="78" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
hls_label_4:13 br label %0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln73"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="7" st_id="7">
|
|
|
|
<operation id="71" st_id="7" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="80" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
.preheader.preheader:0 br label %.preheader
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln96"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="8" st_id="8">
|
|
|
|
<operation id="72" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="82" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
|
<![CDATA[
|
|
.preheader:0 %axi_last_V_3 = phi i1 [ %tmp_last_V_2, %loop_wait_for_eol ], [ %eol, %.preheader.preheader ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="axi_last_V_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="73" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="83" bw="24" op_0_bw="24" op_1_bw="0" op_2_bw="24" op_3_bw="0">
|
|
<![CDATA[
|
|
.preheader:1 %axi_data_V_3 = phi i24 [ %tmp_data_V_2, %loop_wait_for_eol ], [ %axi_data_V_1, %.preheader.preheader ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="axi_data_V_3"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="74" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="84" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
|
|
<![CDATA[
|
|
.preheader:2 %eol_2 = phi i1 [ %tmp_last_V_2, %loop_wait_for_eol ], [ %eol_0, %.preheader.preheader ]
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="eol_2"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="75" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="85" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
|
|
<![CDATA[
|
|
.preheader:3 br i1 %eol_2, label %loop_height_end, label %loop_wait_for_eol
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln96"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="76" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="87" bw="0" op_0_bw="0" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_wait_for_eol:0 call void (...)* @_ssdm_op_SpecLoopName([18 x i8]* @p_str19) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specloopname_ln96"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="77" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="88" bw="32" op_0_bw="32" op_1_bw="0">
|
|
<![CDATA[
|
|
loop_wait_for_eol:1 %tmp_27 = call i32 (...)* @_ssdm_op_SpecRegionBegin([18 x i8]* @p_str19)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_27"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="78" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="89" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
|
|
<![CDATA[
|
|
loop_wait_for_eol:2 call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="specpipeline_ln97"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="79" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="90" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="0">
|
|
<![CDATA[
|
|
loop_wait_for_eol:3 call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 0, i32 0, [1 x i8]* @p_str) nounwind
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="speclooptripcount_ln98"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="80" st_id="8" stage="1" lat="1">
|
|
<core>AXI4Stream</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="91" bw="34" op_0_bw="34" op_1_bw="24" op_2_bw="3" op_3_bw="3" op_4_bw="1" op_5_bw="1" op_6_bw="1" op_7_bw="1" op_8_bw="34">
|
|
<![CDATA[
|
|
loop_wait_for_eol:4 %empty_112 = call { i24, i3, i3, i1, i1, i1, i1 } @_ssdm_op_Read.axis.volatile.i24P.i3P.i3P.i1P.i1P.i1P.i1P(i24* %AXI_video_strm_V_data_V, i3* %AXI_video_strm_V_keep_V, i3* %AXI_video_strm_V_strb_V, i1* %AXI_video_strm_V_user_V, i1* %AXI_video_strm_V_last_V, i1* %AXI_video_strm_V_id_V, i1* %AXI_video_strm_V_dest_V)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_112"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="81" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="92" bw="24" op_0_bw="34">
|
|
<![CDATA[
|
|
loop_wait_for_eol:5 %tmp_data_V_2 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_112, 0
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_data_V_2"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="82" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="93" bw="1" op_0_bw="34">
|
|
<![CDATA[
|
|
loop_wait_for_eol:6 %tmp_last_V_2 = extractvalue { i24, i3, i3, i1, i1, i1, i1 } %empty_112, 4
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="tmp_last_V_2"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="83" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="94" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_wait_for_eol:7 %empty_113 = call i32 (...)* @_ssdm_op_SpecRegionEnd([18 x i8]* @p_str19, i32 %tmp_27)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_113"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="84" st_id="8" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp><literal name="eol_2" val="0"/>
|
|
</and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="95" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
loop_wait_for_eol:8 br label %.preheader
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln103"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
|
|
<state id="9" st_id="9">
|
|
|
|
<operation id="85" st_id="9" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="97" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
|
|
<![CDATA[
|
|
loop_height_end:0 %empty_114 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str7, i32 %tmp_25)
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="empty_114"/></StgValue>
|
|
</operation>
|
|
|
|
<operation id="86" st_id="9" stage="1" lat="1">
|
|
<core>NULL</core>
|
|
<MemPortIdVec></MemPortIdVec>
|
|
<condition id="-1">
|
|
<or_exp><and_exp></and_exp></or_exp>
|
|
</condition>
|
|
|
|
<Node id="98" bw="0" op_0_bw="0">
|
|
<![CDATA[
|
|
loop_height_end:1 br label %.preheader232
|
|
|
|
]]></Node>
|
|
<StgValue><ssdm name="br_ln71"/></StgValue>
|
|
</operation>
|
|
</state>
|
|
</state_list>
|
|
|
|
|
|
<ports>
|
|
</ports>
|
|
|
|
|
|
<dataflows>
|
|
</dataflows>
|
|
|
|
|
|
</stg>
|