riscv O3

Rapport/Fibonnaci/plot.py

@@ -3,7 +3,8 @@ from sklearn.linear_model import LinearRegression
 import numpy as np
 
 Y = [1100, 2150, 3200, 4250, 5300, 6350, 7400, 8450, 9500]
-Y2 = [1100, 2150, 3200, 4250, 5300, 6350, 7400, 8450, 9500]
+YO1 = [796, 1546, 2296, 3046, 3796,  4546, 5296, 6046, 6796]
+YO3 = [764, 1514, 2264, 3014, 3764, 4514, 5264, 6014, 6764]
 Y_ARM = [912, 1736 , 2560 , 3352, 4216, 5304 , 5840,  6704, 7464]
 Y_ARMO3 = [173, 329, 480, 633, 789, 945, 1098, 1308, 1406]
 Y_gcc = [2296, 5119, 6715, 9078, 10830, 12541, 15041, 16780, 18883]
@@ -13,49 +14,50 @@ f_RISCV1 = 50e6
 f_RISCV2 = 100e6
 f_ARM = 800e6
 f_PC = 2400e6
-X = []
+X = [50, 100, 150, 200, 250, 300, 350, 400, 450]
+
+plt.scatter(X, Y, color="b", label="RISCV -O0")
+plt.scatter(X, YO1, color="b", marker="x", label="RISCV -O1")
+plt.scatter(X, YO3, color="b", marker="^", label="RISCV -O3")
+plt.scatter(X, Y_ARM, color="g",  label="ARM -O0")
+plt.scatter(X, Y_ARMO3, color="g", marker="x",label="ARM -O3")
+plt.scatter(X, Y_gcc, color="r", label="desktop -O0 2,4Ghz")
+plt.scatter(X, Y_O3, color="r",marker="x", label="desktop -O3 2,4Ghz")
+
+plt.xlim([0, 500])
+plt.ylim([50, 20000])
+plt.legend()
+plt.title("Cycles d'exécution en fonction de n_max")
+plt.ylabel("Cycles")
+plt.xlabel("N_max")
+plt.show()
+plt.savefig("fibonacci_cycles.png")
 
 for i in range(9) :
     Y[i] = (Y[i]*1e9)/f_RISCV1
-    Y2[i] = (Y2[i]*1e9)/f_RISCV2
+    YO1[i] = (YO1[i]*1e9)/f_RISCV1
+    YO3[i] = (YO3[i]*1e9)/f_RISCV1
     Y_ARM[i] = (Y_ARM[i]*1e9)/f_ARM
     Y_ARMO3[i] = (Y_ARMO3[i]*1e9)/f_ARM
     Y_gcc[i] = (Y_gcc[i]*1e9)/f_PC
     Y_O3[i] = (Y_O3[i]*1e9)/f_PC
-    X.append(50*(1+i))
     
-plt.scatter(X, Y, color="b", marker="x", label="RISCV 50 MHz")
-plt.scatter(X, Y2, color="g", marker="x", label="RISCV 100 MHz")
-plt.scatter(X, Y_ARM, color="b", label="mesures ARM")
-plt.scatter(X, Y_ARMO3, color="g", label="mesures ARM -O3")
-plt.scatter(X, Y_gcc, color="b",marker="*", label="desktop -O0 2,4Ghz")
-plt.scatter(X, Y_O3, color="g", marker="*",label="desktop -O3 2,4Ghz")
 
-x = np.array(X).reshape(-1, 1)
+plt.scatter(X, Y, color="b", label="RISCV -O0")
-y = np.array(Y).reshape(-1, 1)
+plt.scatter(X, YO1, color="b", marker="x", label="RISCV -O1")
-y2 = np.array(Y2).reshape(-1, 1)
+plt.scatter(X, YO3, color="b", marker="^", label="RISCV -O3")
-reg = LinearRegression().fit(x, y)
+plt.scatter(X, Y_ARM, color="g",  label="ARM -O0")
-reg2 = LinearRegression().fit(x, y2)
+plt.scatter(X, Y_ARMO3, color="g", marker="x",label="ARM -O3")
-print("score obtenu : " + str(reg.score(x, y)))
+plt.scatter(X, Y_gcc, color="r", label="desktop -O0 2,4Ghz")
-print("score obtenu : " + str(reg.score(x, y2)))
+plt.scatter(X, Y_O3, color="r",marker="x", label="desktop -O3 2,4Ghz")
-print("attente à zéro : {}".format(reg.intercept_))
-print("attente à zéro : {}".format(reg2.intercept_))
 
-x_lin = [0, max(X)]
-y_lin = [reg.predict(np.array([0]).reshape(-1, 1)), reg.predict(np.array([x_lin[1]]).reshape(-1, 1))]
-y_lin2 = [reg2.predict(np.array([0]).reshape(-1, 1)), reg2.predict(np.array([x_lin[1]]).reshape(-1, 1))]
-y_lin = [y_lin[0][0][0], y_lin[1][0][0]]
-y_lin2 = [y_lin2[0][0][0], y_lin2[1][0][0]]
-
-# plt.plot(x_lin, y_lin, color = "r", label="RegLin 50 score : {:.4f}".format(reg.score(x, y)))
-# plt.plot(x_lin, y_lin2, color = "r")
 plt.yscale("log")
 
 plt.xlim([0, 500])
-plt.ylim([0, 1000000])
+plt.ylim([50, 500000])
 plt.legend()
 plt.title("Temps d'exécution en fonction de n_max")
 plt.ylabel("T (ns)")
 plt.xlabel("N_max")
 plt.show()
-plt.savefig("M2_SETI/A2/fibonacci/linéaire.png")
+plt.savefig("fibonacci_temps.png")

bandwidth_test/main.c

@@ -0,0 +1,105 @@
+// #################################################################################################
+// # << NEORV32 - "Hello World" Demo Program >>                                                    #
+// # ********************************************************************************************* #
+// # BSD 3-Clause License                                                                          #
+// #                                                                                               #
+// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
+// #                                                                                               #
+// # Redistribution and use in source and binary forms, with or without modification, are          #
+// # permitted provided that the following conditions are met:                                     #
+// #                                                                                               #
+// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
+// #    conditions and the following disclaimer.                                                   #
+// #                                                                                               #
+// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
+// #    conditions and the following disclaimer in the documentation and/or other materials        #
+// #    provided with the distribution.                                                            #
+// #                                                                                               #
+// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
+// #    endorse or promote products derived from this software without specific prior written      #
+// #    permission.                                                                                #
+// #                                                                                               #
+// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
+// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
+// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
+// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
+// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
+// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
+// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
+// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
+// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
+// # ********************************************************************************************* #
+// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
+// #################################################################################################
+
+
+/**********************************************************************//**
+ * @file hello_world/main.c
+ * @author Stephan Nolting
+ * @brief Classic 'hello world' demo program.
+ **************************************************************************/
+
+#include <neorv32.h>
+
+
+/**********************************************************************//**
+ * @name User configuration
+ **************************************************************************/
+/**@{*/
+/** UART BAUD rate */
+#define BAUD_RATE 19200
+/**@}*/
+
+void mult(uint32_t *n, uint32_t *y){
+  uint32_t N = *n;
+  uint32_t x[N];
+  uint32_t a = 10;
+
+  for(uint32_t i=0; i<N; i++){
+    y[i] = a * x[i];
+  }
+}
+
+
+/**********************************************************************//**
+ * Main function; prints some fancy stuff via UART.
+ *
+ * @note This program requires the UART interface to be synthesized.
+ *
+ * @return 0 if execution was successful
+ **************************************************************************/
+int main() {
+  long Begin_Time, End_Time, User_Time;
+  uint32_t n_max;
+  // capture all exceptions and give debug info via UART
+  // this is not required, but keeps us safe
+  neorv32_rte_setup();
+
+  // init UART at default baud rate, no parity bits, no HW flow control
+  neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
+
+  // check available hardware extensions and compare with compiler flags
+  neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
+
+  // say hello
+  neorv32_uart0_puts("Memory management cycles measure :\n");
+  neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
+
+  uint32_t y[2000]; 
+  for(uint8_t i=1; i<10; i++){
+    n_max = 200*i;
+
+    Begin_Time = (long)neorv32_mtime_get_time();
+
+    for(uint32_t j=0; j<10; j++){
+      mult(&n_max, y);
+
+    }
+    End_Time = (long)neorv32_mtime_get_time();
+    User_Time = End_Time - Begin_Time;
+
+    neorv32_uart0_printf("NEORV32: mean cycles N = %u :      %u\n",n_max, (uint32_t)User_Time/10);
+  }
+  neorv32_uart0_puts("end:\n");
+  return 0;
+}

bandwidth_test/makefile

@@ -0,0 +1,4 @@
+# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
+NEORV32_HOME ?= ../neorv32
+
+include $(NEORV32_HOME)/sw/common/common.mk

fibonacci/main.c

@@ -91,17 +91,17 @@ int main() {
   neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
 
   for(uint8_t i=1; i<10; i++){
-    n_max = 50;
+    n_max = 50*i;
     Begin_Time = (long)neorv32_mtime_get_time();
 
-    for(uint32_t j=0; j<2*454546; j++){
+    for(uint32_t j=0; j<10; j++){
       fibonnaci(&n_max, &f);
 
     }
     End_Time = (long)neorv32_mtime_get_time();
     User_Time = End_Time - Begin_Time;
-
+    neorv32_uart0_printf("y last : %d \n", f);
-    neorv32_uart0_printf("NEORV32: mean cycles n_max = %u :      %u\n",n_max, (uint32_t)User_Time);
+    neorv32_uart0_printf("NEORV32: mean cycles n_max = %u :      %u\n",n_max, (uint32_t)User_Time/10);
   }
   neorv32_uart0_puts("end:\n");
   return 0;

fibonacci/makefile

@@ -1,4 +1,4 @@
 # Modify this variable to fit your NEORV32 setup (neorv32 home folder)
-NEORV32_HOME ?= ../../..
+NEORV32_HOME ?= ../neorv32
 
 include $(NEORV32_HOME)/sw/common/common.mk

neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd

@@ -43,8 +43,8 @@ entity neorv32_test_setup_bootloader is
   generic (
     -- adapt these for your setup --
     CLOCK_FREQUENCY   : natural := 50000000; -- clock frequency of clk_i in Hz
-    MEM_INT_IMEM_SIZE : natural := 16*1024;   -- size of processor-internal instruction memory in bytes
+    MEM_INT_IMEM_SIZE : natural := 32*1024;   -- size of processor-internal instruction memory in bytes
-    MEM_INT_DMEM_SIZE : natural := 8*1024     -- size of processor-internal data memory in bytes
+    MEM_INT_DMEM_SIZE : natural := 32*1024     -- size of processor-internal data memory in bytes
   );
   port (
     -- Global control --

proj_quartus/db/altsyncram_s6q1.tdf

@@ -0,0 +1,284 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=13 WIDTHAD_B=13 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC  VERSION_END
+
+
+-- Copyright (C) 2022  Intel Corporation. All rights reserved.
+--  Your use of Intel Corporation's design tools, logic functions 
+--  and other software and tools, and any partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Intel Program License 
+--  Subscription Agreement, the Intel Quartus Prime License Agreement,
+--  the Intel FPGA IP License Agreement, or other applicable license
+--  agreement, including, without limitation, that your use is for
+--  the sole purpose of programming logic devices manufactured by
+--  Intel and sold by Intel or its authorized distributors.  Please
+--  refer to the applicable agreement for further details, at
+--  https://fpgasoftware.intel.com/eula.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 8 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_s6q1
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	data_a[7..0]	:	input;
+	q_b[7..0]	:	output;
+	rden_b	:	input;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 8,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[7..0].clk0 = clock0;
+	ram_block1a[7..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[7..0].portawe = wren_a;
+	ram_block1a[7..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[7..0].portbre = rden_b;
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
+END;
+--VALID FILE

proj_quartus/db/test.asm.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678267862173 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678285658625 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678267862173 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  8 10:31:02 2023 " "Processing started: Wed Mar  8 10:31:02 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678267862173 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678267862173 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285658625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  8 15:27:38 2023 " "Processing started: Wed Mar  8 15:27:38 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285658625 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678285658625 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678267862173 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678285658625 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678267862688 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678285659231 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678267867494 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678285664207 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "543 " "Peak virtual memory: 543 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678267867877 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  8 10:31:07 2023 " "Processing ended: Wed Mar  8 10:31:07 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678267867877 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678267867877 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678267867877 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678267867877 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "559 " "Peak virtual memory: 559 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  8 15:27:44 2023 " "Processing ended: Wed Mar  8 15:27:44 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678285664411 ""}