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256 lines
217 KiB
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256 lines
217 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678285044824 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285044825 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:17:24 2023 " "Processing started: Wed Mar 8 15:17:24 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285044825 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285044825 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bootloarder_1 -c test " "Command: quartus_map --read_settings_files=on --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285044825 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678285045060 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678285045060 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_test_setup_bootloader-neorv32_test_setup_bootloader_rtl " "Found design unit 1: neorv32_test_setup_bootloader-neorv32_test_setup_bootloader_rtl" { } { { "../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051562 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_test_setup_bootloader " "Found entity 1: neorv32_test_setup_bootloader" { } { { "../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051562 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051562 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_imem.default.vhd 1 0 " "Found 1 design units, including 0 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_imem.default.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_imem-neorv32_imem_rtl " "Found design unit 1: neorv32_imem-neorv32_imem_rtl" { } { { "../neorv32/rtl/core/mem/neorv32_imem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_imem.default.vhd" 46 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051563 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051563 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_dmem.default.vhd 1 0 " "Found 1 design units, including 0 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_dmem.default.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_dmem-neorv32_dmem_rtl " "Found design unit 1: neorv32_dmem-neorv32_dmem_rtl" { } { { "../neorv32/rtl/core/mem/neorv32_dmem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_dmem.default.vhd" 42 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051564 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051564 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xirq.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xirq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_xirq-neorv32_xirq_rtl " "Found design unit 1: neorv32_xirq-neorv32_xirq_rtl" { } { { "../neorv32/rtl/core/neorv32_xirq.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xirq.vhd" 72 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051565 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_xirq " "Found entity 1: neorv32_xirq" { } { { "../neorv32/rtl/core/neorv32_xirq.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xirq.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051565 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd 4 2 " "Found 4 design units, including 2 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_xip-neorv32_xip_rtl " "Found design unit 1: neorv32_xip-neorv32_xip_rtl" { } { { "../neorv32/rtl/core/neorv32_xip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd" 82 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051566 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 neorv32_xip_phy-neorv32_xip_phy_rtl " "Found design unit 2: neorv32_xip_phy-neorv32_xip_phy_rtl" { } { { "../neorv32/rtl/core/neorv32_xip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd" 501 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051566 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_xip " "Found entity 1: neorv32_xip" { } { { "../neorv32/rtl/core/neorv32_xip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051566 ""} { "Info" "ISGN_ENTITY_NAME" "2 neorv32_xip_phy " "Found entity 2: neorv32_xip_phy" { } { { "../neorv32/rtl/core/neorv32_xip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_xip.vhd" 476 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051566 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051566 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wishbone.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wishbone.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_wishbone-neorv32_wishbone_rtl " "Found design unit 1: neorv32_wishbone-neorv32_wishbone_rtl" { } { { "../neorv32/rtl/core/neorv32_wishbone.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wishbone.vhd" 104 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051567 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_wishbone " "Found entity 1: neorv32_wishbone" { } { { "../neorv32/rtl/core/neorv32_wishbone.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wishbone.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051567 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051567 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wdt.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wdt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_wdt-neorv32_wdt_rtl " "Found design unit 1: neorv32_wdt-neorv32_wdt_rtl" { } { { "../neorv32/rtl/core/neorv32_wdt.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wdt.vhd" 74 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051568 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_wdt " "Found entity 1: neorv32_wdt" { } { { "../neorv32/rtl/core/neorv32_wdt.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_wdt.vhd" 50 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051568 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_uart-neorv32_uart_rtl " "Found design unit 1: neorv32_uart-neorv32_uart_rtl" { } { { "../neorv32/rtl/core/neorv32_uart.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd" 99 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051570 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_uart " "Found entity 1: neorv32_uart" { } { { "../neorv32/rtl/core/neorv32_uart.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd" 68 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051570 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_twi.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_twi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_twi-neorv32_twi_rtl " "Found design unit 1: neorv32_twi-neorv32_twi_rtl" { } { { "../neorv32/rtl/core/neorv32_twi.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_twi.vhd" 71 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051571 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_twi " "Found entity 1: neorv32_twi" { } { { "../neorv32/rtl/core/neorv32_twi.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_twi.vhd" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051571 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051571 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd 6 3 " "Found 6 design units, including 3 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_trng-neorv32_trng_rtl " "Found design unit 1: neorv32_trng-neorv32_trng_rtl" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 63 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 neoTRNG-neoTRNG_rtl " "Found design unit 2: neoTRNG-neoTRNG_rtl" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 310 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 neoTRNG_cell-neoTRNG_cell_rtl " "Found design unit 3: neoTRNG_cell-neoTRNG_cell_rtl" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 638 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_trng " "Found entity 1: neorv32_trng" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} { "Info" "ISGN_ENTITY_NAME" "2 neoTRNG " "Found entity 2: neoTRNG" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 292 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} { "Info" "ISGN_ENTITY_NAME" "3 neoTRNG_cell " "Found entity 3: neoTRNG_cell" { } { { "../neorv32/rtl/core/neorv32_trng.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_trng.vhd" 622 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051572 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_top-neorv32_top_rtl " "Found design unit 1: neorv32_top-neorv32_top_rtl" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 239 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051575 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_top " "Found entity 1: neorv32_top" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051575 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_sysinfo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_sysinfo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_sysinfo-neorv32_sysinfo_rtl " "Found design unit 1: neorv32_sysinfo-neorv32_sysinfo_rtl" { } { { "../neorv32/rtl/core/neorv32_sysinfo.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_sysinfo.vhd" 99 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051576 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_sysinfo " "Found entity 1: neorv32_sysinfo" { } { { "../neorv32/rtl/core/neorv32_sysinfo.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_sysinfo.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051576 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051576 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_spi.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_spi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_spi-neorv32_spi_rtl " "Found design unit 1: neorv32_spi-neorv32_spi_rtl" { } { { "../neorv32/rtl/core/neorv32_spi.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_spi.vhd" 73 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051577 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_spi " "Found entity 1: neorv32_spi" { } { { "../neorv32/rtl/core/neorv32_spi.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_spi.vhd" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051577 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../neorv32/rtl/core/neorv32_sdi.vhd " "Can't analyze file -- file ../neorv32/rtl/core/neorv32_sdi.vhd is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1678285051578 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_pwm.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_pwm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_pwm-neorv32_pwm_rtl " "Found design unit 1: neorv32_pwm-neorv32_pwm_rtl" { } { { "../neorv32/rtl/core/neorv32_pwm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_pwm.vhd" 67 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051579 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_pwm " "Found entity 1: neorv32_pwm" { } { { "../neorv32/rtl/core/neorv32_pwm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_pwm.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051579 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd 4 0 " "Found 4 design units, including 0 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_package (neorv32) " "Found design unit 1: neorv32_package (neorv32)" { } { { "../neorv32/rtl/core/neorv32_package.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd" 39 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051583 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 neorv32_package-body " "Found design unit 2: neorv32_package-body" { } { { "../neorv32/rtl/core/neorv32_package.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd" 2289 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051583 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 neorv32_bootloader_image (neorv32) " "Found design unit 3: neorv32_bootloader_image (neorv32)" { } { { "../neorv32/rtl/core/neorv32_package.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd" 2609 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051583 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 neorv32_application_image (neorv32) " "Found design unit 4: neorv32_application_image (neorv32)" { } { { "../neorv32/rtl/core/neorv32_package.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_package.vhd" 2626 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051583 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051583 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_onewire.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_onewire.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_onewire-neorv32_onewire_rtl " "Found design unit 1: neorv32_onewire-neorv32_onewire_rtl" { } { { "../neorv32/rtl/core/neorv32_onewire.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_onewire.vhd" 73 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051584 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_onewire " "Found entity 1: neorv32_onewire" { } { { "../neorv32/rtl/core/neorv32_onewire.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_onewire.vhd" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051584 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051584 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_neoled.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_neoled.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_neoled-neorv32_neoled_rtl " "Found design unit 1: neorv32_neoled-neorv32_neoled_rtl" { } { { "../neorv32/rtl/core/neorv32_neoled.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_neoled.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051585 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_neoled " "Found entity 1: neorv32_neoled" { } { { "../neorv32/rtl/core/neorv32_neoled.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_neoled.vhd" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051585 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_mtime.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_mtime.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_mtime-neorv32_mtime_rtl " "Found design unit 1: neorv32_mtime-neorv32_mtime_rtl" { } { { "../neorv32/rtl/core/neorv32_mtime.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_mtime.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051586 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_mtime " "Found entity 1: neorv32_mtime" { } { { "../neorv32/rtl/core/neorv32_mtime.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_mtime.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051586 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051586 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_imem.entity.vhd 1 1 " "Found 1 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_imem.entity.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 neorv32_imem " "Found entity 1: neorv32_imem" { } { { "../neorv32/rtl/core/neorv32_imem.entity.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_imem.entity.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051586 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051586 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd 4 2 " "Found 4 design units, including 2 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_icache-neorv32_icache_rtl " "Found design unit 1: neorv32_icache-neorv32_icache_rtl" { } { { "../neorv32/rtl/core/neorv32_icache.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd" 73 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 neorv32_icache_memory-neorv32_icache_memory_rtl " "Found design unit 2: neorv32_icache_memory-neorv32_icache_memory_rtl" { } { { "../neorv32/rtl/core/neorv32_icache.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd" 414 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_icache " "Found entity 1: neorv32_icache" { } { { "../neorv32/rtl/core/neorv32_icache.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} { "Info" "ISGN_ENTITY_NAME" "2 neorv32_icache_memory " "Found entity 2: neorv32_icache_memory" { } { { "../neorv32/rtl/core/neorv32_icache.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_icache.vhd" 385 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051588 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gptmr.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gptmr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_gptmr-neorv32_gptmr_rtl " "Found design unit 1: neorv32_gptmr-neorv32_gptmr_rtl" { } { { "../neorv32/rtl/core/neorv32_gptmr.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gptmr.vhd" 66 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_gptmr " "Found entity 1: neorv32_gptmr" { } { { "../neorv32/rtl/core/neorv32_gptmr.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gptmr.vhd" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051588 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051588 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gpio.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gpio.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_gpio-neorv32_gpio_rtl " "Found design unit 1: neorv32_gpio-neorv32_gpio_rtl" { } { { "../neorv32/rtl/core/neorv32_gpio.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gpio.vhd" 63 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051589 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_gpio " "Found entity 1: neorv32_gpio" { } { { "../neorv32/rtl/core/neorv32_gpio.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_gpio.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051589 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051589 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_fifo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_fifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_fifo-neorv32_fifo_rtl " "Found design unit 1: neorv32_fifo-neorv32_fifo_rtl" { } { { "../neorv32/rtl/core/neorv32_fifo.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_fifo.vhd" 67 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051590 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_fifo " "Found entity 1: neorv32_fifo" { } { { "../neorv32/rtl/core/neorv32_fifo.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_fifo.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051590 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051590 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_dmem.entity.vhd 1 1 " "Found 1 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_dmem.entity.vhd" { { "Info" "ISGN_ENTITY_NAME" "1 neorv32_dmem " "Found entity 1: neorv32_dmem" { } { { "../neorv32/rtl/core/neorv32_dmem.entity.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_dmem.entity.vhd" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051590 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051590 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dtm.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dtm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_debug_dtm-neorv32_debug_dtm_rtl " "Found design unit 1: neorv32_debug_dtm-neorv32_debug_dtm_rtl" { } { { "../neorv32/rtl/core/neorv32_debug_dtm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dtm.vhd" 70 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051591 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_debug_dtm " "Found entity 1: neorv32_debug_dtm" { } { { "../neorv32/rtl/core/neorv32_debug_dtm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dtm.vhd" 41 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051591 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051591 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dm.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_debug_dm-neorv32_debug_dm_rtl " "Found design unit 1: neorv32_debug_dm-neorv32_debug_dm_rtl" { } { { "../neorv32/rtl/core/neorv32_debug_dm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dm.vhd" 88 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051593 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_debug_dm " "Found entity 1: neorv32_debug_dm" { } { { "../neorv32/rtl/core/neorv32_debug_dm.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_debug_dm.vhd" 58 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051593 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051593 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_regfile.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_regfile.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_regfile-neorv32_cpu_regfile_rtl " "Found design unit 1: neorv32_cpu_regfile-neorv32_cpu_regfile_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_regfile.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_regfile.vhd" 78 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051594 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_regfile " "Found entity 1: neorv32_cpu_regfile" { } { { "../neorv32/rtl/core/neorv32_cpu_regfile.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_regfile.vhd" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051594 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051594 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_decompressor.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_decompressor.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_decompressor-neorv32_cpu_decompressor_rtl " "Found design unit 1: neorv32_cpu_decompressor-neorv32_cpu_decompressor_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_decompressor.vhd" 55 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051595 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_decompressor " "Found entity 1: neorv32_cpu_decompressor" { } { { "../neorv32/rtl/core/neorv32_cpu_decompressor.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_decompressor.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051595 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051595 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_cp_shifter-neorv32_cpu_cp_shifter_rtl " "Found design unit 1: neorv32_cpu_cp_shifter-neorv32_cpu_cp_shifter_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" 65 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051596 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_cp_shifter " "Found entity 1: neorv32_cpu_cp_shifter" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051596 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_cp_muldiv-neorv32_cpu_cp_muldiv_rtl " "Found design unit 1: neorv32_cpu_cp_muldiv-neorv32_cpu_cp_muldiv_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" 67 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051596 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_cp_muldiv " "Found entity 1: neorv32_cpu_cp_muldiv" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051596 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd 6 3 " "Found 6 design units, including 3 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_cp_fpu-neorv32_cpu_cp_fpu_rtl " "Found design unit 1: neorv32_cpu_cp_fpu-neorv32_cpu_cp_fpu_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 80 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 neorv32_cpu_cp_fpu_normalizer-neorv32_cpu_cp_fpu_normalizer_rtl " "Found design unit 2: neorv32_cpu_cp_fpu_normalizer-neorv32_cpu_cp_fpu_normalizer_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 1200 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 neorv32_cpu_cp_fpu_f2i-neorv32_cpu_cp_fpu_f2i_rtl " "Found design unit 3: neorv32_cpu_cp_fpu_f2i-neorv32_cpu_cp_fpu_f2i_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 1585 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_cp_fpu " "Found entity 1: neorv32_cpu_cp_fpu" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 58 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} { "Info" "ISGN_ENTITY_NAME" "2 neorv32_cpu_cp_fpu_normalizer " "Found entity 2: neorv32_cpu_cp_fpu_normalizer" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 1178 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} { "Info" "ISGN_ENTITY_NAME" "3 neorv32_cpu_cp_fpu_f2i " "Found entity 3: neorv32_cpu_cp_fpu_f2i" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd" 1565 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051600 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051600 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_cp_cfu-neorv32_cpu_cp_cfu_rtl " "Found design unit 1: neorv32_cpu_cp_cfu-neorv32_cpu_cp_cfu_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" 68 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051601 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_cp_cfu " "Found entity 1: neorv32_cpu_cp_cfu" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051601 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051601 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_cp_bitmanip-neorv32_cpu_cp_bitmanip_rtl " "Found design unit 1: neorv32_cpu_cp_bitmanip-neorv32_cpu_cp_bitmanip_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" 73 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051602 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_cp_bitmanip " "Found entity 1: neorv32_cpu_cp_bitmanip" { } { { "../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051602 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051602 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_control-neorv32_cpu_control_rtl " "Found design unit 1: neorv32_cpu_control-neorv32_cpu_control_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 132 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051607 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_control " "Found entity 1: neorv32_cpu_control" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 52 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051607 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051607 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_bus-neorv32_cpu_bus_rtl " "Found design unit 1: neorv32_cpu_bus-neorv32_cpu_bus_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 85 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051609 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_bus " "Found entity 1: neorv32_cpu_bus" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051609 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051608 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu_alu-neorv32_cpu_cpu_rtl " "Found design unit 1: neorv32_cpu_alu-neorv32_cpu_cpu_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu_alu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd" 79 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051609 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu_alu " "Found entity 1: neorv32_cpu_alu" { } { { "../neorv32/rtl/core/neorv32_cpu_alu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051609 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051609 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cpu-neorv32_cpu_rtl " "Found design unit 1: neorv32_cpu-neorv32_cpu_rtl" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 116 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051611 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cpu " "Found entity 1: neorv32_cpu" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051611 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cfs.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cfs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_cfs-neorv32_cfs_rtl " "Found design unit 1: neorv32_cfs-neorv32_cfs_rtl" { } { { "../neorv32/rtl/core/neorv32_cfs.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cfs.vhd" 78 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051611 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_cfs " "Found entity 1: neorv32_cfs" { } { { "../neorv32/rtl/core/neorv32_cfs.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cfs.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051611 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_busswitch.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_busswitch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_busswitch-neorv32_busswitch_rtl " "Found design unit 1: neorv32_busswitch-neorv32_busswitch_rtl" { } { { "../neorv32/rtl/core/neorv32_busswitch.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_busswitch.vhd" 91 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051612 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_busswitch " "Found entity 1: neorv32_busswitch" { } { { "../neorv32/rtl/core/neorv32_busswitch.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_busswitch.vhd" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051612 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051612 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bus_keeper.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bus_keeper.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_bus_keeper-neorv32_bus_keeper_rtl " "Found design unit 1: neorv32_bus_keeper-neorv32_bus_keeper_rtl" { } { { "../neorv32/rtl/core/neorv32_bus_keeper.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bus_keeper.vhd" 70 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051613 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_bus_keeper " "Found entity 1: neorv32_bus_keeper" { } { { "../neorv32/rtl/core/neorv32_bus_keeper.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bus_keeper.vhd" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051613 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bootloader_image.vhd 1 0 " "Found 1 design units, including 0 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bootloader_image.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_bootloader_image-body " "Found design unit 1: neorv32_bootloader_image-body" { } { { "../neorv32/rtl/core/neorv32_bootloader_image.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_bootloader_image.vhd" 8 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051614 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051614 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_boot_rom.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_boot_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_boot_rom-neorv32_boot_rom_rtl " "Found design unit 1: neorv32_boot_rom-neorv32_boot_rom_rtl" { } { { "../neorv32/rtl/core/neorv32_boot_rom.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_boot_rom.vhd" 58 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051614 ""} { "Info" "ISGN_ENTITY_NAME" "1 neorv32_boot_rom " "Found entity 1: neorv32_boot_rom" { } { { "../neorv32/rtl/core/neorv32_boot_rom.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_boot_rom.vhd" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051614 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051614 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_application_image.vhd 1 0 " "Found 1 design units, including 0 entities, in source file /home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_application_image.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 neorv32_application_image-body " "Found design unit 1: neorv32_application_image-body" { } { { "../neorv32/rtl/core/neorv32_application_image.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_application_image.vhd" 8 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285051615 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285051615 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "neorv32_test_setup_bootloader " "Elaborating entity \"neorv32_test_setup_bootloader\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678285051803 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_top neorv32_top:neorv32_top_inst " "Elaborating entity \"neorv32_top\" for hierarchy \"neorv32_top:neorv32_top_inst\"" { } { { "../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" "neorv32_top_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd" 69 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285051819 ""}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rstn_ext neorv32_top.vhd(254) " "Verilog HDL or VHDL warning at neorv32_top.vhd(254): object \"rstn_ext\" assigned a value but never read" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 254 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1678285051823 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cpu_s neorv32_top.vhd(282) " "Verilog HDL or VHDL warning at neorv32_top.vhd(282): object \"cpu_s\" assigned a value but never read" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 282 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1678285051823 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "xip_enable neorv32_top.vhd(388) " "Verilog HDL or VHDL warning at neorv32_top.vhd(388): object \"xip_enable\" assigned a value but never read" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 388 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1678285051824 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "xip_page neorv32_top.vhd(389) " "Verilog HDL or VHDL warning at neorv32_top.vhd(389): object \"xip_page\" assigned a value but never read" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 389 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1678285051824 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Peripherals = GPIO MTIME UART0 \" neorv32_top.vhd(395) " "VHDL Assertion Statement at neorv32_top.vhd(395): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Peripherals = GPIO MTIME UART0 \" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 395 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051824 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM).\" neorv32_top.vhd(420) " "VHDL Assertion Statement at neorv32_top.vhd(420): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM).\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 420 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051824 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst " "Elaborating entity \"neorv32_cpu\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "neorv32_cpu_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 542 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285051865 ""}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"The NEORV32 RISC-V Processor - github.com/stnolting/neorv32\" neorv32_cpu.vhd(165) " "VHDL Assertion Statement at neorv32_cpu.vhd(165): assertion is false - report \"The NEORV32 RISC-V Processor - github.com/stnolting/neorv32\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 165 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051867 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 CPU CONFIG NOTE: Core ISA ('MARCH') = RV32IMC_Zicsr_Zicntr\" neorv32_cpu.vhd(168) " "VHDL Assertion Statement at neorv32_cpu.vhd(168): assertion is false - report \"NEORV32 CPU CONFIG NOTE: Core ISA ('MARCH') = RV32IMC_Zicsr_Zicntr\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 168 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051867 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 CPU NOTE: Assuming this is real hardware.\" neorv32_cpu.vhd(190) " "VHDL Assertion Statement at neorv32_cpu.vhd(190): assertion is false - report \"NEORV32 CPU NOTE: Assuming this is real hardware.\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 190 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051867 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 CPU CONFIG NOTE: Boot from address 0xffff0000.\" neorv32_cpu.vhd(200) " "VHDL Assertion Statement at neorv32_cpu.vhd(200): assertion is false - report \"NEORV32 CPU CONFIG NOTE: Boot from address 0xffff0000.\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 200 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285051869 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst"}
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{ "Warning" "WVRFX_VHDL_ASSERT_ALWAYS_OCCURS_WARNING" "\"NEORV32 CPU CONFIG WARNING! Overriding <CPU_IPB_ENTRIES> configuration (setting =2) because C ISA extension is enabled.\" neorv32_cpu.vhd(214) " "VHDL Assertion Statement at neorv32_cpu.vhd(214): assertion is false - report \"NEORV32 CPU CONFIG WARNING! Overriding <CPU_IPB_ENTRIES> configuration (setting =2) because C ISA extension is enabled.\" (WARNING)" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 214 0 0 } } } 0 10651 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (WARNING)" 0 0 "Analysis & Synthesis" 0 -1 1678285051869 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_control neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst " "Elaborating entity \"neorv32_cpu_control\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "neorv32_cpu_control_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 260 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 ""}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(249) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(249): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 249 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(251) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(251): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 251 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(253) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(253): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 253 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(255) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(255): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 255 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(257) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(257): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 257 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051902 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(365) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(365): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 365 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285051903 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "neorv32_cpu_control.vhd(1143) " "Verilog HDL or VHDL warning at neorv32_cpu_control.vhd(1143): conditional expression evaluates to a constant" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 1143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "Analysis & Synthesis" 0 -1 1678285051944 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "csr neorv32_cpu_control.vhd(1686) " "VHDL Process Statement warning at neorv32_cpu_control.vhd(1686): inferring latch(es) for signal or variable \"csr\", which holds its previous value in one or more paths through the process" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 1686 0 0 } } } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1678285052100 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(2074) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(2074): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 2074 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052103 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(2480) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(2480): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 2480 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052222 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_control.vhd(2517) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_control.vhd(2517): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 2517 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052229 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Warning" "WVRFX_VHDL_IGNORED_ASSIGNMENT_TO_NULL_RANGE" "neorv32_cpu_control.vhd(2550) " "VHDL warning at neorv32_cpu_control.vhd(2550): ignored assignment of value to null range" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 2550 0 0 } } } 0 10296 "VHDL warning at %1!s!: ignored assignment of value to null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052240 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_fifo neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst\|neorv32_fifo:\\prefetch_buffer:0:prefetch_buffer_inst " "Elaborating entity \"neorv32_fifo\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst\|neorv32_fifo:\\prefetch_buffer:0:prefetch_buffer_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "\\prefetch_buffer:0:prefetch_buffer_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 494 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052465 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_decompressor neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst\|neorv32_cpu_decompressor:\\neorv32_cpu_decompressor_inst_true:neorv32_cpu_decompressor_inst " "Elaborating entity \"neorv32_cpu_decompressor\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_control:neorv32_cpu_control_inst\|neorv32_cpu_decompressor:\\neorv32_cpu_decompressor_inst_true:neorv32_cpu_decompressor_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu_control.vhd" "\\neorv32_cpu_decompressor_inst_true:neorv32_cpu_decompressor_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_control.vhd" 591 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052473 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_regfile neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst " "Elaborating entity \"neorv32_cpu_regfile\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "neorv32_cpu_regfile_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 351 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052483 ""}
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{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 5 " "Parameter WIDTHAD_A set to 5" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 32 " "Parameter NUMWORDS_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 32 " "Parameter WIDTH_B set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 5 " "Parameter WIDTHAD_B set to 5" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 32 " "Parameter NUMWORDS_B set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__2 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__2\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 5 " "Parameter WIDTHAD_A set to 5" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 32 " "Parameter NUMWORDS_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 32 " "Parameter WIDTH_B set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 5 " "Parameter WIDTHAD_B set to 5" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 32 " "Parameter NUMWORDS_B set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285052549 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285052549 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1678285052549 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1 " "Elaborating entity \"altsyncram\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\"" { } { } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052593 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1 " "Elaborated megafunction instantiation \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052594 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1 " "Instantiated megafunction \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 5 " "Parameter \"WIDTHAD_A\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 32 " "Parameter \"NUMWORDS_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 32 " "Parameter \"WIDTH_B\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 5 " "Parameter \"WIDTHAD_B\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 32 " "Parameter \"NUMWORDS_B\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285052594 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678285052594 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u2n1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_u2n1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u2n1 " "Found entity 1: altsyncram_u2n1" { } { { "db/altsyncram_u2n1.tdf" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/db/altsyncram_u2n1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285052631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285052631 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_u2n1 neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\|altsyncram_u2n1:auto_generated " "Elaborating entity \"altsyncram_u2n1\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_regfile:neorv32_cpu_regfile_inst\|altsyncram:reg_file\[0\]\[31\]__1\|altsyncram_u2n1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/seti/intelFPGA/22.1std/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052632 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_alu neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst " "Elaborating entity \"neorv32_cpu_alu\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "neorv32_cpu_alu_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 377 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052641 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_cp_shifter neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst\|neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst " "Elaborating entity \"neorv32_cpu_cp_shifter\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst\|neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu_alu.vhd" "neorv32_cpu_cp_shifter_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052658 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_cp_muldiv neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst\|neorv32_cpu_cp_muldiv:\\neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst " "Elaborating entity \"neorv32_cpu_cp_muldiv\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_alu:neorv32_cpu_alu_inst\|neorv32_cpu_cp_muldiv:\\neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu_alu.vhd" "\\neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_alu.vhd" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052667 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_cpu_bus neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_bus:neorv32_cpu_bus_inst " "Elaborating entity \"neorv32_cpu_bus\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_cpu:neorv32_cpu_inst\|neorv32_cpu_bus:neorv32_cpu_bus_inst\"" { } { { "../neorv32/rtl/core/neorv32_cpu.vhd" "neorv32_cpu_bus_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu.vhd" 414 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052698 ""}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(114) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(114): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 114 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(115) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(115): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 115 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(116) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(116): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 116 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(117) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(117): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 117 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(118) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(118): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 118 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(119) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(119): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 119 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(120) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(120): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 120 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(121) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(121): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 121 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(122) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(122): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 122 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052699 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(427) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(427): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 427 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052702 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(446) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(446): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 446 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052702 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(467) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(467): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 467 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052702 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Warning" "WVRFX_VHDL_NULL_RANGE" "neorv32_cpu_bus.vhd(500) " "VHDL Subtype or Type Declaration warning at neorv32_cpu_bus.vhd(500): subtype or type has null range" { } { { "../neorv32/rtl/core/neorv32_cpu_bus.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_cpu_bus.vhd" 500 0 0 } } } 0 10445 "VHDL Subtype or Type Declaration warning at %1!s!: subtype or type has null range" 0 0 "Analysis & Synthesis" 0 -1 1678285052703 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_busswitch neorv32_top:neorv32_top_inst\|neorv32_busswitch:neorv32_busswitch_inst " "Elaborating entity \"neorv32_busswitch\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_busswitch:neorv32_busswitch_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "neorv32_busswitch_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 691 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052719 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_bus_keeper neorv32_top:neorv32_top_inst\|neorv32_bus_keeper:neorv32_bus_keeper_inst " "Elaborating entity \"neorv32_bus_keeper\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_bus_keeper:neorv32_bus_keeper_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "neorv32_bus_keeper_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 763 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052728 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_imem neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst " "Elaborating entity \"neorv32_imem\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_int_imem_inst_true:neorv32_int_imem_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 799 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052735 ""}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic IMEM.\" neorv32_imem.default.vhd(89) " "VHDL Assertion Statement at neorv32_imem.default.vhd(89): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic IMEM.\" (NOTE)" { } { { "../neorv32/rtl/core/mem/neorv32_imem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_imem.default.vhd" 89 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285052846 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_imem:\neorv32_int_imem_inst_true:neorv32_int_imem_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as blank RAM (32768 bytes).\" neorv32_imem.default.vhd(96) " "VHDL Assertion Statement at neorv32_imem.default.vhd(96): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal IMEM as blank RAM (32768 bytes).\" (NOTE)" { } { { "../neorv32/rtl/core/mem/neorv32_imem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_imem.default.vhd" 96 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285052846 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_imem:\neorv32_int_imem_inst_true:neorv32_int_imem_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_dmem neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst " "Elaborating entity \"neorv32_dmem\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 828 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052862 ""}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic DMEM.\" neorv32_dmem.default.vhd(72) " "VHDL Assertion Statement at neorv32_dmem.default.vhd(72): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Using DEFAULT platform-agnostic DMEM.\" (NOTE)" { } { { "../neorv32/rtl/core/mem/neorv32_dmem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_dmem.default.vhd" 72 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285052883 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_dmem:\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst"}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, 16384 bytes).\" neorv32_dmem.default.vhd(75) " "VHDL Assertion Statement at neorv32_dmem.default.vhd(75): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal DMEM (RAM, 16384 bytes).\" (NOTE)" { } { { "../neorv32/rtl/core/mem/neorv32_dmem.default.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/mem/neorv32_dmem.default.vhd" 75 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285052883 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_dmem:\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_boot_rom neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst " "Elaborating entity \"neorv32_boot_rom\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 856 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052893 ""}
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{ "Info" "IVRFX_VHDL_ASSERT_ALWAYS_OCCURS_INFO" "\"NEORV32 PROCESSOR CONFIG NOTE: Implementing internal bootloader ROM (4096 bytes).\" neorv32_boot_rom.vhd(81) " "VHDL Assertion Statement at neorv32_boot_rom.vhd(81): assertion is false - report \"NEORV32 PROCESSOR CONFIG NOTE: Implementing internal bootloader ROM (4096 bytes).\" (NOTE)" { } { { "../neorv32/rtl/core/neorv32_boot_rom.vhd" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_boot_rom.vhd" 81 0 0 } } } 0 10544 "VHDL Assertion Statement at %2!s!: assertion is false - report %1!s! (NOTE)" 0 0 "Analysis & Synthesis" 0 -1 1678285052909 "|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_boot_rom:\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst"}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_gpio neorv32_top:neorv32_top_inst\|neorv32_gpio:\\neorv32_gpio_inst_true:neorv32_gpio_inst " "Elaborating entity \"neorv32_gpio\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_gpio:\\neorv32_gpio_inst_true:neorv32_gpio_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_gpio_inst_true:neorv32_gpio_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 1059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052951 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_mtime neorv32_top:neorv32_top_inst\|neorv32_mtime:\\neorv32_mtime_inst_true:neorv32_mtime_inst " "Elaborating entity \"neorv32_mtime\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_mtime:\\neorv32_mtime_inst_true:neorv32_mtime_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_mtime_inst_true:neorv32_mtime_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052965 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_uart neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst " "Elaborating entity \"neorv32_uart\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "\\neorv32_uart0_inst_true:neorv32_uart0_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 1157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285052982 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_fifo neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst\|neorv32_fifo:tx_engine_fifo_inst " "Elaborating entity \"neorv32_fifo\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst\|neorv32_fifo:tx_engine_fifo_inst\"" { } { { "../neorv32/rtl/core/neorv32_uart.vhd" "tx_engine_fifo_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd" 334 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285053005 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_fifo neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst\|neorv32_fifo:rx_engine_fifo_inst " "Elaborating entity \"neorv32_fifo\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_uart:\\neorv32_uart0_inst_true:neorv32_uart0_inst\|neorv32_fifo:rx_engine_fifo_inst\"" { } { { "../neorv32/rtl/core/neorv32_uart.vhd" "rx_engine_fifo_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_uart.vhd" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285053011 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "neorv32_sysinfo neorv32_top:neorv32_top_inst\|neorv32_sysinfo:neorv32_sysinfo_inst " "Elaborating entity \"neorv32_sysinfo\" for hierarchy \"neorv32_top:neorv32_top_inst\|neorv32_sysinfo:neorv32_sysinfo_inst\"" { } { { "../neorv32/rtl/core/neorv32_top.vhd" "neorv32_sysinfo_inst" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/neorv32/rtl/core/neorv32_top.vhd" 1605 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285053016 ""}
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{ "Info" "IOPT_INFERENCING_SUMMARY" "9 " "Inferred 9 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b0_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b0_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b1_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b1_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b2_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b2_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b3_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|mem_ram_b3_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b0_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b0_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 13 " "Parameter WIDTHAD_A set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 8192 " "Parameter NUMWORDS_A set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 13 " "Parameter WIDTHAD_B set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 8192 " "Parameter NUMWORDS_B set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b1_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b1_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 13 " "Parameter WIDTHAD_A set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 8192 " "Parameter NUMWORDS_A set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 13 " "Parameter WIDTHAD_B set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 8192 " "Parameter NUMWORDS_B set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b2_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b2_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 13 " "Parameter WIDTHAD_A set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 8192 " "Parameter NUMWORDS_A set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 13 " "Parameter WIDTHAD_B set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 8192 " "Parameter NUMWORDS_B set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b3_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|mem_ram_b3_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 13 " "Parameter WIDTHAD_A set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 8192 " "Parameter NUMWORDS_A set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 13 " "Parameter WIDTHAD_B set to 13" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 8192 " "Parameter NUMWORDS_B set to 8192" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RDCONTROL_REG_B CLOCK0 " "Parameter RDCONTROL_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "IINFER_ALTSYNCRAM_ROM_INFERRED" "neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|Mux26_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|Mux26_rtl_0\"" { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Parameter OPERATION_MODE set to ROM" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 10 " "Parameter WIDTHAD_A set to 10" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 1024 " "Parameter NUMWORDS_A set to 1024" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Parameter RAM_BLOCK_TYPE set to AUTO" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE bootloarder_1.neorv32_test_setup_bootloader0.rtl.mif " "Parameter INIT_FILE set to bootloarder_1.neorv32_test_setup_bootloader0.rtl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 276031 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678285057386 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1678285057386 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|altsyncram:mem_ram_b0_rtl_0 " "Elaborated megafunction instantiation \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|altsyncram:mem_ram_b0_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285057408 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|altsyncram:mem_ram_b0_rtl_0 " "Instantiated megafunction \"neorv32_top:neorv32_top_inst\|neorv32_dmem:\\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst\|altsyncram:mem_ram_b0_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_REG_B CLOCK0 " "Parameter \"RDCONTROL_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057408 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678285057408 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_o6q1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_o6q1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_o6q1 " "Found entity 1: altsyncram_o6q1" { } { { "db/altsyncram_o6q1.tdf" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/db/altsyncram_o6q1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285057437 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285057437 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|altsyncram:mem_ram_b0_rtl_0 " "Elaborated megafunction instantiation \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|altsyncram:mem_ram_b0_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285057472 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|altsyncram:mem_ram_b0_rtl_0 " "Instantiated megafunction \"neorv32_top:neorv32_top_inst\|neorv32_imem:\\neorv32_int_imem_inst_true:neorv32_int_imem_inst\|altsyncram:mem_ram_b0_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 13 " "Parameter \"WIDTHAD_A\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 8192 " "Parameter \"NUMWORDS_A\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 13 " "Parameter \"WIDTHAD_B\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 8192 " "Parameter \"NUMWORDS_B\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RDCONTROL_REG_B CLOCK0 " "Parameter \"RDCONTROL_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057472 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678285057472 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s6q1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_s6q1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s6q1 " "Found entity 1: altsyncram_s6q1" { } { { "db/altsyncram_s6q1.tdf" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/db/altsyncram_s6q1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285057505 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285057505 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|altsyncram:Mux26_rtl_0 " "Elaborated megafunction instantiation \"neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|altsyncram:Mux26_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285057527 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|altsyncram:Mux26_rtl_0 " "Instantiated megafunction \"neorv32_top:neorv32_top_inst\|neorv32_boot_rom:\\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst\|altsyncram:Mux26_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE ROM " "Parameter \"OPERATION_MODE\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 10 " "Parameter \"WIDTHAD_A\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 1024 " "Parameter \"NUMWORDS_A\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE bootloarder_1.neorv32_test_setup_bootloader0.rtl.mif " "Parameter \"INIT_FILE\" = \"bootloarder_1.neorv32_test_setup_bootloader0.rtl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678285057527 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678285057527 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_bg91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_bg91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_bg91 " "Found entity 1: altsyncram_bg91" { } { { "db/altsyncram_bg91.tdf" "" { Text "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/db/altsyncram_bg91.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678285057559 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285057559 ""}
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{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1678285057825 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678285060265 ""}
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{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "43 " "43 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1678285063085 ""}
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{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "gfsdg 24 " "Ignored 24 assignments for entity \"gfsdg\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity gfsdg -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285063182 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Analysis & Synthesis" 0 -1 1678285063182 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678285063438 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678285063438 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "2931 " "Implemented 2931 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678285063697 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678285063697 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2759 " "Implemented 2759 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678285063697 ""} { "Info" "ICUT_CUT_TM_RAMS" "160 " "Implemented 160 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1678285063697 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678285063697 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 58 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 58 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "605 " "Peak virtual memory: 605 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285063721 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:17:43 2023 " "Processing ended: Wed Mar 8 15:17:43 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285063721 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285063721 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285063721 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678285063721 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1678285064997 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285064998 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:17:44 2023 " "Processing started: Wed Mar 8 15:17:44 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285064998 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1678285064998 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_fit --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1678285064998 ""}
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{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1678285065031 ""}
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{ "Info" "0" "" "Project = bootloarder_1" { } { } 0 0 "Project = bootloarder_1" 0 0 "Fitter" 0 0 1678285065032 ""}
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{ "Info" "0" "" "Revision = test" { } { } 0 0 "Revision = test" 0 0 "Fitter" 0 0 1678285065032 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678285065194 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678285065194 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "test 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678285065231 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678285065291 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678285065291 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678285065729 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678285065871 ""}
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{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1678285065925 ""}
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{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1678285076572 ""}
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{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_i~inputCLKENA0 1618 global CLKCTRL_G6 " "clk_i~inputCLKENA0 with 1618 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1678285076688 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1678285076688 ""}
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{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285076688 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678285076717 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678285076721 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678285076730 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678285076738 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678285076738 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678285076742 ""}
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|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678285077615 ""}
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|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678285077615 ""}
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|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678285077672 ""}
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|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1678285077673 ""}
|
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678285077674 ""}
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678285077917 ""}
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|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678285077922 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678285077922 ""}
|
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285078049 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678285082598 ""}
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|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1678285083121 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:16 " "Fitter placement preparation operations ending: elapsed time is 00:00:16" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285098798 ""}
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|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678285114675 ""}
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|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678285119606 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:05 " "Fitter placement operations ending: elapsed time is 00:00:05" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285119606 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678285120983 ""}
|
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Router estimated average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" { } { { "loc" "" { Generic "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678285127281 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678285127281 ""}
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|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678285134602 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678285134602 ""}
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|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:10 " "Fitter routing operations ending: elapsed time is 00:00:10" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285134606 ""}
|
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 4.14 " "Total time spent on timing analysis during the Fitter is 4.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678285138117 ""}
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|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678285138205 ""}
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|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678285139335 ""}
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678285139338 ""}
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678285140390 ""}
|
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:06 " "Fitter post-fit operations ending: elapsed time is 00:00:06" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285144843 ""}
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|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678285145194 ""}
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|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2075 " "Peak virtual memory: 2075 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285146646 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:19:06 2023 " "Processing ended: Wed Mar 8 15:19:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285146646 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:22 " "Elapsed time: 00:01:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285146646 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:48 " "Total CPU time (on all processors): 00:02:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285146646 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678285146646 ""}
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1678285148356 ""}
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|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285148356 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:19:08 2023 " "Processing started: Wed Mar 8 15:19:08 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285148356 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678285148356 ""}
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678285148357 ""}
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678285149003 ""}
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|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678285154252 ""}
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|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "542 " "Peak virtual memory: 542 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285154499 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:19:14 2023 " "Processing ended: Wed Mar 8 15:19:14 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285154499 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285154499 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285154499 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678285154499 ""}
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{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1678285155298 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1678285155922 ""}
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285155922 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:19:15 2023 " "Processing started: Wed Mar 8 15:19:15 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285155922 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678285155922 ""}
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|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta bootloarder_1 -c test " "Command: quartus_sta bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678285155922 ""}
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{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678285155959 ""}
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|
{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "gfsdg 24 " "Ignored 24 assignments for entity \"gfsdg\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity gfsdg -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity gfsdg -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity gfsdg -section_id Top was ignored" { } { } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Design Software" 0 -1 1678285156474 ""} } { } 0 20013 "Ignored %2!d! assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Timing Analyzer" 0 -1 1678285156474 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678285156586 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678285156586 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285156647 ""}
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|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285156647 ""}
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|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678285157379 ""}
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|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157380 ""}
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|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_i clk_i " "create_clock -period 1.000 -name clk_i clk_i" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1678285157405 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285157405 ""}
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{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678285157425 ""}
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|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285157426 ""}
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|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678285157427 ""}
|
|
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678285157434 ""}
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|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678285157803 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678285157803 ""}
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|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.905 " "Worst-case setup slack is -6.905" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157804 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157804 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.905 -14064.684 clk_i " " -6.905 -14064.684 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157804 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157804 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.270 " "Worst-case hold slack is 0.270" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.270 0.000 clk_i " " 0.270 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157820 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157820 ""}
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|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.241 " "Worst-case recovery slack is -2.241" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157823 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157823 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.241 -1851.541 clk_i " " -2.241 -1851.541 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157823 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157823 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.111 " "Worst-case removal slack is 1.111" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.111 0.000 clk_i " " 1.111 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157825 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157825 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157828 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -9157.863 clk_i " " -2.636 -9157.863 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285157828 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285157828 ""}
|
|
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1678285157864 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285157864 ""}
|
|
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678285157866 ""}
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678285157908 ""}
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678285159753 ""}
|
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285160003 ""}
|
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678285160061 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678285160061 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.710 " "Worst-case setup slack is -6.710" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160062 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.710 -13691.469 clk_i " " -6.710 -13691.469 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160062 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285160062 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.286 " "Worst-case hold slack is 0.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160081 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160081 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.286 0.000 clk_i " " 0.286 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160081 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285160081 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -2.015 " "Worst-case recovery slack is -2.015" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.015 -1634.552 clk_i " " -2.015 -1634.552 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160085 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285160085 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.994 " "Worst-case removal slack is 0.994" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160087 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160087 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.994 0.000 clk_i " " 0.994 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160087 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285160087 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -9044.132 clk_i " " -2.636 -9044.132 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285160090 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285160090 ""}
|
|
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1678285160113 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285160113 ""}
|
|
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678285160115 ""}
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678285160279 ""}
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678285161979 ""}
|
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285162206 ""}
|
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678285162224 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678285162224 ""}
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.829 " "Worst-case setup slack is -3.829" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.829 -7231.896 clk_i " " -3.829 -7231.896 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162225 ""}
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|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.135 " "Worst-case hold slack is 0.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.135 0.000 clk_i " " 0.135 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162241 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162241 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.673 " "Worst-case recovery slack is -1.673" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.673 -1394.550 clk_i " " -1.673 -1394.550 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162244 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162244 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.247 " "Worst-case removal slack is 1.247" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.247 0.000 clk_i " " 1.247 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162248 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162248 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -8885.840 clk_i " " -2.636 -8885.840 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162252 ""}
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{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1678285162276 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285162276 ""}
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{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678285162278 ""}
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{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285162543 ""}
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{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1678285162561 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1678285162561 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.351 " "Worst-case setup slack is -3.351" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162561 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162561 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.351 -6208.481 clk_i " " -3.351 -6208.481 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162561 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162561 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.124 " "Worst-case hold slack is 0.124" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162590 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162590 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.124 0.000 clk_i " " 0.124 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162590 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162590 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.536 " "Worst-case recovery slack is -1.536" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162593 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162593 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.536 -1307.131 clk_i " " -1.536 -1307.131 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162593 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162593 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.281 " "Worst-case removal slack is 1.281" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162596 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.281 0.000 clk_i " " 1.281 0.000 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162596 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162596 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -9140.645 clk_i " " -2.636 -9140.645 clk_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1678285162599 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678285162599 ""}
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{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1678285162622 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1678285162622 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678285163747 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678285163747 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 31 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "960 " "Peak virtual memory: 960 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285163794 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:19:23 2023 " "Processing ended: Wed Mar 8 15:19:23 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285163794 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285163794 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285163794 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678285163794 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1678285165237 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285165238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:19:25 2023 " "Processing started: Wed Mar 8 15:19:25 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285165238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285165238 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285165238 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678285165954 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "test.vo /home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/ simulation " "Generated file test.vo in folder \"/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678285166553 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "726 " "Peak virtual memory: 726 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285166617 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:19:26 2023 " "Processing ended: Wed Mar 8 15:19:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285166617 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285166617 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285166617 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285166617 ""}
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{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 95 s " "Quartus Prime Full Compilation was successful. 0 errors, 95 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285167324 ""}
|