fix queue
This commit is contained in:
Leopold Clement
parent
d9e82b1bb6
commit
32c4acc38d
11 changed files with 144 additions and 5637 deletions
File diff suppressed because one or more lines are too long
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@ -62,7 +62,7 @@
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/* #define HAL_SD_MODULE_ENABLED */
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/* #define HAL_SD_MODULE_ENABLED */
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/* #define HAL_MMC_MODULE_ENABLED */
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/* #define HAL_MMC_MODULE_ENABLED */
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/* #define HAL_SPDIFRX_MODULE_ENABLED */
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/* #define HAL_SPDIFRX_MODULE_ENABLED */
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#define HAL_SPI_MODULE_ENABLED
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/* #define HAL_SPI_MODULE_ENABLED */
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#define HAL_TIM_MODULE_ENABLED
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#define HAL_TIM_MODULE_ENABLED
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/* #define HAL_UART_MODULE_ENABLED */
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/* #define HAL_UART_MODULE_ENABLED */
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/* #define HAL_USART_MODULE_ENABLED */
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/* #define HAL_USART_MODULE_ENABLED */
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176
Core/Src/main.c
176
Core/Src/main.c
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@ -61,8 +61,6 @@ LTDC_HandleTypeDef hltdc;
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RNG_HandleTypeDef hrng;
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RNG_HandleTypeDef hrng;
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SPI_HandleTypeDef hspi2;
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TIM_HandleTypeDef htim1;
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TIM_HandleTypeDef htim1;
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TIM_HandleTypeDef htim2;
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TIM_HandleTypeDef htim2;
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TIM_HandleTypeDef htim3;
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TIM_HandleTypeDef htim3;
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@ -89,7 +87,6 @@ void SystemClock_Config(void);
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static void MX_GPIO_Init(void);
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static void MX_GPIO_Init(void);
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static void MX_ADC3_Init(void);
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static void MX_ADC3_Init(void);
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static void MX_LTDC_Init(void);
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static void MX_LTDC_Init(void);
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static void MX_SPI2_Init(void);
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static void MX_TIM1_Init(void);
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static void MX_TIM1_Init(void);
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static void MX_TIM2_Init(void);
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static void MX_TIM2_Init(void);
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static void MX_TIM3_Init(void);
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static void MX_TIM3_Init(void);
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@ -145,12 +142,24 @@ struct Monster
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{
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{
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uint32_t x;
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uint32_t x;
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uint32_t y;
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uint32_t y;
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uint8_t health;
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int8_t health;
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// uint8_t pbmp; // TODO c'est quoi ca ?
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// uint8_t pbmp; // TODO c'est quoi ca ?
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// uint8_t type; // TODO d'autre ennemies ?
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// uint8_t type; // TODO d'autre ennemies ?
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struct Missile missile;
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struct Missile missile;
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};
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};
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struct Collision
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{
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uint8_t idx1;
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uint8_t idx2;
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uint8_t damage;
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};
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enum Msg_Queue_F{ // TODO changer le type de la queue F
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MSG_ennemie_mort,
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MSG_joueur_mort
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};
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// Définition des paramètres du joueurs
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// Définition des paramètres du joueurs
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struct Joueur joueur = {10, 10, 1, 1, 3};
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struct Joueur joueur = {10, 10, 1, 1, 3};
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@ -162,7 +171,7 @@ uint32_t LCD_COLOR_BACKGROUND = LCD_COLOR_BLACK;
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// uint8_t waves_left = 10;
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// uint8_t waves_left = 10;
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// Tableau des monstres (8 par ligne, sur 3 ligne)
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// Tableau des monstres (8 par ligne, sur 3 ligne)
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struct Monster *Table_ennemie[8][3];
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struct Monster Table_ennemie[8][3];
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/* USER CODE END 0 */
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/* USER CODE END 0 */
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@ -201,7 +210,6 @@ int main(void)
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MX_GPIO_Init();
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MX_GPIO_Init();
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MX_ADC3_Init();
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MX_ADC3_Init();
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MX_LTDC_Init();
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MX_LTDC_Init();
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MX_SPI2_Init();
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MX_TIM1_Init();
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MX_TIM1_Init();
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MX_TIM2_Init();
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MX_TIM2_Init();
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MX_TIM3_Init();
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MX_TIM3_Init();
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@ -260,7 +268,7 @@ int main(void)
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Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
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Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
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/* definition and creation of Queue_E */
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/* definition and creation of Queue_E */
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osMessageQDef(Queue_E, 8, uint8_t);
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osMessageQDef(Queue_E, 8, struct Collision);
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Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
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Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
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/* USER CODE BEGIN RTOS_QUEUES */
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/* USER CODE BEGIN RTOS_QUEUES */
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@ -269,15 +277,15 @@ int main(void)
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/* Create the thread(s) */
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/* Create the thread(s) */
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/* definition and creation of GameMaster */
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/* definition and creation of GameMaster */
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osThreadDef(GameMaster, f_GameMaster, osPriorityNormal, 0, 128);
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osThreadDef(GameMaster, f_GameMaster, osPriorityHigh, 0, 128);
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GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
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GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
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/* definition and creation of Joueur_1 */
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/* definition and creation of Joueur_1 */
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osThreadDef(Joueur_1, f_Joueur_1, osPriorityNormal, 0, 128);
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osThreadDef(Joueur_1, f_Joueur_1, osPriorityAboveNormal, 0, 128);
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Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
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Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
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/* definition and creation of Block_Enemie */
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/* definition and creation of Block_Enemie */
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osThreadDef(Block_Enemie, f_block_enemie, osPriorityIdle, 0, 128);
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osThreadDef(Block_Enemie, f_block_enemie, osPriorityBelowNormal, 0, 128);
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Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
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Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
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/* definition and creation of Projectile */
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/* definition and creation of Projectile */
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@ -682,45 +690,6 @@ static void MX_RNG_Init(void)
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/* USER CODE END RNG_Init 2 */
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/* USER CODE END RNG_Init 2 */
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}
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}
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/**
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* @brief SPI2 Initialization Function
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* @param None
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* @retval None
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*/
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static void MX_SPI2_Init(void)
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{
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/* USER CODE BEGIN SPI2_Init 0 */
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/* USER CODE END SPI2_Init 0 */
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/* USER CODE BEGIN SPI2_Init 1 */
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/* USER CODE END SPI2_Init 1 */
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/* SPI2 parameter configuration*/
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hspi2.Instance = SPI2;
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hspi2.Init.Mode = SPI_MODE_MASTER;
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hspi2.Init.Direction = SPI_DIRECTION_2LINES;
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hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
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hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
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hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
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hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
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hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
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hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
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hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
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hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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hspi2.Init.CRCPolynomial = 7;
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hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
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hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
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if (HAL_SPI_Init(&hspi2) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN SPI2_Init 2 */
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/* USER CODE END SPI2_Init 2 */
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}
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/**
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/**
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* @brief TIM1 Initialization Function
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* @brief TIM1 Initialization Function
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* @param None
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* @param None
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@ -1186,6 +1155,14 @@ static void MX_GPIO_Init(void)
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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/*Configure GPIO pin : ARDUINO_SCK_D13_Pin */
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GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
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HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
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/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
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/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
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LED2_Pin LED18_Pin */
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LED2_Pin LED18_Pin */
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GPIO_InitStruct.Pin = LED13_Pin | LED17_Pin | LED11_Pin | LED12_Pin | LED2_Pin | LED18_Pin;
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GPIO_InitStruct.Pin = LED13_Pin | LED17_Pin | LED11_Pin | LED12_Pin | LED2_Pin | LED18_Pin;
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@ -1194,6 +1171,14 @@ static void MX_GPIO_Init(void)
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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/*Configure GPIO pin : PI0 */
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GPIO_InitStruct.Pin = GPIO_PIN_0;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
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HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
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/*Configure GPIO pin : VCP_TX_Pin */
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/*Configure GPIO pin : VCP_TX_Pin */
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GPIO_InitStruct.Pin = VCP_TX_Pin;
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GPIO_InitStruct.Pin = VCP_TX_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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@ -1268,13 +1253,26 @@ static void MX_GPIO_Init(void)
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
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GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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/*Configure GPIO pins : PB14 PB15 */
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GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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}
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}
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/* USER CODE BEGIN 4 */
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/* USER CODE BEGIN 4 */
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const uint32_t Couleur_joueur = LCD_COLOR_CYAN;
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const uint32_t Couleur_monstre = LCD_COLOR_CYAN;
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const uint32_t Couleur_missile = LCD_COLOR_WHITE;
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const uint32_t Couleur_vide = LCD_COLOR_BLACK;
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static int envoie_score(int score)
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static int envoie_score(int score)
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{
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{
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socket
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socket socket_udp = udp_new();
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socket_udp = udp_new();
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return 0;
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return 0;
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}
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}
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@ -1321,6 +1319,10 @@ void lcd_plot_rect(uint16_t pos_x, uint16_t pos_y, uint16_t taille_x, uint16_t t
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xSemaphoreGive(MutexLCDHandle);
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xSemaphoreGive(MutexLCDHandle);
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}
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}
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uint8_t colision_missile(uint16_t m_pos_x, uint16_t m_pos_y, uint16_t o_pos_x, uint16_t o_pos_y, uint16_t o_taille_x, uint16_t o_taille_y)
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{
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return ((m_pos_x > o_pos_x) & (m_pos_x < o_pos_x + o_taille_x) & (m_pos_y > o_pos_y) & (m_pos_y < o_pos_y + o_taille_y));
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}
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/* USER CODE END 4 */
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/* USER CODE END 4 */
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/* USER CODE BEGIN Header_f_GameMaster */
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/* USER CODE BEGIN Header_f_GameMaster */
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@ -1336,7 +1338,7 @@ void f_GameMaster(void const *argument)
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MX_LWIP_Init();
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MX_LWIP_Init();
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/* USER CODE BEGIN 5 */
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/* USER CODE BEGIN 5 */
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TickType_t xLastWakeTime;
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TickType_t xLastWakeTime;
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const TickType_t xPeriodeTache = 10;
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const TickType_t xPeriodeTache = 100 / portTICK_PERIOD_MS;
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// Si la variable end est à 1, le jeu s'arrete.
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// Si la variable end est à 1, le jeu s'arrete.
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uint8_t end = 0;
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uint8_t end = 0;
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uint8_t wave = 0;
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uint8_t wave = 0;
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@ -1376,7 +1378,7 @@ void f_Joueur_1(void const *argument)
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{
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{
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/* USER CODE BEGIN f_Joueur_1 */
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/* USER CODE BEGIN f_Joueur_1 */
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TickType_t xLastWakeTime;
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TickType_t xLastWakeTime;
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const TickType_t xPeriodeTache = 10;
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const TickType_t xPeriodeTache = 100 / portTICK_PERIOD_MS;
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uint32_t joystick_h, joystick_v;
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uint32_t joystick_h, joystick_v;
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uint8_t stop = 1;
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uint8_t stop = 1;
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@ -1403,12 +1405,12 @@ void f_Joueur_1(void const *argument)
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uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
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uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
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uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
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uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
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const uint_32 seuil_joystick = 200;
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const uint32_t seuil_joystick = 200;
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const uint_32 centre_joystick = 2048;
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const uint32_t centre_joystick = 2048;
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/* Infinite loop */
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/* Infinite loop */
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for (;;)
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for (;;)
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{
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{
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lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, LCD_COLOR_BACKGROUND);
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lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, Couleur_vide);
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// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
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// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
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HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
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HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
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if ((joueur.x > joueur.dx) && (joystick_v > centre_joystick + seuil_joystick))
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if ((joueur.x > joueur.dx) && (joystick_v > centre_joystick + seuil_joystick))
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joueur.x -= joueur.dx;
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joueur.x -= joueur.dx;
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lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, LCD_COLOR_BLUE);
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lcd_plot_rect(joueur.x, joueur.y, joueur_width, joueur_height, Couleur_joueur);
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if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
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if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
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joueur.health = joueur.health - missile.damage;
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joueur.health = joueur.health - missile.damage;
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@ -1460,16 +1462,45 @@ void f_block_enemie(void const *argument)
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{
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{
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/* USER CODE BEGIN f_block_enemie */
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/* USER CODE BEGIN f_block_enemie */
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TickType_t xLastWakeTime;
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TickType_t xLastWakeTime;
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const TickType_t xPeriodeTache = 10;
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const TickType_t xPeriodeTache = 500 / portTICK_PERIOD_MS; // Toute les demi secondes
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uint8_t number_monsters = 30;
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struct Monster list_monsters[30];
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uint8_t end = 0;
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uint8_t end = 0;
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uint8_t deplacement = 1;
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uint8_t nombre_monstre;
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struct Missile missile;
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struct Collision collision;
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/* Infinite loop */
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/* Infinite loop */
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for (;;)
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for (;;)
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{
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{
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xQueueReceive(Queue_EHandle, &missile, 0);
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while (xQueueReceive(Queue_EHandle, &collision, 0) == pdPASS)
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{
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Table_ennemie[collision.idx1][collision.idx2].health -= collision.damage;
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}
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for (int idx1 = 0; idx1 < 8; idx1++)
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{
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for (int idx2 = 0; idx2 < 3; idx2++)
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{
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||||||
|
lcd_plot_rect(Table_ennemie[idx1][idx2].x, Table_ennemie[idx1][idx2].y, monstre_width, monstre_height, Couleur_vide);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// TODO déplacement des ennemies
|
||||||
|
|
||||||
|
nombre_monstre = 0;
|
||||||
|
for (int idx1 = 0; idx1 < 8, idx1++)
|
||||||
|
{
|
||||||
|
for (int idx2 = 0; idx2 < 3; idx2++)
|
||||||
|
{
|
||||||
|
if (Table_ennemie[idx1][idx2].health > 0)
|
||||||
|
{
|
||||||
|
nombre_monstre++;
|
||||||
|
lcd_plot_rect(Table_ennemie[idx1][idx2].x, Table_ennemie[idx1][idx2].y, monstre_width, monstre_height, Couleur_monstre);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (nombre_monstre)
|
||||||
|
xQueueSend(Queue_FHandle, &end, 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
xQueueReceive(Queue_EHandle, &collision, 0);
|
||||||
if (number_monsters == 0)
|
if (number_monsters == 0)
|
||||||
{
|
{
|
||||||
xQueueSend(Queue_FHandle, &end, 0);
|
xQueueSend(Queue_FHandle, &end, 0);
|
||||||
|
|
@ -1498,7 +1529,7 @@ void f_block_enemie(void const *argument)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
deplacement = -1;
|
deplacement = -1;
|
||||||
|
*/
|
||||||
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
||||||
}
|
}
|
||||||
/* USER CODE END f_block_enemie */
|
/* USER CODE END f_block_enemie */
|
||||||
|
|
@ -1515,7 +1546,7 @@ void f_projectile(void const *argument)
|
||||||
{
|
{
|
||||||
/* USER CODE BEGIN f_projectile */
|
/* USER CODE BEGIN f_projectile */
|
||||||
TickType_t xLastWakeTime;
|
TickType_t xLastWakeTime;
|
||||||
const TickType_t xPeriodeTache = 5000;
|
const TickType_t xPeriodeTache = 200 / portTICK_PERIOD_MS; // Toutes les 200 ms
|
||||||
const int TAILLE_LISTE_MISSILE = 25;
|
const int TAILLE_LISTE_MISSILE = 25;
|
||||||
/* Infinite loop */
|
/* Infinite loop */
|
||||||
struct Missile liste_missile[TAILLE_LISTE_MISSILE];
|
struct Missile liste_missile[TAILLE_LISTE_MISSILE];
|
||||||
|
|
@ -1539,15 +1570,24 @@ void f_projectile(void const *argument)
|
||||||
new_y = liste_missile[idx_missile].y + liste_missile[idx_missile].dy;
|
new_y = liste_missile[idx_missile].y + liste_missile[idx_missile].dy;
|
||||||
if ((new_x < 0) | (new_x > LCD_WIDTH) | (new_y < 0) | (new_y > LCD_HEIGHT))
|
if ((new_x < 0) | (new_x > LCD_WIDTH) | (new_y < 0) | (new_y > LCD_HEIGHT))
|
||||||
liste_missile[idx_missile].valide = 0;
|
liste_missile[idx_missile].valide = 0;
|
||||||
if ((liste_missile[idx_missile].equipe == 0) & (new_x > joueur.x) & (new_x < joueur_width + joueur.x))
|
if ((liste_missile[idx_missile].equipe == 0) & colision_missile(new_x, new_y, joueur.x, joueur.y, joueur_width, joueur_height))
|
||||||
{ //TODO condition de choc avec le joueur
|
{ //TODO condition de choc avec le joueur
|
||||||
xQueueSend(Queue_JHandle, 1, 0);
|
xQueueSend(Queue_JHandle, &liste_missile[idx_missile], 0);
|
||||||
liste_missile[idx_missile].valide = 0;
|
liste_missile[idx_missile].valide = 0;
|
||||||
}
|
}
|
||||||
if (liste_missile[idx_missile].equipe == 1)
|
if (liste_missile[idx_missile].equipe == 1)
|
||||||
{
|
{
|
||||||
for (int idx_mechant = 0, idx_mechant <, idx_mechant++)
|
for (int idx_mechant_1 = 0; idx_mechant_1 < 8; idx_mechant_1++)
|
||||||
{
|
{
|
||||||
|
for (int idx_mechant_2 = 0; idx_mechant_2 < 3; idx_mechant_2++)
|
||||||
|
{
|
||||||
|
if (colision_missile(new_x, new_y, Table_ennemie[idx_mechant_1][idx_mechant_2].x, Table_ennemie[idx_mechant_1][idx_mechant_2].y, monstre_width, monstre_height))
|
||||||
|
{
|
||||||
|
struct Collision collision = {idx_mechant_1, idx_mechant_2, liste_missile[idx_missile].damage};
|
||||||
|
xQueueSend(Queue_EHandle, (void *)&collision, 0);
|
||||||
|
liste_missile[idx_missile].valide = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
//TODO effacage
|
//TODO effacage
|
||||||
|
|
|
||||||
|
|
@ -552,92 +552,6 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng)
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI MSP Initialization
|
|
||||||
* This function configures the hardware resources used in this example
|
|
||||||
* @param hspi: SPI handle pointer
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
||||||
{
|
|
||||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
||||||
if(hspi->Instance==SPI2)
|
|
||||||
{
|
|
||||||
/* USER CODE BEGIN SPI2_MspInit 0 */
|
|
||||||
|
|
||||||
/* USER CODE END SPI2_MspInit 0 */
|
|
||||||
/* Peripheral clock enable */
|
|
||||||
__HAL_RCC_SPI2_CLK_ENABLE();
|
|
||||||
|
|
||||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
||||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
||||||
/**SPI2 GPIO Configuration
|
|
||||||
PI1 ------> SPI2_SCK
|
|
||||||
PI0 ------> SPI2_NSS
|
|
||||||
PB14 ------> SPI2_MISO
|
|
||||||
PB15 ------> SPI2_MOSI
|
|
||||||
*/
|
|
||||||
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
||||||
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
||||||
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
|
|
||||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
||||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
||||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
||||||
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
||||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
||||||
|
|
||||||
/* USER CODE BEGIN SPI2_MspInit 1 */
|
|
||||||
|
|
||||||
/* USER CODE END SPI2_MspInit 1 */
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI MSP De-Initialization
|
|
||||||
* This function freeze the hardware resources used in this example
|
|
||||||
* @param hspi: SPI handle pointer
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
|
||||||
{
|
|
||||||
if(hspi->Instance==SPI2)
|
|
||||||
{
|
|
||||||
/* USER CODE BEGIN SPI2_MspDeInit 0 */
|
|
||||||
|
|
||||||
/* USER CODE END SPI2_MspDeInit 0 */
|
|
||||||
/* Peripheral clock disable */
|
|
||||||
__HAL_RCC_SPI2_CLK_DISABLE();
|
|
||||||
|
|
||||||
/**SPI2 GPIO Configuration
|
|
||||||
PI1 ------> SPI2_SCK
|
|
||||||
PI0 ------> SPI2_NSS
|
|
||||||
PB14 ------> SPI2_MISO
|
|
||||||
PB15 ------> SPI2_MOSI
|
|
||||||
*/
|
|
||||||
HAL_GPIO_DeInit(GPIOI, ARDUINO_SCK_D13_Pin|GPIO_PIN_0);
|
|
||||||
|
|
||||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
|
|
||||||
|
|
||||||
/* USER CODE BEGIN SPI2_MspDeInit 1 */
|
|
||||||
|
|
||||||
/* USER CODE END SPI2_MspDeInit 1 */
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief TIM_Base MSP Initialization
|
* @brief TIM_Base MSP Initialization
|
||||||
* This function configures the hardware resources used in this example
|
* This function configures the hardware resources used in this example
|
||||||
|
|
|
||||||
|
|
@ -1,852 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32f7xx_hal_spi.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SPI HAL module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32F7xx_HAL_SPI_H
|
|
||||||
#define STM32F7xx_HAL_SPI_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32f7xx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32F7xx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Types SPI Exported Types
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI Configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t Mode; /*!< Specifies the SPI operating mode.
|
|
||||||
This parameter can be a value of @ref SPI_Mode */
|
|
||||||
|
|
||||||
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
|
|
||||||
This parameter can be a value of @ref SPI_Direction */
|
|
||||||
|
|
||||||
uint32_t DataSize; /*!< Specifies the SPI data size.
|
|
||||||
This parameter can be a value of @ref SPI_Data_Size */
|
|
||||||
|
|
||||||
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
|
|
||||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
|
||||||
|
|
||||||
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
|
|
||||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
|
||||||
|
|
||||||
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
|
|
||||||
hardware (NSS pin) or by software using the SSI bit.
|
|
||||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
|
||||||
|
|
||||||
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
|
||||||
used to configure the transmit and receive SCK clock.
|
|
||||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
|
||||||
@note The communication clock is derived from the master
|
|
||||||
clock. The slave clock does not need to be set. */
|
|
||||||
|
|
||||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
|
||||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
|
||||||
|
|
||||||
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
|
|
||||||
This parameter can be a value of @ref SPI_TI_mode */
|
|
||||||
|
|
||||||
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
|
|
||||||
This parameter can be a value of @ref SPI_CRC_Calculation */
|
|
||||||
|
|
||||||
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
|
|
||||||
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
|
|
||||||
|
|
||||||
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
|
|
||||||
CRC Length is only used with Data8 and Data16, not other data size
|
|
||||||
This parameter can be a value of @ref SPI_CRC_length */
|
|
||||||
|
|
||||||
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
|
|
||||||
This parameter can be a value of @ref SPI_NSSP_Mode
|
|
||||||
This mode is activated by the NSSP bit in the SPIx_CR2 register and
|
|
||||||
it takes effect only if the SPI interface is configured as Motorola SPI
|
|
||||||
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
|
|
||||||
CPOL setting is ignored).. */
|
|
||||||
} SPI_InitTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI State structure definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
|
|
||||||
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
|
||||||
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
|
|
||||||
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
|
|
||||||
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
|
|
||||||
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
|
|
||||||
} HAL_SPI_StateTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief SPI handle Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct __SPI_HandleTypeDef
|
|
||||||
{
|
|
||||||
SPI_TypeDef *Instance; /*!< SPI registers base address */
|
|
||||||
|
|
||||||
SPI_InitTypeDef Init; /*!< SPI communication parameters */
|
|
||||||
|
|
||||||
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
|
|
||||||
|
|
||||||
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
|
|
||||||
|
|
||||||
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
|
|
||||||
|
|
||||||
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
|
|
||||||
|
|
||||||
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
|
|
||||||
|
|
||||||
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
|
|
||||||
|
|
||||||
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
|
|
||||||
|
|
||||||
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
|
|
||||||
|
|
||||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
|
||||||
|
|
||||||
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
|
|
||||||
|
|
||||||
__IO uint32_t ErrorCode; /*!< SPI Error code */
|
|
||||||
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
|
|
||||||
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
|
|
||||||
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
|
|
||||||
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
|
|
||||||
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
|
|
||||||
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
|
|
||||||
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
|
|
||||||
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
|
|
||||||
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
|
|
||||||
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
} SPI_HandleTypeDef;
|
|
||||||
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI Callback ID enumeration definition
|
|
||||||
*/
|
|
||||||
typedef enum
|
|
||||||
{
|
|
||||||
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
|
|
||||||
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
|
|
||||||
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
|
|
||||||
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
|
|
||||||
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
|
|
||||||
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
|
|
||||||
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
|
|
||||||
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
|
|
||||||
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
|
|
||||||
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
|
|
||||||
|
|
||||||
} HAL_SPI_CallbackIDTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief HAL SPI Callback pointer definition
|
|
||||||
*/
|
|
||||||
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
|
|
||||||
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Constants SPI Exported Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Error_Code SPI Error Code
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
|
|
||||||
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
|
|
||||||
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
|
|
||||||
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
|
|
||||||
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
|
|
||||||
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
|
||||||
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
|
|
||||||
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Mode SPI Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_MODE_SLAVE (0x00000000U)
|
|
||||||
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Direction SPI Direction Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_DIRECTION_2LINES (0x00000000U)
|
|
||||||
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
|
|
||||||
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Data_Size SPI Data Size
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_DATASIZE_4BIT (0x00000300U)
|
|
||||||
#define SPI_DATASIZE_5BIT (0x00000400U)
|
|
||||||
#define SPI_DATASIZE_6BIT (0x00000500U)
|
|
||||||
#define SPI_DATASIZE_7BIT (0x00000600U)
|
|
||||||
#define SPI_DATASIZE_8BIT (0x00000700U)
|
|
||||||
#define SPI_DATASIZE_9BIT (0x00000800U)
|
|
||||||
#define SPI_DATASIZE_10BIT (0x00000900U)
|
|
||||||
#define SPI_DATASIZE_11BIT (0x00000A00U)
|
|
||||||
#define SPI_DATASIZE_12BIT (0x00000B00U)
|
|
||||||
#define SPI_DATASIZE_13BIT (0x00000C00U)
|
|
||||||
#define SPI_DATASIZE_14BIT (0x00000D00U)
|
|
||||||
#define SPI_DATASIZE_15BIT (0x00000E00U)
|
|
||||||
#define SPI_DATASIZE_16BIT (0x00000F00U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_POLARITY_LOW (0x00000000U)
|
|
||||||
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Clock_Phase SPI Clock Phase
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_PHASE_1EDGE (0x00000000U)
|
|
||||||
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_NSS_SOFT SPI_CR1_SSM
|
|
||||||
#define SPI_NSS_HARD_INPUT (0x00000000U)
|
|
||||||
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
|
|
||||||
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
|
|
||||||
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FIRSTBIT_MSB (0x00000000U)
|
|
||||||
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_TI_mode SPI TI Mode
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_TIMODE_DISABLE (0x00000000U)
|
|
||||||
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
|
|
||||||
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_CRC_length SPI CRC Length
|
|
||||||
* @{
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
|
|
||||||
* SPI_CRC_LENGTH_8BIT : CRC 8bit
|
|
||||||
* SPI_CRC_LENGTH_16BIT : CRC 16bit
|
|
||||||
*/
|
|
||||||
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
|
|
||||||
#define SPI_CRC_LENGTH_8BIT (0x00000001U)
|
|
||||||
#define SPI_CRC_LENGTH_16BIT (0x00000002U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
|
|
||||||
* @{
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
|
|
||||||
* RXNE event is generated if the FIFO
|
|
||||||
* level is greater or equal to 1/4(8-bits).
|
|
||||||
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
|
|
||||||
* level is greater or equal to 1/2(16 bits). */
|
|
||||||
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
|
|
||||||
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
|
|
||||||
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_IT_TXE SPI_CR2_TXEIE
|
|
||||||
#define SPI_IT_RXNE SPI_CR2_RXNEIE
|
|
||||||
#define SPI_IT_ERR SPI_CR2_ERRIE
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_Flags_definition SPI Flags Definition
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
|
|
||||||
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
|
|
||||||
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
|
|
||||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
|
|
||||||
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
|
|
||||||
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
|
|
||||||
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
|
|
||||||
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
|
|
||||||
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
|
|
||||||
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
|
|
||||||
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FTLVL_EMPTY (0x00000000U)
|
|
||||||
#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
|
|
||||||
#define SPI_FTLVL_HALF_FULL (0x00001000U)
|
|
||||||
#define SPI_FTLVL_FULL (0x00001800U)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FRLVL_EMPTY (0x00000000U)
|
|
||||||
#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
|
|
||||||
#define SPI_FRLVL_HALF_FULL (0x00000400U)
|
|
||||||
#define SPI_FRLVL_FULL (0x00000600U)
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Exported_Macros SPI Exported Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Reset SPI handle state.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
|
||||||
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
|
|
||||||
(__HANDLE__)->MspInitCallback = NULL; \
|
|
||||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
|
||||||
} while(0)
|
|
||||||
#else
|
|
||||||
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
|
|
||||||
/** @brief Enable the specified SPI interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Disable the specified SPI interrupts.
|
|
||||||
* @param __HANDLE__ specifies the SPI handle.
|
|
||||||
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI interrupt source is enabled or not.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
|
|
||||||
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI flag is set or not.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
|
||||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
|
||||||
* @arg SPI_FLAG_OVR: Overrun flag
|
|
||||||
* @arg SPI_FLAG_BSY: Busy flag
|
|
||||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
|
||||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
|
||||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
|
||||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
|
||||||
|
|
||||||
/** @brief Clear the SPI CRCERR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
|
|
||||||
|
|
||||||
/** @brief Clear the SPI MODF pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_modf = 0x00U; \
|
|
||||||
tmpreg_modf = (__HANDLE__)->Instance->SR; \
|
|
||||||
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
|
|
||||||
UNUSED(tmpreg_modf); \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Clear the SPI OVR pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_ovr = 0x00U; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
|
|
||||||
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
|
|
||||||
UNUSED(tmpreg_ovr); \
|
|
||||||
} while(0U)
|
|
||||||
|
|
||||||
/** @brief Clear the SPI FRE pending flag.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
|
|
||||||
do{ \
|
|
||||||
__IO uint32_t tmpreg_fre = 0x00U; \
|
|
||||||
tmpreg_fre = (__HANDLE__)->Instance->SR; \
|
|
||||||
UNUSED(tmpreg_fre); \
|
|
||||||
}while(0U)
|
|
||||||
|
|
||||||
/** @brief Enable the SPI peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
|
||||||
|
|
||||||
/** @brief Disable the SPI peripheral.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup SPI_Private_Macros SPI Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @brief Set the SPI transmit-only mode.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
|
||||||
|
|
||||||
/** @brief Set the SPI receive-only mode.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
|
|
||||||
|
|
||||||
/** @brief Reset the CRC calculation of the SPI.
|
|
||||||
* @param __HANDLE__ specifies the SPI Handle.
|
|
||||||
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
|
|
||||||
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI flag is set or not.
|
|
||||||
* @param __SR__ copy of SPI SR register.
|
|
||||||
* @param __FLAG__ specifies the flag to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
|
|
||||||
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
|
|
||||||
* @arg SPI_FLAG_CRCERR: CRC error flag
|
|
||||||
* @arg SPI_FLAG_MODF: Mode fault flag
|
|
||||||
* @arg SPI_FLAG_OVR: Overrun flag
|
|
||||||
* @arg SPI_FLAG_BSY: Busy flag
|
|
||||||
* @arg SPI_FLAG_FRE: Frame format error flag
|
|
||||||
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
|
|
||||||
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
|
|
||||||
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Check whether the specified SPI Interrupt is set or not.
|
|
||||||
* @param __CR2__ copy of SPI CR2 register.
|
|
||||||
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
|
|
||||||
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
|
|
||||||
* @arg SPI_IT_ERR: Error interrupt enable
|
|
||||||
* @retval SET or RESET.
|
|
||||||
*/
|
|
||||||
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
|
|
||||||
(__INTERRUPT__)) ? SET : RESET)
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI Mode.
|
|
||||||
* This parameter can be a value of @ref SPI_Mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
|
|
||||||
((__MODE__) == SPI_MODE_MASTER))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* This parameter can be a value of @ref SPI_Direction
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
|
|
||||||
* @param __MODE__ specifies the SPI Direction Mode.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
|
|
||||||
((__MODE__) == SPI_DIRECTION_1LINE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Data Size parameter is in allowed range.
|
|
||||||
* @param __DATASIZE__ specifies the SPI Data Size.
|
|
||||||
* This parameter can be a value of @ref SPI_Data_Size
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
|
|
||||||
((__DATASIZE__) == SPI_DATASIZE_4BIT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
|
|
||||||
* @param __CPOL__ specifies the SPI serial clock steady state.
|
|
||||||
* This parameter can be a value of @ref SPI_Clock_Polarity
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
|
|
||||||
((__CPOL__) == SPI_POLARITY_HIGH))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
|
|
||||||
* @param __CPHA__ specifies the SPI Clock Phase.
|
|
||||||
* This parameter can be a value of @ref SPI_Clock_Phase
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
|
|
||||||
((__CPHA__) == SPI_PHASE_2EDGE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Slave Select parameter is in allowed range.
|
|
||||||
* @param __NSS__ specifies the SPI Slave Select management parameter.
|
|
||||||
* This parameter can be a value of @ref SPI_Slave_Select_management
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
|
|
||||||
((__NSS__) == SPI_NSS_HARD_INPUT) || \
|
|
||||||
((__NSS__) == SPI_NSS_HARD_OUTPUT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
|
|
||||||
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
|
|
||||||
* This parameter can be a value of @ref SPI_NSSP_Mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
|
|
||||||
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
|
|
||||||
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
|
|
||||||
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
|
|
||||||
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
|
|
||||||
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
|
|
||||||
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
|
|
||||||
((__BIT__) == SPI_FIRSTBIT_LSB))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI TI mode parameter is in allowed range.
|
|
||||||
* @param __MODE__ specifies the SPI TI mode.
|
|
||||||
* This parameter can be a value of @ref SPI_TI_mode
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
|
|
||||||
((__MODE__) == SPI_TIMODE_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
|
|
||||||
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
|
|
||||||
* This parameter can be a value of @ref SPI_CRC_Calculation
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
|
|
||||||
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI CRC length is in allowed range.
|
|
||||||
* @param __LENGTH__ specifies the SPI CRC length.
|
|
||||||
* This parameter can be a value of @ref SPI_CRC_length
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
|
|
||||||
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
|
|
||||||
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
|
|
||||||
|
|
||||||
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
|
|
||||||
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
|
|
||||||
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
|
|
||||||
((__POLYNOMIAL__) <= 0xFFFFU) && \
|
|
||||||
(((__POLYNOMIAL__)&0x1U) != 0U))
|
|
||||||
|
|
||||||
/** @brief Checks if DMA handle is valid.
|
|
||||||
* @param __HANDLE__ specifies a DMA Handle.
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Include SPI HAL Extended module */
|
|
||||||
#include "stm32f7xx_hal_spi_ex.h"
|
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SPI_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Initialization/de-initialization functions ********************************/
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
|
|
||||||
|
|
||||||
/* Callbacks Register/UnRegister functions ***********************************/
|
|
||||||
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
|
|
||||||
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
|
|
||||||
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group2
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* I/O operation functions ***************************************************/
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
|
|
||||||
uint32_t Timeout);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
|
|
||||||
uint16_t Size);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
|
|
||||||
/* Transfer Abort functions */
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
|
|
||||||
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
|
|
||||||
|
|
||||||
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPI_Exported_Functions_Group3
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Peripheral State and Error functions ***************************************/
|
|
||||||
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
|
|
||||||
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32F7xx_HAL_SPI_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -1,75 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32f7xx_hal_spi_ex.h
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Header file of SPI HAL Extended module.
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
|
||||||
#ifndef STM32F7xx_HAL_SPI_EX_H
|
|
||||||
#define STM32F7xx_HAL_SPI_EX_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32f7xx_hal_def.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32F7xx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup SPIEx
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
|
||||||
/* Exported macros -----------------------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
/** @addtogroup SPIEx_Exported_Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Initialization and de-initialization functions ****************************/
|
|
||||||
/* IO operation functions *****************************************************/
|
|
||||||
/** @addtogroup SPIEx_Exported_Functions_Group1
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* STM32F7xx_HAL_SPI_EX_H */
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,115 +0,0 @@
|
||||||
/**
|
|
||||||
******************************************************************************
|
|
||||||
* @file stm32f7xx_hal_spi_ex.c
|
|
||||||
* @author MCD Application Team
|
|
||||||
* @brief Extended SPI HAL module driver.
|
|
||||||
* This file provides firmware functions to manage the following
|
|
||||||
* SPI peripheral extended functionalities :
|
|
||||||
* + IO operation functions
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
* @attention
|
|
||||||
*
|
|
||||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
|
||||||
* All rights reserved.</center></h2>
|
|
||||||
*
|
|
||||||
* This software component is licensed by ST under BSD 3-Clause license,
|
|
||||||
* the "License"; You may not use this file except in compliance with the
|
|
||||||
* License. You may obtain a copy of the License at:
|
|
||||||
* opensource.org/licenses/BSD-3-Clause
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
|
||||||
#include "stm32f7xx_hal.h"
|
|
||||||
|
|
||||||
/** @addtogroup STM32F7xx_HAL_Driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPIEx SPIEx
|
|
||||||
* @brief SPI Extended HAL module driver
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#ifdef HAL_SPI_MODULE_ENABLED
|
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
|
||||||
/* Private defines -----------------------------------------------------------*/
|
|
||||||
/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define SPI_FIFO_SIZE 4UL
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private function prototypes -----------------------------------------------*/
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
|
||||||
|
|
||||||
/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
|
|
||||||
* @brief Data transfers functions
|
|
||||||
*
|
|
||||||
@verbatim
|
|
||||||
==============================================================================
|
|
||||||
##### IO operation functions #####
|
|
||||||
===============================================================================
|
|
||||||
[..]
|
|
||||||
This subsection provides a set of extended functions to manage the SPI
|
|
||||||
data transfers.
|
|
||||||
|
|
||||||
(#) Rx data flush function:
|
|
||||||
(++) HAL_SPIEx_FlushRxFifo()
|
|
||||||
|
|
||||||
@endverbatim
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Flush the RX fifo.
|
|
||||||
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
||||||
* the configuration information for the specified SPI module.
|
|
||||||
* @retval HAL status
|
|
||||||
*/
|
|
||||||
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
|
|
||||||
{
|
|
||||||
__IO uint32_t tmpreg;
|
|
||||||
uint8_t count = 0U;
|
|
||||||
while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
|
|
||||||
{
|
|
||||||
count++;
|
|
||||||
tmpreg = hspi->Instance->DR;
|
|
||||||
UNUSED(tmpreg); /* To avoid GCC warning */
|
|
||||||
if (count == SPI_FIFO_SIZE)
|
|
||||||
{
|
|
||||||
return HAL_TIMEOUT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return HAL_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
||||||
|
|
@ -217,7 +217,7 @@ static void low_level_init(struct netif *netif)
|
||||||
MACAddr[1] = 0x80;
|
MACAddr[1] = 0x80;
|
||||||
MACAddr[2] = 0xE1;
|
MACAddr[2] = 0xE1;
|
||||||
MACAddr[3] = 0x00;
|
MACAddr[3] = 0x00;
|
||||||
MACAddr[4] = 0x00;
|
MACAddr[4] = 0xE0;
|
||||||
MACAddr[5] = 0x00;
|
MACAddr[5] = 0x00;
|
||||||
heth.Init.MACAddr = &MACAddr[0];
|
heth.Init.MACAddr = &MACAddr[0];
|
||||||
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||||
|
|
|
||||||
20
README.md
20
README.md
|
|
@ -12,7 +12,27 @@
|
||||||
|
|
||||||
Pour indiquer le joueur, on utilise 1 et pour les méchants on utilise 0.
|
Pour indiquer le joueur, on utilise 1 et pour les méchants on utilise 0.
|
||||||
|
|
||||||
|
## Threads
|
||||||
|
|
||||||
### Game_master
|
### Game_master
|
||||||
|
|
||||||
Si le game master reçoit un message via FHandle, une des deux entités est morte. Si la variable vaut 0, les méchants sont mort. Si elle vaut 1, le joueur est mort.
|
Si le game master reçoit un message via FHandle, une des deux entités est morte. Si la variable vaut 0, les méchants sont mort. Si elle vaut 1, le joueur est mort.
|
||||||
|
|
||||||
|
## Types
|
||||||
|
|
||||||
|
### ```struc Joueur```
|
||||||
|
Classe permetant d'instancier un objet representant le joueur.
|
||||||
|
|
||||||
|
### ```struc Missile```
|
||||||
|
Classe permetant d'instancier des objets representants les missiles.
|
||||||
|
|
||||||
|
### ```struc Monstre```
|
||||||
|
Classe permetant d'instancier des objets représentants les ennemies
|
||||||
|
|
||||||
|
## Queues
|
||||||
|
|
||||||
|
## BlackBoard
|
||||||
|
|
||||||
|
### ```Table_ennemie```
|
||||||
|
Tableau contenant les ennemies
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
#MicroXplorer Configuration settings - do not modify
|
#MicroXplorer Configuration settings - do not modify
|
||||||
VP_TIM5_VS_ClockSourceINT.Mode=Internal
|
VP_TIM5_VS_ClockSourceINT.Mode=Internal
|
||||||
FREERTOS.Queues01=Queue_F,1,uint8_t,0,Dynamic,NULL,NULL;Queue_N,8,struct Missile,0,Dynamic,NULL,NULL;Queue_J,8,uint8_t,0,Dynamic,NULL,NULL;Queue_E,8,uint8_t,0,Dynamic,NULL,NULL
|
FREERTOS.Queues01=Queue_F,1,uint8_t,0,Dynamic,NULL,NULL;Queue_N,8,struct Missile,0,Dynamic,NULL,NULL;Queue_J,8,uint8_t,0,Dynamic,NULL,NULL;Queue_E,8,struct Collision,0,Dynamic,NULL,NULL
|
||||||
PB13.GPIOParameters=GPIO_Label
|
PB13.GPIOParameters=GPIO_Label
|
||||||
SH.FMC_D0_DA0.ConfNb=1
|
SH.FMC_D0_DA0.ConfNb=1
|
||||||
SH.FMC_A8.ConfNb=1
|
SH.FMC_A8.ConfNb=1
|
||||||
|
|
@ -60,7 +60,6 @@ PE9.Signal=FMC_D6_DA6
|
||||||
PG12.GPIOParameters=GPIO_Label
|
PG12.GPIOParameters=GPIO_Label
|
||||||
PI2.Locked=true
|
PI2.Locked=true
|
||||||
SH.FMC_A2.0=FMC_A2,12b-sda1
|
SH.FMC_A2.0=FMC_A2,12b-sda1
|
||||||
PB14.Mode=Full_Duplex_Master
|
|
||||||
PB1.GPIO_Label=ULPI_D2 [USB3320C-EZK_D2]
|
PB1.GPIO_Label=ULPI_D2 [USB3320C-EZK_D2]
|
||||||
PE4.GPIO_Label=LCD_B0 [RK043FN48H-CT672B_B0]
|
PE4.GPIO_Label=LCD_B0 [RK043FN48H-CT672B_B0]
|
||||||
PF10.Locked=true
|
PF10.Locked=true
|
||||||
|
|
@ -77,7 +76,6 @@ Mcu.Package=TFBGA216
|
||||||
PB1.Signal=USB_OTG_HS_ULPI_D2
|
PB1.Signal=USB_OTG_HS_ULPI_D2
|
||||||
PA5.Locked=true
|
PA5.Locked=true
|
||||||
NVIC.TimeBase=TIM6_DAC_IRQn
|
NVIC.TimeBase=TIM6_DAC_IRQn
|
||||||
SPI2.Mode=SPI_MODE_MASTER
|
|
||||||
PJ11.Locked=true
|
PJ11.Locked=true
|
||||||
SH.FMC_SDNCAS.ConfNb=1
|
SH.FMC_SDNCAS.ConfNb=1
|
||||||
SH.FMC_A11.ConfNb=1
|
SH.FMC_A11.ConfNb=1
|
||||||
|
|
@ -150,7 +148,7 @@ Mcu.Pin64=PJ8
|
||||||
Mcu.Pin65=PJ10
|
Mcu.Pin65=PJ10
|
||||||
PJ11.Signal=LTDC_G4
|
PJ11.Signal=LTDC_G4
|
||||||
RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_8
|
RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_8
|
||||||
ETH.IPParameters=MediaInterface
|
ETH.IPParameters=MediaInterface,MACAddr
|
||||||
LTDC.ImageWidth_L0=480
|
LTDC.ImageWidth_L0=480
|
||||||
PD10.Signal=FMC_D15_DA15
|
PD10.Signal=FMC_D15_DA15
|
||||||
PJ6.Mode=RGB888
|
PJ6.Mode=RGB888
|
||||||
|
|
@ -277,7 +275,6 @@ LTDC.BlendingFactor1_L0=LTDC_BLENDING_FACTOR1_PAxCA
|
||||||
ProjectManager.MainLocation=Core/Src
|
ProjectManager.MainLocation=Core/Src
|
||||||
SH.FMC_A6.ConfNb=1
|
SH.FMC_A6.ConfNb=1
|
||||||
PK3.Signal=GPIO_Output
|
PK3.Signal=GPIO_Output
|
||||||
SPI2.VirtualNSS=VM_NSSHARD
|
|
||||||
SH.FMC_A8.0=FMC_A8,12b-sda1
|
SH.FMC_A8.0=FMC_A8,12b-sda1
|
||||||
PC15/OSC32_OUT.GPIO_Label=RCC_OSC32_OUT
|
PC15/OSC32_OUT.GPIO_Label=RCC_OSC32_OUT
|
||||||
Mcu.Pin150=VP_TIM8_VS_ClockSourceINT
|
Mcu.Pin150=VP_TIM8_VS_ClockSourceINT
|
||||||
|
|
@ -353,13 +350,13 @@ Mcu.IP12=RCC
|
||||||
Mcu.IP11=NVIC
|
Mcu.IP11=NVIC
|
||||||
PI14.Mode=RGB888
|
PI14.Mode=RGB888
|
||||||
PC15/OSC32_OUT.GPIOParameters=GPIO_Label
|
PC15/OSC32_OUT.GPIOParameters=GPIO_Label
|
||||||
Mcu.IP18=TIM3
|
Mcu.IP18=TIM5
|
||||||
Mcu.IP17=TIM2
|
Mcu.IP17=TIM3
|
||||||
Mcu.IP19=TIM5
|
Mcu.IP19=TIM8
|
||||||
Mcu.IP14=SPI2
|
Mcu.IP14=SYS
|
||||||
Mcu.IP13=RNG
|
Mcu.IP13=RNG
|
||||||
Mcu.IP16=TIM1
|
Mcu.IP16=TIM2
|
||||||
Mcu.IP15=SYS
|
Mcu.IP15=TIM1
|
||||||
RCC.VCOInputFreq_Value=1000000
|
RCC.VCOInputFreq_Value=1000000
|
||||||
PA14.Mode=Serial_Wire
|
PA14.Mode=Serial_Wire
|
||||||
PH7.GPIO_Label=LCD_SCL [RK043FN48H-CT672B_SCL]
|
PH7.GPIO_Label=LCD_SCL [RK043FN48H-CT672B_SCL]
|
||||||
|
|
@ -371,7 +368,6 @@ PJ12.GPIO_Label=OTG_FS_VBUS
|
||||||
PB7.Signal=USART1_RX
|
PB7.Signal=USART1_RX
|
||||||
PE3.Locked=true
|
PE3.Locked=true
|
||||||
PH6.GPIOParameters=GPIO_Label
|
PH6.GPIOParameters=GPIO_Label
|
||||||
Mcu.IP20=TIM8
|
|
||||||
SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
|
SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
|
||||||
PB0.Locked=true
|
PB0.Locked=true
|
||||||
PA13.GPIOParameters=GPIO_Label
|
PA13.GPIOParameters=GPIO_Label
|
||||||
|
|
@ -383,7 +379,6 @@ SH.FMC_D4_DA4.ConfNb=1
|
||||||
ProjectManager.ToolChainLocation=
|
ProjectManager.ToolChainLocation=
|
||||||
PA15.Signal=GPIO_Input
|
PA15.Signal=GPIO_Input
|
||||||
PF8.Signal=ADC3_IN6
|
PF8.Signal=ADC3_IN6
|
||||||
PI1.Mode=Full_Duplex_Master
|
|
||||||
Mcu.Pin95=PJ4
|
Mcu.Pin95=PJ4
|
||||||
Mcu.Pin96=PG3
|
Mcu.Pin96=PG3
|
||||||
Mcu.Pin93=PG1
|
Mcu.Pin93=PG1
|
||||||
|
|
@ -455,7 +450,6 @@ SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
|
||||||
PH8.Signal=I2C3_SDA
|
PH8.Signal=I2C3_SDA
|
||||||
PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
|
PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
|
||||||
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
|
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
|
||||||
SPI2.IPParameters=VirtualType,Mode,Direction,VirtualNSS,CalculateBaudRate
|
|
||||||
PK0.GPIOParameters=GPIO_Label
|
PK0.GPIOParameters=GPIO_Label
|
||||||
RCC.USBFreq_Value=48000000
|
RCC.USBFreq_Value=48000000
|
||||||
VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
|
VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
|
||||||
|
|
@ -469,7 +463,6 @@ PG12.Mode=RGB888
|
||||||
RCC.VCOOutputFreq_Value=400000000
|
RCC.VCOOutputFreq_Value=400000000
|
||||||
PI9.Signal=LTDC_VSYNC
|
PI9.Signal=LTDC_VSYNC
|
||||||
PH4.GPIO_Label=ULPI_NXT [USB3320C-EZK_NXT]
|
PH4.GPIO_Label=ULPI_NXT [USB3320C-EZK_NXT]
|
||||||
PB15.Mode=Full_Duplex_Master
|
|
||||||
PI9.Locked=true
|
PI9.Locked=true
|
||||||
PI13.GPIO_Label=LCD_INT
|
PI13.GPIO_Label=LCD_INT
|
||||||
RCC.UART4Freq_Value=50000000
|
RCC.UART4Freq_Value=50000000
|
||||||
|
|
@ -529,7 +522,6 @@ SH.FMC_A4.ConfNb=1
|
||||||
PJ9.Mode=RGB888
|
PJ9.Mode=RGB888
|
||||||
PH12.Signal=GPIO_Output
|
PH12.Signal=GPIO_Output
|
||||||
PH12.Locked=true
|
PH12.Locked=true
|
||||||
SPI2.VirtualType=VM_MASTER
|
|
||||||
VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT
|
VP_TIM5_VS_ClockSourceINT.Signal=TIM5_VS_ClockSourceINT
|
||||||
PK0.Mode=RGB888
|
PK0.Mode=RGB888
|
||||||
PG4.Signal=FMC_A14_BA0
|
PG4.Signal=FMC_A14_BA0
|
||||||
|
|
@ -576,7 +568,6 @@ PJ1.GPIOParameters=GPIO_Label
|
||||||
PI3.Signal=GPIO_Output
|
PI3.Signal=GPIO_Output
|
||||||
PH1/OSC_OUT.Locked=true
|
PH1/OSC_OUT.Locked=true
|
||||||
SH.FMC_D15_DA15.ConfNb=1
|
SH.FMC_D15_DA15.ConfNb=1
|
||||||
SPI2.CalculateBaudRate=25.0 MBits/s
|
|
||||||
ADC3.IPParameters=Channel-0\#ChannelRegularConversion
|
ADC3.IPParameters=Channel-0\#ChannelRegularConversion
|
||||||
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
|
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
|
||||||
PF3.Signal=FMC_A3
|
PF3.Signal=FMC_A3
|
||||||
|
|
@ -621,6 +612,7 @@ PA9.GPIO_Label=VCP_TX [STM32F103CBT6_PA3]
|
||||||
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
|
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
|
||||||
PB8.GPIO_PuPd=GPIO_NOPULL
|
PB8.GPIO_PuPd=GPIO_NOPULL
|
||||||
PC6.Signal=USART6_TX
|
PC6.Signal=USART6_TX
|
||||||
|
ETH.MACAddr=00\:80\:E1\:00\:E0\:00
|
||||||
PB11.GPIO_Label=ULPI_D4 [USB3320C-EZK_D4]
|
PB11.GPIO_Label=ULPI_D4 [USB3320C-EZK_D4]
|
||||||
PD1.Signal=FMC_D3_DA3
|
PD1.Signal=FMC_D3_DA3
|
||||||
RCC.UART8Freq_Value=50000000
|
RCC.UART8Freq_Value=50000000
|
||||||
|
|
@ -736,7 +728,7 @@ PJ9.GPIOParameters=GPIO_Label
|
||||||
LTDC.HBP=13
|
LTDC.HBP=13
|
||||||
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
|
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
|
||||||
PI13.Locked=true
|
PI13.Locked=true
|
||||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_TIM1_Init-TIM1-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true,9-MX_TIM5_Init-TIM5-false-HAL-true,10-MX_TIM8_Init-TIM8-false-HAL-true,11-MX_DAC_Init-DAC-false-HAL-true,12-MX_FMC_Init-FMC-false-HAL-true,13-MX_DMA2D_Init-DMA2D-false-HAL-true,14-MX_CRC_Init-CRC-false-HAL-true,15-MX_RNG_Init-RNG-false-HAL-true,16-MX_LWIP_Init-LWIP-false-HAL-false,17-MX_ADC1_Init-ADC1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_LTDC_Init-LTDC-false-HAL-true,5-MX_TIM1_Init-TIM1-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_TIM3_Init-TIM3-false-HAL-true,8-MX_TIM5_Init-TIM5-false-HAL-true,9-MX_TIM8_Init-TIM8-false-HAL-true,10-MX_DAC_Init-DAC-false-HAL-true,11-MX_FMC_Init-FMC-false-HAL-true,12-MX_DMA2D_Init-DMA2D-false-HAL-true,13-MX_CRC_Init-CRC-false-HAL-true,14-MX_RNG_Init-RNG-false-HAL-true,15-MX_LWIP_Init-LWIP-false-HAL-false,16-MX_ADC1_Init-ADC1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||||
PC0.GPIOParameters=GPIO_Label
|
PC0.GPIOParameters=GPIO_Label
|
||||||
PC0.GPIO_Label=ULPI_STP [USB3320C-EZK_STP]
|
PC0.GPIO_Label=ULPI_STP [USB3320C-EZK_STP]
|
||||||
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
|
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
|
||||||
|
|
@ -764,7 +756,7 @@ SH.GPXTI13.ConfNb=1
|
||||||
Mcu.ThirdPartyNb=0
|
Mcu.ThirdPartyNb=0
|
||||||
PH0/OSC_IN.Mode=HSE-External-Oscillator
|
PH0/OSC_IN.Mode=HSE-External-Oscillator
|
||||||
RCC.HCLKFreq_Value=200000000
|
RCC.HCLKFreq_Value=200000000
|
||||||
Mcu.IPNb=21
|
Mcu.IPNb=20
|
||||||
RCC.PLLI2SRoutputFreq_Value=50000000
|
RCC.PLLI2SRoutputFreq_Value=50000000
|
||||||
RCC.SPDIFRXFreq_Value=50000000
|
RCC.SPDIFRXFreq_Value=50000000
|
||||||
PA0/WKUP.Locked=true
|
PA0/WKUP.Locked=true
|
||||||
|
|
@ -836,7 +828,6 @@ PB9.GPIO_Speed=GPIO_SPEED_FREQ_LOW
|
||||||
PJ3.GPIO_Label=LCD_R4 [RK043FN48H-CT672B_R4]
|
PJ3.GPIO_Label=LCD_R4 [RK043FN48H-CT672B_R4]
|
||||||
PK2.GPIO_Label=LCD_G7 [RK043FN48H-CT672B_G7]
|
PK2.GPIO_Label=LCD_G7 [RK043FN48H-CT672B_G7]
|
||||||
PJ7.Mode=RGB888
|
PJ7.Mode=RGB888
|
||||||
SPI2.Direction=SPI_DIRECTION_2LINES
|
|
||||||
PF0.Signal=FMC_A0
|
PF0.Signal=FMC_A0
|
||||||
SH.FMC_NBL0.ConfNb=1
|
SH.FMC_NBL0.ConfNb=1
|
||||||
PC2.GPIO_Label=ULPI_DIR [USB3320C-EZK_DIR]
|
PC2.GPIO_Label=ULPI_DIR [USB3320C-EZK_DIR]
|
||||||
|
|
@ -873,7 +864,6 @@ PK7.GPIOParameters=GPIO_Label
|
||||||
ProjectManager.TargetToolchain=STM32CubeIDE
|
ProjectManager.TargetToolchain=STM32CubeIDE
|
||||||
LTDC.ActiveH=272
|
LTDC.ActiveH=272
|
||||||
SH.FMC_D1_DA1.ConfNb=1
|
SH.FMC_D1_DA1.ConfNb=1
|
||||||
PI0.Mode=NSS_Signal_Hard_Output
|
|
||||||
ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_0
|
ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_0
|
||||||
PJ9.GPIO_Label=LCD_G2 [RK043FN48H-CT672B_G2]
|
PJ9.GPIO_Label=LCD_G2 [RK043FN48H-CT672B_G2]
|
||||||
PE4.Locked=true
|
PE4.Locked=true
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue