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Projet_SETI_RISC-V/proj_quartus/output_files/test.flow.rpt

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projet base
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Flow report for test
memory
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Thu Mar 9 12:26:39 2023
riscv O3
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Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
projet base
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---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
riscv O3
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+--------------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+----------------------------------------------------+
memory
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; Flow Status ; Successful - Thu Mar 9 12:26:39 2023 ;
riscv O3
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; Quartus Prime Version ; 22.1std.0 Build 915 10/25/2022 SC Standard Edition ;
; Revision Name ; test ;
; Top-level Entity Name ; neorv32_test_setup_bootloader ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Final ;
memory
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; Logic utilization (in ALMs) ; 1,462 / 32,070 ( 5 % ) ;
; Total registers ; 1722 ;
riscv O3
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; Total pins ; 12 / 457 ( 3 % ) ;
; Total virtual pins ; 0 ;
memory
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; Total block memory bits ; 1,214,464 / 4,065,280 ( 30 % ) ;
riscv O3
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; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+----------------------------------------------------+
projet base
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+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
memory
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; Start date & time ; 03/09/2023 12:24:30 ;
projet base
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; Main task ; Compilation ;
; Revision Name ; test ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------------------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------------------------+-----------------------------------+
memory
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; COMPILER_SIGNATURE_ID ; 92407695964.167836107020324 ; -- ; -- ; -- ;
projet base
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; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; gfsdg ; Top ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; neorv32_test_setup_bootloader ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; gfsdg ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; neorv32_test_setup_bootloader ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; gfsdg ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; neorv32_test_setup_bootloader ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; neorv32_test_setup_bootloader ; test ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------------------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
memory
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; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 598 MB ; 00:00:24 ;
; Fitter ; 00:01:28 ; 1.2 ; 2087 MB ; 00:03:00 ;
; Assembler ; 00:00:06 ; 1.0 ; 567 MB ; 00:00:06 ;
; Timing Analyzer ; 00:00:09 ; 2.6 ; 979 MB ; 00:00:19 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 733 MB ; 00:00:01 ;
; Total ; 00:02:02 ; -- ; -- ; 00:03:50 ;
projet base
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
riscv O3
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+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+----------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; seti-VirtualBox ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; Fitter ; seti-VirtualBox ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; Assembler ; seti-VirtualBox ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; Timing Analyzer ; seti-VirtualBox ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
; EDA Netlist Writer ; seti-VirtualBox ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
+----------------------+------------------+----------------+------------+----------------+
projet base
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------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off bootloarder_1 -c test
quartus_fit --read_settings_files=off --write_settings_files=off bootloarder_1 -c test
quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test
quartus_sta bootloarder_1 -c test
quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test
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