106 lines
6.2 KiB
Text
106 lines
6.2 KiB
Text
<<<
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:sectnums:
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== Application-Specific Processor Configuration
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Due to the processor's configuration options, which are mainly defined via the top entity VHDL generics, the SoC
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can be tailored to the application-specific requirements. Note that this chapter does not focus on optional
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_SoC features_ like IO/peripheral modules. It rather gives ideas on how to optimize for _overall goals_
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like performance and area.
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[NOTE]
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Please keep in mind that optimizing the design in one direction (like performance) will also effect other potential
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optimization goals (like area and energy).
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=== Optimize for Performance
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The following points show some concepts to optimize the processor for performance regardless of the costs
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(i.e. increasing area and energy requirements):
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* Enable all performance-related RISC-V CPU extensions that implement dedicated hardware accelerators instead
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of emulating operations entirely in software: `M`, `C`, `Zfinx`
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* Enable mapping of compleX CPU operations to dedicated hardware: `FAST_MUL_EN => true` to use DSP slices for
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multiplications, `FAST_SHIFT_EN => true` use a fast barrel shifter for shift operations.
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* Implement the instruction cache: `ICACHE_EN => true`
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* Use as many _internal_ memory as possible to reduce memory access latency: `MEM_INT_IMEM_EN => true` and
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`MEM_INT_DMEM_EN => true`, maximize `MEM_INT_IMEM_SIZE` and `MEM_INT_DMEM_SIZE`
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* Increase the CPU's instruction prefetch buffer size: if **no** instruction cache is implemented `CPU_IPB_ENTRIES` should be
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quite large
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* _To be continued..._
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=== Optimize for Size
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The NEORV32 is a size-optimized processor system that is intended to fit into tiny niches within large SoC
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designs or to be used a customized microcontroller in really tiny / low-power FPGAs (like Lattice iCE40).
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Here are some ideas how to make the processor even smaller while maintaining it's _general purpose system_
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concept and maximum RISC-V compatibility.
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**SoC**
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* This is obvious, but exclude all unused optional IO/peripheral modules from synthesis via the processor
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configuration generics.
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* If an IO module provides an option to configure the number of "channels", constrain this number to the
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actually required value (e.g. the PWM module `IO_PWM_NUM_CH` or the external interrupt controller `XIRQ_NUM_CH`).
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* Reduce the FIFO sizes of implemented modules (e.g. `SLINK_TX_FIFO`).
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* Disable the instruction cache (`ICACHE_EN => false`) if the design only uses processor-internal IMEM
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and DMEM memories.
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* _To be continued..._
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**CPU**
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* Use the _embedded_ RISC-V CPU architecture extension (`CPU_EXTENSION_RISCV_E`) to reduce block RAM utilization.
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* The compressed instructions extension (`CPU_EXTENSION_RISCV_C`) requires additional logic for the decoder but
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also reduces program code size by approximately 30%.
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* If not explicitly used/required, exclude the CPU standard counters `[m]instret[h]`
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(number of instruction) and `[m]cycle[h]` (number of cycles) from synthesis by disabling the `Zicntr` ISA extension
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(note, this is not RISC-V compliant).
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* Reduce the CPU's prefetch buffer size (`CPU_IPB_ENTRIES`) to its minimum (=1).
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* Map CPU shift operations to a small and iterative shifter unit (`FAST_SHIFT_EN => false`).
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* If you have unused DSP block available, you can map multiplication operations to those slices instead of
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using LUTs to implement the multiplier (`FAST_MUL_EN => true`).
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* If there is no need to execute division in hardware, use the `Zmmul` extension instead of the full-scale
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`M` extension.
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* Disable CPU extension that are not explicitly used.
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* _To be continued..._
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=== Optimize for Clock Speed
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The NEORV32 Processor and CPU are designed to provide minimal logic between register stages to keep the
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critical path as short as possible. When enabling additional extension or modules the impact on the existing
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logic is also kept at a minimum to prevent timing degrading. If there is a major impact on existing
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logic (example: many physical memory protection address configuration registers) the VHDL code automatically
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adds additional register stages to maintain critical path length. Obviously, this increases operation latency.
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In order to optimize for a minimal critical path (= maximum clock speed) the following points should be considered:
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* Complex CPU extensions (in terms of hardware requirements) should be avoided (examples: floating-point unit, physical memory protection).
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* Large carry chains (>32-bit) should be avoided (i.e. constrain the HPM counter sizes via `HPM_CNT_WIDTH`).
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* If the target FPGA provides sufficient DSP resources, CPU multiplication operations can be mapped to DSP slices (`FAST_MUL_EN => true`)
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reducing LUT usage and critical path impact while also increasing overall performance.
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* Use the synchronous (registered) RX path configuration of the external memory interface (`MEM_EXT_ASYNC_RX => false`).
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* _To be continued..._
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[NOTE]
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The short and fixed-length critical path allows to integrate the core into existing clock domains.
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So no clock domain-crossing and no sub-clock generation is required. However, for very high clock
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frequencies (this is technology / platform dependent) clock domain crossing becomes crucial for chip-internal
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connections.
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=== Optimize for Energy
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There are no _dedicated_ configuration options to optimize the processor for energy (minimal consumption;
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energy/instruction ratio) yet. However, a reduced processor area (<<_optimize_for_size>>) will also reduce
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static energy consumption.
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To optimize your setup for low-power applications, you can make use of the CPU sleep mode (`wfi` instruction).
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Put the CPU to sleep mode whenever possible. Disable all processor modules that are not actually used (exclude them
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from synthesis if the will be _never_ used; disable the module via it's control register if the module is not
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_currently_ used). When is sleep mode, you can keep a timer module running (MTIME or the watch dog) to wake up
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the CPU again. Since the wake up is triggered by _any_ interrupt, the external interrupt controller can also
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be used to wake up the CPU again. By this, all timers (and all other modules) can be deactivated as well.
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.Processor-internal clock generator shutdown
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[TIP]
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If _no_ IO/peripheral module is currently enabled, the processor's internal clock generator circuit will be
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shut down reducing switching activity and thus, dynamic energy consumption.
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