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207 lines
14 KiB
VHDL
207 lines
14 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> #
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-- # ********************************************************************************************* #
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-- # This unit provides information regarding the NEORV32 processor system configuration - #
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-- # mostly derived from the top's configuration generics. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_sysinfo is
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generic (
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-- General --
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CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
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CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID
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INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS : natural; -- number of regions (0..64)
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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-- Internal Data memory --
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
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-- Internal Cache memory --
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ICACHE_EN : boolean; -- implement instruction cache
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ICACHE_NUM_BLOCKS : natural; -- i-cache: number of blocks (min 2), has to be a power of 2
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ICACHE_BLOCK_SIZE : natural; -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY : natural; -- i-cache: associativity (min 1), has to be a power 2
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-- External memory interface --
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MEM_EXT_EN : boolean; -- implement external memory bus interface?
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MEM_EXT_BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
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-- On-Chip Debugger --
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ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD?
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-- Processor peripherals --
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IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_SPI_EN : boolean; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
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IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
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IO_SLINK_EN : boolean; -- implement stream link interface?
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IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
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IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean; -- implement execute in place module (XIP)?
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IO_ONEWIRE_EN : boolean -- implement 1-wire interface (ONEWIRE)?
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);
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic -- transfer error
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);
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end neorv32_sysinfo;
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architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal rden : std_ulogic;
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signal wren : std_ulogic;
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signal addr : std_ulogic_vector(2 downto 0);
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-- system information ROM --
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type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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signal sysinfo_mem : info_mem_t;
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begin
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
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rden <= acc_en and rden_i; -- read access
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wren <= acc_en and wren_i; -- write access
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addr <= addr_i(index_size_f(sysinfo_size_c)-1 downto 2);
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-- Construct Info ROM ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- SYSINFO(0): Processor (primary) clock frequency --
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sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
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-- SYSINFO(1): Custom user-defined ID --
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sysinfo_mem(1) <= CUSTOM_ID;
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-- SYSINFO(2): Implemented processor devices/features --
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-- Memory --
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sysinfo_mem(2)(00) <= bool_to_ulogic_f(INT_BOOTLOADER_EN); -- processor-internal bootloader implemented?
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sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_EN); -- external memory bus interface implemented?
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sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_EN) and bool_to_ulogic_f(boolean(MEM_INT_IMEM_SIZE > 0)); -- processor-internal instruction memory implemented?
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sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_DMEM_EN) and bool_to_ulogic_f(boolean(MEM_INT_DMEM_SIZE > 0)); -- processor-internal data memory implemented?
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sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_EXT_BIG_ENDIAN); -- is external memory bus interface using BIG-endian byte-order?
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sysinfo_mem(2)(05) <= bool_to_ulogic_f(ICACHE_EN); -- processor-internal instruction cache implemented?
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--
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sysinfo_mem(2)(12 downto 06) <= (others => '0'); -- reserved
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-- Misc --
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sysinfo_mem(2)(13) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
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sysinfo_mem(2)(14) <= bool_to_ulogic_f(ON_CHIP_DEBUGGER_EN); -- on-chip debugger implemented?
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--
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sysinfo_mem(2)(15) <= '0'; -- reserved
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-- IO --
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sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented?
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sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented?
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sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented?
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sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented?
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sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented?
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sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented?
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sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented?
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sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented?
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sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented?
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sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented?
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sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
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sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented?
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sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented?
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sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented?
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sysinfo_mem(2)(30) <= bool_to_ulogic_f(IO_XIP_EN); -- execute in place module (XIP) implemented?
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sysinfo_mem(2)(31) <= bool_to_ulogic_f(IO_ONEWIRE_EN); -- 1-wire interface (ONEWIRE) implemented?
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-- SYSINFO(3): Cache configuration --
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sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
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sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
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sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
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sysinfo_mem(3)(15 downto 12) <= "0001" when (ICACHE_ASSOCIATIVITY > 1) and (ICACHE_EN = true) else (others => '0'); -- i-cache: replacement strategy (LRU only (yet))
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--
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sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved - d-cache: log2(block_size)
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sysinfo_mem(3)(23 downto 20) <= (others => '0'); -- reserved - d-cache: log2(num_blocks)
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sysinfo_mem(3)(27 downto 24) <= (others => '0'); -- reserved - d-cache: log2(associativity)
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sysinfo_mem(3)(31 downto 28) <= (others => '0'); -- reserved - d-cache: replacement strategy
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-- SYSINFO(4): Base address of instruction memory space --
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sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file
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-- SYSINFO(5): Base address of data memory space --
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sysinfo_mem(5) <= dspace_base_c; -- defined in neorv32_package.vhd file
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-- SYSINFO(6): Size of IMEM in bytes --
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sysinfo_mem(6) <= std_ulogic_vector(to_unsigned(MEM_INT_IMEM_SIZE, 32)) when (MEM_INT_IMEM_EN = true) else (others => '0');
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-- SYSINFO(7): Size of DMEM in bytes --
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sysinfo_mem(7) <= std_ulogic_vector(to_unsigned(MEM_INT_DMEM_SIZE, 32)) when (MEM_INT_DMEM_EN = true) else (others => '0');
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-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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read_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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ack_o <= rden;
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err_o <= wren; -- read-only!
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if (rden = '1') then
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data_o <= sysinfo_mem(to_integer(unsigned(addr)));
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else
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data_o <= (others => '0');
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end if;
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end if;
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end process read_access;
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end neorv32_sysinfo_rtl;
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