Projet_SETI_RISC-V/neorv32/rtl

Hardware RTL Sources

core

This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor. When creating a new synthesis/simulation project make sure that all *.vhd files from this folder are added to a new design library called neorv32.

⚠️ The sub-folder core/mem contains the platform-agnostic VHDL architectures of the processor-internal memories. You can replace inclusion of these files by platform-optimized memory architectures.

processor_templates

Contains pre-configured "SoC" templates that instantiate the processor's top entity from core. These templates can be instantiated directly within a FPGA-specific board wrapper.

system_integration

Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default processor top entity from core, but feature a different interface type. For example: an AXI4-Lite-compatible bus interface instead of the default Wishbone bus interface or a top entity with resolved port signal types.

test_setups

Minimal test setups (FPGA- and board-independent) for the processor. See the README in that folder for more information. Note that these test setups are used in the NEORV32 USer Guide.