334 lines
25 KiB
Markdown
334 lines
25 KiB
Markdown
[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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[](https://gitter.im/neorv32/community)
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1. [Overview](#1-Overview)
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* [Key Features](#Key-Features)
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* [Project Status](#Project-Status)
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2. [Features](#2-Features)
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3. [FPGA Implementation Results](#3-FPGA-Implementation-Results)
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4. [Performance](#4-Performance)
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5. [Software Framework & Tooling](#5-Software-Framework-and-Tooling)
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6. [**Getting Started**](#6-Getting-Started) :rocket:
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## 1. Overview
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** built around the NEORV32
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[RISC-V](https://riscv.org/) CPU and written in **platform-independent VHDL**. The processor is intended as auxiliary
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controller in larger SoC designs or as *ready-to-go* stand-alone custom microcontroller that even fits into a
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Lattice iCE40 UltraPlus low-power & low-density FPGA. The project is intended to work _out of the box_ and targets
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FPGA / RISC-V beginners as well as advanced users.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that _all_ memory accesses are properly acknowledged and that _all_ invalid/malformed
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instructions are always detected as such. Whenever an unexpected situation occurs the application software is
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informed via _precise and resumable_ hardware exceptions.
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* :interrobang: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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* :books: For detailed information see the [NEORV32 online documentation](https://stnolting.github.io/neorv32/).
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* :recycle: Looking for an **all-Verilog** version? Have a look at [neorv32-verilog](https://github.com/stnolting/neorv32-verilog).
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* :heavy_check_mark: [Continuous integration](#Project-Status) to check for regressions (including RISC-V ISA compatibility test using **RISCOF**).
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* :package: [Exemplary setups](https://github.com/stnolting/neorv32-setups) and
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[community projects](https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects)
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targeting various FPGA boards and toolchains to get started.
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* :kite: Support for [Zephyr](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) &
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[FreeRTOS](https://github.com/stnolting/neorv32/tree/main/sw/example/demo_freeRTOS) operating systems and
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[LiteX](https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32) SoC Builder Framework.
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* :label: The project's change log is available in [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md).
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* :rocket: Check out the [quick links below](#6-Getting-Started) and the
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started setting up _your_ NEORV32 processor!
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:bulb: Feel free to open a new [issue](https://github.com/stnolting/neorv32/issues) or start a new
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[discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas or if something is
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not working as expected. Or have a chat on our [gitter channel](https://gitter.im/neorv32/community).
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See how to [contribute](https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md).
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### Key Features
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- [x] all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
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- [x] completely described in behavioral, platform-independent VHDL - **no** platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also [available](https://github.com/stnolting/neorv32-verilog)
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- [x] extensive configuration options for adapting the processor to the requirements of the application
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- [x] highly [extensible hardware](https://stnolting.github.io/neorv32/ug/#_comparative_summary) - on CPU, processor and system level
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- [x] aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
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- [x] FPGA friendly (e.g. _all_ internal memories can be mapped to block RAM - including the CPU's register file)
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- [x] optimized for high clock frequencies to ease integration / timing closure
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- [x] from zero to _"hello world!"_ - completely open source and documented
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- [x] easy to use even for FPGA / RISC-V starters – intended to _work out of the box_
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### Project Status
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/releases)
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| | Repository | CI Status |
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|:--------|:-----------|:----------|
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| GitHub Pages (docs) | [neorv32](https://github.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32) |
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| Build documentation | [neorv32](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) |
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| Processor (SoC) verification | [neorv32](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) |
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| RISCOF core verification | [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) | [](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml) |
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| FPGA implementations | [neorv32-setups](https://github.com/stnolting/neorv32-setups) | [](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation) |
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| All-Verilog "version" | [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) | [](https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml) |
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| Prebuilt GCC toolchains | [riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions/workflows/main.yml) |
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The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the
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[neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program
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(for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
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and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)
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on Intel, Xilinx and Lattice FPGAs. The conversion into a plain-Verilog netlist module is automatically checked by the
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[neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository.
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 2. Features
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The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU.
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By using generics the design is highly configurable and allows a flexible customization to tailor the
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setup according to your needs. Note that all of the following SoC modules are entirely _optional_.
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**CPU Core**
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* [](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) -
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see the [_open-source architecture ID list_](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) in the official RISC-V ISA manual repository
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* 32-bit little-endian RISC-V single-core, pipelined/multi-cycle modified Harvard architecture
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* configurable ISA extensions:
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\
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`RV32`
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[[`I`](https://stnolting.github.io/neorv32/#_i_base_integer_isa)/
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[`E`](https://stnolting.github.io/neorv32/#_e_embedded_cpu)]
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[[`B`](https://stnolting.github.io/neorv32/#_b_bit_manipulation_operations)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_compressed_instructions)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_integer_multiplication_and_division)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_less_privileged_user_mode)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_neorv32_specific_custom_extensions)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_control_and_status_register_access_privileged_architecture)]
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[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_cpu_base_counters)]
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[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_hardware_performance_monitors)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_instruction_stream_synchronization)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_single_precision_floating_point_operations)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_integer_multiplication)]
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[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_custom_instructions_extension_cfu)]
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[[`PMP`](https://stnolting.github.io/neorv32/#_pmp_physical_memory_protection)]
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[[`Sdext`](https://stnolting.github.io/neorv32/#_sdext_external_debug_support)]
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[[`Sdtrig`](https://stnolting.github.io/neorv32/#_sdtrig_trigger_module)]
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* compatible to subsets of the RISC-V
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*Unprivileged ISA Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf))
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and *Privileged Architecture Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf)).
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* `machine` and `user` privilege modes
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* implements **all** standard RISC-V exceptions and interrupts (including MTI, MEI & MSI)
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* 16 fast interrupt request channels as NEORV32-specific extension
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* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as `Zxcfu` ISA extension)
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for _custom RISC-V instructions_ (R3-type, R4-type and R5-type);
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* _intrinsic_ libraries for the `Zxcfu` and `Zfinx` ISA extensions
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**Memories**
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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* pre-installed bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface;
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allows booting application code via UART or from external SPI flash
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**Timers and Counters**
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* 64-bit machine system timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
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* 32-bit general purpose timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
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* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
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**Input / Output**
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* standard serial interfaces
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([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
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[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
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[TWI/I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi)),
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[ONEWIRE/1-Wire](https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire))
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* general purpose IOs ([GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio)) and
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[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
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* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly control NeoPixel(TM) LEDs
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**SoC Connectivity**
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* 32-bit external bus interface - Wishbone b4 compatible
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([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite));
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[wrappers](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration) for AXI4-Lite and Avalon-MM host interfaces
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* 32-bit stream link interface with up to 8 independent RX and TX channels
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink)) - AXI4-Stream compatible
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* external interrupts controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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**Advanced**
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* **true** random number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) based
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on the [neoTRNG](https://github.com/stnolting/neoTRNG)
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* execute-in-place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to execute code directly from SPI flash
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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for custom tightly-coupled co-processors, accelerators or interfaces
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**Debugging**
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via standard JTAG interface
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* compliant to the "Minimal RISC-V Debug Specification Version 1.0"
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* compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 3. FPGA Implementation Results
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Implementation results for **exemplary CPU configurations** generated for an Intel Cyclone IV `EP4CE22F17C6` FPGA
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using Intel Quartus Prime Lite 21.1 (no timing constrains, _balanced optimization_, f_max from _Slow 1200mV 0C Model_).
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| CPU Configuration (version [1.7.8.5](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
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|:-----------------------|:----:|:----:|:----:|:-:|:-------:|
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| `rv32i_Zicsr` | 1223 | 607 | 1024 | 0 | 130 MHz |
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| `rv32i_Zicsr_Zicntr` | 1578 | 773 | 1024 | 0 | 130 MHz |
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| `rv32imc_Zicsr_Zicntr` | 2338 | 992 | 1024 | 0 | 130 MHz |
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Implementation results for an **exemplary SoC/Processor configurations** generated for a Xilinx Artix-7 `xc7a35ticsg324-1L` FPGA
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using Xilinx Vivado 2019.2 (no constraints except for clock speed).
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| SoC Configuration (version [1.7.7.3](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LUTs | FFs | BRAMs | DSPs | Clock |
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|:------------------------------------------------------------------------------------------------------|:----:|:----:|:-----:|:----:|:-------:|
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| CPU: `rv32imcu_Zicsr_Zicnt_DEBUG` + `FST_MUL` + `FAST_SHIFT`; Peripherals: `UART0` + `MTIME` + `GPIO` | 2488 | 1807 | 7 | 4 | 150 MHz |
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:bulb: An incremental list of the CPU extensions and the Processor modules can be found in the
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[_Data Sheet: FPGA Implementation Results_](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 4. Performance
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The NEORV32 CPU is based on a two-stages pipeline architecture (fetch and execute).
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the
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available CPU extensions.
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The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing
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2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/main/sw/example/coremark) CPU benchmark
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(using plain GCC10 rv32i built-in libraries only!).
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | CoreMark Score | CoreMarks/MHz | Average CPI |
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|:------------------------------------------------|:-----:|:----------:|:--------:|
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04** |
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34** |
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54** |
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:bulb: More information regarding the CPU performance can be found in the
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[_Data Sheet: CPU Performance_](https://stnolting.github.io/neorv32/#_cpu_performance).
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The CPU & SoC provide further "tuning" options to optimize the design for maximum performance,
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maximum clock speed, minimal area or minimal power consumption:
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[_UG: Application-Specific Processor Configuration_](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 5. Software Framework and Tooling
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* [core libraries](https://github.com/stnolting/neorv32/tree/main/sw/lib) for high-level usage of the provided functions and peripherals
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* application compilation based on GNU makefiles
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* gcc-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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* [SVD file](https://github.com/stnolting/neorv32/tree/main/sw/svd) for advanced debugging and IDE integration
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* bootloader with UART interface console
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* runtime environment for handling traps
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* several [example programs](https://github.com/stnolting/neorv32/tree/main/sw/example) to get started including CoreMark, FreeRTOS and Conway's Game of Life
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* doxygen-based documentation, available on [GitHub pages](https://stnolting.github.io/neorv32/sw/files.html)
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* supports implementation using open source toolchains - both, software and hardware can be
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developed and debugged with open source tools ([GHDL](https://github.com/ghdl/ghdl), Yosys, nextpnr, openOCD, gtkwave, ...)
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* [continuous integration](https://github.com/stnolting/neorv32/actions) is available for:
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* allowing users to see the expected execution/output of the tools
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* ensuring RISC-V specification compatibility using [RISCOF](https://github.com/stnolting/neorv32-riscof)
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* catching regressions
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* providing ready-to-use and up-to-date [bitstreams](https://github.com/stnolting/neorv32-setups/actions/workflows/Implementation.yml)
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and [documentation](https://stnolting.github.io/neorv32/)
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:bulb: Want to know more? Check out the [_Data Sheet: Software Framework_](https://stnolting.github.io/neorv32/#_software_framework).
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 6. Getting Started
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This overview provides some *quick links* to the most important sections of the
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[online Data Sheet](https://stnolting.github.io/neorv32) and the [online User Guide](https://stnolting.github.io/neorv32/ug).
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### :mag: Project Overview
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* **[NEORV32 Project](https://stnolting.github.io/neorv32/#_overview) - introduction**
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* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - why? how come? what for?
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* [Key Features](https://stnolting.github.io/neorv32/#_project_key_features) - what makes it special
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* [Structure](https://stnolting.github.io/neorv32/#_project_folder_structure) - folders and RTL files
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* [Metrics](https://stnolting.github.io/neorv32/#_fpga_implementation_results) - FPGA implementation and performance evaluation
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### :electric_plug: Hardware Overview
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* **[NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - the SoC**
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - processor/CPU configuration options
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* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configurations
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - IO/peripheral modules and memories
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - in-system debugging of the processor via JTAG
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* **[NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - the Core**
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* [RISC-V Compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs and what is not
|
||
* [Architecture](https://stnolting.github.io/neorv32/#_architecture) - a look under the hood
|
||
* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - execution safety
|
||
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available (RISC-V) ISA extensions
|
||
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
||
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
||
|
||
### :floppy_disk: Software Overview
|
||
|
||
* [Example Programs](https://github.com/stnolting/neorv32/tree/main/sw/example) - examples how to use the processor's IO/peripheral modules
|
||
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
||
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - _doxygen_-based
|
||
* [Application Makefile](https://stnolting.github.io/neorv32/#_application_makefile) - turning _your_ application into an executable
|
||
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
|
||
|
||
### :rocket: User Guide
|
||
|
||
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and setup the RISC-V GCC toolchain
|
||
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - setup a new NEORV32 FPGA project
|
||
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
||
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using `make`
|
||
* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
|
||
* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
|
||
* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
|
||
* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
|
||
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
|
||
* [LiteX Integration](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) - build a SoC using NEORV32 + [LiteX](https://github.com/enjoy-digital/litex)
|
||
* [Convert to Verilog](https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog) - turn the NEORV32 into an all-Verilog design
|
||
|
||
### :copyright: Legal
|
||
|
||
[](https://github.com/stnolting/neorv32/blob/main/LICENSE)
|
||
[](https://doi.org/10.5281/zenodo.5018888)
|
||
|
||
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, etc.
|
||
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
||
|
||
This is an open-source project that is free of charge. Use this project in any way you like
|
||
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE)).
|
||
Please cite it appropriately. :+1:
|
||
|
||
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
||
|
||
|
||
---------------------------------------
|
||
|
||
**:heart: A big shout-out to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors), who helped improving this project!**
|