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This commit is contained in:
higepi 2023-03-09 14:56:26 +01:00
parent 311eadc3a4
commit 99d93a353f
97 changed files with 116669 additions and 5 deletions
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Rapport/Bandwidth/memory_cycles.png Normal file
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Rapport/Bandwidth/plot.py Normal file
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import matplotlib.pyplot as plt
from sklearn.linear_model import LinearRegression
import numpy as np
Y_MEM = [37, 3365, 6693, 10021, 13349, 16677, 20005, 23333, 26661]
Y_CPY = [36, 4004, 7972, 11940, 15908, 19876, 23844, 27812, 31780]
YA_MEM = [28, 1788, 3585, 5298, 7028, 9174, 10515, 12258, 14003]
YA_CPY = [31, 2477 , 4909 , 7372, 9802, 12217 , 15049, 17081, 19514]
X = [0, 128, 256, 384, 512, 640, 768, 896, 1024]
plt.scatter(X, Y_MEM, color="b", label="RISCV MEM")
plt.scatter(X, Y_CPY, color="b", marker="x", label="RISCV COPY")
plt.scatter(X, YA_MEM, color="r", label="ARM MEM")
plt.scatter(X, YA_CPY, color="r",marker="x", label="ARM COPY")
plt.xlim([0, 1024])
plt.ylim([50, 32000])
plt.legend()
plt.title("Cycles d'exécution en fonction de n_max")
plt.ylabel("Cycles")
plt.xlabel("N_max")
plt.savefig("memory_cycles.png")
plt.show()

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bandwidth_test/debug.txt Normal file
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bandwidth_test/main.c → bandwidth_test/mem.c
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@ -56,6 +56,12 @@ void fn_mem(uint32_t N, uint32_t *y){
} }
} }
void fn_copy(uint32_t N, uint32_t *x, uint32_t *y){
for(uint32_t i=0; i<N; i++){
*x = y[i];
}
}
/**********************************************************************//** /**********************************************************************//**
* Main function; prints some fancy stuff via UART. * Main function; prints some fancy stuff via UART.
@ -82,18 +88,29 @@ int main() {
neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK); neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
uint32_t y[1024]; uint32_t y[1024];
uint32_t x;
for(n_max=0; n_max<1024+1; n_max+=128){ for(n_max=0; n_max<1024+1; n_max+=128){
Begin_Time = (long)neorv32_mtime_get_time(); Begin_Time = (long)neorv32_mtime_get_time();
for(uint32_t j=0; j<10; j++){ for(uint32_t j=0; j<10; j++){
fn_mem(n_max, y); fn_mem(n_max, y);
} }
End_Time = (long)neorv32_mtime_get_time(); End_Time = (long)neorv32_mtime_get_time();
User_Time = End_Time - Begin_Time; User_Time = End_Time - Begin_Time;
neorv32_uart0_printf("NEORV32: mean cycles N = %u : %u\n",n_max, (uint32_t)User_Time/10); neorv32_uart0_printf("NEORV32: Memory mean cycles N = %u : %u\n",n_max, (uint32_t)User_Time/10);
Begin_Time = (long)neorv32_mtime_get_time();
for(uint32_t j=0; j<10; j++){
fn_copy(n_max, &x, y);
}
End_Time = (long)neorv32_mtime_get_time();
User_Time = End_Time - Begin_Time;
neorv32_uart0_printf("NEORV32: Copy mean cycles N = %u : %u\n",n_max, (uint32_t)User_Time/10);
} }
neorv32_uart0_puts("end:\n"); neorv32_uart0_puts("end:\n");
return 0; return 0;

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bandwidth_test/neorv32_exe.bin
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neorv32/rtl/core/neorv32_top.vhd.bak Normal file
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5
proj_quartus/.qsys_edit/preferences.xml
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@ -3,11 +3,10 @@
<debug showDebugMenu="0" /> <debug showDebugMenu="0" />
<systemtable filter="All Interfaces"> <systemtable filter="All Interfaces">
<columns> <columns>
<connections preferredWidth="143" /> <connections preferredWidth="47" />
<irq preferredWidth="34" /> <irq preferredWidth="34" />
</columns> </columns>
</systemtable> </systemtable>
<library <library expandedCategories="Library,Project" />
expandedCategories="Library/Qsys Interconnect/Memory-Mapped Alpha,Library/Basic Functions/Simulation; Debug and Verification/Simulation,Library/Qsys Interconnect/Memory-Mapped,Library/Basic Functions,Library/Processors and Peripherals/Hard Processor Components,Library/Qsys Interconnect,Library/Basic Functions/On Chip Memory,Project,Library/Memory Interfaces and Controllers,Library/Processors and Peripherals,Library/Basic Functions/Simulation; Debug and Verification,Library" />
<window width="1508" height="946" x="72" y="27" /> <window width="1508" height="946" x="72" y="27" />
</preferences> </preferences>

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proj_quartus/db/altsyncram_2aq1.tdf Normal file
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--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION decode_5la (data[0..0], enable)
RETURNS ( eq[1..0]);
FUNCTION mux_lfb (data[15..0], sel[0..0])
RETURNS ( result[7..0]);
FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = lut 4 M10K 16 reg 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_2aq1
(
address_a[13..0] : input;
address_b[13..0] : input;
clock0 : input;
data_a[7..0] : input;
q_b[7..0] : output;
rden_b : input;
wren_a : input;
)
VARIABLE
address_reg_b[0..0] : dffe;
decode2 : decode_5la;
mux3 : mux_lfb;
ram_block1a0 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 16384,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[13..0] : WIRE;
address_b_sel[0..0] : WIRE;
address_b_wire[13..0] : WIRE;
BEGIN
address_reg_b[].clk = clock0;
address_reg_b[].d = address_b_sel[];
address_reg_b[].ena = rden_b;
decode2.data[0..0] = address_a_wire[13..13];
decode2.enable = wren_a;
mux3.data[] = ( ram_block1a[15..0].portbdataout[0..0]);
mux3.sel[] = address_reg_b[].q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]);
ram_block1a[15..0].portbre = rden_b;
address_a_wire[] = address_a[];
address_b_sel[0..0] = address_b[13..13];
address_b_wire[] = address_b[];
q_b[] = mux3.result[];
END;
--VALID FILE

59460
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--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=32768 NUMWORDS_B=32768 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=15 WIDTHAD_B=15 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
FUNCTION decode_8la (data[1..0], enable)
RETURNS ( eq[3..0]);
FUNCTION mux_ofb (data[31..0], sel[1..0])
RETURNS ( result[7..0]);
FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = lut 12 M10K 32 reg 2
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_caq1
(
address_a[14..0] : input;
address_b[14..0] : input;
clock0 : input;
data_a[7..0] : input;
q_b[7..0] : output;
rden_b : input;
wren_a : input;
)
VARIABLE
address_reg_b[1..0] : dffe;
decode2 : decode_8la;
mux3 : mux_ofb;
ram_block1a0 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 8192,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 16383,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a16 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a17 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a18 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a19 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a20 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a21 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a22 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a23 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 16384,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 24575,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 16384,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 24575,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a24 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a25 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a26 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a27 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a28 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a29 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a30 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a31 : cyclonev_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 24576,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 32767,
PORT_A_LOGICAL_RAM_DEPTH = 32768,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 13,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 24576,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 32767,
PORT_B_LOGICAL_RAM_DEPTH = 32768,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[14..0] : WIRE;
address_b_sel[1..0] : WIRE;
address_b_wire[14..0] : WIRE;
BEGIN
address_reg_b[].clk = clock0;
address_reg_b[].d = address_b_sel[];
address_reg_b[].ena = rden_b;
decode2.data[1..0] = address_a_wire[14..13];
decode2.enable = wren_a;
mux3.data[] = ( ram_block1a[31..0].portbdataout[0..0]);
mux3.sel[] = address_reg_b[].q;
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[16].portadatain[] = ( data_a[0..0]);
ram_block1a[17].portadatain[] = ( data_a[1..1]);
ram_block1a[18].portadatain[] = ( data_a[2..2]);
ram_block1a[19].portadatain[] = ( data_a[3..3]);
ram_block1a[20].portadatain[] = ( data_a[4..4]);
ram_block1a[21].portadatain[] = ( data_a[5..5]);
ram_block1a[22].portadatain[] = ( data_a[6..6]);
ram_block1a[23].portadatain[] = ( data_a[7..7]);
ram_block1a[24].portadatain[] = ( data_a[0..0]);
ram_block1a[25].portadatain[] = ( data_a[1..1]);
ram_block1a[26].portadatain[] = ( data_a[2..2]);
ram_block1a[27].portadatain[] = ( data_a[3..3]);
ram_block1a[28].portadatain[] = ( data_a[4..4]);
ram_block1a[29].portadatain[] = ( data_a[5..5]);
ram_block1a[30].portadatain[] = ( data_a[6..6]);
ram_block1a[31].portadatain[] = ( data_a[7..7]);
ram_block1a[31..0].portawe = ( decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
ram_block1a[31..0].portbaddr[] = ( address_b_wire[12..0]);
ram_block1a[31..0].portbre = rden_b;
address_a_wire[] = address_a[];
address_b_sel[1..0] = address_b[14..13];
address_b_wire[] = address_b[];
q_b[] = mux3.result[];
END;
--VALID FILE

1924
proj_quartus/db/altsyncram_daq1.tdf Normal file
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3780
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14916
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@ -0,0 +1,188 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=64 LPM_WIDTH=6 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 72
SUBDESIGN decode_2na
(
data[5..0] : input;
enable : input;
eq[63..0] : output;
)
VARIABLE
data_wire[5..0] : WIRE;
enable_wire : WIRE;
eq_node[63..0] : WIRE;
eq_wire[63..0] : WIRE;
w_anode4241w[3..0] : WIRE;
w_anode4258w[3..0] : WIRE;
w_anode4275w[3..0] : WIRE;
w_anode4285w[3..0] : WIRE;
w_anode4295w[3..0] : WIRE;
w_anode4305w[3..0] : WIRE;
w_anode4315w[3..0] : WIRE;
w_anode4325w[3..0] : WIRE;
w_anode4335w[3..0] : WIRE;
w_anode4347w[3..0] : WIRE;
w_anode4358w[3..0] : WIRE;
w_anode4369w[3..0] : WIRE;
w_anode4379w[3..0] : WIRE;
w_anode4389w[3..0] : WIRE;
w_anode4399w[3..0] : WIRE;
w_anode4409w[3..0] : WIRE;
w_anode4419w[3..0] : WIRE;
w_anode4429w[3..0] : WIRE;
w_anode4440w[3..0] : WIRE;
w_anode4451w[3..0] : WIRE;
w_anode4462w[3..0] : WIRE;
w_anode4472w[3..0] : WIRE;
w_anode4482w[3..0] : WIRE;
w_anode4492w[3..0] : WIRE;
w_anode4502w[3..0] : WIRE;
w_anode4512w[3..0] : WIRE;
w_anode4522w[3..0] : WIRE;
w_anode4533w[3..0] : WIRE;
w_anode4544w[3..0] : WIRE;
w_anode4555w[3..0] : WIRE;
w_anode4565w[3..0] : WIRE;
w_anode4575w[3..0] : WIRE;
w_anode4585w[3..0] : WIRE;
w_anode4595w[3..0] : WIRE;
w_anode4605w[3..0] : WIRE;
w_anode4615w[3..0] : WIRE;
w_anode4626w[3..0] : WIRE;
w_anode4637w[3..0] : WIRE;
w_anode4648w[3..0] : WIRE;
w_anode4658w[3..0] : WIRE;
w_anode4668w[3..0] : WIRE;
w_anode4678w[3..0] : WIRE;
w_anode4688w[3..0] : WIRE;
w_anode4698w[3..0] : WIRE;
w_anode4708w[3..0] : WIRE;
w_anode4719w[3..0] : WIRE;
w_anode4730w[3..0] : WIRE;
w_anode4741w[3..0] : WIRE;
w_anode4751w[3..0] : WIRE;
w_anode4761w[3..0] : WIRE;
w_anode4771w[3..0] : WIRE;
w_anode4781w[3..0] : WIRE;
w_anode4791w[3..0] : WIRE;
w_anode4801w[3..0] : WIRE;
w_anode4812w[3..0] : WIRE;
w_anode4823w[3..0] : WIRE;
w_anode4834w[3..0] : WIRE;
w_anode4844w[3..0] : WIRE;
w_anode4854w[3..0] : WIRE;
w_anode4864w[3..0] : WIRE;
w_anode4874w[3..0] : WIRE;
w_anode4884w[3..0] : WIRE;
w_anode4894w[3..0] : WIRE;
w_anode4905w[3..0] : WIRE;
w_anode4916w[3..0] : WIRE;
w_anode4927w[3..0] : WIRE;
w_anode4937w[3..0] : WIRE;
w_anode4947w[3..0] : WIRE;
w_anode4957w[3..0] : WIRE;
w_anode4967w[3..0] : WIRE;
w_anode4977w[3..0] : WIRE;
w_anode4987w[3..0] : WIRE;
w_data4239w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[63..0] = eq_wire[63..0];
eq_wire[] = ( ( w_anode4987w[3..3], w_anode4977w[3..3], w_anode4967w[3..3], w_anode4957w[3..3], w_anode4947w[3..3], w_anode4937w[3..3], w_anode4927w[3..3], w_anode4916w[3..3]), ( w_anode4894w[3..3], w_anode4884w[3..3], w_anode4874w[3..3], w_anode4864w[3..3], w_anode4854w[3..3], w_anode4844w[3..3], w_anode4834w[3..3], w_anode4823w[3..3]), ( w_anode4801w[3..3], w_anode4791w[3..3], w_anode4781w[3..3], w_anode4771w[3..3], w_anode4761w[3..3], w_anode4751w[3..3], w_anode4741w[3..3], w_anode4730w[3..3]), ( w_anode4708w[3..3], w_anode4698w[3..3], w_anode4688w[3..3], w_anode4678w[3..3], w_anode4668w[3..3], w_anode4658w[3..3], w_anode4648w[3..3], w_anode4637w[3..3]), ( w_anode4615w[3..3], w_anode4605w[3..3], w_anode4595w[3..3], w_anode4585w[3..3], w_anode4575w[3..3], w_anode4565w[3..3], w_anode4555w[3..3], w_anode4544w[3..3]), ( w_anode4522w[3..3], w_anode4512w[3..3], w_anode4502w[3..3], w_anode4492w[3..3], w_anode4482w[3..3], w_anode4472w[3..3], w_anode4462w[3..3], w_anode4451w[3..3]), ( w_anode4429w[3..3], w_anode4419w[3..3], w_anode4409w[3..3], w_anode4399w[3..3], w_anode4389w[3..3], w_anode4379w[3..3], w_anode4369w[3..3], w_anode4358w[3..3]), ( w_anode4335w[3..3], w_anode4325w[3..3], w_anode4315w[3..3], w_anode4305w[3..3], w_anode4295w[3..3], w_anode4285w[3..3], w_anode4275w[3..3], w_anode4258w[3..3]));
w_anode4241w[] = ( (w_anode4241w[2..2] & (! data_wire[5..5])), (w_anode4241w[1..1] & (! data_wire[4..4])), (w_anode4241w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode4258w[] = ( (w_anode4258w[2..2] & (! w_data4239w[2..2])), (w_anode4258w[1..1] & (! w_data4239w[1..1])), (w_anode4258w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]);
w_anode4275w[] = ( (w_anode4275w[2..2] & (! w_data4239w[2..2])), (w_anode4275w[1..1] & (! w_data4239w[1..1])), (w_anode4275w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]);
w_anode4285w[] = ( (w_anode4285w[2..2] & (! w_data4239w[2..2])), (w_anode4285w[1..1] & w_data4239w[1..1]), (w_anode4285w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]);
w_anode4295w[] = ( (w_anode4295w[2..2] & (! w_data4239w[2..2])), (w_anode4295w[1..1] & w_data4239w[1..1]), (w_anode4295w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]);
w_anode4305w[] = ( (w_anode4305w[2..2] & w_data4239w[2..2]), (w_anode4305w[1..1] & (! w_data4239w[1..1])), (w_anode4305w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]);
w_anode4315w[] = ( (w_anode4315w[2..2] & w_data4239w[2..2]), (w_anode4315w[1..1] & (! w_data4239w[1..1])), (w_anode4315w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]);
w_anode4325w[] = ( (w_anode4325w[2..2] & w_data4239w[2..2]), (w_anode4325w[1..1] & w_data4239w[1..1]), (w_anode4325w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]);
w_anode4335w[] = ( (w_anode4335w[2..2] & w_data4239w[2..2]), (w_anode4335w[1..1] & w_data4239w[1..1]), (w_anode4335w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]);
w_anode4347w[] = ( (w_anode4347w[2..2] & (! data_wire[5..5])), (w_anode4347w[1..1] & (! data_wire[4..4])), (w_anode4347w[0..0] & data_wire[3..3]), enable_wire);
w_anode4358w[] = ( (w_anode4358w[2..2] & (! w_data4239w[2..2])), (w_anode4358w[1..1] & (! w_data4239w[1..1])), (w_anode4358w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]);
w_anode4369w[] = ( (w_anode4369w[2..2] & (! w_data4239w[2..2])), (w_anode4369w[1..1] & (! w_data4239w[1..1])), (w_anode4369w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]);
w_anode4379w[] = ( (w_anode4379w[2..2] & (! w_data4239w[2..2])), (w_anode4379w[1..1] & w_data4239w[1..1]), (w_anode4379w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]);
w_anode4389w[] = ( (w_anode4389w[2..2] & (! w_data4239w[2..2])), (w_anode4389w[1..1] & w_data4239w[1..1]), (w_anode4389w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]);
w_anode4399w[] = ( (w_anode4399w[2..2] & w_data4239w[2..2]), (w_anode4399w[1..1] & (! w_data4239w[1..1])), (w_anode4399w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]);
w_anode4409w[] = ( (w_anode4409w[2..2] & w_data4239w[2..2]), (w_anode4409w[1..1] & (! w_data4239w[1..1])), (w_anode4409w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]);
w_anode4419w[] = ( (w_anode4419w[2..2] & w_data4239w[2..2]), (w_anode4419w[1..1] & w_data4239w[1..1]), (w_anode4419w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]);
w_anode4429w[] = ( (w_anode4429w[2..2] & w_data4239w[2..2]), (w_anode4429w[1..1] & w_data4239w[1..1]), (w_anode4429w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]);
w_anode4440w[] = ( (w_anode4440w[2..2] & (! data_wire[5..5])), (w_anode4440w[1..1] & data_wire[4..4]), (w_anode4440w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode4451w[] = ( (w_anode4451w[2..2] & (! w_data4239w[2..2])), (w_anode4451w[1..1] & (! w_data4239w[1..1])), (w_anode4451w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]);
w_anode4462w[] = ( (w_anode4462w[2..2] & (! w_data4239w[2..2])), (w_anode4462w[1..1] & (! w_data4239w[1..1])), (w_anode4462w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]);
w_anode4472w[] = ( (w_anode4472w[2..2] & (! w_data4239w[2..2])), (w_anode4472w[1..1] & w_data4239w[1..1]), (w_anode4472w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]);
w_anode4482w[] = ( (w_anode4482w[2..2] & (! w_data4239w[2..2])), (w_anode4482w[1..1] & w_data4239w[1..1]), (w_anode4482w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]);
w_anode4492w[] = ( (w_anode4492w[2..2] & w_data4239w[2..2]), (w_anode4492w[1..1] & (! w_data4239w[1..1])), (w_anode4492w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]);
w_anode4502w[] = ( (w_anode4502w[2..2] & w_data4239w[2..2]), (w_anode4502w[1..1] & (! w_data4239w[1..1])), (w_anode4502w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]);
w_anode4512w[] = ( (w_anode4512w[2..2] & w_data4239w[2..2]), (w_anode4512w[1..1] & w_data4239w[1..1]), (w_anode4512w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]);
w_anode4522w[] = ( (w_anode4522w[2..2] & w_data4239w[2..2]), (w_anode4522w[1..1] & w_data4239w[1..1]), (w_anode4522w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]);
w_anode4533w[] = ( (w_anode4533w[2..2] & (! data_wire[5..5])), (w_anode4533w[1..1] & data_wire[4..4]), (w_anode4533w[0..0] & data_wire[3..3]), enable_wire);
w_anode4544w[] = ( (w_anode4544w[2..2] & (! w_data4239w[2..2])), (w_anode4544w[1..1] & (! w_data4239w[1..1])), (w_anode4544w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]);
w_anode4555w[] = ( (w_anode4555w[2..2] & (! w_data4239w[2..2])), (w_anode4555w[1..1] & (! w_data4239w[1..1])), (w_anode4555w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]);
w_anode4565w[] = ( (w_anode4565w[2..2] & (! w_data4239w[2..2])), (w_anode4565w[1..1] & w_data4239w[1..1]), (w_anode4565w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]);
w_anode4575w[] = ( (w_anode4575w[2..2] & (! w_data4239w[2..2])), (w_anode4575w[1..1] & w_data4239w[1..1]), (w_anode4575w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]);
w_anode4585w[] = ( (w_anode4585w[2..2] & w_data4239w[2..2]), (w_anode4585w[1..1] & (! w_data4239w[1..1])), (w_anode4585w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]);
w_anode4595w[] = ( (w_anode4595w[2..2] & w_data4239w[2..2]), (w_anode4595w[1..1] & (! w_data4239w[1..1])), (w_anode4595w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]);
w_anode4605w[] = ( (w_anode4605w[2..2] & w_data4239w[2..2]), (w_anode4605w[1..1] & w_data4239w[1..1]), (w_anode4605w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]);
w_anode4615w[] = ( (w_anode4615w[2..2] & w_data4239w[2..2]), (w_anode4615w[1..1] & w_data4239w[1..1]), (w_anode4615w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]);
w_anode4626w[] = ( (w_anode4626w[2..2] & data_wire[5..5]), (w_anode4626w[1..1] & (! data_wire[4..4])), (w_anode4626w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode4637w[] = ( (w_anode4637w[2..2] & (! w_data4239w[2..2])), (w_anode4637w[1..1] & (! w_data4239w[1..1])), (w_anode4637w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]);
w_anode4648w[] = ( (w_anode4648w[2..2] & (! w_data4239w[2..2])), (w_anode4648w[1..1] & (! w_data4239w[1..1])), (w_anode4648w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]);
w_anode4658w[] = ( (w_anode4658w[2..2] & (! w_data4239w[2..2])), (w_anode4658w[1..1] & w_data4239w[1..1]), (w_anode4658w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]);
w_anode4668w[] = ( (w_anode4668w[2..2] & (! w_data4239w[2..2])), (w_anode4668w[1..1] & w_data4239w[1..1]), (w_anode4668w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]);
w_anode4678w[] = ( (w_anode4678w[2..2] & w_data4239w[2..2]), (w_anode4678w[1..1] & (! w_data4239w[1..1])), (w_anode4678w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]);
w_anode4688w[] = ( (w_anode4688w[2..2] & w_data4239w[2..2]), (w_anode4688w[1..1] & (! w_data4239w[1..1])), (w_anode4688w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]);
w_anode4698w[] = ( (w_anode4698w[2..2] & w_data4239w[2..2]), (w_anode4698w[1..1] & w_data4239w[1..1]), (w_anode4698w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]);
w_anode4708w[] = ( (w_anode4708w[2..2] & w_data4239w[2..2]), (w_anode4708w[1..1] & w_data4239w[1..1]), (w_anode4708w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]);
w_anode4719w[] = ( (w_anode4719w[2..2] & data_wire[5..5]), (w_anode4719w[1..1] & (! data_wire[4..4])), (w_anode4719w[0..0] & data_wire[3..3]), enable_wire);
w_anode4730w[] = ( (w_anode4730w[2..2] & (! w_data4239w[2..2])), (w_anode4730w[1..1] & (! w_data4239w[1..1])), (w_anode4730w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]);
w_anode4741w[] = ( (w_anode4741w[2..2] & (! w_data4239w[2..2])), (w_anode4741w[1..1] & (! w_data4239w[1..1])), (w_anode4741w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]);
w_anode4751w[] = ( (w_anode4751w[2..2] & (! w_data4239w[2..2])), (w_anode4751w[1..1] & w_data4239w[1..1]), (w_anode4751w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]);
w_anode4761w[] = ( (w_anode4761w[2..2] & (! w_data4239w[2..2])), (w_anode4761w[1..1] & w_data4239w[1..1]), (w_anode4761w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]);
w_anode4771w[] = ( (w_anode4771w[2..2] & w_data4239w[2..2]), (w_anode4771w[1..1] & (! w_data4239w[1..1])), (w_anode4771w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]);
w_anode4781w[] = ( (w_anode4781w[2..2] & w_data4239w[2..2]), (w_anode4781w[1..1] & (! w_data4239w[1..1])), (w_anode4781w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]);
w_anode4791w[] = ( (w_anode4791w[2..2] & w_data4239w[2..2]), (w_anode4791w[1..1] & w_data4239w[1..1]), (w_anode4791w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]);
w_anode4801w[] = ( (w_anode4801w[2..2] & w_data4239w[2..2]), (w_anode4801w[1..1] & w_data4239w[1..1]), (w_anode4801w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]);
w_anode4812w[] = ( (w_anode4812w[2..2] & data_wire[5..5]), (w_anode4812w[1..1] & data_wire[4..4]), (w_anode4812w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode4823w[] = ( (w_anode4823w[2..2] & (! w_data4239w[2..2])), (w_anode4823w[1..1] & (! w_data4239w[1..1])), (w_anode4823w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]);
w_anode4834w[] = ( (w_anode4834w[2..2] & (! w_data4239w[2..2])), (w_anode4834w[1..1] & (! w_data4239w[1..1])), (w_anode4834w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]);
w_anode4844w[] = ( (w_anode4844w[2..2] & (! w_data4239w[2..2])), (w_anode4844w[1..1] & w_data4239w[1..1]), (w_anode4844w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]);
w_anode4854w[] = ( (w_anode4854w[2..2] & (! w_data4239w[2..2])), (w_anode4854w[1..1] & w_data4239w[1..1]), (w_anode4854w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]);
w_anode4864w[] = ( (w_anode4864w[2..2] & w_data4239w[2..2]), (w_anode4864w[1..1] & (! w_data4239w[1..1])), (w_anode4864w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]);
w_anode4874w[] = ( (w_anode4874w[2..2] & w_data4239w[2..2]), (w_anode4874w[1..1] & (! w_data4239w[1..1])), (w_anode4874w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]);
w_anode4884w[] = ( (w_anode4884w[2..2] & w_data4239w[2..2]), (w_anode4884w[1..1] & w_data4239w[1..1]), (w_anode4884w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]);
w_anode4894w[] = ( (w_anode4894w[2..2] & w_data4239w[2..2]), (w_anode4894w[1..1] & w_data4239w[1..1]), (w_anode4894w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]);
w_anode4905w[] = ( (w_anode4905w[2..2] & data_wire[5..5]), (w_anode4905w[1..1] & data_wire[4..4]), (w_anode4905w[0..0] & data_wire[3..3]), enable_wire);
w_anode4916w[] = ( (w_anode4916w[2..2] & (! w_data4239w[2..2])), (w_anode4916w[1..1] & (! w_data4239w[1..1])), (w_anode4916w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]);
w_anode4927w[] = ( (w_anode4927w[2..2] & (! w_data4239w[2..2])), (w_anode4927w[1..1] & (! w_data4239w[1..1])), (w_anode4927w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]);
w_anode4937w[] = ( (w_anode4937w[2..2] & (! w_data4239w[2..2])), (w_anode4937w[1..1] & w_data4239w[1..1]), (w_anode4937w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]);
w_anode4947w[] = ( (w_anode4947w[2..2] & (! w_data4239w[2..2])), (w_anode4947w[1..1] & w_data4239w[1..1]), (w_anode4947w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]);
w_anode4957w[] = ( (w_anode4957w[2..2] & w_data4239w[2..2]), (w_anode4957w[1..1] & (! w_data4239w[1..1])), (w_anode4957w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]);
w_anode4967w[] = ( (w_anode4967w[2..2] & w_data4239w[2..2]), (w_anode4967w[1..1] & (! w_data4239w[1..1])), (w_anode4967w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]);
w_anode4977w[] = ( (w_anode4977w[2..2] & w_data4239w[2..2]), (w_anode4977w[1..1] & w_data4239w[1..1]), (w_anode4977w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]);
w_anode4987w[] = ( (w_anode4987w[2..2] & w_data4239w[2..2]), (w_anode4987w[1..1] & w_data4239w[1..1]), (w_anode4987w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]);
w_data4239w[2..0] = data_wire[2..0];
END;
--VALID FILE

36
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=2 LPM_WIDTH=1 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 1
SUBDESIGN decode_5la
(
data[0..0] : input;
enable : input;
eq[1..0] : output;
)
VARIABLE
eq_node[1..0] : WIRE;
BEGIN
eq[] = eq_node[];
eq_node[] = ( (data[] & enable), ((! data[]) & enable));
END;
--VALID FILE

50
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 4
SUBDESIGN decode_8la
(
data[1..0] : input;
enable : input;
eq[3..0] : output;
)
VARIABLE
data_wire[1..0] : WIRE;
enable_wire : WIRE;
eq_node[3..0] : WIRE;
eq_wire[3..0] : WIRE;
w_anode279w[2..0] : WIRE;
w_anode292w[2..0] : WIRE;
w_anode300w[2..0] : WIRE;
w_anode308w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[3..0] = eq_wire[3..0];
eq_wire[] = ( w_anode308w[2..2], w_anode300w[2..2], w_anode292w[2..2], w_anode279w[2..2]);
w_anode279w[] = ( (w_anode279w[1..1] & (! data_wire[1..1])), (w_anode279w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode292w[] = ( (w_anode292w[1..1] & (! data_wire[1..1])), (w_anode292w[0..0] & data_wire[0..0]), enable_wire);
w_anode300w[] = ( (w_anode300w[1..1] & data_wire[1..1]), (w_anode300w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode308w[] = ( (w_anode308w[1..1] & data_wire[1..1]), (w_anode308w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE

58
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 8
SUBDESIGN decode_dla
(
data[2..0] : input;
enable : input;
eq[7..0] : output;
)
VARIABLE
data_wire[2..0] : WIRE;
enable_wire : WIRE;
eq_node[7..0] : WIRE;
eq_wire[7..0] : WIRE;
w_anode543w[3..0] : WIRE;
w_anode560w[3..0] : WIRE;
w_anode570w[3..0] : WIRE;
w_anode580w[3..0] : WIRE;
w_anode590w[3..0] : WIRE;
w_anode600w[3..0] : WIRE;
w_anode610w[3..0] : WIRE;
w_anode620w[3..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[7..0] = eq_wire[7..0];
eq_wire[] = ( w_anode620w[3..3], w_anode610w[3..3], w_anode600w[3..3], w_anode590w[3..3], w_anode580w[3..3], w_anode570w[3..3], w_anode560w[3..3], w_anode543w[3..3]);
w_anode543w[] = ( (w_anode543w[2..2] & (! data_wire[2..2])), (w_anode543w[1..1] & (! data_wire[1..1])), (w_anode543w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode560w[] = ( (w_anode560w[2..2] & (! data_wire[2..2])), (w_anode560w[1..1] & (! data_wire[1..1])), (w_anode560w[0..0] & data_wire[0..0]), enable_wire);
w_anode570w[] = ( (w_anode570w[2..2] & (! data_wire[2..2])), (w_anode570w[1..1] & data_wire[1..1]), (w_anode570w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode580w[] = ( (w_anode580w[2..2] & (! data_wire[2..2])), (w_anode580w[1..1] & data_wire[1..1]), (w_anode580w[0..0] & data_wire[0..0]), enable_wire);
w_anode590w[] = ( (w_anode590w[2..2] & data_wire[2..2]), (w_anode590w[1..1] & (! data_wire[1..1])), (w_anode590w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode600w[] = ( (w_anode600w[2..2] & data_wire[2..2]), (w_anode600w[1..1] & (! data_wire[1..1])), (w_anode600w[0..0] & data_wire[0..0]), enable_wire);
w_anode610w[] = ( (w_anode610w[2..2] & data_wire[2..2]), (w_anode610w[1..1] & data_wire[1..1]), (w_anode610w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode620w[] = ( (w_anode620w[2..2] & data_wire[2..2]), (w_anode620w[1..1] & data_wire[1..1]), (w_anode620w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE

636
proj_quartus/db/decode_noa.tdf Normal file
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80
proj_quartus/db/decode_tma.tdf Normal file
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@ -0,0 +1,80 @@
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=16 LPM_WIDTH=4 data enable eq
--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 18
SUBDESIGN decode_tma
(
data[3..0] : input;
enable : input;
eq[15..0] : output;
)
VARIABLE
data_wire[3..0] : WIRE;
enable_wire : WIRE;
eq_node[15..0] : WIRE;
eq_wire[15..0] : WIRE;
w_anode1073w[1..0] : WIRE;
w_anode1082w[3..0] : WIRE;
w_anode1099w[3..0] : WIRE;
w_anode1109w[3..0] : WIRE;
w_anode1119w[3..0] : WIRE;
w_anode1129w[3..0] : WIRE;
w_anode1139w[3..0] : WIRE;
w_anode1149w[3..0] : WIRE;
w_anode1159w[3..0] : WIRE;
w_anode1171w[1..0] : WIRE;
w_anode1178w[3..0] : WIRE;
w_anode1189w[3..0] : WIRE;
w_anode1199w[3..0] : WIRE;
w_anode1209w[3..0] : WIRE;
w_anode1219w[3..0] : WIRE;
w_anode1229w[3..0] : WIRE;
w_anode1239w[3..0] : WIRE;
w_anode1249w[3..0] : WIRE;
w_data1071w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[15..0] = eq_wire[15..0];
eq_wire[] = ( ( w_anode1249w[3..3], w_anode1239w[3..3], w_anode1229w[3..3], w_anode1219w[3..3], w_anode1209w[3..3], w_anode1199w[3..3], w_anode1189w[3..3], w_anode1178w[3..3]), ( w_anode1159w[3..3], w_anode1149w[3..3], w_anode1139w[3..3], w_anode1129w[3..3], w_anode1119w[3..3], w_anode1109w[3..3], w_anode1099w[3..3], w_anode1082w[3..3]));
w_anode1073w[] = ( (w_anode1073w[0..0] & (! data_wire[3..3])), enable_wire);
w_anode1082w[] = ( (w_anode1082w[2..2] & (! w_data1071w[2..2])), (w_anode1082w[1..1] & (! w_data1071w[1..1])), (w_anode1082w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
w_anode1099w[] = ( (w_anode1099w[2..2] & (! w_data1071w[2..2])), (w_anode1099w[1..1] & (! w_data1071w[1..1])), (w_anode1099w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
w_anode1109w[] = ( (w_anode1109w[2..2] & (! w_data1071w[2..2])), (w_anode1109w[1..1] & w_data1071w[1..1]), (w_anode1109w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
w_anode1119w[] = ( (w_anode1119w[2..2] & (! w_data1071w[2..2])), (w_anode1119w[1..1] & w_data1071w[1..1]), (w_anode1119w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
w_anode1129w[] = ( (w_anode1129w[2..2] & w_data1071w[2..2]), (w_anode1129w[1..1] & (! w_data1071w[1..1])), (w_anode1129w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
w_anode1139w[] = ( (w_anode1139w[2..2] & w_data1071w[2..2]), (w_anode1139w[1..1] & (! w_data1071w[1..1])), (w_anode1139w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
w_anode1149w[] = ( (w_anode1149w[2..2] & w_data1071w[2..2]), (w_anode1149w[1..1] & w_data1071w[1..1]), (w_anode1149w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
w_anode1159w[] = ( (w_anode1159w[2..2] & w_data1071w[2..2]), (w_anode1159w[1..1] & w_data1071w[1..1]), (w_anode1159w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
w_anode1171w[] = ( (w_anode1171w[0..0] & data_wire[3..3]), enable_wire);
w_anode1178w[] = ( (w_anode1178w[2..2] & (! w_data1071w[2..2])), (w_anode1178w[1..1] & (! w_data1071w[1..1])), (w_anode1178w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
w_anode1189w[] = ( (w_anode1189w[2..2] & (! w_data1071w[2..2])), (w_anode1189w[1..1] & (! w_data1071w[1..1])), (w_anode1189w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
w_anode1199w[] = ( (w_anode1199w[2..2] & (! w_data1071w[2..2])), (w_anode1199w[1..1] & w_data1071w[1..1]), (w_anode1199w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
w_anode1209w[] = ( (w_anode1209w[2..2] & (! w_data1071w[2..2])), (w_anode1209w[1..1] & w_data1071w[1..1]), (w_anode1209w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
w_anode1219w[] = ( (w_anode1219w[2..2] & w_data1071w[2..2]), (w_anode1219w[1..1] & (! w_data1071w[1..1])), (w_anode1219w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
w_anode1229w[] = ( (w_anode1229w[2..2] & w_data1071w[2..2]), (w_anode1229w[1..1] & (! w_data1071w[1..1])), (w_anode1229w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
w_anode1239w[] = ( (w_anode1239w[2..2] & w_data1071w[2..2]), (w_anode1239w[1..1] & w_data1071w[1..1]), (w_anode1239w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
w_anode1249w[] = ( (w_anode1249w[2..2] & w_data1071w[2..2]), (w_anode1249w[1..1] & w_data1071w[1..1]), (w_anode1249w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
w_data1071w[2..0] = data_wire[2..0];
END;
--VALID FILE

4120
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=16 LPM_WIDTH=8 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 40
SUBDESIGN mux_dhb
(
data[127..0] : input;
result[7..0] : output;
sel[3..0] : input;
)
VARIABLE
l1_w0_n0_mux_dataout : WIRE;
l1_w0_n1_mux_dataout : WIRE;
l1_w0_n2_mux_dataout : WIRE;
l1_w0_n3_mux_dataout : WIRE;
l1_w0_n4_mux_dataout : WIRE;
l1_w0_n5_mux_dataout : WIRE;
l1_w0_n6_mux_dataout : WIRE;
l1_w0_n7_mux_dataout : WIRE;
l1_w1_n0_mux_dataout : WIRE;
l1_w1_n1_mux_dataout : WIRE;
l1_w1_n2_mux_dataout : WIRE;
l1_w1_n3_mux_dataout : WIRE;
l1_w1_n4_mux_dataout : WIRE;
l1_w1_n5_mux_dataout : WIRE;
l1_w1_n6_mux_dataout : WIRE;
l1_w1_n7_mux_dataout : WIRE;
l1_w2_n0_mux_dataout : WIRE;
l1_w2_n1_mux_dataout : WIRE;
l1_w2_n2_mux_dataout : WIRE;
l1_w2_n3_mux_dataout : WIRE;
l1_w2_n4_mux_dataout : WIRE;
l1_w2_n5_mux_dataout : WIRE;
l1_w2_n6_mux_dataout : WIRE;
l1_w2_n7_mux_dataout : WIRE;
l1_w3_n0_mux_dataout : WIRE;
l1_w3_n1_mux_dataout : WIRE;
l1_w3_n2_mux_dataout : WIRE;
l1_w3_n3_mux_dataout : WIRE;
l1_w3_n4_mux_dataout : WIRE;
l1_w3_n5_mux_dataout : WIRE;
l1_w3_n6_mux_dataout : WIRE;
l1_w3_n7_mux_dataout : WIRE;
l1_w4_n0_mux_dataout : WIRE;
l1_w4_n1_mux_dataout : WIRE;
l1_w4_n2_mux_dataout : WIRE;
l1_w4_n3_mux_dataout : WIRE;
l1_w4_n4_mux_dataout : WIRE;
l1_w4_n5_mux_dataout : WIRE;
l1_w4_n6_mux_dataout : WIRE;
l1_w4_n7_mux_dataout : WIRE;
l1_w5_n0_mux_dataout : WIRE;
l1_w5_n1_mux_dataout : WIRE;
l1_w5_n2_mux_dataout : WIRE;
l1_w5_n3_mux_dataout : WIRE;
l1_w5_n4_mux_dataout : WIRE;
l1_w5_n5_mux_dataout : WIRE;
l1_w5_n6_mux_dataout : WIRE;
l1_w5_n7_mux_dataout : WIRE;
l1_w6_n0_mux_dataout : WIRE;
l1_w6_n1_mux_dataout : WIRE;
l1_w6_n2_mux_dataout : WIRE;
l1_w6_n3_mux_dataout : WIRE;
l1_w6_n4_mux_dataout : WIRE;
l1_w6_n5_mux_dataout : WIRE;
l1_w6_n6_mux_dataout : WIRE;
l1_w6_n7_mux_dataout : WIRE;
l1_w7_n0_mux_dataout : WIRE;
l1_w7_n1_mux_dataout : WIRE;
l1_w7_n2_mux_dataout : WIRE;
l1_w7_n3_mux_dataout : WIRE;
l1_w7_n4_mux_dataout : WIRE;
l1_w7_n5_mux_dataout : WIRE;
l1_w7_n6_mux_dataout : WIRE;
l1_w7_n7_mux_dataout : WIRE;
l2_w0_n0_mux_dataout : WIRE;
l2_w0_n1_mux_dataout : WIRE;
l2_w0_n2_mux_dataout : WIRE;
l2_w0_n3_mux_dataout : WIRE;
l2_w1_n0_mux_dataout : WIRE;
l2_w1_n1_mux_dataout : WIRE;
l2_w1_n2_mux_dataout : WIRE;
l2_w1_n3_mux_dataout : WIRE;
l2_w2_n0_mux_dataout : WIRE;
l2_w2_n1_mux_dataout : WIRE;
l2_w2_n2_mux_dataout : WIRE;
l2_w2_n3_mux_dataout : WIRE;
l2_w3_n0_mux_dataout : WIRE;
l2_w3_n1_mux_dataout : WIRE;
l2_w3_n2_mux_dataout : WIRE;
l2_w3_n3_mux_dataout : WIRE;
l2_w4_n0_mux_dataout : WIRE;
l2_w4_n1_mux_dataout : WIRE;
l2_w4_n2_mux_dataout : WIRE;
l2_w4_n3_mux_dataout : WIRE;
l2_w5_n0_mux_dataout : WIRE;
l2_w5_n1_mux_dataout : WIRE;
l2_w5_n2_mux_dataout : WIRE;
l2_w5_n3_mux_dataout : WIRE;
l2_w6_n0_mux_dataout : WIRE;
l2_w6_n1_mux_dataout : WIRE;
l2_w6_n2_mux_dataout : WIRE;
l2_w6_n3_mux_dataout : WIRE;
l2_w7_n0_mux_dataout : WIRE;
l2_w7_n1_mux_dataout : WIRE;
l2_w7_n2_mux_dataout : WIRE;
l2_w7_n3_mux_dataout : WIRE;
l3_w0_n0_mux_dataout : WIRE;
l3_w0_n1_mux_dataout : WIRE;
l3_w1_n0_mux_dataout : WIRE;
l3_w1_n1_mux_dataout : WIRE;
l3_w2_n0_mux_dataout : WIRE;
l3_w2_n1_mux_dataout : WIRE;
l3_w3_n0_mux_dataout : WIRE;
l3_w3_n1_mux_dataout : WIRE;
l3_w4_n0_mux_dataout : WIRE;
l3_w4_n1_mux_dataout : WIRE;
l3_w5_n0_mux_dataout : WIRE;
l3_w5_n1_mux_dataout : WIRE;
l3_w6_n0_mux_dataout : WIRE;
l3_w6_n1_mux_dataout : WIRE;
l3_w7_n0_mux_dataout : WIRE;
l3_w7_n1_mux_dataout : WIRE;
l4_w0_n0_mux_dataout : WIRE;
l4_w1_n0_mux_dataout : WIRE;
l4_w2_n0_mux_dataout : WIRE;
l4_w3_n0_mux_dataout : WIRE;
l4_w4_n0_mux_dataout : WIRE;
l4_w5_n0_mux_dataout : WIRE;
l4_w6_n0_mux_dataout : WIRE;
l4_w7_n0_mux_dataout : WIRE;
data_wire[239..0] : WIRE;
result_wire_ext[7..0] : WIRE;
sel_wire[15..0] : WIRE;
BEGIN
l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16];
l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32];
l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48];
l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[72..72] # !(sel_wire[0..0]) & data_wire[64..64];
l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[88..88] # !(sel_wire[0..0]) & data_wire[80..80];
l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[104..104] # !(sel_wire[0..0]) & data_wire[96..96];
l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[120..120] # !(sel_wire[0..0]) & data_wire[112..112];
l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17];
l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33];
l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49];
l1_w1_n4_mux_dataout = sel_wire[0..0] & data_wire[73..73] # !(sel_wire[0..0]) & data_wire[65..65];
l1_w1_n5_mux_dataout = sel_wire[0..0] & data_wire[89..89] # !(sel_wire[0..0]) & data_wire[81..81];
l1_w1_n6_mux_dataout = sel_wire[0..0] & data_wire[105..105] # !(sel_wire[0..0]) & data_wire[97..97];
l1_w1_n7_mux_dataout = sel_wire[0..0] & data_wire[121..121] # !(sel_wire[0..0]) & data_wire[113..113];
l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18];
l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34];
l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50];
l1_w2_n4_mux_dataout = sel_wire[0..0] & data_wire[74..74] # !(sel_wire[0..0]) & data_wire[66..66];
l1_w2_n5_mux_dataout = sel_wire[0..0] & data_wire[90..90] # !(sel_wire[0..0]) & data_wire[82..82];
l1_w2_n6_mux_dataout = sel_wire[0..0] & data_wire[106..106] # !(sel_wire[0..0]) & data_wire[98..98];
l1_w2_n7_mux_dataout = sel_wire[0..0] & data_wire[122..122] # !(sel_wire[0..0]) & data_wire[114..114];
l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19];
l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35];
l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51];
l1_w3_n4_mux_dataout = sel_wire[0..0] & data_wire[75..75] # !(sel_wire[0..0]) & data_wire[67..67];
l1_w3_n5_mux_dataout = sel_wire[0..0] & data_wire[91..91] # !(sel_wire[0..0]) & data_wire[83..83];
l1_w3_n6_mux_dataout = sel_wire[0..0] & data_wire[107..107] # !(sel_wire[0..0]) & data_wire[99..99];
l1_w3_n7_mux_dataout = sel_wire[0..0] & data_wire[123..123] # !(sel_wire[0..0]) & data_wire[115..115];
l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20];
l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36];
l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52];
l1_w4_n4_mux_dataout = sel_wire[0..0] & data_wire[76..76] # !(sel_wire[0..0]) & data_wire[68..68];
l1_w4_n5_mux_dataout = sel_wire[0..0] & data_wire[92..92] # !(sel_wire[0..0]) & data_wire[84..84];
l1_w4_n6_mux_dataout = sel_wire[0..0] & data_wire[108..108] # !(sel_wire[0..0]) & data_wire[100..100];
l1_w4_n7_mux_dataout = sel_wire[0..0] & data_wire[124..124] # !(sel_wire[0..0]) & data_wire[116..116];
l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21];
l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37];
l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53];
l1_w5_n4_mux_dataout = sel_wire[0..0] & data_wire[77..77] # !(sel_wire[0..0]) & data_wire[69..69];
l1_w5_n5_mux_dataout = sel_wire[0..0] & data_wire[93..93] # !(sel_wire[0..0]) & data_wire[85..85];
l1_w5_n6_mux_dataout = sel_wire[0..0] & data_wire[109..109] # !(sel_wire[0..0]) & data_wire[101..101];
l1_w5_n7_mux_dataout = sel_wire[0..0] & data_wire[125..125] # !(sel_wire[0..0]) & data_wire[117..117];
l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22];
l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38];
l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54];
l1_w6_n4_mux_dataout = sel_wire[0..0] & data_wire[78..78] # !(sel_wire[0..0]) & data_wire[70..70];
l1_w6_n5_mux_dataout = sel_wire[0..0] & data_wire[94..94] # !(sel_wire[0..0]) & data_wire[86..86];
l1_w6_n6_mux_dataout = sel_wire[0..0] & data_wire[110..110] # !(sel_wire[0..0]) & data_wire[102..102];
l1_w6_n7_mux_dataout = sel_wire[0..0] & data_wire[126..126] # !(sel_wire[0..0]) & data_wire[118..118];
l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23];
l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39];
l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55];
l1_w7_n4_mux_dataout = sel_wire[0..0] & data_wire[79..79] # !(sel_wire[0..0]) & data_wire[71..71];
l1_w7_n5_mux_dataout = sel_wire[0..0] & data_wire[95..95] # !(sel_wire[0..0]) & data_wire[87..87];
l1_w7_n6_mux_dataout = sel_wire[0..0] & data_wire[111..111] # !(sel_wire[0..0]) & data_wire[103..103];
l1_w7_n7_mux_dataout = sel_wire[0..0] & data_wire[127..127] # !(sel_wire[0..0]) & data_wire[119..119];
l2_w0_n0_mux_dataout = sel_wire[5..5] & data_wire[129..129] # !(sel_wire[5..5]) & data_wire[128..128];
l2_w0_n1_mux_dataout = sel_wire[5..5] & data_wire[131..131] # !(sel_wire[5..5]) & data_wire[130..130];
l2_w0_n2_mux_dataout = sel_wire[5..5] & data_wire[133..133] # !(sel_wire[5..5]) & data_wire[132..132];
l2_w0_n3_mux_dataout = sel_wire[5..5] & data_wire[135..135] # !(sel_wire[5..5]) & data_wire[134..134];
l2_w1_n0_mux_dataout = sel_wire[5..5] & data_wire[137..137] # !(sel_wire[5..5]) & data_wire[136..136];
l2_w1_n1_mux_dataout = sel_wire[5..5] & data_wire[139..139] # !(sel_wire[5..5]) & data_wire[138..138];
l2_w1_n2_mux_dataout = sel_wire[5..5] & data_wire[141..141] # !(sel_wire[5..5]) & data_wire[140..140];
l2_w1_n3_mux_dataout = sel_wire[5..5] & data_wire[143..143] # !(sel_wire[5..5]) & data_wire[142..142];
l2_w2_n0_mux_dataout = sel_wire[5..5] & data_wire[145..145] # !(sel_wire[5..5]) & data_wire[144..144];
l2_w2_n1_mux_dataout = sel_wire[5..5] & data_wire[147..147] # !(sel_wire[5..5]) & data_wire[146..146];
l2_w2_n2_mux_dataout = sel_wire[5..5] & data_wire[149..149] # !(sel_wire[5..5]) & data_wire[148..148];
l2_w2_n3_mux_dataout = sel_wire[5..5] & data_wire[151..151] # !(sel_wire[5..5]) & data_wire[150..150];
l2_w3_n0_mux_dataout = sel_wire[5..5] & data_wire[153..153] # !(sel_wire[5..5]) & data_wire[152..152];
l2_w3_n1_mux_dataout = sel_wire[5..5] & data_wire[155..155] # !(sel_wire[5..5]) & data_wire[154..154];
l2_w3_n2_mux_dataout = sel_wire[5..5] & data_wire[157..157] # !(sel_wire[5..5]) & data_wire[156..156];
l2_w3_n3_mux_dataout = sel_wire[5..5] & data_wire[159..159] # !(sel_wire[5..5]) & data_wire[158..158];
l2_w4_n0_mux_dataout = sel_wire[5..5] & data_wire[161..161] # !(sel_wire[5..5]) & data_wire[160..160];
l2_w4_n1_mux_dataout = sel_wire[5..5] & data_wire[163..163] # !(sel_wire[5..5]) & data_wire[162..162];
l2_w4_n2_mux_dataout = sel_wire[5..5] & data_wire[165..165] # !(sel_wire[5..5]) & data_wire[164..164];
l2_w4_n3_mux_dataout = sel_wire[5..5] & data_wire[167..167] # !(sel_wire[5..5]) & data_wire[166..166];
l2_w5_n0_mux_dataout = sel_wire[5..5] & data_wire[169..169] # !(sel_wire[5..5]) & data_wire[168..168];
l2_w5_n1_mux_dataout = sel_wire[5..5] & data_wire[171..171] # !(sel_wire[5..5]) & data_wire[170..170];
l2_w5_n2_mux_dataout = sel_wire[5..5] & data_wire[173..173] # !(sel_wire[5..5]) & data_wire[172..172];
l2_w5_n3_mux_dataout = sel_wire[5..5] & data_wire[175..175] # !(sel_wire[5..5]) & data_wire[174..174];
l2_w6_n0_mux_dataout = sel_wire[5..5] & data_wire[177..177] # !(sel_wire[5..5]) & data_wire[176..176];
l2_w6_n1_mux_dataout = sel_wire[5..5] & data_wire[179..179] # !(sel_wire[5..5]) & data_wire[178..178];
l2_w6_n2_mux_dataout = sel_wire[5..5] & data_wire[181..181] # !(sel_wire[5..5]) & data_wire[180..180];
l2_w6_n3_mux_dataout = sel_wire[5..5] & data_wire[183..183] # !(sel_wire[5..5]) & data_wire[182..182];
l2_w7_n0_mux_dataout = sel_wire[5..5] & data_wire[185..185] # !(sel_wire[5..5]) & data_wire[184..184];
l2_w7_n1_mux_dataout = sel_wire[5..5] & data_wire[187..187] # !(sel_wire[5..5]) & data_wire[186..186];
l2_w7_n2_mux_dataout = sel_wire[5..5] & data_wire[189..189] # !(sel_wire[5..5]) & data_wire[188..188];
l2_w7_n3_mux_dataout = sel_wire[5..5] & data_wire[191..191] # !(sel_wire[5..5]) & data_wire[190..190];
l3_w0_n0_mux_dataout = sel_wire[10..10] & data_wire[193..193] # !(sel_wire[10..10]) & data_wire[192..192];
l3_w0_n1_mux_dataout = sel_wire[10..10] & data_wire[195..195] # !(sel_wire[10..10]) & data_wire[194..194];
l3_w1_n0_mux_dataout = sel_wire[10..10] & data_wire[197..197] # !(sel_wire[10..10]) & data_wire[196..196];
l3_w1_n1_mux_dataout = sel_wire[10..10] & data_wire[199..199] # !(sel_wire[10..10]) & data_wire[198..198];
l3_w2_n0_mux_dataout = sel_wire[10..10] & data_wire[201..201] # !(sel_wire[10..10]) & data_wire[200..200];
l3_w2_n1_mux_dataout = sel_wire[10..10] & data_wire[203..203] # !(sel_wire[10..10]) & data_wire[202..202];
l3_w3_n0_mux_dataout = sel_wire[10..10] & data_wire[205..205] # !(sel_wire[10..10]) & data_wire[204..204];
l3_w3_n1_mux_dataout = sel_wire[10..10] & data_wire[207..207] # !(sel_wire[10..10]) & data_wire[206..206];
l3_w4_n0_mux_dataout = sel_wire[10..10] & data_wire[209..209] # !(sel_wire[10..10]) & data_wire[208..208];
l3_w4_n1_mux_dataout = sel_wire[10..10] & data_wire[211..211] # !(sel_wire[10..10]) & data_wire[210..210];
l3_w5_n0_mux_dataout = sel_wire[10..10] & data_wire[213..213] # !(sel_wire[10..10]) & data_wire[212..212];
l3_w5_n1_mux_dataout = sel_wire[10..10] & data_wire[215..215] # !(sel_wire[10..10]) & data_wire[214..214];
l3_w6_n0_mux_dataout = sel_wire[10..10] & data_wire[217..217] # !(sel_wire[10..10]) & data_wire[216..216];
l3_w6_n1_mux_dataout = sel_wire[10..10] & data_wire[219..219] # !(sel_wire[10..10]) & data_wire[218..218];
l3_w7_n0_mux_dataout = sel_wire[10..10] & data_wire[221..221] # !(sel_wire[10..10]) & data_wire[220..220];
l3_w7_n1_mux_dataout = sel_wire[10..10] & data_wire[223..223] # !(sel_wire[10..10]) & data_wire[222..222];
l4_w0_n0_mux_dataout = sel_wire[15..15] & data_wire[225..225] # !(sel_wire[15..15]) & data_wire[224..224];
l4_w1_n0_mux_dataout = sel_wire[15..15] & data_wire[227..227] # !(sel_wire[15..15]) & data_wire[226..226];
l4_w2_n0_mux_dataout = sel_wire[15..15] & data_wire[229..229] # !(sel_wire[15..15]) & data_wire[228..228];
l4_w3_n0_mux_dataout = sel_wire[15..15] & data_wire[231..231] # !(sel_wire[15..15]) & data_wire[230..230];
l4_w4_n0_mux_dataout = sel_wire[15..15] & data_wire[233..233] # !(sel_wire[15..15]) & data_wire[232..232];
l4_w5_n0_mux_dataout = sel_wire[15..15] & data_wire[235..235] # !(sel_wire[15..15]) & data_wire[234..234];
l4_w6_n0_mux_dataout = sel_wire[15..15] & data_wire[237..237] # !(sel_wire[15..15]) & data_wire[236..236];
l4_w7_n0_mux_dataout = sel_wire[15..15] & data_wire[239..239] # !(sel_wire[15..15]) & data_wire[238..238];
data_wire[] = ( l3_w7_n1_mux_dataout, l3_w7_n0_mux_dataout, l3_w6_n1_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n1_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n1_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n1_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n1_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n1_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w7_n3_mux_dataout, l2_w7_n2_mux_dataout, l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n3_mux_dataout, l2_w6_n2_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n3_mux_dataout, l2_w5_n2_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n3_mux_dataout, l2_w4_n2_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n3_mux_dataout, l2_w3_n2_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n3_mux_dataout, l2_w2_n2_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n3_mux_dataout, l2_w1_n2_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n7_mux_dataout, l1_w7_n6_mux_dataout, l1_w7_n5_mux_dataout, l1_w7_n4_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n7_mux_dataout, l1_w6_n6_mux_dataout, l1_w6_n5_mux_dataout, l1_w6_n4_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n7_mux_dataout, l1_w5_n6_mux_dataout, l1_w5_n5_mux_dataout, l1_w5_n4_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n7_mux_dataout, l1_w4_n6_mux_dataout, l1_w4_n5_mux_dataout, l1_w4_n4_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n7_mux_dataout, l1_w3_n6_mux_dataout, l1_w3_n5_mux_dataout, l1_w3_n4_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n7_mux_dataout, l1_w2_n6_mux_dataout, l1_w2_n5_mux_dataout, l1_w2_n4_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n7_mux_dataout, l1_w1_n6_mux_dataout, l1_w1_n5_mux_dataout, l1_w1_n4_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
result[] = result_wire_ext[];
result_wire_ext[] = ( l4_w7_n0_mux_dataout, l4_w6_n0_mux_dataout, l4_w5_n0_mux_dataout, l4_w4_n0_mux_dataout, l4_w3_n0_mux_dataout, l4_w2_n0_mux_dataout, l4_w1_n0_mux_dataout, l4_w0_n0_mux_dataout);
sel_wire[] = ( sel[3..3], B"0000", sel[2..2], B"0000", sel[1..1], B"0000", sel[0..0]);
END;
--VALID FILE

1048
proj_quartus/db/mux_ihb.tdf Normal file
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56
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 3
SUBDESIGN mux_lfb
(
data[15..0] : input;
result[7..0] : output;
sel[0..0] : input;
)
VARIABLE
l1_w0_n0_mux_dataout : WIRE;
l1_w1_n0_mux_dataout : WIRE;
l1_w2_n0_mux_dataout : WIRE;
l1_w3_n0_mux_dataout : WIRE;
l1_w4_n0_mux_dataout : WIRE;
l1_w5_n0_mux_dataout : WIRE;
l1_w6_n0_mux_dataout : WIRE;
l1_w7_n0_mux_dataout : WIRE;
data_wire[15..0] : WIRE;
result_wire_ext[7..0] : WIRE;
sel_wire[0..0] : WIRE;
BEGIN
l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
data_wire[] = ( data[]);
result[] = result_wire_ext[];
result_wire_ext[] = ( l1_w7_n0_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n0_mux_dataout);
sel_wire[] = ( sel[0..0]);
END;
--VALID FILE

88
proj_quartus/db/mux_ofb.tdf Normal file
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 8
SUBDESIGN mux_ofb
(
data[31..0] : input;
result[7..0] : output;
sel[1..0] : input;
)
VARIABLE
l1_w0_n0_mux_dataout : WIRE;
l1_w0_n1_mux_dataout : WIRE;
l1_w1_n0_mux_dataout : WIRE;
l1_w1_n1_mux_dataout : WIRE;
l1_w2_n0_mux_dataout : WIRE;
l1_w2_n1_mux_dataout : WIRE;
l1_w3_n0_mux_dataout : WIRE;
l1_w3_n1_mux_dataout : WIRE;
l1_w4_n0_mux_dataout : WIRE;
l1_w4_n1_mux_dataout : WIRE;
l1_w5_n0_mux_dataout : WIRE;
l1_w5_n1_mux_dataout : WIRE;
l1_w6_n0_mux_dataout : WIRE;
l1_w6_n1_mux_dataout : WIRE;
l1_w7_n0_mux_dataout : WIRE;
l1_w7_n1_mux_dataout : WIRE;
l2_w0_n0_mux_dataout : WIRE;
l2_w1_n0_mux_dataout : WIRE;
l2_w2_n0_mux_dataout : WIRE;
l2_w3_n0_mux_dataout : WIRE;
l2_w4_n0_mux_dataout : WIRE;
l2_w5_n0_mux_dataout : WIRE;
l2_w6_n0_mux_dataout : WIRE;
l2_w7_n0_mux_dataout : WIRE;
data_wire[47..0] : WIRE;
result_wire_ext[7..0] : WIRE;
sel_wire[3..0] : WIRE;
BEGIN
l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16];
l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17];
l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18];
l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19];
l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20];
l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21];
l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22];
l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23];
l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[33..33] # !(sel_wire[3..3]) & data_wire[32..32];
l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[35..35] # !(sel_wire[3..3]) & data_wire[34..34];
l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[37..37] # !(sel_wire[3..3]) & data_wire[36..36];
l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[39..39] # !(sel_wire[3..3]) & data_wire[38..38];
l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[41..41] # !(sel_wire[3..3]) & data_wire[40..40];
l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[43..43] # !(sel_wire[3..3]) & data_wire[42..42];
l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[45..45] # !(sel_wire[3..3]) & data_wire[44..44];
l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[47..47] # !(sel_wire[3..3]) & data_wire[46..46];
data_wire[] = ( l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
result[] = result_wire_ext[];
result_wire_ext[] = ( l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout);
sel_wire[] = ( sel[1..1], B"00", sel[0..0]);
END;
--VALID FILE

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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=8 LPM_WIDTH=8 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END
-- Copyright (C) 2022 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--synthesis_resources = lut 19
SUBDESIGN mux_tfb
(
data[63..0] : input;
result[7..0] : output;
sel[2..0] : input;
)
VARIABLE
l1_w0_n0_mux_dataout : WIRE;
l1_w0_n1_mux_dataout : WIRE;
l1_w0_n2_mux_dataout : WIRE;
l1_w0_n3_mux_dataout : WIRE;
l1_w1_n0_mux_dataout : WIRE;
l1_w1_n1_mux_dataout : WIRE;
l1_w1_n2_mux_dataout : WIRE;
l1_w1_n3_mux_dataout : WIRE;
l1_w2_n0_mux_dataout : WIRE;
l1_w2_n1_mux_dataout : WIRE;
l1_w2_n2_mux_dataout : WIRE;
l1_w2_n3_mux_dataout : WIRE;
l1_w3_n0_mux_dataout : WIRE;
l1_w3_n1_mux_dataout : WIRE;
l1_w3_n2_mux_dataout : WIRE;
l1_w3_n3_mux_dataout : WIRE;
l1_w4_n0_mux_dataout : WIRE;
l1_w4_n1_mux_dataout : WIRE;
l1_w4_n2_mux_dataout : WIRE;
l1_w4_n3_mux_dataout : WIRE;
l1_w5_n0_mux_dataout : WIRE;
l1_w5_n1_mux_dataout : WIRE;
l1_w5_n2_mux_dataout : WIRE;
l1_w5_n3_mux_dataout : WIRE;
l1_w6_n0_mux_dataout : WIRE;
l1_w6_n1_mux_dataout : WIRE;
l1_w6_n2_mux_dataout : WIRE;
l1_w6_n3_mux_dataout : WIRE;
l1_w7_n0_mux_dataout : WIRE;
l1_w7_n1_mux_dataout : WIRE;
l1_w7_n2_mux_dataout : WIRE;
l1_w7_n3_mux_dataout : WIRE;
l2_w0_n0_mux_dataout : WIRE;
l2_w0_n1_mux_dataout : WIRE;
l2_w1_n0_mux_dataout : WIRE;
l2_w1_n1_mux_dataout : WIRE;
l2_w2_n0_mux_dataout : WIRE;
l2_w2_n1_mux_dataout : WIRE;
l2_w3_n0_mux_dataout : WIRE;
l2_w3_n1_mux_dataout : WIRE;
l2_w4_n0_mux_dataout : WIRE;
l2_w4_n1_mux_dataout : WIRE;
l2_w5_n0_mux_dataout : WIRE;
l2_w5_n1_mux_dataout : WIRE;
l2_w6_n0_mux_dataout : WIRE;
l2_w6_n1_mux_dataout : WIRE;
l2_w7_n0_mux_dataout : WIRE;
l2_w7_n1_mux_dataout : WIRE;
l3_w0_n0_mux_dataout : WIRE;
l3_w1_n0_mux_dataout : WIRE;
l3_w2_n0_mux_dataout : WIRE;
l3_w3_n0_mux_dataout : WIRE;
l3_w4_n0_mux_dataout : WIRE;
l3_w5_n0_mux_dataout : WIRE;
l3_w6_n0_mux_dataout : WIRE;
l3_w7_n0_mux_dataout : WIRE;
data_wire[111..0] : WIRE;
result_wire_ext[7..0] : WIRE;
sel_wire[8..0] : WIRE;
BEGIN
l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16];
l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32];
l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48];
l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17];
l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33];
l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49];
l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18];
l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34];
l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50];
l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19];
l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35];
l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51];
l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20];
l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36];
l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52];
l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21];
l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37];
l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53];
l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22];
l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38];
l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54];
l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23];
l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39];
l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55];
l2_w0_n0_mux_dataout = sel_wire[4..4] & data_wire[65..65] # !(sel_wire[4..4]) & data_wire[64..64];
l2_w0_n1_mux_dataout = sel_wire[4..4] & data_wire[67..67] # !(sel_wire[4..4]) & data_wire[66..66];
l2_w1_n0_mux_dataout = sel_wire[4..4] & data_wire[69..69] # !(sel_wire[4..4]) & data_wire[68..68];
l2_w1_n1_mux_dataout = sel_wire[4..4] & data_wire[71..71] # !(sel_wire[4..4]) & data_wire[70..70];
l2_w2_n0_mux_dataout = sel_wire[4..4] & data_wire[73..73] # !(sel_wire[4..4]) & data_wire[72..72];
l2_w2_n1_mux_dataout = sel_wire[4..4] & data_wire[75..75] # !(sel_wire[4..4]) & data_wire[74..74];
l2_w3_n0_mux_dataout = sel_wire[4..4] & data_wire[77..77] # !(sel_wire[4..4]) & data_wire[76..76];
l2_w3_n1_mux_dataout = sel_wire[4..4] & data_wire[79..79] # !(sel_wire[4..4]) & data_wire[78..78];
l2_w4_n0_mux_dataout = sel_wire[4..4] & data_wire[81..81] # !(sel_wire[4..4]) & data_wire[80..80];
l2_w4_n1_mux_dataout = sel_wire[4..4] & data_wire[83..83] # !(sel_wire[4..4]) & data_wire[82..82];
l2_w5_n0_mux_dataout = sel_wire[4..4] & data_wire[85..85] # !(sel_wire[4..4]) & data_wire[84..84];
l2_w5_n1_mux_dataout = sel_wire[4..4] & data_wire[87..87] # !(sel_wire[4..4]) & data_wire[86..86];
l2_w6_n0_mux_dataout = sel_wire[4..4] & data_wire[89..89] # !(sel_wire[4..4]) & data_wire[88..88];
l2_w6_n1_mux_dataout = sel_wire[4..4] & data_wire[91..91] # !(sel_wire[4..4]) & data_wire[90..90];
l2_w7_n0_mux_dataout = sel_wire[4..4] & data_wire[93..93] # !(sel_wire[4..4]) & data_wire[92..92];
l2_w7_n1_mux_dataout = sel_wire[4..4] & data_wire[95..95] # !(sel_wire[4..4]) & data_wire[94..94];
l3_w0_n0_mux_dataout = sel_wire[8..8] & data_wire[97..97] # !(sel_wire[8..8]) & data_wire[96..96];
l3_w1_n0_mux_dataout = sel_wire[8..8] & data_wire[99..99] # !(sel_wire[8..8]) & data_wire[98..98];
l3_w2_n0_mux_dataout = sel_wire[8..8] & data_wire[101..101] # !(sel_wire[8..8]) & data_wire[100..100];
l3_w3_n0_mux_dataout = sel_wire[8..8] & data_wire[103..103] # !(sel_wire[8..8]) & data_wire[102..102];
l3_w4_n0_mux_dataout = sel_wire[8..8] & data_wire[105..105] # !(sel_wire[8..8]) & data_wire[104..104];
l3_w5_n0_mux_dataout = sel_wire[8..8] & data_wire[107..107] # !(sel_wire[8..8]) & data_wire[106..106];
l3_w6_n0_mux_dataout = sel_wire[8..8] & data_wire[109..109] # !(sel_wire[8..8]) & data_wire[108..108];
l3_w7_n0_mux_dataout = sel_wire[8..8] & data_wire[111..111] # !(sel_wire[8..8]) & data_wire[110..110];
data_wire[] = ( l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
result[] = result_wire_ext[];
result_wire_ext[] = ( l3_w7_n0_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n0_mux_dataout);
sel_wire[] = ( sel[2..2], B"000", sel[1..1], B"000", sel[0..0]);
END;
--VALID FILE

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