From 99d93a353f6289ee2bbf8dc6472ab7615b190a5a Mon Sep 17 00:00:00 2001 From: higepi Date: Thu, 9 Mar 2023 14:56:26 +0100 Subject: [PATCH] memory --- Rapport/Bandwidth/memory_cycles.png | Bin 0 -> 30577 bytes Rapport/Bandwidth/plot.py | 23 + bandwidth_test/debug.txt | 26485 ++++++++++ bandwidth_test/main.bin | Bin 4584 -> 4760 bytes bandwidth_test/main.c.o | Bin 15240 -> 19296 bytes bandwidth_test/main.elf | Bin 68460 -> 69416 bytes bandwidth_test/{main.c => mem.c} | 21 +- bandwidth_test/neorv32_exe.bin | Bin 4596 -> 4772 bytes neorv32/rtl/core/neorv32_top.vhd.bak | 1740 + proj_quartus/.qsys_edit/preferences.xml | 5 +- proj_quartus/db/altsyncram_2aq1.tdf | 532 + proj_quartus/db/altsyncram_6gq1.tdf | 59460 ++++++++++++++++++++++ proj_quartus/db/altsyncram_caq1.tdf | 996 + proj_quartus/db/altsyncram_daq1.tdf | 1924 + proj_quartus/db/altsyncram_ocq1.tdf | 3780 ++ proj_quartus/db/altsyncram_qdq1.tdf | 14916 ++++++ proj_quartus/db/decode_2na.tdf | 188 + proj_quartus/db/decode_5la.tdf | 36 + proj_quartus/db/decode_8la.tdf | 50 + proj_quartus/db/decode_dla.tdf | 58 + proj_quartus/db/decode_noa.tdf | 636 + proj_quartus/db/decode_tma.tdf | 80 + proj_quartus/db/mux_7jb.tdf | 4120 ++ proj_quartus/db/mux_dhb.tdf | 280 + proj_quartus/db/mux_ihb.tdf | 1048 + proj_quartus/db/mux_lfb.tdf | 56 + proj_quartus/db/mux_ofb.tdf | 88 + proj_quartus/db/mux_tfb.tdf | 152 + proj_quartus/db/test.(35).cnf.cdb | Bin 0 -> 7428 bytes proj_quartus/db/test.(35).cnf.hdb | Bin 0 -> 3643 bytes proj_quartus/db/test.(36).cnf.cdb | Bin 0 -> 28484 bytes proj_quartus/db/test.(36).cnf.hdb | Bin 0 -> 8600 bytes proj_quartus/db/test.(38).cnf.cdb | Bin 0 -> 8126 bytes proj_quartus/db/test.(38).cnf.hdb | Bin 0 -> 3355 bytes proj_quartus/db/test.(39).cnf.cdb | Bin 0 -> 3598 bytes proj_quartus/db/test.(39).cnf.hdb | Bin 0 -> 1588 bytes proj_quartus/db/test.(40).cnf.cdb | Bin 0 -> 1963 bytes proj_quartus/db/test.(40).cnf.hdb | Bin 0 -> 832 bytes proj_quartus/db/test.(41).cnf.cdb | Bin 0 -> 10339 bytes proj_quartus/db/test.(41).cnf.hdb | Bin 0 -> 2254 bytes proj_quartus/db/test.(42).cnf.cdb | Bin 0 -> 2766 bytes proj_quartus/db/test.(42).cnf.hdb | Bin 0 -> 1646 bytes proj_quartus/db/test.(43).cnf.cdb | Bin 0 -> 8175 bytes proj_quartus/db/test.(43).cnf.hdb | Bin 0 -> 2955 bytes proj_quartus/db/test.(45).cnf.cdb | Bin 0 -> 7799 bytes proj_quartus/db/test.(45).cnf.hdb | Bin 0 -> 3295 bytes proj_quartus/db/test.(46).cnf.cdb | Bin 0 -> 3526 bytes proj_quartus/db/test.(46).cnf.hdb | Bin 0 -> 1577 bytes proj_quartus/db/test.(47).cnf.cdb | Bin 0 -> 1951 bytes proj_quartus/db/test.(47).cnf.hdb | Bin 0 -> 828 bytes proj_quartus/db/test.(48).cnf.cdb | Bin 0 -> 7163 bytes proj_quartus/db/test.(48).cnf.hdb | Bin 0 -> 992 bytes proj_quartus/db/test.(50).cnf.cdb | Bin 0 -> 7801 bytes proj_quartus/db/test.(50).cnf.hdb | Bin 0 -> 3309 bytes proj_quartus/db/test.(51).cnf.cdb | Bin 0 -> 7874 bytes proj_quartus/db/test.(51).cnf.hdb | Bin 0 -> 3323 bytes proj_quartus/db/test.(52).cnf.cdb | Bin 0 -> 3597 bytes proj_quartus/db/test.(52).cnf.hdb | Bin 0 -> 1577 bytes proj_quartus/db/test.(53).cnf.cdb | Bin 0 -> 1897 bytes proj_quartus/db/test.(53).cnf.hdb | Bin 0 -> 827 bytes proj_quartus/db/test.(54).cnf.cdb | Bin 0 -> 4045 bytes proj_quartus/db/test.(54).cnf.hdb | Bin 0 -> 1189 bytes proj_quartus/db/test.(55).cnf.cdb | Bin 0 -> 896 bytes proj_quartus/db/test.(55).cnf.hdb | Bin 0 -> 560 bytes proj_quartus/db/test.(56).cnf.cdb | Bin 0 -> 1540 bytes proj_quartus/db/test.(56).cnf.hdb | Bin 0 -> 875 bytes proj_quartus/db/test.(57).cnf.cdb | Bin 0 -> 1857 bytes proj_quartus/db/test.(57).cnf.hdb | Bin 0 -> 830 bytes proj_quartus/db/test.(58).cnf.cdb | Bin 0 -> 2681 bytes proj_quartus/db/test.(58).cnf.hdb | Bin 0 -> 917 bytes proj_quartus/db/test.(60).cnf.cdb | Bin 0 -> 7904 bytes proj_quartus/db/test.(60).cnf.hdb | Bin 0 -> 3335 bytes proj_quartus/db/test.(61).cnf.cdb | Bin 0 -> 3540 bytes proj_quartus/db/test.(61).cnf.hdb | Bin 0 -> 1572 bytes proj_quartus/db/test.(62).cnf.cdb | Bin 0 -> 1937 bytes proj_quartus/db/test.(62).cnf.hdb | Bin 0 -> 831 bytes proj_quartus/db/test.(63).cnf.cdb | Bin 0 -> 5164 bytes proj_quartus/db/test.(63).cnf.hdb | Bin 0 -> 1363 bytes proj_quartus/db/test.(64).cnf.cdb | Bin 0 -> 1215 bytes proj_quartus/db/test.(64).cnf.hdb | Bin 0 -> 876 bytes proj_quartus/db/test.(65).cnf.cdb | Bin 0 -> 2833 bytes proj_quartus/db/test.(65).cnf.hdb | Bin 0 -> 1230 bytes proj_quartus/db/test.(67).cnf.cdb | Bin 0 -> 3603 bytes proj_quartus/db/test.(67).cnf.hdb | Bin 0 -> 1592 bytes proj_quartus/db/test.(69).cnf.cdb | Bin 0 -> 8027 bytes proj_quartus/db/test.(69).cnf.hdb | Bin 0 -> 3367 bytes proj_quartus/db/test.(70).cnf.cdb | Bin 0 -> 3605 bytes proj_quartus/db/test.(70).cnf.hdb | Bin 0 -> 1589 bytes proj_quartus/db/test.(71).cnf.cdb | Bin 0 -> 1951 bytes proj_quartus/db/test.(71).cnf.hdb | Bin 0 -> 829 bytes proj_quartus/db/test.(72).cnf.cdb | Bin 0 -> 6967 bytes proj_quartus/db/test.(72).cnf.hdb | Bin 0 -> 1654 bytes proj_quartus/db/test.(73).cnf.cdb | Bin 0 -> 1803 bytes proj_quartus/db/test.(73).cnf.hdb | Bin 0 -> 1109 bytes proj_quartus/db/test.(74).cnf.cdb | Bin 0 -> 4824 bytes proj_quartus/db/test.(74).cnf.hdb | Bin 0 -> 1755 bytes proj_quartus/test.qws | Bin 0 -> 2135 bytes 97 files changed, 116669 insertions(+), 5 deletions(-) create mode 100644 Rapport/Bandwidth/memory_cycles.png create mode 100644 Rapport/Bandwidth/plot.py create mode 100644 bandwidth_test/debug.txt rename bandwidth_test/{main.c => mem.c} (90%) create mode 100644 neorv32/rtl/core/neorv32_top.vhd.bak create mode 100644 proj_quartus/db/altsyncram_2aq1.tdf create mode 100644 proj_quartus/db/altsyncram_6gq1.tdf create mode 100644 proj_quartus/db/altsyncram_caq1.tdf create mode 100644 proj_quartus/db/altsyncram_daq1.tdf create mode 100644 proj_quartus/db/altsyncram_ocq1.tdf create mode 100644 proj_quartus/db/altsyncram_qdq1.tdf create mode 100644 proj_quartus/db/decode_2na.tdf create mode 100644 proj_quartus/db/decode_5la.tdf create mode 100644 proj_quartus/db/decode_8la.tdf create mode 100644 proj_quartus/db/decode_dla.tdf create mode 100644 proj_quartus/db/decode_noa.tdf create mode 100644 proj_quartus/db/decode_tma.tdf create mode 100644 proj_quartus/db/mux_7jb.tdf create mode 100644 proj_quartus/db/mux_dhb.tdf create mode 100644 proj_quartus/db/mux_ihb.tdf create mode 100644 proj_quartus/db/mux_lfb.tdf create mode 100644 proj_quartus/db/mux_ofb.tdf create mode 100644 proj_quartus/db/mux_tfb.tdf create mode 100644 proj_quartus/db/test.(35).cnf.cdb create mode 100644 proj_quartus/db/test.(35).cnf.hdb create mode 100644 proj_quartus/db/test.(36).cnf.cdb create mode 100644 proj_quartus/db/test.(36).cnf.hdb create mode 100644 proj_quartus/db/test.(38).cnf.cdb create mode 100644 proj_quartus/db/test.(38).cnf.hdb create mode 100644 proj_quartus/db/test.(39).cnf.cdb create mode 100644 proj_quartus/db/test.(39).cnf.hdb create mode 100644 proj_quartus/db/test.(40).cnf.cdb create mode 100644 proj_quartus/db/test.(40).cnf.hdb create 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proj_quartus/db/test.(62).cnf.hdb create mode 100644 proj_quartus/db/test.(63).cnf.cdb create mode 100644 proj_quartus/db/test.(63).cnf.hdb create mode 100644 proj_quartus/db/test.(64).cnf.cdb create mode 100644 proj_quartus/db/test.(64).cnf.hdb create mode 100644 proj_quartus/db/test.(65).cnf.cdb create mode 100644 proj_quartus/db/test.(65).cnf.hdb create mode 100644 proj_quartus/db/test.(67).cnf.cdb create mode 100644 proj_quartus/db/test.(67).cnf.hdb create mode 100644 proj_quartus/db/test.(69).cnf.cdb create mode 100644 proj_quartus/db/test.(69).cnf.hdb create mode 100644 proj_quartus/db/test.(70).cnf.cdb create mode 100644 proj_quartus/db/test.(70).cnf.hdb create mode 100644 proj_quartus/db/test.(71).cnf.cdb create mode 100644 proj_quartus/db/test.(71).cnf.hdb create mode 100644 proj_quartus/db/test.(72).cnf.cdb create mode 100644 proj_quartus/db/test.(72).cnf.hdb create mode 100644 proj_quartus/db/test.(73).cnf.cdb create mode 100644 proj_quartus/db/test.(73).cnf.hdb create mode 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z-`O>3V=EIb{`jNSb9itBpZPiukSkb9YAU*YLAX50O$Y<60t1No-gYlkkOW`@@(Llr z1-p*HN@QWvD$Okss#-#uIxRrYB+uvsf(nGSBNQ&$T&g;3l_{0z7BTwQ$(IIV`Sh5Pjnly?01zmiLS1DlL3h@Y|ifJf@#OBjF4 NtTI{6%{O)m{~wli: + 0: 30005073 csrwi mstatus,0 + +00000004 <__crt0_cpu_csr_init>: + 4: 30401073 csrw mie,zero + 8: 00000097 auipc ra,0x0 + c: 13408093 addi ra,ra,308 # 13c <__crt0_trap_handler> + 10: 30509073 csrw mtvec,ra + +00000014 <__crt0_pointer_init>: + 14: 80002117 auipc sp,0x80002 + 18: fe810113 addi sp,sp,-24 # 80001ffc <__crt0_stack_begin+0x0> + 1c: 80001197 auipc gp,0x80001 + 20: 02418193 addi gp,gp,36 # 80001040 <__crt0_stack_begin+0xfffff044> + +00000024 <__crt0_reg_file_init>: + 24: 00000213 li tp,0 + 28: 00000293 li t0,0 + 2c: 00000313 li t1,0 + 30: 00000393 li t2,0 + 34: 00000413 li s0,0 + 38: 00000493 li s1,0 + 3c: 00000813 li a6,0 + 40: 00000893 li a7,0 + 44: 00000913 li s2,0 + 48: 00000993 li s3,0 + 4c: 00000a13 li s4,0 + 50: 00000a93 li s5,0 + 54: 00000b13 li s6,0 + 58: 00000b93 li s7,0 + 5c: 00000c13 li s8,0 + 60: 00000c93 li s9,0 + 64: 00000d13 li s10,0 + 68: 00000d93 li s11,0 + 6c: 00000e13 li t3,0 + 70: 00000e93 li t4,0 + 74: 00000f13 li t5,0 + 78: 00000f93 li t6,0 + +0000007c <__crt0_copy_data>: + 7c: 00002597 auipc a1,0x2 + 80: a5458593 addi a1,a1,-1452 # 1ad0 <__RODATA_END__> + 84: 80000617 auipc a2,0x80000 + 88: f7c60613 addi a2,a2,-132 # 80000000 <__crt0_stack_begin+0xffffe004> + 8c: 80000697 auipc a3,0x80000 + 90: 7b468693 addi a3,a3,1972 # 80000840 <__crt0_stack_begin+0xffffe844> + 94: 00c58e63 beq a1,a2,b0 <__crt0_clear_bss> + +00000098 <__crt0_copy_data_loop>: + 98: 00d65c63 bge a2,a3,b0 <__crt0_clear_bss> + 9c: 0005a703 lw a4,0(a1) + a0: 00e62023 sw a4,0(a2) + a4: 00458593 addi a1,a1,4 + a8: 00460613 addi a2,a2,4 + ac: fedff06f j 98 <__crt0_copy_data_loop> + +000000b0 <__crt0_clear_bss>: + b0: 80000717 auipc a4,0x80000 + b4: 79070713 addi a4,a4,1936 # 80000840 <__crt0_stack_begin+0xffffe844> + b8: 8ac18793 addi a5,gp,-1876 # 800008ec <__BSS_END__> + +000000bc <__crt0_clear_bss_loop>: + bc: 00f75863 bge a4,a5,cc <__crt0_call_constructors> + c0: 00072023 sw zero,0(a4) + c4: 00470713 addi a4,a4,4 + c8: ff5ff06f j bc <__crt0_clear_bss_loop> + +000000cc <__crt0_call_constructors>: + cc: 00001417 auipc s0,0x1 + d0: 65440413 addi s0,s0,1620 # 1720 <__fini_array_end> + d4: 00001497 auipc s1,0x1 + d8: 64c48493 addi s1,s1,1612 # 1720 <__fini_array_end> + +000000dc <__crt0_call_constructors_loop>: + dc: 00945a63 bge s0,s1,f0 <__crt0_call_constructors_loop_end> + e0: 00042083 lw ra,0(s0) + e4: 000080e7 jalr ra + e8: 00440413 addi s0,s0,4 + ec: ff1ff06f j dc <__crt0_call_constructors_loop> + +000000f0 <__crt0_call_constructors_loop_end>: + f0: 00000513 li a0,0 + f4: 00000593 li a1,0 + f8: 090000ef jal ra,188
+ +000000fc <__crt0_main_exit>: + fc: 30401073 csrw mie,zero + 100: 34051073 csrw mscratch,a0 + +00000104 <__crt0_call_destructors>: + 104: 00001417 auipc s0,0x1 + 108: 61c40413 addi s0,s0,1564 # 1720 <__fini_array_end> + 10c: 00001497 auipc s1,0x1 + 110: 61448493 addi s1,s1,1556 # 1720 <__fini_array_end> + +00000114 <__crt0_call_destructors_loop>: + 114: 00945a63 bge s0,s1,128 <__crt0_call_destructors_loop_end> + 118: 00042083 lw ra,0(s0) + 11c: 000080e7 jalr ra + 120: 00440413 addi s0,s0,4 + 124: ff1ff06f j 114 <__crt0_call_destructors_loop> + +00000128 <__crt0_call_destructors_loop_end>: + 128: 00000093 li ra,0 + 12c: 00008463 beqz ra,134 <__crt0_main_aftermath_end> + 130: 000080e7 jalr ra + +00000134 <__crt0_main_aftermath_end>: + 134: 10500073 wfi + 138: 0000006f j 138 <__crt0_main_aftermath_end+0x4> + +0000013c <__crt0_trap_handler>: + 13c: ff810113 addi sp,sp,-8 + 140: 00812023 sw s0,0(sp) + 144: 00912223 sw s1,4(sp) + 148: 34202473 csrr s0,mcause + 14c: 02044663 bltz s0,178 <__crt0_trap_handler_end> + 150: 34102473 csrr s0,mepc + 154: 00041483 lh s1,0(s0) + 158: 0034f493 andi s1,s1,3 + 15c: 00240413 addi s0,s0,2 + 160: 34141073 csrw mepc,s0 + 164: 00300413 li s0,3 + 168: 00941863 bne s0,s1,178 <__crt0_trap_handler_end> + 16c: 34102473 csrr s0,mepc + 170: 00240413 addi s0,s0,2 + 174: 34141073 csrw mepc,s0 + +00000178 <__crt0_trap_handler_end>: + 178: 00012403 lw s0,0(sp) + 17c: 00412483 lw s1,4(sp) + 180: 00810113 addi sp,sp,8 + 184: 30200073 mret + +00000188
: + 188: fe010113 addi sp,sp,-32 + 18c: 00112e23 sw ra,28(sp) + 190: 00812c23 sw s0,24(sp) + 194: 01212823 sw s2,16(sp) + 198: 01412423 sw s4,8(sp) + 19c: 01512223 sw s5,4(sp) + 1a0: 00912a23 sw s1,20(sp) + 1a4: 01312623 sw s3,12(sp) + 1a8: 6c4000ef jal ra,86c + 1ac: 00005537 lui a0,0x5 + 1b0: 00000613 li a2,0 + 1b4: 00000593 li a1,0 + 1b8: b0050513 addi a0,a0,-1280 # 4b00 <__neorv32_ram_size+0x2b00> + 1bc: 0ed000ef jal ra,aa8 + 1c0: 00000513 li a0,0 + 1c4: 700000ef jal ra,8c4 + 1c8: 00001537 lui a0,0x1 + 1cc: 72050513 addi a0,a0,1824 # 1720 <__fini_array_end> + 1d0: 19d000ef jal ra,b6c + 1d4: fe002583 lw a1,-32(zero) # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + 1d8: 00001537 lui a0,0x1 + 1dc: 74450513 addi a0,a0,1860 # 1744 <__fini_array_end+0x24> + 1e0: 1e5000ef jal ra,bc4 + 1e4: 00040537 lui a0,0x40 + 1e8: 46b000ef jal ra,e52 + 1ec: 00050913 mv s2,a0 + 1f0: 00000413 li s0,0 + 1f4: 00001ab7 lui s5,0x1 + 1f8: 00010a37 lui s4,0x10 + 1fc: 09c000ef jal ra,298 + 200: 00050493 mv s1,a0 + 204: 00a00993 li s3,10 + 208: 00090593 mv a1,s2 + 20c: 00040513 mv a0,s0 + 210: fff98993 addi s3,s3,-1 + 214: 064000ef jal ra,278 + 218: fe0998e3 bnez s3,208 + 21c: 07c000ef jal ra,298 + 220: 00a00593 li a1,10 + 224: 40950533 sub a0,a0,s1 + 228: 3b5000ef jal ra,ddc <__hidden___udivsi3> + 22c: 00050613 mv a2,a0 + 230: 00040593 mv a1,s0 + 234: 758a8513 addi a0,s5,1880 # 1758 <__fini_array_end+0x38> + 238: 04040413 addi s0,s0,64 + 23c: 189000ef jal ra,bc4 + 240: fb441ee3 bne s0,s4,1fc + 244: 00001537 lui a0,0x1 + 248: 78050513 addi a0,a0,1920 # 1780 <__fini_array_end+0x60> + 24c: 121000ef jal ra,b6c + 250: 01c12083 lw ra,28(sp) + 254: 01812403 lw s0,24(sp) + 258: 01412483 lw s1,20(sp) + 25c: 01012903 lw s2,16(sp) + 260: 00c12983 lw s3,12(sp) + 264: 00812a03 lw s4,8(sp) + 268: 00412a83 lw s5,4(sp) + 26c: 00000513 li a0,0 + 270: 02010113 addi sp,sp,32 + 274: 00008067 ret + +00000278 : + 278: 00000793 li a5,0 + 27c: 00a79463 bne a5,a0,284 + 280: 00008067 ret + 284: 00279713 slli a4,a5,0x2 + 288: 00e58733 add a4,a1,a4 + 28c: 00a72023 sw a0,0(a4) + 290: 00178793 addi a5,a5,1 + 294: fe9ff06f j 27c + +00000298 : + 298: f9402583 lw a1,-108(zero) # ffffff94 <__crt0_stack_begin+0x7fffdf98> + 29c: f9002503 lw a0,-112(zero) # ffffff90 <__crt0_stack_begin+0x7fffdf94> + 2a0: f9402783 lw a5,-108(zero) # ffffff94 <__crt0_stack_begin+0x7fffdf98> + 2a4: fef59ae3 bne a1,a5,298 + 2a8: 00008067 ret + +000002ac <__neorv32_rte_core>: + 2ac: fb010113 addi sp,sp,-80 + 2b0: 04112623 sw ra,76(sp) + 2b4: 04512423 sw t0,72(sp) + 2b8: 04612223 sw t1,68(sp) + 2bc: 04712023 sw t2,64(sp) + 2c0: 02812e23 sw s0,60(sp) + 2c4: 02a12c23 sw a0,56(sp) + 2c8: 02b12a23 sw a1,52(sp) + 2cc: 02c12823 sw a2,48(sp) + 2d0: 02d12623 sw a3,44(sp) + 2d4: 02e12423 sw a4,40(sp) + 2d8: 02f12223 sw a5,36(sp) + 2dc: 03012023 sw a6,32(sp) + 2e0: 01112e23 sw a7,28(sp) + 2e4: 01c12c23 sw t3,24(sp) + 2e8: 01d12a23 sw t4,20(sp) + 2ec: 01e12823 sw t5,16(sp) + 2f0: 01f12623 sw t6,12(sp) + 2f4: 34202473 csrr s0,mcause + 2f8: 00b00793 li a5,11 + 2fc: 0287ea63 bltu a5,s0,330 <__neorv32_rte_core+0x84> + 300: 00001737 lui a4,0x1 + 304: 00241793 slli a5,s0,0x2 + 308: 78870713 addi a4,a4,1928 # 1788 <__fini_array_end+0x68> + 30c: 00e787b3 add a5,a5,a4 + 310: 0007a783 lw a5,0(a5) + 314: 00078067 jr a5 + 318: 00001737 lui a4,0x1 + 31c: 00279793 slli a5,a5,0x2 + 320: 7b870713 addi a4,a4,1976 # 17b8 <__fini_array_end+0x98> + 324: 00e787b3 add a5,a5,a4 + 328: 0007a783 lw a5,0(a5) + 32c: 00078067 jr a5 + 330: 800007b7 lui a5,0x80000 + 334: ffd7c793 xori a5,a5,-3 + 338: 00f407b3 add a5,s0,a5 + 33c: 01c00713 li a4,28 + 340: fcf77ce3 bgeu a4,a5,318 <__neorv32_rte_core+0x6c> + 344: 220000ef jal ra,564 <__neorv32_rte_debug_handler> + 348: 00045a63 bgez s0,35c <__neorv32_rte_core+0xb0> + 34c: 0c00006f j 40c <__neorv32_rte_core+0x160> + 350: 800017b7 lui a5,0x80001 + 354: 8507a783 lw a5,-1968(a5) # 80000850 <__crt0_stack_begin+0xffffe854> + 358: 000780e7 jalr a5 + 35c: 34102773 csrr a4,mepc + 360: 00075783 lhu a5,0(a4) + 364: 01079793 slli a5,a5,0x10 + 368: 0107d793 srli a5,a5,0x10 + 36c: 00470613 addi a2,a4,4 + 370: 301026f3 csrr a3,misa + 374: 0046f693 andi a3,a3,4 + 378: 00068a63 beqz a3,38c <__neorv32_rte_core+0xe0> + 37c: 0037f793 andi a5,a5,3 + 380: 00300693 li a3,3 + 384: 00d78463 beq a5,a3,38c <__neorv32_rte_core+0xe0> + 388: 00270613 addi a2,a4,2 + 38c: 34161073 csrw mepc,a2 + 390: 07c0006f j 40c <__neorv32_rte_core+0x160> + 394: 800017b7 lui a5,0x80001 + 398: 8547a783 lw a5,-1964(a5) # 80000854 <__crt0_stack_begin+0xffffe858> + 39c: fbdff06f j 358 <__neorv32_rte_core+0xac> + 3a0: 800017b7 lui a5,0x80001 + 3a4: 8587a783 lw a5,-1960(a5) # 80000858 <__crt0_stack_begin+0xffffe85c> + 3a8: fb1ff06f j 358 <__neorv32_rte_core+0xac> + 3ac: 800017b7 lui a5,0x80001 + 3b0: 85c7a783 lw a5,-1956(a5) # 8000085c <__crt0_stack_begin+0xffffe860> + 3b4: fa5ff06f j 358 <__neorv32_rte_core+0xac> + 3b8: 800017b7 lui a5,0x80001 + 3bc: 8607a783 lw a5,-1952(a5) # 80000860 <__crt0_stack_begin+0xffffe864> + 3c0: f99ff06f j 358 <__neorv32_rte_core+0xac> + 3c4: 800017b7 lui a5,0x80001 + 3c8: 8647a783 lw a5,-1948(a5) # 80000864 <__crt0_stack_begin+0xffffe868> + 3cc: f8dff06f j 358 <__neorv32_rte_core+0xac> + 3d0: 800017b7 lui a5,0x80001 + 3d4: 8687a783 lw a5,-1944(a5) # 80000868 <__crt0_stack_begin+0xffffe86c> + 3d8: f81ff06f j 358 <__neorv32_rte_core+0xac> + 3dc: 800017b7 lui a5,0x80001 + 3e0: 86c7a783 lw a5,-1940(a5) # 8000086c <__crt0_stack_begin+0xffffe870> + 3e4: f75ff06f j 358 <__neorv32_rte_core+0xac> + 3e8: 800017b7 lui a5,0x80001 + 3ec: 8707a783 lw a5,-1936(a5) # 80000870 <__crt0_stack_begin+0xffffe874> + 3f0: f69ff06f j 358 <__neorv32_rte_core+0xac> + 3f4: 800017b7 lui a5,0x80001 + 3f8: 8747a783 lw a5,-1932(a5) # 80000874 <__crt0_stack_begin+0xffffe878> + 3fc: f5dff06f j 358 <__neorv32_rte_core+0xac> + 400: 800017b7 lui a5,0x80001 + 404: 8787a783 lw a5,-1928(a5) # 80000878 <__crt0_stack_begin+0xffffe87c> + 408: 000780e7 jalr a5 + 40c: 03c12403 lw s0,60(sp) + 410: 04c12083 lw ra,76(sp) + 414: 04812283 lw t0,72(sp) + 418: 04412303 lw t1,68(sp) + 41c: 04012383 lw t2,64(sp) + 420: 03812503 lw a0,56(sp) + 424: 03412583 lw a1,52(sp) + 428: 03012603 lw a2,48(sp) + 42c: 02c12683 lw a3,44(sp) + 430: 02812703 lw a4,40(sp) + 434: 02412783 lw a5,36(sp) + 438: 02012803 lw a6,32(sp) + 43c: 01c12883 lw a7,28(sp) + 440: 01812e03 lw t3,24(sp) + 444: 01412e83 lw t4,20(sp) + 448: 01012f03 lw t5,16(sp) + 44c: 00c12f83 lw t6,12(sp) + 450: 05010113 addi sp,sp,80 + 454: 30200073 mret + 458: 800017b7 lui a5,0x80001 + 45c: 87c7a783 lw a5,-1924(a5) # 8000087c <__crt0_stack_begin+0xffffe880> + 460: fa9ff06f j 408 <__neorv32_rte_core+0x15c> + 464: 800017b7 lui a5,0x80001 + 468: 8807a783 lw a5,-1920(a5) # 80000880 <__crt0_stack_begin+0xffffe884> + 46c: f9dff06f j 408 <__neorv32_rte_core+0x15c> + 470: 800017b7 lui a5,0x80001 + 474: 8847a783 lw a5,-1916(a5) # 80000884 <__crt0_stack_begin+0xffffe888> + 478: f91ff06f j 408 <__neorv32_rte_core+0x15c> + 47c: 8481a783 lw a5,-1976(gp) # 80000888 <__neorv32_rte_vector_lut+0x38> + 480: f89ff06f j 408 <__neorv32_rte_core+0x15c> + 484: 84c1a783 lw a5,-1972(gp) # 8000088c <__neorv32_rte_vector_lut+0x3c> + 488: f81ff06f j 408 <__neorv32_rte_core+0x15c> + 48c: 8501a783 lw a5,-1968(gp) # 80000890 <__neorv32_rte_vector_lut+0x40> + 490: f79ff06f j 408 <__neorv32_rte_core+0x15c> + 494: 8541a783 lw a5,-1964(gp) # 80000894 <__neorv32_rte_vector_lut+0x44> + 498: f71ff06f j 408 <__neorv32_rte_core+0x15c> + 49c: 8581a783 lw a5,-1960(gp) # 80000898 <__neorv32_rte_vector_lut+0x48> + 4a0: f69ff06f j 408 <__neorv32_rte_core+0x15c> + 4a4: 85c1a783 lw a5,-1956(gp) # 8000089c <__neorv32_rte_vector_lut+0x4c> + 4a8: f61ff06f j 408 <__neorv32_rte_core+0x15c> + 4ac: 8601a783 lw a5,-1952(gp) # 800008a0 <__neorv32_rte_vector_lut+0x50> + 4b0: f59ff06f j 408 <__neorv32_rte_core+0x15c> + 4b4: 8641a783 lw a5,-1948(gp) # 800008a4 <__neorv32_rte_vector_lut+0x54> + 4b8: f51ff06f j 408 <__neorv32_rte_core+0x15c> + 4bc: 8681a783 lw a5,-1944(gp) # 800008a8 <__neorv32_rte_vector_lut+0x58> + 4c0: f49ff06f j 408 <__neorv32_rte_core+0x15c> + 4c4: 86c1a783 lw a5,-1940(gp) # 800008ac <__neorv32_rte_vector_lut+0x5c> + 4c8: f41ff06f j 408 <__neorv32_rte_core+0x15c> + 4cc: 8701a783 lw a5,-1936(gp) # 800008b0 <__neorv32_rte_vector_lut+0x60> + 4d0: f39ff06f j 408 <__neorv32_rte_core+0x15c> + 4d4: 8741a783 lw a5,-1932(gp) # 800008b4 <__neorv32_rte_vector_lut+0x64> + 4d8: f31ff06f j 408 <__neorv32_rte_core+0x15c> + 4dc: 8781a783 lw a5,-1928(gp) # 800008b8 <__neorv32_rte_vector_lut+0x68> + 4e0: f29ff06f j 408 <__neorv32_rte_core+0x15c> + 4e4: 87c1a783 lw a5,-1924(gp) # 800008bc <__neorv32_rte_vector_lut+0x6c> + 4e8: f21ff06f j 408 <__neorv32_rte_core+0x15c> + 4ec: 8801a783 lw a5,-1920(gp) # 800008c0 <__neorv32_rte_vector_lut+0x70> + 4f0: f19ff06f j 408 <__neorv32_rte_core+0x15c> + +000004f4 <__neorv32_rte_print_hex_word>: + 4f4: fe010113 addi sp,sp,-32 + 4f8: 01212823 sw s2,16(sp) + 4fc: 00050913 mv s2,a0 + 500: 00002537 lui a0,0x2 + 504: 00912a23 sw s1,20(sp) + 508: 82c50513 addi a0,a0,-2004 # 182c <__fini_array_end+0x10c> + 50c: 000024b7 lui s1,0x2 + 510: 00812c23 sw s0,24(sp) + 514: 01312623 sw s3,12(sp) + 518: 00112e23 sw ra,28(sp) + 51c: 01c00413 li s0,28 + 520: 64c000ef jal ra,b6c + 524: aa048493 addi s1,s1,-1376 # 1aa0 + 528: ffc00993 li s3,-4 + 52c: 008957b3 srl a5,s2,s0 + 530: 00f7f793 andi a5,a5,15 + 534: 00f487b3 add a5,s1,a5 + 538: 0007c503 lbu a0,0(a5) + 53c: ffc40413 addi s0,s0,-4 + 540: 614000ef jal ra,b54 + 544: ff3414e3 bne s0,s3,52c <__neorv32_rte_print_hex_word+0x38> + 548: 01c12083 lw ra,28(sp) + 54c: 01812403 lw s0,24(sp) + 550: 01412483 lw s1,20(sp) + 554: 01012903 lw s2,16(sp) + 558: 00c12983 lw s3,12(sp) + 55c: 02010113 addi sp,sp,32 + 560: 00008067 ret + +00000564 <__neorv32_rte_debug_handler>: + 564: fe010113 addi sp,sp,-32 + 568: 00112e23 sw ra,28(sp) + 56c: 00812c23 sw s0,24(sp) + 570: 00912a23 sw s1,20(sp) + 574: 01212823 sw s2,16(sp) + 578: 01312623 sw s3,12(sp) + 57c: 51c000ef jal ra,a98 + 580: 2a050063 beqz a0,820 <__neorv32_rte_debug_handler+0x2bc> + 584: 00002537 lui a0,0x2 + 588: 83050513 addi a0,a0,-2000 # 1830 <__fini_array_end+0x110> + 58c: 5e0000ef jal ra,b6c + 590: 342024f3 csrr s1,mcause + 594: 00b00793 li a5,11 + 598: 00002437 lui s0,0x2 + 59c: 0097ee63 bltu a5,s1,5b8 <__neorv32_rte_debug_handler+0x54> + 5a0: 00002737 lui a4,0x2 + 5a4: 00249793 slli a5,s1,0x2 + 5a8: 9e870713 addi a4,a4,-1560 # 19e8 <__fini_array_end+0x2c8> + 5ac: 00e787b3 add a5,a5,a4 + 5b0: 0007a783 lw a5,0(a5) + 5b4: 00078067 jr a5 + 5b8: 800007b7 lui a5,0x80000 + 5bc: 00b78713 addi a4,a5,11 # 8000000b <__crt0_stack_begin+0xffffe00f> + 5c0: 22e48863 beq s1,a4,7f0 <__neorv32_rte_debug_handler+0x28c> + 5c4: 04976463 bltu a4,s1,60c <__neorv32_rte_debug_handler+0xa8> + 5c8: 00378713 addi a4,a5,3 + 5cc: 1ee48c63 beq s1,a4,7c4 <__neorv32_rte_debug_handler+0x260> + 5d0: 00778793 addi a5,a5,7 + 5d4: 20f48863 beq s1,a5,7e4 <__neorv32_rte_debug_handler+0x280> + 5d8: 00002537 lui a0,0x2 + 5dc: 98850513 addi a0,a0,-1656 # 1988 <__fini_array_end+0x268> + 5e0: 58c000ef jal ra,b6c + 5e4: 00048513 mv a0,s1 + 5e8: f0dff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 5ec: 85840513 addi a0,s0,-1960 # 1858 <__fini_array_end+0x138> + 5f0: 57c000ef jal ra,b6c + 5f4: 34102473 csrr s0,mepc + 5f8: 00040513 mv a0,s0 + 5fc: ef9ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 600: 00200793 li a5,2 + 604: 0cf48e63 beq s1,a5,6e0 <__neorv32_rte_debug_handler+0x17c> + 608: 0380006f j 640 <__neorv32_rte_debug_handler+0xdc> + 60c: ff07c793 xori a5,a5,-16 + 610: 00f487b3 add a5,s1,a5 + 614: 00f00713 li a4,15 + 618: fcf760e3 bltu a4,a5,5d8 <__neorv32_rte_debug_handler+0x74> + 61c: 00002537 lui a0,0x2 + 620: 97c50513 addi a0,a0,-1668 # 197c <__fini_array_end+0x25c> + 624: 548000ef jal ra,b6c + 628: 00f4f513 andi a0,s1,15 + 62c: ec9ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 630: 85840513 addi a0,s0,-1960 + 634: 538000ef jal ra,b6c + 638: 34102573 csrr a0,mepc + 63c: eb9ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 640: 1004c663 bltz s1,74c <__neorv32_rte_debug_handler+0x1e8> + 644: 0200006f j 664 <__neorv32_rte_debug_handler+0x100> + 648: 00002537 lui a0,0x2 + 64c: 83850513 addi a0,a0,-1992 # 1838 <__fini_array_end+0x118> + 650: 51c000ef jal ra,b6c + 654: 85840513 addi a0,s0,-1960 + 658: 514000ef jal ra,b6c + 65c: 34102573 csrr a0,mepc + 660: e95ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 664: 00002537 lui a0,0x2 + 668: 9e050513 addi a0,a0,-1568 # 19e0 <__fini_array_end+0x2c0> + 66c: 500000ef jal ra,b6c + 670: 34302573 csrr a0,mtval + 674: 1680006f j 7dc <__neorv32_rte_debug_handler+0x278> + 678: 00002537 lui a0,0x2 + 67c: 86050513 addi a0,a0,-1952 # 1860 <__fini_array_end+0x140> + 680: 4ec000ef jal ra,b6c + 684: f7802783 lw a5,-136(zero) # ffffff78 <__crt0_stack_begin+0x7fffdf7c> + 688: 1807d063 bgez a5,808 <__neorv32_rte_debug_handler+0x2a4> + 68c: 0017f793 andi a5,a5,1 + 690: 16078663 beqz a5,7fc <__neorv32_rte_debug_handler+0x298> + 694: 00002537 lui a0,0x2 + 698: 9a050513 addi a0,a0,-1632 # 19a0 <__fini_array_end+0x280> + 69c: 4d0000ef jal ra,b6c + 6a0: 85840513 addi a0,s0,-1960 + 6a4: 4c8000ef jal ra,b6c + 6a8: 34102473 csrr s0,mepc + 6ac: 00040513 mv a0,s0 + 6b0: e45ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 6b4: 00200793 li a5,2 + 6b8: 02f48463 beq s1,a5,6e0 <__neorv32_rte_debug_handler+0x17c> + 6bc: fa9ff06f j 664 <__neorv32_rte_debug_handler+0x100> + 6c0: 00002537 lui a0,0x2 + 6c4: 87c50513 addi a0,a0,-1924 # 187c <__fini_array_end+0x15c> + 6c8: 4a4000ef jal ra,b6c + 6cc: 85840513 addi a0,s0,-1960 + 6d0: 49c000ef jal ra,b6c + 6d4: 34102473 csrr s0,mepc + 6d8: 00040513 mv a0,s0 + 6dc: e19ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 6e0: 00002537 lui a0,0x2 + 6e4: 9cc50513 addi a0,a0,-1588 # 19cc <__fini_array_end+0x2ac> + 6e8: 484000ef jal ra,b6c + 6ec: 00045483 lhu s1,0(s0) + 6f0: 01049493 slli s1,s1,0x10 + 6f4: 0104d493 srli s1,s1,0x10 + 6f8: 00240513 addi a0,s0,2 + 6fc: 00055503 lhu a0,0(a0) + 700: 00300793 li a5,3 + 704: 01051513 slli a0,a0,0x10 + 708: 0034f713 andi a4,s1,3 + 70c: 01055513 srli a0,a0,0x10 + 710: 10f70263 beq a4,a5,814 <__neorv32_rte_debug_handler+0x2b0> + 714: 00002537 lui a0,0x2 + 718: 82c50513 addi a0,a0,-2004 # 182c <__fini_array_end+0x10c> + 71c: 00002937 lui s2,0x2 + 720: 44c000ef jal ra,b6c + 724: 00c00413 li s0,12 + 728: aa090913 addi s2,s2,-1376 # 1aa0 + 72c: ffc00993 li s3,-4 + 730: 4084d7b3 sra a5,s1,s0 + 734: 00f7f793 andi a5,a5,15 + 738: 00f907b3 add a5,s2,a5 + 73c: 0007c503 lbu a0,0(a5) + 740: ffc40413 addi s0,s0,-4 + 744: 410000ef jal ra,b54 + 748: ff3414e3 bne s0,s3,730 <__neorv32_rte_debug_handler+0x1cc> + 74c: 01812403 lw s0,24(sp) + 750: 01c12083 lw ra,28(sp) + 754: 01412483 lw s1,20(sp) + 758: 01012903 lw s2,16(sp) + 75c: 00c12983 lw s3,12(sp) + 760: 00002537 lui a0,0x2 + 764: 9d450513 addi a0,a0,-1580 # 19d4 <__fini_array_end+0x2b4> + 768: 02010113 addi sp,sp,32 + 76c: 4000006f j b6c + 770: 00002537 lui a0,0x2 + 774: 89050513 addi a0,a0,-1904 # 1890 <__fini_array_end+0x170> + 778: ed9ff06f j 650 <__neorv32_rte_debug_handler+0xec> + 77c: 00002537 lui a0,0x2 + 780: 89c50513 addi a0,a0,-1892 # 189c <__fini_array_end+0x17c> + 784: ecdff06f j 650 <__neorv32_rte_debug_handler+0xec> + 788: 00002537 lui a0,0x2 + 78c: 8b450513 addi a0,a0,-1868 # 18b4 <__fini_array_end+0x194> + 790: ef1ff06f j 680 <__neorv32_rte_debug_handler+0x11c> + 794: 00002537 lui a0,0x2 + 798: 8c850513 addi a0,a0,-1848 # 18c8 <__fini_array_end+0x1a8> + 79c: eb5ff06f j 650 <__neorv32_rte_debug_handler+0xec> + 7a0: 00002537 lui a0,0x2 + 7a4: 8e450513 addi a0,a0,-1820 # 18e4 <__fini_array_end+0x1c4> + 7a8: ed9ff06f j 680 <__neorv32_rte_debug_handler+0x11c> + 7ac: 00002537 lui a0,0x2 + 7b0: 8f850513 addi a0,a0,-1800 # 18f8 <__fini_array_end+0x1d8> + 7b4: e9dff06f j 650 <__neorv32_rte_debug_handler+0xec> + 7b8: 00002537 lui a0,0x2 + 7bc: 91850513 addi a0,a0,-1768 # 1918 <__fini_array_end+0x1f8> + 7c0: e91ff06f j 650 <__neorv32_rte_debug_handler+0xec> + 7c4: 00002537 lui a0,0x2 + 7c8: 93850513 addi a0,a0,-1736 # 1938 <__fini_array_end+0x218> + 7cc: 3a0000ef jal ra,b6c + 7d0: 85840513 addi a0,s0,-1960 + 7d4: 398000ef jal ra,b6c + 7d8: 34102573 csrr a0,mepc + 7dc: d19ff0ef jal ra,4f4 <__neorv32_rte_print_hex_word> + 7e0: f6dff06f j 74c <__neorv32_rte_debug_handler+0x1e8> + 7e4: 00002537 lui a0,0x2 + 7e8: 95050513 addi a0,a0,-1712 # 1950 <__fini_array_end+0x230> + 7ec: fe1ff06f j 7cc <__neorv32_rte_debug_handler+0x268> + 7f0: 00002537 lui a0,0x2 + 7f4: 96450513 addi a0,a0,-1692 # 1964 <__fini_array_end+0x244> + 7f8: fd5ff06f j 7cc <__neorv32_rte_debug_handler+0x268> + 7fc: 00002537 lui a0,0x2 + 800: 9b050513 addi a0,a0,-1616 # 19b0 <__fini_array_end+0x290> + 804: e99ff06f j 69c <__neorv32_rte_debug_handler+0x138> + 808: 00002537 lui a0,0x2 + 80c: 9c050513 addi a0,a0,-1600 # 19c0 <__fini_array_end+0x2a0> + 810: e8dff06f j 69c <__neorv32_rte_debug_handler+0x138> + 814: 01051513 slli a0,a0,0x10 + 818: 00956533 or a0,a0,s1 + 81c: fc1ff06f j 7dc <__neorv32_rte_debug_handler+0x278> + 820: 01c12083 lw ra,28(sp) + 824: 01812403 lw s0,24(sp) + 828: 01412483 lw s1,20(sp) + 82c: 01012903 lw s2,16(sp) + 830: 00c12983 lw s3,12(sp) + 834: 02010113 addi sp,sp,32 + 838: 00008067 ret + +0000083c : + 83c: 01f00793 li a5,31 + 840: 02a7e263 bltu a5,a0,864 + 844: 800017b7 lui a5,0x80001 + 848: 00251513 slli a0,a0,0x2 + 84c: 85078793 addi a5,a5,-1968 # 80000850 <__crt0_stack_begin+0xffffe854> + 850: 00a787b3 add a5,a5,a0 + 854: 56400713 li a4,1380 + 858: 00e7a023 sw a4,0(a5) + 85c: 00000513 li a0,0 + 860: 00008067 ret + 864: 00100513 li a0,1 + 868: 00008067 ret + +0000086c : + 86c: ff010113 addi sp,sp,-16 + 870: 00112623 sw ra,12(sp) + 874: 00812423 sw s0,8(sp) + 878: 00912223 sw s1,4(sp) + 87c: 2ac00793 li a5,684 + 880: 30579073 csrw mtvec,a5 + 884: 00000793 li a5,0 + 888: 30479073 csrw mie,a5 + 88c: 34479073 csrw mip,a5 + 890: f6002c23 sw zero,-136(zero) # ffffff78 <__crt0_stack_begin+0x7fffdf7c> + 894: 00000413 li s0,0 + 898: 01d00493 li s1,29 + 89c: 00040513 mv a0,s0 + 8a0: 00140413 addi s0,s0,1 + 8a4: 0ff47413 zext.b s0,s0 + 8a8: f95ff0ef jal ra,83c + 8ac: fe9418e3 bne s0,s1,89c + 8b0: 00c12083 lw ra,12(sp) + 8b4: 00812403 lw s0,8(sp) + 8b8: 00412483 lw s1,4(sp) + 8bc: 01010113 addi sp,sp,16 + 8c0: 00008067 ret + +000008c4 : + 8c4: 30102673 csrr a2,misa + 8c8: 400005b7 lui a1,0x40000 + 8cc: 10058593 addi a1,a1,256 # 40000100 <__neorv32_ram_size+0x3fffe100> + 8d0: 00b677b3 and a5,a2,a1 + 8d4: 04b78263 beq a5,a1,918 + 8d8: 04051463 bnez a0,920 + 8dc: fe010113 addi sp,sp,-32 + 8e0: 00c12623 sw a2,12(sp) + 8e4: 00112e23 sw ra,28(sp) + 8e8: 1b0000ef jal ra,a98 + 8ec: 400007b7 lui a5,0x40000 + 8f0: 00c12603 lw a2,12(sp) + 8f4: 10078593 addi a1,a5,256 # 40000100 <__neorv32_ram_size+0x3fffe100> + 8f8: 00050863 beqz a0,908 + 8fc: 00002537 lui a0,0x2 + 900: a1850513 addi a0,a0,-1512 # 1a18 <__fini_array_end+0x2f8> + 904: 2c0000ef jal ra,bc4 + 908: 01c12083 lw ra,28(sp) + 90c: 00100513 li a0,1 + 910: 02010113 addi sp,sp,32 + 914: 00008067 ret + 918: 00000513 li a0,0 + 91c: 00008067 ret + 920: 00100513 li a0,1 + 924: 00008067 ret + +00000928 <__neorv32_uart_itoa>: + 928: fd010113 addi sp,sp,-48 + 92c: 02812423 sw s0,40(sp) + 930: 02912223 sw s1,36(sp) + 934: 03212023 sw s2,32(sp) + 938: 01312e23 sw s3,28(sp) + 93c: 01412c23 sw s4,24(sp) + 940: 02112623 sw ra,44(sp) + 944: 01512a23 sw s5,20(sp) + 948: 00002a37 lui s4,0x2 + 94c: 00050493 mv s1,a0 + 950: 00058413 mv s0,a1 + 954: 00058523 sb zero,10(a1) + 958: 00000993 li s3,0 + 95c: 00410913 addi s2,sp,4 + 960: ac4a0a13 addi s4,s4,-1340 # 1ac4 + 964: 00a00593 li a1,10 + 968: 00048513 mv a0,s1 + 96c: 49c000ef jal ra,e08 <__umodsi3> + 970: 00aa0533 add a0,s4,a0 + 974: 00054783 lbu a5,0(a0) + 978: 01390ab3 add s5,s2,s3 + 97c: 00048513 mv a0,s1 + 980: 00fa8023 sb a5,0(s5) + 984: 00a00593 li a1,10 + 988: 454000ef jal ra,ddc <__hidden___udivsi3> + 98c: 00198993 addi s3,s3,1 + 990: 00a00793 li a5,10 + 994: 00050493 mv s1,a0 + 998: fcf996e3 bne s3,a5,964 <__neorv32_uart_itoa+0x3c> + 99c: 00090693 mv a3,s2 + 9a0: 00900713 li a4,9 + 9a4: 03000613 li a2,48 + 9a8: 0096c583 lbu a1,9(a3) + 9ac: 00070793 mv a5,a4 + 9b0: fff70713 addi a4,a4,-1 + 9b4: 01071713 slli a4,a4,0x10 + 9b8: 01075713 srli a4,a4,0x10 + 9bc: 00c59a63 bne a1,a2,9d0 <__neorv32_uart_itoa+0xa8> + 9c0: 000684a3 sb zero,9(a3) + 9c4: fff68693 addi a3,a3,-1 + 9c8: fe0710e3 bnez a4,9a8 <__neorv32_uart_itoa+0x80> + 9cc: 00000793 li a5,0 + 9d0: 00f907b3 add a5,s2,a5 + 9d4: 00000713 li a4,0 + 9d8: 0007c683 lbu a3,0(a5) + 9dc: 00068c63 beqz a3,9f4 <__neorv32_uart_itoa+0xcc> + 9e0: 00170613 addi a2,a4,1 + 9e4: 00e40733 add a4,s0,a4 + 9e8: 00d70023 sb a3,0(a4) + 9ec: 01061713 slli a4,a2,0x10 + 9f0: 01075713 srli a4,a4,0x10 + 9f4: fff78693 addi a3,a5,-1 + 9f8: 02f91863 bne s2,a5,a28 <__neorv32_uart_itoa+0x100> + 9fc: 00e40433 add s0,s0,a4 + a00: 00040023 sb zero,0(s0) + a04: 02c12083 lw ra,44(sp) + a08: 02812403 lw s0,40(sp) + a0c: 02412483 lw s1,36(sp) + a10: 02012903 lw s2,32(sp) + a14: 01c12983 lw s3,28(sp) + a18: 01812a03 lw s4,24(sp) + a1c: 01412a83 lw s5,20(sp) + a20: 03010113 addi sp,sp,48 + a24: 00008067 ret + a28: 00068793 mv a5,a3 + a2c: fadff06f j 9d8 <__neorv32_uart_itoa+0xb0> + +00000a30 <__neorv32_uart_tohex>: + a30: 00002637 lui a2,0x2 + a34: 00758693 addi a3,a1,7 + a38: 00000713 li a4,0 + a3c: ab060613 addi a2,a2,-1360 # 1ab0 + a40: 02000813 li a6,32 + a44: 00e557b3 srl a5,a0,a4 + a48: 00f7f793 andi a5,a5,15 + a4c: 00f607b3 add a5,a2,a5 + a50: 0007c783 lbu a5,0(a5) + a54: 00470713 addi a4,a4,4 + a58: fff68693 addi a3,a3,-1 + a5c: 00f680a3 sb a5,1(a3) + a60: ff0712e3 bne a4,a6,a44 <__neorv32_uart_tohex+0x14> + a64: 00058423 sb zero,8(a1) + a68: 00008067 ret + +00000a6c <__neorv32_uart_touppercase.constprop.0>: + a6c: 00b50693 addi a3,a0,11 + a70: 01900613 li a2,25 + a74: 00054783 lbu a5,0(a0) + a78: f9f78713 addi a4,a5,-97 + a7c: 0ff77713 zext.b a4,a4 + a80: 00e66663 bltu a2,a4,a8c <__neorv32_uart_touppercase.constprop.0+0x20> + a84: fe078793 addi a5,a5,-32 + a88: 00f50023 sb a5,0(a0) + a8c: 00150513 addi a0,a0,1 + a90: fea692e3 bne a3,a0,a74 <__neorv32_uart_touppercase.constprop.0+0x8> + a94: 00008067 ret + +00000a98 : + a98: fe802503 lw a0,-24(zero) # ffffffe8 <__crt0_stack_begin+0x7fffdfec> + a9c: 01255513 srli a0,a0,0x12 + aa0: 00157513 andi a0,a0,1 + aa4: 00008067 ret + +00000aa8 : + aa8: ff010113 addi sp,sp,-16 + aac: 00812423 sw s0,8(sp) + ab0: 00912223 sw s1,4(sp) + ab4: 00112623 sw ra,12(sp) + ab8: fa002023 sw zero,-96(zero) # ffffffa0 <__crt0_stack_begin+0x7fffdfa4> + abc: fe002783 lw a5,-32(zero) # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + ac0: 00058413 mv s0,a1 + ac4: 00151593 slli a1,a0,0x1 + ac8: 00078513 mv a0,a5 + acc: 00060493 mv s1,a2 + ad0: 30c000ef jal ra,ddc <__hidden___udivsi3> + ad4: 01051513 slli a0,a0,0x10 + ad8: 000017b7 lui a5,0x1 + adc: 01055513 srli a0,a0,0x10 + ae0: 00000713 li a4,0 + ae4: ffe78793 addi a5,a5,-2 # ffe <_malloc_r+0x1a0> + ae8: 04a7e463 bltu a5,a0,b30 + aec: 0034f493 andi s1,s1,3 + af0: 01449493 slli s1,s1,0x14 + af4: 00347413 andi s0,s0,3 + af8: fff50793 addi a5,a0,-1 + afc: 0097e7b3 or a5,a5,s1 + b00: 01641413 slli s0,s0,0x16 + b04: 0087e7b3 or a5,a5,s0 + b08: 01871713 slli a4,a4,0x18 + b0c: 00c12083 lw ra,12(sp) + b10: 00812403 lw s0,8(sp) + b14: 00e7e7b3 or a5,a5,a4 + b18: 10000737 lui a4,0x10000 + b1c: 00e7e7b3 or a5,a5,a4 + b20: faf02023 sw a5,-96(zero) # ffffffa0 <__crt0_stack_begin+0x7fffdfa4> + b24: 00412483 lw s1,4(sp) + b28: 01010113 addi sp,sp,16 + b2c: 00008067 ret + b30: ffe70693 addi a3,a4,-2 # ffffffe <__neorv32_ram_size+0xfffdffe> + b34: 0fd6f693 andi a3,a3,253 + b38: 00069a63 bnez a3,b4c + b3c: 00355513 srli a0,a0,0x3 + b40: 00170713 addi a4,a4,1 + b44: 0ff77713 zext.b a4,a4 + b48: fa1ff06f j ae8 + b4c: 00155513 srli a0,a0,0x1 + b50: ff1ff06f j b40 + +00000b54 : + b54: 00040737 lui a4,0x40 + b58: fa002783 lw a5,-96(zero) # ffffffa0 <__crt0_stack_begin+0x7fffdfa4> + b5c: 00e7f7b3 and a5,a5,a4 + b60: fe079ce3 bnez a5,b58 + b64: faa02223 sw a0,-92(zero) # ffffffa4 <__crt0_stack_begin+0x7fffdfa8> + b68: 00008067 ret + +00000b6c : + b6c: ff010113 addi sp,sp,-16 + b70: 00812423 sw s0,8(sp) + b74: 01212023 sw s2,0(sp) + b78: 00112623 sw ra,12(sp) + b7c: 00912223 sw s1,4(sp) + b80: 00050413 mv s0,a0 + b84: 00a00913 li s2,10 + b88: 00044483 lbu s1,0(s0) + b8c: 00140413 addi s0,s0,1 + b90: 00049e63 bnez s1,bac + b94: 00c12083 lw ra,12(sp) + b98: 00812403 lw s0,8(sp) + b9c: 00412483 lw s1,4(sp) + ba0: 00012903 lw s2,0(sp) + ba4: 01010113 addi sp,sp,16 + ba8: 00008067 ret + bac: 01249663 bne s1,s2,bb8 + bb0: 00d00513 li a0,13 + bb4: fa1ff0ef jal ra,b54 + bb8: 00048513 mv a0,s1 + bbc: f99ff0ef jal ra,b54 + bc0: fc9ff06f j b88 + +00000bc4 : + bc4: fa010113 addi sp,sp,-96 + bc8: 04f12a23 sw a5,84(sp) + bcc: 04410793 addi a5,sp,68 + bd0: 02912a23 sw s1,52(sp) + bd4: 03212823 sw s2,48(sp) + bd8: 03312623 sw s3,44(sp) + bdc: 03412423 sw s4,40(sp) + be0: 03512223 sw s5,36(sp) + be4: 03612023 sw s6,32(sp) + be8: 01712e23 sw s7,28(sp) + bec: 01812c23 sw s8,24(sp) + bf0: 01912a23 sw s9,20(sp) + bf4: 02112e23 sw ra,60(sp) + bf8: 02812c23 sw s0,56(sp) + bfc: 00050493 mv s1,a0 + c00: 04b12223 sw a1,68(sp) + c04: 04c12423 sw a2,72(sp) + c08: 04d12623 sw a3,76(sp) + c0c: 04e12823 sw a4,80(sp) + c10: 05012c23 sw a6,88(sp) + c14: 05112e23 sw a7,92(sp) + c18: 00f12023 sw a5,0(sp) + c1c: 02500a13 li s4,37 + c20: 00a00a93 li s5,10 + c24: 07000913 li s2,112 + c28: 07500b13 li s6,117 + c2c: 07800b93 li s7,120 + c30: 07300c13 li s8,115 + c34: 06300993 li s3,99 + c38: 06400c93 li s9,100 + c3c: 0004c403 lbu s0,0(s1) + c40: 02041c63 bnez s0,c78 + c44: 03c12083 lw ra,60(sp) + c48: 03812403 lw s0,56(sp) + c4c: 03412483 lw s1,52(sp) + c50: 03012903 lw s2,48(sp) + c54: 02c12983 lw s3,44(sp) + c58: 02812a03 lw s4,40(sp) + c5c: 02412a83 lw s5,36(sp) + c60: 02012b03 lw s6,32(sp) + c64: 01c12b83 lw s7,28(sp) + c68: 01812c03 lw s8,24(sp) + c6c: 01412c83 lw s9,20(sp) + c70: 06010113 addi sp,sp,96 + c74: 00008067 ret + c78: 11441463 bne s0,s4,d80 + c7c: 0014c403 lbu s0,1(s1) + c80: 0f240263 beq s0,s2,d64 + c84: 06896263 bltu s2,s0,ce8 + c88: 09340463 beq s0,s3,d10 + c8c: 0089ee63 bltu s3,s0,ca8 + c90: 05800793 li a5,88 + c94: 0af40663 beq s0,a5,d40 + c98: 02500513 li a0,37 + c9c: eb9ff0ef jal ra,b54 + ca0: 00040513 mv a0,s0 + ca4: 07c0006f j d20 + ca8: 01940663 beq s0,s9,cb4 + cac: 06900793 li a5,105 + cb0: fef414e3 bne s0,a5,c98 + cb4: 00012783 lw a5,0(sp) + cb8: 0007a403 lw s0,0(a5) + cbc: 00478713 addi a4,a5,4 + cc0: 00e12023 sw a4,0(sp) + cc4: 00045863 bgez s0,cd4 + cc8: 02d00513 li a0,45 + ccc: 40800433 neg s0,s0 + cd0: e85ff0ef jal ra,b54 + cd4: 00410593 addi a1,sp,4 + cd8: 00040513 mv a0,s0 + cdc: c4dff0ef jal ra,928 <__neorv32_uart_itoa> + ce0: 00410513 addi a0,sp,4 + ce4: 0200006f j d04 + ce8: 05640063 beq s0,s6,d28 + cec: 07740c63 beq s0,s7,d64 + cf0: fb8414e3 bne s0,s8,c98 + cf4: 00012783 lw a5,0(sp) + cf8: 0007a503 lw a0,0(a5) + cfc: 00478713 addi a4,a5,4 + d00: 00e12023 sw a4,0(sp) + d04: e69ff0ef jal ra,b6c + d08: 00248493 addi s1,s1,2 + d0c: f31ff06f j c3c + d10: 00012783 lw a5,0(sp) + d14: 0007c503 lbu a0,0(a5) + d18: 00478713 addi a4,a5,4 + d1c: 00e12023 sw a4,0(sp) + d20: e35ff0ef jal ra,b54 + d24: fe5ff06f j d08 + d28: 00012783 lw a5,0(sp) + d2c: 00410593 addi a1,sp,4 + d30: 00478713 addi a4,a5,4 + d34: 0007a503 lw a0,0(a5) + d38: 00e12023 sw a4,0(sp) + d3c: fa1ff06f j cdc + d40: 00012783 lw a5,0(sp) + d44: 00410593 addi a1,sp,4 + d48: 0007a503 lw a0,0(a5) + d4c: 00478713 addi a4,a5,4 + d50: 00e12023 sw a4,0(sp) + d54: cddff0ef jal ra,a30 <__neorv32_uart_tohex> + d58: 00410513 addi a0,sp,4 + d5c: d11ff0ef jal ra,a6c <__neorv32_uart_touppercase.constprop.0> + d60: f81ff06f j ce0 + d64: 00012783 lw a5,0(sp) + d68: 00410593 addi a1,sp,4 + d6c: 0007a503 lw a0,0(a5) + d70: 00478713 addi a4,a5,4 + d74: 00e12023 sw a4,0(sp) + d78: cb9ff0ef jal ra,a30 <__neorv32_uart_tohex> + d7c: f65ff06f j ce0 + d80: 01541663 bne s0,s5,d8c + d84: 00d00513 li a0,13 + d88: dcdff0ef jal ra,b54 + d8c: 00040513 mv a0,s0 + d90: 00148493 addi s1,s1,1 + d94: dc1ff0ef jal ra,b54 + d98: ea5ff06f j c3c + +00000d9c <_sbrk>: + d9c: 80001637 lui a2,0x80001 + da0: 8ac18693 addi a3,gp,-1876 # 800008ec <__BSS_END__> + da4: 8ac18593 addi a1,gp,-1876 # 800008ec <__BSS_END__> + da8: 00050713 mv a4,a0 + dac: 83062503 lw a0,-2000(a2) # 80000830 <__crt0_stack_begin+0xffffe834> + db0: 00b68e63 beq a3,a1,dcc <_sbrk+0x30> + db4: 00e506b3 add a3,a0,a4 + db8: 8ac18793 addi a5,gp,-1876 # 800008ec <__BSS_END__> + dbc: 00f6f463 bgeu a3,a5,dc4 <_sbrk+0x28> + dc0: 00e687b3 add a5,a3,a4 + dc4: 82f62823 sw a5,-2000(a2) + dc8: 00008067 ret + dcc: 00000513 li a0,0 + dd0: 00008067 ret + +00000dd4 <__divsi3>: + dd4: 02054e63 bltz a0,e10 <__umodsi3+0x8> + dd8: 0405c363 bltz a1,e1e <__umodsi3+0x16> + +00000ddc <__hidden___udivsi3>: + ddc: 862e mv a2,a1 + dde: 85aa mv a1,a0 + de0: 557d li a0,-1 + de2: c215 beqz a2,e06 <__hidden___udivsi3+0x2a> + de4: 4685 li a3,1 + de6: 00b67863 bgeu a2,a1,df6 <__hidden___udivsi3+0x1a> + dea: 00c05663 blez a2,df6 <__hidden___udivsi3+0x1a> + dee: 0606 slli a2,a2,0x1 + df0: 0686 slli a3,a3,0x1 + df2: feb66ce3 bltu a2,a1,dea <__hidden___udivsi3+0xe> + df6: 4501 li a0,0 + df8: 00c5e463 bltu a1,a2,e00 <__hidden___udivsi3+0x24> + dfc: 8d91 sub a1,a1,a2 + dfe: 8d55 or a0,a0,a3 + e00: 8285 srli a3,a3,0x1 + e02: 8205 srli a2,a2,0x1 + e04: faf5 bnez a3,df8 <__hidden___udivsi3+0x1c> + e06: 8082 ret + +00000e08 <__umodsi3>: + e08: 8286 mv t0,ra + e0a: 3fc9 jal ddc <__hidden___udivsi3> + e0c: 852e mv a0,a1 + e0e: 8282 jr t0 + e10: 40a00533 neg a0,a0 + e14: 00b04763 bgtz a1,e22 <__umodsi3+0x1a> + e18: 40b005b3 neg a1,a1 + e1c: b7c1 j ddc <__hidden___udivsi3> + e1e: 40b005b3 neg a1,a1 + e22: 8286 mv t0,ra + e24: 3f65 jal ddc <__hidden___udivsi3> + e26: 40a00533 neg a0,a0 + e2a: 8282 jr t0 + +00000e2c <__modsi3>: + e2c: 8286 mv t0,ra + e2e: 0005c763 bltz a1,e3c <__modsi3+0x10> + e32: 00054963 bltz a0,e44 <__modsi3+0x18> + e36: 375d jal ddc <__hidden___udivsi3> + e38: 852e mv a0,a1 + e3a: 8282 jr t0 + e3c: 40b005b3 neg a1,a1 + e40: fe055be3 bgez a0,e36 <__modsi3+0xa> + e44: 40a00533 neg a0,a0 + e48: 3f51 jal ddc <__hidden___udivsi3> + e4a: 40b00533 neg a0,a1 + e4e: 8282 jr t0 + ... + +00000e52 : + e52: 800017b7 lui a5,0x80001 + e56: 85aa mv a1,a0 + e58: 83c7a503 lw a0,-1988(a5) # 8000083c <__crt0_stack_begin+0xffffe840> + e5c: a009 j e5e <_malloc_r> + +00000e5e <_malloc_r>: + e5e: 7179 addi sp,sp,-48 + e60: ce4e sw s3,28(sp) + e62: d606 sw ra,44(sp) + e64: d422 sw s0,40(sp) + e66: d226 sw s1,36(sp) + e68: d04a sw s2,32(sp) + e6a: cc52 sw s4,24(sp) + e6c: ca56 sw s5,20(sp) + e6e: c85a sw s6,16(sp) + e70: c65e sw s7,12(sp) + e72: c462 sw s8,8(sp) + e74: c266 sw s9,4(sp) + e76: 00b58793 addi a5,a1,11 + e7a: 4759 li a4,22 + e7c: 89aa mv s3,a0 + e7e: 04f76f63 bltu a4,a5,edc <_malloc_r+0x7e> + e82: 47c1 li a5,16 + e84: 18b7e063 bltu a5,a1,1004 <_malloc_r+0x1a6> + e88: 23ad jal 13f2 <__malloc_lock> + e8a: 44c1 li s1,16 + e8c: 47e1 li a5,24 + e8e: 4589 li a1,2 + e90: 80000937 lui s2,0x80000 + e94: 00090913 mv s2,s2 + e98: 97ca add a5,a5,s2 + e9a: 43c0 lw s0,4(a5) + e9c: ff878713 addi a4,a5,-8 + ea0: 24e40363 beq s0,a4,10e6 <_malloc_r+0x288> + ea4: 405c lw a5,4(s0) + ea6: 4454 lw a3,12(s0) + ea8: 4410 lw a2,8(s0) + eaa: 9bf1 andi a5,a5,-4 + eac: 97a2 add a5,a5,s0 + eae: 43d8 lw a4,4(a5) + eb0: c654 sw a3,12(a2) + eb2: c690 sw a2,8(a3) + eb4: 00176713 ori a4,a4,1 + eb8: 854e mv a0,s3 + eba: c3d8 sw a4,4(a5) + ebc: 2b25 jal 13f4 <__malloc_unlock> + ebe: 00840513 addi a0,s0,8 + ec2: 50b2 lw ra,44(sp) + ec4: 5422 lw s0,40(sp) + ec6: 5492 lw s1,36(sp) + ec8: 5902 lw s2,32(sp) + eca: 49f2 lw s3,28(sp) + ecc: 4a62 lw s4,24(sp) + ece: 4ad2 lw s5,20(sp) + ed0: 4b42 lw s6,16(sp) + ed2: 4bb2 lw s7,12(sp) + ed4: 4c22 lw s8,8(sp) + ed6: 4c92 lw s9,4(sp) + ed8: 6145 addi sp,sp,48 + eda: 8082 ret + edc: ff87f493 andi s1,a5,-8 + ee0: 1207c263 bltz a5,1004 <_malloc_r+0x1a6> + ee4: 12b4e063 bltu s1,a1,1004 <_malloc_r+0x1a6> + ee8: 2329 jal 13f2 <__malloc_lock> + eea: 1f700793 li a5,503 + eee: 2a97fb63 bgeu a5,s1,11a4 <_malloc_r+0x346> + ef2: 0094d793 srli a5,s1,0x9 + ef6: 10078c63 beqz a5,100e <_malloc_r+0x1b0> + efa: 4711 li a4,4 + efc: 22f76a63 bltu a4,a5,1130 <_malloc_r+0x2d2> + f00: 0064d793 srli a5,s1,0x6 + f04: 03978593 addi a1,a5,57 + f08: 03878513 addi a0,a5,56 + f0c: 00359693 slli a3,a1,0x3 + f10: 80000937 lui s2,0x80000 + f14: 00090913 mv s2,s2 + f18: 96ca add a3,a3,s2 + f1a: 42c0 lw s0,4(a3) + f1c: 16e1 addi a3,a3,-8 + f1e: 02868063 beq a3,s0,f3e <_malloc_r+0xe0> + f22: 463d li a2,15 + f24: a031 j f30 <_malloc_r+0xd2> + f26: 1a075d63 bgez a4,10e0 <_malloc_r+0x282> + f2a: 4440 lw s0,12(s0) + f2c: 00868963 beq a3,s0,f3e <_malloc_r+0xe0> + f30: 405c lw a5,4(s0) + f32: 9bf1 andi a5,a5,-4 + f34: 40978733 sub a4,a5,s1 + f38: fee657e3 bge a2,a4,f26 <_malloc_r+0xc8> + f3c: 85aa mv a1,a0 + f3e: 01092403 lw s0,16(s2) # 80000010 <__crt0_stack_begin+0xffffe014> + f42: 80000837 lui a6,0x80000 + f46: 00880813 addi a6,a6,8 # 80000008 <__crt0_stack_begin+0xffffe00c> + f4a: 17040a63 beq s0,a6,10be <_malloc_r+0x260> + f4e: 405c lw a5,4(s0) + f50: 46bd li a3,15 + f52: 9bf1 andi a5,a5,-4 + f54: 40978733 sub a4,a5,s1 + f58: 24e6cb63 blt a3,a4,11ae <_malloc_r+0x350> + f5c: 01092a23 sw a6,20(s2) + f60: 01092823 sw a6,16(s2) + f64: 22075663 bgez a4,1190 <_malloc_r+0x332> + f68: 1ff00713 li a4,511 + f6c: 00492503 lw a0,4(s2) + f70: 18f76063 bltu a4,a5,10f0 <_malloc_r+0x292> + f74: ff87f713 andi a4,a5,-8 + f78: 0721 addi a4,a4,8 # 40008 <__neorv32_ram_size+0x3e008> + f7a: 974a add a4,a4,s2 + f7c: 4314 lw a3,0(a4) + f7e: 0057d613 srli a2,a5,0x5 + f82: 4785 li a5,1 + f84: 00c797b3 sll a5,a5,a2 + f88: 8d5d or a0,a0,a5 + f8a: ff870793 addi a5,a4,-8 + f8e: c45c sw a5,12(s0) + f90: c414 sw a3,8(s0) + f92: 00a92223 sw a0,4(s2) + f96: c300 sw s0,0(a4) + f98: c6c0 sw s0,12(a3) + f9a: 4025d793 srai a5,a1,0x2 + f9e: 4605 li a2,1 + fa0: 00f61633 sll a2,a2,a5 + fa4: 06c56c63 bltu a0,a2,101c <_malloc_r+0x1be> + fa8: 00a677b3 and a5,a2,a0 + fac: ef81 bnez a5,fc4 <_malloc_r+0x166> + fae: 0606 slli a2,a2,0x1 + fb0: 99f1 andi a1,a1,-4 + fb2: 00a677b3 and a5,a2,a0 + fb6: 0591 addi a1,a1,4 + fb8: e791 bnez a5,fc4 <_malloc_r+0x166> + fba: 0606 slli a2,a2,0x1 + fbc: 00a677b3 and a5,a2,a0 + fc0: 0591 addi a1,a1,4 + fc2: dfe5 beqz a5,fba <_malloc_r+0x15c> + fc4: 48bd li a7,15 + fc6: 00359313 slli t1,a1,0x3 + fca: 934a add t1,t1,s2 + fcc: 851a mv a0,t1 + fce: 455c lw a5,12(a0) + fd0: 8e2e mv t3,a1 + fd2: 16f50f63 beq a0,a5,1150 <_malloc_r+0x2f2> + fd6: 43d8 lw a4,4(a5) + fd8: 843e mv s0,a5 + fda: 47dc lw a5,12(a5) + fdc: 9b71 andi a4,a4,-4 + fde: 409706b3 sub a3,a4,s1 + fe2: 16d8ce63 blt a7,a3,115e <_malloc_r+0x300> + fe6: fe06c6e3 bltz a3,fd2 <_malloc_r+0x174> + fea: 9722 add a4,a4,s0 + fec: 4354 lw a3,4(a4) + fee: 4410 lw a2,8(s0) + ff0: 854e mv a0,s3 + ff2: 0016e693 ori a3,a3,1 + ff6: c354 sw a3,4(a4) + ff8: c65c sw a5,12(a2) + ffa: c790 sw a2,8(a5) + ffc: 2ee5 jal 13f4 <__malloc_unlock> + ffe: 00840513 addi a0,s0,8 + 1002: b5c1 j ec2 <_malloc_r+0x64> + 1004: 47b1 li a5,12 + 1006: 00f9a023 sw a5,0(s3) + 100a: 4501 li a0,0 + 100c: bd5d j ec2 <_malloc_r+0x64> + 100e: 20000693 li a3,512 + 1012: 04000593 li a1,64 + 1016: 03f00513 li a0,63 + 101a: bddd j f10 <_malloc_r+0xb2> + 101c: 00892403 lw s0,8(s2) + 1020: 405c lw a5,4(s0) + 1022: ffc7fb13 andi s6,a5,-4 + 1026: 009b6763 bltu s6,s1,1034 <_malloc_r+0x1d6> + 102a: 409b0733 sub a4,s6,s1 + 102e: 47bd li a5,15 + 1030: 08e7ca63 blt a5,a4,10c4 <_malloc_r+0x266> + 1034: 800017b7 lui a5,0x80001 + 1038: 80001cb7 lui s9,0x80001 + 103c: 8487aa83 lw s5,-1976(a5) # 80000848 <__crt0_stack_begin+0xffffe84c> + 1040: 834ca703 lw a4,-1996(s9) # 80000834 <__crt0_stack_begin+0xffffe838> + 1044: 57fd li a5,-1 + 1046: 01640a33 add s4,s0,s6 + 104a: 9aa6 add s5,s5,s1 + 104c: 2cf70063 beq a4,a5,130c <_malloc_r+0x4ae> + 1050: 6785 lui a5,0x1 + 1052: 07bd addi a5,a5,15 # 100f <_malloc_r+0x1b1> + 1054: 9abe add s5,s5,a5 + 1056: 77fd lui a5,0xfffff + 1058: 00fafab3 and s5,s5,a5 + 105c: 85d6 mv a1,s5 + 105e: 854e mv a0,s3 + 1060: 2e59 jal 13f6 <_sbrk_r> + 1062: 57fd li a5,-1 + 1064: 8baa mv s7,a0 + 1066: 18f50463 beq a0,a5,11ee <_malloc_r+0x390> + 106a: 19456063 bltu a0,s4,11ea <_malloc_r+0x38c> + 106e: 88418c13 addi s8,gp,-1916 # 800008c4 <__malloc_current_mallinfo> + 1072: 000c2583 lw a1,0(s8) + 1076: 95d6 add a1,a1,s5 + 1078: 00bc2023 sw a1,0(s8) + 107c: 872e mv a4,a1 + 107e: 1eaa1463 bne s4,a0,1266 <_malloc_r+0x408> + 1082: 01451793 slli a5,a0,0x14 + 1086: 1e079063 bnez a5,1266 <_malloc_r+0x408> + 108a: 00892b83 lw s7,8(s2) + 108e: 015b07b3 add a5,s6,s5 + 1092: 0017e793 ori a5,a5,1 + 1096: 00fba223 sw a5,4(s7) + 109a: 80001737 lui a4,0x80001 + 109e: 84472683 lw a3,-1980(a4) # 80000844 <__crt0_stack_begin+0xffffe848> + 10a2: 00b6f463 bgeu a3,a1,10aa <_malloc_r+0x24c> + 10a6: 84b72223 sw a1,-1980(a4) + 10aa: 80001737 lui a4,0x80001 + 10ae: 84072683 lw a3,-1984(a4) # 80000840 <__crt0_stack_begin+0xffffe844> + 10b2: 00b6f463 bgeu a3,a1,10ba <_malloc_r+0x25c> + 10b6: 84b72023 sw a1,-1984(a4) + 10ba: 845e mv s0,s7 + 10bc: aa25 j 11f4 <_malloc_r+0x396> + 10be: 00492503 lw a0,4(s2) + 10c2: bde1 j f9a <_malloc_r+0x13c> + 10c4: 0014e793 ori a5,s1,1 + 10c8: c05c sw a5,4(s0) + 10ca: 94a2 add s1,s1,s0 + 10cc: 00992423 sw s1,8(s2) + 10d0: 00176713 ori a4,a4,1 + 10d4: 854e mv a0,s3 + 10d6: c0d8 sw a4,4(s1) + 10d8: 2e31 jal 13f4 <__malloc_unlock> + 10da: 00840513 addi a0,s0,8 + 10de: b3d5 j ec2 <_malloc_r+0x64> + 10e0: 4454 lw a3,12(s0) + 10e2: 4410 lw a2,8(s0) + 10e4: b3e1 j eac <_malloc_r+0x4e> + 10e6: 47c0 lw s0,12(a5) + 10e8: 0589 addi a1,a1,2 + 10ea: e4878ae3 beq a5,s0,f3e <_malloc_r+0xe0> + 10ee: bb5d j ea4 <_malloc_r+0x46> + 10f0: 0097d713 srli a4,a5,0x9 + 10f4: 4691 li a3,4 + 10f6: 0ee6f263 bgeu a3,a4,11da <_malloc_r+0x37c> + 10fa: 46d1 li a3,20 + 10fc: 24e6e163 bltu a3,a4,133e <_malloc_r+0x4e0> + 1100: 05c70613 addi a2,a4,92 + 1104: 05b70693 addi a3,a4,91 + 1108: 060e slli a2,a2,0x3 + 110a: 964a add a2,a2,s2 + 110c: 4218 lw a4,0(a2) + 110e: 1661 addi a2,a2,-8 + 1110: 00e61663 bne a2,a4,111c <_malloc_r+0x2be> + 1114: aaf5 j 1310 <_malloc_r+0x4b2> + 1116: 4718 lw a4,8(a4) + 1118: 00e60663 beq a2,a4,1124 <_malloc_r+0x2c6> + 111c: 4354 lw a3,4(a4) + 111e: 9af1 andi a3,a3,-4 + 1120: fed7ebe3 bltu a5,a3,1116 <_malloc_r+0x2b8> + 1124: 4750 lw a2,12(a4) + 1126: c450 sw a2,12(s0) + 1128: c418 sw a4,8(s0) + 112a: c600 sw s0,8(a2) + 112c: c740 sw s0,12(a4) + 112e: b5b5 j f9a <_malloc_r+0x13c> + 1130: 4751 li a4,20 + 1132: 0cf77d63 bgeu a4,a5,120c <_malloc_r+0x3ae> + 1136: 05400713 li a4,84 + 113a: 20f76e63 bltu a4,a5,1356 <_malloc_r+0x4f8> + 113e: 00c4d793 srli a5,s1,0xc + 1142: 06f78593 addi a1,a5,111 # fffff06f <__crt0_stack_begin+0x7fffd073> + 1146: 06e78513 addi a0,a5,110 + 114a: 00359693 slli a3,a1,0x3 + 114e: b3c9 j f10 <_malloc_r+0xb2> + 1150: 0e05 addi t3,t3,1 + 1152: 003e7793 andi a5,t3,3 + 1156: 0521 addi a0,a0,8 + 1158: c7f1 beqz a5,1224 <_malloc_r+0x3c6> + 115a: 455c lw a5,12(a0) + 115c: bd9d j fd2 <_malloc_r+0x174> + 115e: 4410 lw a2,8(s0) + 1160: 0014e593 ori a1,s1,1 + 1164: c04c sw a1,4(s0) + 1166: c65c sw a5,12(a2) + 1168: c790 sw a2,8(a5) + 116a: 94a2 add s1,s1,s0 + 116c: 00992a23 sw s1,20(s2) + 1170: 00992823 sw s1,16(s2) + 1174: 0016e793 ori a5,a3,1 + 1178: 0104a623 sw a6,12(s1) + 117c: 0104a423 sw a6,8(s1) + 1180: c0dc sw a5,4(s1) + 1182: 9722 add a4,a4,s0 + 1184: 854e mv a0,s3 + 1186: c314 sw a3,0(a4) + 1188: 24b5 jal 13f4 <__malloc_unlock> + 118a: 00840513 addi a0,s0,8 + 118e: bb15 j ec2 <_malloc_r+0x64> + 1190: 97a2 add a5,a5,s0 + 1192: 43d8 lw a4,4(a5) + 1194: 854e mv a0,s3 + 1196: 00176713 ori a4,a4,1 + 119a: c3d8 sw a4,4(a5) + 119c: 2ca1 jal 13f4 <__malloc_unlock> + 119e: 00840513 addi a0,s0,8 + 11a2: b305 j ec2 <_malloc_r+0x64> + 11a4: 0034d593 srli a1,s1,0x3 + 11a8: 00848793 addi a5,s1,8 + 11ac: b1d5 j e90 <_malloc_r+0x32> + 11ae: 0014e693 ori a3,s1,1 + 11b2: c054 sw a3,4(s0) + 11b4: 94a2 add s1,s1,s0 + 11b6: 00992a23 sw s1,20(s2) + 11ba: 00992823 sw s1,16(s2) + 11be: 00176693 ori a3,a4,1 + 11c2: 0104a623 sw a6,12(s1) + 11c6: 0104a423 sw a6,8(s1) + 11ca: c0d4 sw a3,4(s1) + 11cc: 97a2 add a5,a5,s0 + 11ce: 854e mv a0,s3 + 11d0: c398 sw a4,0(a5) + 11d2: 240d jal 13f4 <__malloc_unlock> + 11d4: 00840513 addi a0,s0,8 + 11d8: b1ed j ec2 <_malloc_r+0x64> + 11da: 0067d713 srli a4,a5,0x6 + 11de: 03970613 addi a2,a4,57 + 11e2: 03870693 addi a3,a4,56 + 11e6: 060e slli a2,a2,0x3 + 11e8: b70d j 110a <_malloc_r+0x2ac> + 11ea: 07240763 beq s0,s2,1258 <_malloc_r+0x3fa> + 11ee: 00892403 lw s0,8(s2) + 11f2: 405c lw a5,4(s0) + 11f4: 9bf1 andi a5,a5,-4 + 11f6: 40978733 sub a4,a5,s1 + 11fa: 0097e563 bltu a5,s1,1204 <_malloc_r+0x3a6> + 11fe: 47bd li a5,15 + 1200: ece7c2e3 blt a5,a4,10c4 <_malloc_r+0x266> + 1204: 854e mv a0,s3 + 1206: 22fd jal 13f4 <__malloc_unlock> + 1208: 4501 li a0,0 + 120a: b965 j ec2 <_malloc_r+0x64> + 120c: 05c78593 addi a1,a5,92 + 1210: 05b78513 addi a0,a5,91 + 1214: 00359693 slli a3,a1,0x3 + 1218: b9e5 j f10 <_malloc_r+0xb2> + 121a: 00832783 lw a5,8(t1) + 121e: 15fd addi a1,a1,-1 + 1220: 1c679663 bne a5,t1,13ec <_malloc_r+0x58e> + 1224: 0035f793 andi a5,a1,3 + 1228: 1361 addi t1,t1,-8 + 122a: fbe5 bnez a5,121a <_malloc_r+0x3bc> + 122c: 00492703 lw a4,4(s2) + 1230: fff64793 not a5,a2 + 1234: 8ff9 and a5,a5,a4 + 1236: 00f92223 sw a5,4(s2) + 123a: 0606 slli a2,a2,0x1 + 123c: dec7e0e3 bltu a5,a2,101c <_malloc_r+0x1be> + 1240: dc060ee3 beqz a2,101c <_malloc_r+0x1be> + 1244: 00f67733 and a4,a2,a5 + 1248: e711 bnez a4,1254 <_malloc_r+0x3f6> + 124a: 0606 slli a2,a2,0x1 + 124c: 00f67733 and a4,a2,a5 + 1250: 0e11 addi t3,t3,4 + 1252: df65 beqz a4,124a <_malloc_r+0x3ec> + 1254: 85f2 mv a1,t3 + 1256: bb85 j fc6 <_malloc_r+0x168> + 1258: 88418c13 addi s8,gp,-1916 # 800008c4 <__malloc_current_mallinfo> + 125c: 000c2703 lw a4,0(s8) + 1260: 9756 add a4,a4,s5 + 1262: 00ec2023 sw a4,0(s8) + 1266: 834ca683 lw a3,-1996(s9) + 126a: 57fd li a5,-1 + 126c: 10f68263 beq a3,a5,1370 <_malloc_r+0x512> + 1270: 414b87b3 sub a5,s7,s4 + 1274: 97ba add a5,a5,a4 + 1276: 00fc2023 sw a5,0(s8) + 127a: 007bfc93 andi s9,s7,7 + 127e: 0a0c8163 beqz s9,1320 <_malloc_r+0x4c2> + 1282: 6705 lui a4,0x1 + 1284: 419b8bb3 sub s7,s7,s9 + 1288: 00870593 addi a1,a4,8 # 1008 <_malloc_r+0x1aa> + 128c: 0ba1 addi s7,s7,8 + 128e: 419585b3 sub a1,a1,s9 + 1292: 9ade add s5,s5,s7 + 1294: 415585b3 sub a1,a1,s5 + 1298: 177d addi a4,a4,-1 + 129a: 00e5fa33 and s4,a1,a4 + 129e: 85d2 mv a1,s4 + 12a0: 854e mv a0,s3 + 12a2: 2a91 jal 13f6 <_sbrk_r> + 12a4: 57fd li a5,-1 + 12a6: 10f50563 beq a0,a5,13b0 <_malloc_r+0x552> + 12aa: 41750533 sub a0,a0,s7 + 12ae: 01450ab3 add s5,a0,s4 + 12b2: 000c2703 lw a4,0(s8) + 12b6: 01792423 sw s7,8(s2) + 12ba: 001ae793 ori a5,s5,1 + 12be: 00ea05b3 add a1,s4,a4 + 12c2: 00bc2023 sw a1,0(s8) + 12c6: 00fba223 sw a5,4(s7) + 12ca: dd2408e3 beq s0,s2,109a <_malloc_r+0x23c> + 12ce: 46bd li a3,15 + 12d0: 0b66f363 bgeu a3,s6,1376 <_malloc_r+0x518> + 12d4: 4058 lw a4,4(s0) + 12d6: ff4b0793 addi a5,s6,-12 + 12da: 9be1 andi a5,a5,-8 + 12dc: 8b05 andi a4,a4,1 + 12de: 8f5d or a4,a4,a5 + 12e0: c058 sw a4,4(s0) + 12e2: 4615 li a2,5 + 12e4: 00f40733 add a4,s0,a5 + 12e8: c350 sw a2,4(a4) + 12ea: c710 sw a2,8(a4) + 12ec: 00f6e563 bltu a3,a5,12f6 <_malloc_r+0x498> + 12f0: 004ba783 lw a5,4(s7) + 12f4: b35d j 109a <_malloc_r+0x23c> + 12f6: 00840593 addi a1,s0,8 + 12fa: 854e mv a0,s3 + 12fc: 2ad5 jal 14f0 <_free_r> + 12fe: 00892b83 lw s7,8(s2) + 1302: 000c2583 lw a1,0(s8) + 1306: 004ba783 lw a5,4(s7) + 130a: bb41 j 109a <_malloc_r+0x23c> + 130c: 0ac1 addi s5,s5,16 + 130e: b3b9 j 105c <_malloc_r+0x1fe> + 1310: 8689 srai a3,a3,0x2 + 1312: 4785 li a5,1 + 1314: 00d797b3 sll a5,a5,a3 + 1318: 8d5d or a0,a0,a5 + 131a: 00a92223 sw a0,4(s2) + 131e: b521 j 1126 <_malloc_r+0x2c8> + 1320: 015b85b3 add a1,s7,s5 + 1324: 40b005b3 neg a1,a1 + 1328: 05d2 slli a1,a1,0x14 + 132a: 0145da13 srli s4,a1,0x14 + 132e: 85d2 mv a1,s4 + 1330: 854e mv a0,s3 + 1332: 20d1 jal 13f6 <_sbrk_r> + 1334: 57fd li a5,-1 + 1336: f6f51ae3 bne a0,a5,12aa <_malloc_r+0x44c> + 133a: 4a01 li s4,0 + 133c: bf9d j 12b2 <_malloc_r+0x454> + 133e: 05400693 li a3,84 + 1342: 02e6ee63 bltu a3,a4,137e <_malloc_r+0x520> + 1346: 00c7d713 srli a4,a5,0xc + 134a: 06f70613 addi a2,a4,111 + 134e: 06e70693 addi a3,a4,110 + 1352: 060e slli a2,a2,0x3 + 1354: bb5d j 110a <_malloc_r+0x2ac> + 1356: 15400713 li a4,340 + 135a: 02f76e63 bltu a4,a5,1396 <_malloc_r+0x538> + 135e: 00f4d793 srli a5,s1,0xf + 1362: 07878593 addi a1,a5,120 + 1366: 07778513 addi a0,a5,119 + 136a: 00359693 slli a3,a1,0x3 + 136e: b64d j f10 <_malloc_r+0xb2> + 1370: 837caa23 sw s7,-1996(s9) + 1374: b719 j 127a <_malloc_r+0x41c> + 1376: 4785 li a5,1 + 1378: 00fba223 sw a5,4(s7) + 137c: b561 j 1204 <_malloc_r+0x3a6> + 137e: 15400693 li a3,340 + 1382: 02e6ed63 bltu a3,a4,13bc <_malloc_r+0x55e> + 1386: 00f7d713 srli a4,a5,0xf + 138a: 07870613 addi a2,a4,120 + 138e: 07770693 addi a3,a4,119 + 1392: 060e slli a2,a2,0x3 + 1394: bb9d j 110a <_malloc_r+0x2ac> + 1396: 55400713 li a4,1364 + 139a: 02f76d63 bltu a4,a5,13d4 <_malloc_r+0x576> + 139e: 0124d793 srli a5,s1,0x12 + 13a2: 07d78593 addi a1,a5,125 + 13a6: 07c78513 addi a0,a5,124 + 13aa: 00359693 slli a3,a1,0x3 + 13ae: b68d j f10 <_malloc_r+0xb2> + 13b0: 1ce1 addi s9,s9,-8 + 13b2: 9ae6 add s5,s5,s9 + 13b4: 417a8ab3 sub s5,s5,s7 + 13b8: 4a01 li s4,0 + 13ba: bde5 j 12b2 <_malloc_r+0x454> + 13bc: 55400693 li a3,1364 + 13c0: 02e6e163 bltu a3,a4,13e2 <_malloc_r+0x584> + 13c4: 0127d713 srli a4,a5,0x12 + 13c8: 07d70613 addi a2,a4,125 + 13cc: 07c70693 addi a3,a4,124 + 13d0: 060e slli a2,a2,0x3 + 13d2: bb25 j 110a <_malloc_r+0x2ac> + 13d4: 3f800693 li a3,1016 + 13d8: 07f00593 li a1,127 + 13dc: 07e00513 li a0,126 + 13e0: be05 j f10 <_malloc_r+0xb2> + 13e2: 3f800613 li a2,1016 + 13e6: 07e00693 li a3,126 + 13ea: b305 j 110a <_malloc_r+0x2ac> + 13ec: 00492783 lw a5,4(s2) + 13f0: b5a9 j 123a <_malloc_r+0x3dc> + +000013f2 <__malloc_lock>: + 13f2: 8082 ret + +000013f4 <__malloc_unlock>: + 13f4: 8082 ret + +000013f6 <_sbrk_r>: + 13f6: 1141 addi sp,sp,-16 + 13f8: c422 sw s0,8(sp) + 13fa: c226 sw s1,4(sp) + 13fc: 842a mv s0,a0 + 13fe: 852e mv a0,a1 + 1400: c606 sw ra,12(sp) + 1402: 8001a623 sw zero,-2036(gp) # 8000084c + 1406: 997ff0ef jal ra,d9c <_sbrk> + 140a: 57fd li a5,-1 + 140c: 00f50763 beq a0,a5,141a <_sbrk_r+0x24> + 1410: 40b2 lw ra,12(sp) + 1412: 4422 lw s0,8(sp) + 1414: 4492 lw s1,4(sp) + 1416: 0141 addi sp,sp,16 + 1418: 8082 ret + 141a: 80c1a783 lw a5,-2036(gp) # 8000084c + 141e: dbed beqz a5,1410 <_sbrk_r+0x1a> + 1420: 40b2 lw ra,12(sp) + 1422: c01c sw a5,0(s0) + 1424: 4422 lw s0,8(sp) + 1426: 4492 lw s1,4(sp) + 1428: 0141 addi sp,sp,16 + 142a: 8082 ret + +0000142c <_malloc_trim_r>: + 142c: 1101 addi sp,sp,-32 + 142e: c64e sw s3,12(sp) + 1430: 800009b7 lui s3,0x80000 + 1434: cc22 sw s0,24(sp) + 1436: ca26 sw s1,20(sp) + 1438: c84a sw s2,16(sp) + 143a: c452 sw s4,8(sp) + 143c: ce06 sw ra,28(sp) + 143e: 8a2e mv s4,a1 + 1440: 892a mv s2,a0 + 1442: 00098993 mv s3,s3 + 1446: 3775 jal 13f2 <__malloc_lock> + 1448: 0089a703 lw a4,8(s3) # 80000008 <__crt0_stack_begin+0xffffe00c> + 144c: 6785 lui a5,0x1 + 144e: fef78413 addi s0,a5,-17 # fef <_malloc_r+0x191> + 1452: 4344 lw s1,4(a4) + 1454: 98f1 andi s1,s1,-4 + 1456: 9426 add s0,s0,s1 + 1458: 41440433 sub s0,s0,s4 + 145c: 8031 srli s0,s0,0xc + 145e: 147d addi s0,s0,-1 + 1460: 0432 slli s0,s0,0xc + 1462: 00f44a63 blt s0,a5,1476 <_malloc_trim_r+0x4a> + 1466: 4581 li a1,0 + 1468: 854a mv a0,s2 + 146a: 3771 jal 13f6 <_sbrk_r> + 146c: 0089a783 lw a5,8(s3) + 1470: 97a6 add a5,a5,s1 + 1472: 00f50d63 beq a0,a5,148c <_malloc_trim_r+0x60> + 1476: 854a mv a0,s2 + 1478: 3fb5 jal 13f4 <__malloc_unlock> + 147a: 40f2 lw ra,28(sp) + 147c: 4462 lw s0,24(sp) + 147e: 44d2 lw s1,20(sp) + 1480: 4942 lw s2,16(sp) + 1482: 49b2 lw s3,12(sp) + 1484: 4a22 lw s4,8(sp) + 1486: 4501 li a0,0 + 1488: 6105 addi sp,sp,32 + 148a: 8082 ret + 148c: 408005b3 neg a1,s0 + 1490: 854a mv a0,s2 + 1492: 3795 jal 13f6 <_sbrk_r> + 1494: 57fd li a5,-1 + 1496: 02f50863 beq a0,a5,14c6 <_malloc_trim_r+0x9a> + 149a: 88418793 addi a5,gp,-1916 # 800008c4 <__malloc_current_mallinfo> + 149e: 4398 lw a4,0(a5) + 14a0: 0089a683 lw a3,8(s3) + 14a4: 8c81 sub s1,s1,s0 + 14a6: 0014e493 ori s1,s1,1 + 14aa: 8f01 sub a4,a4,s0 + 14ac: 854a mv a0,s2 + 14ae: c2c4 sw s1,4(a3) + 14b0: c398 sw a4,0(a5) + 14b2: 3789 jal 13f4 <__malloc_unlock> + 14b4: 40f2 lw ra,28(sp) + 14b6: 4462 lw s0,24(sp) + 14b8: 44d2 lw s1,20(sp) + 14ba: 4942 lw s2,16(sp) + 14bc: 49b2 lw s3,12(sp) + 14be: 4a22 lw s4,8(sp) + 14c0: 4505 li a0,1 + 14c2: 6105 addi sp,sp,32 + 14c4: 8082 ret + 14c6: 4581 li a1,0 + 14c8: 854a mv a0,s2 + 14ca: 3735 jal 13f6 <_sbrk_r> + 14cc: 0089a703 lw a4,8(s3) + 14d0: 46bd li a3,15 + 14d2: 40e507b3 sub a5,a0,a4 + 14d6: faf6d0e3 bge a3,a5,1476 <_malloc_trim_r+0x4a> + 14da: 800016b7 lui a3,0x80001 + 14de: 8346a683 lw a3,-1996(a3) # 80000834 <__crt0_stack_begin+0xffffe838> + 14e2: 0017e793 ori a5,a5,1 + 14e6: c35c sw a5,4(a4) + 14e8: 8d15 sub a0,a0,a3 + 14ea: 88a1a223 sw a0,-1916(gp) # 800008c4 <__malloc_current_mallinfo> + 14ee: b761 j 1476 <_malloc_trim_r+0x4a> + +000014f0 <_free_r>: + 14f0: 10058b63 beqz a1,1606 <_free_r+0x116> + 14f4: 1141 addi sp,sp,-16 + 14f6: c422 sw s0,8(sp) + 14f8: c226 sw s1,4(sp) + 14fa: 842e mv s0,a1 + 14fc: 84aa mv s1,a0 + 14fe: c606 sw ra,12(sp) + 1500: 3dcd jal 13f2 <__malloc_lock> + 1502: ffc42503 lw a0,-4(s0) + 1506: ff840713 addi a4,s0,-8 + 150a: 800005b7 lui a1,0x80000 + 150e: ffe57793 andi a5,a0,-2 + 1512: 00f70633 add a2,a4,a5 + 1516: 00058593 mv a1,a1 + 151a: 4254 lw a3,4(a2) + 151c: 0085a803 lw a6,8(a1) # 80000008 <__crt0_stack_begin+0xffffe00c> + 1520: 9af1 andi a3,a3,-4 + 1522: 12c80563 beq a6,a2,164c <_free_r+0x15c> + 1526: c254 sw a3,4(a2) + 1528: 8905 andi a0,a0,1 + 152a: 00d60833 add a6,a2,a3 + 152e: e93d bnez a0,15a4 <_free_r+0xb4> + 1530: ff842303 lw t1,-8(s0) + 1534: 00482803 lw a6,4(a6) + 1538: 80000537 lui a0,0x80000 + 153c: 40670733 sub a4,a4,t1 + 1540: 00872883 lw a7,8(a4) + 1544: 00850513 addi a0,a0,8 # 80000008 <__crt0_stack_begin+0xffffe00c> + 1548: 979a add a5,a5,t1 + 154a: 00187813 andi a6,a6,1 + 154e: 0ea88263 beq a7,a0,1632 <_free_r+0x142> + 1552: 00c72303 lw t1,12(a4) + 1556: 0068a623 sw t1,12(a7) + 155a: 01132423 sw a7,8(t1) + 155e: 12080363 beqz a6,1684 <_free_r+0x194> + 1562: 0017e693 ori a3,a5,1 + 1566: c354 sw a3,4(a4) + 1568: c21c sw a5,0(a2) + 156a: 1ff00693 li a3,511 + 156e: 04f6e863 bltu a3,a5,15be <_free_r+0xce> + 1572: ff87f693 andi a3,a5,-8 + 1576: 06a1 addi a3,a3,8 + 1578: 41c8 lw a0,4(a1) + 157a: 96ae add a3,a3,a1 + 157c: 4290 lw a2,0(a3) + 157e: 0057d813 srli a6,a5,0x5 + 1582: 4785 li a5,1 + 1584: 010797b3 sll a5,a5,a6 + 1588: 8fc9 or a5,a5,a0 + 158a: ff868513 addi a0,a3,-8 + 158e: c748 sw a0,12(a4) + 1590: c710 sw a2,8(a4) + 1592: c1dc sw a5,4(a1) + 1594: c298 sw a4,0(a3) + 1596: c658 sw a4,12(a2) + 1598: 4422 lw s0,8(sp) + 159a: 40b2 lw ra,12(sp) + 159c: 8526 mv a0,s1 + 159e: 4492 lw s1,4(sp) + 15a0: 0141 addi sp,sp,16 + 15a2: bd89 j 13f4 <__malloc_unlock> + 15a4: 00482503 lw a0,4(a6) + 15a8: 8905 andi a0,a0,1 + 15aa: cd39 beqz a0,1608 <_free_r+0x118> + 15ac: 0017e693 ori a3,a5,1 + 15b0: fed42e23 sw a3,-4(s0) + 15b4: c21c sw a5,0(a2) + 15b6: 1ff00693 li a3,511 + 15ba: faf6fce3 bgeu a3,a5,1572 <_free_r+0x82> + 15be: 0097d693 srli a3,a5,0x9 + 15c2: 4611 li a2,4 + 15c4: 0cd66263 bltu a2,a3,1688 <_free_r+0x198> + 15c8: 0067d693 srli a3,a5,0x6 + 15cc: 03968513 addi a0,a3,57 + 15d0: 03868613 addi a2,a3,56 + 15d4: 050e slli a0,a0,0x3 + 15d6: 952e add a0,a0,a1 + 15d8: 4114 lw a3,0(a0) + 15da: 1561 addi a0,a0,-8 + 15dc: 00d51663 bne a0,a3,15e8 <_free_r+0xf8> + 15e0: a0dd j 16c6 <_free_r+0x1d6> + 15e2: 4694 lw a3,8(a3) + 15e4: 00d50663 beq a0,a3,15f0 <_free_r+0x100> + 15e8: 42d0 lw a2,4(a3) + 15ea: 9a71 andi a2,a2,-4 + 15ec: fec7ebe3 bltu a5,a2,15e2 <_free_r+0xf2> + 15f0: 46c8 lw a0,12(a3) + 15f2: c748 sw a0,12(a4) + 15f4: c714 sw a3,8(a4) + 15f6: 4422 lw s0,8(sp) + 15f8: c518 sw a4,8(a0) + 15fa: 40b2 lw ra,12(sp) + 15fc: 8526 mv a0,s1 + 15fe: 4492 lw s1,4(sp) + 1600: c6d8 sw a4,12(a3) + 1602: 0141 addi sp,sp,16 + 1604: bbc5 j 13f4 <__malloc_unlock> + 1606: 8082 ret + 1608: 80000537 lui a0,0x80000 + 160c: 97b6 add a5,a5,a3 + 160e: 00850513 addi a0,a0,8 # 80000008 <__crt0_stack_begin+0xffffe00c> + 1612: 4614 lw a3,8(a2) + 1614: 08a68f63 beq a3,a0,16b2 <_free_r+0x1c2> + 1618: 00c62803 lw a6,12(a2) + 161c: 0017e513 ori a0,a5,1 + 1620: 00f70633 add a2,a4,a5 + 1624: 0106a623 sw a6,12(a3) + 1628: 00d82423 sw a3,8(a6) + 162c: c348 sw a0,4(a4) + 162e: c21c sw a5,0(a2) + 1630: bf2d j 156a <_free_r+0x7a> + 1632: 0e081163 bnez a6,1714 <_free_r+0x224> + 1636: 460c lw a1,8(a2) + 1638: 4650 lw a2,12(a2) + 163a: 96be add a3,a3,a5 + 163c: 0016e793 ori a5,a3,1 + 1640: c5d0 sw a2,12(a1) + 1642: c60c sw a1,8(a2) + 1644: c35c sw a5,4(a4) + 1646: 9736 add a4,a4,a3 + 1648: c314 sw a3,0(a4) + 164a: b7b9 j 1598 <_free_r+0xa8> + 164c: 8905 andi a0,a0,1 + 164e: 96be add a3,a3,a5 + 1650: e909 bnez a0,1662 <_free_r+0x172> + 1652: ff842503 lw a0,-8(s0) + 1656: 8f09 sub a4,a4,a0 + 1658: 475c lw a5,12(a4) + 165a: 4710 lw a2,8(a4) + 165c: 96aa add a3,a3,a0 + 165e: c65c sw a5,12(a2) + 1660: c790 sw a2,8(a5) + 1662: 800017b7 lui a5,0x80001 + 1666: 0016e613 ori a2,a3,1 + 166a: 8387a783 lw a5,-1992(a5) # 80000838 <__crt0_stack_begin+0xffffe83c> + 166e: c350 sw a2,4(a4) + 1670: c598 sw a4,8(a1) + 1672: f2f6e3e3 bltu a3,a5,1598 <_free_r+0xa8> + 1676: 800017b7 lui a5,0x80001 + 167a: 8487a583 lw a1,-1976(a5) # 80000848 <__crt0_stack_begin+0xffffe84c> + 167e: 8526 mv a0,s1 + 1680: 3375 jal 142c <_malloc_trim_r> + 1682: bf19 j 1598 <_free_r+0xa8> + 1684: 97b6 add a5,a5,a3 + 1686: b771 j 1612 <_free_r+0x122> + 1688: 4651 li a2,20 + 168a: 00d67e63 bgeu a2,a3,16a6 <_free_r+0x1b6> + 168e: 05400613 li a2,84 + 1692: 04d66463 bltu a2,a3,16da <_free_r+0x1ea> + 1696: 00c7d693 srli a3,a5,0xc + 169a: 06f68513 addi a0,a3,111 + 169e: 06e68613 addi a2,a3,110 + 16a2: 050e slli a0,a0,0x3 + 16a4: bf0d j 15d6 <_free_r+0xe6> + 16a6: 05c68513 addi a0,a3,92 + 16aa: 05b68613 addi a2,a3,91 + 16ae: 050e slli a0,a0,0x3 + 16b0: b71d j 15d6 <_free_r+0xe6> + 16b2: c9d8 sw a4,20(a1) + 16b4: c998 sw a4,16(a1) + 16b6: 0017e693 ori a3,a5,1 + 16ba: c748 sw a0,12(a4) + 16bc: c708 sw a0,8(a4) + 16be: c354 sw a3,4(a4) + 16c0: 973e add a4,a4,a5 + 16c2: c31c sw a5,0(a4) + 16c4: bdd1 j 1598 <_free_r+0xa8> + 16c6: 0045a803 lw a6,4(a1) + 16ca: 8609 srai a2,a2,0x2 + 16cc: 4785 li a5,1 + 16ce: 00c797b3 sll a5,a5,a2 + 16d2: 0107e7b3 or a5,a5,a6 + 16d6: c1dc sw a5,4(a1) + 16d8: bf29 j 15f2 <_free_r+0x102> + 16da: 15400613 li a2,340 + 16de: 00d66a63 bltu a2,a3,16f2 <_free_r+0x202> + 16e2: 00f7d693 srli a3,a5,0xf + 16e6: 07868513 addi a0,a3,120 + 16ea: 07768613 addi a2,a3,119 + 16ee: 050e slli a0,a0,0x3 + 16f0: b5dd j 15d6 <_free_r+0xe6> + 16f2: 55400613 li a2,1364 + 16f6: 00d66a63 bltu a2,a3,170a <_free_r+0x21a> + 16fa: 0127d693 srli a3,a5,0x12 + 16fe: 07d68513 addi a0,a3,125 + 1702: 07c68613 addi a2,a3,124 + 1706: 050e slli a0,a0,0x3 + 1708: b5f9 j 15d6 <_free_r+0xe6> + 170a: 3f800513 li a0,1016 + 170e: 07e00613 li a2,126 + 1712: b5d1 j 15d6 <_free_r+0xe6> + 1714: 0017e693 ori a3,a5,1 + 1718: c354 sw a3,4(a4) + 171a: c21c sw a5,0(a2) + 171c: bdb5 j 1598 <_free_r+0xa8> + ... + +Disassembly of section .rodata: + +00001720 <__fini_array_end>: + 1720: 654d lui a0,0x13 + 1722: 6f6d lui t5,0x1b + 1724: 7972 .2byte 0x7972 + 1726: 6d20 .2byte 0x6d20 + 1728: 6e61 lui t3,0x18 + 172a: 6761 lui a4,0x18 + 172c: 6d65 lui s10,0x19 + 172e: 6e65 lui t3,0x19 + 1730: 2074 .2byte 0x2074 + 1732: 6c637963 bgeu t1,t1,1e04 <__RODATA_END__+0x334> + 1736: 7365 lui t1,0xffff9 + 1738: 6d20 .2byte 0x6d20 + 173a: 6165 addi sp,sp,112 + 173c: 65727573 csrrci a0,0x657,4 + 1740: 3a20 .2byte 0x3a20 + 1742: 000a c.slli zero,0x2 + 1744: 454e lw a0,208(sp) + 1746: 3356524f .4byte 0x3356524f + 174a: 3a32 .2byte 0x3a32 + 174c: 4620 lw s0,72(a2) + 174e: 6572 .2byte 0x6572 + 1750: 2071 jal 17dc <__fini_array_end+0xbc> + 1752: 203d jal 1780 <__fini_array_end+0x60> + 1754: 7525 lui a0,0xfffe9 + 1756: 000a c.slli zero,0x2 + 1758: 454e lw a0,208(sp) + 175a: 3356524f .4byte 0x3356524f + 175e: 3a32 .2byte 0x3a32 + 1760: 6d20 .2byte 0x6d20 + 1762: 6165 addi sp,sp,112 + 1764: 206e .2byte 0x206e + 1766: 6c637963 bgeu t1,t1,1e38 <__RODATA_END__+0x368> + 176a: 7365 lui t1,0xffff9 + 176c: 4e20 lw s0,88(a2) + 176e: 3d20 .2byte 0x3d20 + 1770: 2520 .2byte 0x2520 + 1772: 2075 jal 181e <__fini_array_end+0xfe> + 1774: 203a .2byte 0x203a + 1776: 2020 .2byte 0x2020 + 1778: 2020 .2byte 0x2020 + 177a: 2520 .2byte 0x2520 + 177c: 0a75 addi s4,s4,29 + 177e: 0000 unimp + 1780: 6e65 lui t3,0x19 + 1782: 3a64 .2byte 0x3a64 + 1784: 000a c.slli zero,0x2 + 1786: 0000 unimp + 1788: 0350 addi a2,sp,388 + 178a: 0000 unimp + 178c: 0394 addi a3,sp,448 + 178e: 0000 unimp + 1790: 03a0 addi s0,sp,456 + 1792: 0000 unimp + 1794: 03ac addi a1,sp,456 + 1796: 0000 unimp + 1798: 03b8 addi a4,sp,456 + 179a: 0000 unimp + 179c: 03c4 addi s1,sp,452 + 179e: 0000 unimp + 17a0: 03d0 addi a2,sp,452 + 17a2: 0000 unimp + 17a4: 03dc addi a5,sp,452 + 17a6: 0000 unimp + 17a8: 03e8 addi a0,sp,460 + 17aa: 0000 unimp + 17ac: 0344 addi s1,sp,388 + 17ae: 0000 unimp + 17b0: 0344 addi s1,sp,388 + 17b2: 0000 unimp + 17b4: 03f4 addi a3,sp,460 + 17b6: 0000 unimp + 17b8: 0400 addi s0,sp,512 + 17ba: 0000 unimp + 17bc: 0344 addi s1,sp,388 + 17be: 0000 unimp + 17c0: 0344 addi s1,sp,388 + 17c2: 0000 unimp + 17c4: 0344 addi s1,sp,388 + 17c6: 0000 unimp + 17c8: 0458 addi a4,sp,516 + 17ca: 0000 unimp + 17cc: 0344 addi s1,sp,388 + 17ce: 0000 unimp + 17d0: 0344 addi s1,sp,388 + 17d2: 0000 unimp + 17d4: 0344 addi s1,sp,388 + 17d6: 0000 unimp + 17d8: 0464 addi s1,sp,524 + 17da: 0000 unimp + 17dc: 0344 addi s1,sp,388 + 17de: 0000 unimp + 17e0: 0344 addi s1,sp,388 + 17e2: 0000 unimp + 17e4: 0344 addi s1,sp,388 + 17e6: 0000 unimp + 17e8: 0344 addi s1,sp,388 + 17ea: 0000 unimp + 17ec: 0470 addi a2,sp,524 + 17ee: 0000 unimp + 17f0: 047c addi a5,sp,524 + 17f2: 0000 unimp + 17f4: 0484 addi s1,sp,576 + 17f6: 0000 unimp + 17f8: 048c addi a1,sp,576 + 17fa: 0000 unimp + 17fc: 0494 addi a3,sp,576 + 17fe: 0000 unimp + 1800: 049c addi a5,sp,576 + 1802: 0000 unimp + 1804: 04a4 addi s1,sp,584 + 1806: 0000 unimp + 1808: 04ac addi a1,sp,584 + 180a: 0000 unimp + 180c: 04b4 addi a3,sp,584 + 180e: 0000 unimp + 1810: 04bc addi a5,sp,584 + 1812: 0000 unimp + 1814: 04c4 addi s1,sp,580 + 1816: 0000 unimp + 1818: 04cc addi a1,sp,580 + 181a: 0000 unimp + 181c: 04d4 addi a3,sp,580 + 181e: 0000 unimp + 1820: 04dc addi a5,sp,580 + 1822: 0000 unimp + 1824: 04e4 addi s1,sp,588 + 1826: 0000 unimp + 1828: 04ec addi a1,sp,588 + 182a: 0000 unimp + 182c: 7830 .2byte 0x7830 + 182e: 0000 unimp + 1830: 523c lw a5,96(a2) + 1832: 4554 lw a3,12(a0) + 1834: 203e .2byte 0x203e + 1836: 0000 unimp + 1838: 6e49 lui t3,0x12 + 183a: 75727473 csrrci s0,0x757,4 + 183e: 6f697463 bgeu s2,s6,1f26 <__RODATA_END__+0x456> + 1842: 206e .2byte 0x206e + 1844: 6461 lui s0,0x18 + 1846: 7264 .2byte 0x7264 + 1848: 7365 lui t1,0xffff9 + 184a: 696d2073 csrs 0x696,s10 + 184e: 696c6173 csrrsi sp,0x696,24 + 1852: 64656e67 .4byte 0x64656e67 + 1856: 0000 unimp + 1858: 4020 lw s0,64(s0) + 185a: 5020 lw s0,96(s0) + 185c: 00003d43 .4byte 0x3d43 + 1860: 6e49 lui t3,0x12 + 1862: 75727473 csrrci s0,0x757,4 + 1866: 6f697463 bgeu s2,s6,1f4e <__RODATA_END__+0x47e> + 186a: 206e .2byte 0x206e + 186c: 6361 lui t1,0x18 + 186e: 73736563 bltu t1,s7,1f98 <__RODATA_END__+0x4c8> + 1872: 6620 .2byte 0x6620 + 1874: 7561 lui a0,0xffff8 + 1876: 746c .2byte 0x746c + 1878: 0000 unimp + 187a: 0000 unimp + 187c: 6c49 lui s8,0x12 + 187e: 656c .2byte 0x656c + 1880: 206c6167 .4byte 0x206c6167 + 1884: 6e69 lui t3,0x1a + 1886: 75727473 csrrci s0,0x757,4 + 188a: 6f697463 bgeu s2,s6,1f72 <__RODATA_END__+0x4a2> + 188e: 006e c.slli zero,0x1b + 1890: 7242 .2byte 0x7242 + 1892: 6165 addi sp,sp,112 + 1894: 696f706b .4byte 0x696f706b + 1898: 746e .2byte 0x746e + 189a: 0000 unimp + 189c: 6f4c .2byte 0x6f4c + 189e: 6461 lui s0,0x18 + 18a0: 6120 .2byte 0x6120 + 18a2: 6464 .2byte 0x6464 + 18a4: 6572 .2byte 0x6572 + 18a6: 6d207373 csrrci t1,0x6d2,0 + 18aa: 7369 lui t1,0xffffa + 18ac: 6c61 lui s8,0x18 + 18ae: 6769 lui a4,0x1a + 18b0: 656e .2byte 0x656e + 18b2: 0064 addi s1,sp,12 + 18b4: 6f4c .2byte 0x6f4c + 18b6: 6461 lui s0,0x18 + 18b8: 6120 .2byte 0x6120 + 18ba: 73656363 bltu a0,s6,1fe0 <__RODATA_END__+0x510> + 18be: 61662073 csrs 0x616,a2 + 18c2: 6c75 lui s8,0x1d + 18c4: 0074 addi a3,sp,12 + 18c6: 0000 unimp + 18c8: 726f7453 .4byte 0x726f7453 + 18cc: 2065 jal 1974 <__fini_array_end+0x254> + 18ce: 6461 lui s0,0x18 + 18d0: 7264 .2byte 0x7264 + 18d2: 7365 lui t1,0xffff9 + 18d4: 696d2073 csrs 0x696,s10 + 18d8: 696c6173 csrrsi sp,0x696,24 + 18dc: 64656e67 .4byte 0x64656e67 + 18e0: 0000 unimp + 18e2: 0000 unimp + 18e4: 726f7453 .4byte 0x726f7453 + 18e8: 2065 jal 1990 <__fini_array_end+0x270> + 18ea: 6361 lui t1,0x18 + 18ec: 73736563 bltu t1,s7,2016 <__neorv32_ram_size+0x16> + 18f0: 6620 .2byte 0x6620 + 18f2: 7561 lui a0,0xffff8 + 18f4: 746c .2byte 0x746c + 18f6: 0000 unimp + 18f8: 6e45 lui t3,0x11 + 18fa: 6976 .2byte 0x6976 + 18fc: 6f72 .2byte 0x6f72 + 18fe: 6d6e .2byte 0x6d6e + 1900: 6e65 lui t3,0x19 + 1902: 2074 .2byte 0x2074 + 1904: 6c6c6163 bltu s8,t1,1fc6 <__RODATA_END__+0x4f6> + 1908: 6620 .2byte 0x6620 + 190a: 6f72 .2byte 0x6f72 + 190c: 206d jal 19b6 <__fini_array_end+0x296> + 190e: 2d55 jal 1fc2 <__RODATA_END__+0x4f2> + 1910: 6f6d lui t5,0x1b + 1912: 6564 .2byte 0x6564 + 1914: 0000 unimp + 1916: 0000 unimp + 1918: 6e45 lui t3,0x11 + 191a: 6976 .2byte 0x6976 + 191c: 6f72 .2byte 0x6f72 + 191e: 6d6e .2byte 0x6d6e + 1920: 6e65 lui t3,0x19 + 1922: 2074 .2byte 0x2074 + 1924: 6c6c6163 bltu s8,t1,1fe6 <__RODATA_END__+0x516> + 1928: 6620 .2byte 0x6620 + 192a: 6f72 .2byte 0x6f72 + 192c: 206d jal 19d6 <__fini_array_end+0x2b6> + 192e: 2d4d jal 1fe0 <__RODATA_END__+0x510> + 1930: 6f6d lui t5,0x1b + 1932: 6564 .2byte 0x6564 + 1934: 0000 unimp + 1936: 0000 unimp + 1938: 614d addi sp,sp,176 + 193a: 6e696863 bltu s2,t1,202a <__neorv32_ram_size+0x2a> + 193e: 2065 jal 19e6 <__fini_array_end+0x2c6> + 1940: 74666f73 csrrsi t5,0x746,12 + 1944: 65726177 .4byte 0x65726177 + 1948: 4920 lw s0,80(a0) + 194a: 5152 lw sp,52(sp) + 194c: 0000 unimp + 194e: 0000 unimp + 1950: 614d addi sp,sp,176 + 1952: 6e696863 bltu s2,t1,2042 <__neorv32_ram_size+0x42> + 1956: 2065 jal 19fe <__fini_array_end+0x2de> + 1958: 6974 .2byte 0x6974 + 195a: 656d lui a0,0x1b + 195c: 2072 .2byte 0x2072 + 195e: 5249 li tp,-14 + 1960: 0051 c.nop 20 + 1962: 0000 unimp + 1964: 614d addi sp,sp,176 + 1966: 6e696863 bltu s2,t1,2056 <__neorv32_ram_size+0x56> + 196a: 2065 jal 1a12 <__fini_array_end+0x2f2> + 196c: 7865 lui a6,0xffff9 + 196e: 6574 .2byte 0x6574 + 1970: 6e72 .2byte 0x6e72 + 1972: 6c61 lui s8,0x18 + 1974: 4920 lw s0,80(a0) + 1976: 5152 lw sp,52(sp) + 1978: 0000 unimp + 197a: 0000 unimp + 197c: 6146 .2byte 0x6146 + 197e: 49207473 csrrci s0,0x492,0 + 1982: 5152 lw sp,52(sp) + 1984: 0020 addi s0,sp,8 + 1986: 0000 unimp + 1988: 6e55 lui t3,0x15 + 198a: 776f6e6b .4byte 0x776f6e6b + 198e: 206e .2byte 0x206e + 1990: 7274 .2byte 0x7274 + 1992: 7061 c.lui zero,0xffff8 + 1994: 6320 .2byte 0x6320 + 1996: 7561 lui a0,0xffff8 + 1998: 203a6573 csrrsi a0,0x203,20 + 199c: 0000 unimp + 199e: 0000 unimp + 19a0: 5b20 lw s0,112(a4) + 19a2: 4954 lw a3,20(a0) + 19a4: 454d li a0,19 + 19a6: 5f54554f .4byte 0x5f54554f + 19aa: 5245 li tp,-15 + 19ac: 5d52 lw s10,52(sp) + 19ae: 0000 unimp + 19b0: 5b20 lw s0,112(a4) + 19b2: 4544 lw s1,12(a0) + 19b4: 4956 lw s2,84(sp) + 19b6: 455f4543 .4byte 0x455f4543 + 19ba: 5252 lw tp,52(sp) + 19bc: 005d c.nop 23 + 19be: 0000 unimp + 19c0: 5b20 lw s0,112(a4) + 19c2: 4d50 lw a2,28(a0) + 19c4: 5f50 lw a2,60(a4) + 19c6: 5245 li tp,-15 + 19c8: 5d52 lw s10,52(sp) + 19ca: 0000 unimp + 19cc: 202c .2byte 0x202c + 19ce: 4e49 li t3,18 + 19d0: 003d5453 .4byte 0x3d5453 + 19d4: 3c20 .2byte 0x3c20 + 19d6: 4554522f .4byte 0x4554522f + 19da: 0a3e slli s4,s4,0xf + 19dc: 0000 unimp + 19de: 0000 unimp + 19e0: 202c .2byte 0x202c + 19e2: 4441 li s0,16 + 19e4: 5244 lw s1,36(a2) + 19e6: 003d c.nop 15 + 19e8: 0648 addi a0,sp,772 + 19ea: 0000 unimp + 19ec: 0678 addi a4,sp,780 + 19ee: 0000 unimp + 19f0: 06c0 addi s0,sp,836 + 19f2: 0000 unimp + 19f4: 0770 addi a2,sp,908 + 19f6: 0000 unimp + 19f8: 077c addi a5,sp,908 + 19fa: 0000 unimp + 19fc: 0788 addi a0,sp,960 + 19fe: 0000 unimp + 1a00: 0794 addi a3,sp,960 + 1a02: 0000 unimp + 1a04: 07a0 addi s0,sp,968 + 1a06: 0000 unimp + 1a08: 07ac addi a1,sp,968 + 1a0a: 0000 unimp + 1a0c: 05d8 addi a4,sp,708 + 1a0e: 0000 unimp + 1a10: 05d8 addi a4,sp,708 + 1a12: 0000 unimp + 1a14: 07b8 addi a4,sp,968 + 1a16: 0000 unimp + 1a18: 570a lw a4,160(sp) + 1a1a: 5241 li tp,-16 + 1a1c: 494e lw s2,208(sp) + 1a1e: 474e lw a4,208(sp) + 1a20: 2021 jal 1a28 <__fini_array_end+0x308> + 1a22: 495f5753 .4byte 0x495f5753 + 1a26: 28204153 .4byte 0x28204153 + 1a2a: 6566 .2byte 0x6566 + 1a2c: 7461 lui s0,0xffff8 + 1a2e: 7275 lui tp,0xffffd + 1a30: 7365 lui t1,0xffff9 + 1a32: 7220 .2byte 0x7220 + 1a34: 7165 addi sp,sp,-400 + 1a36: 6975 lui s2,0x1d + 1a38: 6572 .2byte 0x6572 + 1a3a: 2964 .2byte 0x2964 + 1a3c: 7620 .2byte 0x7620 + 1a3e: 57482073 csrs 0x574,a6 + 1a42: 495f 4153 2820 .byte 0x5f, 0x49, 0x53, 0x41, 0x20, 0x28 + 1a48: 6566 .2byte 0x6566 + 1a4a: 7461 lui s0,0xffff8 + 1a4c: 7275 lui tp,0xffffd + 1a4e: 7365 lui t1,0xffff9 + 1a50: 6120 .2byte 0x6120 + 1a52: 6176 .2byte 0x6176 + 1a54: 6c69 lui s8,0x1a + 1a56: 6261 lui tp,0x18 + 1a58: 656c .2byte 0x656c + 1a5a: 2029 jal 1a64 <__fini_array_end+0x344> + 1a5c: 696d lui s2,0x1b + 1a5e: 74616d73 csrrsi s10,0x746,2 + 1a62: 0a216863 bltu sp,sp,1b12 <__RODATA_END__+0x42> + 1a66: 495f5753 .4byte 0x495f5753 + 1a6a: 3d204153 .4byte 0x3d204153 + 1a6e: 3020 .2byte 0x3020 + 1a70: 2578 .2byte 0x2578 + 1a72: 2078 .2byte 0x2078 + 1a74: 6328 .2byte 0x6328 + 1a76: 69706d6f jal s10,890c <__neorv32_ram_size+0x690c> + 1a7a: 656c .2byte 0x656c + 1a7c: 2072 .2byte 0x2072 + 1a7e: 6c66 .2byte 0x6c66 + 1a80: 6761 lui a4,0x18 + 1a82: 480a2973 csrrs s2,0x480,s4 + 1a86: 53495f57 .4byte 0x53495f57 + 1a8a: 2041 jal 1b0a <__RODATA_END__+0x3a> + 1a8c: 203d jal 1aba + 1a8e: 7830 .2byte 0x7830 + 1a90: 7825 lui a6,0xfffe9 + 1a92: 2820 .2byte 0x2820 + 1a94: 696d lui s2,0x1b + 1a96: 63206173 csrrsi sp,0x632,0 + 1a9a: 0a297273 csrrci tp,0xa2,18 + 1a9e: 000a c.slli zero,0x2 + +00001aa0 : + 1aa0: 3130 .2byte 0x3130 + 1aa2: 3332 .2byte 0x3332 + 1aa4: 3534 .2byte 0x3534 + 1aa6: 3736 .2byte 0x3736 + 1aa8: 3938 .2byte 0x3938 + 1aaa: 4241 li tp,16 + 1aac: 46454443 .4byte 0x46454443 + +00001ab0 : + 1ab0: 3130 .2byte 0x3130 + 1ab2: 3332 .2byte 0x3332 + 1ab4: 3534 .2byte 0x3534 + 1ab6: 3736 .2byte 0x3736 + 1ab8: 3938 .2byte 0x3938 + 1aba: 6261 lui tp,0x18 + 1abc: 66656463 bltu a0,t1,2124 <__neorv32_ram_size+0x124> + 1ac0: 0000 unimp + ... + +00001ac4 : + 1ac4: 3130 .2byte 0x3130 + 1ac6: 3332 .2byte 0x3332 + 1ac8: 3534 .2byte 0x3534 + 1aca: 3736 .2byte 0x3736 + 1acc: 3938 .2byte 0x3938 + ... + +Disassembly of section .data: + +80000000 <__malloc_av_>: + ... +80000008: 0000 unimp +8000000a: 8000 .2byte 0x8000 +8000000c: 0000 unimp +8000000e: 8000 .2byte 0x8000 +80000010: 0008 .2byte 0x8 +80000012: 8000 .2byte 0x8000 +80000014: 0008 .2byte 0x8 +80000016: 8000 .2byte 0x8000 +80000018: 0010 .2byte 0x10 +8000001a: 8000 .2byte 0x8000 +8000001c: 0010 .2byte 0x10 +8000001e: 8000 .2byte 0x8000 +80000020: 0018 .2byte 0x18 +80000022: 8000 .2byte 0x8000 +80000024: 0018 .2byte 0x18 +80000026: 8000 .2byte 0x8000 +80000028: 0020 addi s0,sp,8 +8000002a: 8000 .2byte 0x8000 +8000002c: 0020 addi s0,sp,8 +8000002e: 8000 .2byte 0x8000 +80000030: 0028 addi a0,sp,8 +80000032: 8000 .2byte 0x8000 +80000034: 0028 addi a0,sp,8 +80000036: 8000 .2byte 0x8000 +80000038: 0030 addi a2,sp,8 +8000003a: 8000 .2byte 0x8000 +8000003c: 0030 addi a2,sp,8 +8000003e: 8000 .2byte 0x8000 +80000040: 0038 addi a4,sp,8 +80000042: 8000 .2byte 0x8000 +80000044: 0038 addi a4,sp,8 +80000046: 8000 .2byte 0x8000 +80000048: 0040 addi s0,sp,4 +8000004a: 8000 .2byte 0x8000 +8000004c: 0040 addi s0,sp,4 +8000004e: 8000 .2byte 0x8000 +80000050: 0048 addi a0,sp,4 +80000052: 8000 .2byte 0x8000 +80000054: 0048 addi a0,sp,4 +80000056: 8000 .2byte 0x8000 +80000058: 0050 addi a2,sp,4 +8000005a: 8000 .2byte 0x8000 +8000005c: 0050 addi a2,sp,4 +8000005e: 8000 .2byte 0x8000 +80000060: 0058 addi a4,sp,4 +80000062: 8000 .2byte 0x8000 +80000064: 0058 addi a4,sp,4 +80000066: 8000 .2byte 0x8000 +80000068: 0060 addi s0,sp,12 +8000006a: 8000 .2byte 0x8000 +8000006c: 0060 addi s0,sp,12 +8000006e: 8000 .2byte 0x8000 +80000070: 0068 addi a0,sp,12 +80000072: 8000 .2byte 0x8000 +80000074: 0068 addi a0,sp,12 +80000076: 8000 .2byte 0x8000 +80000078: 0070 addi a2,sp,12 +8000007a: 8000 .2byte 0x8000 +8000007c: 0070 addi a2,sp,12 +8000007e: 8000 .2byte 0x8000 +80000080: 0078 addi a4,sp,12 +80000082: 8000 .2byte 0x8000 +80000084: 0078 addi a4,sp,12 +80000086: 8000 .2byte 0x8000 +80000088: 0080 addi s0,sp,64 +8000008a: 8000 .2byte 0x8000 +8000008c: 0080 addi s0,sp,64 +8000008e: 8000 .2byte 0x8000 +80000090: 0088 addi a0,sp,64 +80000092: 8000 .2byte 0x8000 +80000094: 0088 addi a0,sp,64 +80000096: 8000 .2byte 0x8000 +80000098: 0090 addi a2,sp,64 +8000009a: 8000 .2byte 0x8000 +8000009c: 0090 addi a2,sp,64 +8000009e: 8000 .2byte 0x8000 +800000a0: 0098 addi a4,sp,64 +800000a2: 8000 .2byte 0x8000 +800000a4: 0098 addi a4,sp,64 +800000a6: 8000 .2byte 0x8000 +800000a8: 00a0 addi s0,sp,72 +800000aa: 8000 .2byte 0x8000 +800000ac: 00a0 addi s0,sp,72 +800000ae: 8000 .2byte 0x8000 +800000b0: 00a8 addi a0,sp,72 +800000b2: 8000 .2byte 0x8000 +800000b4: 00a8 addi a0,sp,72 +800000b6: 8000 .2byte 0x8000 +800000b8: 00b0 addi a2,sp,72 +800000ba: 8000 .2byte 0x8000 +800000bc: 00b0 addi a2,sp,72 +800000be: 8000 .2byte 0x8000 +800000c0: 00b8 addi a4,sp,72 +800000c2: 8000 .2byte 0x8000 +800000c4: 00b8 addi a4,sp,72 +800000c6: 8000 .2byte 0x8000 +800000c8: 00c0 addi s0,sp,68 +800000ca: 8000 .2byte 0x8000 +800000cc: 00c0 addi s0,sp,68 +800000ce: 8000 .2byte 0x8000 +800000d0: 00c8 addi a0,sp,68 +800000d2: 8000 .2byte 0x8000 +800000d4: 00c8 addi a0,sp,68 +800000d6: 8000 .2byte 0x8000 +800000d8: 00d0 addi a2,sp,68 +800000da: 8000 .2byte 0x8000 +800000dc: 00d0 addi a2,sp,68 +800000de: 8000 .2byte 0x8000 +800000e0: 00d8 addi a4,sp,68 +800000e2: 8000 .2byte 0x8000 +800000e4: 00d8 addi a4,sp,68 +800000e6: 8000 .2byte 0x8000 +800000e8: 00e0 addi s0,sp,76 +800000ea: 8000 .2byte 0x8000 +800000ec: 00e0 addi s0,sp,76 +800000ee: 8000 .2byte 0x8000 +800000f0: 00e8 addi a0,sp,76 +800000f2: 8000 .2byte 0x8000 +800000f4: 00e8 addi a0,sp,76 +800000f6: 8000 .2byte 0x8000 +800000f8: 00f0 addi a2,sp,76 +800000fa: 8000 .2byte 0x8000 +800000fc: 00f0 addi a2,sp,76 +800000fe: 8000 .2byte 0x8000 +80000100: 00f8 addi a4,sp,76 +80000102: 8000 .2byte 0x8000 +80000104: 00f8 addi a4,sp,76 +80000106: 8000 .2byte 0x8000 +80000108: 0100 addi s0,sp,128 +8000010a: 8000 .2byte 0x8000 +8000010c: 0100 addi s0,sp,128 +8000010e: 8000 .2byte 0x8000 +80000110: 0108 addi a0,sp,128 +80000112: 8000 .2byte 0x8000 +80000114: 0108 addi a0,sp,128 +80000116: 8000 .2byte 0x8000 +80000118: 0110 addi a2,sp,128 +8000011a: 8000 .2byte 0x8000 +8000011c: 0110 addi a2,sp,128 +8000011e: 8000 .2byte 0x8000 +80000120: 0118 addi a4,sp,128 +80000122: 8000 .2byte 0x8000 +80000124: 0118 addi a4,sp,128 +80000126: 8000 .2byte 0x8000 +80000128: 0120 addi s0,sp,136 +8000012a: 8000 .2byte 0x8000 +8000012c: 0120 addi s0,sp,136 +8000012e: 8000 .2byte 0x8000 +80000130: 0128 addi a0,sp,136 +80000132: 8000 .2byte 0x8000 +80000134: 0128 addi a0,sp,136 +80000136: 8000 .2byte 0x8000 +80000138: 0130 addi a2,sp,136 +8000013a: 8000 .2byte 0x8000 +8000013c: 0130 addi a2,sp,136 +8000013e: 8000 .2byte 0x8000 +80000140: 0138 addi a4,sp,136 +80000142: 8000 .2byte 0x8000 +80000144: 0138 addi a4,sp,136 +80000146: 8000 .2byte 0x8000 +80000148: 0140 addi s0,sp,132 +8000014a: 8000 .2byte 0x8000 +8000014c: 0140 addi s0,sp,132 +8000014e: 8000 .2byte 0x8000 +80000150: 0148 addi a0,sp,132 +80000152: 8000 .2byte 0x8000 +80000154: 0148 addi a0,sp,132 +80000156: 8000 .2byte 0x8000 +80000158: 0150 addi a2,sp,132 +8000015a: 8000 .2byte 0x8000 +8000015c: 0150 addi a2,sp,132 +8000015e: 8000 .2byte 0x8000 +80000160: 0158 addi a4,sp,132 +80000162: 8000 .2byte 0x8000 +80000164: 0158 addi a4,sp,132 +80000166: 8000 .2byte 0x8000 +80000168: 0160 addi s0,sp,140 +8000016a: 8000 .2byte 0x8000 +8000016c: 0160 addi s0,sp,140 +8000016e: 8000 .2byte 0x8000 +80000170: 0168 addi a0,sp,140 +80000172: 8000 .2byte 0x8000 +80000174: 0168 addi a0,sp,140 +80000176: 8000 .2byte 0x8000 +80000178: 0170 addi a2,sp,140 +8000017a: 8000 .2byte 0x8000 +8000017c: 0170 addi a2,sp,140 +8000017e: 8000 .2byte 0x8000 +80000180: 0178 addi a4,sp,140 +80000182: 8000 .2byte 0x8000 +80000184: 0178 addi a4,sp,140 +80000186: 8000 .2byte 0x8000 +80000188: 0180 addi s0,sp,192 +8000018a: 8000 .2byte 0x8000 +8000018c: 0180 addi s0,sp,192 +8000018e: 8000 .2byte 0x8000 +80000190: 0188 addi a0,sp,192 +80000192: 8000 .2byte 0x8000 +80000194: 0188 addi a0,sp,192 +80000196: 8000 .2byte 0x8000 +80000198: 0190 addi a2,sp,192 +8000019a: 8000 .2byte 0x8000 +8000019c: 0190 addi a2,sp,192 +8000019e: 8000 .2byte 0x8000 +800001a0: 0198 addi a4,sp,192 +800001a2: 8000 .2byte 0x8000 +800001a4: 0198 addi a4,sp,192 +800001a6: 8000 .2byte 0x8000 +800001a8: 01a0 addi s0,sp,200 +800001aa: 8000 .2byte 0x8000 +800001ac: 01a0 addi s0,sp,200 +800001ae: 8000 .2byte 0x8000 +800001b0: 01a8 addi a0,sp,200 +800001b2: 8000 .2byte 0x8000 +800001b4: 01a8 addi a0,sp,200 +800001b6: 8000 .2byte 0x8000 +800001b8: 01b0 addi a2,sp,200 +800001ba: 8000 .2byte 0x8000 +800001bc: 01b0 addi a2,sp,200 +800001be: 8000 .2byte 0x8000 +800001c0: 01b8 addi a4,sp,200 +800001c2: 8000 .2byte 0x8000 +800001c4: 01b8 addi a4,sp,200 +800001c6: 8000 .2byte 0x8000 +800001c8: 01c0 addi s0,sp,196 +800001ca: 8000 .2byte 0x8000 +800001cc: 01c0 addi s0,sp,196 +800001ce: 8000 .2byte 0x8000 +800001d0: 01c8 addi a0,sp,196 +800001d2: 8000 .2byte 0x8000 +800001d4: 01c8 addi a0,sp,196 +800001d6: 8000 .2byte 0x8000 +800001d8: 01d0 addi a2,sp,196 +800001da: 8000 .2byte 0x8000 +800001dc: 01d0 addi a2,sp,196 +800001de: 8000 .2byte 0x8000 +800001e0: 01d8 addi a4,sp,196 +800001e2: 8000 .2byte 0x8000 +800001e4: 01d8 addi a4,sp,196 +800001e6: 8000 .2byte 0x8000 +800001e8: 01e0 addi s0,sp,204 +800001ea: 8000 .2byte 0x8000 +800001ec: 01e0 addi s0,sp,204 +800001ee: 8000 .2byte 0x8000 +800001f0: 01e8 addi a0,sp,204 +800001f2: 8000 .2byte 0x8000 +800001f4: 01e8 addi a0,sp,204 +800001f6: 8000 .2byte 0x8000 +800001f8: 01f0 addi a2,sp,204 +800001fa: 8000 .2byte 0x8000 +800001fc: 01f0 addi a2,sp,204 +800001fe: 8000 .2byte 0x8000 +80000200: 01f8 addi a4,sp,204 +80000202: 8000 .2byte 0x8000 +80000204: 01f8 addi a4,sp,204 +80000206: 8000 .2byte 0x8000 +80000208: 0200 addi s0,sp,256 +8000020a: 8000 .2byte 0x8000 +8000020c: 0200 addi s0,sp,256 +8000020e: 8000 .2byte 0x8000 +80000210: 0208 addi a0,sp,256 +80000212: 8000 .2byte 0x8000 +80000214: 0208 addi a0,sp,256 +80000216: 8000 .2byte 0x8000 +80000218: 0210 addi a2,sp,256 +8000021a: 8000 .2byte 0x8000 +8000021c: 0210 addi a2,sp,256 +8000021e: 8000 .2byte 0x8000 +80000220: 0218 addi a4,sp,256 +80000222: 8000 .2byte 0x8000 +80000224: 0218 addi a4,sp,256 +80000226: 8000 .2byte 0x8000 +80000228: 0220 addi s0,sp,264 +8000022a: 8000 .2byte 0x8000 +8000022c: 0220 addi s0,sp,264 +8000022e: 8000 .2byte 0x8000 +80000230: 0228 addi a0,sp,264 +80000232: 8000 .2byte 0x8000 +80000234: 0228 addi a0,sp,264 +80000236: 8000 .2byte 0x8000 +80000238: 0230 addi a2,sp,264 +8000023a: 8000 .2byte 0x8000 +8000023c: 0230 addi a2,sp,264 +8000023e: 8000 .2byte 0x8000 +80000240: 0238 addi a4,sp,264 +80000242: 8000 .2byte 0x8000 +80000244: 0238 addi a4,sp,264 +80000246: 8000 .2byte 0x8000 +80000248: 0240 addi s0,sp,260 +8000024a: 8000 .2byte 0x8000 +8000024c: 0240 addi s0,sp,260 +8000024e: 8000 .2byte 0x8000 +80000250: 0248 addi a0,sp,260 +80000252: 8000 .2byte 0x8000 +80000254: 0248 addi a0,sp,260 +80000256: 8000 .2byte 0x8000 +80000258: 0250 addi a2,sp,260 +8000025a: 8000 .2byte 0x8000 +8000025c: 0250 addi a2,sp,260 +8000025e: 8000 .2byte 0x8000 +80000260: 0258 addi a4,sp,260 +80000262: 8000 .2byte 0x8000 +80000264: 0258 addi a4,sp,260 +80000266: 8000 .2byte 0x8000 +80000268: 0260 addi s0,sp,268 +8000026a: 8000 .2byte 0x8000 +8000026c: 0260 addi s0,sp,268 +8000026e: 8000 .2byte 0x8000 +80000270: 0268 addi a0,sp,268 +80000272: 8000 .2byte 0x8000 +80000274: 0268 addi a0,sp,268 +80000276: 8000 .2byte 0x8000 +80000278: 0270 addi a2,sp,268 +8000027a: 8000 .2byte 0x8000 +8000027c: 0270 addi a2,sp,268 +8000027e: 8000 .2byte 0x8000 +80000280: 0278 addi a4,sp,268 +80000282: 8000 .2byte 0x8000 +80000284: 0278 addi a4,sp,268 +80000286: 8000 .2byte 0x8000 +80000288: 0280 addi s0,sp,320 +8000028a: 8000 .2byte 0x8000 +8000028c: 0280 addi s0,sp,320 +8000028e: 8000 .2byte 0x8000 +80000290: 0288 addi a0,sp,320 +80000292: 8000 .2byte 0x8000 +80000294: 0288 addi a0,sp,320 +80000296: 8000 .2byte 0x8000 +80000298: 0290 addi a2,sp,320 +8000029a: 8000 .2byte 0x8000 +8000029c: 0290 addi a2,sp,320 +8000029e: 8000 .2byte 0x8000 +800002a0: 0298 addi a4,sp,320 +800002a2: 8000 .2byte 0x8000 +800002a4: 0298 addi a4,sp,320 +800002a6: 8000 .2byte 0x8000 +800002a8: 02a0 addi s0,sp,328 +800002aa: 8000 .2byte 0x8000 +800002ac: 02a0 addi s0,sp,328 +800002ae: 8000 .2byte 0x8000 +800002b0: 02a8 addi a0,sp,328 +800002b2: 8000 .2byte 0x8000 +800002b4: 02a8 addi a0,sp,328 +800002b6: 8000 .2byte 0x8000 +800002b8: 02b0 addi a2,sp,328 +800002ba: 8000 .2byte 0x8000 +800002bc: 02b0 addi a2,sp,328 +800002be: 8000 .2byte 0x8000 +800002c0: 02b8 addi a4,sp,328 +800002c2: 8000 .2byte 0x8000 +800002c4: 02b8 addi a4,sp,328 +800002c6: 8000 .2byte 0x8000 +800002c8: 02c0 addi s0,sp,324 +800002ca: 8000 .2byte 0x8000 +800002cc: 02c0 addi s0,sp,324 +800002ce: 8000 .2byte 0x8000 +800002d0: 02c8 addi a0,sp,324 +800002d2: 8000 .2byte 0x8000 +800002d4: 02c8 addi a0,sp,324 +800002d6: 8000 .2byte 0x8000 +800002d8: 02d0 addi a2,sp,324 +800002da: 8000 .2byte 0x8000 +800002dc: 02d0 addi a2,sp,324 +800002de: 8000 .2byte 0x8000 +800002e0: 02d8 addi a4,sp,324 +800002e2: 8000 .2byte 0x8000 +800002e4: 02d8 addi a4,sp,324 +800002e6: 8000 .2byte 0x8000 +800002e8: 02e0 addi s0,sp,332 +800002ea: 8000 .2byte 0x8000 +800002ec: 02e0 addi s0,sp,332 +800002ee: 8000 .2byte 0x8000 +800002f0: 02e8 addi a0,sp,332 +800002f2: 8000 .2byte 0x8000 +800002f4: 02e8 addi a0,sp,332 +800002f6: 8000 .2byte 0x8000 +800002f8: 02f0 addi a2,sp,332 +800002fa: 8000 .2byte 0x8000 +800002fc: 02f0 addi a2,sp,332 +800002fe: 8000 .2byte 0x8000 +80000300: 02f8 addi a4,sp,332 +80000302: 8000 .2byte 0x8000 +80000304: 02f8 addi a4,sp,332 +80000306: 8000 .2byte 0x8000 +80000308: 0300 addi s0,sp,384 +8000030a: 8000 .2byte 0x8000 +8000030c: 0300 addi s0,sp,384 +8000030e: 8000 .2byte 0x8000 +80000310: 0308 addi a0,sp,384 +80000312: 8000 .2byte 0x8000 +80000314: 0308 addi a0,sp,384 +80000316: 8000 .2byte 0x8000 +80000318: 0310 addi a2,sp,384 +8000031a: 8000 .2byte 0x8000 +8000031c: 0310 addi a2,sp,384 +8000031e: 8000 .2byte 0x8000 +80000320: 0318 addi a4,sp,384 +80000322: 8000 .2byte 0x8000 +80000324: 0318 addi a4,sp,384 +80000326: 8000 .2byte 0x8000 +80000328: 0320 addi s0,sp,392 +8000032a: 8000 .2byte 0x8000 +8000032c: 0320 addi s0,sp,392 +8000032e: 8000 .2byte 0x8000 +80000330: 0328 addi a0,sp,392 +80000332: 8000 .2byte 0x8000 +80000334: 0328 addi a0,sp,392 +80000336: 8000 .2byte 0x8000 +80000338: 0330 addi a2,sp,392 +8000033a: 8000 .2byte 0x8000 +8000033c: 0330 addi a2,sp,392 +8000033e: 8000 .2byte 0x8000 +80000340: 0338 addi a4,sp,392 +80000342: 8000 .2byte 0x8000 +80000344: 0338 addi a4,sp,392 +80000346: 8000 .2byte 0x8000 +80000348: 0340 addi s0,sp,388 +8000034a: 8000 .2byte 0x8000 +8000034c: 0340 addi s0,sp,388 +8000034e: 8000 .2byte 0x8000 +80000350: 0348 addi a0,sp,388 +80000352: 8000 .2byte 0x8000 +80000354: 0348 addi a0,sp,388 +80000356: 8000 .2byte 0x8000 +80000358: 0350 addi a2,sp,388 +8000035a: 8000 .2byte 0x8000 +8000035c: 0350 addi a2,sp,388 +8000035e: 8000 .2byte 0x8000 +80000360: 0358 addi a4,sp,388 +80000362: 8000 .2byte 0x8000 +80000364: 0358 addi a4,sp,388 +80000366: 8000 .2byte 0x8000 +80000368: 0360 addi s0,sp,396 +8000036a: 8000 .2byte 0x8000 +8000036c: 0360 addi s0,sp,396 +8000036e: 8000 .2byte 0x8000 +80000370: 0368 addi a0,sp,396 +80000372: 8000 .2byte 0x8000 +80000374: 0368 addi a0,sp,396 +80000376: 8000 .2byte 0x8000 +80000378: 0370 addi a2,sp,396 +8000037a: 8000 .2byte 0x8000 +8000037c: 0370 addi a2,sp,396 +8000037e: 8000 .2byte 0x8000 +80000380: 0378 addi a4,sp,396 +80000382: 8000 .2byte 0x8000 +80000384: 0378 addi a4,sp,396 +80000386: 8000 .2byte 0x8000 +80000388: 0380 addi s0,sp,448 +8000038a: 8000 .2byte 0x8000 +8000038c: 0380 addi s0,sp,448 +8000038e: 8000 .2byte 0x8000 +80000390: 0388 addi a0,sp,448 +80000392: 8000 .2byte 0x8000 +80000394: 0388 addi a0,sp,448 +80000396: 8000 .2byte 0x8000 +80000398: 0390 addi a2,sp,448 +8000039a: 8000 .2byte 0x8000 +8000039c: 0390 addi a2,sp,448 +8000039e: 8000 .2byte 0x8000 +800003a0: 0398 addi a4,sp,448 +800003a2: 8000 .2byte 0x8000 +800003a4: 0398 addi a4,sp,448 +800003a6: 8000 .2byte 0x8000 +800003a8: 03a0 addi s0,sp,456 +800003aa: 8000 .2byte 0x8000 +800003ac: 03a0 addi s0,sp,456 +800003ae: 8000 .2byte 0x8000 +800003b0: 03a8 addi a0,sp,456 +800003b2: 8000 .2byte 0x8000 +800003b4: 03a8 addi a0,sp,456 +800003b6: 8000 .2byte 0x8000 +800003b8: 03b0 addi a2,sp,456 +800003ba: 8000 .2byte 0x8000 +800003bc: 03b0 addi a2,sp,456 +800003be: 8000 .2byte 0x8000 +800003c0: 03b8 addi a4,sp,456 +800003c2: 8000 .2byte 0x8000 +800003c4: 03b8 addi a4,sp,456 +800003c6: 8000 .2byte 0x8000 +800003c8: 03c0 addi s0,sp,452 +800003ca: 8000 .2byte 0x8000 +800003cc: 03c0 addi s0,sp,452 +800003ce: 8000 .2byte 0x8000 +800003d0: 03c8 addi a0,sp,452 +800003d2: 8000 .2byte 0x8000 +800003d4: 03c8 addi a0,sp,452 +800003d6: 8000 .2byte 0x8000 +800003d8: 03d0 addi a2,sp,452 +800003da: 8000 .2byte 0x8000 +800003dc: 03d0 addi a2,sp,452 +800003de: 8000 .2byte 0x8000 +800003e0: 03d8 addi a4,sp,452 +800003e2: 8000 .2byte 0x8000 +800003e4: 03d8 addi a4,sp,452 +800003e6: 8000 .2byte 0x8000 +800003e8: 03e0 addi s0,sp,460 +800003ea: 8000 .2byte 0x8000 +800003ec: 03e0 addi s0,sp,460 +800003ee: 8000 .2byte 0x8000 +800003f0: 03e8 addi a0,sp,460 +800003f2: 8000 .2byte 0x8000 +800003f4: 03e8 addi a0,sp,460 +800003f6: 8000 .2byte 0x8000 +800003f8: 03f0 addi a2,sp,460 +800003fa: 8000 .2byte 0x8000 +800003fc: 03f0 addi a2,sp,460 +800003fe: 8000 .2byte 0x8000 +80000400: 03f8 addi a4,sp,460 +80000402: 8000 .2byte 0x8000 +80000404: 03f8 addi a4,sp,460 +80000406: 8000 .2byte 0x8000 + +80000408 : +80000408: 0000 unimp +8000040a: 0000 unimp +8000040c: 06f4 addi a3,sp,844 +8000040e: 8000 .2byte 0x8000 +80000410: 075c addi a5,sp,900 +80000412: 8000 .2byte 0x8000 +80000414: 07c4 addi s1,sp,964 +80000416: 8000 .2byte 0x8000 + ... +800004b0: 0001 nop +800004b2: 0000 unimp +800004b4: 0000 unimp +800004b6: 0000 unimp +800004b8: 330e .2byte 0x330e +800004ba: abcd j 80000aac <__BSS_END__+0x1c0> +800004bc: 1234 addi a3,sp,296 +800004be: e66d bnez a2,800005a8 +800004c0: deec sw a1,124(a3) +800004c2: 0005 c.nop 1 +800004c4: 0000000b .4byte 0xb + ... + +80000830 : +80000830: 08ec addi a1,sp,92 +80000832: 8000 .2byte 0x8000 + +80000834 <__malloc_sbrk_base>: +80000834: ffff .2byte 0xffff +80000836: ffff .2byte 0xffff + +80000838 <__malloc_trim_threshold>: +80000838: 0000 unimp +8000083a: 0002 c.slli64 zero + +8000083c <_impure_ptr>: +8000083c: 0408 addi a0,sp,512 +8000083e: 8000 .2byte 0x8000 + +Disassembly of section .bss: + +80000840 <__malloc_max_total_mem>: +80000840: 0000 unimp + ... + +80000844 <__malloc_max_sbrked_mem>: +80000844: 0000 unimp + ... + +80000848 <__malloc_top_pad>: +80000848: 0000 unimp + ... + +8000084c : +8000084c: 0000 unimp + ... + +80000850 <__neorv32_rte_vector_lut>: + ... + +800008c4 <__malloc_current_mallinfo>: + ... + +Disassembly of section .comment: + +00000000 <.comment>: + 0: 3a434347 .4byte 0x3a434347 + 4: 2820 .2byte 0x2820 + 6: 65653267 .4byte 0x65653267 + a: 6535 lui a0,0xd + c: 3334 .2byte 0x3334 + e: 3030 .2byte 0x3030 + 10: 3831 jal fffff82c <__crt0_stack_begin+0x7fffd830> + 12: 2029 jal 1c + 14: 3231 jal fffff920 <__crt0_stack_begin+0x7fffd924> + 16: 322e .2byte 0x322e + 18: 302e .2byte 0x302e + 1a: 4700 lw s0,8(a4) + 1c: 203a4343 .4byte 0x203a4343 + 20: 4728 lw a0,72(a4) + 22: 554e lw a0,240(sp) + 24: 2029 jal 2e + 26: 3231 jal fffff932 <__crt0_stack_begin+0x7fffd936> + 28: 322e .2byte 0x322e + 2a: 302e .2byte 0x302e + ... + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2941 jal 490 <__neorv32_rte_core+0x1e4> + 2: 0000 unimp + 4: 7200 .2byte 0x7200 + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <__crt0_pointer_init> + c: 001f 0000 1004 .byte 0x1f, 0x00, 0x00, 0x00, 0x04, 0x10 + 12: 7205 lui tp,0xfffe1 + 14: 3376 .2byte 0x3376 + 16: 6932 .2byte 0x6932 + 18: 7032 .2byte 0x7032 + 1a: 5f30 lw a2,120(a4) + 1c: 326d jal fffff9c6 <__crt0_stack_begin+0x7fffd9ca> + 1e: 3070 .2byte 0x3070 + 20: 635f 7032 0030 .byte 0x5f, 0x63, 0x32, 0x70, 0x30, 0x00 + 26: 0108 addi a0,sp,128 + 28: 0b0a slli s6,s6,0x2 + +Disassembly of section .debug_aranges: + +00000000 <.debug_aranges>: + 0: 0024 addi s1,sp,8 + 2: 0000 unimp + 4: 0002 c.slli64 zero + 6: 0000 unimp + 8: 0000 unimp + a: 0004 .2byte 0x4 + c: 0000 unimp + e: 0000 unimp + 10: 0278 addi a4,sp,268 + 12: 0000 unimp + 14: 0020 addi s0,sp,8 + 16: 0000 unimp + 18: 0188 addi a0,sp,192 + 1a: 0000 unimp + 1c: 00f0 addi a2,sp,76 + ... + 26: 0000 unimp + 28: 003c addi a5,sp,8 + 2a: 0000 unimp + 2c: 0002 c.slli64 zero + 2e: 03d8 addi a4,sp,452 + 30: 0000 unimp + 32: 0004 .2byte 0x4 + ... + 48: 0298 addi a4,sp,320 + 4a: 0000 unimp + 4c: 0014 .2byte 0x14 + ... + 66: 0000 unimp + 68: 008c addi a1,sp,64 + 6a: 0000 unimp + 6c: 0002 c.slli64 zero + 6e: 074c addi a1,sp,900 + 70: 0000 unimp + 72: 0004 .2byte 0x4 + 74: 0000 unimp + 76: 0000 unimp + 78: 02ac addi a1,sp,328 + 7a: 0000 unimp + 7c: 0248 addi a0,sp,260 + 7e: 0000 unimp + 80: 04f4 addi a3,sp,588 + 82: 0000 unimp + 84: 0070 addi a2,sp,12 + ... + 96: 0000 unimp + 98: 0564 addi s1,sp,652 + 9a: 0000 unimp + 9c: 02d8 addi a4,sp,324 + ... + a6: 0000 unimp + a8: 083c addi a5,sp,24 + aa: 0000 unimp + ac: 0030 addi a2,sp,8 + ae: 0000 unimp + b0: 086c addi a1,sp,28 + b2: 0000 unimp + b4: 0058 addi a4,sp,4 + ... + e6: 0000 unimp + e8: 08c4 addi s1,sp,84 + ea: 0000 unimp + ec: 0064 addi s1,sp,12 + ... + f6: 0000 unimp + f8: 010c addi a1,sp,128 + fa: 0000 unimp + fc: 0002 c.slli64 zero + fe: 281c .2byte 0x281c + 100: 0000 unimp + 102: 0004 .2byte 0x4 + 104: 0000 unimp + 106: 0000 unimp + 108: 0928 addi a0,sp,152 + 10a: 0000 unimp + 10c: 0108 addi a0,sp,128 + 10e: 0000 unimp + 110: 0a30 addi a2,sp,280 + 112: 0000 unimp + 114: 003c addi a5,sp,8 + 116: 0000 unimp + 118: 0a6c addi a1,sp,284 + 11a: 0000 unimp + 11c: 002c addi a1,sp,8 + 11e: 0000 unimp + 120: 0a98 addi a4,sp,336 + 122: 0000 unimp + 124: 0010 .2byte 0x10 + 126: 0000 unimp + 128: 0aa8 addi a0,sp,344 + 12a: 0000 unimp + 12c: 00ac addi a1,sp,72 + ... + 13e: 0000 unimp + 140: 0b54 addi a3,sp,404 + 142: 0000 unimp + 144: 0018 .2byte 0x18 + ... + 17e: 0000 unimp + 180: 0b6c addi a1,sp,412 + 182: 0000 unimp + 184: 0058 addi a4,sp,4 + 186: 0000 unimp + 188: 0bc4 addi s1,sp,468 + 18a: 0000 unimp + 18c: 01d8 addi a4,sp,196 + ... + 206: 0000 unimp + 208: 0124 addi s1,sp,136 + 20a: 0000 unimp + 20c: 0002 c.slli64 zero + 20e: 3558 .2byte 0x3558 + 210: 0000 unimp + 212: 0004 .2byte 0x4 + ... + 320: 0d9c addi a5,sp,720 + 322: 0000 unimp + 324: 0038 addi a4,sp,8 + ... + 32e: 0000 unimp + 330: 001c .2byte 0x1c + 332: 0000 unimp + 334: 0002 c.slli64 zero + 336: 4120 lw s0,64(a0) + 338: 0000 unimp + 33a: 0004 .2byte 0x4 + ... + 344: 0188 addi a0,sp,192 + ... + 34e: 0000 unimp + 350: 001c .2byte 0x1c + 352: 0000 unimp + 354: 0002 c.slli64 zero + 356: 4145 li sp,17 + 358: 0000 unimp + 35a: 0004 .2byte 0x4 + 35c: 0000 unimp + 35e: 0000 unimp + 360: 0dd4 addi a3,sp,724 + 362: 0000 unimp + 364: 007c addi a5,sp,12 + ... + +Disassembly of section .debug_info: + +00000000 <.debug_info>: + 0: 03d4 addi a3,sp,452 + 2: 0000 unimp + 4: 0005 c.nop 1 + 6: 0401 addi s0,s0,0 # ffff8000 <__crt0_stack_begin+0x7fff6004> + 8: 0000 unimp + a: 0000 unimp + c: 1d14 addi a3,sp,688 + e: 0001 nop + 10: 1d00 addi s0,sp,688 + 12: 0000 unimp + 14: 0000 unimp + 16: 00000007 .4byte 0x7 + 1a: 0045 c.nop 17 + ... + 24: 0000 unimp + 26: 0102 c.slli64 sp + 28: e906 .2byte 0xe906 + 2a: 0000 unimp + 2c: 0300 addi s0,sp,384 + 2e: 0000 unimp + 30: 0000 unimp + 32: 2b02 .2byte 0x2b02 + 34: 3918 .2byte 0x3918 + 36: 0000 unimp + 38: 0200 addi s0,sp,256 + 3a: 0801 addi a6,a6,0 # fffe9000 <__crt0_stack_begin+0x7ffe7004> + 3c: 000000e7 jalr zero # 0 <__crt0_entry> + 40: 0202 c.slli64 tp + 42: 2805 jal 72 + 44: 0002 c.slli64 zero + 46: 0200 addi s0,sp,256 + 48: 0702 c.slli64 a4 + 4a: 003a c.slli zero,0xe + 4c: 0000 unimp + 4e: 0402 c.slli64 s0 + 50: ff05 bnez a4,ffffff88 <__crt0_stack_begin+0x7fffdf8c> + 52: 0001 nop + 54: 0300 addi s0,sp,384 + 56: 00000197 auipc gp,0x0 + 5a: 4f02 lw t5,0(sp) + 5c: 6119 addi sp,sp,384 + 5e: 0000 unimp + 60: 0200 addi s0,sp,256 + 62: 0704 addi s1,sp,896 + 64: 000000bb .4byte 0xbb + 68: 0802 c.slli64 a6 + 6a: fa05 bnez a2,ffffff9a <__crt0_stack_begin+0x7fffdf9e> + 6c: 0001 nop + 6e: 0300 addi s0,sp,384 + 70: 023e slli tp,tp,0xf + 72: 0000 unimp + 74: 6902 .2byte 0x6902 + 76: 7b19 lui s6,0xfffe6 + 78: 0000 unimp + 7a: 0200 addi s0,sp,256 + 7c: 0708 addi a0,sp,896 + 7e: 00b6 slli ra,ra,0xd + 80: 0000 unimp + 82: 0415 addi s0,s0,5 + 84: 6905 lui s2,0x1 + 86: 746e .2byte 0x746e + 88: 0200 addi s0,sp,256 + 8a: 0704 addi s1,sp,896 + 8c: 00c0 addi s0,sp,68 + 8e: 0000 unimp + 90: 00000203 lb tp,0(zero) # 0 <__crt0_entry> + 94: 0300 addi s0,sp,384 + 96: 1318 addi a4,sp,416 + 98: 002d c.nop 11 + 9a: 0000 unimp + 9c: 00019903 lh s2,0(gp) # 56 + a0: 0300 addi s0,sp,384 + a2: 1430 addi a2,sp,552 + a4: 0055 c.nop 21 + a6: 0000 unimp + a8: 9c0d .2byte 0x9c0d + aa: 0000 unimp + ac: 0300 addi s0,sp,384 + ae: 0240 addi s0,sp,260 + b0: 0000 unimp + b2: 6f143c03 .4byte 0x6f143c03 + b6: 0000 unimp + b8: 0300 addi s0,sp,384 + ba: 26f6 .2byte 0x26f6 + bc: 0000 unimp + be: d604 sw s1,40(a2) + c0: 00008917 auipc s2,0x8 + c4: 0200 addi s0,sp,256 + c6: 0410 addi a2,sp,512 + c8: 025d addi tp,tp,23 # fffe1017 <__crt0_stack_begin+0x7ffdf01b> + ca: 0000 unimp + cc: 0416 slli s0,s0,0x5 + ce: 0102 c.slli64 sp + d0: f008 .2byte 0xf008 + d2: 0000 unimp + d4: 0d00 addi s0,sp,656 + d6: 00ce slli ra,ra,0x13 + d8: 0000 unimp + da: d50e sw gp,168(sp) + dc: 0000 unimp + de: 0f00 addi s0,sp,912 + e0: 000001ab .4byte 0x1ab + e4: 0089 addi ra,ra,2 + e6: 0000 unimp + e8: 0441 addi s0,s0,16 + ea: 0101 addi sp,sp,0 + ec: 0000 unimp + ee: 8004 .2byte 0x8004 + f0: 0002 c.slli64 zero + f2: 0000 unimp + f4: 1c04 addi s1,sp,560 + f6: 0002 c.slli64 zero + f8: 0200 addi s0,sp,256 + fa: ef04 .2byte 0xef04 + fc: 0001 nop + fe: 0300 addi s0,sp,384 + 100: 0f00 addi s0,sp,912 + 102: 000a c.slli zero,0x2 + 104: 0000 unimp + 106: 0089 addi ra,ra,2 + 108: 0000 unimp + 10a: 0448 addi a0,sp,516 + 10c: 0129 addi sp,sp,10 + 10e: 0000 unimp + 110: 6c04 .2byte 0x6c04 + 112: 0000 unimp + 114: 0000 unimp + 116: de04 sw s1,56(a2) + 118: 0001 nop + 11a: 0100 addi s0,sp,128 + 11c: 2904 .2byte 0x2904 + 11e: 0000 unimp + 120: 0200 addi s0,sp,256 + 122: 0804 addi s1,sp,16 + 124: 0002 c.slli64 zero + 126: 0300 addi s0,sp,384 + 128: 1700 addi s0,sp,928 + 12a: 0420 addi s0,sp,520 + 12c: 4405 li s0,1 + 12e: 0905 addi s2,s2,1 # 80c1 <__neorv32_ram_size+0x60c1> + 130: 0195 addi gp,gp,5 # 80001045 <__global_pointer$+0x5> + 132: 0000 unimp + 134: 4310 lw a2,0(a4) + 136: 4b4c lw a1,20(a4) + 138: 4500 lw s0,8(a0) + 13a: a805 j 16a <__crt0_trap_handler+0x2e> + 13c: 0000 unimp + 13e: 0000 unimp + 140: 8406 mv s0,ra + 142: 0000 unimp + 144: 4600 lw s0,8(a2) + 146: a805 j 176 <__crt0_trap_handler+0x3a> + 148: 0000 unimp + 14a: 0400 addi s0,sp,512 + 14c: 5310 lw a2,32(a4) + 14e: 4700434f .4byte 0x4700434f + 152: a805 j 182 <__crt0_trap_handler_end+0xa> + 154: 0000 unimp + 156: 0800 addi s0,sp,16 + 158: bd06 .2byte 0xbd06 + 15a: 48000003 lb zero,1152(zero) # 480 <__neorv32_rte_core+0x1d4> + 15e: a805 j 18e + 160: 0000 unimp + 162: 0c00 addi s0,sp,528 + 164: 3206 .2byte 0x3206 + 166: 0002 c.slli64 zero + 168: 4900 lw s0,16(a0) + 16a: a805 j 19a + 16c: 0000 unimp + 16e: 1000 addi s0,sp,32 + 170: aa06 .2byte 0xaa06 + 172: 0000 unimp + 174: 4a00 lw s0,16(a2) + 176: a805 j 1a6 + 178: 0000 unimp + 17a: 1400 addi s0,sp,544 + 17c: 4d06 lw s10,64(sp) + 17e: 0000 unimp + 180: 4b00 lw s0,16(a4) + 182: a805 j 1b2 + 184: 0000 unimp + 186: 1800 addi s0,sp,48 + 188: 8e06 mv t3,ra + 18a: 0000 unimp + 18c: 4c00 lw s0,24(s0) + 18e: a805 j 1be + 190: 0000 unimp + 192: 1c00 addi s0,sp,560 + 194: 1800 addi s0,sp,48 + 196: 0098 addi a4,sp,64 + 198: 0000 unimp + 19a: 4d05 li s10,1 + 19c: 0305 addi t1,t1,1 # ffffa001 <__crt0_stack_begin+0x7fff8005> + 19e: 0129 addi sp,sp,10 + 1a0: 0000 unimp + 1a2: 1904 addi s1,sp,176 + 1a4: 0269 addi tp,tp,26 # 1a + 1a6: 0000 unimp + 1a8: 3109 jal fffffdaa <__crt0_stack_begin+0x7fffddae> + 1aa: ad0a .2byte 0xad0a + 1ac: 0000 unimp + 1ae: 1100 addi s0,sp,160 + 1b0: 028c addi a1,sp,320 + 1b2: 0000 unimp + 1b4: cc076c07 .4byte 0xcc076c07 + 1b8: 0000 unimp + 1ba: c500 sw s0,8(a0) + 1bc: 0001 nop + 1be: 0500 addi s0,sp,640 + 1c0: 00b9 addi ra,ra,14 + 1c2: 0000 unimp + 1c4: 0b00 addi s0,sp,400 + 1c6: 00000057 .4byte 0x57 + 1ca: 0001d63f 00da0500 .8byte 0xda05000001d63f + 1d2: 0000 unimp + 1d4: 001a c.slli zero,0x6 + 1d6: 0000cd0b .4byte 0xcd0b + 1da: 3e00 .2byte 0x3e00 + 1dc: 01e6 slli gp,gp,0x19 + 1de: 0000 unimp + 1e0: da05 beqz a2,110 <__crt0_call_destructors+0xc> + 1e2: 0000 unimp + 1e4: 0000 unimp + 1e6: 0711 addi a4,a4,4 # 18004 <__neorv32_ram_size+0x16004> + 1e8: 0001 nop + 1ea: 0800 addi s0,sp,16 + 1ec: 00820a63 beq tp,s0,200 + 1f0: 0000 unimp + 1f2: 01fc addi a5,sp,204 + 1f4: 0000 unimp + 1f6: 8205 srli a2,a2,0x1 + 1f8: 0000 unimp + 1fa: 0000 unimp + 1fc: 0002490b .4byte 0x2490b + 200: 3500 .2byte 0x3500 + 202: 0216 slli tp,tp,0x5 + 204: 0000 unimp + 206: 9c05 .2byte 0x9c05 + 208: 0000 unimp + 20a: 0500 addi s0,sp,640 + 20c: 0090 addi a2,sp,64 + 20e: 0000 unimp + 210: 9005 srli s0,s0,0x21 + 212: 0000 unimp + 214: 0000 unimp + 216: 0000f51b .4byte 0xf51b + 21a: 0800 addi s0,sp,16 + 21c: 0658 addi a4,sp,772 + 21e: c41c sw a5,8(s0) + 220: 0001 nop + 222: 0100 addi s0,sp,128 + 224: 00820543 .4byte 0x820543 + 228: 0000 unimp + 22a: 0188 addi a0,sp,192 + 22c: 0000 unimp + 22e: 00f0 addi a2,sp,76 + 230: 0000 unimp + 232: 9c01 .2byte 0x9c01 + 234: 0000038b .4byte 0x38b + 238: c908 sw a0,16(a0) + 23a: 0001 nop + 23c: 4400 lw s0,8(s0) + 23e: 4e08 lw a0,24(a2) + 240: 0000 unimp + 242: 0c00 addi s0,sp,528 + 244: 0000 unimp + 246: 0800 addi s0,sp,16 + 248: 01a2 slli gp,gp,0x8 + 24a: 0000 unimp + 24c: 1444 addi s1,sp,548 + 24e: 004e c.slli zero,0x13 + 250: 0000 unimp + 252: 0018 .2byte 0x18 + 254: 0000 unimp + 256: d408 sw a0,40(s0) + 258: 0001 nop + 25a: 4400 lw s0,8(s0) + 25c: 4e1e lw t3,196(sp) + 25e: 0000 unimp + 260: 2400 .2byte 0x2400 + 262: 0000 unimp + 264: 0800 addi s0,sp,16 + 266: 007e c.slli zero,0x1f + 268: 0000 unimp + 26a: 0c45 addi s8,s8,17 # 1a011 <__neorv32_ram_size+0x18011> + 26c: 009c addi a5,sp,64 + 26e: 0000 unimp + 270: 0040 addi s0,sp,4 + 272: 0000 unimp + 274: 7909 lui s2,0xfffe2 + 276: 5400 lw s0,40(s0) + 278: 8b0d andi a4,a4,3 + 27a: 64000003 lb zero,1600(zero) # 640 <__neorv32_rte_debug_handler+0xdc> + 27e: 0000 unimp + 280: 1200 addi s0,sp,288 + 282: 001f 0000 02f9 .byte 0x1f, 0x00, 0x00, 0x00, 0xf9, 0x02 + 288: 0000 unimp + 28a: 6909 lui s2,0x2 + 28c: 5500 lw s0,40(a0) + 28e: 9c10 .2byte 0x9c10 + 290: 0000 unimp + 292: 7b00 .2byte 0x7b00 + 294: 0000 unimp + 296: 1200 addi s0,sp,288 + 298: 0032 c.slli zero,0xc + 29a: 0000 unimp + 29c: 02c4 addi s1,sp,324 + 29e: 0000 unimp + 2a0: 6a09 lui s4,0x2 + 2a2: 5a00 lw s0,48(a2) + 2a4: 9c12 add s8,s8,tp + 2a6: 0000 unimp + 2a8: 8800 .2byte 0x8800 + 2aa: 0000 unimp + 2ac: 0c00 addi s0,sp,528 + 2ae: 0218 addi a4,sp,256 + 2b0: 0000 unimp + 2b2: 0390 addi a2,sp,448 + 2b4: 0000 unimp + 2b6: 0101 addi sp,sp,0 + 2b8: 025a slli tp,tp,0x16 + 2ba: 0078 addi a4,sp,12 + 2bc: 0101 addi sp,sp,0 + 2be: 0082025b .4byte 0x82025b + 2c2: 0000 unimp + 2c4: 000a c.slli zero,0x2 + 2c6: 0002 c.slli64 zero + 2c8: a300 .2byte 0xa300 + 2ca: 0001 nop + 2cc: 0a00 addi s0,sp,272 + 2ce: 0220 addi s0,sp,264 + 2d0: 0000 unimp + 2d2: 000001a3 sb zero,3(zero) # 3 + 2d6: 2c0a .2byte 0x2c0a + 2d8: 0002 c.slli64 zero + 2da: ce00 sw s0,24(a2) + 2dc: 0c000003 lb zero,192(zero) # c0 <__crt0_clear_bss_loop+0x4> + 2e0: 0240 addi s0,sp,260 + 2e2: 0000 unimp + 2e4: 01c5 addi gp,gp,17 # 80001051 <__global_pointer$+0x11> + 2e6: 0000 unimp + 2e8: 0101 addi sp,sp,0 + 2ea: 055a slli a0,a0,0x16 + 2ec: 00175803 lhu a6,1(a4) + 2f0: 0100 addi s0,sp,128 + 2f2: 5b01 li s6,-32 + 2f4: 7802 .2byte 0x7802 + 2f6: 0040 addi s0,sp,4 + 2f8: 0a00 addi s0,sp,272 + 2fa: 01ac addi a1,sp,200 + 2fc: 0000 unimp + 2fe: 0216 slli tp,tp,0x5 + 300: 0000 unimp + 302: 0001c007 .4byte 0x1c007 + 306: fc00 .2byte 0xfc00 + 308: 0001 nop + 30a: 2100 .2byte 0x2100 + 30c: 01000003 lb zero,16(zero) # 10 + 310: 5a01 li s4,-32 + 312: 4b000a03 lb s4,1200(zero) # 4b0 <__neorv32_rte_core+0x204> + 316: 0101 addi sp,sp,0 + 318: 0130015b .4byte 0x130015b + 31c: 5c01 li s8,-32 + 31e: 3001 jal fffffb1e <__crt0_stack_begin+0x7fffdb22> + 320: 0700 addi s0,sp,896 + 322: 01c8 addi a0,sp,196 + 324: 0000 unimp + 326: 01e6 slli gp,gp,0x19 + 328: 0000 unimp + 32a: 0334 addi a3,sp,392 + 32c: 0000 unimp + 32e: 0101 addi sp,sp,0 + 330: 015a slli sp,sp,0x16 + 332: 0030 addi a2,sp,8 + 334: 0001d407 .4byte 0x1d407 + 338: d600 sw s0,40(a2) + 33a: 0001 nop + 33c: 4b00 lw s0,16(a4) + 33e: 01000003 lb zero,16(zero) # 10 + 342: 5a01 li s4,-32 + 344: 0305 addi t1,t1,1 + 346: 1720 addi s0,sp,936 + 348: 0000 unimp + 34a: 0700 addi s0,sp,896 + 34c: 01e4 addi s1,sp,204 + 34e: 0000 unimp + 350: 01c5 addi gp,gp,17 # 80001051 <__global_pointer$+0x11> + 352: 0000 unimp + 354: 0362 slli t1,t1,0x18 + 356: 0000 unimp + 358: 0101 addi sp,sp,0 + 35a: 055a slli a0,a0,0x16 + 35c: 00174403 lbu s0,1(a4) + 360: 0000 unimp + 362: 0001ec07 .4byte 0x1ec07 + 366: af00 .2byte 0xaf00 + 368: 0001 nop + 36a: 7700 .2byte 0x7700 + 36c: 01000003 lb zero,16(zero) # 10 + 370: 5a01 li s4,-32 + 372: 243e4003 lbu zero,579(t3) # 15243 <__neorv32_ram_size+0x13243> + 376: 0c00 addi s0,sp,528 + 378: 0250 addi a2,sp,260 + 37a: 0000 unimp + 37c: 01d6 slli gp,gp,0x15 + 37e: 0000 unimp + 380: 0101 addi sp,sp,0 + 382: 055a slli a0,a0,0x16 + 384: 00178003 lb zero,1(a5) + 388: 0000 unimp + 38a: 0e00 addi s0,sp,784 + 38c: 009c addi a5,sp,64 + 38e: 0000 unimp + 390: e01d bnez s0,3b6 <__neorv32_rte_core+0x10a> + 392: 0000 unimp + 394: 0100 addi s0,sp,128 + 396: 0635 addi a2,a2,13 + 398: 0278 addi a4,sp,268 + 39a: 0000 unimp + 39c: 0020 addi s0,sp,8 + 39e: 0000 unimp + 3a0: 9c01 .2byte 0x9c01 + 3a2: 03ce slli t2,t2,0x13 + 3a4: 0000 unimp + 3a6: 16004e13 xori t3,zero,352 + 3aa: 009c addi a5,sp,64 + 3ac: 0000 unimp + 3ae: 5a01 li s4,-32 + 3b0: 23007913 andi s2,zero,560 + 3b4: 0000038b .4byte 0x38b + 3b8: 5b01 li s6,-32 + 3ba: 0c1e slli s8,s8,0x7 + 3bc: 0000 unimp + 3be: 0900 addi s0,sp,144 + 3c0: 0069 c.nop 26 + 3c2: 1036 c.slli zero,0x2d + 3c4: 009c addi a5,sp,64 + 3c6: 0000 unimp + 3c8: 000000b3 add ra,zero,zero + 3cc: 0000 unimp + 3ce: 2f1f 0029 2f00 .byte 0x1f, 0x2f, 0x29, 0x00, 0x00, 0x2f + 3d4: 0029 c.nop 10 + 3d6: 0000 unimp + 3d8: 0370 addi a2,sp,396 + 3da: 0000 unimp + 3dc: 0005 c.nop 1 + 3de: 0401 addi s0,s0,0 + 3e0: 000001cf .4byte 0x1cf + 3e4: 00011d0f .4byte 0x11d0f + 3e8: 1d00 addi s0,sp,688 + 3ea: 0171 addi sp,sp,28 + 3ec: 0000 unimp + 3ee: 0198 addi a4,sp,192 + 3f0: 0000 unimp + 3f2: 0064 addi s1,sp,12 + 3f4: 0000 unimp + 3f6: 0000 unimp + 3f8: 0000 unimp + 3fa: 0270 addi a2,sp,268 + 3fc: 0000 unimp + 3fe: 0102 c.slli64 sp + 400: e906 .2byte 0xe906 + 402: 0000 unimp + 404: 0200 addi s0,sp,256 + 406: 0801 addi a6,a6,0 + 408: 000000e7 jalr zero # 0 <__crt0_entry> + 40c: 0202 c.slli64 tp + 40e: 2805 jal 43e <__neorv32_rte_core+0x192> + 410: 0002 c.slli64 zero + 412: 0200 addi s0,sp,256 + 414: 0702 c.slli64 a4 + 416: 003a c.slli zero,0xe + 418: 0000 unimp + 41a: 0402 c.slli64 s0 + 41c: ff05 bnez a4,354 <__neorv32_rte_core+0xa8> + 41e: 0001 nop + 420: 0500 addi s0,sp,640 + 422: 00000197 auipc gp,0x0 + 426: 4f02 lw t5,0(sp) + 428: 5519 li a0,-26 + 42a: 0000 unimp + 42c: 0200 addi s0,sp,256 + 42e: 0704 addi s1,sp,896 + 430: 000000bb .4byte 0xbb + 434: 0802 c.slli64 a6 + 436: fa05 bnez a2,366 <__neorv32_rte_core+0xba> + 438: 0001 nop + 43a: 0500 addi s0,sp,640 + 43c: 023e slli tp,tp,0xf + 43e: 0000 unimp + 440: 6902 .2byte 0x6902 + 442: 6f19 lui t5,0x6 + 444: 0000 unimp + 446: 0200 addi s0,sp,256 + 448: 0708 addi a0,sp,896 + 44a: 00b6 slli ra,ra,0xd + 44c: 0000 unimp + 44e: 0410 addi a2,sp,512 + 450: 6905 lui s2,0x1 + 452: 746e .2byte 0x746e + 454: 0200 addi s0,sp,256 + 456: 0704 addi s1,sp,896 + 458: 00c0 addi s0,sp,68 + 45a: 0000 unimp + 45c: 9905 andi a0,a0,-31 + 45e: 0001 nop + 460: 0300 addi s0,sp,384 + 462: 1430 addi a2,sp,552 + 464: 0049 c.nop 18 + 466: 0000 unimp + 468: 8411 srai s0,s0,0x4 + 46a: 0000 unimp + 46c: 0500 addi s0,sp,640 + 46e: 0240 addi s0,sp,260 + 470: 0000 unimp + 472: 63143c03 .4byte 0x63143c03 + 476: 0000 unimp + 478: 0200 addi s0,sp,256 + 47a: 0410 addi a2,sp,512 + 47c: 025d addi tp,tp,23 # 17 + 47e: 0000 unimp + 480: 0102 c.slli64 sp + 482: f008 .2byte 0xf008 + 484: 0000 unimp + 486: 0900 addi s0,sp,144 + 488: f110 .2byte 0xf110 + 48a: 0000ec03 .4byte 0xec03 + 48e: 0300 addi s0,sp,384 + 490: 02c6 slli t0,t0,0x11 + 492: 0000 unimp + 494: 03f2 slli t2,t2,0x1c + 496: 840c .2byte 0x840c + 498: 0000 unimp + 49a: 0000 unimp + 49c: 00055303 lhu t1,0(a0) # d000 <__neorv32_ram_size+0xb000> + 4a0: f300 .2byte 0xf300 + 4a2: 00840c03 lb s8,8(s0) + 4a6: 0000 unimp + 4a8: 0304 addi s1,sp,384 + 4aa: 0535 addi a0,a0,13 + 4ac: 0000 unimp + 4ae: 03f4 addi a3,sp,460 + 4b0: 840c .2byte 0x840c + 4b2: 0000 unimp + 4b4: 0800 addi s0,sp,16 + 4b6: 0004da03 lhu s4,0(s1) + 4ba: f500 .2byte 0xf500 + 4bc: 00840c03 lb s8,8(s0) + 4c0: 0000 unimp + 4c2: 000c .2byte 0xc + 4c4: 7c0a .2byte 0x7c0a + 4c6: f6000003 lb zero,-160(zero) # ffffff60 <__crt0_stack_begin+0x7fffdf64> + 4ca: 0000af03 lw t5,0(ra) + 4ce: 0900 addi s0,sp,144 + 4d0: 4420 lw s0,72(s0) + 4d2: 6605 lui a2,0x1 + 4d4: 0001 nop + 4d6: 0b00 addi s0,sp,400 + 4d8: 004b4c43 .4byte 0x4b4c43 + 4dc: 0545 addi a0,a0,17 + 4de: 0090 addi a2,sp,64 + 4e0: 0000 unimp + 4e2: 0300 addi s0,sp,384 + 4e4: 0084 addi s1,sp,64 + 4e6: 0000 unimp + 4e8: 0546 slli a0,a0,0x11 + 4ea: 9012 c.add zero,tp + 4ec: 0000 unimp + 4ee: 0400 addi s0,sp,512 + 4f0: 434f530b .4byte 0x434f530b + 4f4: 4700 lw s0,8(a4) + 4f6: 9005 srli s0,s0,0x21 + 4f8: 0000 unimp + 4fa: 0800 addi s0,sp,16 + 4fc: 0003bd03 .4byte 0x3bd03 + 500: 4800 lw s0,16(s0) + 502: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 504: 0090 addi a2,sp,64 + 506: 0000 unimp + 508: 030c addi a1,sp,384 + 50a: 0232 slli tp,tp,0xc + 50c: 0000 unimp + 50e: 0549 addi a0,a0,18 + 510: 9012 c.add zero,tp + 512: 0000 unimp + 514: 1000 addi s0,sp,32 + 516: 0000aa03 lw s4,0(ra) + 51a: 4a00 lw s0,16(a2) + 51c: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 51e: 0090 addi a2,sp,64 + 520: 0000 unimp + 522: 0314 addi a3,sp,384 + 524: 004d c.nop 19 + 526: 0000 unimp + 528: 9012054b .4byte 0x9012054b + 52c: 0000 unimp + 52e: 1800 addi s0,sp,48 + 530: 00008e03 lb t3,0(ra) + 534: 4c00 lw s0,24(s0) + 536: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 538: 0090 addi a2,sp,64 + 53a: 0000 unimp + 53c: 001c .2byte 0x1c + 53e: 980a add a6,a6,sp + 540: 0000 unimp + 542: 4d00 lw s0,24(a0) + 544: f705 bnez a4,46c <__neorv32_rte_core+0x1c0> + 546: 0000 unimp + 548: 1200 addi s0,sp,288 + 54a: 02ad addi t0,t0,11 + 54c: 0000 unimp + 54e: 007d0407 .4byte 0x7d0407 + 552: 0000 unimp + 554: 5604 lw s1,40(a2) + 556: 0605 addi a2,a2,1 # 1001 <_malloc_r+0x1a3> + 558: 0215 addi tp,tp,5 # 5 + 55a: 0000 unimp + 55c: 3401 jal ffffff5c <__crt0_stack_begin+0x7fffdf60> + 55e: 0004 .2byte 0x4 + 560: 0000 unimp + 562: fa01 bnez a2,472 <__neorv32_rte_core+0x1c6> + 564: 0004 .2byte 0x4 + 566: 0100 addi s0,sp,128 + 568: ce01 beqz a2,580 <__neorv32_rte_debug_handler+0x1c> + 56a: 0002 c.slli64 zero + 56c: 0200 addi s0,sp,256 + 56e: e701 bnez a4,576 <__neorv32_rte_debug_handler+0x12> + 570: 0002 c.slli64 zero + 572: 0300 addi s0,sp,384 + 574: 7f01 lui t5,0xfffe0 + 576: 0004 .2byte 0x4 + 578: 0400 addi s0,sp,512 + 57a: b001 j fffffd7a <__crt0_stack_begin+0x7fffdd7e> + 57c: 05000003 lb zero,80(zero) # 50 + 580: 1501 addi a0,a0,-32 + 582: 0d000003 lb zero,208(zero) # d0 <__crt0_call_constructors+0x4> + 586: a001 j 586 <__neorv32_rte_debug_handler+0x22> + 588: 0e000003 lb zero,224(zero) # e0 <__crt0_call_constructors_loop+0x4> + 58c: 2101 jal 98c <__neorv32_uart_itoa+0x64> + 58e: 0005 c.nop 1 + 590: 1000 addi s0,sp,32 + 592: 0001 nop + 594: 11000003 lb zero,272(zero) # 110 <__crt0_call_destructors+0xc> + 598: b001 j fffffd98 <__crt0_stack_begin+0x7fffdd9c> + 59a: 0004 .2byte 0x4 + 59c: 1200 addi s0,sp,288 + 59e: 4b01 li s6,0 + 5a0: 0004 .2byte 0x4 + 5a2: 1300 addi s0,sp,416 + 5a4: c301 beqz a4,5a4 <__neorv32_rte_debug_handler+0x40> + 5a6: 14000003 lb zero,320(zero) # 140 <__crt0_trap_handler+0x4> + 5aa: 3f01 jal 4ba <__neorv32_rte_core+0x20e> + 5ac: 15000003 lb zero,336(zero) # 150 <__crt0_trap_handler+0x14> + 5b0: 4001 c.li zero,0 + 5b2: 0005 c.nop 1 + 5b4: 1600 addi s0,sp,800 + 5b6: 0e01 addi t3,t3,0 + 5b8: 0005 c.nop 1 + 5ba: 1700 addi s0,sp,928 + 5bc: 8c01 sub s0,s0,s0 + 5be: 18000003 lb zero,384(zero) # 180 <__crt0_trap_handler_end+0x8> + 5c2: 0401 addi s0,s0,0 + 5c4: 0004 .2byte 0x4 + 5c6: 1900 addi s0,sp,176 + 5c8: c501 beqz a0,5d0 <__neorv32_rte_debug_handler+0x6c> + 5ca: 0004 .2byte 0x4 + 5cc: 1a00 addi s0,sp,304 + 5ce: d601 beqz a2,4d6 <__neorv32_rte_core+0x22a> + 5d0: 1b000003 lb zero,432(zero) # 1b0 + 5d4: 1901 addi s2,s2,-32 # fe0 <_malloc_r+0x182> + 5d6: 0004 .2byte 0x4 + 5d8: 1c00 addi s0,sp,560 + 5da: e501 bnez a0,5e2 <__neorv32_rte_debug_handler+0x7e> + 5dc: 0004 .2byte 0x4 + 5de: 1d00 addi s0,sp,688 + 5e0: 5201 li tp,-32 + 5e2: 1e000003 lb zero,480(zero) # 1e0 + 5e6: 6501 .2byte 0x6501 + 5e8: 1f000003 lb zero,496(zero) # 1f0 + 5ec: 0c00 addi s0,sp,528 + 5ee: 0465 addi s0,s0,25 + 5f0: 0000 unimp + 5f2: 9594 .2byte 0x9594 + ... + 5fc: 0000 unimp + 5fe: 0100 addi s0,sp,128 + 600: 539c lw a5,32(a5) + 602: 0002 c.slli64 zero + 604: 0600 addi s0,sp,768 + 606: 4896 lw a7,68(sp) + 608: 0002 c.slli64 zero + 60a: 0400 addi s0,sp,512 + 60c: 042d addi s0,s0,11 + 60e: 0000 unimp + 610: 00009597 auipc a1,0x9 + 614: 0400 addi s0,sp,512 + 616: 04a9 addi s1,s1,10 + 618: 0000 unimp + 61a: 5398 lw a4,32(a5) + 61c: 0002 c.slli64 zero + 61e: 0000 unimp + 620: 00045e07 .4byte 0x45e07 + 624: 9900 .2byte 0x9900 + 626: 022d addi tp,tp,11 # b + 628: 0000 unimp + 62a: 1300 addi s0,sp,416 + 62c: 0084 addi s1,sp,64 + 62e: 0000 unimp + 630: 00000263 beqz zero,634 <__neorv32_rte_debug_handler+0xd0> + 634: 7d14 .2byte 0x7d14 + 636: 0000 unimp + 638: 0100 addi s0,sp,128 + 63a: 0d00 addi s0,sp,656 + 63c: 00000293 li t0,0 + 640: 007e c.slli zero,0x1f + 642: 0000 unimp + 644: 0000 unimp + 646: 0000 unimp + 648: 0100 addi s0,sp,128 + 64a: af9c .2byte 0xaf9c + 64c: 0002 c.slli64 zero + 64e: 0e00 addi s0,sp,784 + 650: 00000477 .4byte 0x477 + 654: 297e .2byte 0x297e + 656: 0095 addi ra,ra,5 + 658: 0000 unimp + 65a: 5a06 lw s4,96(sp) + 65c: 935b0493 addi s1,s6,-1739 # fffe5935 <__crt0_stack_begin+0x7ffe3939> + 660: 0604 addi s1,sp,768 + 662: a480 .2byte 0xa480 + 664: 0002 c.slli64 zero + 666: 0400 addi s0,sp,512 + 668: 042d addi s0,s0,11 + 66a: 0000 unimp + 66c: 9581 srai a1,a1,0x20 + 66e: 0000 unimp + 670: 0400 addi s0,sp,512 + 672: 04a9 addi s1,s1,10 + 674: 0000 unimp + 676: 5382 lw t2,32(sp) + 678: 0002 c.slli64 zero + 67a: 0000 unimp + 67c: 00045e07 .4byte 0x45e07 + 680: 8300 .2byte 0x8300 + 682: 0289 addi t0,t0,2 + 684: 0000 unimp + 686: 0c00 addi s0,sp,528 + 688: 0269 addi tp,tp,26 # 1a + 68a: 0000 unimp + 68c: 955e add a0,a0,s7 + 68e: 0000 unimp + 690: 9800 .2byte 0x9800 + 692: 0002 c.slli64 zero + 694: 1400 addi s0,sp,544 + 696: 0000 unimp + 698: 0100 addi s0,sp,128 + 69a: 119c addi a5,sp,224 + 69c: 06000003 lb zero,96(zero) # 60 + 6a0: e260 .2byte 0xe260 + 6a2: 0002 c.slli64 zero + 6a4: 0400 addi s0,sp,512 + 6a6: 042d addi s0,s0,11 + 6a8: 0000 unimp + 6aa: 9561 srai a0,a0,0x38 + 6ac: 0000 unimp + 6ae: 0400 addi s0,sp,512 + 6b0: 04a9 addi s1,s1,10 + 6b2: 0000 unimp + 6b4: 5362 lw t1,56(sp) + 6b6: 0002 c.slli64 zero + 6b8: 0000 unimp + 6ba: 00045e07 .4byte 0x45e07 + 6be: 6300 .2byte 0x6300 + 6c0: 000002c7 .4byte 0x2c7 + 6c4: 9a08 .2byte 0x9a08 + 6c6: 0004 .2byte 0x4 + 6c8: 0c00 addi s0,sp,528 + 6ca: 0084 addi s1,sp,64 + 6cc: 0000 unimp + 6ce: 5b01 li s6,-32 + 6d0: 9f08 .2byte 0x9f08 + 6d2: 0004 .2byte 0x4 + 6d4: 1200 addi s0,sp,288 + 6d6: 0084 addi s1,sp,64 + 6d8: 0000 unimp + 6da: 5a01 li s4,-32 + 6dc: a408 .2byte 0xa408 + 6de: 0004 .2byte 0x4 + 6e0: 1800 addi s0,sp,48 + 6e2: 0084 addi s1,sp,64 + 6e4: 0000 unimp + 6e6: 5f01 li t5,-32 + 6e8: 0d00 addi s0,sp,656 + 6ea: 0328 addi a0,sp,392 + 6ec: 0000 unimp + 6ee: 0046 c.slli zero,0x11 + 6f0: 0000 unimp + 6f2: 0000 unimp + 6f4: 0000 unimp + 6f6: 0100 addi s0,sp,128 + 6f8: 5d9c lw a5,56(a1) + 6fa: 0e000003 lb zero,224(zero) # e0 <__crt0_call_constructors_loop+0x4> + 6fe: 0000027b .4byte 0x27b + 702: 2646 .2byte 0x2646 + 704: 0095 addi ra,ra,5 + 706: 0000 unimp + 708: 5a06 lw s4,96(sp) + 70a: 935b0493 addi s1,s6,-1739 + 70e: 0604 addi s1,sp,768 + 710: 5248 lw a0,36(a2) + 712: 04000003 lb zero,64(zero) # 40 + 716: 042d addi s0,s0,11 + 718: 0000 unimp + 71a: 9549 srai a0,a0,0x32 + 71c: 0000 unimp + 71e: 0400 addi s0,sp,512 + 720: 04a9 addi s1,s1,10 + 722: 0000 unimp + 724: 534a lw t1,176(sp) + 726: 0002 c.slli64 zero + 728: 0000 unimp + 72a: 00045e07 .4byte 0x45e07 + 72e: 4b00 lw s0,16(a4) + 730: 00000337 lui t1,0x0 + 734: 1500 addi s0,sp,672 + 736: 03ec addi a1,sp,460 + 738: 0000 unimp + 73a: 3401 jal 13a <__crt0_main_aftermath_end+0x6> + 73c: 7605 lui a2,0xfffe1 + ... + 746: 0000 unimp + 748: 0100 addi s0,sp,128 + 74a: 009c addi a5,sp,64 + 74c: 20cc .2byte 0x20cc + 74e: 0000 unimp + 750: 0005 c.nop 1 + 752: 0401 addi s0,s0,0 + 754: 0000033f 00011d35 .8byte 0x11d350000033f + 75c: 1d00 addi s0,sp,688 + 75e: 020a slli tp,tp,0x2 + 760: 0000 unimp + 762: 0198 addi a4,sp,192 + 764: 0000 unimp + 766: 01e4 addi s1,sp,204 + 768: 0000 unimp + 76a: 0000 unimp + 76c: 0000 unimp + 76e: 049e slli s1,s1,0x7 + 770: 0000 unimp + 772: 010a slli sp,sp,0x2 + 774: e906 .2byte 0xe906 + 776: 0000 unimp + 778: 0b00 addi s0,sp,400 + 77a: 0000 unimp + 77c: 0000 unimp + 77e: 39182b03 lw s6,913(a6) + 782: 0000 unimp + 784: 0a00 addi s0,sp,272 + 786: 0801 addi a6,a6,0 + 788: 000000e7 jalr zero # 0 <__crt0_entry> + 78c: 0018240b .4byte 0x18240b + 790: 0300 addi s0,sp,384 + 792: 004c1837 lui a6,0x4c1 + 796: 0000 unimp + 798: 020a slli tp,tp,0x2 + 79a: 2805 jal 7ca <__neorv32_rte_debug_handler+0x266> + 79c: 0002 c.slli64 zero + 79e: 0b00 addi s0,sp,400 + 7a0: 0dcc addi a1,sp,724 + 7a2: 0000 unimp + 7a4: 5f193903 .4byte 0x5f193903 + 7a8: 0000 unimp + 7aa: 0a00 addi s0,sp,272 + 7ac: 0702 c.slli64 a4 + 7ae: 003a c.slli zero,0xe + 7b0: 0000 unimp + 7b2: 001db30b .4byte 0x1db30b + 7b6: 0300 addi s0,sp,384 + 7b8: 184d addi a6,a6,-13 # 4c0ff3 <__neorv32_ram_size+0x4beff3> + 7ba: 0072 c.slli zero,0x1c + 7bc: 0000 unimp + 7be: 040a slli s0,s0,0x2 + 7c0: ff05 bnez a4,6f8 <__neorv32_rte_debug_handler+0x194> + 7c2: 0001 nop + 7c4: 0b00 addi s0,sp,400 + 7c6: 00000197 auipc gp,0x0 + 7ca: 85194f03 lbu t5,-1967(s2) + 7ce: 0000 unimp + 7d0: 0a00 addi s0,sp,272 + 7d2: 0704 addi s1,sp,896 + 7d4: 000000bb .4byte 0xbb + 7d8: 080a slli a6,a6,0x2 + 7da: fa05 bnez a2,70a <__neorv32_rte_debug_handler+0x1a6> + 7dc: 0001 nop + 7de: 0a00 addi s0,sp,272 + 7e0: 0708 addi a0,sp,896 + 7e2: 00b6 slli ra,ra,0xd + 7e4: 0000 unimp + 7e6: 0436 slli s0,s0,0xd + 7e8: 6905 lui s2,0x1 + 7ea: 746e .2byte 0x746e + 7ec: 1600 addi s0,sp,800 + 7ee: 009a slli ra,ra,0x6 + 7f0: 0000 unimp + 7f2: 040a slli s0,s0,0x2 + 7f4: 0000c007 .4byte 0xc007 + 7f8: 0b00 addi s0,sp,400 + 7fa: 0002 c.slli64 zero + 7fc: 0000 unimp + 7fe: 1804 addi s1,sp,48 + 800: 00002d13 slti s10,zero,0 + 804: 0b00 addi s0,sp,400 + 806: 1826 slli a6,a6,0x29 + 808: 0000 unimp + 80a: 2004 .2byte 0x2004 + 80c: 00004013 xori zero,zero,0 + 810: 0b00 addi s0,sp,400 + 812: 0dce slli s11,s11,0x13 + 814: 0000 unimp + 816: 2404 .2byte 0x2404 + 818: 5314 lw a3,32(a4) + 81a: 0000 unimp + 81c: 1600 addi s0,sp,800 + 81e: 00c5 addi ra,ra,17 + 820: 0000 unimp + 822: 001db50b .4byte 0x1db50b + 826: 0400 addi s0,sp,512 + 828: 132c addi a1,sp,424 + 82a: 0066 c.slli zero,0x19 + 82c: 0000 unimp + 82e: 0001990b .4byte 0x1990b + 832: 0400 addi s0,sp,512 + 834: 1430 addi a2,sp,552 + 836: 0079 c.nop 30 + 838: 0000 unimp + 83a: e216 .2byte 0xe216 + 83c: 0000 unimp + 83e: 0a00 addi s0,sp,272 + 840: 0410 addi a2,sp,512 + 842: 025d addi tp,tp,23 # 17 + 844: 0000 unimp + 846: 010a slli sp,sp,0x2 + 848: f008 .2byte 0xf008 + 84a: 0000 unimp + 84c: 1600 addi s0,sp,800 + 84e: 00fa slli ra,ra,0x1e + 850: 0000 unimp + 852: 0b25 addi s6,s6,9 + 854: 0001 nop + 856: 3700 .2byte 0x3700 + 858: 0125 addi sp,sp,9 + 85a: 0001 nop + 85c: 2600 .2byte 0x2600 + 85e: 0fc5 addi t6,t6,17 + 860: 0000 unimp + 862: 00a6 slli ra,ra,0x9 + 864: 0000 unimp + 866: 3e05 jal 396 <__neorv32_rte_core+0xea> + 868: 000006c7 .4byte 0x6c7 + 86c: c402 sw zero,8(sp) + 86e: 0014 .2byte 0x14 + 870: 0100 addi s0,sp,128 + 872: 5002 .2byte 0x5002 + 874: 0006 c.slli zero,0x1 + 876: 0200 addi s0,sp,256 + 878: f002 .2byte 0xf002 + 87a: 0009 c.nop 2 + 87c: 0300 addi s0,sp,384 + 87e: bf01 j 78e <__neorv32_rte_debug_handler+0x22a> + 880: 0019 c.nop 6 + 882: 0000 unimp + 884: 1a4c0103 lb sp,420(s8) + 888: 0000 unimp + 88a: 0301 addi t1,t1,0 # 0 <__crt0_entry> + 88c: e001 bnez s0,88c + 88e: 000a c.slli zero,0x2 + 890: 0400 addi s0,sp,512 + 892: 0d0b0103 lb sp,208(s6) + 896: 0000 unimp + 898: 0305 addi t1,t1,1 + 89a: fe01 bnez a2,7b2 <__neorv32_rte_debug_handler+0x24e> + 89c: 000e c.slli zero,0x3 + 89e: 0600 addi s0,sp,768 + 8a0: 0c0d0103 lb sp,192(s10) # 190c0 <__neorv32_ram_size+0x170c0> + 8a4: 0000 unimp + 8a6: 030a slli t1,t1,0x2 + 8a8: e201 bnez a2,8a8 + 8aa: 0005 c.nop 1 + 8ac: 1000 addi s0,sp,32 + 8ae: 0ffd0103 lb sp,255(s10) + 8b2: 0000 unimp + 8b4: 031a slli t1,t1,0x6 + 8b6: 8201 c.srli64 a2 + 8b8: 001d c.nop 7 + 8ba: 2000 .2byte 0x2000 + 8bc: 13620103 lb sp,310(tp) # 136 <__crt0_main_aftermath_end+0x2> + 8c0: 0000 unimp + 8c2: 71010323 sb a6,1798(sp) + 8c6: 24000013 li zero,576 + 8ca: 13800103 lb sp,312(zero) # 138 <__crt0_main_aftermath_end+0x4> + 8ce: 0000 unimp + 8d0: 0325 addi t1,t1,9 + 8d2: 8f01 sub a4,a4,s0 + 8d4: 26000013 li zero,608 + 8d8: 139e0103 lb sp,313(t3) + 8dc: 0000 unimp + 8de: ad010327 .4byte 0xad010327 + 8e2: 28000013 li zero,640 + 8e6: 13bc0103 lb sp,315(s8) + 8ea: 0000 unimp + 8ec: 0329 addi t1,t1,10 + 8ee: 6301 .2byte 0x6301 + 8f0: 0010 .2byte 0x10 + 8f2: 2a00 .2byte 0x2a00 + 8f4: 10730103 lb sp,263(t1) + 8f8: 0000 unimp + 8fa: 8301032b .4byte 0x8301032b + 8fe: 0010 .2byte 0x10 + 900: 2c00 .2byte 0x2c00 + 902: 10930103 lb sp,265(t1) + 906: 0000 unimp + 908: 032d addi t1,t1,11 + 90a: a301 j e0a <__umodsi3+0x2> + 90c: 0010 .2byte 0x10 + 90e: 2e00 .2byte 0x2e00 + 910: 10b30103 lb sp,267(t1) + 914: 0000 unimp + 916: c301032f .4byte 0xc301032f + 91a: 0010 .2byte 0x10 + 91c: 3000 .2byte 0x3000 + 91e: 10d30103 lb sp,269(t1) + 922: 0000 unimp + 924: 0331 addi t1,t1,12 + 926: e301 bnez a4,926 + 928: 0010 .2byte 0x10 + 92a: 3200 .2byte 0x3200 + 92c: 10f30103 lb sp,271(t1) + 930: 0000 unimp + 932: 70010333 .4byte 0x70010333 + 936: 0011 c.nop 4 + 938: 3400 .2byte 0x3400 + 93a: 11800103 lb sp,280(zero) # 118 <__crt0_call_destructors_loop+0x4> + 93e: 0000 unimp + 940: 0335 addi t1,t1,13 + 942: 9001 srli s0,s0,0x20 + 944: 0011 c.nop 4 + 946: 3600 .2byte 0x3600 + 948: 11a00103 lb sp,282(zero) # 11a <__crt0_call_destructors_loop+0x6> + 94c: 0000 unimp + 94e: b0010337 lui t1,0xb0010 + 952: 0011 c.nop 4 + 954: 3800 .2byte 0x3800 + 956: 11c00103 lb sp,284(zero) # 11c <__crt0_call_destructors_loop+0x8> + 95a: 0000 unimp + 95c: 0339 addi t1,t1,14 # b001000e <__crt0_stack_begin+0x3000e012> + 95e: d001 beqz s0,85e + 960: 0011 c.nop 4 + 962: 3a00 .2byte 0x3a00 + 964: 11e00103 lb sp,286(zero) # 11e <__crt0_call_destructors_loop+0xa> + 968: 0000 unimp + 96a: f001033b .4byte 0xf001033b + 96e: 0011 c.nop 4 + 970: 3c00 .2byte 0x3c00 + 972: 12000103 lb sp,288(zero) # 120 <__crt0_call_destructors_loop+0xc> + 976: 0000 unimp + 978: 033d addi t1,t1,15 + 97a: dd01 beqz a0,892 + 97c: 0012 c.slli zero,0x4 + 97e: 3e00 .2byte 0x3e00 + 980: 12ed0103 lb sp,302(s10) + 984: 0000 unimp + 986: 3301033f 40000016 .8byte 0x400000163301033f + 98e: 1daa0103 lb sp,474(s4) # 21da <__neorv32_ram_size+0x1da> + 992: 0000 unimp + 994: 0341 addi t1,t1,16 + 996: 7801 lui a6,0xfffe0 + 998: 4200001b .4byte 0x4200001b + 99c: 09e60103 lb sp,158(a2) # fffe109e <__crt0_stack_begin+0x7ffdf0a2> + 9a0: 0000 unimp + 9a2: e8010343 .4byte 0xe8010343 + 9a6: 000a c.slli zero,0x2 + 9a8: 4400 lw s0,8(s0) + 9aa: 1dcb0103 lb sp,476(s6) + 9ae: 0000 unimp + 9b0: 03a0 addi s0,sp,456 + 9b2: d701 beqz a4,8ba + 9b4: 001d c.nop 7 + 9b6: a100 .2byte 0xa100 + 9b8: 1de30103 lb sp,478(t1) + 9bc: 0000 unimp + 9be: 03a2 slli t2,t2,0x8 + 9c0: ef01 bnez a4,9d8 <__neorv32_uart_itoa+0xb0> + 9c2: 001d c.nop 7 + 9c4: a300 .2byte 0xa300 + 9c6: 1e0e0103 lb sp,480(t3) + 9ca: 0000 unimp + 9cc: 03b0 addi a2,sp,456 + 9ce: 1b01 addi s6,s6,-32 + 9d0: 001e c.slli zero,0x7 + 9d2: b100 .2byte 0xb100 + 9d4: 1e280103 lb sp,482(a6) # fffe01e2 <__crt0_stack_begin+0x7ffde1e6> + 9d8: 0000 unimp + 9da: 03b2 slli t2,t2,0xc + 9dc: 3501 jal 7dc <__neorv32_rte_debug_handler+0x278> + 9de: 001e c.slli zero,0x7 + 9e0: b300 .2byte 0xb300 + 9e2: 1e420103 lb sp,484(tp) # 1e4 + 9e6: 0000 unimp + 9e8: 03b4 addi a3,sp,456 + 9ea: 4f01 li t5,0 + 9ec: 001e c.slli zero,0x7 + 9ee: b500 .2byte 0xb500 + 9f0: 1e5c0103 lb sp,485(s8) + 9f4: 0000 unimp + 9f6: 03b6 slli t2,t2,0xd + 9f8: 6901 .2byte 0x6901 + 9fa: 001e c.slli zero,0x7 + 9fc: b700 .2byte 0xb700 + 9fe: 1e760103 lb sp,487(a2) + a02: 0000 unimp + a04: 03b8 addi a4,sp,456 + a06: 1501 addi a0,a0,-32 + a08: 000d c.nop 3 + a0a: b900 .2byte 0xb900 + a0c: 0bc70103 lb sp,188(a4) + a10: 0000 unimp + a12: 03ba slli t2,t2,0xe + a14: d501 beqz a0,91c + a16: bb00000b .4byte 0xbb00000b + a1a: 0be30103 lb sp,190(t1) + a1e: 0000 unimp + a20: 03bc addi a5,sp,456 + a22: f101 bnez a0,922 + a24: bd00000b .4byte 0xbd00000b + a28: 0bff0103 lb sp,191(t5) # fffe00bf <__crt0_stack_begin+0x7ffde0c3> + a2c: 0000 unimp + a2e: 03be slli t2,t2,0xf + a30: 0d01 addi s10,s10,0 + a32: 0014 .2byte 0x14 + a34: bf00 .2byte 0xbf00 + a36: 11580103 lb sp,277(a6) + a3a: 0000 unimp + a3c: 07a0 addi s0,sp,968 + a3e: 4101 li sp,0 + a40: 0018 .2byte 0x18 + a42: a100 .2byte 0xa100 + a44: 1b830107 .4byte 0x1b830107 + a48: 0000 unimp + a4a: 07a2 slli a5,a5,0x8 + a4c: 8e01 sub a2,a2,s0 + a4e: a300001b .4byte 0xa300001b + a52: 06010107 .4byte 0x6010107 + a56: 0000 unimp + a58: 07a4 addi s1,sp,968 + a5a: 2601 jal d5a + a5c: 000c .2byte 0xc + a5e: a500 .2byte 0xa500 + a60: 095d0107 .4byte 0x95d0107 + a64: 0000 unimp + a66: 07a8 addi a0,sp,968 + a68: ee01 bnez a2,a80 <__neorv32_uart_touppercase.constprop.0+0x14> + a6a: 000c .2byte 0xc + a6c: aa00 .2byte 0xaa00 + a6e: 09990107 .4byte 0x9990107 + a72: 0000 unimp + a74: 07b0 addi a2,sp,968 + a76: d001 beqz s0,976 <__neorv32_uart_itoa+0x4e> + a78: b1000013 li zero,-1264 + a7c: 079e0107 .4byte 0x79e0107 + a80: 0000 unimp + a82: 07b2 slli a5,a5,0xc + a84: f901 bnez a0,994 <__neorv32_uart_itoa+0x6c> + a86: 000a c.slli zero,0x2 + a88: 0000 unimp + a8a: 05b2010b .4byte 0x5b2010b + a8e: 0000 unimp + a90: 0b02 c.slli64 s6 + a92: 7701 lui a4,0xfffe0 + a94: 000c .2byte 0xc + a96: 0300 addi s0,sp,384 + a98: 0c88010b .4byte 0xc88010b + a9c: 0000 unimp + a9e: 0b04 addi s1,sp,400 + aa0: 9901 andi a0,a0,-32 + aa2: 000c .2byte 0xc + aa4: 0500 addi s0,sp,640 + aa6: 0caa010b .4byte 0xcaa010b + aaa: 0000 unimp + aac: 0b06 slli s6,s6,0x1 + aae: bb01 j 7be <__neorv32_rte_debug_handler+0x25a> + ab0: 000c .2byte 0xc + ab2: 0700 addi s0,sp,896 + ab4: 0ccc010b .4byte 0xccc010b + ab8: 0000 unimp + aba: 0b08 addi a0,sp,400 + abc: dd01 beqz a0,9d4 <__neorv32_uart_itoa+0xac> + abe: 000c .2byte 0xc + ac0: 0900 addi s0,sp,144 + ac2: 06a5010b .4byte 0x6a5010b + ac6: 0000 unimp + ac8: 0b0a slli s6,s6,0x2 + aca: b701 j 9ca <__neorv32_uart_itoa+0xa2> + acc: 0006 c.slli zero,0x1 + ace: 0b00 addi s0,sp,400 + ad0: 06c9010b .4byte 0x6c9010b + ad4: 0000 unimp + ad6: 0b0c addi a1,sp,400 + ad8: db01 beqz a4,9e8 <__neorv32_uart_itoa+0xc0> + ada: 0006 c.slli zero,0x1 + adc: 0d00 addi s0,sp,656 + ade: 06ed010b .4byte 0x6ed010b + ae2: 0000 unimp + ae4: 0b0e slli s6,s6,0x3 + ae6: ff01 bnez a4,9fe <__neorv32_uart_itoa+0xd6> + ae8: 0006 c.slli zero,0x1 + aea: 0f00 addi s0,sp,912 + aec: 0711010b .4byte 0x711010b + af0: 0000 unimp + af2: 0b10 addi a2,sp,400 + af4: 2301 jal ff4 <_malloc_r+0x196> + af6: 11000007 .4byte 0x11000007 + afa: 0735010b .4byte 0x735010b + afe: 0000 unimp + b00: 0b12 slli s6,s6,0x4 + b02: 4701 li a4,0 + b04: 13000007 .4byte 0x13000007 + b08: 0806010b .4byte 0x806010b + b0c: 0000 unimp + b0e: 0b14 addi a3,sp,400 + b10: 1801 addi a6,a6,-32 + b12: 0008 .2byte 0x8 + b14: 1500 addi s0,sp,672 + b16: 082a010b .4byte 0x82a010b + b1a: 0000 unimp + b1c: 0b16 slli s6,s6,0x5 + b1e: 3c01 jal 52e <__neorv32_rte_print_hex_word+0x3a> + b20: 0008 .2byte 0x8 + b22: 1700 addi s0,sp,928 + b24: 084e010b .4byte 0x84e010b + b28: 0000 unimp + b2a: 0b18 addi a4,sp,400 + b2c: 6001 .2byte 0x6001 + b2e: 0008 .2byte 0x8 + b30: 1900 addi s0,sp,176 + b32: 0872010b .4byte 0x872010b + b36: 0000 unimp + b38: 0b1a slli s6,s6,0x6 + b3a: 8401 c.srai64 s0 + b3c: 0008 .2byte 0x8 + b3e: 1b00 addi s0,sp,432 + b40: 0896010b .4byte 0x896010b + b44: 0000 unimp + b46: 0b1c addi a5,sp,400 + b48: a801 j b58 + b4a: 0008 .2byte 0x8 + b4c: 1d00 addi s0,sp,688 + b4e: 09f9010b .4byte 0x9f9010b + b52: 0000 unimp + b54: 0b1e slli s6,s6,0x7 + b56: 0b01 addi s6,s6,0 + b58: 000a c.slli zero,0x2 + b5a: 1f00 addi s0,sp,944 + b5c: 1164010b .4byte 0x1164010b + b60: 0000 unimp + b62: 0b80 addi s0,sp,464 + b64: 9f01 .2byte 0x9f01 + b66: 82000017 auipc zero,0x82000 + b6a: 0a1d010b .4byte 0xa1d010b + b6e: 0000 unimp + b70: 4c010b83 lb s7,1216(sp) + b74: 8400000b .4byte 0x8400000b + b78: 144b010b .4byte 0x144b010b + b7c: 0000 unimp + b7e: 0b85 addi s7,s7,1 + b80: 6501 .2byte 0x6501 + b82: 000c .2byte 0xc + b84: 8600 .2byte 0x8600 + b86: 0d6d010b .4byte 0xd6d010b + b8a: 0000 unimp + b8c: d7010b87 .4byte 0xd7010b87 + b90: 000d c.nop 3 + b92: 8800 .2byte 0x8800 + b94: 0e45010b .4byte 0xe45010b + b98: 0000 unimp + b9a: 0b89 addi s7,s7,2 + b9c: b001 j 39c <__neorv32_rte_core+0xf0> + b9e: 0016 c.slli zero,0x5 + ba0: 8a00 .2byte 0x8a00 + ba2: 171b010b .4byte 0x171b010b + ba6: 0000 unimp + ba8: c2010b8b .4byte 0xc2010b8b + bac: 8c000017 auipc zero,0x8c000 + bb0: 182e010b .4byte 0x182e010b + bb4: 0000 unimp + bb6: 0b8d addi s7,s7,3 + bb8: 2501 jal 11b8 <_malloc_r+0x35a> + bba: 0019 c.nop 6 + bbc: 8e00 .2byte 0x8e00 + bbe: 19dd010b .4byte 0x19dd010b + bc2: 0000 unimp + bc4: 68010b8f .4byte 0x68010b8f + bc8: 001a c.slli zero,0x6 + bca: 9000 .2byte 0x9000 + bcc: 1b99010b .4byte 0x1b99010b + bd0: 0000 unimp + bd2: 0b91 addi s7,s7,4 + bd4: ec01 bnez s0,bec + bd6: 001c .2byte 0x1c + bd8: 9200 .2byte 0x9200 + bda: 1dfb010b .4byte 0x1dfb010b + bde: 0000 unimp + be0: f2010b93 addi s7,sp,-224 + be4: 001a c.slli zero,0x6 + be6: 9400 .2byte 0x9400 + be8: 1c12010b .4byte 0x1c12010b + bec: 0000 unimp + bee: 0b95 addi s7,s7,5 + bf0: 2101 jal ff0 <_malloc_r+0x192> + bf2: 001d c.nop 7 + bf4: 9600 .2byte 0x9600 + bf6: 13e7010b .4byte 0x13e7010b + bfa: 0000 unimp + bfc: 5b010b97 auipc s7,0x5b010 + c00: 0005 c.nop 1 + c02: 9800 .2byte 0x9800 + c04: 063d010b .4byte 0x63d010b + c08: 0000 unimp + c0a: 0b99 addi s7,s7,6 # 5b010c02 <__neorv32_ram_size+0x5b00ec02> + c0c: 6001 .2byte 0x6001 + c0e: 9a000007 .4byte 0x9a000007 + c12: 094a010b .4byte 0x94a010b + c16: 0000 unimp + c18: 2f010b9b .4byte 0x2f010b9b + c1c: 000a c.slli zero,0x2 + c1e: 9c00 .2byte 0x9c00 + c20: 0b70010b .4byte 0xb70010b + c24: 0000 unimp + c26: 0b9d addi s7,s7,7 + c28: 7301 lui t1,0xfffe0 + c2a: 9e000007 .4byte 0x9e000007 + c2e: 0974010b .4byte 0x974010b + c32: 0000 unimp + c34: 0b9f ad01 0017 .byte 0x9f, 0x0b, 0x01, 0xad, 0x17, 0x00 + c3a: 0000 unimp + c3c: 010c addi a1,sp,128 + c3e: 00001793 slli a5,zero,0x0 + c42: 0c02 c.slli64 s8 + c44: 4001 c.li zero,0 + c46: 0016 c.slli zero,0x5 + c48: 0300 addi s0,sp,384 + c4a: 010c addi a1,sp,128 + c4c: 1650 addi a2,sp,804 + c4e: 0000 unimp + c50: 0c04 addi s1,sp,528 + c52: 6001 .2byte 0x6001 + c54: 0016 c.slli zero,0x5 + c56: 0500 addi s0,sp,640 + c58: 010c addi a1,sp,128 + c5a: 1670 addi a2,sp,812 + c5c: 0000 unimp + c5e: 0c06 slli s8,s8,0x1 + c60: 8001 c.srli64 s0 + c62: 0016 c.slli zero,0x5 + c64: 0700 addi s0,sp,896 + c66: 010c addi a1,sp,128 + c68: 1690 addi a2,sp,864 + c6a: 0000 unimp + c6c: 0c08 addi a0,sp,528 + c6e: a001 j c6e + c70: 0016 c.slli zero,0x5 + c72: 0900 addi s0,sp,144 + c74: 010c addi a1,sp,128 + c76: 00001a7b .4byte 0x1a7b + c7a: 0c0a slli s8,s8,0x2 + c7c: 8c01 sub s0,s0,s0 + c7e: 001a c.slli zero,0x6 + c80: 0b00 addi s0,sp,400 + c82: 010c addi a1,sp,128 + c84: 1a9d addi s5,s5,-25 + c86: 0000 unimp + c88: 0c0c addi a1,sp,528 + c8a: ae01 j f9a <_malloc_r+0x13c> + c8c: 001a c.slli zero,0x6 + c8e: 0d00 addi s0,sp,656 + c90: 010c addi a1,sp,128 + c92: 00001abf d0010c0e .8byte 0xd0010c0e00001abf + c9a: 001a c.slli zero,0x6 + c9c: 0f00 addi s0,sp,912 + c9e: 010c addi a1,sp,128 + ca0: 1ae1 addi s5,s5,-8 + ca2: 0000 unimp + ca4: 0c10 addi a2,sp,528 + ca6: d501 beqz a0,bae + ca8: 0009 c.nop 2 + caa: 1100 addi s0,sp,160 + cac: 010c addi a1,sp,128 + cae: 1b05 addi s6,s6,-31 + cb0: 0000 unimp + cb2: 0c12 slli s8,s8,0x4 + cb4: 1601 addi a2,a2,-32 + cb6: 1300001b .4byte 0x1300001b + cba: 010c addi a1,sp,128 + cbc: 1bac addi a1,sp,504 + cbe: 0000 unimp + cc0: 0c14 addi a3,sp,528 + cc2: bd01 j ad2 + cc4: 1500001b .4byte 0x1500001b + cc8: 010c addi a1,sp,128 + cca: 1bce slli s7,s7,0x33 + ccc: 0000 unimp + cce: 0c16 slli s8,s8,0x5 + cd0: df01 beqz a4,be8 + cd2: 1700001b .4byte 0x1700001b + cd6: 010c addi a1,sp,128 + cd8: 1bf0 addi a2,sp,508 + cda: 0000 unimp + cdc: 0c18 addi a4,sp,528 + cde: 0101 addi sp,sp,0 + ce0: 001c .2byte 0x1c + ce2: 1900 addi s0,sp,176 + ce4: 010c addi a1,sp,128 + ce6: 0ba5 addi s7,s7,9 + ce8: 0000 unimp + cea: 0c1a slli s8,s8,0x6 + cec: b601 j 7ec <__neorv32_rte_debug_handler+0x288> + cee: 1b00000b .4byte 0x1b00000b + cf2: 010c addi a1,sp,128 + cf4: 1c25 addi s8,s8,-23 + cf6: 0000 unimp + cf8: 0c1c addi a5,sp,528 + cfa: 3601 jal 7fa <__neorv32_rte_debug_handler+0x296> + cfc: 001c .2byte 0x1c + cfe: 1d00 addi s0,sp,688 + d00: 010c addi a1,sp,128 + d02: 1cff .2byte 0x1cff + d04: 0000 unimp + d06: 0c1e slli s8,s8,0x7 + d08: 1001 c.nop -32 + d0a: 001d c.nop 7 + d0c: 1f00 addi s0,sp,944 + d0e: 010c addi a1,sp,128 + d10: 08ed addi a7,a7,27 + d12: 0000 unimp + d14: 0c80 addi s0,sp,592 + d16: 4201 li tp,0 + d18: 000a c.slli zero,0x2 + d1a: 8200 .2byte 0x8200 + d1c: 010c addi a1,sp,128 + d1e: 1d64 addi s1,sp,700 + d20: 0000 unimp + d22: a7010c83 lb s9,-1424(sp) + d26: 001e c.slli zero,0x7 + d28: 8400 .2byte 0x8400 + d2a: 010c addi a1,sp,128 + d2c: 05d1 addi a1,a1,20 # 9624 <__neorv32_ram_size+0x7624> + d2e: 0000 unimp + d30: 0c85 addi s9,s9,1 + d32: 6a01 .2byte 0x6a01 + d34: 0006 c.slli zero,0x1 + d36: 8600 .2byte 0x8600 + d38: 010c addi a1,sp,128 + d3a: 07ac addi a1,sp,968 + d3c: 0000 unimp + d3e: a2010c87 .4byte 0xa2010c87 + d42: 0009 c.nop 2 + d44: 8800 .2byte 0x8800 + d46: 010c addi a1,sp,128 + d48: 0a94 addi a3,sp,336 + d4a: 0000 unimp + d4c: 0c89 addi s9,s9,2 + d4e: c301 beqz a4,d4e + d50: 0016 c.slli zero,0x5 + d52: 8a00 .2byte 0x8a00 + d54: 010c addi a1,sp,128 + d56: 1752 slli a4,a4,0x34 + d58: 0000 unimp + d5a: 05010c8b .4byte 0x5010c8b + d5e: 0018 .2byte 0x18 + d60: 8c00 .2byte 0x8c00 + d62: 010c addi a1,sp,128 + d64: 1854 addi a3,sp,52 + d66: 0000 unimp + d68: 0c8d addi s9,s9,3 + d6a: 4e01 li t3,0 + d6c: 0019 c.nop 6 + d6e: 8e00 .2byte 0x8e00 + d70: 010c addi a1,sp,128 + d72: 1a1c addi a5,sp,304 + d74: 0000 unimp + d76: 53010c8f .4byte 0x53010c8f + d7a: 000c .2byte 0xc + d7c: 9000 .2byte 0x9000 + d7e: 010c addi a1,sp,128 + d80: 0dba slli s11,s11,0xe + d82: 0000 unimp + d84: 0c91 addi s9,s9,4 + d86: 3401 jal 786 <__neorv32_rte_debug_handler+0x222> + d88: 001d c.nop 7 + d8a: 9200 .2byte 0x9200 + d8c: 010c addi a1,sp,128 + d8e: 00001e83 lh t4,0(zero) # 0 <__crt0_entry> + d92: 4d010c93 addi s9,sp,1232 + d96: 9400001b .4byte 0x9400001b + d9a: 010c addi a1,sp,128 + d9c: 00001c57 .4byte 0x1c57 + da0: 0c95 addi s9,s9,5 + da2: 5201 li tp,-32 + da4: 001d c.nop 7 + da6: 9600 .2byte 0x9600 + da8: 010c addi a1,sp,128 + daa: 1e95 addi t4,t4,-27 + dac: 0000 unimp + dae: bf010c97 auipc s9,0xbf010 + db2: 0005 c.nop 1 + db4: 9800 .2byte 0x9800 + db6: 010c addi a1,sp,128 + db8: 0658 addi a4,sp,772 + dba: 0000 unimp + dbc: 0c99 addi s9,s9,6 # bf010db4 <__crt0_stack_begin+0x3f00edb8> + dbe: 8601 c.srai64 a2 + dc0: 9a000007 .4byte 0x9a000007 + dc4: 010c addi a1,sp,128 + dc6: 00000987 .4byte 0x987 + dca: 6e010c9b .4byte 0x6e010c9b + dce: 000a c.slli zero,0x2 + dd0: 9c00 .2byte 0x9c00 + dd2: 010c addi a1,sp,128 + dd4: 00000b83 lb s7,0(zero) # 0 <__crt0_entry> + dd8: 0c9d addi s9,s9,7 + dda: bd01 j bea + ddc: 9e000007 .4byte 0x9e000007 + de0: 010c addi a1,sp,128 + de2: 000009b3 add s3,zero,zero + de6: 0c9f 2001 000f .byte 0x9f, 0x0c, 0x01, 0x20, 0x0f, 0x00 + dec: 1100 addi s0,sp,160 + dee: 0de9010f .4byte 0xde9010f + df2: 0000 unimp + df4: 0f12 slli t5,t5,0x4 + df6: fa01 bnez a2,d06 + df8: 0016 c.slli zero,0x5 + dfa: 1300 addi s0,sp,416 + dfc: 1b6c010f .4byte 0x1b6c010f + e00: 0000 unimp + e02: 0f14 addi a3,sp,912 + e04: a301 j 1304 <_malloc_r+0x4a6> + e06: 001c .2byte 0x1c + e08: 1500 addi s0,sp,672 + e0a: 096a010f .4byte 0x96a010f + e0e: 0000 unimp + e10: 0fc0 addi s0,sp,980 + e12: 1000 addi s0,sp,32 + e14: 08ba slli a7,a7,0xe + e16: 0000 unimp + e18: 00a6 slli ra,ra,0x9 + e1a: 0000 unimp + e1c: 016a slli sp,sp,0x1a + e1e: 4a06 lw s4,64(sp) + e20: 02000007 .4byte 0x2000007 + e24: 00001817 auipc a6,0x1 + e28: 1d750203 lb tp,471(a0) + e2c: 0000 unimp + e2e: 1cb20207 .4byte 0x1cb20207 + e32: 0000 unimp + e34: 0e01020b .4byte 0xe01020b + e38: 0000 unimp + e3a: 0210 addi a2,sp,256 + e3c: 0e62 slli t3,t3,0x18 + e3e: 0000 unimp + e40: 0211 addi tp,tp,4 # 4 <__crt0_cpu_csr_init> + e42: 0fb6 slli t6,t6,0xd + e44: 0000 unimp + e46: 0212 slli tp,tp,0x4 + e48: 100a c.slli zero,0x22 + e4a: 0000 unimp + e4c: 11490213 addi tp,s2,276 # 1114 <_malloc_r+0x2b6> + e50: 0000 unimp + e52: 0214 addi a3,sp,256 + e54: 1240 addi s0,sp,292 + e56: 0000 unimp + e58: 0215 addi tp,tp,5 # 5 + e5a: 00001317 auipc t1,0x1 + e5e: 0216 slli tp,tp,0x5 + e60: 132e slli t1,t1,0x2b + e62: 0000 unimp + e64: 13d80217 auipc tp,0x13d80 + e68: 0000 unimp + e6a: 0218 addi a4,sp,256 + e6c: 1482 slli s1,s1,0x20 + e6e: 0000 unimp + e70: 0219 addi tp,tp,6 # 13d80e6a <__neorv32_ram_size+0x13d7ee6a> + e72: 000007cf .4byte 0x7cf + e76: 021a slli tp,tp,0x6 + e78: 09c5 addi s3,s3,17 + e7a: 0000 unimp + e7c: 0ac5021b .4byte 0xac5021b + e80: 0000 unimp + e82: 021c addi a5,sp,256 + e84: 0b95 addi s7,s7,5 + e86: 0000 unimp + e88: 021d addi tp,tp,7 # 7 + e8a: 00000c33 add s8,zero,zero + e8e: 021e slli tp,tp,0x7 + e90: 00000cfb .4byte 0xcfb + e94: 001f 5710 000d .byte 0x1f, 0x00, 0x10, 0x57, 0x0d, 0x00 + e9a: a600 .2byte 0xa600 + e9c: 0000 unimp + e9e: a100 .2byte 0xa100 + ea0: 0601 addi a2,a2,0 + ea2: 000007a3 sb zero,15(zero) # f + ea6: 4202 lw tp,0(sp) + ea8: 0010 .2byte 0x10 + eaa: 0000 unimp + eac: 4d02 lw s10,0(sp) + eae: 0010 .2byte 0x10 + eb0: 0100 addi s0,sp,128 + eb2: 5802 lw a6,32(sp) + eb4: 0010 .2byte 0x10 + eb6: 0200 addi s0,sp,256 + eb8: 5702 lw a4,32(sp) + eba: 000e c.slli zero,0x3 + ebc: 0300 addi s0,sp,384 + ebe: 7102 .2byte 0x7102 + ec0: 000e c.slli zero,0x3 + ec2: 0400 addi s0,sp,512 + ec4: 9402 jalr s0 + ec6: 000e c.slli zero,0x3 + ec8: 0500 addi s0,sp,640 + eca: b202 .2byte 0xb202 + ecc: 000e c.slli zero,0x3 + ece: 0800 addi s0,sp,16 + ed0: d602 sw zero,44(sp) + ed2: 000e c.slli zero,0x3 + ed4: 0c00 addi s0,sp,528 + ed6: 1802 slli a6,a6,0x20 + ed8: 0011 c.nop 4 + eda: 1400 addi s0,sp,544 + edc: 3702 .2byte 0x3702 + ede: 0011 c.nop 4 + ee0: 1700 addi s0,sp,928 + ee2: 4302 lw t1,0(sp) + ee4: 000c .2byte 0xc + ee6: 1e00 addi s0,sp,816 + ee8: df02 sw zero,188(sp) + eea: 1f000007 .4byte 0x1f000007 + eee: 1000 addi s0,sp,32 + ef0: 1705 addi a4,a4,-31 # fffdffe1 <__crt0_stack_begin+0x7ffddfe5> + ef2: 0000 unimp + ef4: 00a6 slli ra,ra,0x9 + ef6: 0000 unimp + ef8: 01b4 addi a3,sp,200 + efa: 0206 slli tp,tp,0x1 + efc: 0008 .2byte 0x8 + efe: 0200 addi s0,sp,256 + f00: 00001783 lh a5,0(zero) # 0 <__crt0_entry> + f04: 0200 addi s0,sp,256 + f06: 0e9f 0000 0201 .byte 0x9f, 0x0e, 0x00, 0x00, 0x01, 0x02 + f0c: 199d addi s3,s3,-25 + f0e: 0000 unimp + f10: 0202 c.slli64 tp + f12: 1a0c addi a1,sp,304 + f14: 0000 unimp + f16: 0d2b0203 lb tp,210(s6) + f1a: 0000 unimp + f1c: 0205 addi tp,tp,1 # 1 + f1e: 1879 addi a6,a6,-2 # 1e22 <__RODATA_END__+0x352> + f20: 0000 unimp + f22: 1a2e0207 .4byte 0x1a2e0207 + f26: 0000 unimp + f28: 0208 addi a0,sp,256 + f2a: 0000158f .4byte 0x158f + f2e: 0209 addi tp,tp,2 # 2 + f30: 1a3c addi a5,sp,312 + f32: 0000 unimp + f34: 020a slli tp,tp,0x2 + f36: 1502 slli a0,a0,0x20 + f38: 0000 unimp + f3a: 1cbf020b .4byte 0x1cbf020b + f3e: 0000 unimp + f40: 0214 addi a3,sp,256 + f42: 000005ef jal a1,f42 <_malloc_r+0xe4> + f46: 021e slli tp,tp,0x7 + f48: 122c addi a1,sp,296 + f4a: 0000 unimp + f4c: 001f 0b10 0006 .byte 0x1f, 0x00, 0x10, 0x0b, 0x06, 0x00 + f52: a600 .2byte 0xa600 + f54: 0000 unimp + f56: fc00 .2byte 0xfc00 + f58: 0601 addi a2,a2,0 + f5a: 08fa slli a7,a7,0x1e + f5c: 0000 unimp + f5e: 2e02 .2byte 0x2e02 + f60: 000e c.slli zero,0x3 + f62: 0000 unimp + f64: 2e02 .2byte 0x2e02 + f66: 01000017 auipc zero,0x1000 + f6a: b002 .2byte 0xb002 + f6c: 0014 .2byte 0x14 + f6e: 0200 addi s0,sp,256 + f70: 2802 .2byte 0x2802 + f72: 0006 c.slli zero,0x1 + f74: 0300 addi s0,sp,384 + f76: 6402 .2byte 0x6402 + f78: 04000017 auipc zero,0x4000 + f7c: ef02 .2byte 0xef02 + f7e: 0014 .2byte 0x14 + f80: 0500 addi s0,sp,640 + f82: ef02 .2byte 0xef02 + f84: 06000007 .4byte 0x6000007 + f88: d602 sw zero,44(sp) + f8a: 0700000f fence orw,unknown + f8e: bc02 .2byte 0xbc02 + f90: 0015 c.nop 5 + f92: 0800 addi s0,sp,16 + f94: 2702 .2byte 0x2702 + f96: 0b00001b .4byte 0xb00001b + f9a: 1008 addi a0,sp,32 + f9c: 0012 c.slli zero,0x4 + f9e: 0300 addi s0,sp,384 + fa0: 0000 unimp + fa2: 0880 addi s0,sp,80 + fa4: 1dbd addi s11,s11,-17 + fa6: 0000 unimp + fa8: 80000007 .4byte 0x80000007 + fac: 1e08 addi a0,sp,816 + fae: 0012 c.slli zero,0x4 + fb0: 0b00 addi s0,sp,400 + fb2: 0000 unimp + fb4: 0880 addi s0,sp,80 + fb6: 0f2e slli t5,t5,0xb + fb8: 0000 unimp + fba: 0010 .2byte 0x10 + fbc: 8000 .2byte 0x8000 + fbe: 3f08 .2byte 0x3f08 + fc0: 1100000f .4byte 0x1100000f + fc4: 0000 unimp + fc6: 0880 addi s0,sp,80 + fc8: 0f50 addi a2,sp,916 + fca: 0000 unimp + fcc: 0012 c.slli zero,0x4 + fce: 8000 .2byte 0x8000 + fd0: 6108 .2byte 0x6108 + fd2: 1300000f .4byte 0x1300000f + fd6: 0000 unimp + fd8: 0880 addi s0,sp,80 + fda: 0f72 slli t5,t5,0x1c + fdc: 0000 unimp + fde: 0014 .2byte 0x14 + fe0: 8000 .2byte 0x8000 + fe2: 8308 .2byte 0x8308 + fe4: 1500000f .4byte 0x1500000f + fe8: 0000 unimp + fea: 0880 addi s0,sp,80 + fec: 0f94 addi a3,sp,976 + fee: 0000 unimp + ff0: 0016 c.slli zero,0x5 + ff2: 8000 .2byte 0x8000 + ff4: a508 .2byte 0xa508 + ff6: 1700000f .4byte 0x1700000f + ffa: 0000 unimp + ffc: 0880 addi s0,sp,80 + ffe: 0000141b .4byte 0x141b + 1002: 0018 .2byte 0x18 + 1004: 8000 .2byte 0x8000 + 1006: 2c08 .2byte 0x2c08 + 1008: 0014 .2byte 0x14 + 100a: 1900 addi s0,sp,176 + 100c: 0000 unimp + 100e: 0880 addi s0,sp,80 + 1010: 0b04 addi s1,sp,400 + 1012: 0000 unimp + 1014: 001a c.slli zero,0x6 + 1016: 8000 .2byte 0x8000 + 1018: 1608 addi a0,sp,800 + 101a: 1b00000b .4byte 0x1b00000b + 101e: 0000 unimp + 1020: 0880 addi s0,sp,80 + 1022: 0b28 addi a0,sp,408 + 1024: 0000 unimp + 1026: 001c .2byte 0x1c + 1028: 8000 .2byte 0x8000 + 102a: 3a08 .2byte 0x3a08 + 102c: 1d00000b .4byte 0x1d00000b + 1030: 0000 unimp + 1032: 0880 addi s0,sp,80 + 1034: 16e8 addi a0,sp,876 + 1036: 0000 unimp + 1038: 001e c.slli zero,0x7 + 103a: 8000 .2byte 0x8000 + 103c: 5e08 lw a0,56(a2) + 103e: 1f00000b .4byte 0x1f00000b + 1042: 0000 unimp + 1044: 0080 addi s0,sp,64 + 1046: 03c50827 .4byte 0x3c50827 + 104a: 0000091b .4byte 0x91b + 104e: cb0d beqz a4,1080 <_malloc_r+0x222> + 1050: c6000013 li zero,-928 + 1054: 0000e203 .4byte 0xe203 + 1058: 0000 unimp + 105a: 9a0d andi a2,a2,-29 + 105c: 001c .2byte 0x1c + 105e: c700 sw s0,8(a4) + 1060: 0000ee03 .4byte 0xee03 + 1064: 0400 addi s0,sp,512 + 1066: 2800 .2byte 0x2800 + 1068: 0a80 addi s0,sp,336 + 106a: 0000 unimp + 106c: 03c8 addi a0,sp,452 + 106e: 08fa slli a7,a7,0x1e + 1070: 0000 unimp + 1072: 4610 lw a2,8(a2) + 1074: a6000013 li zero,-1440 + 1078: 0000 unimp + 107a: d100 sw s0,32(a0) + 107c: 09430603 lb a2,148(t1) # 1eee <__RODATA_END__+0x41e> + 1080: 0000 unimp + 1082: 5502 lw a0,32(sp) + 1084: 001a c.slli zero,0x6 + 1086: 0000 unimp + 1088: d502 sw zero,168(sp) + 108a: 0016 c.slli zero,0x5 + 108c: 1f00 addi s0,sp,944 + 108e: 2700 .2byte 0x2700 + 1090: 4420 lw s0,72(s0) + 1092: ac05 j 12c2 <_malloc_r+0x464> + 1094: 0009 c.nop 2 + 1096: 2900 .2byte 0x2900 + 1098: 004b4c43 .4byte 0x4b4c43 + 109c: 0545 addi a0,a0,17 + 109e: 00ee slli ra,ra,0x1b + 10a0: 0000 unimp + 10a2: 0d00 addi s0,sp,656 + 10a4: 0084 addi s1,sp,64 + 10a6: 0000 unimp + 10a8: 0546 slli a0,a0,0x11 + 10aa: 00ee slli ra,ra,0x1b + 10ac: 0000 unimp + 10ae: 2904 .2byte 0x2904 + 10b0: 00434f53 .4byte 0x434f53 + 10b4: 00ee0547 .4byte 0xee0547 + 10b8: 0000 unimp + 10ba: 0d08 addi a0,sp,656 + 10bc: 03bd addi t2,t2,15 + 10be: 0000 unimp + 10c0: 0548 addi a0,sp,644 + 10c2: 00ee slli ra,ra,0x1b + 10c4: 0000 unimp + 10c6: 0d0c addi a1,sp,656 + 10c8: 0232 slli tp,tp,0xc + 10ca: 0000 unimp + 10cc: 0549 addi a0,a0,18 + 10ce: 00ee slli ra,ra,0x1b + 10d0: 0000 unimp + 10d2: 0d10 addi a2,sp,656 + 10d4: 00aa slli ra,ra,0xa + 10d6: 0000 unimp + 10d8: 054a slli a0,a0,0x12 + 10da: 00ee slli ra,ra,0x1b + 10dc: 0000 unimp + 10de: 0d14 addi a3,sp,656 + 10e0: 004d c.nop 19 + 10e2: 0000 unimp + 10e4: 00ee054b .4byte 0xee054b + 10e8: 0000 unimp + 10ea: 0d18 addi a4,sp,656 + 10ec: 008e slli ra,ra,0x3 + 10ee: 0000 unimp + 10f0: 054c addi a1,sp,644 + 10f2: 00ee slli ra,ra,0x1b + 10f4: 0000 unimp + 10f6: 001c .2byte 0x1c + 10f8: 9828 .2byte 0x9828 + 10fa: 0000 unimp + 10fc: 4d00 lw s0,24(a0) + 10fe: 4305 li t1,1 + 1100: 0009 c.nop 2 + 1102: 1000 addi s0,sp,32 + 1104: 02ad addi t0,t0,11 + 1106: 0000 unimp + 1108: 00a6 slli ra,ra,0x9 + 110a: 0000 unimp + 110c: 0556 slli a0,a0,0x15 + 110e: 5806 lw a6,96(sp) + 1110: 000a c.slli zero,0x2 + 1112: 0200 addi s0,sp,256 + 1114: 0434 addi a3,sp,520 + 1116: 0000 unimp + 1118: 0200 addi s0,sp,256 + 111a: 04fa slli s1,s1,0x1e + 111c: 0000 unimp + 111e: 0201 addi tp,tp,0 # 0 <__crt0_entry> + 1120: 02ce slli t0,t0,0x13 + 1122: 0000 unimp + 1124: 0202 c.slli64 tp + 1126: 000002e7 jalr t0,zero # 0 <__crt0_entry> + 112a: 047f0203 lb tp,71(t5) + 112e: 0000 unimp + 1130: 0204 addi s1,sp,256 + 1132: 03b0 addi a2,sp,456 + 1134: 0000 unimp + 1136: 0205 addi tp,tp,1 # 1 + 1138: 0315 addi t1,t1,5 + 113a: 0000 unimp + 113c: 020d addi tp,tp,3 # 3 + 113e: 03a0 addi s0,sp,456 + 1140: 0000 unimp + 1142: 020e slli tp,tp,0x3 + 1144: 0521 addi a0,a0,8 + 1146: 0000 unimp + 1148: 0210 addi a2,sp,256 + 114a: 0300 addi s0,sp,384 + 114c: 0000 unimp + 114e: 0211 addi tp,tp,4 # 4 <__crt0_cpu_csr_init> + 1150: 04b0 addi a2,sp,584 + 1152: 0000 unimp + 1154: 0212 slli tp,tp,0x4 + 1156: 0000044b .4byte 0x44b + 115a: 03c30213 addi tp,t1,60 + 115e: 0000 unimp + 1160: 0214 addi a3,sp,256 + 1162: 0000033f 05400215 .8byte 0x54002150000033f + 116a: 0000 unimp + 116c: 0216 slli tp,tp,0x5 + 116e: 050e slli a0,a0,0x3 + 1170: 0000 unimp + 1172: 038c0217 auipc tp,0x38c0 + 1176: 0000 unimp + 1178: 0218 addi a4,sp,256 + 117a: 0404 addi s1,sp,512 + 117c: 0000 unimp + 117e: 0219 addi tp,tp,6 # 38c1178 <__neorv32_ram_size+0x38bf178> + 1180: 04c5 addi s1,s1,17 + 1182: 0000 unimp + 1184: 021a slli tp,tp,0x6 + 1186: 03d6 slli t2,t2,0x15 + 1188: 0000 unimp + 118a: 0419021b .4byte 0x419021b + 118e: 0000 unimp + 1190: 021c addi a5,sp,256 + 1192: 04e5 addi s1,s1,25 + 1194: 0000 unimp + 1196: 021d addi tp,tp,7 # 7 + 1198: 0352 slli t1,t1,0x14 + 119a: 0000 unimp + 119c: 021e slli tp,tp,0x7 + 119e: 0365 addi t1,t1,25 + 11a0: 0000 unimp + 11a2: 001f 6910 001c .byte 0x1f, 0x00, 0x10, 0x69, 0x1c, 0x00 + 11a8: a600 .2byte 0xa600 + 11aa: 0000 unimp + 11ac: 7400 .2byte 0x7400 + 11ae: 0705 addi a4,a4,1 + 11b0: 0ac9 addi s5,s5,18 + 11b2: 0000 unimp + 11b4: 4f02 lw t5,0(sp) + 11b6: 0012 c.slli zero,0x4 + 11b8: 0000 unimp + 11ba: 6d02 .2byte 0x6d02 + 11bc: 0012 c.slli zero,0x4 + 11be: 0100 addi s0,sp,128 + 11c0: 8b02 jr s6 + 11c2: 0012 c.slli zero,0x4 + 11c4: 0200 addi s0,sp,256 + 11c6: a902 .2byte 0xa902 + 11c8: 0012 c.slli zero,0x4 + 11ca: 0300 addi s0,sp,384 + 11cc: cf02 sw zero,156(sp) + 11ce: 0008 .2byte 0x8 + 11d0: 0400 addi s0,sp,512 + 11d2: 1002 c.slli zero,0x20 + 11d4: 000e c.slli zero,0x3 + 11d6: 0500 addi s0,sp,640 + 11d8: f802 .2byte 0xf802 + 11da: 0008 .2byte 0x8 + 11dc: 0600 addi s0,sp,768 + 11de: 1602 slli a2,a2,0x20 + 11e0: 0009 c.nop 2 + 11e2: 0700 addi s0,sp,896 + 11e4: d002 sw zero,32(sp) + 11e6: 0015 c.nop 5 + 11e8: 0800 addi s0,sp,16 + 11ea: f102 .2byte 0xf102 + 11ec: 0015 c.nop 5 + 11ee: 0900 addi s0,sp,144 + 11f0: 1202 slli tp,tp,0x20 + 11f2: 0016 c.slli zero,0x5 + 11f4: 0a00 addi s0,sp,272 + 11f6: 8402 jr s0 + 11f8: 0006 c.slli zero,0x1 + 11fa: 0b00 addi s0,sp,400 + 11fc: 1302 slli t1,t1,0x20 + 11fe: 0015 c.nop 5 + 1200: 0c00 addi s0,sp,528 + 1202: 3202 .2byte 0x3202 + 1204: 0015 c.nop 5 + 1206: 0d00 addi s0,sp,656 + 1208: 5102 lw sp,32(sp) + 120a: 0015 c.nop 5 + 120c: 0e00 addi s0,sp,784 + 120e: 7002 .2byte 0x7002 + 1210: 0015 c.nop 5 + 1212: 0f00 addi s0,sp,912 + 1214: 2600 .2byte 0x2600 + 1216: 00001893 slli a7,zero,0x0 + 121a: 00a6 slli ra,ra,0x9 + 121c: 0000 unimp + 121e: 3606 .2byte 0x3606 + 1220: 00000b87 .4byte 0xb87 + 1224: 3802 .2byte 0x3802 + 1226: 0019 c.nop 6 + 1228: 0000 unimp + 122a: ad02 .2byte 0xad02 + 122c: 0019 c.nop 6 + 122e: 0100 addi s0,sp,128 + 1230: d502 sw zero,168(sp) + 1232: 02000017 auipc zero,0x2000 + 1236: 2302 .2byte 0x2302 + 1238: 0011 c.nop 4 + 123a: 0300 addi s0,sp,384 + 123c: 3402 .2byte 0x3402 + 123e: 0009 c.nop 2 + 1240: 0400 addi s0,sp,512 + 1242: 3b02 .2byte 0x3b02 + 1244: 0500001b .4byte 0x500001b + 1248: c702 sw zero,140(sp) + 124a: 0012 c.slli zero,0x4 + 124c: 0600 addi s0,sp,768 + 124e: cb02 sw zero,148(sp) + 1250: 0019 c.nop 6 + 1252: 0700 addi s0,sp,896 + 1254: 6602 .2byte 0x6602 + 1256: 0018 .2byte 0x18 + 1258: 0800 addi s0,sp,16 + 125a: 9f02 jalr t5 + 125c: 0005 c.nop 1 + 125e: 0900 addi s0,sp,144 + 1260: 5f02 lw t5,32(sp) + 1262: 0a00001b .4byte 0xa00001b + 1266: 8402 jr s0 + 1268: 001c .2byte 0x1c + 126a: 0b00 addi s0,sp,400 + 126c: 1902 slli s2,s2,0x20 + 126e: 000c .2byte 0xc + 1270: 0c00 addi s0,sp,528 + 1272: c402 sw zero,8(sp) + 1274: 001e c.slli zero,0x7 + 1276: 0d00 addi s0,sp,656 + 1278: d402 sw zero,40(sp) + 127a: 001e c.slli zero,0x7 + 127c: 0e00 addi s0,sp,784 + 127e: e402 .2byte 0xe402 + 1280: 001e c.slli zero,0x7 + 1282: 0f00 addi s0,sp,912 + 1284: f402 .2byte 0xf402 + 1286: 001e c.slli zero,0x7 + 1288: 1000 addi s0,sp,32 + 128a: 0402 c.slli64 s0 + 128c: 001f 1100 1402 .byte 0x1f, 0x00, 0x00, 0x11, 0x02, 0x14 + 1292: 001f 1200 2402 .byte 0x1f, 0x00, 0x00, 0x12, 0x02, 0x24 + 1298: 001f 1300 3402 .byte 0x1f, 0x00, 0x00, 0x13, 0x02, 0x34 + 129e: 001f 1400 4402 .byte 0x1f, 0x00, 0x00, 0x14, 0x02, 0x44 + 12a4: 001f 1500 5402 .byte 0x1f, 0x00, 0x00, 0x15, 0x02, 0x54 + 12aa: 001f 1600 b102 .byte 0x1f, 0x00, 0x00, 0x16, 0x02, 0xb1 + 12b0: 0018 .2byte 0x18 + 12b2: 1700 addi s0,sp,928 + 12b4: c202 sw zero,4(sp) + 12b6: 0018 .2byte 0x18 + 12b8: 1800 addi s0,sp,48 + 12ba: d302 sw zero,164(sp) + 12bc: 0018 .2byte 0x18 + 12be: 1900 addi s0,sp,176 + 12c0: e402 .2byte 0xe402 + 12c2: 0018 .2byte 0x18 + 12c4: 1a00 addi s0,sp,304 + 12c6: f502 .2byte 0xf502 + 12c8: 0018 .2byte 0x18 + 12ca: 1b00 addi s0,sp,432 + 12cc: 0602 c.slli64 a2 + 12ce: 0019 c.nop 6 + 12d0: 1c00 addi s0,sp,560 + 12d2: 1f00 addi s0,sp,944 + 12d4: 00e2 slli ra,ra,0x18 + 12d6: 0000 unimp + 12d8: 00000b97 auipc s7,0x0 + 12dc: a619 j 15e2 <_free_r+0xf2> + 12de: 0000 unimp + 12e0: 1c00 addi s0,sp,560 + 12e2: 3800 .2byte 0x3800 + 12e4: 1984 addi s1,sp,240 + 12e6: 0000 unimp + 12e8: 2f01 jal 19f8 <__fini_array_end+0x2d8> + 12ea: 8711 srai a4,a4,0x4 + 12ec: 0500000b .4byte 0x500000b + 12f0: 00085003 lhu zero,0(a6) + 12f4: 1780 addi s0,sp,992 + 12f6: 0ebd addi t4,t4,15 + 12f8: 0000 unimp + 12fa: 3702 .2byte 0x3702 + 12fc: e20a .2byte 0xe20a + 12fe: 0000 unimp + 1300: 1700 addi s0,sp,928 + 1302: 0d7f .2byte 0xd7f + 1304: 0000 unimp + 1306: 3602 .2byte 0x3602 + 1308: e20a .2byte 0xe20a + 130a: 0000 unimp + 130c: 1700 addi s0,sp,928 + 130e: 000014cf .4byte 0x14cf + 1312: 3402 .2byte 0x3402 + 1314: e20a .2byte 0xe20a + 1316: 0000 unimp + 1318: 1700 addi s0,sp,928 + 131a: 0aa5 addi s5,s5,9 + 131c: 0000 unimp + 131e: 3302 .2byte 0x3302 + 1320: e20a .2byte 0xe20a + 1322: 0000 unimp + 1324: 2000 .2byte 0x2000 + 1326: 00000057 .4byte 0x57 + 132a: 000bea3f 010c2100 .8byte 0x10c2100000bea3f + 1332: 0000 unimp + 1334: 0039 c.nop 14 + 1336: fa20 .2byte 0xfa20 + 1338: 38000013 li zero,896 + 133c: 0bfa slli s7,s7,0x1e + 133e: 0000 unimp + 1340: fa21 bnez a2,1290 <_malloc_r+0x432> + 1342: 0000 unimp + 1344: 0000 unimp + 1346: cd20 sw s0,88(a0) + 1348: 0000 unimp + 134a: 3e00 .2byte 0x3e00 + 134c: 0c0a slli s8,s8,0x2 + 134e: 0000 unimp + 1350: 0c21 addi s8,s8,8 + 1352: 0001 nop + 1354: 0000 unimp + 1356: 000e7c17 auipc s8,0xe7 + 135a: 0700 addi s0,sp,896 + 135c: 0634 addi a3,sp,776 + 135e: 009a slli ra,ra,0x6 + 1360: 0000 unimp + 1362: 073a slli a4,a4,0xe + 1364: 0001 nop + 1366: 0100 addi s0,sp,128 + 1368: 030a slli t1,t1,0x2 + 136a: 9a05 andi a2,a2,-31 + 136c: 0000 unimp + 136e: c400 sw s0,8(s0) + 1370: 0008 .2byte 0x8 + 1372: 6400 .2byte 0x6400 + 1374: 0000 unimp + 1376: 0100 addi s0,sp,128 + 1378: c29c sw a5,0(a3) + 137a: 000c .2byte 0xc + 137c: 2a00 .2byte 0x2a00 + 137e: 1142 slli sp,sp,0x30 + 1380: 0000 unimp + 1382: 030a slli t1,t1,0x2 + 1384: 9a1f 0000 d700 .byte 0x1f, 0x9a, 0x00, 0x00, 0x00, 0xd7 + 138a: 0000 unimp + 138c: 3b00 .2byte 0x3b00 + 138e: 18a9 addi a7,a7,-22 + 1390: 0000 unimp + 1392: 0c01 addi s8,s8,0 # e8356 <__neorv32_ram_size+0xe6356> + 1394: 00e20c03 lb s8,14(tp) # e + 1398: 0000 unimp + 139a: 0100 addi s0,sp,128 + 139c: 4000 lw s0,0(s0) + 139e: 5d0e lw s10,224(sp) + 13a0: 0014 .2byte 0x14 + 13a2: 0d00 addi s0,sp,656 + 13a4: 00e20c03 lb s8,14(tp) # e + 13a8: 0000 unimp + 13aa: 00000123 sb zero,2(zero) # 2 + 13ae: 600e .2byte 0x600e + 13b0: 0019 c.nop 6 + 13b2: 1000 addi s0,sp,32 + 13b4: 00e20c03 lb s8,14(tp) # e + 13b8: 0000 unimp + 13ba: 0152 slli sp,sp,0x14 + 13bc: 0000 unimp + 13be: e909 bnez a0,13d0 <_malloc_r+0x572> + 13c0: c400001b .4byte 0xc400001b + 13c4: 0008 .2byte 0x8 + 13c6: 0400 addi s0,sp,512 + 13c8: 0000 unimp + 13ca: 0d00 addi s0,sp,656 + 13cc: 0c951603 lh a2,201(a0) + 13d0: 0000 unimp + 13d2: f706 .2byte 0xf706 + 13d4: a100001b .4byte 0xa100001b + 13d8: 0001 nop + 13da: 0700 addi s0,sp,896 + 13dc: 1c02 slli s8,s8,0x20 + 13de: 0000 unimp + 13e0: 0500 addi s0,sp,640 + 13e2: 08ec addi a1,sp,92 + 13e4: 0000 unimp + 13e6: 0c0a slli s8,s8,0x2 + 13e8: 0000 unimp + 13ea: 0811 addi a6,a6,4 + 13ec: 0009 c.nop 2 + 13ee: d900 sw s0,48(a0) + 13f0: 0300000b .4byte 0x300000b + 13f4: 5a01 li s4,-32 + 13f6: 0305 addi t1,t1,1 + 13f8: 1a18 addi a4,sp,304 + 13fa: 0000 unimp + 13fc: 055b0103 lb sp,85(s6) + 1400: 000c .2byte 0xc + 1402: 0001 nop + 1404: 0340 addi s0,sp,388 + 1406: 5c01 li s8,-32 + 1408: 066c9103 lh sp,102(s9) + 140c: 0000 unimp + 140e: e83c .2byte 0xe83c + 1410: 01000017 auipc zero,0x1000 + 1414: 02d6 slli t0,t0,0x15 + 1416: e20a .2byte 0xe20a + 1418: 0000 unimp + 141a: 0100 addi s0,sp,128 + 141c: 0ce1 addi s9,s9,24 + 141e: 0000 unimp + 1420: 00177b13 andi s6,a4,1 + 1424: d800 sw s0,48(s0) + 1426: 0c02 c.slli64 s8 + 1428: 00e2 slli ra,ra,0x18 + 142a: 0000 unimp + 142c: 1a00 addi s0,sp,304 + 142e: 0585 addi a1,a1,1 + 1430: 0000 unimp + 1432: 02a8 addi a0,sp,328 + ... + 143c: 9c01 .2byte 0x9c01 + 143e: 00000d13 li s10,0 + 1442: 0005 c.nop 1 + 1444: 0000 unimp + 1446: 0a00 addi s0,sp,272 + 1448: 000c .2byte 0xc + 144a: 1b00 addi s0,sp,432 + 144c: 0000 unimp + 144e: 0000 unimp + 1450: 0bfa slli s7,s7,0x1e + 1452: 0000 unimp + 1454: 055a0103 lb sp,85(s4) + 1458: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 145c: 0000 unimp + 145e: 1a00 addi s0,sp,304 + 1460: 056e slli a0,a0,0x1b + 1462: 0000 unimp + 1464: 027d addi tp,tp,31 # 1f + ... + 146e: 9c01 .2byte 0x9c01 + 1470: 0ddc addi a5,sp,724 + 1472: 0000 unimp + 1474: 001eb82b .4byte 0x1eb82b + 1478: 7f00 .2byte 0x7f00 + 147a: 1202 slli tp,tp,0x20 + 147c: 0ddc addi a5,sp,724 + 147e: 0000 unimp + 1480: 7ed09103 lh sp,2029(ra) + 1484: 7518 .2byte 0x7518 + 1486: 8b00 .2byte 0x8b00 + 1488: 0702 c.slli64 a4 + 148a: 009a slli ra,ra,0x6 + 148c: 0000 unimp + 148e: 8b00760f .4byte 0x8b00760f + 1492: 0902 c.slli64 s2 + 1494: 009a slli ra,ra,0x6 + 1496: 0000 unimp + 1498: 01b0 addi a2,sp,200 + 149a: 0000 unimp + 149c: 8b00770f .4byte 0x8b00770f + 14a0: 0b02 c.slli64 s6 + 14a2: 009a slli ra,ra,0x6 + 14a4: 0000 unimp + 14a6: 01c8 addi a0,sp,196 + 14a8: 0000 unimp + 14aa: 706d740f .4byte 0x706d740f + 14ae: 8c00 .2byte 0x8c00 + 14b0: 0c02 c.slli64 s8 + 14b2: 00c5 addi ra,ra,17 + 14b4: 0000 unimp + 14b6: 000001f3 .4byte 0x1f3 + 14ba: 8d00630f .4byte 0x8d00630f + 14be: 0802 c.slli64 a6 + 14c0: 00fa slli ra,ra,0x1e + 14c2: 0000 unimp + 14c4: 020a slli tp,tp,0x2 + 14c6: 0000 unimp + 14c8: 0004 .2byte 0x4 + 14ca: 0000 unimp + 14cc: bb00 .2byte 0xbb00 + 14ce: 0020 addi s0,sp,8 + 14d0: 9f00 .2byte 0x9f00 + 14d2: 000d c.nop 3 + 14d4: 0300 addi s0,sp,384 + 14d6: 5a01 li s4,-32 + 14d8: 7202 .2byte 0x7202 + 14da: 0300 addi s0,sp,384 + 14dc: 5b01 li s6,-32 + 14de: 0305 addi t1,t1,1 + 14e0: 0000 unimp + 14e2: 0000 unimp + 14e4: 025c0103 lb sp,37(s8) + 14e8: 7e08 .2byte 0x7e08 + 14ea: 0500 addi s0,sp,640 + 14ec: 0000 unimp + 14ee: 0000 unimp + 14f0: 0c0a slli s8,s8,0x2 + 14f2: 0000 unimp + 14f4: 0004 .2byte 0x4 + 14f6: 0000 unimp + 14f8: fa00 .2byte 0xfa00 + 14fa: bf00000b .4byte 0xbf00000b + 14fe: 000d c.nop 3 + 1500: 0300 addi s0,sp,384 + 1502: 5a01 li s4,-32 + 1504: 0305 addi t1,t1,1 + 1506: 0000 unimp + 1508: 0000 unimp + 150a: 0500 addi s0,sp,640 + 150c: 0000 unimp + 150e: 0000 unimp + 1510: 0bea slli s7,s7,0x1a + 1512: 0000 unimp + 1514: 0000001b .4byte 0x1b + 1518: fa00 .2byte 0xfa00 + 151a: 0300000b .4byte 0x300000b + 151e: 5a01 li s4,-32 + 1520: 0305 addi t1,t1,1 + 1522: 0000 unimp + 1524: 0000 unimp + 1526: 0000 unimp + 1528: d11f 0000 f200 .byte 0x1f, 0xd1, 0x00, 0x00, 0x00, 0xf2 + 152e: 000d c.nop 3 + 1530: 1900 addi s0,sp,176 + 1532: 00a6 slli ra,ra,0x9 + 1534: 0000 unimp + 1536: 1908 addi a0,sp,176 + 1538: 00a6 slli ra,ra,0x9 + 153a: 0000 unimp + 153c: 0006 c.slli zero,0x1 + 153e: a01a .2byte 0xa01a + 1540: 000d c.nop 3 + 1542: 6f00 .2byte 0x6f00 + 1544: 0002 c.slli64 zero + 1546: 0000 unimp + 1548: 0000 unimp + 154a: 0000 unimp + 154c: 0100 addi s0,sp,128 + 154e: 249c .2byte 0x249c + 1550: 000e c.slli zero,0x3 + 1552: 0500 addi s0,sp,640 + 1554: 0000 unimp + 1556: 0000 unimp + 1558: 0c0a slli s8,s8,0x2 + 155a: 0000 unimp + 155c: 0000001b .4byte 0x1b + 1560: fa00 .2byte 0xfa00 + 1562: 0300000b .4byte 0x300000b + 1566: 5a01 li s4,-32 + 1568: 0305 addi t1,t1,1 + 156a: 0000 unimp + 156c: 0000 unimp + 156e: 0000 unimp + 1570: 653d lui a0,0xf + 1572: 0014 .2byte 0x14 + 1574: 0100 addi s0,sp,128 + 1576: 024d addi tp,tp,19 # 13 + 1578: 0106 slli sp,sp,0x1 + 157a: 0e55 addi t3,t3,21 + 157c: 0000 unimp + 157e: 6918 .2byte 0x6918 + 1580: 4f00 lw s0,24(a4) + 1582: 0c02 c.slli64 s8 + 1584: 00e2 slli ra,ra,0x18 + 1586: 0000 unimp + 1588: 7418 .2byte 0x7418 + 158a: 706d c.lui zero,0xffffb + 158c: 5000 lw s0,32(s0) + 158e: 0802 c.slli64 a6 + 1590: 00fa slli ra,ra,0x1e + 1592: 0000 unimp + 1594: 6318 .2byte 0x6318 + 1596: 746e .2byte 0x746e + 1598: 5000 lw s0,32(s0) + 159a: 0d02 c.slli64 s10 + 159c: 00fa slli ra,ra,0x1e + 159e: 0000 unimp + 15a0: 2c00 .2byte 0x2c00 + 15a2: 159f 0000 023c .byte 0x9f, 0x15, 0x00, 0x00, 0x3c, 0x02 + 15a8: 9306 add t1,t1,ra + 15aa: 000e c.slli zero,0x3 + 15ac: 3e00 .2byte 0x3e00 + 15ae: 756e .2byte 0x756e + 15b0: 006d c.nop 27 + 15b2: 3c01 jal fc2 <_malloc_r+0x164> + 15b4: 2c02 .2byte 0x2c02 + 15b6: 00c5 addi ra,ra,17 + 15b8: 0000 unimp + 15ba: 000df513 andi a0,s11,0 + 15be: 3e00 .2byte 0x3e00 + 15c0: 1502 slli a0,a0,0x20 + 15c2: 00000ea3 sb zero,29(zero) # 1d + 15c6: 6918 .2byte 0x6918 + 15c8: 4200 lw s0,0(a2) + 15ca: 0702 c.slli64 a4 + 15cc: 009a slli ra,ra,0x6 + 15ce: 0000 unimp + 15d0: 132d addi t1,t1,-21 + 15d2: 0fe9 addi t6,t6,26 + 15d4: 0000 unimp + 15d6: 0244 addi s1,sp,260 + 15d8: e20e .2byte 0xe20e + 15da: 0000 unimp + 15dc: 0000 unimp + 15de: 1f00 addi s0,sp,944 + 15e0: 0101 addi sp,sp,0 + 15e2: 0000 unimp + 15e4: 00000ea3 sb zero,29(zero) # 1d + 15e8: a619 j 18ee <__fini_array_end+0x1ce> + 15ea: 0000 unimp + 15ec: 0f00 addi s0,sp,912 + 15ee: 1600 addi s0,sp,800 + 15f0: 00000e93 li t4,0 + 15f4: 192e slli s2,s2,0x2b + 15f6: 0010 .2byte 0x10 + 15f8: 2800 .2byte 0x2800 + 15fa: 0602 c.slli64 a2 + 15fc: 04f4 addi a3,sp,588 + 15fe: 0000 unimp + 1600: 0070 addi a2,sp,12 + 1602: 0000 unimp + 1604: 9c01 .2byte 0x9c01 + 1606: 0f26 slli t5,t5,0x9 + 1608: 0000 unimp + 160a: 6d756e3f 02280100 .8byte 0x22801006d756e3f + 1612: e22c .2byte 0xe22c + 1614: 0000 unimp + 1616: 2300 .2byte 0x2300 + 1618: 0002 c.slli64 zero + 161a: 2b00 .2byte 0x2b00 + 161c: 0df5 addi s11,s11,29 + 161e: 0000 unimp + 1620: 022a slli tp,tp,0xa + 1622: a315 j 1b46 <__RODATA_END__+0x76> + 1624: 000e c.slli zero,0x3 + 1626: 0500 addi s0,sp,640 + 1628: 001aa003 lw zero,1(s5) + 162c: 0f00 addi s0,sp,912 + 162e: 0069 c.nop 26 + 1630: 022e slli tp,tp,0xb + 1632: 00009a07 .4byte 0x9a07 + 1636: 4800 lw s0,16(s0) + 1638: 0002 c.slli64 zero + 163a: 2f00 .2byte 0x2f00 + 163c: 00b1 addi ra,ra,12 + 163e: 0000 unimp + 1640: 0f12 slli t5,t5,0x4 + 1642: 0000 unimp + 1644: e90e .2byte 0xe90e + 1646: 3000000f .4byte 0x3000000f + 164a: 0e02 c.slli64 t3 + 164c: 00e2 slli ra,ra,0x18 + 164e: 0000 unimp + 1650: 0255 addi tp,tp,21 # 15 + 1652: 0000 unimp + 1654: 4405 li s0,1 + 1656: 0005 c.nop 1 + 1658: ea00 .2byte 0xea00 + 165a: 0000000b .4byte 0xb + 165e: 2411 jal 1862 <__fini_array_end+0x142> + 1660: 0005 c.nop 1 + 1662: fa00 .2byte 0xfa00 + 1664: 0300000b .4byte 0x300000b + 1668: 5a01 li s4,-32 + 166a: 0305 addi t1,t1,1 + 166c: 182c addi a1,sp,56 + 166e: 0000 unimp + 1670: 0000 unimp + 1672: e12e .2byte 0xe12e + 1674: 000e c.slli zero,0x3 + 1676: 1500 addi s0,sp,672 + 1678: 0d02 c.slli64 s10 + ... + 1682: 9c01 .2byte 0x9c01 + 1684: 0f7a slli t5,t5,0x1e + 1686: 0000 unimp + 1688: 982a add a6,a6,a0 + 168a: 15000007 .4byte 0x15000007 + 168e: 2e02 .2byte 0x2e02 + 1690: 009a slli ra,ra,0x6 + 1692: 0000 unimp + 1694: 027a slli tp,tp,0x1e + 1696: 0000 unimp + 1698: 0004 .2byte 0x4 + 169a: 0000 unimp + 169c: ea00 .2byte 0xea00 + 169e: 6000000b .4byte 0x6000000b + 16a2: 0300000f fence rw,unknown + 16a6: 5a01 li s4,-32 + 16a8: 0802 c.slli64 a6 + 16aa: 0005005b .4byte 0x5005b + 16ae: 0000 unimp + 16b0: ea00 .2byte 0xea00 + 16b2: 1b00000b .4byte 0x1b00000b + 16b6: 0000 unimp + 16b8: 0000 unimp + 16ba: 0bea slli s7,s7,0x1a + 16bc: 0000 unimp + 16be: 025a0103 lb sp,37(s4) + 16c2: 5d08 lw a0,56(a0) + 16c4: 0000 unimp + 16c6: 912c .2byte 0x912c + 16c8: 0014 .2byte 0x14 + 16ca: 0400 addi s0,sp,512 + 16cc: 0d02 c.slli64 s10 + 16ce: 0f94 addi a3,sp,976 + 16d0: 0000 unimp + 16d2: 9840 .2byte 0x9840 + 16d4: 01000007 .4byte 0x1000007 + 16d8: 0204 addi s1,sp,256 + 16da: 9a30 .2byte 0x9a30 + 16dc: 0000 unimp + 16de: 0000 unimp + 16e0: 3b1a .2byte 0x3b1a + 16e2: 000d c.nop 3 + 16e4: 2000 .2byte 0x2000 + 16e6: 0001 nop + 16e8: 0000 unimp + 16ea: 0000 unimp + 16ec: 0000 unimp + 16ee: 0100 addi s0,sp,128 + 16f0: 149c addi a5,sp,608 + 16f2: 0019 c.nop 6 + 16f4: 0f00 addi s0,sp,912 + 16f6: 6d74 .2byte 0x6d74 + 16f8: 0070 addi a2,sp,12 + 16fa: 0126 slli sp,sp,0x9 + 16fc: e20c .2byte 0xe20c + 16fe: 0000 unimp + 1700: 9f00 .2byte 0x9f00 + 1702: 0002 c.slli64 zero + 1704: 0f00 addi s0,sp,912 + 1706: 0069 c.nop 26 + 1708: 9a070127 .4byte 0x9a070127 + 170c: 0000 unimp + 170e: fc00 .2byte 0xfc00 + 1710: 0002 c.slli64 zero + 1712: 0f00 addi s0,sp,912 + 1714: 01280063 beq a6,s2,1714 <_free_r+0x224> + 1718: fa08 .2byte 0xfa08 + 171a: 0000 unimp + 171c: 1400 addi s0,sp,544 + 171e: 0e000003 lb zero,224(zero) # e0 <__crt0_call_constructors_loop+0x4> + 1722: 00001c47 .4byte 0x1c47 + 1726: e20c0183 lb gp,-480(s8) + 172a: 0000 unimp + 172c: 2300 .2byte 0x2300 + 172e: 0e000003 lb zero,224(zero) # e0 <__crt0_call_constructors_loop+0x4> + 1732: 1326 slli t1,t1,0x29 + 1734: 0000 unimp + 1736: 018d addi gp,gp,3 # 7c9 <__neorv32_rte_debug_handler+0x265> + 1738: e20c .2byte 0xe20c + 173a: 0000 unimp + 173c: 5200 lw s0,32(a2) + 173e: 2f000003 lb zero,752(zero) # 2f0 <__neorv32_rte_core+0x44> + 1742: 01d1 addi gp,gp,20 # 80001054 <__global_pointer$+0x14> + 1744: 0000 unimp + 1746: 00001077 .4byte 0x1077 + 174a: 170e slli a4,a4,0x23 + 174c: 0019 c.nop 6 + 174e: bb00 .2byte 0xbb00 + 1750: 0e01 addi t3,t3,0 + 1752: 00e2 slli ra,ra,0x18 + 1754: 0000 unimp + 1756: 038d addi t2,t2,3 + 1758: 0000 unimp + 175a: 3d0e .2byte 0x3d0e + 175c: 0014 .2byte 0x14 + 175e: c300 sw s0,0(a4) + 1760: 0e01 addi t3,t3,0 + 1762: 00e2 slli ra,ra,0x18 + 1764: 0000 unimp + 1766: 03b1 addi t2,t2,12 + 1768: 0000 unimp + 176a: fd0e .2byte 0xfd0e + 176c: 0012 c.slli zero,0x4 + 176e: cb00 sw s0,16(a4) + 1770: 0e01 addi t3,t3,0 + 1772: 00e2 slli ra,ra,0x18 + 1774: 0000 unimp + 1776: 03d5 addi t2,t2,21 + 1778: 0000 unimp + 177a: 0004 .2byte 0x4 + 177c: 0000 unimp + 177e: d900 sw s0,48(a0) + 1780: 4500000b .4byte 0x4500000b + 1784: 0010 .2byte 0x10 + 1786: 0300 addi s0,sp,384 + 1788: 5a01 li s4,-32 + 178a: 0305 addi t1,t1,1 + 178c: 0000 unimp + 178e: 0000 unimp + 1790: 0500 addi s0,sp,640 + 1792: 0000 unimp + 1794: 0000 unimp + 1796: 20c6 .2byte 0x20c6 + 1798: 0000 unimp + 179a: 0011 c.nop 4 + 179c: 0000 unimp + 179e: d900 sw s0,48(a0) + 17a0: 0300000b .4byte 0x300000b + 17a4: 5a01 li s4,-32 + 17a6: 0305 addi t1,t1,1 + 17a8: 0000 unimp + 17aa: 0000 unimp + 17ac: 035c0103 lb sp,53(s8) + 17b0: 5c91 li s9,-28 + 17b2: 0306 slli t1,t1,0x1 + 17b4: 5d01 li s10,-32 + 17b6: 06549103 lh sp,101(s1) + 17ba: 035e0103 lb sp,53(t3) + 17be: 5891 li a7,-28 + 17c0: 0006 c.slli zero,0x1 + 17c2: 0900 addi s0,sp,144 + 17c4: 1be9 addi s7,s7,-6 # 12d2 <_malloc_r+0x474> + ... + 17ce: 0000 unimp + 17d0: 0130 addi a2,sp,136 + 17d2: 00109a4f .4byte 0x109a4f + 17d6: 0600 addi s0,sp,768 + 17d8: 00001bf7 .4byte 0x1bf7 + 17dc: 0404 addi s1,sp,512 + 17de: 0000 unimp + 17e0: 001c0207 .4byte 0x1c0207 + 17e4: 0000 unimp + 17e6: e909 bnez a0,17f8 <__fini_array_end+0xd8> + 17e8: 0000001b .4byte 0x1b + 17ec: 0000 unimp + 17ee: 0000 unimp + 17f0: 0000 unimp + 17f2: 3500 .2byte 0x3500 + 17f4: 0301 addi t1,t1,0 + 17f6: 10bd addi ra,ra,-17 + 17f8: 0000 unimp + 17fa: f706 .2byte 0xf706 + 17fc: 1300001b .4byte 0x1300001b + 1800: 0004 .2byte 0x4 + 1802: 0700 addi s0,sp,896 + 1804: 1c02 slli s8,s8,0x20 + 1806: 0000 unimp + 1808: 0900 addi s0,sp,144 + 180a: 1be9 addi s7,s7,-6 + ... + 1814: 0000 unimp + 1816: 0135 addi sp,sp,13 + 1818: 0010e003 .4byte 0x10e003 + 181c: 0600 addi s0,sp,768 + 181e: 00001bf7 .4byte 0x1bf7 + 1822: 0422 slli s0,s0,0x8 + 1824: 0000 unimp + 1826: 001c0207 .4byte 0x1c0207 + 182a: 0000 unimp + 182c: e909 bnez a0,183e <__fini_array_end+0x11e> + 182e: 0000001b .4byte 0x1b + 1832: 0000 unimp + 1834: 0000 unimp + 1836: 0000 unimp + 1838: 3500 .2byte 0x3500 + 183a: 0301 addi t1,t1,0 + 183c: 00001103 lh sp,0(zero) # 0 <__crt0_entry> + 1840: f706 .2byte 0xf706 + 1842: 3100001b .4byte 0x3100001b + 1846: 0004 .2byte 0x4 + 1848: 0700 addi s0,sp,896 + 184a: 1c02 slli s8,s8,0x20 + 184c: 0000 unimp + 184e: 0900 addi s0,sp,144 + 1850: 1be9 addi s7,s7,-6 + ... + 185a: 0000 unimp + 185c: 0135 addi sp,sp,13 + 185e: 00112603 lw a2,1(sp) + 1862: 0600 addi s0,sp,768 + 1864: 00001bf7 .4byte 0x1bf7 + 1868: 0440 addi s0,sp,516 + 186a: 0000 unimp + 186c: 001c0207 .4byte 0x1c0207 + 1870: 0000 unimp + 1872: e909 bnez a0,1884 <__fini_array_end+0x164> + 1874: 0000001b .4byte 0x1b + 1878: 0000 unimp + 187a: 0000 unimp + 187c: 0000 unimp + 187e: 4600 lw s0,8(a2) + 1880: 0901 addi s2,s2,0 + 1882: 1149 addi sp,sp,-14 + 1884: 0000 unimp + 1886: f706 .2byte 0xf706 + 1888: 4f00001b .4byte 0x4f00001b + 188c: 0004 .2byte 0x4 + 188e: 0700 addi s0,sp,896 + 1890: 1c02 slli s8,s8,0x20 + 1892: 0000 unimp + 1894: 0900 addi s0,sp,144 + 1896: 1be9 addi s7,s7,-6 + ... + 18a0: 0000 unimp + 18a2: 0151 addi sp,sp,20 + 18a4: 6c09 lui s8,0x2 + 18a6: 0011 c.nop 4 + 18a8: 0600 addi s0,sp,768 + 18aa: 00001bf7 .4byte 0x1bf7 + 18ae: 045e slli s0,s0,0x17 + 18b0: 0000 unimp + 18b2: 001c0207 .4byte 0x1c0207 + 18b6: 0000 unimp + 18b8: e909 bnez a0,18ca <__fini_array_end+0x1aa> + 18ba: 0000001b .4byte 0x1b + 18be: 0000 unimp + 18c0: 0000 unimp + 18c2: 0000 unimp + 18c4: 5b00 lw s0,48(a4) + 18c6: 0901 addi s2,s2,0 + 18c8: 0000118f .4byte 0x118f + 18cc: f706 .2byte 0xf706 + 18ce: 6d00001b .4byte 0x6d00001b + 18d2: 0004 .2byte 0x4 + 18d4: 0700 addi s0,sp,896 + 18d6: 1c02 slli s8,s8,0x20 + 18d8: 0000 unimp + 18da: 0500 addi s0,sp,640 + 18dc: 0000 unimp + 18de: 0000 unimp + 18e0: 0c0a slli s8,s8,0x2 + 18e2: 0000 unimp + 18e4: 0004 .2byte 0x4 + 18e6: 0000 unimp + 18e8: d900 sw s0,48(a0) + 18ea: af00000b .4byte 0xaf00000b + 18ee: 0011 c.nop 4 + 18f0: 0300 addi s0,sp,384 + 18f2: 5a01 li s4,-32 + 18f4: 0305 addi t1,t1,1 + 18f6: 0000 unimp + 18f8: 0000 unimp + 18fa: 0400 addi s0,sp,512 + 18fc: 0000 unimp + 18fe: 0000 unimp + 1900: 0bd9 addi s7,s7,22 + 1902: 0000 unimp + 1904: 11c6 slli gp,gp,0x31 + 1906: 0000 unimp + 1908: 055a0103 lb sp,85(s4) + 190c: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1910: 0000 unimp + 1912: 0004 .2byte 0x4 + 1914: 0000 unimp + 1916: d900 sw s0,48(a0) + 1918: dd00000b .4byte 0xdd00000b + 191c: 0011 c.nop 4 + 191e: 0300 addi s0,sp,384 + 1920: 5a01 li s4,-32 + 1922: 0305 addi t1,t1,1 + 1924: 0000 unimp + 1926: 0000 unimp + 1928: 0500 addi s0,sp,640 + 192a: 0000 unimp + 192c: 0000 unimp + 192e: 0f7a slli t5,t5,0x1e + 1930: 0000 unimp + 1932: 0004 .2byte 0x4 + 1934: 0000 unimp + 1936: d900 sw s0,48(a0) + 1938: fd00000b .4byte 0xfd00000b + 193c: 0011 c.nop 4 + 193e: 0300 addi s0,sp,384 + 1940: 5a01 li s4,-32 + 1942: 0305 addi t1,t1,1 + 1944: 0000 unimp + 1946: 0000 unimp + 1948: 0400 addi s0,sp,512 + 194a: 0000 unimp + 194c: 0000 unimp + 194e: 0bd9 addi s7,s7,22 + 1950: 0000 unimp + 1952: 1214 addi a3,sp,288 + 1954: 0000 unimp + 1956: 055a0103 lb sp,85(s4) + 195a: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 195e: 0000 unimp + 1960: 0005 c.nop 1 + 1962: 0000 unimp + 1964: 7a00 .2byte 0x7a00 + 1966: 0400000f fence o,unknown + 196a: 0000 unimp + 196c: 0000 unimp + 196e: 0bd9 addi s7,s7,22 + 1970: 0000 unimp + 1972: 1234 addi a3,sp,296 + 1974: 0000 unimp + 1976: 055a0103 lb sp,85(s4) + 197a: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 197e: 0000 unimp + 1980: 0004 .2byte 0x4 + 1982: 0000 unimp + 1984: d900 sw s0,48(a0) + 1986: 4b00000b .4byte 0x4b00000b + 198a: 0012 c.slli zero,0x4 + 198c: 0300 addi s0,sp,384 + 198e: 5a01 li s4,-32 + 1990: 0305 addi t1,t1,1 + 1992: 0000 unimp + 1994: 0000 unimp + 1996: 0500 addi s0,sp,640 + 1998: 0000 unimp + 199a: 0000 unimp + 199c: 0e24 addi s1,sp,792 + 199e: 0000 unimp + 19a0: 0004 .2byte 0x4 + 19a2: 0000 unimp + 19a4: d900 sw s0,48(a0) + 19a6: 6b00000b .4byte 0x6b00000b + 19aa: 0012 c.slli zero,0x4 + 19ac: 0300 addi s0,sp,384 + 19ae: 5a01 li s4,-32 + 19b0: 0305 addi t1,t1,1 + 19b2: 0000 unimp + 19b4: 0000 unimp + 19b6: 0400 addi s0,sp,512 + 19b8: 0000 unimp + 19ba: 0000 unimp + 19bc: 0bd9 addi s7,s7,22 + 19be: 0000 unimp + 19c0: 1282 slli t0,t0,0x20 + 19c2: 0000 unimp + 19c4: 055a0103 lb sp,85(s4) + 19c8: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 19cc: 0000 unimp + 19ce: 0005 c.nop 1 + 19d0: 0000 unimp + 19d2: d900 sw s0,48(a0) + 19d4: 0400000b .4byte 0x400000b + 19d8: 0000 unimp + 19da: 0000 unimp + 19dc: 0bd9 addi s7,s7,22 + 19de: 0000 unimp + 19e0: 12a2 slli t0,t0,0x28 + 19e2: 0000 unimp + 19e4: 055a0103 lb sp,85(s4) + 19e8: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 19ec: 0000 unimp + 19ee: 0004 .2byte 0x4 + 19f0: 0000 unimp + 19f2: ea00 .2byte 0xea00 + 19f4: b700000b .4byte 0xb700000b + 19f8: 0012 c.slli zero,0x4 + 19fa: 0300 addi s0,sp,384 + 19fc: 5a01 li s4,-32 + 19fe: 00c17803 .4byte 0xc17803 + 1a02: 0400 addi s0,sp,512 + 1a04: 0000 unimp + 1a06: 0000 unimp + 1a08: 0bea slli s7,s7,0x1a + 1a0a: 0000 unimp + 1a0c: 000012cb .4byte 0x12cb + 1a10: 025a0103 lb sp,37(s4) + 1a14: 2008 .2byte 0x2008 + 1a16: 0400 addi s0,sp,512 + 1a18: 0000 unimp + 1a1a: 0000 unimp + 1a1c: 0bd9 addi s7,s7,22 + 1a1e: 0000 unimp + 1a20: 12e2 slli t0,t0,0x38 + 1a22: 0000 unimp + 1a24: 055a0103 lb sp,85(s4) + 1a28: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1a2c: 0000 unimp + 1a2e: 0004 .2byte 0x4 + 1a30: 0000 unimp + 1a32: d900 sw s0,48(a0) + 1a34: f900000b .4byte 0xf900000b + 1a38: 0012 c.slli zero,0x4 + 1a3a: 0300 addi s0,sp,384 + 1a3c: 5a01 li s4,-32 + 1a3e: 0305 addi t1,t1,1 + 1a40: 0000 unimp + 1a42: 0000 unimp + 1a44: 0400 addi s0,sp,512 + 1a46: 0000 unimp + 1a48: 0000 unimp + 1a4a: 0bd9 addi s7,s7,22 + 1a4c: 0000 unimp + 1a4e: 1310 addi a2,sp,416 + 1a50: 0000 unimp + 1a52: 055a0103 lb sp,85(s4) + 1a56: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1a5a: 0000 unimp + 1a5c: 0004 .2byte 0x4 + 1a5e: 0000 unimp + 1a60: d900 sw s0,48(a0) + 1a62: 2700000b .4byte 0x2700000b + 1a66: 03000013 li zero,48 + 1a6a: 5a01 li s4,-32 + 1a6c: 0305 addi t1,t1,1 + 1a6e: 0000 unimp + 1a70: 0000 unimp + 1a72: 0400 addi s0,sp,512 + 1a74: 0000 unimp + 1a76: 0000 unimp + 1a78: 0bd9 addi s7,s7,22 + 1a7a: 0000 unimp + 1a7c: 133e slli t1,t1,0x2f + 1a7e: 0000 unimp + 1a80: 055a0103 lb sp,85(s4) + 1a84: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1a88: 0000 unimp + 1a8a: 0004 .2byte 0x4 + 1a8c: 0000 unimp + 1a8e: d900 sw s0,48(a0) + 1a90: 5500000b .4byte 0x5500000b + 1a94: 03000013 li zero,48 + 1a98: 5a01 li s4,-32 + 1a9a: 0305 addi t1,t1,1 + 1a9c: 0000 unimp + 1a9e: 0000 unimp + 1aa0: 0400 addi s0,sp,512 + 1aa2: 0000 unimp + 1aa4: 0000 unimp + 1aa6: 0bd9 addi s7,s7,22 + 1aa8: 0000 unimp + 1aaa: 136c addi a1,sp,428 + 1aac: 0000 unimp + 1aae: 055a0103 lb sp,85(s4) + 1ab2: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1ab6: 0000 unimp + 1ab8: 0004 .2byte 0x4 + 1aba: 0000 unimp + 1abc: d900 sw s0,48(a0) + 1abe: 8300000b .4byte 0x8300000b + 1ac2: 03000013 li zero,48 + 1ac6: 5a01 li s4,-32 + 1ac8: 0305 addi t1,t1,1 + 1aca: 0000 unimp + 1acc: 0000 unimp + 1ace: 0400 addi s0,sp,512 + 1ad0: 0000 unimp + 1ad2: 0000 unimp + 1ad4: 0bd9 addi s7,s7,22 + 1ad6: 0000 unimp + 1ad8: 139a slli t2,t2,0x26 + 1ada: 0000 unimp + 1adc: 055a0103 lb sp,85(s4) + 1ae0: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1ae4: 0000 unimp + 1ae6: 0004 .2byte 0x4 + 1ae8: 0000 unimp + 1aea: d900 sw s0,48(a0) + 1aec: b100000b .4byte 0xb100000b + 1af0: 03000013 li zero,48 + 1af4: 5a01 li s4,-32 + 1af6: 0305 addi t1,t1,1 + 1af8: 0000 unimp + 1afa: 0000 unimp + 1afc: 0400 addi s0,sp,512 + 1afe: 0000 unimp + 1b00: 0000 unimp + 1b02: 0bd9 addi s7,s7,22 + 1b04: 0000 unimp + 1b06: 13c8 addi a0,sp,484 + 1b08: 0000 unimp + 1b0a: 055a0103 lb sp,85(s4) + 1b0e: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1b12: 0000 unimp + 1b14: 0004 .2byte 0x4 + 1b16: 0000 unimp + 1b18: d900 sw s0,48(a0) + 1b1a: df00000b .4byte 0xdf00000b + 1b1e: 03000013 li zero,48 + 1b22: 5a01 li s4,-32 + 1b24: 0305 addi t1,t1,1 + 1b26: 0000 unimp + 1b28: 0000 unimp + 1b2a: 0400 addi s0,sp,512 + 1b2c: 0000 unimp + 1b2e: 0000 unimp + 1b30: 0bd9 addi s7,s7,22 + 1b32: 0000 unimp + 1b34: 13f6 slli t2,t2,0x3d + 1b36: 0000 unimp + 1b38: 055a0103 lb sp,85(s4) + 1b3c: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1b40: 0000 unimp + 1b42: 0005 c.nop 1 + 1b44: 0000 unimp + 1b46: cd00 sw s0,24(a0) + 1b48: 0500000b .4byte 0x500000b + 1b4c: 0000 unimp + 1b4e: 0000 unimp + 1b50: 0bc1 addi s7,s7,16 + 1b52: 0000 unimp + 1b54: 0004 .2byte 0x4 + 1b56: 0000 unimp + 1b58: d900 sw s0,48(a0) + 1b5a: 2600000b .4byte 0x2600000b + 1b5e: 0014 .2byte 0x14 + 1b60: 0300 addi s0,sp,384 + 1b62: 5a01 li s4,-32 + 1b64: 0305 addi t1,t1,1 + 1b66: 0000 unimp + 1b68: 0000 unimp + 1b6a: 035b0103 lb sp,53(s6) + 1b6e: 5491 li s1,-28 + 1b70: 0006 c.slli zero,0x1 + 1b72: 0004 .2byte 0x4 + 1b74: 0000 unimp + 1b76: d900 sw s0,48(a0) + 1b78: 3d00000b .4byte 0x3d00000b + 1b7c: 0014 .2byte 0x14 + 1b7e: 0300 addi s0,sp,384 + 1b80: 5a01 li s4,-32 + 1b82: 0305 addi t1,t1,1 + 1b84: 0000 unimp + 1b86: 0000 unimp + 1b88: 0500 addi s0,sp,640 + 1b8a: 0000 unimp + 1b8c: 0000 unimp + 1b8e: 0bb5 addi s7,s7,13 + 1b90: 0000 unimp + 1b92: 0005 c.nop 1 + 1b94: 0000 unimp + 1b96: a900 .2byte 0xa900 + 1b98: 0400000b .4byte 0x400000b + 1b9c: 0000 unimp + 1b9e: 0000 unimp + 1ba0: 0bd9 addi s7,s7,22 + 1ba2: 0000 unimp + 1ba4: 146d addi s0,s0,-5 + 1ba6: 0000 unimp + 1ba8: 055a0103 lb sp,85(s4) + 1bac: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1bb0: 0300 addi s0,sp,384 + 1bb2: 5b01 li s6,-32 + 1bb4: 06549103 lh sp,101(s1) + 1bb8: 0400 addi s0,sp,512 + 1bba: 0000 unimp + 1bbc: 0000 unimp + 1bbe: 0bd9 addi s7,s7,22 + 1bc0: 0000 unimp + 1bc2: 1484 addi s1,sp,608 + 1bc4: 0000 unimp + 1bc6: 055a0103 lb sp,85(s4) + 1bca: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1bce: 0000 unimp + 1bd0: 0004 .2byte 0x4 + 1bd2: 0000 unimp + 1bd4: d900 sw s0,48(a0) + 1bd6: 9b00000b .4byte 0x9b00000b + 1bda: 0014 .2byte 0x14 + 1bdc: 0300 addi s0,sp,384 + 1bde: 5a01 li s4,-32 + 1be0: 0305 addi t1,t1,1 + 1be2: 0000 unimp + 1be4: 0000 unimp + 1be6: 0400 addi s0,sp,512 + 1be8: 0000 unimp + 1bea: 0000 unimp + 1bec: 0bd9 addi s7,s7,22 + 1bee: 0000 unimp + 1bf0: 14b2 slli s1,s1,0x2c + 1bf2: 0000 unimp + 1bf4: 055a0103 lb sp,85(s4) + 1bf8: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1bfc: 0000 unimp + 1bfe: 0004 .2byte 0x4 + 1c00: 0000 unimp + 1c02: d900 sw s0,48(a0) + 1c04: c900000b .4byte 0xc900000b + 1c08: 0014 .2byte 0x14 + 1c0a: 0300 addi s0,sp,384 + 1c0c: 5a01 li s4,-32 + 1c0e: 0305 addi t1,t1,1 + 1c10: 0000 unimp + 1c12: 0000 unimp + 1c14: 0400 addi s0,sp,512 + 1c16: 0000 unimp + 1c18: 0000 unimp + 1c1a: 0bd9 addi s7,s7,22 + 1c1c: 0000 unimp + 1c1e: 14e0 addi s0,sp,620 + 1c20: 0000 unimp + 1c22: 055a0103 lb sp,85(s4) + 1c26: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1c2a: 0000 unimp + 1c2c: 0004 .2byte 0x4 + 1c2e: 0000 unimp + 1c30: d900 sw s0,48(a0) + 1c32: f700000b .4byte 0xf700000b + 1c36: 0014 .2byte 0x14 + 1c38: 0300 addi s0,sp,384 + 1c3a: 5a01 li s4,-32 + 1c3c: 0305 addi t1,t1,1 + 1c3e: 0000 unimp + 1c40: 0000 unimp + 1c42: 0400 addi s0,sp,512 + 1c44: 0000 unimp + 1c46: 0000 unimp + 1c48: 0bd9 addi s7,s7,22 + 1c4a: 0000 unimp + 1c4c: 150e slli a0,a0,0x23 + 1c4e: 0000 unimp + 1c50: 055a0103 lb sp,85(s4) + 1c54: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1c58: 0000 unimp + 1c5a: 0004 .2byte 0x4 + 1c5c: 0000 unimp + 1c5e: d900 sw s0,48(a0) + 1c60: 2500000b .4byte 0x2500000b + 1c64: 0015 c.nop 5 + 1c66: 0300 addi s0,sp,384 + 1c68: 5a01 li s4,-32 + 1c6a: 0305 addi t1,t1,1 + 1c6c: 0000 unimp + 1c6e: 0000 unimp + 1c70: 0400 addi s0,sp,512 + 1c72: 0000 unimp + 1c74: 0000 unimp + 1c76: 0bd9 addi s7,s7,22 + 1c78: 0000 unimp + 1c7a: 153c addi a5,sp,680 + 1c7c: 0000 unimp + 1c7e: 055a0103 lb sp,85(s4) + 1c82: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1c86: 0000 unimp + 1c88: 0004 .2byte 0x4 + 1c8a: 0000 unimp + 1c8c: d900 sw s0,48(a0) + 1c8e: 5300000b .4byte 0x5300000b + 1c92: 0015 c.nop 5 + 1c94: 0300 addi s0,sp,384 + 1c96: 5a01 li s4,-32 + 1c98: 0305 addi t1,t1,1 + 1c9a: 0000 unimp + 1c9c: 0000 unimp + 1c9e: 0500 addi s0,sp,640 + 1ca0: 0000 unimp + 1ca2: 0000 unimp + 1ca4: 0bd9 addi s7,s7,22 + 1ca6: 0000 unimp + 1ca8: 0004 .2byte 0x4 + 1caa: 0000 unimp + 1cac: d900 sw s0,48(a0) + 1cae: 7300000b .4byte 0x7300000b + 1cb2: 0015 c.nop 5 + 1cb4: 0300 addi s0,sp,384 + 1cb6: 5a01 li s4,-32 + 1cb8: 0305 addi t1,t1,1 + 1cba: 0000 unimp + 1cbc: 0000 unimp + 1cbe: 0500 addi s0,sp,640 + 1cc0: 0000 unimp + 1cc2: 0000 unimp + 1cc4: 0f7a slli t5,t5,0x1e + 1cc6: 0000 unimp + 1cc8: 0004 .2byte 0x4 + 1cca: 0000 unimp + 1ccc: d900 sw s0,48(a0) + 1cce: 9300000b .4byte 0x9300000b + 1cd2: 0015 c.nop 5 + 1cd4: 0300 addi s0,sp,384 + 1cd6: 5a01 li s4,-32 + 1cd8: 0305 addi t1,t1,1 + 1cda: 0000 unimp + 1cdc: 0000 unimp + 1cde: 0500 addi s0,sp,640 + 1ce0: 0000 unimp + 1ce2: 0000 unimp + 1ce4: 0bd9 addi s7,s7,22 + 1ce6: 0000 unimp + 1ce8: 0004 .2byte 0x4 + 1cea: 0000 unimp + 1cec: d900 sw s0,48(a0) + 1cee: b300000b .4byte 0xb300000b + 1cf2: 0015 c.nop 5 + 1cf4: 0300 addi s0,sp,384 + 1cf6: 5a01 li s4,-32 + 1cf8: 0305 addi t1,t1,1 + 1cfa: 0000 unimp + 1cfc: 0000 unimp + 1cfe: 0400 addi s0,sp,512 + 1d00: 0000 unimp + 1d02: 0000 unimp + 1d04: 0f26 slli t5,t5,0x9 + 1d06: 0000 unimp + 1d08: 000015cb .4byte 0x15cb + 1d0c: 065a0103 lb sp,101(s4) + 1d10: 0078 addi a4,sp,12 + 1d12: 3c40 .2byte 0x3c40 + 1d14: 1a24 addi s1,sp,312 + 1d16: 0400 addi s0,sp,512 + 1d18: 0000 unimp + 1d1a: 0000 unimp + 1d1c: 0bd9 addi s7,s7,22 + 1d1e: 0000 unimp + 1d20: 15e2 slli a1,a1,0x38 + 1d22: 0000 unimp + 1d24: 055a0103 lb sp,85(s4) + 1d28: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1d2c: 0000 unimp + 1d2e: 0004 .2byte 0x4 + 1d30: 0000 unimp + 1d32: 2600 .2byte 0x2600 + 1d34: fa00000f .4byte 0xfa00000f + 1d38: 0015 c.nop 5 + 1d3a: 0300 addi s0,sp,384 + 1d3c: 5a01 li s4,-32 + 1d3e: 7806 .2byte 0x7806 + 1d40: 4000 lw s0,0(s0) + 1d42: 243d jal 1f70 <__RODATA_END__+0x4a0> + 1d44: 001a c.slli zero,0x6 + 1d46: 0004 .2byte 0x4 + 1d48: 0000 unimp + 1d4a: d900 sw s0,48(a0) + 1d4c: 1100000b .4byte 0x1100000b + 1d50: 0016 c.slli zero,0x5 + 1d52: 0300 addi s0,sp,384 + 1d54: 5a01 li s4,-32 + 1d56: 0305 addi t1,t1,1 + 1d58: 0000 unimp + 1d5a: 0000 unimp + 1d5c: 0400 addi s0,sp,512 + 1d5e: 0000 unimp + 1d60: 0000 unimp + 1d62: 0f26 slli t5,t5,0x9 + 1d64: 0000 unimp + 1d66: 1629 addi a2,a2,-22 + 1d68: 0000 unimp + 1d6a: 065a0103 lb sp,101(s4) + 1d6e: 0078 addi a4,sp,12 + 1d70: 3e40 .2byte 0x3e40 + 1d72: 1a24 addi s1,sp,312 + 1d74: 0400 addi s0,sp,512 + 1d76: 0000 unimp + 1d78: 0000 unimp + 1d7a: 0bd9 addi s7,s7,22 + 1d7c: 0000 unimp + 1d7e: 1640 addi s0,sp,804 + 1d80: 0000 unimp + 1d82: 055a0103 lb sp,85(s4) + 1d86: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1d8a: 0000 unimp + 1d8c: 0004 .2byte 0x4 + 1d8e: 0000 unimp + 1d90: 2600 .2byte 0x2600 + 1d92: 5800000f .4byte 0x5800000f + 1d96: 0016 c.slli zero,0x5 + 1d98: 0300 addi s0,sp,384 + 1d9a: 5a01 li s4,-32 + 1d9c: 7806 .2byte 0x7806 + 1d9e: 4000 lw s0,0(s0) + 1da0: 2446 .2byte 0x2446 + 1da2: 001a c.slli zero,0x6 + 1da4: 0004 .2byte 0x4 + 1da6: 0000 unimp + 1da8: d900 sw s0,48(a0) + 1daa: 6f00000b .4byte 0x6f00000b + 1dae: 0016 c.slli zero,0x5 + 1db0: 0300 addi s0,sp,384 + 1db2: 5a01 li s4,-32 + 1db4: 0305 addi t1,t1,1 + 1db6: 0000 unimp + 1db8: 0000 unimp + 1dba: 0400 addi s0,sp,512 + 1dbc: 0000 unimp + 1dbe: 0000 unimp + 1dc0: 0f26 slli t5,t5,0x9 + 1dc2: 0000 unimp + 1dc4: 00001687 .4byte 0x1687 + 1dc8: 065a0103 lb sp,101(s4) + 1dcc: 0078 addi a4,sp,12 + 1dce: 3f40 .2byte 0x3f40 + 1dd0: 1a24 addi s1,sp,312 + 1dd2: 0400 addi s0,sp,512 + 1dd4: 0000 unimp + 1dd6: 0000 unimp + 1dd8: 0bd9 addi s7,s7,22 + 1dda: 0000 unimp + 1ddc: 169e slli a3,a3,0x27 + 1dde: 0000 unimp + 1de0: 055a0103 lb sp,85(s4) + 1de4: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1de8: 0000 unimp + 1dea: 0004 .2byte 0x4 + 1dec: 0000 unimp + 1dee: 2600 .2byte 0x2600 + 1df0: b600000f .4byte 0xb600000f + 1df4: 0016 c.slli zero,0x5 + 1df6: 0300 addi s0,sp,384 + 1df8: 5a01 li s4,-32 + 1dfa: 7806 .2byte 0x7806 + 1dfc: 4000 lw s0,0(s0) + 1dfe: 2440 .2byte 0x2440 + 1e00: 001a c.slli zero,0x6 + 1e02: 0004 .2byte 0x4 + 1e04: 0000 unimp + 1e06: d900 sw s0,48(a0) + 1e08: cd00000b .4byte 0xcd00000b + 1e0c: 0016 c.slli zero,0x5 + 1e0e: 0300 addi s0,sp,384 + 1e10: 5a01 li s4,-32 + 1e12: 0305 addi t1,t1,1 + 1e14: 0000 unimp + 1e16: 0000 unimp + 1e18: 0400 addi s0,sp,512 + 1e1a: 0000 unimp + 1e1c: 0000 unimp + 1e1e: 0f26 slli t5,t5,0x9 + 1e20: 0000 unimp + 1e22: 16e5 addi a3,a3,-7 + 1e24: 0000 unimp + 1e26: 065a0103 lb sp,101(s4) + 1e2a: 0078 addi a4,sp,12 + 1e2c: 4140 lw s0,4(a0) + 1e2e: 1a24 addi s1,sp,312 + 1e30: 0400 addi s0,sp,512 + 1e32: 0000 unimp + 1e34: 0000 unimp + 1e36: 0bd9 addi s7,s7,22 + 1e38: 0000 unimp + 1e3a: 16fc addi a5,sp,876 + 1e3c: 0000 unimp + 1e3e: 055a0103 lb sp,85(s4) + 1e42: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1e46: 0000 unimp + 1e48: 0004 .2byte 0x4 + 1e4a: 0000 unimp + 1e4c: 2600 .2byte 0x2600 + 1e4e: 1400000f .4byte 0x1400000f + 1e52: 03000017 auipc zero,0x3000 + 1e56: 5a01 li s4,-32 + 1e58: 7806 .2byte 0x7806 + 1e5a: 4000 lw s0,0(s0) + 1e5c: 2442 .2byte 0x2442 + 1e5e: 001a c.slli zero,0x6 + 1e60: 0004 .2byte 0x4 + 1e62: 0000 unimp + 1e64: d900 sw s0,48(a0) + 1e66: 2b00000b .4byte 0x2b00000b + 1e6a: 03000017 auipc zero,0x3000 + 1e6e: 5a01 li s4,-32 + 1e70: 0305 addi t1,t1,1 + 1e72: 0000 unimp + 1e74: 0000 unimp + 1e76: 0400 addi s0,sp,512 + 1e78: 0000 unimp + 1e7a: 0000 unimp + 1e7c: 0f26 slli t5,t5,0x9 + 1e7e: 0000 unimp + 1e80: 00001743 .4byte 0x1743 + 1e84: 065a0103 lb sp,101(s4) + 1e88: 0078 addi a4,sp,12 + 1e8a: 4440 lw s0,12(s0) + 1e8c: 1a24 addi s1,sp,312 + 1e8e: 0400 addi s0,sp,512 + 1e90: 0000 unimp + 1e92: 0000 unimp + 1e94: 0bd9 addi s7,s7,22 + 1e96: 0000 unimp + 1e98: 175a slli a4,a4,0x36 + 1e9a: 0000 unimp + 1e9c: 055a0103 lb sp,85(s4) + 1ea0: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1ea4: 0000 unimp + 1ea6: 0004 .2byte 0x4 + 1ea8: 0000 unimp + 1eaa: 2600 .2byte 0x2600 + 1eac: 7200000f .4byte 0x7200000f + 1eb0: 03000017 auipc zero,0x3000 + 1eb4: 5a01 li s4,-32 + 1eb6: 7806 .2byte 0x7806 + 1eb8: 4000 lw s0,0(s0) + 1eba: 001a2443 .4byte 0x1a2443 + 1ebe: 0004 .2byte 0x4 + 1ec0: 0000 unimp + 1ec2: d900 sw s0,48(a0) + 1ec4: 8900000b .4byte 0x8900000b + 1ec8: 03000017 auipc zero,0x3000 + 1ecc: 5a01 li s4,-32 + 1ece: 0305 addi t1,t1,1 + 1ed0: 0000 unimp + 1ed2: 0000 unimp + 1ed4: 0400 addi s0,sp,512 + 1ed6: 0000 unimp + 1ed8: 0000 unimp + 1eda: 0f26 slli t5,t5,0x9 + 1edc: 0000 unimp + 1ede: 17a1 addi a5,a5,-24 + 1ee0: 0000 unimp + 1ee2: 065a0103 lb sp,101(s4) + 1ee6: 0078 addi a4,sp,12 + 1ee8: 4540 lw s0,12(a0) + 1eea: 1a24 addi s1,sp,312 + 1eec: 0400 addi s0,sp,512 + 1eee: 0000 unimp + 1ef0: 0000 unimp + 1ef2: 0bd9 addi s7,s7,22 + 1ef4: 0000 unimp + 1ef6: 17b8 addi a4,sp,1000 + 1ef8: 0000 unimp + 1efa: 055a0103 lb sp,85(s4) + 1efe: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1f02: 0000 unimp + 1f04: 0004 .2byte 0x4 + 1f06: 0000 unimp + 1f08: 2600 .2byte 0x2600 + 1f0a: d000000f .4byte 0xd000000f + 1f0e: 03000017 auipc zero,0x3000 + 1f12: 5a01 li s4,-32 + 1f14: 7806 .2byte 0x7806 + 1f16: 4000 lw s0,0(s0) + 1f18: 001a2447 .4byte 0x1a2447 + 1f1c: 0004 .2byte 0x4 + 1f1e: 0000 unimp + 1f20: d900 sw s0,48(a0) + 1f22: e700000b .4byte 0xe700000b + 1f26: 03000017 auipc zero,0x3000 + 1f2a: 5a01 li s4,-32 + 1f2c: 0305 addi t1,t1,1 + 1f2e: 0000 unimp + 1f30: 0000 unimp + 1f32: 0400 addi s0,sp,512 + 1f34: 0000 unimp + 1f36: 0000 unimp + 1f38: 0f26 slli t5,t5,0x9 + 1f3a: 0000 unimp + 1f3c: 17ff .2byte 0x17ff + 1f3e: 0000 unimp + 1f40: 065a0103 lb sp,101(s4) + 1f44: 0078 addi a4,sp,12 + 1f46: 4840 lw s0,20(s0) + 1f48: 1a24 addi s1,sp,312 + 1f4a: 0400 addi s0,sp,512 + 1f4c: 0000 unimp + 1f4e: 0000 unimp + 1f50: 0bd9 addi s7,s7,22 + 1f52: 0000 unimp + 1f54: 1816 slli a6,a6,0x25 + 1f56: 0000 unimp + 1f58: 055a0103 lb sp,85(s4) + 1f5c: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1f60: 0000 unimp + 1f62: 0004 .2byte 0x4 + 1f64: 0000 unimp + 1f66: 2600 .2byte 0x2600 + 1f68: 2e00000f .4byte 0x2e00000f + 1f6c: 0018 .2byte 0x18 + 1f6e: 0300 addi s0,sp,384 + 1f70: 5a01 li s4,-32 + 1f72: 7806 .2byte 0x7806 + 1f74: 4000 lw s0,0(s0) + 1f76: 2449 jal 21f8 <__neorv32_ram_size+0x1f8> + 1f78: 001a c.slli zero,0x6 + 1f7a: 0004 .2byte 0x4 + 1f7c: 0000 unimp + 1f7e: d900 sw s0,48(a0) + 1f80: 4500000b .4byte 0x4500000b + 1f84: 0018 .2byte 0x18 + 1f86: 0300 addi s0,sp,384 + 1f88: 5a01 li s4,-32 + 1f8a: 0305 addi t1,t1,1 + 1f8c: 0000 unimp + 1f8e: 0000 unimp + 1f90: 0400 addi s0,sp,512 + 1f92: 0000 unimp + 1f94: 0000 unimp + 1f96: 0f26 slli t5,t5,0x9 + 1f98: 0000 unimp + 1f9a: 185d addi a6,a6,-9 + 1f9c: 0000 unimp + 1f9e: 065a0103 lb sp,101(s4) + 1fa2: 0078 addi a4,sp,12 + 1fa4: 4a40 lw s0,20(a2) + 1fa6: 1a24 addi s1,sp,312 + 1fa8: 0400 addi s0,sp,512 + 1faa: 0000 unimp + 1fac: 0000 unimp + 1fae: 0bd9 addi s7,s7,22 + 1fb0: 0000 unimp + 1fb2: 1874 addi a3,sp,60 + 1fb4: 0000 unimp + 1fb6: 055a0103 lb sp,85(s4) + 1fba: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1fbe: 0000 unimp + 1fc0: 0004 .2byte 0x4 + 1fc2: 0000 unimp + 1fc4: 2600 .2byte 0x2600 + 1fc6: 8d00000f .4byte 0x8d00000f + 1fca: 0018 .2byte 0x18 + 1fcc: 0300 addi s0,sp,384 + 1fce: 5a01 li s4,-32 + 1fd0: 40007807 .4byte 0x40007807 + 1fd4: 1a1f244b .4byte 0x1a1f244b + 1fd8: 3000 .2byte 0x3000 + 1fda: 0000 unimp + 1fdc: 0000 unimp + 1fde: 0bd9 addi s7,s7,22 + 1fe0: 0000 unimp + 1fe2: 18a4 addi s1,sp,120 + 1fe4: 0000 unimp + 1fe6: 055a0103 lb sp,85(s4) + 1fea: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 1fee: 0000 unimp + 1ff0: 0004 .2byte 0x4 + 1ff2: 0000 unimp + 1ff4: d900 sw s0,48(a0) + 1ff6: bb00000b .4byte 0xbb00000b + 1ffa: 0018 .2byte 0x18 + 1ffc: 0300 addi s0,sp,384 + 1ffe: 5a01 li s4,-32 + 2000: 0305 addi t1,t1,1 + 2002: 0000 unimp + 2004: 0000 unimp + 2006: 0400 addi s0,sp,512 + 2008: 0000 unimp + 200a: 0000 unimp + 200c: 0bd9 addi s7,s7,22 + 200e: 0000 unimp + 2010: 18d2 slli a7,a7,0x34 + 2012: 0000 unimp + 2014: 055a0103 lb sp,85(s4) + 2018: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 201c: 0000 unimp + 201e: 0004 .2byte 0x4 + 2020: 0000 unimp + 2022: d900 sw s0,48(a0) + 2024: e900000b .4byte 0xe900000b + 2028: 0018 .2byte 0x18 + 202a: 0300 addi s0,sp,384 + 202c: 5a01 li s4,-32 + 202e: 0305 addi t1,t1,1 + 2030: 0000 unimp + 2032: 0000 unimp + 2034: 0400 addi s0,sp,512 + 2036: 0000 unimp + 2038: 0000 unimp + 203a: 0bd9 addi s7,s7,22 + 203c: 0000 unimp + 203e: 1900 addi s0,sp,176 + 2040: 0000 unimp + 2042: 055a0103 lb sp,85(s4) + 2046: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 204a: 0000 unimp + 204c: 0011 c.nop 4 + 204e: 0000 unimp + 2050: d900 sw s0,48(a0) + 2052: 0300000b .4byte 0x300000b + 2056: 5a01 li s4,-32 + 2058: 0305 addi t1,t1,1 + 205a: 0000 unimp + 205c: 0000 unimp + 205e: 0000 unimp + 2060: d041 beqz s0,1fe0 <__RODATA_END__+0x510> + 2062: 001c .2byte 0x1c + 2064: 0100 addi s0,sp,128 + 2066: 0dc6 slli s11,s11,0x11 + 2068: 6601 .2byte 0x6601 + 206a: 0019 c.nop 6 + 206c: 1200 addi s0,sp,288 + 206e: 000017b7 lui a5,0x1 + 2072: d001 beqz s0,1f72 <__RODATA_END__+0x4a2> + 2074: e20c .2byte 0xe20c + 2076: 0000 unimp + 2078: 1300 addi s0,sp,416 + 207a: 067f .2byte 0x67f + 207c: 0000 unimp + 207e: 0104 addi s1,sp,128 + 2080: e20c .2byte 0xe20c + 2082: 0000 unimp + 2084: 4200 lw s0,0(a2) + 2086: 0000194b .4byte 0x194b + 208a: 4c12 lw s8,4(sp) + 208c: 0018 .2byte 0x18 + 208e: 0100 addi s0,sp,128 + 2090: 0ef4 addi a3,sp,860 + 2092: 00e2 slli ra,ra,0x18 + 2094: 0000 unimp + 2096: 2d00 .2byte 0x2d00 + 2098: 001c9113 slli sp,s9,0x1 + 209c: 0a00 addi s0,sp,272 + 209e: 0e01 addi t3,t3,0 + 20a0: 00e2 slli ra,ra,0x18 + 20a2: 0000 unimp + 20a4: 00188a13 addi s4,a7,1 + 20a8: 0b00 addi s0,sp,400 + 20aa: 0e01 addi t3,t3,0 + 20ac: 00e2 slli ra,ra,0x18 + 20ae: 0000 unimp + 20b0: 0000 unimp + 20b2: 000f0d43 .4byte 0xf0d43 + 20b6: 0100 addi s0,sp,128 + 20b8: 4880 lw s0,16(s1) + 20ba: ac04 .2byte 0xac04 + 20bc: 0002 c.slli64 zero + 20be: 4800 lw s0,16(s0) + 20c0: 0002 c.slli64 zero + 20c2: 0100 addi s0,sp,128 + 20c4: a09c .2byte 0xa09c + 20c6: 001a c.slli zero,0x6 + 20c8: 1c00 addi s0,sp,560 + 20ca: 0ad5 addi s5,s5,21 + 20cc: 0000 unimp + 20ce: 0c82 c.slli64 s9 + 20d0: 00e2 slli ra,ra,0x18 + 20d2: 0000 unimp + 20d4: 047c addi a5,sp,524 + 20d6: 0000 unimp + 20d8: 461c lw a5,8(a2) + 20da: 001d c.nop 7 + 20dc: 8500 .2byte 0x8500 + 20de: e20c .2byte 0xe20c + 20e0: 0000 unimp + 20e2: 9300 .2byte 0x9300 + 20e4: 0004 .2byte 0x4 + 20e6: 1c00 addi s0,sp,560 + 20e8: 1036 c.slli zero,0x2d + 20ea: 0000 unimp + 20ec: 0aa8 addi a0,sp,344 + 20ee: 0106 slli sp,sp,0x1 + 20f0: 0000 unimp + 20f2: 00000493 li s1,0 + 20f6: 5c44 lw s1,60(s0) + 20f8: 34000003 lb zero,832(zero) # 340 <__neorv32_rte_core+0x94> + 20fc: 0000 unimp + 20fe: 6e00 .2byte 0x6e00 + 2100: 001a c.slli zero,0x6 + 2102: 1c00 addi s0,sp,560 + 2104: 0000067b .4byte 0x67b + 2108: 0eb0 addi a2,sp,856 + 210a: 00e2 slli ra,ra,0x18 + 210c: 0000 unimp + 210e: 066d addi a2,a2,27 + 2110: 0000 unimp + 2112: ef12 .2byte 0xef12 + 2114: 0100000f fence w,unknown + 2118: 00e20eb3 add t4,tp,a4 + 211c: 0000 unimp + 211e: e914 .2byte 0xe914 + 2120: 5c00001b .4byte 0x5c00001b + 2124: 04000003 lb zero,64(zero) # 40 + 2128: 0000 unimp + 212a: b000 .2byte 0xb000 + 212c: f419 bnez s0,203a <__neorv32_ram_size+0x3a> + 212e: 0019 c.nop 6 + 2130: 0600 addi s0,sp,768 + 2132: 00001bf7 .4byte 0x1bf7 + 2136: 0684 addi s1,sp,832 + 2138: 0000 unimp + 213a: 001c0207 .4byte 0x1c0207 + 213e: 0000 unimp + 2140: 0f14 addi a3,sp,912 + 2142: 001c .2byte 0x1c + 2144: 6000 .2byte 0x6000 + 2146: 0c000003 lb zero,192(zero) # c0 <__crt0_clear_bss_loop+0x4> + 214a: 0000 unimp + 214c: b300 .2byte 0xb300 + 214e: 1f28 addi a0,sp,952 + 2150: 001a c.slli zero,0x6 + 2152: 0600 addi s0,sp,768 + 2154: 1c1d addi s8,s8,-25 # 1fe7 <__RODATA_END__+0x517> + 2156: 0000 unimp + 2158: 00000693 li a3,0 + 215c: 280c .2byte 0x280c + 215e: 001c .2byte 0x1c + 2160: 9f00 .2byte 0x9f00 + 2162: 0006 c.slli zero,0x1 + 2164: 0700 addi s0,sp,896 + 2166: 1c34 addi a3,sp,568 + 2168: 0000 unimp + 216a: 1400 addi s0,sp,544 + 216c: 1be9 addi s7,s7,-6 + 216e: 0000 unimp + 2170: 0370 addi a2,sp,396 + 2172: 0000 unimp + 2174: 0004 .2byte 0x4 + 2176: 0000 unimp + 2178: 09b6 slli s3,s3,0xd + 217a: 1a41 addi s4,s4,-16 + 217c: 0000 unimp + 217e: f706 .2byte 0xf706 + 2180: ab00001b .4byte 0xab00001b + 2184: 0006 c.slli zero,0x1 + 2186: 0700 addi s0,sp,896 + 2188: 1c02 slli s8,s8,0x20 + 218a: 0000 unimp + 218c: 4500 lw s0,8(a0) + 218e: 1bb9 addi s7,s7,-18 + 2190: 0000 unimp + 2192: 038c addi a1,sp,448 + 2194: 0000 unimp + 2196: 0004 .2byte 0x4 + 2198: 0000 unimp + 219a: bd01 j 1faa <__RODATA_END__+0x4da> + 219c: 0605 addi a2,a2,1 + 219e: 1bd1 addi s7,s7,-12 + 21a0: 0000 unimp + 21a2: 06ba slli a3,a3,0xe + 21a4: 0000 unimp + 21a6: c606 sw ra,12(sp) + 21a8: c600001b .4byte 0xc600001b + 21ac: 0006 c.slli zero,0x1 + 21ae: 0c00 addi s0,sp,528 + 21b0: 1bdc addi a5,sp,500 + 21b2: 0000 unimp + 21b4: 06d5 addi a3,a3,21 + 21b6: 0000 unimp + 21b8: 0000 unimp + 21ba: e922 .2byte 0xe922 + 21bc: ac00001b .4byte 0xac00001b + 21c0: 0002 c.slli64 zero + 21c2: 9e00 .2byte 0x9e00 + 21c4: 0000 unimp + 21c6: 8200 .2byte 0x8200 + 21c8: 9619 srai a2,a2,0x26 + 21ca: 001a c.slli zero,0x6 + 21cc: 0600 addi s0,sp,768 + 21ce: 00001bf7 .4byte 0x1bf7 + 21d2: 06e1 addi a3,a3,24 + 21d4: 0000 unimp + 21d6: 9e15 .2byte 0x9e15 + 21d8: 0000 unimp + 21da: 0700 addi s0,sp,896 + 21dc: 1c02 slli s8,s8,0x20 + 21de: 0000 unimp + 21e0: 0000 unimp + 21e2: 4805 li a6,1 + 21e4: 14000003 lb zero,320(zero) # 140 <__crt0_trap_handler+0x4> + 21e8: 0019 c.nop 6 + 21ea: 0000 unimp + 21ec: 6631 lui a2,0xc + 21ee: 0019 c.nop 6 + 21f0: 7000 .2byte 0x7000 + 21f2: 009a slli ra,ra,0x6 + 21f4: 0000 unimp + 21f6: 083c addi a5,sp,24 + 21f8: 0000 unimp + 21fa: 0030 addi a2,sp,8 + 21fc: 0000 unimp + 21fe: 9c01 .2byte 0x9c01 + 2200: 00001ac7 .4byte 0x1ac7 + 2204: 6932 .2byte 0x6932 + 2206: 0064 addi s1,sp,12 + 2208: 2b70 .2byte 0x2b70 + 220a: 00ad addi ra,ra,11 + 220c: 0000 unimp + 220e: 06f0 addi a2,sp,844 + 2210: 0000 unimp + 2212: 3100 .2byte 0x3100 + 2214: 19f0 addi a2,sp,252 + 2216: 0000 unimp + 2218: 9a5e add s4,s4,s7 + ... + 2222: 0000 unimp + 2224: 0100 addi s0,sp,128 + 2226: fc9c .2byte 0xfc9c + 2228: 001a c.slli zero,0x6 + 222a: 3200 .2byte 0x3200 + 222c: 6469 lui s0,0x1a + 222e: 5e00 lw s0,56(a2) + 2230: ad29 j 284a <__neorv32_ram_size+0x84a> + 2232: 0000 unimp + 2234: 2300 .2byte 0x2300 + 2236: 46000007 .4byte 0x46000007 + 223a: 1d4a slli s10,s10,0x32 + 223c: 0000 unimp + 223e: 5e01 li t3,-32 + 2240: 0634 addi a3,sp,776 + 2242: 0001 nop + 2244: 0100 addi s0,sp,128 + 2246: f547005b .4byte 0xf547005b + 224a: 0000 unimp + 224c: 0100 addi s0,sp,128 + 224e: 0641 addi a2,a2,16 # c010 <__neorv32_ram_size+0xa010> + 2250: 086c addi a1,sp,28 + 2252: 0000 unimp + 2254: 0058 addi a4,sp,4 + 2256: 0000 unimp + 2258: 9c01 .2byte 0x9c01 + 225a: 1bb9 addi s7,s7,-18 + 225c: 0000 unimp + 225e: 6948 .2byte 0x6948 + 2260: 0064 addi s1,sp,12 + 2262: 5001 c.li zero,-32 + 2264: 0000ad0b .4byte 0xad0b + 2268: 5600 lw s0,40(a2) + 226a: 22000007 .4byte 0x22000007 + 226e: 1bb9 addi s7,s7,-18 + 2270: 0000 unimp + 2272: 086c addi a1,sp,28 + 2274: 0000 unimp + 2276: 01b5 addi gp,gp,13 # 8000104d <__global_pointer$+0xd> + 2278: 0000 unimp + 227a: 0344 addi s1,sp,388 + 227c: 1b59 addi s6,s6,-10 + 227e: 0000 unimp + 2280: d106 sw ra,160(sp) + 2282: 7900001b .4byte 0x7900001b + 2286: 06000007 .4byte 0x6000007 + 228a: 1bc6 slli s7,s7,0x31 + 228c: 0000 unimp + 228e: 078a slli a5,a5,0x2 + 2290: 0000 unimp + 2292: b515 j 20b6 <__neorv32_ram_size+0xb6> + 2294: 0001 nop + 2296: 4900 lw s0,16(a0) + 2298: 1bdc addi a5,sp,500 + 229a: 0000 unimp + 229c: 0306 slli t1,t1,0x1 + 229e: 02ac addi a1,sp,328 + 22a0: 0000 unimp + 22a2: 009f 1400 1bb9 .byte 0x9f, 0x00, 0x00, 0x14, 0xb9, 0x1b + 22a8: 0000 unimp + 22aa: 0884 addi s1,sp,80 + 22ac: 0000 unimp + 22ae: 0008 .2byte 0x8 + 22b0: 0000 unimp + 22b2: 1b840347 .4byte 0x1b840347 + 22b6: 0000 unimp + 22b8: d106 sw ra,160(sp) + 22ba: 9900001b .4byte 0x9900001b + 22be: 06000007 .4byte 0x6000007 + 22c2: 1bc6 slli s7,s7,0x31 + 22c4: 0000 unimp + 22c6: 07a6 slli a5,a5,0x9 + 22c8: 0000 unimp + 22ca: 001bdc33 srl s8,s7,ra + 22ce: 0000 unimp + 22d0: b914 .2byte 0xb914 + 22d2: 8c00001b .4byte 0x8c00001b + 22d6: 0008 .2byte 0x8 + 22d8: 0400 addi s0,sp,512 + 22da: 0000 unimp + 22dc: 4a00 lw s0,16(a2) + 22de: 001baf03 lw t5,1(s7) + 22e2: 0600 addi s0,sp,768 + 22e4: 1bd1 addi s7,s7,-12 + 22e6: 0000 unimp + 22e8: 07b5 addi a5,a5,13 # 100d <_malloc_r+0x1af> + 22ea: 0000 unimp + 22ec: c606 sw ra,12(sp) + 22ee: c200001b .4byte 0xc200001b + 22f2: 33000007 .4byte 0x33000007 + 22f6: 1bdc addi a5,sp,500 + 22f8: 0000 unimp + 22fa: 0500 addi s0,sp,640 + 22fc: 08ac addi a1,sp,88 + 22fe: 0000 unimp + 2300: 1aa0 addi s0,sp,376 + 2302: 0000 unimp + 2304: 4a00 lw s0,16(a2) + 2306: 1d94 addi a3,sp,752 + 2308: 0000 unimp + 230a: e502 .2byte 0xe502 + 230c: 032d addi t1,t1,11 + 230e: 1be9 addi s7,s7,-6 + 2310: 0000 unimp + 2312: 591d li s2,-25 + 2314: e5000007 .4byte 0xe5000007 + 2318: a14d j 27ba <__neorv32_ram_size+0x7ba> + 231a: 0000 unimp + 231c: 1d00 addi s0,sp,688 + 231e: 0af4 addi a3,sp,348 + 2320: 0000 unimp + 2322: 5ee5 li t4,-7 + 2324: 00e2 slli ra,ra,0x18 + 2326: 0000 unimp + 2328: 2212 .2byte 0x2212 + 232a: 000d c.nop 3 + 232c: 0200 addi s0,sp,256 + 232e: 00e20ce7 jalr s9,14(tp) # 0 <__crt0_entry> + 2332: 0000 unimp + 2334: 3400 .2byte 0x3400 + 2336: 00001103 lh sp,0(zero) # 0 <__crt0_entry> + 233a: e2d5 bnez a3,23de <__neorv32_ram_size+0x3de> + 233c: 0000 unimp + 233e: 0f00 addi s0,sp,912 + 2340: 001c .2byte 0x1c + 2342: 1d00 addi s0,sp,688 + 2344: 0759 addi a4,a4,22 + 2346: 0000 unimp + 2348: 50d5 li ra,-11 + 234a: 00a1 addi ra,ra,8 + 234c: 0000 unimp + 234e: 2212 .2byte 0x2212 + 2350: 000d c.nop 3 + 2352: 0200 addi s0,sp,256 + 2354: 00e20cd7 .4byte 0xe20cd7 + 2358: 0000 unimp + 235a: 3400 .2byte 0x3400 + 235c: 00000a4f .4byte 0xa4f + 2360: 0000c58f .4byte 0xc58f + 2364: 4100 lw s0,0(a0) + 2366: 001c .2byte 0x1c + 2368: 1d00 addi s0,sp,688 + 236a: 1312 slli t1,t1,0x24 + 236c: 0000 unimp + 236e: 00e2598f .4byte 0xe2598f + 2372: 0000 unimp + 2374: 0e12 slli t3,t3,0x4 + 2376: 02000013 li zero,32 + 237a: 0c91 addi s9,s9,4 + 237c: 00e2 slli ra,ra,0x18 + 237e: 0000 unimp + 2380: f012 .2byte 0xf012 + 2382: 000a c.slli zero,0x2 + 2384: 0200 addi s0,sp,256 + 2386: 0c92 slli s9,s9,0x4 + 2388: 00c5 addi ra,ra,17 + 238a: 0000 unimp + 238c: 1e00 addi s0,sp,816 + 238e: 0f7a slli t5,t5,0x1e + ... + 2398: 0000 unimp + 239a: 9c01 .2byte 0x9c01 + 239c: 1c85 addi s9,s9,-31 + 239e: 0000 unimp + 23a0: 8606 mv a2,ra + 23a2: d100000f .4byte 0xd100000f + 23a6: 09000007 .4byte 0x9000007 + 23aa: 0f7a slli t5,t5,0x1e + ... + 23b4: 0000 unimp + 23b6: 0204 addi s1,sp,256 + 23b8: 7b0d lui s6,0xfffe3 + 23ba: 001c .2byte 0x1c + 23bc: 0600 addi s0,sp,768 + 23be: 0f86 slli t6,t6,0x1 + 23c0: 0000 unimp + 23c2: 0804 addi s1,sp,16 + 23c4: 0000 unimp + 23c6: 4b00 lw s0,16(a4) + 23c8: 0000 unimp + 23ca: 0000 unimp + 23cc: 0bfa slli s7,s7,0x1e + 23ce: 0000 unimp + 23d0: 1e00 addi s0,sp,816 + 23d2: 1914 addi a3,sp,176 + 23d4: 0000 unimp + 23d6: 0564 addi s1,sp,652 + 23d8: 0000 unimp + 23da: 02d8 addi a4,sp,324 + 23dc: 0000 unimp + 23de: 9c01 .2byte 0x9c01 + 23e0: 00001ffb .4byte 0x1ffb + 23e4: 00192107 .4byte 0x192107 + 23e8: 0700 addi s0,sp,896 + 23ea: 192d addi s2,s2,-21 + 23ec: 0000 unimp + 23ee: 1422 slli s0,s0,0x28 + 23f0: 0019 c.nop 6 + 23f2: 8400 .2byte 0x8400 + 23f4: 0005 c.nop 1 + 23f6: d600 sw s0,40(a2) + 23f8: 0000 unimp + 23fa: c600 sw s0,8(a2) + 23fc: f10d bnez a0,231e <__neorv32_ram_size+0x31e> + 23fe: 001f 1500 00d6 .byte 0x1f, 0x00, 0x00, 0x15, 0xd6, 0x00 + 2404: 0000 unimp + 2406: 210c .2byte 0x210c + 2408: 0019 c.nop 6 + 240a: 1e00 addi s0,sp,816 + 240c: 0008 .2byte 0x8 + 240e: 0c00 addi s0,sp,528 + 2410: 192d addi s2,s2,-21 + 2412: 0000 unimp + 2414: 0840 addi s0,sp,20 + 2416: 0000 unimp + 2418: e914 .2byte 0xe914 + 241a: 9000001b .4byte 0x9000001b + 241e: 0005 c.nop 1 + 2420: 0400 addi s0,sp,512 + 2422: 0000 unimp + 2424: d000 sw s0,32(s0) + 2426: ee19 bnez a2,2444 <__neorv32_ram_size+0x444> + 2428: 001c .2byte 0x1c + 242a: 0600 addi s0,sp,768 + 242c: 00001bf7 .4byte 0x1bf7 + 2430: 00000883 lb a7,0(zero) # 0 <__crt0_entry> + 2434: 001c0207 .4byte 0x1c0207 + 2438: 0000 unimp + 243a: 001be923 .4byte 0x1be923 + 243e: f400 .2byte 0xf400 + 2440: 0005 c.nop 1 + 2442: fb00 .2byte 0xfb00 + 2444: 0000 unimp + 2446: 0400 addi s0,sp,512 + 2448: 1301 addi t1,t1,-32 + 244a: 00001d17 auipc s10,0x1 + 244e: f706 .2byte 0xf706 + 2450: 9200001b .4byte 0x9200001b + 2454: 0008 .2byte 0x8 + 2456: 1500 addi s0,sp,672 + 2458: 000000fb .4byte 0xfb + 245c: 001c0207 .4byte 0x1c0207 + 2460: 0000 unimp + 2462: 2300 .2byte 0x2300 + 2464: 1be9 addi s7,s7,-6 + 2466: 0000 unimp + 2468: 0670 addi a2,sp,780 + 246a: 0000 unimp + 246c: 0132 slli sp,sp,0xc + 246e: 0000 unimp + 2470: 0115 addi sp,sp,5 + 2472: 4005 c.li zero,1 + 2474: 001d c.nop 7 + 2476: 0600 addi s0,sp,768 + 2478: 00001bf7 .4byte 0x1bf7 + 247c: 000008e7 jalr a7,zero # 0 <__crt0_entry> + 2480: 3215 jal 1da4 <__RODATA_END__+0x2d4> + 2482: 0001 nop + 2484: 0700 addi s0,sp,896 + 2486: 1c02 slli s8,s8,0x20 + 2488: 0000 unimp + 248a: 0000 unimp + 248c: 3924 .2byte 0x3924 + 248e: 0019 c.nop 6 + 2490: 4500 lw s0,8(a0) + 2492: 0001 nop + 2494: 6000 .2byte 0x6000 + 2496: 001d c.nop 7 + 2498: 0c00 addi s0,sp,528 + 249a: 193e slli s2,s2,0x2f + 249c: 0000 unimp + 249e: 08f6 slli a7,a7,0x1d + 24a0: 0000 unimp + 24a2: a005 j 24c2 <__neorv32_ram_size+0x4c2> + 24a4: 0006 c.slli zero,0x1 + 24a6: fa00 .2byte 0xfa00 + 24a8: 0000000b .4byte 0xb + 24ac: 4b24 lw s1,80(a4) + 24ae: 0019 c.nop 6 + 24b0: 5800 lw s0,48(s0) + 24b2: 0001 nop + 24b4: 3f00 .2byte 0x3f00 + 24b6: 001e c.slli zero,0x7 + 24b8: 0700 addi s0,sp,896 + 24ba: 194c addi a1,sp,180 + 24bc: 0000 unimp + 24be: 00195807 .4byte 0x195807 + 24c2: 0900 addi s0,sp,144 + 24c4: 00001c0f .4byte 0x1c0f + 24c8: 06ec addi a1,sp,844 + 24ca: 0000 unimp + 24cc: 000c .2byte 0xc + 24ce: 0000 unimp + 24d0: 010a slli sp,sp,0x2 + 24d2: 001da323 sw ra,6(s11) + 24d6: 0600 addi s0,sp,768 + 24d8: 1c1d addi s8,s8,-25 + 24da: 0000 unimp + 24dc: 090d addi s2,s2,3 + 24de: 0000 unimp + 24e0: 280c .2byte 0x280c + 24e2: 001c .2byte 0x1c + 24e4: 1900 addi s0,sp,176 + 24e6: 0009 c.nop 2 + 24e8: 0700 addi s0,sp,896 + 24ea: 1c34 addi a3,sp,568 + 24ec: 0000 unimp + 24ee: 2300 .2byte 0x2300 + 24f0: 00001c0f .4byte 0x1c0f + 24f4: 06f8 addi a4,sp,844 + 24f6: 0000 unimp + 24f8: 0000016b .4byte 0x16b + 24fc: d523010b .4byte 0xd523010b + 2500: 001d c.nop 7 + 2502: 0600 addi s0,sp,768 + 2504: 1c1d addi s8,s8,-25 + 2506: 0000 unimp + 2508: 0930 addi a2,sp,152 + 250a: 0000 unimp + 250c: 6b15 lui s6,0x5 + 250e: 0001 nop + 2510: 0c00 addi s0,sp,528 + 2512: 1c28 addi a0,sp,568 + 2514: 0000 unimp + 2516: 0956 slli s2,s2,0x15 + 2518: 0000 unimp + 251a: 001c3407 .4byte 0x1c3407 + 251e: 0000 unimp + 2520: 0900 addi s0,sp,144 + 2522: 0e55 addi t3,t3,21 + 2524: 0000 unimp + 2526: 0714 addi a3,sp,896 + 2528: 0000 unimp + 252a: 0038 addi a4,sp,8 + 252c: 0000 unimp + 252e: 010d addi sp,sp,3 + 2530: 001e2b07 .4byte 0x1e2b07 + 2534: 4c00 lw s0,24(s0) + 2536: 0e61 addi t3,t3,24 + 2538: 0000 unimp + 253a: 7a0c .2byte 0x7a0c + 253c: 000e c.slli zero,0x3 + 253e: 8900 .2byte 0x8900 + 2540: 0009 c.nop 2 + 2542: 2400 .2byte 0x2400 + 2544: 0e84 addi s1,sp,848 + 2546: 0000 unimp + 2548: 0190 addi a2,sp,192 + 254a: 0000 unimp + 254c: 00001e17 auipc t3,0x1 + 2550: 850c .2byte 0x850c + 2552: 000e c.slli zero,0x3 + 2554: 9600 .2byte 0x9600 + 2556: 0009 c.nop 2 + 2558: 0500 addi s0,sp,640 + 255a: 0748 addi a0,sp,900 + 255c: 0000 unimp + 255e: 0bea slli s7,s7,0x1a + 2560: 0000 unimp + 2562: 1100 addi s0,sp,160 + 2564: 0724 addi s1,sp,904 + 2566: 0000 unimp + 2568: 0bfa slli s7,s7,0x1e + 256a: 0000 unimp + 256c: 055a0103 lb sp,85(s4) + 2570: 00182c03 lw s8,1(a6) + 2574: 0000 unimp + 2576: 1100 addi s0,sp,160 + 2578: 06ec addi a1,sp,844 + 257a: 0000 unimp + 257c: 0bfa slli s7,s7,0x1e + 257e: 0000 unimp + 2580: 055a0103 lb sp,85(s4) + 2584: 0019cc03 lbu s8,1(s3) + 2588: 0000 unimp + 258a: 0400 addi s0,sp,512 + 258c: 0590 addi a2,sp,704 + 258e: 0000 unimp + 2590: 0bfa slli s7,s7,0x1e + 2592: 0000 unimp + 2594: 1e56 slli t3,t3,0x35 + 2596: 0000 unimp + 2598: 055a0103 lb sp,85(s4) + 259c: 00183003 .4byte 0x183003 + 25a0: 0000 unimp + 25a2: e404 .2byte 0xe404 + 25a4: 0005 c.nop 1 + 25a6: fa00 .2byte 0xfa00 + 25a8: 6d00000b .4byte 0x6d00000b + 25ac: 001e c.slli zero,0x7 + 25ae: 0300 addi s0,sp,384 + 25b0: 5a01 li s4,-32 + 25b2: 0305 addi t1,t1,1 + 25b4: 1988 addi a0,sp,240 + 25b6: 0000 unimp + 25b8: 0400 addi s0,sp,512 + 25ba: 05ec addi a1,sp,716 + 25bc: 0000 unimp + 25be: 0ea8 addi a0,sp,856 + 25c0: 0000 unimp + 25c2: 1e81 addi t4,t4,-32 + 25c4: 0000 unimp + 25c6: 025a0103 lb sp,37(s4) + 25ca: 0079 c.nop 30 + 25cc: 0400 addi s0,sp,512 + 25ce: 05f4 addi a3,sp,716 + 25d0: 0000 unimp + 25d2: 0bfa slli s7,s7,0x1e + 25d4: 0000 unimp + 25d6: 1e98 addi a4,sp,880 + 25d8: 0000 unimp + 25da: 055a0103 lb sp,85(s4) + 25de: 00185803 lhu a6,1(a6) + 25e2: 0000 unimp + 25e4: 0004 .2byte 0x4 + 25e6: 0006 c.slli zero,0x1 + 25e8: a800 .2byte 0xa800 + 25ea: 000e c.slli zero,0x3 + 25ec: ac00 .2byte 0xac00 + 25ee: 001e c.slli zero,0x7 + 25f0: 0300 addi s0,sp,384 + 25f2: 5a01 li s4,-32 + 25f4: 7802 .2byte 0x7802 + 25f6: 0000 unimp + 25f8: 2804 .2byte 0x2804 + 25fa: 0006 c.slli zero,0x1 + 25fc: fa00 .2byte 0xfa00 + 25fe: c300000b .4byte 0xc300000b + 2602: 001e c.slli zero,0x7 + 2604: 0300 addi s0,sp,384 + 2606: 5a01 li s4,-32 + 2608: 0305 addi t1,t1,1 + 260a: 197c addi a5,sp,188 + 260c: 0000 unimp + 260e: 0400 addi s0,sp,512 + 2610: 0630 addi a2,sp,776 + 2612: 0000 unimp + 2614: 0ea8 addi a0,sp,856 + 2616: 0000 unimp + 2618: 1ed9 addi t4,t4,-10 + 261a: 0000 unimp + 261c: 045a0103 lb sp,69(s4) + 2620: 0079 c.nop 30 + 2622: 04001a3f 00000638 .8byte 0x63804001a3f + 262a: 0bfa slli s7,s7,0x1e + 262c: 0000 unimp + 262e: 1ef0 addi a2,sp,892 + 2630: 0000 unimp + 2632: 055a0103 lb sp,85(s4) + 2636: 00185803 lhu a6,1(a6) + 263a: 0000 unimp + 263c: 4005 c.li zero,1 + 263e: 0006 c.slli zero,0x1 + 2640: a800 .2byte 0xa800 + 2642: 000e c.slli zero,0x3 + 2644: 0500 addi s0,sp,640 + 2646: 0654 addi a3,sp,772 + 2648: 0000 unimp + 264a: 0bfa slli s7,s7,0x1e + 264c: 0000 unimp + 264e: 5c04 lw s1,56(s0) + 2650: 0006 c.slli zero,0x1 + 2652: fa00 .2byte 0xfa00 + 2654: 1900000b .4byte 0x1900000b + 2658: 001f 0300 5a01 .byte 0x1f, 0x00, 0x00, 0x03, 0x01, 0x5a + 265e: 0305 addi t1,t1,1 + 2660: 1858 addi a4,sp,52 + 2662: 0000 unimp + 2664: 0500 addi s0,sp,640 + 2666: 0664 addi s1,sp,780 + 2668: 0000 unimp + 266a: 0ea8 addi a0,sp,856 + 266c: 0000 unimp + 266e: 7004 .2byte 0x7004 + 2670: 0006 c.slli zero,0x1 + 2672: fa00 .2byte 0xfa00 + 2674: 3900000b .4byte 0x3900000b + 2678: 001f 0300 5a01 .byte 0x1f, 0x00, 0x00, 0x03, 0x01, 0x5a + 267e: 0305 addi t1,t1,1 + 2680: 19e0 addi s0,sp,252 + 2682: 0000 unimp + 2684: 0500 addi s0,sp,640 + 2686: 0684 addi s1,sp,832 + 2688: 0000 unimp + 268a: 0bfa slli s7,s7,0x1e + 268c: 0000 unimp + 268e: a804 .2byte 0xa804 + 2690: 0006 c.slli zero,0x1 + 2692: fa00 .2byte 0xfa00 + 2694: 5900000b .4byte 0x5900000b + 2698: 001f 0300 5a01 .byte 0x1f, 0x00, 0x00, 0x03, 0x01, 0x5a + 269e: 0305 addi t1,t1,1 + 26a0: 1858 addi a4,sp,52 + 26a2: 0000 unimp + 26a4: 0400 addi s0,sp,512 + 26a6: 06b4 addi a3,sp,840 + 26a8: 0000 unimp + 26aa: 0ea8 addi a0,sp,856 + 26ac: 0000 unimp + 26ae: 1f6d addi t5,t5,-5 + 26b0: 0000 unimp + 26b2: 025a0103 lb sp,37(s4) + 26b6: 0078 addi a4,sp,12 + 26b8: 0400 addi s0,sp,512 + 26ba: 06cc addi a1,sp,836 + 26bc: 0000 unimp + 26be: 0bfa slli s7,s7,0x1e + 26c0: 0000 unimp + 26c2: 1f84 addi s1,sp,1008 + 26c4: 0000 unimp + 26c6: 055a0103 lb sp,85(s4) + 26ca: 00187c03 .4byte 0x187c03 + 26ce: 0000 unimp + 26d0: d404 sw s1,40(s0) + 26d2: 0006 c.slli zero,0x1 + 26d4: fa00 .2byte 0xfa00 + 26d6: 9b00000b .4byte 0x9b00000b + 26da: 001f 0300 5a01 .byte 0x1f, 0x00, 0x00, 0x03, 0x01, 0x5a + 26e0: 0305 addi t1,t1,1 + 26e2: 1858 addi a4,sp,52 + 26e4: 0000 unimp + 26e6: 0400 addi s0,sp,512 + 26e8: 06e0 addi s0,sp,844 + 26ea: 0000 unimp + 26ec: 0ea8 addi a0,sp,856 + 26ee: 0000 unimp + 26f0: 00001faf .4byte 0x1faf + 26f4: 025a0103 lb sp,37(s4) + 26f8: 0078 addi a4,sp,12 + 26fa: 3000 .2byte 0x3000 + 26fc: 0770 addi a2,sp,908 + 26fe: 0000 unimp + 2700: 0bfa slli s7,s7,0x1e + 2702: 0000 unimp + 2704: 1fc6 slli t6,t6,0x31 + 2706: 0000 unimp + 2708: 055a0103 lb sp,85(s4) + 270c: 0019d403 lhu s0,1(s3) + 2710: 0000 unimp + 2712: d005 beqz s0,2632 <__neorv32_ram_size+0x632> + 2714: fa000007 .4byte 0xfa000007 + 2718: 0400000b .4byte 0x400000b + 271c: 07d8 addi a4,sp,964 + 271e: 0000 unimp + 2720: 0bfa slli s7,s7,0x1e + 2722: 0000 unimp + 2724: 1fe6 slli t6,t6,0x39 + 2726: 0000 unimp + 2728: 055a0103 lb sp,85(s4) + 272c: 00185803 lhu a6,1(a6) + 2730: 0000 unimp + 2732: e005 bnez s0,2752 <__neorv32_ram_size+0x752> + 2734: a8000007 .4byte 0xa8000007 + 2738: 000e c.slli zero,0x3 + 273a: 0000 unimp + 273c: 0500 addi s0,sp,640 + 273e: 0580 addi s0,sp,704 + 2740: 0000 unimp + 2742: 0c0a slli s8,s8,0x2 + 2744: 0000 unimp + 2746: 1e00 addi s0,sp,816 + 2748: 0e24 addi s1,sp,792 + ... + 2752: 0000 unimp + 2754: 9c01 .2byte 0x9c01 + 2756: 209e .2byte 0x209e + 2758: 0000 unimp + 275a: 000e3207 .4byte 0xe3207 + 275e: 0700 addi s0,sp,896 + 2760: 0e3c addi a5,sp,792 + 2762: 0000 unimp + 2764: 000e4807 .4byte 0xe4807 + 2768: 0900 addi s0,sp,144 + 276a: 0e24 addi s1,sp,792 + ... + 2774: 0000 unimp + 2776: 024d addi tp,tp,19 # 13 + 2778: 9406 add s0,s0,ra + 277a: 0020 addi s0,sp,8 + 277c: 0700 addi s0,sp,896 + 277e: 0e32 slli t3,t3,0xc + 2780: 0000 unimp + 2782: 000e3c07 .4byte 0xe3c07 + 2786: 0700 addi s0,sp,896 + 2788: 0e48 addi a0,sp,788 + 278a: 0000 unimp + 278c: e909 bnez a0,279e <__neorv32_ram_size+0x79e> + 278e: 0000001b .4byte 0x1b + 2792: 0000 unimp + 2794: 0000 unimp + 2796: 0000 unimp + 2798: 5800 lw s0,48(s0) + 279a: 1202 slli tp,tp,0x20 + 279c: 00002063 .4byte 0x2063 + 27a0: f706 .2byte 0xf706 + 27a2: c300001b .4byte 0xc300001b + 27a6: 0009 c.nop 2 + 27a8: 0700 addi s0,sp,896 + 27aa: 1c02 slli s8,s8,0x20 + 27ac: 0000 unimp + 27ae: 0500 addi s0,sp,640 + 27b0: 0000 unimp + 27b2: 0000 unimp + 27b4: 0bea slli s7,s7,0x1a + 27b6: 0000 unimp + 27b8: 0004 .2byte 0x4 + 27ba: 0000 unimp + 27bc: ea00 .2byte 0xea00 + 27be: 8300000b .4byte 0x8300000b + 27c2: 0020 addi s0,sp,8 + 27c4: 0300 addi s0,sp,384 + 27c6: 5a01 li s4,-32 + 27c8: 7805 lui a6,0xfffe1 + 27ca: 8200 .2byte 0x8200 + 27cc: 2200 .2byte 0x2200 + 27ce: 1100 addi s0,sp,160 + 27d0: 0000 unimp + 27d2: 0000 unimp + 27d4: 0bea slli s7,s7,0x1a + 27d6: 0000 unimp + 27d8: 025a0103 lb sp,37(s4) + 27dc: 2e08 .2byte 0x2e08 + 27de: 0000 unimp + 27e0: 0005 c.nop 1 + 27e2: 0000 unimp + 27e4: 0a00 addi s0,sp,272 + 27e6: 000c .2byte 0xc + 27e8: 0000 unimp + 27ea: c21e sw t2,4(sp) + 27ec: 000c .2byte 0xc + ... + 27f6: 0100 addi s0,sp,128 + 27f8: bb9c .2byte 0xbb9c + 27fa: 0020 addi s0,sp,8 + 27fc: 4d00 lw s0,24(a0) + 27fe: 0cd4 addi a3,sp,596 + 2800: 0000 unimp + 2802: 0100 addi s0,sp,128 + 2804: 4000 lw s0,0(s0) + 2806: 4e00 lw s0,24(a2) + 2808: 0000174b .4byte 0x174b + 280c: 1741 addi a4,a4,-16 + 280e: 0000 unimp + 2810: 0008 .2byte 0x8 + 2812: 00133d4f .4byte 0x133d4f + 2816: 3d00 .2byte 0x3d00 + 2818: 00000013 nop + 281c: 0d38 addi a4,sp,664 + 281e: 0000 unimp + 2820: 0005 c.nop 1 + 2822: 0401 addi s0,s0,0 # 1a000 <__neorv32_ram_size+0x18000> + 2824: 080a slli a6,a6,0x2 + 2826: 0000 unimp + 2828: 00011d27 .4byte 0x11d27 + 282c: 1d00 addi s0,sp,688 + 282e: 0248 addi a0,sp,260 + 2830: 0000 unimp + 2832: 0198 addi a4,sp,192 + 2834: 0000 unimp + 2836: 029d addi t0,t0,7 + 2838: 0000 unimp + 283a: 0000 unimp + 283c: 0000 unimp + 283e: 21fd jal 2d2c <__neorv32_ram_size+0xd2c> + 2840: 0000 unimp + 2842: 0108 addi a0,sp,128 + 2844: e906 .2byte 0xe906 + 2846: 0000 unimp + 2848: 0900 addi s0,sp,144 + 284a: 0000 unimp + 284c: 0000 unimp + 284e: 2b02 .2byte 0x2b02 + 2850: 3918 .2byte 0x3918 + 2852: 0000 unimp + 2854: 0800 addi s0,sp,16 + 2856: 0801 addi a6,a6,0 # fffe1000 <__crt0_stack_begin+0x7ffdf004> + 2858: 000000e7 jalr zero # 0 <__crt0_entry> + 285c: 0208 addi a0,sp,256 + 285e: 2805 jal 288e <__neorv32_ram_size+0x88e> + 2860: 0002 c.slli64 zero + 2862: 0900 addi s0,sp,144 + 2864: 0dcc addi a1,sp,724 + 2866: 0000 unimp + 2868: 3902 .2byte 0x3902 + 286a: 5319 li t1,-26 + 286c: 0000 unimp + 286e: 0800 addi s0,sp,16 + 2870: 0702 c.slli64 a4 + 2872: 003a c.slli zero,0xe + 2874: 0000 unimp + 2876: b309 j 2578 <__neorv32_ram_size+0x578> + 2878: 001d c.nop 7 + 287a: 0200 addi s0,sp,256 + 287c: 184d addi a6,a6,-13 + 287e: 0066 c.slli zero,0x19 + 2880: 0000 unimp + 2882: 0408 addi a0,sp,512 + 2884: ff05 bnez a4,27bc <__neorv32_ram_size+0x7bc> + 2886: 0001 nop + 2888: 0900 addi s0,sp,144 + 288a: 00000197 auipc gp,0x0 + 288e: 4f02 lw t5,0(sp) + 2890: 7919 lui s2,0xfffe6 + 2892: 0000 unimp + 2894: 0800 addi s0,sp,16 + 2896: 0704 addi s1,sp,896 + 2898: 000000bb .4byte 0xbb + 289c: 0808 addi a0,sp,16 + 289e: fa05 bnez a2,27ce <__neorv32_ram_size+0x7ce> + 28a0: 0001 nop + 28a2: 0800 addi s0,sp,16 + 28a4: 0708 addi a0,sp,896 + 28a6: 00b6 slli ra,ra,0xd + 28a8: 0000 unimp + 28aa: 0428 addi a0,sp,520 + 28ac: 6905 lui s2,0x1 + 28ae: 746e .2byte 0x746e + 28b0: 0800 addi s0,sp,16 + 28b2: 0704 addi s1,sp,896 + 28b4: 00c0 addi s0,sp,68 + 28b6: 0000 unimp + 28b8: 0209 addi tp,tp,2 # 2 + 28ba: 0000 unimp + 28bc: 0300 addi s0,sp,384 + 28be: 1318 addi a4,sp,416 + 28c0: 002d c.nop 11 + 28c2: 0000 unimp + 28c4: ce09 beqz a2,28de <__neorv32_ram_size+0x8de> + 28c6: 000d c.nop 3 + 28c8: 0300 addi s0,sp,384 + 28ca: 1424 addi s1,sp,552 + 28cc: 00000047 .4byte 0x47 + 28d0: b509 j 26d2 <__neorv32_ram_size+0x6d2> + 28d2: 001d c.nop 7 + 28d4: 0300 addi s0,sp,384 + 28d6: 132c addi a1,sp,424 + 28d8: 005a c.slli zero,0x16 + 28da: 0000 unimp + 28dc: 9909 andi a0,a0,-30 + 28de: 0001 nop + 28e0: 0300 addi s0,sp,384 + 28e2: 1430 addi a2,sp,552 + 28e4: 006d c.nop 27 + 28e6: 0000 unimp + 28e8: c011 beqz s0,28ec <__neorv32_ram_size+0x8ec> + 28ea: 0000 unimp + 28ec: 0800 addi s0,sp,16 + 28ee: 0410 addi a2,sp,512 + 28f0: 025d addi tp,tp,23 # 17 + 28f2: 0000 unimp + 28f4: 0429 addi s0,s0,10 + 28f6: 20f5 jal 29e2 <__neorv32_ram_size+0x9e2> + 28f8: 0000 unimp + 28fa: e31c .2byte 0xe31c + 28fc: 0000 unimp + 28fe: 0800 addi s0,sp,16 + 2900: 0801 addi a6,a6,0 + 2902: 00f0 addi a2,sp,76 + 2904: 0000 unimp + 2906: e311 bnez a4,290a <__neorv32_ram_size+0x90a> + 2908: 0000 unimp + 290a: 1c00 addi s0,sp,560 + 290c: 00ea slli ra,ra,0x1a + 290e: 0000 unimp + 2910: 0814 addi a3,sp,16 + 2912: 0405 addi s0,s0,1 + 2914: 00000117 auipc sp,0x0 + 2918: cb0a sw sp,148(sp) + 291a: 06000013 li zero,96 + 291e: 0c04 addi s1,sp,528 + 2920: 00c0 addi s0,sp,68 + 2922: 0000 unimp + 2924: 0a00 addi s0,sp,272 + 2926: 000022cb .4byte 0x22cb + 292a: c00c0407 .4byte 0xc00c0407 + 292e: 0000 unimp + 2930: 0400 addi s0,sp,512 + 2932: 1500 addi s0,sp,672 + 2934: 1fb1 addi t6,t6,-20 + 2936: 0000 unimp + 2938: 0408 addi a0,sp,512 + 293a: 00f4 addi a3,sp,76 + 293c: 0000 unimp + 293e: 0814 addi a3,sp,16 + 2940: 0411 addi s0,s0,4 + 2942: 0145 addi sp,sp,17 # 2925 <__neorv32_ram_size+0x925> + 2944: 0000 unimp + 2946: cb0a sw sp,148(sp) + 2948: 12000013 li zero,288 + 294c: 0c04 addi s1,sp,528 + 294e: 00c0 addi s0,sp,68 + 2950: 0000 unimp + 2952: 0a00 addi s0,sp,272 + 2954: 000022cb .4byte 0x22cb + 2958: c00c0413 addi s0,s8,-1024 + 295c: 0000 unimp + 295e: 0400 addi s0,sp,512 + 2960: 1500 addi s0,sp,672 + 2962: 247e .2byte 0x247e + 2964: 0000 unimp + 2966: 0414 addi a3,sp,512 + 2968: 0122 slli sp,sp,0x8 + 296a: 0000 unimp + 296c: 6716 .2byte 0x6716 + 296e: 0024 addi s1,sp,8 + 2970: 9500 .2byte 0x9500 + 2972: 0000 unimp + 2974: 1d00 addi s0,sp,688 + 2976: 1a04 addi s1,sp,304 + 2978: 0002 c.slli64 zero + 297a: 0100 addi s0,sp,128 + 297c: 0000204b .4byte 0x204b + 2980: 0100 addi s0,sp,128 + 2982: 205c .2byte 0x205c + 2984: 0000 unimp + 2986: 0101 addi sp,sp,0 + 2988: 2274 .2byte 0x2274 + 298a: 0000 unimp + 298c: 0102 c.slli64 sp + 298e: 207e .2byte 0x207e + 2990: 0000 unimp + 2992: 208f0103 lb sp,520(t5) + 2996: 0000 unimp + 2998: 0104 addi s1,sp,128 + 299a: 20a0 .2byte 0x20a0 + 299c: 0000 unimp + 299e: 0105 addi sp,sp,1 + 29a0: 20b1 jal 29ec <__neorv32_ram_size+0x9ec> + 29a2: 0000 unimp + 29a4: 0106 slli sp,sp,0x1 + 29a6: 20c2 .2byte 0x20c2 + 29a8: 0000 unimp + 29aa: 20d30107 .4byte 0x20d30107 + 29ae: 0000 unimp + 29b0: 0108 addi a0,sp,128 + 29b2: 20e4 .2byte 0x20e4 + 29b4: 0000 unimp + 29b6: 0109 addi sp,sp,2 + 29b8: 00002507 .4byte 0x2507 + 29bc: 010a slli sp,sp,0x2 + 29be: 000021e7 .4byte 0x21e7 + 29c2: 231e010b .4byte 0x231e010b + 29c6: 0000 unimp + 29c8: 010c addi a1,sp,128 + 29ca: 000022e3 .4byte 0x22e3 + 29ce: 010d addi sp,sp,3 + 29d0: 2285 jal 2b30 <__neorv32_ram_size+0xb30> + 29d2: 0000 unimp + 29d4: 010e slli sp,sp,0x3 + 29d6: 0000243f 248e010f .8byte 0x248e010f0000243f + 29de: 0000 unimp + 29e0: 0110 addi a2,sp,128 + 29e2: 000022a7 .4byte 0x22a7 + 29e6: 0111 addi sp,sp,4 + 29e8: 1f9f 0000 0112 .byte 0x9f, 0x1f, 0x00, 0x00, 0x12, 0x01 + 29ee: 1f8e slli t6,t6,0x23 + 29f0: 0000 unimp + 29f2: 0114 addi a3,sp,128 + 29f4: 23c4 .2byte 0x23c4 + 29f6: 0000 unimp + 29f8: 0115 addi sp,sp,5 + 29fa: 2228 .2byte 0x2228 + 29fc: 0000 unimp + 29fe: 0116 slli sp,sp,0x5 + 2a00: 2239 jal 2b0e <__neorv32_ram_size+0xb0e> + 2a02: 0000 unimp + 2a04: 21970117 auipc sp,0x21970 + 2a08: 0000 unimp + 2a0a: 0118 addi a4,sp,128 + 2a0c: 000021a7 .4byte 0x21a7 + 2a10: 0119 addi sp,sp,6 # 21972a0a <__neorv32_ram_size+0x21970a0a> + 2a12: 000021b7 lui gp,0x2 + 2a16: 011a slli sp,sp,0x6 + 2a18: 00002397 auipc t2,0x2 + 2a1c: 213e011b .4byte 0x213e011b + 2a20: 0000 unimp + 2a22: 011c addi a5,sp,128 + 2a24: 000024cf .4byte 0x24cf + 2a28: 011d addi sp,sp,7 + 2a2a: 206d jal 2ad4 <__neorv32_ram_size+0xad4> + 2a2c: 0000 unimp + 2a2e: 011e slli sp,sp,0x7 + 2a30: 22b9 jal 2b7e <__neorv32_ram_size+0xb7e> + 2a32: 0000 unimp + 2a34: 001f b816 0024 .byte 0x1f, 0x00, 0x16, 0xb8, 0x24, 0x00 + 2a3a: 9500 .2byte 0x9500 + 2a3c: 0000 unimp + 2a3e: 5000 lw s0,32(s0) + 2a40: 4e04 lw s1,24(a2) + 2a42: 0002 c.slli64 zero + 2a44: 0100 addi s0,sp,128 + 2a46: 1ff8 addi a4,sp,1020 + 2a48: 0000 unimp + 2a4a: 0100 addi s0,sp,128 + 2a4c: 24aa .2byte 0x24aa + 2a4e: 0000 unimp + 2a50: 21880107 .4byte 0x21880107 + 2a54: 0000 unimp + 2a56: 011c addi a5,sp,128 + 2a58: 2265 jal 2c00 <__neorv32_ram_size+0xc00> + 2a5a: 0000 unimp + 2a5c: 011d addi sp,sp,7 + 2a5e: 23ad jal 2fc8 <__neorv32_ram_size+0xfc8> + 2a60: 0000 unimp + 2a62: 011e slli sp,sp,0x7 + 2a64: 00002297 auipc t0,0x2 + 2a68: 001f 2014 0544 .byte 0x1f, 0x00, 0x14, 0x20, 0x44, 0x05 + 2a6e: 02bd addi t0,t0,15 # 4a73 <__neorv32_ram_size+0x2a73> + 2a70: 0000 unimp + 2a72: 431d li t1,7 + 2a74: 4b4c lw a1,20(a4) + 2a76: 4500 lw s0,8(a0) + 2a78: cc05 beqz s0,2ab0 <__neorv32_ram_size+0xab0> + 2a7a: 0000 unimp + 2a7c: 0000 unimp + 2a7e: 840a mv s0,sp + 2a80: 0000 unimp + 2a82: 4600 lw s0,8(a2) + 2a84: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 2a86: 00cc addi a1,sp,68 + 2a88: 0000 unimp + 2a8a: 1d04 addi s1,sp,688 + 2a8c: 00434f53 .4byte 0x434f53 + 2a90: 00cc0547 .4byte 0xcc0547 + 2a94: 0000 unimp + 2a96: 0a08 addi a0,sp,272 + 2a98: 03bd addi t2,t2,15 # 4a27 <__neorv32_ram_size+0x2a27> + 2a9a: 0000 unimp + 2a9c: 0548 addi a0,sp,644 + 2a9e: cc12 sw tp,24(sp) + 2aa0: 0000 unimp + 2aa2: 0c00 addi s0,sp,528 + 2aa4: 320a .2byte 0x320a + 2aa6: 0002 c.slli64 zero + 2aa8: 4900 lw s0,16(a0) + 2aaa: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 2aac: 00cc addi a1,sp,68 + 2aae: 0000 unimp + 2ab0: 0a10 addi a2,sp,272 + 2ab2: 00aa slli ra,ra,0xa + 2ab4: 0000 unimp + 2ab6: 054a slli a0,a0,0x12 + 2ab8: cc12 sw tp,24(sp) + 2aba: 0000 unimp + 2abc: 1400 addi s0,sp,544 + 2abe: 4d0a lw s10,128(sp) + 2ac0: 0000 unimp + 2ac2: 4b00 lw s0,16(a4) + 2ac4: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 2ac6: 00cc addi a1,sp,68 + 2ac8: 0000 unimp + 2aca: 0a18 addi a4,sp,272 + 2acc: 008e slli ra,ra,0x3 + 2ace: 0000 unimp + 2ad0: 054c addi a1,sp,644 + 2ad2: cc12 sw tp,24(sp) + 2ad4: 0000 unimp + 2ad6: 1c00 addi s0,sp,560 + 2ad8: 1500 addi s0,sp,672 + 2ada: 0098 addi a4,sp,64 + 2adc: 0000 unimp + 2ade: 054d addi a0,a0,19 # f013 <__neorv32_ram_size+0xd013> + 2ae0: 024e slli tp,tp,0x13 + 2ae2: 0000 unimp + 2ae4: ad16 .2byte 0xad16 + 2ae6: 0002 c.slli64 zero + 2ae8: 9500 .2byte 0x9500 + 2aea: 0000 unimp + 2aec: 5600 lw s0,40(a2) + 2aee: 6805 lui a6,0x1 + 2af0: 01000003 lb zero,16(zero) # 10 + 2af4: 0434 addi a3,sp,520 + 2af6: 0000 unimp + 2af8: 0100 addi s0,sp,128 + 2afa: 04fa slli s1,s1,0x1e + 2afc: 0000 unimp + 2afe: 0101 addi sp,sp,0 + 2b00: 02ce slli t0,t0,0x13 + 2b02: 0000 unimp + 2b04: 0102 c.slli64 sp + 2b06: 000002e7 jalr t0,zero # 0 <__crt0_entry> + 2b0a: 047f0103 lb sp,71(t5) + 2b0e: 0000 unimp + 2b10: 0104 addi s1,sp,128 + 2b12: 03b0 addi a2,sp,456 + 2b14: 0000 unimp + 2b16: 0105 addi sp,sp,1 + 2b18: 0315 addi t1,t1,5 + 2b1a: 0000 unimp + 2b1c: 010d addi sp,sp,3 + 2b1e: 03a0 addi s0,sp,456 + 2b20: 0000 unimp + 2b22: 010e slli sp,sp,0x3 + 2b24: 0521 addi a0,a0,8 + 2b26: 0000 unimp + 2b28: 0110 addi a2,sp,128 + 2b2a: 0300 addi s0,sp,384 + 2b2c: 0000 unimp + 2b2e: 0111 addi sp,sp,4 + 2b30: 04b0 addi a2,sp,584 + 2b32: 0000 unimp + 2b34: 0112 slli sp,sp,0x4 + 2b36: 0000044b .4byte 0x44b + 2b3a: 03c30113 addi sp,t1,60 + 2b3e: 0000 unimp + 2b40: 0114 addi a3,sp,128 + 2b42: 0000033f 05400115 .8byte 0x54001150000033f + 2b4a: 0000 unimp + 2b4c: 0116 slli sp,sp,0x5 + 2b4e: 050e slli a0,a0,0x3 + 2b50: 0000 unimp + 2b52: 038c0117 auipc sp,0x38c0 + 2b56: 0000 unimp + 2b58: 0118 addi a4,sp,128 + 2b5a: 0404 addi s1,sp,512 + 2b5c: 0000 unimp + 2b5e: 0119 addi sp,sp,6 # 38c2b58 <__neorv32_ram_size+0x38c0b58> + 2b60: 04c5 addi s1,s1,17 + 2b62: 0000 unimp + 2b64: 011a slli sp,sp,0x6 + 2b66: 03d6 slli t2,t2,0x15 + 2b68: 0000 unimp + 2b6a: 0419011b .4byte 0x419011b + 2b6e: 0000 unimp + 2b70: 011c addi a5,sp,128 + 2b72: 04e5 addi s1,s1,25 + 2b74: 0000 unimp + 2b76: 011d addi sp,sp,7 + 2b78: 0352 slli t1,t1,0x14 + 2b7a: 0000 unimp + 2b7c: 011e slli sp,sp,0x7 + 2b7e: 0365 addi t1,t1,25 + 2b80: 0000 unimp + 2b82: 001f d509 0023 .byte 0x1f, 0x00, 0x09, 0xd5, 0x23, 0x00 + 2b88: 0500 addi s0,sp,640 + 2b8a: 1b28 addi a0,sp,440 + 2b8c: 00d8 addi a4,sp,68 + 2b8e: 0000 unimp + 2b90: dc09 beqz s0,2aaa <__neorv32_ram_size+0xaaa> + 2b92: 05000023 sb a6,64(zero) # 40 + 2b96: 03681863 bne a6,s6,2bc6 <__neorv32_ram_size+0xbc6> + 2b9a: 0000 unimp + 2b9c: 4a2a lw s4,136(sp) + 2b9e: 0022 c.slli zero,0x8 + 2ba0: 0100 addi s0,sp,128 + 2ba2: 038d addi t2,t2,3 + 2ba4: 010d addi sp,sp,3 + 2ba6: 03b0 addi a2,sp,456 + 2ba8: 0000 unimp + 2baa: 6c1e .2byte 0x6c1e + 2bac: 6e65 lui t3,0x19 + 2bae: 3100 .2byte 0x3100 + 2bb0: 00c0 addi s0,sp,68 + 2bb2: 0000 unimp + 2bb4: 701e .2byte 0x701e + 2bb6: 7274 .2byte 0x7274 + 2bb8: 3c00 .2byte 0x3c00 + 2bba: 00de slli ra,ra,0x17 + 2bbc: 0000 unimp + 2bbe: 706d742b .4byte 0x706d742b + 2bc2: 0100 addi s0,sp,128 + 2bc4: e308038f .4byte 0xe308038f + 2bc8: 0000 unimp + 2bca: 0000 unimp + 2bcc: fc1f 0023 7900 .byte 0x1f, 0xfc, 0x23, 0x00, 0x00, 0x79 + 2bd2: 000a3003 .4byte 0xa3003 + 2bd6: 3c00 .2byte 0x3c00 + 2bd8: 0000 unimp + 2bda: 0100 addi s0,sp,128 + 2bdc: 169c addi a5,sp,864 + 2bde: 0004 .2byte 0x4 + 2be0: 1700 addi s0,sp,928 + 2be2: 0078 addi a4,sp,12 + 2be4: 0379 addi t1,t1,30 + 2be6: 0000c02b .4byte 0xc02b + 2bea: 0100 addi s0,sp,128 + 2bec: 175a slli a4,a4,0x36 + 2bee: 6572 .2byte 0x6572 + 2bf0: 03790073 .4byte 0x3790073 + 2bf4: de34 sw a3,120(a2) + 2bf6: 0000 unimp + 2bf8: 0100 addi s0,sp,128 + 2bfa: 0df90e5b .4byte 0xdf90e5b + 2bfe: 0000 unimp + 2c00: 2615037b .4byte 0x2615037b + 2c04: 0004 .2byte 0x4 + 2c06: 0500 addi s0,sp,640 + 2c08: 001ab003 .4byte 0x1ab003 + 2c0c: 0500 addi s0,sp,640 + 2c0e: 0069 c.nop 26 + 2c10: 037d addi t1,t1,31 + 2c12: 00008e07 .4byte 0x8e07 + 2c16: de00 sw s0,56(a2) + 2c18: 0009 c.nop 2 + 2c1a: 2c00 .2byte 0x2c00 + 2c1c: 0278 addi a4,sp,268 + 2c1e: 0000 unimp + 2c20: 00238f07 .4byte 0x238f07 + 2c24: 7f00 .2byte 0x7f00 + 2c26: 00c00e03 lb t3,12(zero) # c + 2c2a: 0000 unimp + 2c2c: 00000a0f .4byte 0xa0f + 2c30: 0000 unimp + 2c32: ea18 .2byte 0xea18 + 2c34: 0000 unimp + 2c36: 2600 .2byte 0x2600 + 2c38: 0004 .2byte 0x4 + 2c3a: 1900 addi s0,sp,176 + 2c3c: 0095 addi ra,ra,5 + 2c3e: 0000 unimp + 2c40: 0010 .2byte 0x10 + 2c42: 1611 addi a2,a2,-28 + 2c44: 0004 .2byte 0x4 + 2c46: 1f00 addi s0,sp,944 + 2c48: 1fe4 addi s1,sp,1020 + 2c4a: 0000 unimp + 2c4c: 0351 addi t1,t1,20 + 2c4e: 0928 addi a0,sp,152 + 2c50: 0000 unimp + 2c52: 0108 addi a0,sp,128 + 2c54: 0000 unimp + 2c56: 9c01 .2byte 0x9c01 + 2c58: 04ae slli s1,s1,0xb + 2c5a: 0000 unimp + 2c5c: 7812 .2byte 0x7812 + 2c5e: 5100 lw s0,32(a0) + 2c60: 00c02a03 lw s4,12(zero) # c + 2c64: 0000 unimp + 2c66: 0a30 addi a2,sp,280 + 2c68: 0000 unimp + 2c6a: 7212 .2byte 0x7212 + 2c6c: 7365 lui t1,0xffff9 + 2c6e: 5100 lw s0,32(a0) + 2c70: 00de3303 .4byte 0xde3303 + 2c74: 0000 unimp + 2c76: 0a5d addi s4,s4,23 + 2c78: 0000 unimp + 2c7a: a50e .2byte 0xa50e + 2c7c: 53000023 sb a6,1312(zero) # 520 <__neorv32_rte_print_hex_word+0x2c> + 2c80: 04be1503 lh a0,75(t3) # 1904b <__neorv32_ram_size+0x1704b> + 2c84: 0000 unimp + 2c86: 0305 addi t1,t1,1 # ffff9001 <__crt0_stack_begin+0x7fff7005> + 2c88: 1ac4 addi s1,sp,372 + 2c8a: 0000 unimp + 2c8c: 360e .2byte 0x360e + 2c8e: 0021 c.nop 8 + 2c90: 5400 lw s0,40(s0) + 2c92: 04c30803 lb a6,76(t1) + 2c96: 0000 unimp + 2c98: 9102 jalr sp + 2c9a: 0554 addi a3,sp,644 + 2c9c: 0069 c.nop 26 + 2c9e: 0355 addi t1,t1,21 + 2ca0: a80c .2byte 0xa80c + 2ca2: 0000 unimp + 2ca4: 8d00 .2byte 0x8d00 + 2ca6: 000a c.slli zero,0x2 + 2ca8: 0500 addi s0,sp,640 + 2caa: 006a c.slli zero,0x1a + 2cac: 0355 addi t1,t1,21 + 2cae: 0000a80f .4byte 0xa80f + 2cb2: ca00 sw s0,16(a2) + 2cb4: 000a c.slli zero,0x2 + 2cb6: 0400 addi s0,sp,512 + 2cb8: 0970 addi a2,sp,156 + 2cba: 0000 unimp + 2cbc: 0d29 addi s10,s10,10 # 3454 <__neorv32_ram_size+0x1454> + 2cbe: 0000 unimp + 2cc0: 8c04 .2byte 0x8c04 + 2cc2: 0009 c.nop 2 + 2cc4: 3200 .2byte 0x3200 + 2cc6: 000d c.nop 3 + 2cc8: 0000 unimp + 2cca: ea18 .2byte 0xea18 + 2ccc: 0000 unimp + 2cce: be00 .2byte 0xbe00 + 2cd0: 0004 .2byte 0x4 + 2cd2: 1900 addi s0,sp,176 + 2cd4: 0095 addi ra,ra,5 + 2cd6: 0000 unimp + 2cd8: 000a c.slli zero,0x2 + 2cda: ae11 j 2fee <__neorv32_ram_size+0xfee> + 2cdc: 0004 .2byte 0x4 + 2cde: 1800 addi s0,sp,48 + 2ce0: 000000e3 beqz zero,34e0 <__neorv32_ram_size+0x14e0> + 2ce4: 000004d3 .4byte 0x4d3 + 2ce8: 9519 srai a0,a0,0x26 + 2cea: 0000 unimp + 2cec: 0a00 addi s0,sp,272 + 2cee: 0c00 addi s0,sp,528 + 2cf0: 00002373 csrr t1,ustatus + 2cf4: 0326 slli t1,t1,0x9 + 2cf6: 8e05 sub a2,a2,s1 + ... + 2d00: 0000 unimp + 2d02: 0100 addi s0,sp,128 + 2d04: 7b9c .2byte 0x7b9c + 2d06: 0005 c.nop 1 + 2d08: 0600 addi s0,sp,768 + 2d0a: 0000242b .4byte 0x242b + 2d0e: 0326 slli t1,t1,0x9 + 2d10: de1e sw t2,60(sp) + 2d12: 0000 unimp + 2d14: ec00 .2byte 0xec00 + 2d16: 000a c.slli zero,0x2 + 2d18: 0600 addi s0,sp,768 + 2d1a: 24a1 jal 2f62 <__neorv32_ram_size+0xf62> + 2d1c: 0000 unimp + 2d1e: 0326 slli t1,t1,0x9 + 2d20: 8e2a mv t3,a0 + 2d22: 0000 unimp + 2d24: 1900 addi s0,sp,176 + 2d26: 0600000b .4byte 0x600000b + 2d2a: 00002223 sw zero,4(zero) # 4 <__crt0_cpu_csr_init> + 2d2e: 0326 slli t1,t1,0x9 + 2d30: 8e38 .2byte 0x8e38 + 2d32: 0000 unimp + 2d34: 4000 lw s0,0(s0) + 2d36: 0500000b .4byte 0x500000b + 2d3a: 03280063 beq a6,s2,2d5a <__neorv32_ram_size+0xd5a> + 2d3e: e308 .2byte 0xe308 + 2d40: 0000 unimp + 2d42: 6500 .2byte 0x6500 + 2d44: 0700000b .4byte 0x700000b + 2d48: 2411 jal 2f4c <__neorv32_ram_size+0xf4c> + 2d4a: 0000 unimp + 2d4c: 0329 addi t1,t1,10 + 2d4e: 00008e07 .4byte 0x8e07 + 2d52: 9300 .2byte 0x9300 + 2d54: 0400000b .4byte 0x400000b + 2d58: 0000 unimp + 2d5a: 0000 unimp + 2d5c: 00000743 .4byte 0x743 + 2d60: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 2d64: 8700 .2byte 0x8700 + 2d66: 0006 c.slli zero,0x1 + 2d68: 5b00 lw s0,48(a4) + 2d6a: 0005 c.nop 1 + 2d6c: 0200 addi s0,sp,256 + 2d6e: 5a01 li s4,-32 + 2d70: 0305 addi t1,t1,1 + 2d72: 0000 unimp + 2d74: 0000 unimp + 2d76: 0300 addi s0,sp,384 + 2d78: 0000 unimp + 2d7a: 0000 unimp + 2d7c: 00000797 auipc a5,0x0 + 2d80: 0571 addi a0,a0,28 + 2d82: 0000 unimp + 2d84: 0102 c.slli64 sp + 2d86: 045a slli s0,s0,0x16 + 2d88: 4c91 li s9,4 + 2d8a: 0194 addi a3,sp,192 + 2d8c: 0400 addi s0,sp,512 + 2d8e: 0000 unimp + 2d90: 0000 unimp + 2d92: 00000743 .4byte 0x743 + 2d96: 0d00 addi s0,sp,656 + 2d98: 2331 jal 32a4 <__neorv32_ram_size+0x12a4> + 2d9a: 0000 unimp + 2d9c: 02e2 slli t0,t0,0x18 + ... + 2da6: 9c01 .2byte 0x9c01 + 2da8: 00000687 .4byte 0x687 + 2dac: bd06 .2byte 0xbd06 + 2dae: e2000023 sb zero,-480(zero) # fffffe20 <__crt0_stack_begin+0x7fffde24> + 2db2: 2702 .2byte 0x2702 + 2db4: 000000ef jal ra,2db4 <__neorv32_ram_size+0xdb4> + 2db8: 0bb6 slli s7,s7,0xd + 2dba: 0000 unimp + 2dbc: 0520 addi s0,sp,648 + 2dbe: 02e40063 beq s0,a4,2dde <__neorv32_ram_size+0xdde> + 2dc2: e308 .2byte 0xe308 + 2dc4: 0000 unimp + 2dc6: 1900 addi s0,sp,176 + 2dc8: 000c .2byte 0xc + 2dca: 0e00 addi s0,sp,784 + 2dcc: 000024ef jal s1,4dcc <__neorv32_ram_size+0x2dcc> + 2dd0: 02e4 addi s1,sp,332 + 2dd2: 0004c30b .4byte 0x4c30b + 2dd6: 0300 addi s0,sp,384 + 2dd8: a491 j 301c <__neorv32_ram_size+0x101c> + 2dda: 057f .2byte 0x57f + 2ddc: 006e c.slli zero,0x1b + 2dde: 02e5 addi t0,t0,25 + 2de0: 0000b40b .4byte 0xb40b + 2de4: 5e00 lw s0,56(a2) + 2de6: 000c .2byte 0xc + 2de8: 2100 .2byte 0x2100 + 2dea: 0061 c.nop 24 + 2dec: 037402e7 jalr t0,55(s0) + 2df0: 0000 unimp + 2df2: 7fa09103 lh sp,2042(ra) + 2df6: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 2dfa: 9700 .2byte 0x9700 + 2dfc: ee000007 .4byte 0xee000007 + 2e00: 0005 c.nop 1 + 2e02: 0200 addi s0,sp,256 + 2e04: 5a01 li s4,-32 + 2e06: 8402 jr s0 + 2e08: 0000 unimp + 2e0a: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 2e0e: 9700 .2byte 0x9700 + 2e10: 02000007 .4byte 0x2000007 + 2e14: 0006 c.slli zero,0x1 + 2e16: 0200 addi s0,sp,256 + 2e18: 5a01 li s4,-32 + 2e1a: 0802 c.slli64 a6 + 2e1c: 002d c.nop 11 + 2e1e: 0004 .2byte 0x4 + 2e20: 0000 unimp + 2e22: 2b00 .2byte 0x2b00 + 2e24: 0004 .2byte 0x4 + 2e26: 0400 addi s0,sp,512 + 2e28: 0000 unimp + 2e2a: 0000 unimp + 2e2c: 00000687 .4byte 0x687 + 2e30: 0004 .2byte 0x4 + 2e32: 0000 unimp + 2e34: 9700 .2byte 0x9700 + 2e36: 03000007 .4byte 0x3000007 + 2e3a: 0000 unimp + 2e3c: 0000 unimp + 2e3e: 03b0 addi a2,sp,456 + 2e40: 0000 unimp + 2e42: 0632 slli a2,a2,0xc + 2e44: 0000 unimp + 2e46: 0102 c.slli64 sp + 2e48: a491035b .4byte 0xa491035b + 2e4c: 007f .2byte 0x7f + 2e4e: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 2e52: fd00 .2byte 0xfd00 + 2e54: 000c .2byte 0xc + 2e56: 4e00 lw s0,24(a2) + 2e58: 0006 c.slli zero,0x1 + 2e5a: 0200 addi s0,sp,256 + 2e5c: 5a01 li s4,-32 + 2e5e: 7fa49103 lh sp,2042(s1) + 2e62: 8e22 mv t3,s0 + 2e64: 01000003 lb zero,16(zero) # 10 + 2e68: 0003003b .4byte 0x3003b + 2e6c: 0000 unimp + 2e6e: b000 .2byte 0xb000 + 2e70: 63000003 lb zero,1584(zero) # 630 <__neorv32_rte_debug_handler+0xcc> + 2e74: 0006 c.slli zero,0x1 + 2e76: 0200 addi s0,sp,256 + 2e78: 5b01 li s6,-32 + 2e7a: 7fa49103 lh sp,2042(s1) + 2e7e: 0300 addi s0,sp,384 + 2e80: 0000 unimp + 2e82: 0000 unimp + 2e84: 00000797 auipc a5,0x0 + 2e88: 0676 slli a2,a2,0x1d + 2e8a: 0000 unimp + 2e8c: 0102 c.slli64 sp + 2e8e: 015a slli sp,sp,0x16 + 2e90: 003d c.nop 15 + 2e92: 0000000f fence unknown,unknown + 2e96: 9700 .2byte 0x9700 + 2e98: 02000007 .4byte 0x2000007 + 2e9c: 5a01 li s4,-32 + 2e9e: 7802 .2byte 0x7802 + 2ea0: 0000 unimp + 2ea2: 0d00 addi s0,sp,656 + 2ea4: 22f6 .2byte 0x22f6 + 2ea6: 0000 unimp + 2ea8: 02c5 addi t0,t0,17 + ... + 2eb2: 9c01 .2byte 0x9c01 + 2eb4: 06dc addi a5,sp,836 + 2eb6: 0000 unimp + 2eb8: 7312 .2byte 0x7312 + 2eba: c500 sw s0,8(a0) + 2ebc: 2502 .2byte 0x2502 + 2ebe: 000000ef jal ra,2ebe <__neorv32_ram_size+0xebe> + 2ec2: 0c6a slli s8,s8,0x1a + 2ec4: 0000 unimp + 2ec6: 6305 lui t1,0x1 + 2ec8: c700 sw s0,8(a4) + 2eca: 0802 c.slli64 a6 + 2ecc: 000000e3 beqz zero,36cc <__neorv32_ram_size+0x16cc> + 2ed0: 0c8c addi a1,sp,592 + 2ed2: 0000 unimp + 2ed4: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 2ed8: 9700 .2byte 0x9700 + 2eda: cb000007 .4byte 0xcb000007 + 2ede: 0006 c.slli zero,0x1 + 2ee0: 0200 addi s0,sp,256 + 2ee2: 5a01 li s4,-32 + 2ee4: 3d01 jal 2cf4 <__neorv32_ram_size+0xcf4> + 2ee6: 0f00 addi s0,sp,912 + 2ee8: 0000 unimp + 2eea: 0000 unimp + 2eec: 00000797 auipc a5,0x0 + 2ef0: 0102 c.slli64 sp + 2ef2: 025a slli tp,tp,0x16 + 2ef4: 0079 c.nop 30 + 2ef6: 0000 unimp + 2ef8: 4b10 lw a2,16(a4) + 2efa: 0021 c.nop 8 + 2efc: b800 .2byte 0xb800 + 2efe: 0602 c.slli64 a2 + 2f00: 000000e3 beqz zero,3700 <__neorv32_ram_size+0x1700> + ... + 2f0c: 9c01 .2byte 0x9c01 + 2f0e: 2610 .2byte 0x2610 + 2f10: 0020 addi s0,sp,8 + 2f12: a500 .2byte 0xa500 + 2f14: 0502 c.slli64 a0 + 2f16: 008e slli ra,ra,0x3 + ... + 2f20: 0000 unimp + 2f22: 9c01 .2byte 0x9c01 + 2f24: e40c .2byte 0xe40c + 2f26: 7e000023 sb zero,2016(zero) # 7e0 <__neorv32_rte_debug_handler+0x27c> + 2f2a: 0502 c.slli64 a0 + 2f2c: 008e slli ra,ra,0x3 + ... + 2f36: 0000 unimp + 2f38: 9c01 .2byte 0x9c01 + 2f3a: 00000743 .4byte 0x743 + 2f3e: f406 .2byte 0xf406 + 2f40: 000a c.slli zero,0x2 + 2f42: 7e00 .2byte 0x7e00 + 2f44: 2302 .2byte 0x2302 + 2f46: 00de slli ra,ra,0x17 + 2f48: 0000 unimp + 2f4a: 00000caf .4byte 0xcaf + 2f4e: 0021df07 .4byte 0x21df07 + 2f52: 8000 .2byte 0x8000 + 2f54: 0c02 c.slli64 s8 + 2f56: 00c0 addi s0,sp,68 + 2f58: 0000 unimp + 2f5a: 0ce2 slli s9,s9,0x18 + 2f5c: 0000 unimp + 2f5e: 0c00 addi s0,sp,528 + 2f60: 2210 .2byte 0x2210 + 2f62: 0000 unimp + 2f64: 0265 addi tp,tp,25 # 19 + 2f66: e306 .2byte 0xe306 + ... + 2f70: 0000 unimp + 2f72: 0100 addi s0,sp,128 + 2f74: 6c9c .2byte 0x6c9c + 2f76: 05000007 .4byte 0x5000007 + 2f7a: 0064 addi s1,sp,12 + 2f7c: c00c0267 jalr tp,-1024(s8) + 2f80: 0000 unimp + 2f82: f900 .2byte 0xf900 + 2f84: 000c .2byte 0xc + 2f86: 0000 unimp + 2f88: 180c addi a1,sp,48 + 2f8a: 0025 c.nop 9 + 2f8c: 5200 lw s0,32(a2) + 2f8e: 0502 c.slli64 a0 + 2f90: 008e slli ra,ra,0x3 + ... + 2f9a: 0000 unimp + 2f9c: 9c01 .2byte 0x9c01 + 2f9e: 00000797 auipc a5,0x0 + 2fa2: 00243207 .4byte 0x243207 + 2fa6: 5400 lw s0,40(s0) + 2fa8: 0c02 c.slli64 s8 + 2faa: 00c0 addi s0,sp,68 + 2fac: 0000 unimp + 2fae: 0d05 addi s10,s10,1 + 2fb0: 0000 unimp + 2fb2: 0d00 addi s0,sp,656 + 2fb4: 22d0 .2byte 0x22d0 + 2fb6: 0000 unimp + 2fb8: 00000243 .4byte 0x243 + 2fbc: 0000 unimp + 2fbe: 0000 unimp + 2fc0: 0000 unimp + 2fc2: 9c01 .2byte 0x9c01 + 2fc4: 07b9 addi a5,a5,14 # 2fac <__neorv32_ram_size+0xfac> + 2fc6: 0000 unimp + 2fc8: 43006317 auipc t1,0x43006 + 2fcc: 1e02 slli t3,t3,0x20 + 2fce: 000000e3 beqz zero,37ce <__neorv32_ram_size+0x17ce> + 2fd2: 5a01 li s4,-32 + 2fd4: 2300 .2byte 0x2300 + 2fd6: 2309 jal 34d8 <__neorv32_ram_size+0x14d8> + 2fd8: 0000 unimp + 2fda: 0236 slli tp,tp,0xd + ... + 2fe4: 9c01 .2byte 0x9c01 + 2fe6: 00217223 .4byte 0x217223 + 2fea: 2d00 .2byte 0x2d00 + 2fec: 0002 c.slli64 zero + 2fee: 0000 unimp + 2ff0: 0000 unimp + 2ff2: 0000 unimp + 2ff4: 0100 addi s0,sp,128 + 2ff6: 0d9c addi a5,sp,720 + 2ff8: 2122 .2byte 0x2122 + 2ffa: 0000 unimp + 2ffc: 01f0 addi a2,sp,204 + ... + 3006: 9c01 .2byte 0x9c01 + 3008: 000008b3 add a7,zero,zero + 300c: 4206 lw tp,64(sp) + 300e: 0020 addi s0,sp,8 + 3010: f000 .2byte 0xf000 + 3012: 2301 jal 3512 <__neorv32_ram_size+0x1512> + 3014: 00c0 addi s0,sp,68 + 3016: 0000 unimp + 3018: 0d11 addi s10,s10,4 + 301a: 0000 unimp + 301c: 6b06 .2byte 0x6b06 + 301e: 0021 c.nop 8 + 3020: f000 .2byte 0xf000 + 3022: 3501 jal 2e22 <__neorv32_ram_size+0xe22> + 3024: 009c addi a5,sp,64 + 3026: 0000 unimp + 3028: 00000d2b .4byte 0xd2b + 302c: 8606 mv a2,ra + 302e: f0000023 sb zero,-256(zero) # ffffff00 <__crt0_stack_begin+0x7fffdf04> + 3032: 4501 li a0,0 + 3034: 009c addi a5,sp,64 + 3036: 0000 unimp + 3038: 0d45 addi s10,s10,17 + 303a: 0000 unimp + 303c: 0024e907 .4byte 0x24e907 + 3040: f400 .2byte 0xf400 + 3042: 0c01 addi s8,s8,0 + 3044: 00c0 addi s0,sp,68 + 3046: 0000 unimp + 3048: 0d5f 0000 6905 .byte 0x5f, 0x0d, 0x00, 0x00, 0x05, 0x69 + 304e: f500 .2byte 0xf500 + 3050: 0c01 addi s8,s8,0 + 3052: 00a8 addi a0,sp,72 + 3054: 0000 unimp + 3056: 00000d6b .4byte 0xd6b + 305a: 7005 c.lui zero,0xfffe1 + 305c: f600 .2byte 0xf600 + 305e: 0b01 addi s6,s6,0 # 5000 <__neorv32_ram_size+0x3000> + 3060: 009c addi a5,sp,64 + 3062: 0000 unimp + 3064: 00000d83 lb s11,0(zero) # 0 <__crt0_entry> + 3068: 00236a07 .4byte 0x236a07 + 306c: 0d00 addi s0,sp,656 + 306e: 0c02 c.slli64 s8 + 3070: 00c0 addi s0,sp,68 + 3072: 0000 unimp + 3074: 0db1 addi s11,s11,12 + 3076: 0000 unimp + 3078: 00200607 .4byte 0x200607 + 307c: 1000 addi s0,sp,32 + 307e: 0c02 c.slli64 s8 + 3080: 00c0 addi s0,sp,68 + 3082: 0000 unimp + 3084: 0dcc addi a1,sp,724 + 3086: 0000 unimp + 3088: 00234607 .4byte 0x234607 + 308c: 1400 addi s0,sp,544 + 308e: 0c02 c.slli64 s8 + 3090: 00c0 addi s0,sp,68 + 3092: 0000 unimp + 3094: 0df2 slli s11,s11,0x1c + 3096: 0000 unimp + 3098: 001fd607 .4byte 0x1fd607 + 309c: 1700 addi s0,sp,928 + 309e: 0c02 c.slli64 s8 + 30a0: 00c0 addi s0,sp,68 + 30a2: 0000 unimp + 30a4: 0e01 addi t3,t3,0 + 30a6: 0000 unimp + 30a8: fa2d bnez a2,301a <__neorv32_ram_size+0x101a> + 30aa: 0024 addi s1,sp,8 + 30ac: 0100 addi s0,sp,128 + 30ae: 021a slli tp,tp,0x6 + 30b0: c00c sw a1,0(s0) + 30b2: 0000 unimp + 30b4: 0700 addi s0,sp,896 + 30b6: 24e0 .2byte 0x24e0 + 30b8: 0000 unimp + 30ba: c00c0223 sb zero,-1020(s8) + 30be: 0000 unimp + 30c0: 1c00 addi s0,sp,560 + 30c2: 000e c.slli zero,0x3 + 30c4: 0400 addi s0,sp,512 + 30c6: 0000 unimp + 30c8: 0000 unimp + 30ca: 0d32 slli s10,s10,0xc + 30cc: 0000 unimp + 30ce: 1000 addi s0,sp,32 + 30d0: 21f8 .2byte 0x21f8 + 30d2: 0000 unimp + 30d4: 01d9 addi gp,gp,22 # 2016 <__neorv32_ram_size+0x16> + 30d6: 8e05 sub a2,a2,s1 + ... + 30e0: 0000 unimp + 30e2: 0100 addi s0,sp,128 + 30e4: 0c9c addi a5,sp,592 + 30e6: 2418 .2byte 0x2418 + 30e8: 0000 unimp + 30ea: 8e0501af .4byte 0x8e0501af + ... + 30f6: 0000 unimp + 30f8: 0100 addi s0,sp,128 + 30fa: 719c .2byte 0x719c + 30fc: 0009 c.nop 2 + 30fe: 0600 addi s0,sp,768 + 3100: 0000242b .4byte 0x242b + 3104: de1e01af .4byte 0xde1e01af + 3108: 0000 unimp + 310a: 2900 .2byte 0x2900 + 310c: 000e c.slli zero,0x3 + 310e: 0600 addi s0,sp,768 + 3110: 24a1 jal 3358 <__neorv32_ram_size+0x1358> + 3112: 0000 unimp + 3114: 8e2a01af .4byte 0x8e2a01af + 3118: 0000 unimp + 311a: 5600 lw s0,40(a2) + 311c: 000e c.slli zero,0x3 + 311e: 0600 addi s0,sp,768 + 3120: 00002223 sw zero,4(zero) # 4 <__crt0_cpu_csr_init> + 3124: 8e3801af .4byte 0x8e3801af + 3128: 0000 unimp + 312a: 7d00 .2byte 0x7d00 + 312c: 000e c.slli zero,0x3 + 312e: 0500 addi s0,sp,640 + 3130: 01b10063 beq sp,s11,3130 <__neorv32_ram_size+0x1130> + 3134: e308 .2byte 0xe308 + 3136: 0000 unimp + 3138: a200 .2byte 0xa200 + 313a: 000e c.slli zero,0x3 + 313c: 0700 addi s0,sp,896 + 313e: 2411 jal 3342 <__neorv32_ram_size+0x1342> + 3140: 0000 unimp + 3142: 01b2 slli gp,gp,0xc + 3144: 00008e07 .4byte 0x8e07 + 3148: d000 sw s0,32(s0) + 314a: 000e c.slli zero,0x3 + 314c: 0400 addi s0,sp,512 + 314e: 0000 unimp + 3150: 0000 unimp + 3152: 0b39 addi s6,s6,14 + 3154: 0000 unimp + 3156: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 315a: 7d00 .2byte 0x7d00 + 315c: 000a c.slli zero,0x2 + 315e: 5100 lw s0,32(a0) + 3160: 0009 c.nop 2 + 3162: 0200 addi s0,sp,256 + 3164: 5a01 li s4,-32 + 3166: 0305 addi t1,t1,1 # 43008fc9 <__neorv32_ram_size+0x43006fc9> + 3168: 0000 unimp + 316a: 0000 unimp + 316c: 0300 addi s0,sp,384 + 316e: 0000 unimp + 3170: 0000 unimp + 3172: 0b88 addi a0,sp,464 + 3174: 0000 unimp + 3176: 00000967 jalr s2,zero # 0 <__crt0_entry> + 317a: 0102 c.slli64 sp + 317c: 045a slli s0,s0,0x16 + 317e: 4c91 li s9,4 + 3180: 0194 addi a3,sp,192 + 3182: 0400 addi s0,sp,512 + 3184: 0000 unimp + 3186: 0000 unimp + 3188: 0b39 addi s6,s6,14 + 318a: 0000 unimp + 318c: 0d00 addi s0,sp,656 + 318e: 00000057 .4byte 0x57 + 3192: 0bc4016b .4byte 0xbc4016b + 3196: 0000 unimp + 3198: 01d8 addi a4,sp,196 + 319a: 0000 unimp + 319c: 9c01 .2byte 0x9c01 + 319e: 0a7d addi s4,s4,31 + 31a0: 0000 unimp + 31a2: bd06 .2byte 0xbd06 + 31a4: 6b000023 sb a6,1696(zero) # 6a0 <__neorv32_rte_debug_handler+0x13c> + 31a8: 2701 jal 38a8 <__neorv32_ram_size+0x18a8> + 31aa: 000000ef jal ra,31aa <__neorv32_ram_size+0x11aa> + 31ae: 00000ef3 .4byte 0xef3 + 31b2: 0520 addi s0,sp,648 + 31b4: 016d0063 beq s10,s6,31b4 <__neorv32_ram_size+0x11b4> + 31b8: e308 .2byte 0xe308 + 31ba: 0000 unimp + 31bc: 5600 lw s0,40(a2) + 31be: 0e00000f fence ior,unknown + 31c2: 000024ef jal s1,51c2 <__neorv32_ram_size+0x31c2> + 31c6: 016d addi sp,sp,27 + 31c8: 0004c30b .4byte 0x4c30b + 31cc: 0300 addi s0,sp,384 + 31ce: a491 j 3412 <__neorv32_ram_size+0x1412> + 31d0: 057f .2byte 0x57f + 31d2: 006e c.slli zero,0x1b + 31d4: 016e slli sp,sp,0x1b + 31d6: 0000b40b .4byte 0xb40b + 31da: 9b00 .2byte 0x9b00 + 31dc: 2100000f .4byte 0x2100000f + 31e0: 0061 c.nop 24 + 31e2: 0170 addi a2,sp,140 + 31e4: 0374 addi a3,sp,396 + 31e6: 0000 unimp + 31e8: 7fa09103 lh sp,2042(ra) + 31ec: 000ca003 lw zero,0(s9) + 31f0: 8800 .2byte 0x8800 + 31f2: e400000b .4byte 0xe400000b + 31f6: 0009 c.nop 2 + 31f8: 0200 addi s0,sp,256 + 31fa: 5a01 li s4,-32 + 31fc: 8402 jr s0 + 31fe: 0000 unimp + 3200: 000cd403 lhu s0,0(s9) + 3204: 8800 .2byte 0x8800 + 3206: f800000b .4byte 0xf800000b + 320a: 0009 c.nop 2 + 320c: 0200 addi s0,sp,256 + 320e: 5a01 li s4,-32 + 3210: 0802 c.slli64 a6 + 3212: 002d c.nop 11 + 3214: e004 .2byte 0xe004 + 3216: 000c .2byte 0xc + 3218: 2b00 .2byte 0x2b00 + 321a: 0004 .2byte 0x4 + 321c: 0400 addi s0,sp,512 + 321e: 0d08 addi a0,sp,656 + 3220: 0000 unimp + 3222: 0a7d addi s4,s4,31 + 3224: 0000 unimp + 3226: 2404 .2byte 0x2404 + 3228: 000d c.nop 3 + 322a: 8800 .2byte 0x8800 + 322c: 0300000b .4byte 0x300000b + 3230: 0d58 addi a4,sp,660 + 3232: 0000 unimp + 3234: 03b0 addi a2,sp,456 + 3236: 0000 unimp + 3238: 0a28 addi a0,sp,280 + 323a: 0000 unimp + 323c: 0102 c.slli64 sp + 323e: a491035b .4byte 0xa491035b + 3242: 007f .2byte 0x7f + 3244: 000d6003 .4byte 0xd6003 + 3248: fd00 .2byte 0xfd00 + 324a: 000c .2byte 0xc + 324c: 4400 lw s0,8(s0) + 324e: 000a c.slli zero,0x2 + 3250: 0200 addi s0,sp,256 + 3252: 5a01 li s4,-32 + 3254: 7fa49103 lh sp,2042(s1) + 3258: 8e22 mv t3,s0 + 325a: 01000003 lb zero,16(zero) # 10 + 325e: 7c03003b .4byte 0x7c03003b + 3262: 000d c.nop 3 + 3264: b000 .2byte 0xb000 + 3266: 59000003 lb zero,1424(zero) # 590 <__neorv32_rte_debug_handler+0x2c> + 326a: 000a c.slli zero,0x2 + 326c: 0200 addi s0,sp,256 + 326e: 5b01 li s6,-32 + 3270: 7fa49103 lh sp,2042(s1) + 3274: 0300 addi s0,sp,384 + 3276: 0d8c addi a1,sp,720 + 3278: 0000 unimp + 327a: 0b88 addi a0,sp,464 + 327c: 0000 unimp + 327e: 0a6c addi a1,sp,284 + 3280: 0000 unimp + 3282: 0102 c.slli64 sp + 3284: 015a slli sp,sp,0x16 + 3286: 003d c.nop 15 + 3288: 000d980f .4byte 0xd980f + 328c: 8800 .2byte 0x8800 + 328e: 0200000b .4byte 0x200000b + 3292: 5a01 li s4,-32 + 3294: 7802 .2byte 0x7802 + 3296: 0000 unimp + 3298: 0d00 addi s0,sp,656 + 329a: 00cd addi ra,ra,19 + 329c: 0000 unimp + 329e: 014e slli sp,sp,0x13 + 32a0: 0b6c addi a1,sp,412 + 32a2: 0000 unimp + 32a4: 0058 addi a4,sp,4 + 32a6: 0000 unimp + 32a8: 9c01 .2byte 0x9c01 + 32aa: 0ad2 slli s5,s5,0x14 + 32ac: 0000 unimp + 32ae: 7312 .2byte 0x7312 + 32b0: 4e00 lw s0,24(a2) + 32b2: 2501 jal 38b2 <__neorv32_ram_size+0x18b2> + 32b4: 000000ef jal ra,32b4 <__neorv32_ram_size+0x12b4> + 32b8: 00000fa7 .4byte 0xfa7 + 32bc: 6305 lui t1,0x1 + 32be: 5000 lw s0,32(s0) + 32c0: 0801 addi a6,a6,0 # 1000 <_malloc_r+0x1a2> + 32c2: 000000e3 beqz zero,3ac2 <__neorv32_ram_size+0x1ac2> + 32c6: 0fc9 addi t6,t6,18 + 32c8: 0000 unimp + 32ca: 000bb803 .4byte 0xbb803 + 32ce: 8800 .2byte 0x8800 + 32d0: c100000b .4byte 0xc100000b + 32d4: 000a c.slli zero,0x2 + 32d6: 0200 addi s0,sp,256 + 32d8: 5a01 li s4,-32 + 32da: 3d01 jal 30ea <__neorv32_ram_size+0x10ea> + 32dc: 0f00 addi s0,sp,912 + 32de: 0bc0 addi s0,sp,468 + 32e0: 0000 unimp + 32e2: 0b88 addi a0,sp,464 + 32e4: 0000 unimp + 32e6: 0102 c.slli64 sp + 32e8: 025a slli tp,tp,0x16 + 32ea: 0079 c.nop 30 + 32ec: 0000 unimp + 32ee: 6410 .2byte 0x6410 + 32f0: 001f 4100 0601 .byte 0x1f, 0x00, 0x00, 0x41, 0x01, 0x06 + 32f6: 000000e3 beqz zero,3af6 <__neorv32_ram_size+0x1af6> + ... + 3302: 9c01 .2byte 0x9c01 + 3304: 4e10 lw a2,24(a2) + 3306: 2e000023 sb zero,736(zero) # 2e0 <__neorv32_rte_core+0x34> + 330a: 0501 addi a0,a0,0 + 330c: 008e slli ra,ra,0x3 + ... + 3316: 0000 unimp + 3318: 9c01 .2byte 0x9c01 + 331a: c70c sw a1,8(a4) + 331c: 0021 c.nop 8 + 331e: 0700 addi s0,sp,896 + 3320: 0501 addi a0,a0,0 + 3322: 008e slli ra,ra,0x3 + ... + 332c: 0000 unimp + 332e: 9c01 .2byte 0x9c01 + 3330: 0b39 addi s6,s6,14 + 3332: 0000 unimp + 3334: f406 .2byte 0xf406 + 3336: 000a c.slli zero,0x2 + 3338: 0700 addi s0,sp,896 + 333a: 2301 jal 383a <__neorv32_ram_size+0x183a> + 333c: 00de slli ra,ra,0x17 + 333e: 0000 unimp + 3340: 0fec addi a1,sp,988 + 3342: 0000 unimp + 3344: 0021df07 .4byte 0x21df07 + 3348: 0900 addi s0,sp,144 + 334a: 0c01 addi s8,s8,0 + 334c: 00c0 addi s0,sp,68 + 334e: 0000 unimp + 3350: 101f 0000 1300 .byte 0x1f, 0x10, 0x00, 0x00, 0x00, 0x13 + 3356: 00002107 .4byte 0x2107 + 335a: 06ee slli a3,a3,0x1b + 335c: 000000e3 beqz zero,3b5c <__neorv32_ram_size+0x1b5c> + ... + 3368: 9c01 .2byte 0x9c01 + 336a: 0b60 addi s0,sp,412 + 336c: 0000 unimp + 336e: 641a .2byte 0x641a + 3370: f000 .2byte 0xf000 + 3372: c00c sw a1,0(s0) + 3374: 0000 unimp + 3376: 3600 .2byte 0x3600 + 3378: 0010 .2byte 0x10 + 337a: 0000 unimp + 337c: 00245113 srli sp,s0,0x2 + 3380: db00 sw s0,48(a4) + 3382: 8e05 sub a2,a2,s1 + ... + 338c: 0000 unimp + 338e: 0100 addi s0,sp,128 + 3390: 889c .2byte 0x889c + 3392: 0b00000b .4byte 0xb00000b + 3396: 2432 .2byte 0x2432 + 3398: 0000 unimp + 339a: c0dd beqz s1,3440 <__neorv32_ram_size+0x1440> + 339c: 0000 unimp + 339e: 4200 lw s0,0(a2) + 33a0: 0010 .2byte 0x10 + 33a2: 0000 unimp + 33a4: fa24 .2byte 0xfa24 + 33a6: cc000013 li zero,-832 + 33aa: 0b54 addi a3,sp,404 + 33ac: 0000 unimp + 33ae: 0018 .2byte 0x18 + 33b0: 0000 unimp + 33b2: 9c01 .2byte 0x9c01 + 33b4: 0ba9 addi s7,s7,10 + 33b6: 0000 unimp + 33b8: 632e .2byte 0x632e + 33ba: 0100 addi s0,sp,128 + 33bc: 1ecc addi a1,sp,884 + 33be: 000000e3 beqz zero,3bbe <__neorv32_ram_size+0x1bbe> + 33c2: 5a01 li s4,-32 + 33c4: 2500 .2byte 0x2500 + 33c6: 1fc1 addi t6,t6,-16 + 33c8: 0000 unimp + 33ca: 000000bf 00000000 .8byte 0xbf + 33d2: 0100 addi s0,sp,128 + 33d4: 259c .2byte 0x259c + 33d6: 2010 .2byte 0x2010 + 33d8: 0000 unimp + 33da: 00b6 slli ra,ra,0xd + 33dc: 0000 unimp + 33de: 0000 unimp + 33e0: 0000 unimp + 33e2: 0100 addi s0,sp,128 + 33e4: 249c .2byte 0x249c + 33e6: 0249 addi tp,tp,18 # 12 + 33e8: 0000 unimp + 33ea: a876 .2byte 0xa876 + 33ec: 000a c.slli zero,0x2 + 33ee: ac00 .2byte 0xac00 + 33f0: 0000 unimp + 33f2: 0100 addi s0,sp,128 + 33f4: 8b9c .2byte 0x8b9c + 33f6: 000c .2byte 0xc + 33f8: 1b00 addi s0,sp,432 + 33fa: 2042 .2byte 0x2042 + 33fc: 0000 unimp + 33fe: 0000c023 .4byte 0xc023 + 3402: 4e00 lw s0,24(a2) + 3404: 0010 .2byte 0x10 + 3406: 1b00 addi s0,sp,432 + 3408: 0000216b .4byte 0x216b + 340c: 9c35 .2byte 0x9c35 + 340e: 0000 unimp + 3410: 6800 .2byte 0x6800 + 3412: 0010 .2byte 0x10 + 3414: 1b00 addi s0,sp,432 + 3416: 2386 .2byte 0x2386 + 3418: 0000 unimp + 341a: 9c45 .2byte 0x9c45 + 341c: 0000 unimp + 341e: 8200 .2byte 0x8200 + 3420: 0010 .2byte 0x10 + 3422: 0b00 addi s0,sp,400 + 3424: 24e9 jal 36ee <__neorv32_ram_size+0x16ee> + 3426: 0000 unimp + 3428: c07a sw t5,0(sp) + 342a: 0000 unimp + 342c: 9c00 .2byte 0x9c00 + 342e: 0010 .2byte 0x10 + 3430: 1a00 addi s0,sp,304 + 3432: 0069 c.nop 26 + 3434: 00a80c7b .4byte 0xa80c7b + 3438: 0000 unimp + 343a: 10a8 addi a0,sp,104 + 343c: 0000 unimp + 343e: 701a .2byte 0x701a + 3440: 7c00 .2byte 0x7c00 + 3442: 00009c0b .4byte 0x9c0b + 3446: c000 sw s0,0(s0) + 3448: 0010 .2byte 0x10 + 344a: 0b00 addi s0,sp,400 + 344c: 236a .2byte 0x236a + 344e: 0000 unimp + 3450: 0000c093 xori ra,ra,0 + 3454: ee00 .2byte 0xee00 + 3456: 0010 .2byte 0x10 + 3458: 0b00 addi s0,sp,400 + 345a: 2006 .2byte 0x2006 + 345c: 0000 unimp + 345e: c096 sw t0,64(sp) + 3460: 0000 unimp + 3462: 0900 addi s0,sp,144 + 3464: 0011 c.nop 4 + 3466: 0b00 addi s0,sp,400 + 3468: 2346 .2byte 0x2346 + 346a: 0000 unimp + 346c: c09a sw t1,64(sp) + 346e: 0000 unimp + 3470: 2f00 .2byte 0x2f00 + 3472: 0011 c.nop 4 + 3474: 0b00 addi s0,sp,400 + 3476: 1fd6 slli t6,t6,0x35 + 3478: 0000 unimp + 347a: c09d beqz s1,34a0 <__neorv32_ram_size+0x14a0> + 347c: 0000 unimp + 347e: 3e00 .2byte 0x3e00 + 3480: 0011 c.nop 4 + 3482: 2f00 .2byte 0x2f00 + 3484: 24fa .2byte 0x24fa + 3486: 0000 unimp + 3488: a001 j 3488 <__neorv32_ram_size+0x1488> + 348a: c00c sw a1,0(s0) + 348c: 0000 unimp + 348e: 0b00 addi s0,sp,400 + 3490: 24e0 .2byte 0x24e0 + 3492: 0000 unimp + 3494: c0ac sw a1,64(s1) + 3496: 0000 unimp + 3498: 5900 lw s0,48(a0) + 349a: 0011 c.nop 4 + 349c: 0400 addi s0,sp,512 + 349e: 0ad4 addi a3,sp,340 + 34a0: 0000 unimp + 34a2: 0d32 slli s10,s10,0xc + 34a4: 0000 unimp + 34a6: 3000 .2byte 0x3000 + 34a8: 0e7c addi a5,sp,796 + 34aa: 0000 unimp + 34ac: 5f01 li t5,-32 + 34ae: 8e05 sub a2,a2,s1 + 34b0: 0000 unimp + 34b2: 9800 .2byte 0x9800 + 34b4: 000a c.slli zero,0x2 + 34b6: 1000 addi s0,sp,32 + 34b8: 0000 unimp + 34ba: 0100 addi s0,sp,128 + 34bc: 139c addi a5,sp,480 + 34be: 00002437 lui s0,0x2 + 34c2: 0550 addi a2,sp,644 + 34c4: 008e slli ra,ra,0x3 + ... + 34ce: 0000 unimp + 34d0: 9c01 .2byte 0x9c01 + 34d2: 0cc4 addi s1,sp,596 + 34d4: 0000 unimp + 34d6: 0004 .2byte 0x4 + 34d8: 0000 unimp + 34da: 3900 .2byte 0x3900 + 34dc: 0000000b .4byte 0xb + 34e0: 00211a13 slli s4,sp,0x2 + 34e4: 4400 lw s0,8(s0) + 34e6: 8e05 sub a2,a2,s1 + ... + 34f0: 0000 unimp + 34f2: 0100 addi s0,sp,128 + 34f4: fd9c .2byte 0xfd9c + 34f6: 000c .2byte 0xc + 34f8: 3100 .2byte 0x3100 + 34fa: 01006863 bltu zero,a6,350a <__neorv32_ram_size+0x150a> + 34fe: 1144 addi s1,sp,164 + 3500: 008e slli ra,ra,0x3 + 3502: 0000 unimp + 3504: 1166 slli sp,sp,0x39 + 3506: 0000 unimp + 3508: 0000000f fence unknown,unknown + 350c: 8800 .2byte 0x8800 + 350e: 0200000b .4byte 0x200000b + 3512: 5a01 li s4,-32 + 3514: 7802 .2byte 0x7802 + 3516: 0000 unimp + 3518: 3200 .2byte 0x3200 + 351a: 0380 addi s0,sp,448 + 351c: 0000 unimp + 351e: 0a6c addi a1,sp,284 + 3520: 0000 unimp + 3522: 002c addi a1,sp,8 + 3524: 0000 unimp + 3526: 9c01 .2byte 0x9c01 + 3528: 0d29 addi s10,s10,10 + 352a: 0000 unimp + 352c: 00039833 sll a6,t2,zero + 3530: 8800 .2byte 0x8800 + 3532: 0011 c.nop 4 + 3534: 3400 .2byte 0x3400 + 3536: 03a2 slli t2,t2,0x8 + 3538: 0000 unimp + 353a: 119f 0000 8e35 .byte 0x9f, 0x11, 0x00, 0x00, 0x35, 0x8e + 3540: 0b000003 lb zero,176(zero) # b0 <__crt0_clear_bss> + 3544: 2600 .2byte 0x2600 + 3546: 1f84 addi s1,sp,1008 + 3548: 0000 unimp + 354a: 1f84 addi s1,sp,1008 + 354c: 0000 unimp + 354e: 2f26 .2byte 0x2f26 + 3550: 0029 c.nop 10 + 3552: 2f00 .2byte 0x2f00 + 3554: 0029 c.nop 10 + 3556: 0000 unimp + 3558: 0bc4 addi s1,sp,468 + 355a: 0000 unimp + 355c: 0005 c.nop 1 + 355e: 0401 addi s0,s0,0 # 2000 <__neorv32_ram_size> + 3560: 0b7f .2byte 0xb7f + 3562: 0000 unimp + 3564: 1d1d addi s10,s10,-25 + 3566: 0001 nop + 3568: 1d00 addi s0,sp,688 + 356a: 00000277 .4byte 0x277 + 356e: 0198 addi a4,sp,192 + 3570: 0000 unimp + 3572: 03c1 addi t2,t2,16 + 3574: 0000 unimp + 3576: 0000 unimp + 3578: 0000 unimp + 357a: 37a5 jal 34e2 <__neorv32_ram_size+0x14e2> + 357c: 0000 unimp + 357e: 0108 addi a0,sp,128 + 3580: e906 .2byte 0xe906 + 3582: 0000 unimp + 3584: 0800 addi s0,sp,16 + 3586: 0801 addi a6,a6,0 + 3588: 000000e7 jalr zero # 0 <__crt0_entry> + 358c: 0208 addi a0,sp,256 + 358e: 2805 jal 35be <__neorv32_ram_size+0x15be> + 3590: 0002 c.slli64 zero + 3592: 0800 addi s0,sp,16 + 3594: 0702 c.slli64 a4 + 3596: 003a c.slli zero,0xe + 3598: 0000 unimp + 359a: 0408 addi a0,sp,512 + 359c: ff05 bnez a4,34d4 <__neorv32_ram_size+0x14d4> + 359e: 0001 nop + 35a0: 0100 addi s0,sp,128 + 35a2: 00000197 auipc gp,0x0 + 35a6: 4f02 lw t5,0(sp) + 35a8: 5519 li a0,-26 + 35aa: 0000 unimp + 35ac: 0800 addi s0,sp,16 + 35ae: 0704 addi s1,sp,896 + 35b0: 000000bb .4byte 0xbb + 35b4: 0808 addi a0,sp,16 + 35b6: fa05 bnez a2,34e6 <__neorv32_ram_size+0x14e6> + 35b8: 0001 nop + 35ba: 0800 addi s0,sp,16 + 35bc: 0708 addi a0,sp,896 + 35be: 00b6 slli ra,ra,0xd + 35c0: 0000 unimp + 35c2: a601 j 38c2 <__neorv32_ram_size+0x18c2> + 35c4: 0025 c.nop 9 + 35c6: 0200 addi s0,sp,256 + 35c8: 1ec8 addi a0,sp,884 + 35ca: 005c addi a5,sp,4 + 35cc: 0000 unimp + 35ce: 041e slli s0,s0,0x7 + 35d0: 6905 lui s2,0x1 + 35d2: 746e .2byte 0x746e + 35d4: 0800 addi s0,sp,16 + 35d6: 0704 addi s1,sp,896 + 35d8: 00c0 addi s0,sp,68 + 35da: 0000 unimp + 35dc: b701 j 34dc <__neorv32_ram_size+0x14dc> + 35de: 0026 c.slli zero,0x9 + 35e0: 0300 addi s0,sp,384 + 35e2: 1a91 addi s5,s5,-28 + 35e4: 0076 c.slli zero,0x1d + 35e6: 0000 unimp + 35e8: f601 bnez a2,34f0 <__neorv32_ram_size+0x14f0> + 35ea: 0026 c.slli zero,0x9 + 35ec: 0300 addi s0,sp,384 + 35ee: 17d6 slli a5,a5,0x35 + 35f0: 007d c.nop 31 + 35f2: 0000 unimp + 35f4: 1008 addi a0,sp,32 + 35f6: 5d04 lw s1,56(a0) + 35f8: 0002 c.slli64 zero + 35fa: 0100 addi s0,sp,128 + 35fc: 000025d7 .4byte 0x25d7 + 3600: 1e04 addi s1,sp,816 + 3602: 420e lw tp,192(sp) + 3604: 0000 unimp + 3606: 0100 addi s0,sp,128 + 3608: 26f1 jal 39d4 <__neorv32_ram_size+0x19d4> + 360a: 0000 unimp + 360c: 2204 .2byte 0x2204 + 360e: 420e lw tp,192(sp) + 3610: 0000 unimp + 3612: 0100 addi s0,sp,128 + 3614: 2536 .2byte 0x2536 + 3616: 0000 unimp + 3618: 2e04 .2byte 0x2e04 + 361a: 420e lw tp,192(sp) + 361c: 0000 unimp + 361e: 0100 addi s0,sp,128 + 3620: 26d0 .2byte 0x26d0 + 3622: 0000 unimp + 3624: 3804 .2byte 0x3804 + 3626: 0000340f .4byte 0x340f + 362a: 0100 addi s0,sp,128 + 362c: 2794 .2byte 0x2794 + 362e: 0000 unimp + 3630: 3c04 .2byte 0x3c04 + 3632: 3b18 .2byte 0x3b18 + 3634: 0000 unimp + 3636: 0100 addi s0,sp,128 + 3638: 253d jal 3c66 <__neorv32_ram_size+0x1c66> + 363a: 0000 unimp + 363c: 3f04 .2byte 0x3f04 + 363e: 3b18 .2byte 0x3b18 + 3640: 0000 unimp + 3642: 0100 addi s0,sp,128 + 3644: 2762 .2byte 0x2762 + 3646: 0000 unimp + 3648: 4b04 lw s1,16(a4) + 364a: 3b18 .2byte 0x3b18 + 364c: 0000 unimp + 364e: 0100 addi s0,sp,128 + 3650: 25bd jal 3cbe <__neorv32_ram_size+0x1cbe> + 3652: 0000 unimp + 3654: 5a04 lw s1,48(a2) + 3656: 4914 lw a3,16(a0) + 3658: 0000 unimp + 365a: 0100 addi s0,sp,128 + 365c: 2535 jal 3c88 <__neorv32_ram_size+0x1c88> + 365e: 0000 unimp + 3660: 6604 .2byte 0x6604 + 3662: bb10 .2byte 0xbb10 + 3664: 0000 unimp + 3666: 0100 addi s0,sp,128 + 3668: 27fa .2byte 0x27fa + 366a: 0000 unimp + 366c: 9304 .2byte 0x9304 + 366e: 00007617 auipc a2,0x7 + 3672: 1f00 addi s0,sp,944 + 3674: 0104 addi s1,sp,128 + 3676: 267e .2byte 0x267e + 3678: 0000 unimp + 367a: d104 sw s1,32(a0) + 367c: 3b18 .2byte 0x3b18 + 367e: 0000 unimp + 3680: 0100 addi s0,sp,128 + 3682: 2662 .2byte 0x2662 + 3684: 0000 unimp + 3686: d204 sw s1,32(a2) + 3688: 0000420f .4byte 0x420f + 368c: 0600 addi s0,sp,768 + 368e: 0000013f 0001350e .8byte 0x1350e0000013f + 3696: 0800 addi s0,sp,16 + 3698: 0801 addi a6,a6,0 + 369a: 00f0 addi a2,sp,76 + 369c: 0000 unimp + 369e: 3f0e .2byte 0x3f0e + 36a0: 0001 nop + 36a2: 0600 addi s0,sp,768 + 36a4: 0146 slli sp,sp,0x11 + 36a6: 0000 unimp + 36a8: 6401 .2byte 0x6401 + 36aa: 0026 c.slli zero,0x9 + 36ac: 0500 addi s0,sp,640 + 36ae: 1725 addi a4,a4,-23 + 36b0: 0129 addi sp,sp,10 + 36b2: 0000 unimp + 36b4: 8501 c.srai64 a0 + 36b6: 05000003 lb zero,80(zero) # 50 + 36ba: 122a slli tp,tp,0x2a + 36bc: 006a c.slli zero,0x1a + 36be: 0000 unimp + 36c0: 0026a10b .4byte 0x26a10b + 36c4: 1000 addi s0,sp,32 + 36c6: 3605 jal 31e6 <__neorv32_ram_size+0x11e6> + 36c8: 0000018f .4byte 0x18f + 36cc: de02 sw zero,60(sp) + 36ce: 0026 c.slli zero,0x9 + 36d0: 0500 addi s0,sp,640 + 36d2: 015c0a37 lui s4,0x15c0 + 36d6: 0000 unimp + 36d8: 0200 addi s0,sp,256 + 36da: 276a .2byte 0x276a + 36dc: 0000 unimp + 36de: 3805 jal 2f0e <__neorv32_ram_size+0xf0e> + 36e0: 500e .2byte 0x500e + 36e2: 0001 nop + 36e4: 0800 addi s0,sp,16 + 36e6: 0b00 addi s0,sp,400 + 36e8: 2750 .2byte 0x2750 + 36ea: 0000 unimp + 36ec: 0610 addi a2,sp,768 + 36ee: 0001b62f .4byte 0x1b62f + 36f2: 0200 addi s0,sp,256 + 36f4: 26de .2byte 0x26de + 36f6: 0000 unimp + 36f8: 3006 .2byte 0x3006 + 36fa: 5c09 li s8,-30 + 36fc: 0001 nop + 36fe: 0000 unimp + 3700: c802 sw zero,16(sp) + 3702: 0026 c.slli zero,0x9 + 3704: 0600 addi s0,sp,768 + 3706: 0731 addi a4,a4,12 + 3708: 0042 c.slli zero,0x10 + 370a: 0000 unimp + 370c: 0008 .2byte 0x8 + 370e: 8f0e mv t5,gp + 3710: 0001 nop + 3712: 0100 addi s0,sp,128 + 3714: 25d9 jal 3dda <__neorv32_ram_size+0x1dda> + 3716: 0000 unimp + 3718: a3146107 .4byte 0xa3146107 + 371c: 0000 unimp + 371e: 0100 addi s0,sp,128 + 3720: 000026f3 csrr a3,ustatus + 3724: af156607 .4byte 0xaf156607 + 3728: 0000 unimp + 372a: 0100 addi s0,sp,128 + 372c: 00002613 slti a2,zero,0 + 3730: 55136b07 .4byte 0x55136b07 + 3734: 0000 unimp + 3736: 0100 addi s0,sp,128 + 3738: 2764 .2byte 0x2764 + 373a: 0000 unimp + 373c: eb128b07 .4byte 0xeb128b07 + 3740: 0000 unimp + 3742: 0100 addi s0,sp,128 + 3744: 00002537 lui a0,0x2 + 3748: 03129d07 .4byte 0x3129d07 + 374c: 0001 nop + 374e: 0100 addi s0,sp,128 + 3750: 26d2 .2byte 0x26d2 + 3752: 0000 unimp + 3754: c712a107 .4byte 0xc712a107 + 3758: 0000 unimp + 375a: 0100 addi s0,sp,128 + 375c: 2796 .2byte 0x2796 + 375e: 0000 unimp + 3760: d312a507 .4byte 0xd312a507 + 3764: 0000 unimp + 3766: 0100 addi s0,sp,128 + 3768: 0000253f df12a907 .8byte 0xdf12a9070000253f + 3770: 0000 unimp + 3772: 0100 addi s0,sp,128 + 3774: 000027fb .4byte 0x27fb + 3778: 0f12b807 .4byte 0xf12b807 + 377c: 0001 nop + 377e: 0100 addi s0,sp,128 + 3780: 000025bf f712bd07 .8byte 0xf712bd07000025bf + 3788: 0000 unimp + 378a: 0100 addi s0,sp,128 + 378c: 2680 .2byte 0x2680 + 378e: 0000 unimp + 3790: 1d13c207 .4byte 0x1d13c207 + 3794: 0001 nop + 3796: 0b00 addi s0,sp,400 + 3798: 26d9 jal 3b5e <__neorv32_ram_size+0x1b5e> + 379a: 0000 unimp + 379c: 0858 addi a4,sp,20 + 379e: 0003021b .4byte 0x3021b + 37a2: 0200 addi s0,sp,256 + 37a4: 000027f3 csrr a5,ustatus + 37a8: 1d08 addi a0,sp,688 + 37aa: f70a .2byte 0xf70a + 37ac: 0001 nop + 37ae: 0000 unimp + 37b0: b602 .2byte 0xb602 + 37b2: 0025 c.nop 9 + 37b4: 0800 addi s0,sp,16 + 37b6: 0a1e slli s4,s4,0x7 + 37b8: 01df 0000 0202 .byte 0xdf, 0x01, 0x00, 0x00, 0x02, 0x02 + 37be: 279c .2byte 0x279c + 37c0: 0000 unimp + 37c2: 1f08 addi a0,sp,944 + 37c4: 270a .2byte 0x270a + 37c6: 0002 c.slli64 zero + 37c8: 0400 addi s0,sp,512 + 37ca: 1202 slli tp,tp,0x20 + 37cc: 08000027 .4byte 0x8000027 + 37d0: 0b20 addi s0,sp,408 + 37d2: 00000233 add tp,zero,zero + 37d6: 0208 addi a0,sp,256 + 37d8: 0000263b .4byte 0x263b + 37dc: 2108 .2byte 0x2108 + 37de: 030a slli t1,t1,0x2 + 37e0: 0002 c.slli64 zero + 37e2: 0a00 addi s0,sp,272 + 37e4: b302 .2byte 0xb302 + 37e6: 08000027 .4byte 0x8000027 + 37ea: 0a22 slli s4,s4,0x8 + 37ec: 0000020f .4byte 0x20f + 37f0: 020c addi a1,sp,256 + 37f2: 2778 .2byte 0x2778 + 37f4: 0000 unimp + 37f6: 2308 .2byte 0x2308 + 37f8: f70a .2byte 0xf70a + 37fa: 0001 nop + 37fc: 0e00 addi s0,sp,784 + 37fe: af02 .2byte 0xaf02 + 3800: 0026 c.slli zero,0x9 + 3802: 0800 addi s0,sp,16 + 3804: 0a24 addi s1,sp,280 + 3806: 000001eb .4byte 0x1eb + 380a: 0210 addi a2,sp,256 + 380c: 0000260b .4byte 0x260b + 3810: 2a08 .2byte 0x2a08 + 3812: 00018f13 mv t5,gp + 3816: 1800 addi s0,sp,48 + 3818: 1002 c.slli zero,0x20 + 381a: 0028 addi a0,sp,8 + 381c: 0800 addi s0,sp,16 + 381e: 018f132b .4byte 0x18f132b + 3822: 0000 unimp + 3824: 0228 addi a0,sp,264 + 3826: 254a .2byte 0x254a + 3828: 0000 unimp + 382a: 2c08 .2byte 0x2c08 + 382c: 00018f13 mv t5,gp + 3830: 3800 .2byte 0x3800 + 3832: 3b02 .2byte 0x3b02 + 3834: 08000027 .4byte 0x8000027 + 3838: 112d addi sp,sp,-21 + 383a: 000001c7 .4byte 0x1c7 + 383e: 0248 addi a0,sp,260 + 3840: 2631 jal 3b4c <__neorv32_ram_size+0x1b4c> + 3842: 0000 unimp + 3844: 2e08 .2byte 0x2e08 + 3846: bb0c .2byte 0xbb0c + 3848: 0001 nop + 384a: 4c00 lw s0,24(s0) + 384c: 4202 lw tp,0(sp) + 384e: 0026 c.slli zero,0x9 + 3850: 0800 addi s0,sp,16 + 3852: 0930 addi a2,sp,152 + 3854: 0302 c.slli64 t1 + 3856: 0000 unimp + 3858: 0050 addi a2,sp,4 + 385a: 4215 li tp,5 + 385c: 0000 unimp + 385e: 1200 addi s0,sp,288 + 3860: 20000003 lb zero,512(zero) # 200 + 3864: 007d c.nop 31 + 3866: 0000 unimp + 3868: 0001 nop + 386a: 0027ed0b .4byte 0x27ed0b + 386e: 1000 addi s0,sp,32 + 3870: 1a09 addi s4,s4,-30 # 15bffe2 <__neorv32_ram_size+0x15bdfe2> + 3872: 00000353 .4byte 0x353 + 3876: 7b02 .2byte 0x7b02 + 3878: 0002 c.slli64 zero + 387a: 0900 addi s0,sp,144 + 387c: 0a1c addi a5,sp,272 + 387e: 015c addi a5,sp,132 + 3880: 0000 unimp + 3882: 0200 addi s0,sp,256 + 3884: 2629 jal 3b8e <__neorv32_ram_size+0x1b8e> + 3886: 0000 unimp + 3888: 1d09 addi s10,s10,-30 + 388a: 3b12 .2byte 0x3b12 + 388c: 0000 unimp + 388e: 0800 addi s0,sp,16 + 3890: 2002 .2byte 0x2002 + 3892: 0026 c.slli zero,0x9 + 3894: 0900 addi s0,sp,144 + 3896: 091e slli s2,s2,0x7 + 3898: 0034 addi a3,sp,8 + 389a: 0000 unimp + 389c: 020a slli tp,tp,0x2 + 389e: 00002563 .4byte 0x2563 + 38a2: 1f09 addi t5,t5,-30 + 38a4: 3409 jal 32a6 <__neorv32_ram_size+0x12a6> + 38a6: 0000 unimp + 38a8: 0c00 addi s0,sp,528 + 38aa: 2100 .2byte 0x2100 + 38ac: 6d74 .2byte 0x6d74 + 38ae: 0a100073 .4byte 0xa100073 + 38b2: 0811 addi a6,a6,4 + 38b4: 0395 addi t2,t2,5 + 38b6: 0000 unimp + 38b8: 4602 lw a2,0(sp) + 38ba: 0a000027 .4byte 0xa000027 + 38be: 0a12 slli s4,s4,0x4 + 38c0: 000001d3 .4byte 0x1d3 + 38c4: 0200 addi s0,sp,256 + 38c6: 000025eb .4byte 0x25eb + 38ca: 130a slli t1,t1,0x22 + 38cc: d30a sw sp,164(sp) + 38ce: 0001 nop + 38d0: 0400 addi s0,sp,512 + 38d2: 9002 ebreak + 38d4: 0025 c.nop 9 + 38d6: 0a00 addi s0,sp,272 + 38d8: 0a14 addi a3,sp,272 + 38da: 000001d3 .4byte 0x1d3 + 38de: 0208 addi a0,sp,256 + 38e0: 27c2 .2byte 0x27c2 + 38e2: 0000 unimp + 38e4: 150a slli a0,a0,0x22 + 38e6: d30a sw sp,164(sp) + 38e8: 0001 nop + 38ea: 0c00 addi s0,sp,528 + 38ec: 0b00 addi s0,sp,400 + 38ee: 265a .2byte 0x265a + 38f0: 0000 unimp + 38f2: 0b10 addi a2,sp,400 + 38f4: bc0c .2byte 0xbc0c + 38f6: 02000003 lb zero,32(zero) # 20 + 38fa: 252e .2byte 0x252e + 38fc: 0000 unimp + 38fe: 5c0a0e0b .4byte 0x5c0a0e0b + 3902: 0001 nop + 3904: 0000 unimp + 3906: 8c02 jr s8 + 3908: 0b000027 .4byte 0xb000027 + 390c: 015c0a0f .4byte 0x15c0a0f + 3910: 0000 unimp + 3912: 0008 .2byte 0x8 + 3914: 950e add a0,a0,gp + 3916: 06000003 lb zero,96(zero) # 60 + 391a: 03c6 slli t2,t2,0x11 + 391c: 0000 unimp + 391e: 2322 .2byte 0x2322 + 3920: 26a9 jal 3c6a <__neorv32_ram_size+0x1c6a> + 3922: 0000 unimp + 3924: 2901 jal 3d34 <__neorv32_ram_size+0x1d34> + 3926: 760c .2byte 0x760c + 3928: 0000 unimp + 392a: 1500 addi s0,sp,672 + 392c: 0000013f 000003de .8byte 0x3de0000013f + 3934: 0024 addi s1,sp,8 + 3936: e016 .2byte 0xe016 + 3938: 10000027 .4byte 0x10000027 + 393c: d301 beqz a4,383c <__neorv32_ram_size+0x183c> + 393e: 16000003 lb zero,352(zero) # 160 <__crt0_trap_handler+0x24> + 3942: 0000259b .4byte 0x259b + 3946: 0111 addi sp,sp,4 + 3948: 000003d3 .4byte 0x3d3 + 394c: 6225 lui tp,0x9 + 394e: 6b72 .2byte 0x6b72 + 3950: 0100 addi s0,sp,128 + 3952: 0112 slli sp,sp,0x4 + 3954: 350e .2byte 0x350e + 3956: 0001 nop + 3958: 0500 addi s0,sp,640 + 395a: 00083003 .4byte 0x83003 + 395e: 1780 addi s0,sp,992 + 3960: 13fa slli t2,t2,0x3e + 3962: 0000 unimp + 3964: 1738 addi a4,sp,936 + 3966: 0004 .2byte 0x4 + 3968: 1800 addi s0,sp,48 + 396a: 0000013f 21071900 .8byte 0x210719000000013f + 3972: 0000 unimp + 3974: 3f3a .2byte 0x3f3a + 3976: 0001 nop + 3978: 1700 addi s0,sp,928 + 397a: 00cd addi ra,ra,19 + 397c: 0000 unimp + 397e: 313e .2byte 0x313e + 3980: 0004 .2byte 0x4 + 3982: 1800 addi s0,sp,48 + 3984: 0000014b .4byte 0x14b + 3988: 1900 addi s0,sp,176 + 398a: 0e7c addi a5,sp,796 + 398c: 0000 unimp + 398e: 7634 .2byte 0x7634 + 3990: 0000 unimp + 3992: 1200 addi s0,sp,288 + 3994: 2832 .2byte 0x2832 + 3996: 0000 unimp + 3998: 011a slli sp,sp,0x6 + 399a: 00011b07 .4byte 0x11b07 + 399e: 9c00 .2byte 0x9c00 + 39a0: 000d c.nop 3 + 39a2: 3800 .2byte 0x3800 + 39a4: 0000 unimp + 39a6: 0100 addi s0,sp,128 + 39a8: 769c .2byte 0x769c + 39aa: 0004 .2byte 0x4 + 39ac: 1300 addi s0,sp,416 + 39ae: 282d jal 39e8 <__neorv32_ram_size+0x19e8> + 39b0: 0000 unimp + 39b2: 011a slli sp,sp,0x6 + 39b4: 00008417 auipc s0,0x8 + 39b8: c400 sw s0,8(s0) + 39ba: 0011 c.nop 4 + 39bc: 1a00 addi s0,sp,304 + 39be: 2676 .2byte 0x2676 + 39c0: 0000 unimp + 39c2: 011c addi a5,sp,128 + 39c4: 0001350b .4byte 0x1350b + 39c8: db00 sw s0,48(a4) + 39ca: 0011 c.nop 4 + 39cc: 0000 unimp + 39ce: 7912 .2byte 0x7912 + 39d0: 0026 c.slli zero,0x9 + 39d2: 1400 addi s0,sp,544 + 39d4: 0501 addi a0,a0,0 # 2000 <__neorv32_ram_size> + 39d6: 0076 c.slli zero,0x1d + ... + 39e0: 0000 unimp + 39e2: 9c01 .2byte 0x9c01 + 39e4: 04a1 addi s1,s1,8 + 39e6: 0000 unimp + 39e8: 00131213 slli tp,t1,0x1 + 39ec: 1400 addi s0,sp,544 + 39ee: 1001 c.nop -32 + 39f0: 0000011b .4byte 0x11b + 39f4: 11f6 slli gp,gp,0x3d + 39f6: 0000 unimp + 39f8: 1200 addi s0,sp,288 + 39fa: 00001da3 sh zero,27(zero) # 1b + 39fe: 0101 addi sp,sp,0 + 3a00: 1b09 addi s6,s6,-30 + 3a02: 0002 c.slli64 zero + ... + 3a0c: 0100 addi s0,sp,128 + 3a0e: 0a9c addi a5,sp,336 + 3a10: 0005 c.nop 1 + 3a12: 1300 addi s0,sp,416 + 3a14: 2736 .2byte 0x2736 + 3a16: 0000 unimp + 3a18: 0101 addi sp,sp,0 + 3a1a: 7614 .2byte 0x7614 + 3a1c: 0000 unimp + 3a1e: 1100 addi s0,sp,160 + 3a20: 0012 c.slli zero,0x4 + 3a22: 1b00 addi s0,sp,432 + 3a24: 7470 .2byte 0x7470 + 3a26: 0072 c.slli zero,0x1c + 3a28: c126 sw s1,128(sp) + 3a2a: 2b000003 lb zero,688(zero) # 2b0 <__neorv32_rte_core+0x4> + 3a2e: 0012 c.slli zero,0x4 + 3a30: 1b00 addi s0,sp,432 + 3a32: 656c .2byte 0x656c + 3a34: 006e c.slli zero,0x1b + 3a36: 9032 c.add zero,a2 + 3a38: 0000 unimp + 3a3a: 4d00 lw s0,24(a0) + 3a3c: 0012 c.slli zero,0x4 + 3a3e: 1a00 addi s0,sp,304 + 3a40: 2706 .2byte 0x2706 + 3a42: 0000 unimp + 3a44: 0104 addi s1,sp,128 + 3a46: c111 beqz a0,3a4a <__neorv32_ram_size+0x1a4a> + 3a48: 7d000003 lb zero,2000(zero) # 7d0 <__neorv32_rte_debug_handler+0x26c> + 3a4c: 0012 c.slli zero,0x4 + 3a4e: 0c00 addi s0,sp,528 + 3a50: 0000 unimp + 3a52: 0000 unimp + 3a54: 0431 addi s0,s0,12 # b9c0 <__neorv32_ram_size+0x99c0> + 3a56: 0000 unimp + 3a58: 000c .2byte 0xc + 3a5a: 0000 unimp + 3a5c: 0700 addi s0,sp,896 + 3a5e: 0004 .2byte 0x4 + 3a60: 0000 unimp + 3a62: 0026eb03 .4byte 0x26eb03 + 3a66: fb00 .2byte 0xfb00 + 3a68: 7605 lui a2,0xfffe1 + ... + 3a72: 0000 unimp + 3a74: 0100 addi s0,sp,128 + 3a76: 339c .2byte 0x339c + 3a78: 0005 c.nop 1 + 3a7a: 0500 addi s0,sp,640 + 3a7c: 0000272f .4byte 0x272f + 3a80: 053310fb .4byte 0x53310fb + 3a84: 0000 unimp + 3a86: 12c6 slli t0,t0,0x31 + 3a88: 0000 unimp + 3a8a: 0600 addi s0,sp,768 + 3a8c: 0076 c.slli zero,0x1d + 3a8e: 0000 unimp + 3a90: 490d li s2,3 + 3a92: f5000027 .4byte 0xf5000027 + 3a96: 7605 lui a2,0xfffe1 + 3a98: 0000 unimp + 3a9a: 5e00 lw s0,56(a2) + 3a9c: 0005 c.nop 1 + 3a9e: 0400 addi s0,sp,512 + 3aa0: 2581 jal 40e0 <__neorv32_ram_size+0x20e0> + 3aa2: 0000 unimp + 3aa4: 18f5 addi a7,a7,-3 + 3aa6: 0000014b .4byte 0x14b + 3aaa: 0404 addi s1,sp,512 + 3aac: 0028 addi a0,sp,8 + 3aae: f500 .2byte 0xf500 + 3ab0: 5e34 lw a3,120(a2) + 3ab2: 0005 c.nop 1 + 3ab4: 0000 unimp + 3ab6: bc06 .2byte 0xbc06 + 3ab8: 03000003 lb zero,48(zero) # 30 + 3abc: 2818 .2byte 0x2818 + 3abe: 0000 unimp + 3ac0: 007605ef jal a1,642c6 <__neorv32_ram_size+0x622c6> + ... + 3acc: 0000 unimp + 3ace: 9c01 .2byte 0x9c01 + 3ad0: 058c addi a1,sp,704 + 3ad2: 0000 unimp + 3ad4: 0105 addi sp,sp,1 + 3ad6: ef000027 .4byte 0xef000027 + 3ada: 4b19 li s6,6 + 3adc: 0001 nop + 3ade: e000 .2byte 0xe000 + 3ae0: 0012 c.slli zero,0x4 + 3ae2: 0000 unimp + 3ae4: 00280303 lb t1,2(a6) + 3ae8: ea00 .2byte 0xea00 + 3aea: d309 beqz a4,39ec <__neorv32_ram_size+0x19ec> + 3aec: 0001 nop + ... + 3af6: 0100 addi s0,sp,128 + 3af8: b59c .2byte 0xb59c + 3afa: 0005 c.nop 1 + 3afc: 0a00 addi s0,sp,272 + 3afe: 7562 .2byte 0x7562 + 3b00: 0066 c.slli zero,0x19 + 3b02: 1cea slli s9,s9,0x3a + 3b04: 05b5 addi a1,a1,13 + 3b06: 0000 unimp + 3b08: 12fa slli t0,t0,0x3e + 3b0a: 0000 unimp + 3b0c: 0600 addi s0,sp,768 + 3b0e: 00000353 .4byte 0x353 + 3b12: e20d bnez a2,3b34 <__neorv32_ram_size+0x1b34> + 3b14: 0025 c.nop 9 + 3b16: e400 .2byte 0xe400 + 3b18: 4206 lw tp,64(sp) + 3b1a: 0000 unimp + 3b1c: d500 sw s0,40(a0) + 3b1e: 0005 c.nop 1 + 3b20: 0400 addi s0,sp,512 + 3b22: 2701 jal 4222 <__neorv32_ram_size+0x2222> + 3b24: 0000 unimp + 3b26: 13e4 addi s1,sp,492 + 3b28: 0076 c.slli zero,0x1d + 3b2a: 0000 unimp + 3b2c: 0300 addi s0,sp,384 + 3b2e: 26d8 .2byte 0x26d8 + 3b30: 0000 unimp + 3b32: 05dc addi a5,sp,708 + 3b34: 0076 c.slli zero,0x1d + ... + 3b3e: 0000 unimp + 3b40: 9c01 .2byte 0x9c01 + 3b42: 060a slli a2,a2,0x2 + 3b44: 0000 unimp + 3b46: 3605 jal 3666 <__neorv32_ram_size+0x1666> + 3b48: dc000027 .4byte 0xdc000027 + 3b4c: 00014b17 auipc s6,0x14 + 3b50: 1400 addi s0,sp,544 + 3b52: 09000013 li zero,144 + 3b56: dc007473 csrrci s0,0xdc0,0 + 3b5a: 0a2a slli s4,s4,0xa + 3b5c: 0006 c.slli zero,0x1 + 3b5e: 0100 addi s0,sp,128 + 3b60: 3f06005b .4byte 0x3f06005b + 3b64: 0002 c.slli64 zero + 3b66: 0300 addi s0,sp,384 + 3b68: 1112 slli sp,sp,0x24 + 3b6a: 0000 unimp + 3b6c: 09ca slli s3,s3,0x12 + 3b6e: 0000021b .4byte 0x21b + ... + 3b7a: 9c01 .2byte 0x9c01 + 3b7c: 0694 addi a3,sp,832 + 3b7e: 0000 unimp + 3b80: 3605 jal 36a0 <__neorv32_ram_size+0x16a0> + 3b82: ca000027 .4byte 0xca000027 + 3b86: 00007613 andi a2,zero,0 + 3b8a: 2e00 .2byte 0x2e00 + 3b8c: 0a000013 li zero,160 + 3b90: 7470 .2byte 0x7470 + 3b92: 0072 c.slli zero,0x1c + 3b94: 1fca slli t6,t6,0x32 + 3b96: 0000011b .4byte 0x11b + 3b9a: 1348 addi a0,sp,420 + 3b9c: 0000 unimp + 3b9e: 6c0a .2byte 0x6c0a + 3ba0: 6e65 lui t3,0x19 + 3ba2: ca00 sw s0,16(a2) + 3ba4: 0000902b .4byte 0x902b + 3ba8: 6d00 .2byte 0x6d00 + 3baa: 26000013 li zero,608 + 3bae: 2759 jal 4334 <__neorv32_ram_size+0x2334> + 3bb0: 0000 unimp + 3bb2: cc01 beqz s0,3bca <__neorv32_ram_size+0x1bca> + 3bb4: 7609 lui a2,0xfffe2 + 3bb6: 0000 unimp + 3bb8: 8f00 .2byte 0x8f00 + 3bba: 27000013 li zero,624 + ... + 3bc6: 068a slli a3,a3,0x2 + 3bc8: 0000 unimp + 3bca: 8828 .2byte 0x8828 + 3bcc: 0026 c.slli zero,0x9 + 3bce: 0100 addi s0,sp,128 + 3bd0: 0dd0 addi a2,sp,724 + 3bd2: 0135 addi sp,sp,13 + 3bd4: 0000 unimp + 3bd6: 5801 li a6,-32 + 3bd8: 000c .2byte 0xc + 3bda: 0000 unimp + 3bdc: 1700 addi s0,sp,928 + 3bde: 0004 .2byte 0x4 + 3be0: 0000 unimp + 3be2: 000c .2byte 0xc + 3be4: 0000 unimp + 3be6: 3100 .2byte 0x3100 + 3be8: 0004 .2byte 0x4 + 3bea: 0000 unimp + 3bec: 520d li tp,-29 + 3bee: 0025 c.nop 9 + 3bf0: c400 sw s0,8(s0) + 3bf2: 7605 lui a2,0xfffe1 + 3bf4: 0000 unimp + 3bf6: d000 sw s0,32(s0) + 3bf8: 0006 c.slli zero,0x1 + 3bfa: 0400 addi s0,sp,512 + 3bfc: 2780 .2byte 0x2780 + 3bfe: 0000 unimp + 3c00: 11c4 addi s1,sp,228 + 3c02: 0076 c.slli zero,0x1d + 3c04: 0000 unimp + 3c06: 0104 addi s1,sp,128 + 3c08: c4000027 .4byte 0xc4000027 + 3c0c: 4b24 lw s1,80(a4) + 3c0e: 0001 nop + 3c10: 0400 addi s0,sp,512 + 3c12: 280a .2byte 0x280a + 3c14: 0000 unimp + 3c16: 2ec4 .2byte 0x2ec4 + 3c18: 0076 c.slli zero,0x1d + 3c1a: 0000 unimp + 3c1c: e404 .2byte 0xe404 + 3c1e: 0024 addi s1,sp,8 + 3c20: c400 sw s0,8(s0) + 3c22: 7639 lui a2,0xfffee + 3c24: 0000 unimp + 3c26: 0000 unimp + 3c28: 00278603 lb a2,2(a5) + 3c2c: bf00 .2byte 0xbf00 + 3c2e: 7605 lui a2,0xfffe1 + ... + 3c38: 0000 unimp + 3c3a: 0100 addi s0,sp,128 + 3c3c: 139c addi a5,sp,480 + 3c3e: 05000007 .4byte 0x5000007 + 3c42: 2701 jal 4342 <__neorv32_ram_size+0x2342> + 3c44: 0000 unimp + 3c46: 014b17bf 13a70000 .8byte 0x13a70000014b17bf + 3c4e: 0000 unimp + 3c50: 00280a07 .4byte 0x280a07 + 3c54: bf00 .2byte 0xbf00 + 3c56: 7621 lui a2,0xfffe8 + 3c58: 0000 unimp + 3c5a: 0100 addi s0,sp,128 + 3c5c: 24e4075b .4byte 0x24e4075b + 3c60: 0000 unimp + 3c62: 00762cbf 5c010000 .8byte 0x5c01000000762cbf + 3c6a: 0d00 addi s0,sp,656 + 3c6c: 2826 .2byte 0x2826 + 3c6e: 0000 unimp + 3c70: 05b9 addi a1,a1,14 + 3c72: 0076 c.slli zero,0x1d + 3c74: 0000 unimp + 3c76: 0738 addi a4,sp,904 + 3c78: 0000 unimp + 3c7a: 3604 .2byte 0x3604 + 3c7c: b9000027 .4byte 0xb9000027 + 3c80: 4b18 lw a4,16(a4) + 3c82: 0001 nop + 3c84: 1c00 addi s0,sp,560 + 3c86: b9007473 csrrci s0,mhpmcounter16h,0 + 3c8a: 00060a2b .4byte 0x60a2b + 3c8e: 0000 unimp + 3c90: 0025f503 .4byte 0x25f503 + 3c94: b400 .2byte 0xb400 + 3c96: 0001eb07 .4byte 0x1eb07 + ... + 3ca2: 0100 addi s0,sp,128 + 3ca4: 7b9c .2byte 0x7b9c + 3ca6: 05000007 .4byte 0x5000007 + 3caa: 2736 .2byte 0x2736 + 3cac: 0000 unimp + 3cae: 12b4 addi a3,sp,360 + 3cb0: 0076 c.slli zero,0x1d + 3cb2: 0000 unimp + 3cb4: 13c1 addi t2,t2,-16 + 3cb6: 0000 unimp + 3cb8: 7009 c.lui zero,0xfffe2 + 3cba: 7274 .2byte 0x7274 + 3cbc: b400 .2byte 0xb400 + 3cbe: eb1e .2byte 0xeb1e + 3cc0: 0001 nop + 3cc2: 0100 addi s0,sp,128 + 3cc4: 6964095b .4byte 0x6964095b + 3cc8: 0072 c.slli zero,0x1c + 3cca: 27b4 .2byte 0x27b4 + 3ccc: 0076 c.slli zero,0x1d + 3cce: 0000 unimp + 3cd0: 5c01 li s8,-32 + 3cd2: 0300 addi s0,sp,384 + 3cd4: 2820 .2byte 0x2820 + 3cd6: 0000 unimp + 3cd8: 05ae slli a1,a1,0xb + 3cda: 0076 c.slli zero,0x1d + ... + 3ce4: 0000 unimp + 3ce6: 9c01 .2byte 0x9c01 + 3ce8: 07b1 addi a5,a5,12 + 3cea: 0000 unimp + 3cec: fd05 bnez a0,3c24 <__neorv32_ram_size+0x1c24> + 3cee: 0026 c.slli zero,0x9 + 3cf0: ae00 .2byte 0xae00 + 3cf2: 00014b17 auipc s6,0x14 + 3cf6: db00 sw s0,48(a4) + 3cf8: 07000013 li zero,112 + 3cfc: 27a4 .2byte 0x27a4 + 3cfe: 0000 unimp + 3d00: 2dae .2byte 0x2dae + 3d02: 0000014b .4byte 0x14b + 3d06: 5b01 li s6,-32 + 3d08: 0300 addi s0,sp,384 + 3d0a: 27ad jal 4474 <__neorv32_ram_size+0x2474> + 3d0c: 0000 unimp + 3d0e: 05a8 addi a0,sp,712 + 3d10: 0076 c.slli zero,0x1d + ... + 3d1a: 0000 unimp + 3d1c: 9c01 .2byte 0x9c01 + 3d1e: 000007e7 jalr a5,zero # 0 <__crt0_entry> + 3d22: 700a .2byte 0x700a + 3d24: 6469 lui s0,0x1a + 3d26: a800 .2byte 0xa800 + 3d28: 0000760f .4byte 0x760f + 3d2c: f500 .2byte 0xf500 + 3d2e: 09000013 li zero,144 + 3d32: 00676973 csrrsi s2,0x6,14 + 3d36: 18a8 addi a0,sp,120 + 3d38: 0076 c.slli zero,0x1d + 3d3a: 0000 unimp + 3d3c: 5b01 li s6,-32 + 3d3e: 0300 addi s0,sp,384 + 3d40: 2699 jal 4086 <__neorv32_ram_size+0x2086> + 3d42: 0000 unimp + 3d44: 007605a3 sb t2,11(a2) # fffe800b <__crt0_stack_begin+0x7ffe600f> + ... + 3d50: 0000 unimp + 3d52: 9c01 .2byte 0x9c01 + 3d54: 0810 addi a2,sp,16 + 3d56: 0000 unimp + 3d58: 3605 jal 3878 <__neorv32_ram_size+0x1878> + 3d5a: a3000027 .4byte 0xa3000027 + 3d5e: 7611 lui a2,0xfffe4 + 3d60: 0000 unimp + 3d62: 0f00 addi s0,sp,912 + 3d64: 0014 .2byte 0x14 + 3d66: 0000 unimp + 3d68: 0027cd03 lbu s10,2(a5) + 3d6c: 9d00 .2byte 0x9d00 + 3d6e: 7605 lui a2,0xfffe1 + ... + 3d78: 0000 unimp + 3d7a: 0100 addi s0,sp,128 + 3d7c: 459c lw a5,8(a1) + 3d7e: 0008 .2byte 0x8 + 3d80: 0a00 addi s0,sp,272 + 3d82: 7074 .2byte 0x7074 + 3d84: 9d00 .2byte 0x9d00 + 3d86: 00084523 .4byte 0x84523 + 3d8a: 3600 .2byte 0x3600 + 3d8c: 0014 .2byte 0x14 + 3d8e: 0900 addi s0,sp,144 + 3d90: 7a74 .2byte 0x7a74 + 3d92: 0070 addi a2,sp,12 + 3d94: 2d9d jal 440a <__neorv32_ram_size+0x240a> + 3d96: 0000011b .4byte 0x11b + 3d9a: 5b01 li s6,-32 + 3d9c: 0600 addi s0,sp,768 + 3d9e: 0168 addi a0,sp,140 + 3da0: 0000 unimp + 3da2: 0329 addi t1,t1,10 # 100a <_malloc_r+0x1ac> + 3da4: 0026 c.slli zero,0x9 + 3da6: 0100 addi s0,sp,128 + 3da8: 0598 addi a4,sp,704 + 3daa: 0076 c.slli zero,0x1d + ... + 3db4: 0000 unimp + 3db6: 9c01 .2byte 0x9c01 + 3db8: 00269103 lh sp,2(a3) + 3dbc: 9200 .2byte 0x9200 + 3dbe: 00013507 .4byte 0x13507 + ... + 3dca: 0100 addi s0,sp,128 + 3dcc: 969c .2byte 0x969c + 3dce: 0008 .2byte 0x8 + 3dd0: 0a00 addi s0,sp,272 + 3dd2: 7562 .2byte 0x7562 + 3dd4: 0066 c.slli zero,0x19 + 3dd6: 1592 slli a1,a1,0x24 + 3dd8: 0135 addi sp,sp,13 + 3dda: 0000 unimp + 3ddc: 1450 addi a2,sp,548 + 3dde: 0000 unimp + 3de0: 00192007 .4byte 0x192007 + 3de4: 9200 .2byte 0x9200 + 3de6: 9021 srli s0,s0,0x28 + 3de8: 0000 unimp + 3dea: 0100 addi s0,sp,128 + 3dec: 1b0d005b .4byte 0x1b0d005b + 3df0: 8c000027 .4byte 0x8c000027 + 3df4: 7605 lui a2,0xfffe1 + 3df6: 0000 unimp + 3df8: b000 .2byte 0xb000 + 3dfa: 0008 .2byte 0x8 + 3dfc: 1c00 addi s0,sp,560 + 3dfe: 7074 .2byte 0x7074 + 3e00: 8c00 .2byte 0x8c00 + 3e02: b01a .2byte 0xb01a + 3e04: 0008 .2byte 0x8 + 3e06: 0000 unimp + 3e08: 1206 slli tp,tp,0x21 + 3e0a: 03000003 lb zero,48(zero) # 30 + 3e0e: 255a .2byte 0x255a + 3e10: 0000 unimp + 3e12: 0586 slli a1,a1,0x1 + 3e14: 0076 c.slli zero,0x1d + ... + 3e1e: 0000 unimp + 3e20: 9c01 .2byte 0x9c01 + 3e22: 0904 addi s1,sp,144 + 3e24: 0000 unimp + 3e26: 8005 srli s0,s0,0x1 + 3e28: 86000027 .4byte 0x86000027 + 3e2c: 7612 .2byte 0x7612 + 3e2e: 0000 unimp + 3e30: 6a00 .2byte 0x6a00 + 3e32: 0014 .2byte 0x14 + 3e34: 0700 addi s0,sp,896 + 3e36: 2736 .2byte 0x2736 + 3e38: 0000 unimp + 3e3a: 2586 .2byte 0x2586 + 3e3c: 0000014b .4byte 0x14b + 3e40: 5b01 li s6,-32 + 3e42: 7309 lui t1,0xfffe2 + 3e44: 0074 addi a3,sp,12 + 3e46: 3886 .2byte 0x3886 + 3e48: 060a slli a2,a2,0x2 + 3e4a: 0000 unimp + 3e4c: 5c01 li s8,-32 + 3e4e: 00280a07 .4byte 0x280a07 + 3e52: 8600 .2byte 0x8600 + 3e54: 7640 .2byte 0x7640 + 3e56: 0000 unimp + 3e58: 0100 addi s0,sp,128 + 3e5a: 005d c.nop 23 + 3e5c: 0025fc03 .4byte 0x25fc03 + 3e60: 8000 .2byte 0x8000 + 3e62: 7605 lui a2,0xfffe1 + ... + 3e6c: 0000 unimp + 3e6e: 0100 addi s0,sp,128 + 3e70: 399c .2byte 0x399c + 3e72: 0009 c.nop 2 + 3e74: 0500 addi s0,sp,640 + 3e76: 2736 .2byte 0x2736 + 3e78: 0000 unimp + 3e7a: 1080 addi s0,sp,96 + 3e7c: 0076 c.slli zero,0x1d + 3e7e: 0000 unimp + 3e80: 1484 addi s1,sp,608 + 3e82: 0000 unimp + 3e84: 7309 lui t1,0xfffe2 + 3e86: 0074 addi a3,sp,12 + 3e88: 2380 .2byte 0x2380 + 3e8a: 060a slli a2,a2,0x2 + 3e8c: 0000 unimp + 3e8e: 5b01 li s6,-32 + 3e90: 2a00 .2byte 0x2a00 + 3e92: 26e5 jal 427a <__neorv32_ram_size+0x227a> + 3e94: 0000 unimp + 3e96: 7a01 lui s4,0xfffe0 + 3e98: 7605 lui a2,0xfffe1 + ... + 3ea2: 0000 unimp + 3ea4: 0100 addi s0,sp,128 + 3ea6: 0f9c addi a5,sp,976 + 3ea8: 25c6 .2byte 0x25c6 + 3eaa: 0000 unimp + 3eac: 7674 .2byte 0x7674 + 3eae: 0000 unimp + 3eb0: 8a00 .2byte 0x8a00 + 3eb2: 0009 c.nop 2 + 3eb4: 0400 addi s0,sp,512 + 3eb6: 2780 .2byte 0x2780 + 3eb8: 0000 unimp + 3eba: 1474 addi a3,sp,556 + 3ebc: 0076 c.slli zero,0x1d + 3ebe: 0000 unimp + 3ec0: 3604 .2byte 0x3604 + 3ec2: 74000027 .4byte 0x74000027 + 3ec6: 00014b27 .4byte 0x14b27 + 3eca: 0400 addi s0,sp,512 + 3ecc: 24e4 .2byte 0x24e4 + 3ece: 0000 unimp + 3ed0: 3174 .2byte 0x3174 + 3ed2: 0076 c.slli zero,0x1d + 3ed4: 0000 unimp + 3ed6: 0a04 addi s1,sp,272 + 3ed8: 0028 addi a0,sp,8 + 3eda: 7400 .2byte 0x7400 + 3edc: 0000763b .4byte 0x763b + 3ee0: 0000 unimp + 3ee2: 0026702b .4byte 0x26702b + 3ee6: 0d00 addi s0,sp,656 + 3ee8: 0612 slli a2,a2,0x4 + ... + 3ef2: 9c01 .2byte 0x9c01 + 3ef4: 09ae slli s3,s3,0xb + 3ef6: 0000 unimp + 3ef8: 00272a07 .4byte 0x272a07 + 3efc: 6b00 .2byte 0x6b00 + 3efe: 7610 .2byte 0x7610 + 3f00: 0000 unimp + 3f02: 0100 addi s0,sp,128 + 3f04: 005a c.slli zero,0x16 + 3f06: 00272203 lw tp,2(a4) + 3f0a: 6500 .2byte 0x6500 + 3f0c: 7605 lui a2,0xfffe1 + ... + 3f16: 0000 unimp + 3f18: 0100 addi s0,sp,128 + 3f1a: f19c .2byte 0xf19c + 3f1c: 0009 c.nop 2 + 3f1e: 0500 addi s0,sp,640 + 3f20: 2701 jal 4620 <__neorv32_ram_size+0x2620> + 3f22: 0000 unimp + 3f24: 1965 addi s2,s2,-7 # ff9 <_malloc_r+0x19b> + 3f26: 0000014b .4byte 0x14b + 3f2a: 149e slli s1,s1,0x27 + 3f2c: 0000 unimp + 3f2e: 0027db07 .4byte 0x27db07 + 3f32: 6500 .2byte 0x6500 + 3f34: 0009f12b .4byte 0x9f12b + 3f38: 0100 addi s0,sp,128 + 3f3a: 6e65095b .4byte 0x6e65095b + 3f3e: 0076 c.slli zero,0x1d + 3f40: 3f65 jal 3ef8 <__neorv32_ram_size+0x1ef8> + 3f42: 09f1 addi s3,s3,28 + 3f44: 0000 unimp + 3f46: 5c01 li s8,-32 + 3f48: 0600 addi s0,sp,768 + 3f4a: 013a slli sp,sp,0xe + 3f4c: 0000 unimp + 3f4e: 0026530f .4byte 0x26530f + 3f52: 6000 .2byte 0x6000 + 3f54: 0076 c.slli zero,0x1d + 3f56: 0000 unimp + 3f58: 0a10 addi a2,sp,272 + 3f5a: 0000 unimp + 3f5c: 3604 .2byte 0x3604 + 3f5e: 60000027 .4byte 0x60000027 + 3f62: 7610 .2byte 0x7610 + 3f64: 0000 unimp + 3f66: 0000 unimp + 3f68: 00264c03 lbu s8,2(a2) # fffe1002 <__crt0_stack_begin+0x7ffdf006> + 3f6c: 5a00 lw s0,48(a2) + 3f6e: 7605 lui a2,0xfffe1 + ... + 3f78: 0000 unimp + 3f7a: 0100 addi s0,sp,128 + 3f7c: 539c lw a5,32(a5) + 3f7e: 000a c.slli zero,0x2 + 3f80: 0500 addi s0,sp,640 + 3f82: 2581 jal 45c2 <__neorv32_ram_size+0x25c2> + 3f84: 0000 unimp + 3f86: 185a slli a6,a6,0x36 + 3f88: 0000014b .4byte 0x14b + 3f8c: 14b8 addi a4,sp,616 + 3f8e: 0000 unimp + 3f90: 00277207 .4byte 0x277207 + 3f94: 5a00 lw s0,48(a2) + 3f96: 0324 addi s1,sp,392 + 3f98: 0002 c.slli64 zero + 3f9a: 0100 addi s0,sp,128 + 3f9c: 25d1075b .4byte 0x25d1075b + 3fa0: 0000 unimp + 3fa2: 315a .2byte 0x315a + 3fa4: 0000020f .4byte 0x20f + 3fa8: 5c01 li s8,-32 + 3faa: 0300 addi s0,sp,384 + 3fac: 0000270b .4byte 0x270b + 3fb0: 0554 addi a3,sp,644 + 3fb2: 0076 c.slli zero,0x1d + ... + 3fbc: 0000 unimp + 3fbe: 9c01 .2byte 0x9c01 + 3fc0: 0a89 addi s5,s5,2 + 3fc2: 0000 unimp + 3fc4: 8105 srli a0,a0,0x1 + 3fc6: 0025 c.nop 9 + 3fc8: 5400 lw s0,40(s0) + 3fca: 4b18 lw a4,16(a4) + 3fcc: 0001 nop + 3fce: d200 sw s0,32(a2) + 3fd0: 0014 .2byte 0x14 + 3fd2: 0700 addi s0,sp,896 + 3fd4: 24e4 .2byte 0x24e4 + 3fd6: 0000 unimp + 3fd8: 2554 .2byte 0x2554 + 3fda: 00000227 .4byte 0x227 + 3fde: 5b01 li s6,-32 + 3fe0: 0f00 addi s0,sp,912 + 3fe2: 26c1 jal 43a2 <__neorv32_ram_size+0x23a2> + 3fe4: 0000 unimp + 3fe6: 764e .2byte 0x764e + 3fe8: 0000 unimp + 3fea: a300 .2byte 0xa300 + 3fec: 000a c.slli zero,0x2 + 3fee: 0400 addi s0,sp,512 + 3ff0: 2581 jal 4630 <__neorv32_ram_size+0x2630> + 3ff2: 0000 unimp + 3ff4: 184e slli a6,a6,0x33 + 3ff6: 0000014b .4byte 0x14b + 3ffa: 0300 addi s0,sp,384 + 3ffc: 27ba .2byte 0x27ba + 3ffe: 0000 unimp + 4000: 0548 addi a0,sp,644 + 4002: 0076 c.slli zero,0x1d + ... + 400c: 0000 unimp + 400e: 9c01 .2byte 0x9c01 + 4010: 0ad9 addi s5,s5,22 + 4012: 0000 unimp + 4014: 3605 jal 3b34 <__neorv32_ram_size+0x1b34> + 4016: 48000027 .4byte 0x48000027 + 401a: 4b19 li s6,6 + 401c: 0001 nop + 401e: ec00 .2byte 0xec00 + 4020: 0014 .2byte 0x14 + 4022: 0700 addi s0,sp,896 + 4024: 24e4 .2byte 0x24e4 + 4026: 0000 unimp + 4028: 2348 .2byte 0x2348 + 402a: 0076 c.slli zero,0x1d + 402c: 0000 unimp + 402e: 5b01 li s6,-32 + 4030: 0f00 addi s0,sp,912 + 4032: 2586 .2byte 0x2586 + 4034: 0000 unimp + 4036: 7642 .2byte 0x7642 + 4038: 0000 unimp + 403a: fe00 .2byte 0xfe00 + 403c: 000a c.slli zero,0x2 + 403e: 0400 addi s0,sp,512 + 4040: 0000261b .4byte 0x261b + 4044: 2642 .2byte 0x2642 + 4046: 0afe slli s5,s5,0x1f + 4048: 0000 unimp + 404a: 4504 lw s1,8(a0) + 404c: 0025 c.nop 9 + 404e: 4200 lw s0,0(a2) + 4050: 033d addi t1,t1,15 # fffe200f <__crt0_stack_begin+0x7ffe0013> + 4052: 0000000b .4byte 0xb + 4056: b606 .2byte 0xb606 + 4058: 0001 nop + 405a: 0600 addi s0,sp,768 + 405c: 0000018f .4byte 0x18f + 4060: 6b2c .2byte 0x6b2c + 4062: 0025 c.nop 9 + 4064: 0100 addi s0,sp,128 + 4066: 0000063b .4byte 0x63b + 406a: 0000 unimp + 406c: 0000 unimp + 406e: 0000 unimp + 4070: 9c01 .2byte 0x9c01 + 4072: 00000b3b .4byte 0xb3b + 4076: 000c .2byte 0xc + 4078: 0000 unimp + 407a: 3100 .2byte 0x3100 + 407c: 0004 .2byte 0x4 + 407e: 2d00 .2byte 0x2d00 + 4080: 0000 unimp + 4082: 0000 unimp + 4084: 0421 addi s0,s0,8 # 1a008 <__neorv32_ram_size+0x18008> + 4086: 0000 unimp + 4088: 012e slli sp,sp,0xb + 408a: 055a slli a0,a0,0x16 + 408c: 00000003 lb zero,0(zero) # 0 <__crt0_entry> + 4090: 0000 unimp + 4092: 1400 addi s0,sp,544 + 4094: 0ad9 addi s5,s5,22 + ... + 409e: 0000 unimp + 40a0: 9c01 .2byte 0x9c01 + 40a2: 0b5f 0000 e710 .byte 0x5f, 0x0b, 0x00, 0x00, 0x10, 0xe7 + 40a8: 000a c.slli zero,0x2 + 40aa: 0600 addi s0,sp,768 + 40ac: 0015 c.nop 5 + 40ae: 1100 addi s0,sp,160 + 40b0: 0af2 slli s5,s5,0x1c + 40b2: 0000 unimp + 40b4: 5b01 li s6,-32 + 40b6: 1400 addi s0,sp,544 + 40b8: 0a89 addi s5,s5,2 + ... + 40c2: 0000 unimp + 40c4: 9c01 .2byte 0x9c01 + 40c6: 0b7c addi a5,sp,412 + 40c8: 0000 unimp + 40ca: 9710 .2byte 0x9710 + 40cc: 000a c.slli zero,0x2 + 40ce: 2000 .2byte 0x2000 + 40d0: 0015 c.nop 5 + 40d2: 0000 unimp + 40d4: f614 .2byte 0xf614 + 40d6: 0009 c.nop 2 + ... + 40e0: 0100 addi s0,sp,128 + 40e2: 999c .2byte 0x999c + 40e4: 1000000b .4byte 0x1000000b + 40e8: 0a04 addi s1,sp,272 + 40ea: 0000 unimp + 40ec: 153a slli a0,a0,0x2e + 40ee: 0000 unimp + 40f0: 2f00 .2byte 0x2f00 + 40f2: 0000094f .4byte 0x94f + ... + 40fe: 9c01 .2byte 0x9c01 + 4100: 5d10 lw a2,56(a0) + 4102: 0009 c.nop 2 + 4104: 5400 lw s0,40(s0) + 4106: 0015 c.nop 5 + 4108: 1100 addi s0,sp,160 + 410a: 0968 addi a0,sp,156 + 410c: 0000 unimp + 410e: 5b01 li s6,-32 + 4110: 7311 lui t1,0xfffe4 + 4112: 0009 c.nop 2 + 4114: 0100 addi s0,sp,128 + 4116: 115c addi a5,sp,164 + 4118: 097e slli s2,s2,0x1f + 411a: 0000 unimp + 411c: 5d01 li s10,-32 + 411e: 0000 unimp + 4120: 0021 c.nop 8 + 4122: 0000 unimp + 4124: 0005 c.nop 1 + 4126: 0401 addi s0,s0,0 + 4128: 0e82 c.slli64 t4 + 412a: 0000 unimp + 412c: 8401 c.srai64 s0 + 412e: 0000003f 90000000 .8byte 0x900000000000003f + 4136: 00283803 .4byte 0x283803 + 413a: 3f00 .2byte 0x3f00 + 413c: 0028 addi a0,sp,8 + 413e: 8200 .2byte 0x8200 + 4140: 0028 addi a0,sp,8 + 4142: 0100 addi s0,sp,128 + 4144: 5380 lw s0,32(a5) + 4146: 0000 unimp + 4148: 0500 addi s0,sp,640 + 414a: 0100 addi s0,sp,128 + 414c: 9604 .2byte 0x9604 + 414e: 000e c.slli zero,0x3 + 4150: 0100 addi s0,sp,128 + 4152: 41ce lw gp,208(sp) + 4154: 0000 unimp + 4156: 0dd4 addi a3,sp,724 + 4158: 0000 unimp + 415a: 8e7e mv t3,t6 + 415c: 0028 addi a0,sp,8 + 415e: cb00 sw s0,16(a4) + 4160: 0028 addi a0,sp,8 + 4162: 8200 .2byte 0x8200 + 4164: 0028 addi a0,sp,8 + 4166: 0100 addi s0,sp,128 + 4168: 0280 addi s0,sp,320 + 416a: 291d jal 45a0 <__neorv32_ram_size+0x25a0> + 416c: 0000 unimp + 416e: 0dd4 addi a3,sp,724 + 4170: 0000 unimp + 4172: 0258 addi a4,sp,260 + 4174: 0000292f .4byte 0x292f + 4178: 0ddc addi a5,sp,724 + 417a: 0000 unimp + 417c: 022c addi a1,sp,264 + 417e: 2926 .2byte 0x2926 + 4180: 0000 unimp + 4182: 0ddc addi a5,sp,724 + 4184: 0000 unimp + 4186: 022c addi a1,sp,264 + 4188: 1f84 addi s1,sp,1008 + 418a: 0000 unimp + 418c: 0e08 addi a0,sp,784 + 418e: 0000 unimp + 4190: 0208 addi a0,sp,256 + 4192: 2939 jal 45b0 <__neorv32_ram_size+0x25b0> + 4194: 0000 unimp + 4196: 0e2c addi a1,sp,792 + 4198: 0000 unimp + 419a: 0024 addi s1,sp,8 + +Disassembly of section .debug_abbrev: + +00000000 <.debug_abbrev>: + 0: 4901 li s2,0 + 2: 0200 addi s0,sp,256 + 4: 7e18 .2byte 0x7e18 + 6: 0018 .2byte 0x18 + 8: 0200 addi s0,sp,256 + a: 0024 addi s1,sp,8 + c: 0b3e0b0b .4byte 0xb3e0b0b + 10: 00000e03 lb t3,0(zero) # 0 <__crt0_entry> + 14: 03001603 lh a2,48(zero) # 30 + 18: 3a0e .2byte 0x3a0e + 1a: 390b3b0b .4byte 0x390b3b0b + 1e: 0013490b .4byte 0x13490b + 22: 0400 addi s0,sp,512 + 24: 0028 addi a0,sp,8 + 26: 0b1c0e03 lb t3,177(s8) + 2a: 0000 unimp + 2c: 0505 addi a0,a0,1 + 2e: 4900 lw s0,16(a0) + 30: 06000013 li zero,96 + 34: 000d c.nop 3 + 36: 213a0e03 lb t3,531(s4) # fffe0213 <__crt0_stack_begin+0x7ffde217> + 3a: 3b05 jal fffffd6a <__crt0_stack_begin+0x7fffdd6e> + 3c: 3905 jal fffffc6c <__crt0_stack_begin+0x7fffdc70> + 3e: 1221 addi tp,tp,-24 # 8fe8 <__neorv32_ram_size+0x6fe8> + 40: 1349 addi t1,t1,-14 # fffe3ff2 <__crt0_stack_begin+0x7ffe1ff6> + 42: 0b38 addi a4,sp,408 + 44: 0000 unimp + 46: 7d014807 .4byte 0x7d014807 + 4a: 7f01 lui t5,0xfffe0 + 4c: 00130113 addi sp,t1,1 + 50: 0800 addi s0,sp,16 + 52: 0034 addi a3,sp,8 + 54: 213a0e03 lb t3,531(s4) + 58: 3b01 jal fffffd68 <__crt0_stack_begin+0x7fffdd6c> + 5a: 490b390b .4byte 0x490b390b + 5e: 00170213 addi tp,a4,1 + 62: 0900 addi s0,sp,144 + 64: 0034 addi a3,sp,8 + 66: 213a0803 lb a6,531(s4) + 6a: 3b01 jal fffffd7a <__crt0_stack_begin+0x7fffdd7e> + 6c: 490b390b .4byte 0x490b390b + 70: 00170213 addi tp,a4,1 + 74: 0a00 addi s0,sp,272 + 76: 0048 addi a0,sp,4 + 78: 017d addi sp,sp,31 + 7a: 137f .2byte 0x137f + 7c: 0000 unimp + 7e: 3f012e0b .4byte 0x3f012e0b + 82: 0319 addi t1,t1,6 + 84: 3a0e .2byte 0x3a0e + 86: 0621 addi a2,a2,8 # fffe1008 <__crt0_stack_begin+0x7ffdf00c> + 88: 21390b3b .4byte 0x21390b3b + 8c: 2706 .2byte 0x2706 + 8e: 3c19 jal fffffaa4 <__crt0_stack_begin+0x7fffdaa8> + 90: 0119 addi sp,sp,6 + 92: 0c000013 li zero,192 + 96: 0148 addi a0,sp,132 + 98: 017d addi sp,sp,31 + 9a: 137f .2byte 0x137f + 9c: 0000 unimp + 9e: 260d jal 3c0 <__neorv32_rte_core+0x114> + a0: 4900 lw s0,16(a0) + a2: 0e000013 li zero,224 + a6: 210b000f .4byte 0x210b000f + aa: 4904 lw s1,16(a0) + ac: 0f000013 li zero,240 + b0: 0104 addi s1,sp,128 + b2: 213e0e03 lb t3,531(t3) # 19213 <__neorv32_ram_size+0x17213> + b6: 04210b07 .4byte 0x4210b07 + ba: 1349 addi t1,t1,-14 + bc: 213a .2byte 0x213a + be: 3b05 jal fffffdee <__crt0_stack_begin+0x7fffddf2> + c0: 3905 jal fffffcf0 <__crt0_stack_begin+0x7fffdcf4> + c2: 0621 addi a2,a2,8 + c4: 1301 addi t1,t1,-32 + c6: 0000 unimp + c8: 0d10 addi a2,sp,656 + ca: 0300 addi s0,sp,384 + cc: 3a08 .2byte 0x3a08 + ce: 0521 addi a0,a0,8 + d0: 2139053b .4byte 0x2139053b + d4: 4912 lw s2,4(sp) + d6: 000b3813 sltiu a6,s6,0 + da: 1100 addi s0,sp,160 + dc: 012e slli sp,sp,0xb + de: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + e6: 0b39 addi s6,s6,14 # 17d00 <__neorv32_ram_size+0x15d00> + e8: 13491927 .4byte 0x13491927 + ec: 193c addi a5,sp,184 + ee: 1301 addi t1,t1,-32 + f0: 0000 unimp + f2: 0b12 slli s6,s6,0x4 + f4: 5501 li a0,-32 + f6: 00130117 auipc sp,0x130 + fa: 1300 addi s0,sp,416 + fc: 0005 c.nop 1 + fe: 213a0803 lb a6,531(s4) + 102: 3b01 jal fffffe12 <__crt0_stack_begin+0x7fffde16> + 104: 3521 jal ffffff0c <__crt0_stack_begin+0x7fffdf10> + 106: 0b39 addi s6,s6,14 + 108: 1349 addi t1,t1,-14 + 10a: 1802 slli a6,a6,0x20 + 10c: 0000 unimp + 10e: 1114 addi a3,sp,160 + 110: 2501 jal 710 <__neorv32_rte_debug_handler+0x1ac> + 112: 130e slli t1,t1,0x23 + 114: 1b1f030b .4byte 0x1b1f030b + 118: 551f 1117 1001 .byte 0x1f, 0x55, 0x17, 0x11, 0x01, 0x10 + 11e: 15000017 auipc zero,0x15000 + 122: 0024 addi s1,sp,8 + 124: 0b3e0b0b .4byte 0xb3e0b0b + 128: 00000803 lb a6,0(zero) # 0 <__crt0_entry> + 12c: 0f16 slli t5,t5,0x5 + 12e: 0b00 addi s0,sp,400 + 130: 1700000b .4byte 0x1700000b + 134: 0b0b0113 addi sp,s6,176 + 138: 0188 addi a0,sp,192 + 13a: 3b0b3a0b .4byte 0x3b0b3a0b + 13e: 3905 jal fffffd6e <__crt0_stack_begin+0x7fffdd72> + 140: 0013010b .4byte 0x13010b + 144: 1800 addi s0,sp,48 + 146: 0016 c.slli zero,0x5 + 148: 0b3a0e03 lb t3,179(s4) + 14c: 0b39053b .4byte 0xb39053b + 150: 1349 addi t1,t1,-14 + 152: 0188 addi a0,sp,192 + 154: 1900000b .4byte 0x1900000b + 158: 002e c.slli zero,0xb + 15a: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 162: 0b39 addi s6,s6,14 + 164: 13491927 .4byte 0x13491927 + 168: 193c addi a5,sp,184 + 16a: 0000 unimp + 16c: 181a slli a6,a6,0x26 + 16e: 0000 unimp + 170: 1b00 addi s0,sp,432 + 172: 002e c.slli zero,0xb + 174: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 17c: 0b39 addi s6,s6,14 + 17e: 193c1927 .4byte 0x193c1927 + 182: 0000 unimp + 184: 2e1c .2byte 0x2e1c + 186: 3f01 jal 96 <__crt0_copy_data+0x1a> + 188: 0319 addi t1,t1,6 + 18a: 3a0e .2byte 0x3a0e + 18c: 390b3b0b .4byte 0x390b3b0b + 190: 1113490b .4byte 0x1113490b + 194: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + 196: 4006 .2byte 0x4006 + 198: 7a18 .2byte 0x7a18 + 19a: 0119 addi sp,sp,6 # 1300fc <__neorv32_ram_size+0x12e0fc> + 19c: 1d000013 li zero,464 + 1a0: 012e slli sp,sp,0xb + 1a2: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 1aa: 0b39 addi s6,s6,14 + 1ac: 01111927 .4byte 0x1111927 + 1b0: 0612 slli a2,a2,0x4 + 1b2: 1840 addi s0,sp,52 + 1b4: 197a slli s2,s2,0x3e + 1b6: 1301 addi t1,t1,-32 + 1b8: 0000 unimp + 1ba: 0b1e slli s6,s6,0x7 + 1bc: 5501 li a0,-32 + 1be: 1f000017 auipc zero,0x1f000 + 1c2: 002e c.slli zero,0xb + 1c4: 193c193f 0e030e6e .8byte 0xe030e6e193c193f + 1cc: 0000 unimp + 1ce: 0100 addi s0,sp,128 + 1d0: 0028 addi a0,sp,8 + 1d2: 0b1c0e03 lb t3,177(s8) + 1d6: 0000 unimp + 1d8: 2402 .2byte 0x2402 + 1da: 0b00 addi s0,sp,400 + 1dc: 030b3e0b .4byte 0x30b3e0b + 1e0: 000e c.slli zero,0x3 + 1e2: 0300 addi s0,sp,384 + 1e4: 000d c.nop 3 + 1e6: 213a0e03 lb t3,531(s4) + 1ea: 3b04 .2byte 0x3b04 + 1ec: 3905 jal fffffe1c <__crt0_stack_begin+0x7fffde20> + 1ee: 3813490b .4byte 0x3813490b + 1f2: 0400000b .4byte 0x400000b + 1f6: 000d c.nop 3 + 1f8: 213a0e03 lb t3,531(s4) + 1fc: 3b01 jal ffffff0c <__crt0_stack_begin+0x7fffdf10> + 1fe: 0e21390b .4byte 0xe21390b + 202: 1349 addi t1,t1,-14 + 204: 0000 unimp + 206: 1605 addi a2,a2,-31 + 208: 0300 addi s0,sp,384 + 20a: 3a0e .2byte 0x3a0e + 20c: 390b3b0b .4byte 0x390b3b0b + 210: 0013490b .4byte 0x13490b + 214: 0600 addi s0,sp,768 + 216: 210b0117 auipc sp,0x210b0 + 21a: 3a08 .2byte 0x3a08 + 21c: 0121 addi sp,sp,8 # 210b021e <__neorv32_ram_size+0x210ae21e> + 21e: 21390b3b .4byte 0x21390b3b + 222: 00130103 lb sp,1(t1) + 226: 0700 addi s0,sp,896 + 228: 0034 addi a3,sp,8 + 22a: 213a0e03 lb t3,531(s4) + 22e: 3b01 jal ffffff3e <__crt0_stack_begin+0x7fffdf42> + 230: 0521390b .4byte 0x521390b + 234: 1349 addi t1,t1,-14 + 236: 0000 unimp + 238: 3408 .2byte 0x3408 + 23a: 0300 addi s0,sp,384 + 23c: 3a0e .2byte 0x3a0e + 23e: 0121 addi sp,sp,8 + 240: 00e5213b .4byte 0xe5213b + 244: 0b39 addi s6,s6,14 + 246: 1349 addi t1,t1,-14 + 248: 1802 slli a6,a6,0x20 + 24a: 0000 unimp + 24c: 1309 addi t1,t1,-30 + 24e: 0b01 addi s6,s6,0 + 250: 2101880b .4byte 0x2101880b + 254: 3a04 .2byte 0x3a04 + 256: 0421 addi s0,s0,8 + 258: 2139053b .4byte 0x2139053b + 25c: 0109 addi sp,sp,2 + 25e: 0a000013 li zero,160 + 262: 0016 c.slli zero,0x5 + 264: 213a0e03 lb t3,531(s4) + 268: 3b04 .2byte 0x3b04 + 26a: 3905 jal fffffe9a <__crt0_stack_begin+0x7fffde9e> + 26c: 0321 addi t1,t1,8 + 26e: 1349 addi t1,t1,-14 + 270: 0188 addi a0,sp,192 + 272: 0421 addi s0,s0,8 + 274: 0000 unimp + 276: 03000d0b .4byte 0x3000d0b + 27a: 3a08 .2byte 0x3a08 + 27c: 0421 addi s0,s0,8 + 27e: 2139053b .4byte 0x2139053b + 282: 4912 lw s2,4(sp) + 284: 000b3813 sltiu a6,s6,0 + 288: 0c00 addi s0,sp,528 + 28a: 012e slli sp,sp,0xb + 28c: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 294: 0a21390b .4byte 0xa21390b + 298: 13491927 .4byte 0x13491927 + 29c: 0111 addi sp,sp,4 + 29e: 0612 slli a2,a2,0x4 + 2a0: 1840 addi s0,sp,52 + 2a2: 197a slli s2,s2,0x3e + 2a4: 1301 addi t1,t1,-32 + 2a6: 0000 unimp + 2a8: 2e0d jal 5da <__neorv32_rte_debug_handler+0x76> + 2aa: 3f01 jal 1ba + 2ac: 0319 addi t1,t1,6 + 2ae: 3a0e .2byte 0x3a0e + 2b0: 0121 addi sp,sp,8 + 2b2: 21390b3b .4byte 0x21390b3b + 2b6: 2706 .2byte 0x2706 + 2b8: 1119 addi sp,sp,-26 + 2ba: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + 2bc: 4006 .2byte 0x4006 + 2be: 7a18 .2byte 0x7a18 + 2c0: 0119 addi sp,sp,6 + 2c2: 0e000013 li zero,224 + 2c6: 0005 c.nop 1 + 2c8: 213a0e03 lb t3,531(s4) + 2cc: 3b01 jal ffffffdc <__crt0_stack_begin+0x7fffdfe0> + 2ce: 490b390b .4byte 0x490b390b + 2d2: 00180213 addi tp,a6,1 + 2d6: 0f00 addi s0,sp,912 + 2d8: 0111 addi sp,sp,4 + 2da: 0e25 addi t3,t3,9 + 2dc: 1f030b13 addi s6,t1,496 + 2e0: 17551f1b .4byte 0x17551f1b + 2e4: 0111 addi sp,sp,4 + 2e6: 1710 addi a2,sp,928 + 2e8: 0000 unimp + 2ea: 2410 .2byte 0x2410 + 2ec: 0b00 addi s0,sp,400 + 2ee: 030b3e0b .4byte 0x30b3e0b + 2f2: 0008 .2byte 0x8 + 2f4: 1100 addi s0,sp,160 + 2f6: 0026 c.slli zero,0x9 + 2f8: 1349 addi t1,t1,-14 + 2fa: 0000 unimp + 2fc: 0412 slli s0,s0,0x4 + 2fe: 0301 addi t1,t1,0 + 300: 3e0e .2byte 0x3e0e + 302: 490b0b0b .4byte 0x490b0b0b + 306: 3b0b3a13 sltiu s4,s6,944 + 30a: 3905 jal ffffff3a <__crt0_stack_begin+0x7fffdf3e> + 30c: 0013010b .4byte 0x13010b + 310: 1300 addi s0,sp,416 + 312: 0101 addi sp,sp,0 + 314: 1349 addi t1,t1,-14 + 316: 1301 addi t1,t1,-32 + 318: 0000 unimp + 31a: 2114 .2byte 0x2114 + 31c: 4900 lw s0,16(a0) + 31e: 000b2f13 slti t5,s6,0 + 322: 1500 addi s0,sp,672 + 324: 002e c.slli zero,0xb + 326: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 32e: 0b39 addi s6,s6,14 + 330: 13491927 .4byte 0x13491927 + 334: 0111 addi sp,sp,4 + 336: 0612 slli a2,a2,0x4 + 338: 1840 addi s0,sp,52 + 33a: 197a slli s2,s2,0x3e + 33c: 0000 unimp + 33e: 0100 addi s0,sp,128 + 340: 0028 addi a0,sp,8 + 342: 051c0e03 lb t3,81(s8) + 346: 0000 unimp + 348: 2802 .2byte 0x2802 + 34a: 0300 addi s0,sp,384 + 34c: 1c0e slli s8,s8,0x23 + 34e: 0300000b .4byte 0x300000b + 352: 0049 c.nop 18 + 354: 1802 slli a6,a6,0x20 + 356: 187e slli a6,a6,0x3f + 358: 0000 unimp + 35a: 4804 lw s1,16(s0) + 35c: 7d01 lui s10,0xfffe0 + 35e: 7f01 lui t5,0xfffe0 + 360: 00130113 addi sp,t1,1 + 364: 0500 addi s0,sp,640 + 366: 0048 addi a0,sp,4 + 368: 017d addi sp,sp,31 + 36a: 137f .2byte 0x137f + 36c: 0000 unimp + 36e: 0506 slli a0,a0,0x1 + 370: 3100 .2byte 0x3100 + 372: 00170213 addi tp,a4,1 + 376: 0700 addi s0,sp,896 + 378: 0034 addi a3,sp,8 + 37a: 1331 addi t1,t1,-20 + 37c: 0000 unimp + 37e: 2808 .2byte 0x2808 + 380: 0300 addi s0,sp,384 + 382: 1c0e slli s8,s8,0x23 + 384: 0006 c.slli zero,0x1 + 386: 0900 addi s0,sp,144 + 388: 011d addi sp,sp,7 + 38a: 1331 addi t1,t1,-20 + 38c: 0111 addi sp,sp,4 + 38e: 0612 slli a2,a2,0x4 + 390: 2158 .2byte 0x2158 + 392: 5901 li s2,-32 + 394: 5705 li a4,-31 + 396: 0013010b .4byte 0x13010b + 39a: 0a00 addi s0,sp,272 + 39c: 0024 addi s1,sp,8 + 39e: 0b3e0b0b .4byte 0xb3e0b0b + 3a2: 00000e03 lb t3,0(zero) # 0 <__crt0_entry> + 3a6: 0300160b .4byte 0x300160b + 3aa: 3a0e .2byte 0x3a0e + 3ac: 390b3b0b .4byte 0x390b3b0b + 3b0: 0013490b .4byte 0x13490b + 3b4: 0c00 addi s0,sp,528 + 3b6: 0034 addi a3,sp,8 + 3b8: 1331 addi t1,t1,-20 + 3ba: 1702 slli a4,a4,0x20 + 3bc: 0000 unimp + 3be: 0d0d addi s10,s10,3 # fffe0003 <__crt0_stack_begin+0x7ffde007> + 3c0: 0300 addi s0,sp,384 + 3c2: 3a0e .2byte 0x3a0e + 3c4: 0521 addi a0,a0,8 + 3c6: 2139053b .4byte 0x2139053b + 3ca: 4912 lw s2,4(sp) + 3cc: 000b3813 sltiu a6,s6,0 + 3d0: 0e00 addi s0,sp,784 + 3d2: 0034 addi a3,sp,8 + 3d4: 213a0e03 lb t3,531(s4) + 3d8: 3b01 jal e8 <__crt0_call_constructors_loop+0xc> + 3da: 3905 jal a + 3dc: 0213490b .4byte 0x213490b + 3e0: 0f000017 auipc zero,0xf000 + 3e4: 0034 addi a3,sp,8 + 3e6: 213a0803 lb a6,531(s4) + 3ea: 3b01 jal fa <__crt0_call_constructors_loop_end+0xa> + 3ec: 3905 jal 1c + 3ee: 0213490b .4byte 0x213490b + 3f2: 10000017 auipc zero,0x10000 + 3f6: 0104 addi s1,sp,128 + 3f8: 213e0e03 lb t3,531(t3) + 3fc: 04210b07 .4byte 0x4210b07 + 400: 1349 addi t1,t1,-14 + 402: 213a .2byte 0x213a + 404: 3b05 jal 134 <__crt0_main_aftermath_end> + 406: 3905 jal 36 + 408: 0013010b .4byte 0x13010b + 40c: 1100 addi s0,sp,160 + 40e: 0148 addi a0,sp,132 + 410: 017d addi sp,sp,31 + 412: 137f .2byte 0x137f + 414: 0000 unimp + 416: 3412 .2byte 0x3412 + 418: 0300 addi s0,sp,384 + 41a: 3a0e .2byte 0x3a0e + 41c: 390b3b0b .4byte 0x390b3b0b + 420: 0013490b .4byte 0x13490b + 424: 1300 addi s0,sp,416 + 426: 0034 addi a3,sp,8 + 428: 213a0e03 lb t3,531(s4) + 42c: 3b01 jal 13c <__crt0_trap_handler> + 42e: 3905 jal 5e + 430: 0013490b .4byte 0x13490b + 434: 1400 addi s0,sp,544 + 436: 011d addi sp,sp,7 + 438: 1331 addi t1,t1,-20 + 43a: 0111 addi sp,sp,4 + 43c: 0612 slli a2,a2,0x4 + 43e: 2158 .2byte 0x2158 + 440: 5901 li s2,-32 + 442: 010b570b .4byte 0x10b570b + 446: 15000013 li zero,336 + 44a: 1755010b .4byte 0x1755010b + 44e: 0000 unimp + 450: 2616 .2byte 0x2616 + 452: 4900 lw s0,16(a0) + 454: 17000013 li zero,368 + 458: 002e c.slli zero,0xb + 45a: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 462: 0b39 addi s6,s6,14 + 464: 13491927 .4byte 0x13491927 + 468: 193c addi a5,sp,184 + 46a: 0000 unimp + 46c: 3418 .2byte 0x3418 + 46e: 0300 addi s0,sp,384 + 470: 3a08 .2byte 0x3a08 + 472: 0121 addi sp,sp,8 + 474: 0b39053b .4byte 0xb39053b + 478: 1349 addi t1,t1,-14 + 47a: 0000 unimp + 47c: 2119 jal 882 + 47e: 4900 lw s0,16(a0) + 480: 000b2f13 slti t5,s6,0 + 484: 1a00 addi s0,sp,304 + 486: 012e slli sp,sp,0xb + 488: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 490: 3905 jal c0 <__crt0_clear_bss_loop+0x4> + 492: 0621 addi a2,a2,8 + 494: 01111927 .4byte 0x1111927 + 498: 0612 slli a2,a2,0x4 + 49a: 1840 addi s0,sp,52 + 49c: 197a slli s2,s2,0x3e + 49e: 1301 addi t1,t1,-32 + 4a0: 0000 unimp + 4a2: 7d01481b .4byte 0x7d01481b + 4a6: 8201 c.srli64 a2 + 4a8: 1901 addi s2,s2,-32 + 4aa: 137f .2byte 0x137f + 4ac: 0000 unimp + 4ae: 341c .2byte 0x341c + 4b0: 0300 addi s0,sp,384 + 4b2: 3a0e .2byte 0x3a0e + 4b4: 0121 addi sp,sp,8 + 4b6: 0b390b3b .4byte 0xb390b3b + 4ba: 1349 addi t1,t1,-14 + 4bc: 1702 slli a4,a4,0x20 + 4be: 0000 unimp + 4c0: 051d addi a0,a0,7 + 4c2: 0300 addi s0,sp,384 + 4c4: 3a0e .2byte 0x3a0e + 4c6: 0221 addi tp,tp,8 # 8 + 4c8: 0b390b3b .4byte 0xb390b3b + 4cc: 1349 addi t1,t1,-14 + 4ce: 0000 unimp + 4d0: 2e1e .2byte 0x2e1e + 4d2: 3101 jal d2 <__crt0_call_constructors+0x6> + 4d4: 12011113 .4byte 0x12011113 + 4d8: 4006 .2byte 0x4006 + 4da: 7a18 .2byte 0x7a18 + 4dc: 0119 addi sp,sp,6 + 4de: 1f000013 li zero,496 + 4e2: 0101 addi sp,sp,0 + 4e4: 1349 addi t1,t1,-14 + 4e6: 1301 addi t1,t1,-32 + 4e8: 0000 unimp + 4ea: 2e20 .2byte 0x2e20 + 4ec: 3f01 jal 3fc <__neorv32_rte_core+0x150> + 4ee: 0319 addi t1,t1,6 + 4f0: 3a0e .2byte 0x3a0e + 4f2: 0721 addi a4,a4,8 + 4f4: 21390b3b .4byte 0x21390b3b + 4f8: 2706 .2byte 0x2706 + 4fa: 3c19 jal ffffff10 <__crt0_stack_begin+0x7fffdf14> + 4fc: 0119 addi sp,sp,6 + 4fe: 21000013 li zero,528 + 502: 0005 c.nop 1 + 504: 1349 addi t1,t1,-14 + 506: 0000 unimp + 508: 1d22 slli s10,s10,0x28 + 50a: 3101 jal 10a <__crt0_call_destructors+0x6> + 50c: 55015213 .4byte 0x55015213 + 510: 01215817 auipc a6,0x1215 + 514: 0b59 addi s6,s6,22 + 516: 13010b57 .4byte 0x13010b57 + 51a: 0000 unimp + 51c: 31011d23 sh a6,794(sp) + 520: 55015213 .4byte 0x55015213 + 524: 01215817 auipc a6,0x1215 + 528: 0559 addi a0,a0,22 + 52a: 13010b57 .4byte 0x13010b57 + 52e: 0000 unimp + 530: 0b24 addi s1,sp,408 + 532: 3101 jal 132 <__crt0_call_destructors_loop_end+0xa> + 534: 01175513 srli a0,a4,0x11 + 538: 25000013 li zero,592 + 53c: 210b000f .4byte 0x210b000f + 540: 4904 lw s1,16(a0) + 542: 26000013 li zero,608 + 546: 0104 addi s1,sp,128 + 548: 213e0e03 lb t3,531(t3) + 54c: 04210b07 .4byte 0x4210b07 + 550: 1349 addi t1,t1,-14 + 552: 0b3a slli s6,s6,0xe + 554: 21390b3b .4byte 0x21390b3b + 558: 0106 slli sp,sp,0x1 + 55a: 27000013 li zero,624 + 55e: 0b0b0113 addi sp,s6,176 + 562: 0188 addi a0,sp,192 + 564: 0421 addi s0,s0,8 + 566: 213a .2byte 0x213a + 568: 3b05 jal 298 + 56a: 3905 jal 19a + 56c: 0921 addi s2,s2,8 + 56e: 1301 addi t1,t1,-32 + 570: 0000 unimp + 572: 1628 addi a0,sp,808 + 574: 0300 addi s0,sp,384 + 576: 3a0e .2byte 0x3a0e + 578: 0521 addi a0,a0,8 + 57a: 2139053b .4byte 0x2139053b + 57e: 88134903 lbu s2,-1919(t1) + 582: 2101 jal 982 <__neorv32_uart_itoa+0x5a> + 584: 0004 .2byte 0x4 + 586: 2900 .2byte 0x2900 + 588: 000d c.nop 3 + 58a: 213a0803 lb a6,531(s4) + 58e: 3b05 jal 2be <__neorv32_rte_core+0x12> + 590: 3905 jal 1c0 + 592: 1221 addi tp,tp,-24 # ffffffe8 <__crt0_stack_begin+0x7fffdfec> + 594: 1349 addi t1,t1,-14 + 596: 0b38 addi a4,sp,408 + 598: 0000 unimp + 59a: 052a slli a0,a0,0xa + 59c: 0300 addi s0,sp,384 + 59e: 3a0e .2byte 0x3a0e + 5a0: 0121 addi sp,sp,8 + 5a2: 0b39053b .4byte 0xb39053b + 5a6: 1349 addi t1,t1,-14 + 5a8: 1702 slli a4,a4,0x20 + 5aa: 0000 unimp + 5ac: 0300342b .4byte 0x300342b + 5b0: 3a0e .2byte 0x3a0e + 5b2: 0121 addi sp,sp,8 + 5b4: 0b39053b .4byte 0xb39053b + 5b8: 1349 addi t1,t1,-14 + 5ba: 1802 slli a6,a6,0x20 + 5bc: 0000 unimp + 5be: 2e2c .2byte 0x2e2c + 5c0: 0301 addi t1,t1,0 + 5c2: 3a0e .2byte 0x3a0e + 5c4: 0121 addi sp,sp,8 + 5c6: 0b39053b .4byte 0xb39053b + 5ca: 21201927 .4byte 0x21201927 + 5ce: 0101 addi sp,sp,0 + 5d0: 2d000013 li zero,720 + 5d4: 0000010b .4byte 0x10b + 5d8: 2e2e .2byte 0x2e2e + 5da: 0301 addi t1,t1,0 + 5dc: 3a0e .2byte 0x3a0e + 5de: 0121 addi sp,sp,8 + 5e0: 0b39053b .4byte 0xb39053b + 5e4: 01111927 .4byte 0x1111927 + 5e8: 0612 slli a2,a2,0x4 + 5ea: 1840 addi s0,sp,52 + 5ec: 197a slli s2,s2,0x3e + 5ee: 1301 addi t1,t1,-32 + 5f0: 0000 unimp + 5f2: 55010b2f .4byte 0x55010b2f + 5f6: 00130117 auipc sp,0x130 + 5fa: 3000 .2byte 0x3000 + 5fc: 0148 addi a0,sp,132 + 5fe: 017d addi sp,sp,31 # 130615 <__neorv32_ram_size+0x12e615> + 600: 0182 c.slli64 gp + 602: 7f19 lui t5,0xfffe6 + 604: 00130113 addi sp,t1,1 + 608: 3100 .2byte 0x3100 + 60a: 012e slli sp,sp,0xb + 60c: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 614: 0521390b .4byte 0x521390b + 618: 13491927 .4byte 0x13491927 + 61c: 0111 addi sp,sp,4 + 61e: 0612 slli a2,a2,0x4 + 620: 1840 addi s0,sp,52 + 622: 197a slli s2,s2,0x3e + 624: 1301 addi t1,t1,-32 + 626: 0000 unimp + 628: 0532 slli a0,a0,0xc + 62a: 0300 addi s0,sp,384 + 62c: 3a08 .2byte 0x3a08 + 62e: 0121 addi sp,sp,8 + 630: 0b390b3b .4byte 0xb390b3b + 634: 1349 addi t1,t1,-14 + 636: 1702 slli a4,a4,0x20 + 638: 0000 unimp + 63a: 31003433 .4byte 0x31003433 + 63e: 00211c13 slli s8,sp,0x2 + 642: 0000 unimp + 644: 2e34 .2byte 0x2e34 + 646: 3f01 jal 556 <__neorv32_rte_print_hex_word+0x62> + 648: 0319 addi t1,t1,6 + 64a: 3a0e .2byte 0x3a0e + 64c: 0221 addi tp,tp,8 # 8 + 64e: 21390b3b .4byte 0x21390b3b + 652: 2731 jal d5e + 654: 4919 li s2,6 + 656: 03212013 slti zero,sp,50 + 65a: 1301 addi t1,t1,-32 + 65c: 0000 unimp + 65e: 1135 addi sp,sp,-19 + 660: 2501 jal c60 + 662: 130e slli t1,t1,0x23 + 664: 1b1f030b .4byte 0x1b1f030b + 668: 551f 1117 1001 .byte 0x1f, 0x55, 0x17, 0x11, 0x01, 0x10 + 66e: 36000017 auipc zero,0x36000 + 672: 0024 addi s1,sp,8 + 674: 0b3e0b0b .4byte 0xb3e0b0b + 678: 00000803 lb a6,0(zero) # 0 <__crt0_entry> + 67c: 27001537 lui a0,0x27001 + 680: 0019 c.nop 6 + 682: 3800 .2byte 0x3800 + 684: 0034 addi a3,sp,8 + 686: 0b3a0e03 lb t3,179(s4) + 68a: 0b390b3b .4byte 0xb390b3b + 68e: 1349 addi t1,t1,-14 + 690: 1802 slli a6,a6,0x20 + 692: 0000 unimp + 694: 1839 addi a6,a6,-18 # 1215512 <__neorv32_ram_size+0x1213512> + 696: 0000 unimp + 698: 3a00 .2byte 0x3a00 + 69a: 012e slli sp,sp,0xb + 69c: 0e03193f 053b0b3a .8byte 0x53b0b3a0e03193f + 6a4: 0b39 addi s6,s6,14 + 6a6: 13491927 .4byte 0x13491927 + 6aa: 0111 addi sp,sp,4 + 6ac: 0612 slli a2,a2,0x4 + 6ae: 1840 addi s0,sp,52 + 6b0: 197a slli s2,s2,0x3e + 6b2: 1301 addi t1,t1,-32 + 6b4: 0000 unimp + 6b6: 0300343b .4byte 0x300343b + 6ba: 3a0e .2byte 0x3a0e + 6bc: 39053b0b .4byte 0x39053b0b + 6c0: 1c13490b .4byte 0x1c13490b + 6c4: 0006 c.slli zero,0x1 + 6c6: 3c00 .2byte 0x3c00 + 6c8: 012e slli sp,sp,0xb + 6ca: 0e03193f 053b0b3a .8byte 0x53b0b3a0e03193f + 6d2: 0b39 addi s6,s6,14 + 6d4: 13491927 .4byte 0x13491927 + 6d8: 0b20 addi s0,sp,408 + 6da: 1301 addi t1,t1,-32 + 6dc: 0000 unimp + 6de: 2e3d jal a1c <__neorv32_uart_itoa+0xf4> + 6e0: 3f01 jal 5f0 <__neorv32_rte_debug_handler+0x8c> + 6e2: 0319 addi t1,t1,6 + 6e4: 3a0e .2byte 0x3a0e + 6e6: 39053b0b .4byte 0x39053b0b + 6ea: 2019270b .4byte 0x2019270b + 6ee: 0013010b .4byte 0x13010b + 6f2: 3e00 .2byte 0x3e00 + 6f4: 0005 c.nop 1 + 6f6: 0b3a0803 lb a6,179(s4) + 6fa: 0b39053b .4byte 0xb39053b + 6fe: 1349 addi t1,t1,-14 + 700: 0000 unimp + 702: 0300053f 3b0b3a08 .8byte 0x3b0b3a080300053f + 70a: 3905 jal 33a <__neorv32_rte_core+0x8e> + 70c: 0213490b .4byte 0x213490b + 710: 40000017 auipc zero,0x40000 + 714: 0005 c.nop 1 + 716: 0b3a0e03 lb t3,179(s4) + 71a: 0b39053b .4byte 0xb39053b + 71e: 1349 addi t1,t1,-14 + 720: 0000 unimp + 722: 2e41 jal ab2 + 724: 0301 addi t1,t1,0 + 726: 3a0e .2byte 0x3a0e + 728: 390b3b0b .4byte 0x390b3b0b + 72c: 2019270b .4byte 0x2019270b + 730: 0013010b .4byte 0x13010b + 734: 4200 lw s0,0(a2) + 736: 1301010b .4byte 0x1301010b + 73a: 0000 unimp + 73c: 03012e43 .4byte 0x3012e43 + 740: 3a0e .2byte 0x3a0e + 742: 390b3b0b .4byte 0x390b3b0b + 746: 8819270b .4byte 0x8819270b + 74a: 0b01 addi s6,s6,0 + 74c: 0111 addi sp,sp,4 + 74e: 0612 slli a2,a2,0x4 + 750: 1840 addi s0,sp,52 + 752: 197c addi a5,sp,188 + 754: 1301 addi t1,t1,-32 + 756: 0000 unimp + 758: 0b44 addi s1,sp,404 + 75a: 1101 addi sp,sp,-32 + 75c: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + 75e: 0106 slli sp,sp,0x1 + 760: 45000013 li zero,1104 + 764: 011d addi sp,sp,7 + 766: 1331 addi t1,t1,-20 + 768: 0111 addi sp,sp,4 + 76a: 0612 slli a2,a2,0x4 + 76c: 0b58 addi a4,sp,404 + 76e: 0b59 addi s6,s6,22 + 770: 00000b57 .4byte 0xb57 + 774: 0546 slli a0,a0,0x11 + 776: 0300 addi s0,sp,384 + 778: 3a0e .2byte 0x3a0e + 77a: 390b3b0b .4byte 0x390b3b0b + 77e: 0213490b .4byte 0x213490b + 782: 0018 .2byte 0x18 + 784: 4700 lw s0,8(a4) + 786: 012e slli sp,sp,0xb + 788: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + 790: 0b39 addi s6,s6,14 + 792: 01111927 .4byte 0x1111927 + 796: 0612 slli a2,a2,0x4 + 798: 1840 addi s0,sp,52 + 79a: 197a slli s2,s2,0x3e + 79c: 1301 addi t1,t1,-32 + 79e: 0000 unimp + 7a0: 3448 .2byte 0x3448 + 7a2: 0300 addi s0,sp,384 + 7a4: 3a08 .2byte 0x3a08 + 7a6: 390b3b0b .4byte 0x390b3b0b + 7aa: 0213490b .4byte 0x213490b + 7ae: 49000017 auipc zero,0x49000 + 7b2: 0034 addi a3,sp,8 + 7b4: 1331 addi t1,t1,-20 + 7b6: 1802 slli a6,a6,0x20 + 7b8: 0000 unimp + 7ba: 2e4a .2byte 0x2e4a + 7bc: 3f01 jal 6cc <__neorv32_rte_debug_handler+0x168> + 7be: 0319 addi t1,t1,6 + 7c0: 3a0e .2byte 0x3a0e + 7c2: 390b3b0b .4byte 0x390b3b0b + 7c6: 2019270b .4byte 0x2019270b + 7ca: 0013010b .4byte 0x13010b + 7ce: 4b00 lw s0,16(a4) + 7d0: 0048 addi a0,sp,4 + 7d2: 017d addi sp,sp,31 + 7d4: 0182 c.slli64 gp + 7d6: 7f19 lui t5,0xfffe6 + 7d8: 4c000013 li zero,1216 + 7dc: 0005 c.nop 1 + 7de: 1331 addi t1,t1,-20 + 7e0: 0000 unimp + 7e2: 344d jal 284 + 7e4: 3100 .2byte 0x3100 + 7e6: 00061c13 slli s8,a2,0x0 + 7ea: 4e00 lw s0,24(a2) + 7ec: 002e c.slli zero,0xb + 7ee: 193c193f 0e030e6e .8byte 0xe030e6e193c193f + 7f6: 0b3a slli s6,s6,0xe + 7f8: 00000b3b .4byte 0xb3b + 7fc: 3f002e4f .4byte 0x3f002e4f + 800: 3c19 jal 216 + 802: 6e19 lui t3,0x6 + 804: 030e slli t1,t1,0x3 + 806: 000e c.slli zero,0x3 + 808: 0000 unimp + 80a: 2801 jal 81a <__neorv32_rte_debug_handler+0x2b6> + 80c: 0300 addi s0,sp,384 + 80e: 1c0e slli s8,s8,0x23 + 810: 0200000b .4byte 0x200000b + 814: 0049 c.nop 18 + 816: 1802 slli a6,a6,0x20 + 818: 187e slli a6,a6,0x3f + 81a: 0000 unimp + 81c: 7d014803 lbu a6,2000(sp) + 820: 7f01 lui t5,0xfffe0 + 822: 00130113 addi sp,t1,1 + 826: 0400 addi s0,sp,512 + 828: 0048 addi a0,sp,4 + 82a: 017d addi sp,sp,31 + 82c: 137f .2byte 0x137f + 82e: 0000 unimp + 830: 3405 jal 250 + 832: 0300 addi s0,sp,384 + 834: 3a08 .2byte 0x3a08 + 836: 0121 addi sp,sp,8 + 838: 0b39053b .4byte 0xb39053b + 83c: 1349 addi t1,t1,-14 + 83e: 1702 slli a4,a4,0x20 + 840: 0000 unimp + 842: 0506 slli a0,a0,0x1 + 844: 0300 addi s0,sp,384 + 846: 3a0e .2byte 0x3a0e + 848: 0121 addi sp,sp,8 + 84a: 0b39053b .4byte 0xb39053b + 84e: 1349 addi t1,t1,-14 + 850: 1702 slli a4,a4,0x20 + 852: 0000 unimp + 854: 03003407 .4byte 0x3003407 + 858: 3a0e .2byte 0x3a0e + 85a: 0121 addi sp,sp,8 + 85c: 0b39053b .4byte 0xb39053b + 860: 1349 addi t1,t1,-14 + 862: 1702 slli a4,a4,0x20 + 864: 0000 unimp + 866: 2408 .2byte 0x2408 + 868: 0b00 addi s0,sp,400 + 86a: 030b3e0b .4byte 0x30b3e0b + 86e: 000e c.slli zero,0x3 + 870: 0900 addi s0,sp,144 + 872: 0016 c.slli zero,0x5 + 874: 0b3a0e03 lb t3,179(s4) + 878: 0b390b3b .4byte 0xb390b3b + 87c: 1349 addi t1,t1,-14 + 87e: 0000 unimp + 880: 0d0a slli s10,s10,0x2 + 882: 0300 addi s0,sp,384 + 884: 3a0e .2byte 0x3a0e + 886: 0421 addi s0,s0,8 + 888: 0b39053b .4byte 0xb39053b + 88c: 1349 addi t1,t1,-14 + 88e: 0b38 addi a4,sp,408 + 890: 0000 unimp + 892: 0300340b .4byte 0x300340b + 896: 3a0e .2byte 0x3a0e + 898: 0121 addi sp,sp,8 + 89a: 21390b3b .4byte 0x21390b3b + 89e: 490c lw a1,16(a0) + 8a0: 00170213 addi tp,a4,1 + 8a4: 0c00 addi s0,sp,528 + 8a6: 012e slli sp,sp,0xb + 8a8: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 8b0: 3905 jal 4e0 <__neorv32_rte_core+0x234> + 8b2: 4919270b .4byte 0x4919270b + 8b6: 12011113 .4byte 0x12011113 + 8ba: 4006 .2byte 0x4006 + 8bc: 7a18 .2byte 0x7a18 + 8be: 0119 addi sp,sp,6 + 8c0: 0d000013 li zero,208 + 8c4: 012e slli sp,sp,0xb + 8c6: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 8ce: 3905 jal 4fe <__neorv32_rte_print_hex_word+0xa> + 8d0: 0621 addi a2,a2,8 + 8d2: 01111927 .4byte 0x1111927 + 8d6: 0612 slli a2,a2,0x4 + 8d8: 1840 addi s0,sp,52 + 8da: 197a slli s2,s2,0x3e + 8dc: 1301 addi t1,t1,-32 + 8de: 0000 unimp + 8e0: 340e .2byte 0x340e + 8e2: 0300 addi s0,sp,384 + 8e4: 3a0e .2byte 0x3a0e + 8e6: 0121 addi sp,sp,8 + 8e8: 0b39053b .4byte 0xb39053b + 8ec: 1349 addi t1,t1,-14 + 8ee: 1802 slli a6,a6,0x20 + 8f0: 0000 unimp + 8f2: 7d01480f .4byte 0x7d01480f + 8f6: 7f01 lui t5,0xfffe0 + 8f8: 10000013 li zero,256 + 8fc: 002e c.slli zero,0xb + 8fe: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + 906: 3905 jal 536 <__neorv32_rte_print_hex_word+0x42> + 908: 4919270b .4byte 0x4919270b + 90c: 12011113 .4byte 0x12011113 + 910: 4006 .2byte 0x4006 + 912: 7a18 .2byte 0x7a18 + 914: 0019 c.nop 6 + 916: 1100 addi s0,sp,160 + 918: 0026 c.slli zero,0x9 + 91a: 1349 addi t1,t1,-14 + 91c: 0000 unimp + 91e: 0512 slli a0,a0,0x4 + 920: 0300 addi s0,sp,384 + 922: 3a08 .2byte 0x3a08 + 924: 0121 addi sp,sp,8 + 926: 0b39053b .4byte 0xb39053b + 92a: 1349 addi t1,t1,-14 + 92c: 1702 slli a4,a4,0x20 + 92e: 0000 unimp + 930: 3f012e13 slti t3,sp,1008 + 934: 0319 addi t1,t1,6 + 936: 3a0e .2byte 0x3a0e + 938: 0121 addi sp,sp,8 + 93a: 0b390b3b .4byte 0xb390b3b + 93e: 13491927 .4byte 0x13491927 + 942: 0111 addi sp,sp,4 + 944: 0612 slli a2,a2,0x4 + 946: 1840 addi s0,sp,52 + 948: 197a slli s2,s2,0x3e + 94a: 1301 addi t1,t1,-32 + 94c: 0000 unimp + 94e: 1314 addi a3,sp,416 + 950: 0b01 addi s6,s6,0 + 952: 2101880b .4byte 0x2101880b + 956: 3a04 .2byte 0x3a04 + 958: 0421 addi s0,s0,8 + 95a: 2139053b .4byte 0x2139053b + 95e: 0109 addi sp,sp,2 + 960: 15000013 li zero,336 + 964: 0016 c.slli zero,0x5 + 966: 213a0e03 lb t3,531(s4) + 96a: 3b04 .2byte 0x3b04 + 96c: 3905 jal 59c <__neorv32_rte_debug_handler+0x38> + 96e: 0321 addi t1,t1,8 + 970: 1349 addi t1,t1,-14 + 972: 0188 addi a0,sp,192 + 974: 0421 addi s0,s0,8 + 976: 0000 unimp + 978: 0416 slli s0,s0,0x5 + 97a: 0301 addi t1,t1,0 + 97c: 3e0e .2byte 0x3e0e + 97e: 0721 addi a4,a4,8 + 980: 4904210b .4byte 0x4904210b + 984: 04213a13 sltiu s4,sp,66 + 988: 2139053b .4byte 0x2139053b + 98c: 0106 slli sp,sp,0x1 + 98e: 17000013 li zero,368 + 992: 0005 c.nop 1 + 994: 213a0803 lb a6,531(s4) + 998: 3b01 jal 6a8 <__neorv32_rte_debug_handler+0x144> + 99a: 3905 jal 5ca <__neorv32_rte_debug_handler+0x66> + 99c: 0213490b .4byte 0x213490b + 9a0: 0018 .2byte 0x18 + 9a2: 1800 addi s0,sp,48 + 9a4: 0101 addi sp,sp,0 + 9a6: 1349 addi t1,t1,-14 + 9a8: 1301 addi t1,t1,-32 + 9aa: 0000 unimp + 9ac: 2119 jal db2 <_sbrk+0x16> + 9ae: 4900 lw s0,16(a0) + 9b0: 000b2f13 slti t5,s6,0 + 9b4: 1a00 addi s0,sp,304 + 9b6: 0034 addi a3,sp,8 + 9b8: 213a0803 lb a6,531(s4) + 9bc: 3b01 jal 6cc <__neorv32_rte_debug_handler+0x168> + 9be: 490b390b .4byte 0x490b390b + 9c2: 00170213 addi tp,a4,1 + 9c6: 1b00 addi s0,sp,432 + 9c8: 0005 c.nop 1 + 9ca: 213a0e03 lb t3,531(s4) + 9ce: 3b01 jal 6de <__neorv32_rte_debug_handler+0x17a> + 9d0: f621 bnez a2,918 + 9d2: 3900 .2byte 0x3900 + 9d4: 0213490b .4byte 0x213490b + 9d8: 1c000017 auipc zero,0x1c000 + 9dc: 210b000f .4byte 0x210b000f + 9e0: 4904 lw s1,16(a0) + 9e2: 1d000013 li zero,464 + 9e6: 000d c.nop 3 + 9e8: 213a0803 lb a6,531(s4) + 9ec: 3b04 .2byte 0x3b04 + 9ee: 3905 jal 61e <__neorv32_rte_debug_handler+0xba> + 9f0: 1221 addi tp,tp,-24 # ffffffe8 <__crt0_stack_begin+0x7fffdfec> + 9f2: 1349 addi t1,t1,-14 + 9f4: 0b38 addi a4,sp,408 + 9f6: 0000 unimp + 9f8: 051e slli a0,a0,0x7 + 9fa: 0300 addi s0,sp,384 + 9fc: 3a08 .2byte 0x3a08 + 9fe: 0121 addi sp,sp,8 + a00: 078d213b .4byte 0x78d213b + a04: 0b39 addi s6,s6,14 + a06: 1349 addi t1,t1,-14 + a08: 0000 unimp + a0a: 2e1f 0301 3a0e .byte 0x1f, 0x2e, 0x01, 0x03, 0x0e, 0x3a + a10: 0121 addi sp,sp,8 + a12: 2139053b .4byte 0x2139053b + a16: 270d jal 1138 <_malloc_r+0x2da> + a18: 1119 addi sp,sp,-26 + a1a: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + a1c: 4006 .2byte 0x4006 + a1e: 7a18 .2byte 0x7a18 + a20: 0119 addi sp,sp,6 + a22: 20000013 li zero,512 + a26: 0018 .2byte 0x18 + a28: 0000 unimp + a2a: 3421 jal 432 <__neorv32_rte_core+0x186> + a2c: 0300 addi s0,sp,384 + a2e: 3a08 .2byte 0x3a08 + a30: 0121 addi sp,sp,8 + a32: 2139053b .4byte 0x2139053b + a36: 0213490b .4byte 0x213490b + a3a: 0018 .2byte 0x18 + a3c: 2200 .2byte 0x2200 + a3e: 0049 c.nop 18 + a40: 0180 addi s0,sp,192 + a42: 00187e13 andi t3,a6,1 + a46: 2300 .2byte 0x2300 + a48: 002e c.slli zero,0xb + a4a: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + a52: 3905 jal 682 <__neorv32_rte_debug_handler+0x11e> + a54: 0621 addi a2,a2,8 + a56: 01111927 .4byte 0x1111927 + a5a: 0612 slli a2,a2,0x4 + a5c: 1840 addi s0,sp,52 + a5e: 197a slli s2,s2,0x3e + a60: 0000 unimp + a62: 2e24 .2byte 0x2e24 + a64: 3f01 jal 974 <__neorv32_uart_itoa+0x4c> + a66: 0319 addi t1,t1,6 + a68: 3a0e .2byte 0x3a0e + a6a: 0121 addi sp,sp,8 + a6c: 21390b3b .4byte 0x21390b3b + a70: 2706 .2byte 0x2706 + a72: 1119 addi sp,sp,-26 + a74: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + a76: 4006 .2byte 0x4006 + a78: 7a18 .2byte 0x7a18 + a7a: 0119 addi sp,sp,6 + a7c: 25000013 li zero,592 + a80: 002e c.slli zero,0xb + a82: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + a8a: 0621390b .4byte 0x621390b + a8e: 01111927 .4byte 0x1111927 + a92: 0612 slli a2,a2,0x4 + a94: 1840 addi s0,sp,52 + a96: 197a slli s2,s2,0x3e + a98: 0000 unimp + a9a: 2e26 .2byte 0x2e26 + a9c: 3f00 .2byte 0x3f00 + a9e: 3c19 jal 4b4 <__neorv32_rte_core+0x208> + aa0: 6e19 lui t3,0x6 + aa2: 030e slli t1,t1,0x3 + aa4: 000e c.slli zero,0x3 + aa6: 2700 .2byte 0x2700 + aa8: 0111 addi sp,sp,4 + aaa: 0e25 addi t3,t3,9 # 6009 <__neorv32_ram_size+0x4009> + aac: 1f030b13 addi s6,t1,496 + ab0: 17551f1b .4byte 0x17551f1b + ab4: 0111 addi sp,sp,4 + ab6: 1710 addi a2,sp,928 + ab8: 0000 unimp + aba: 2428 .2byte 0x2428 + abc: 0b00 addi s0,sp,400 + abe: 030b3e0b .4byte 0x30b3e0b + ac2: 0008 .2byte 0x8 + ac4: 2900 .2byte 0x2900 + ac6: 0b0b000f .4byte 0xb0b000f + aca: 00000e03 lb t3,0(zero) # 0 <__crt0_entry> + ace: 2e2a .2byte 0x2e2a + ad0: 0301 addi t1,t1,0 + ad2: 3a0e .2byte 0x3a0e + ad4: 39053b0b .4byte 0x39053b0b + ad8: 2019270b .4byte 0x2019270b + adc: 0013010b .4byte 0x13010b + ae0: 2b00 .2byte 0x2b00 + ae2: 0034 addi a3,sp,8 + ae4: 0b3a0803 lb a6,179(s4) + ae8: 0b39053b .4byte 0xb39053b + aec: 1349 addi t1,t1,-14 + aee: 0000 unimp + af0: 0b2c addi a1,sp,408 + af2: 5501 li a0,-32 + af4: 2d000017 auipc zero,0x2d000 + af8: 0034 addi a3,sp,8 + afa: 0b3a0e03 lb t3,179(s4) + afe: 0b39053b .4byte 0xb39053b + b02: 1349 addi t1,t1,-14 + b04: 0000 unimp + b06: 052e slli a0,a0,0xb + b08: 0300 addi s0,sp,384 + b0a: 3a08 .2byte 0x3a08 + b0c: 390b3b0b .4byte 0x390b3b0b + b10: 0213490b .4byte 0x213490b + b14: 0018 .2byte 0x18 + b16: 2f00 .2byte 0x2f00 + b18: 0034 addi a3,sp,8 + b1a: 0b3a0e03 lb t3,179(s4) + b1e: 0b390b3b .4byte 0xb390b3b + b22: 1349 addi t1,t1,-14 + b24: 0000 unimp + b26: 2e30 .2byte 0x2e30 + b28: 3f00 .2byte 0x3f00 + b2a: 0319 addi t1,t1,6 + b2c: 3a0e .2byte 0x3a0e + b2e: 390b3b0b .4byte 0x390b3b0b + b32: 4919270b .4byte 0x4919270b + b36: 12011113 .4byte 0x12011113 + b3a: 4006 .2byte 0x4006 + b3c: 7a18 .2byte 0x7a18 + b3e: 0019 c.nop 6 + b40: 3100 .2byte 0x3100 + b42: 0005 c.nop 1 + b44: 0b3a0803 lb a6,179(s4) + b48: 0b390b3b .4byte 0xb390b3b + b4c: 1349 addi t1,t1,-14 + b4e: 1702 slli a4,a4,0x20 + b50: 0000 unimp + b52: 2e32 .2byte 0x2e32 + b54: 3101 jal 754 <__neorv32_rte_debug_handler+0x1f0> + b56: 12011113 .4byte 0x12011113 + b5a: 4006 .2byte 0x4006 + b5c: 7a18 .2byte 0x7a18 + b5e: 0119 addi sp,sp,6 + b60: 33000013 li zero,816 + b64: 0005 c.nop 1 + b66: 1331 addi t1,t1,-20 + b68: 1702 slli a4,a4,0x20 + b6a: 0000 unimp + b6c: 3434 .2byte 0x3434 + b6e: 3100 .2byte 0x3100 + b70: 00170213 addi tp,a4,1 + b74: 3500 .2byte 0x3500 + b76: 0005 c.nop 1 + b78: 1331 addi t1,t1,-20 + b7a: 0b1c addi a5,sp,400 + b7c: 0000 unimp + b7e: 0100 addi s0,sp,128 + b80: 0016 c.slli zero,0x5 + b82: 0b3a0e03 lb t3,179(s4) + b86: 0b390b3b .4byte 0xb390b3b + b8a: 1349 addi t1,t1,-14 + b8c: 0000 unimp + b8e: 0d02 c.slli64 s10 + b90: 0300 addi s0,sp,384 + b92: 3a0e .2byte 0x3a0e + b94: 390b3b0b .4byte 0x390b3b0b + b98: 3813490b .4byte 0x3813490b + b9c: 0300000b .4byte 0x300000b + ba0: 012e slli sp,sp,0xb + ba2: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + baa: 270b390b .4byte 0x270b390b + bae: 4919 li s2,6 + bb0: 12011113 .4byte 0x12011113 + bb4: 4006 .2byte 0x4006 + bb6: 7a18 .2byte 0x7a18 + bb8: 0119 addi sp,sp,6 + bba: 04000013 li zero,64 + bbe: 0005 c.nop 1 + bc0: 213a0e03 lb t3,531(s4) + bc4: 3b01 jal 8d4 + bc6: 490b390b .4byte 0x490b390b + bca: 05000013 li zero,80 + bce: 0005 c.nop 1 + bd0: 213a0e03 lb t3,531(s4) + bd4: 3b01 jal 8e4 + bd6: 490b390b .4byte 0x490b390b + bda: 00170213 addi tp,a4,1 + bde: 0600 addi s0,sp,768 + be0: 210b000f .4byte 0x210b000f + be4: 4904 lw s1,16(a0) + be6: 07000013 li zero,112 + bea: 0005 c.nop 1 + bec: 213a0e03 lb t3,531(s4) + bf0: 3b01 jal 900 + bf2: 490b390b .4byte 0x490b390b + bf6: 00180213 addi tp,a6,1 + bfa: 0800 addi s0,sp,16 + bfc: 0024 addi s1,sp,8 + bfe: 0b3e0b0b .4byte 0xb3e0b0b + c02: 00000e03 lb t3,0(zero) # 0 <__crt0_entry> + c06: 0509 addi a0,a0,2 # 27001002 <__neorv32_ram_size+0x26fff002> + c08: 0300 addi s0,sp,384 + c0a: 3a08 .2byte 0x3a08 + c0c: 0121 addi sp,sp,8 + c0e: 0b390b3b .4byte 0xb390b3b + c12: 1349 addi t1,t1,-14 + c14: 1802 slli a6,a6,0x20 + c16: 0000 unimp + c18: 050a slli a0,a0,0x2 + c1a: 0300 addi s0,sp,384 + c1c: 3a08 .2byte 0x3a08 + c1e: 0121 addi sp,sp,8 + c20: 0b390b3b .4byte 0xb390b3b + c24: 1349 addi t1,t1,-14 + c26: 1702 slli a4,a4,0x20 + c28: 0000 unimp + c2a: 0301130b .4byte 0x301130b + c2e: 0b0e slli s6,s6,0x3 + c30: 3b0b3a0b .4byte 0x3b0b3a0b + c34: 0821390b .4byte 0x821390b + c38: 1301 addi t1,t1,-32 + c3a: 0000 unimp + c3c: 480c lw a1,16(s0) + c3e: 7d00 .2byte 0x7d00 + c40: 7f01 lui t5,0xfffe0 + c42: 0d000013 li zero,208 + c46: 012e slli sp,sp,0xb + c48: 0e03193f 3b01213a .8byte 0x3b01213a0e03193f + c50: 270b390b .4byte 0x270b390b + c54: 4919 li s2,6 + c56: 00130113 addi sp,t1,1 + c5a: 0e00 addi s0,sp,784 + c5c: 0026 c.slli zero,0x9 + c5e: 1349 addi t1,t1,-14 + c60: 0000 unimp + c62: 3f012e0f .4byte 0x3f012e0f + c66: 0319 addi t1,t1,6 + c68: 3a0e .2byte 0x3a0e + c6a: 0121 addi sp,sp,8 + c6c: 21390b3b .4byte 0x21390b3b + c70: 2705 jal 1390 <_malloc_r+0x532> + c72: 4919 li s2,6 + c74: 01212013 slti zero,sp,18 + c78: 1301 addi t1,t1,-32 + c7a: 0000 unimp + c7c: 0510 addi a2,sp,640 + c7e: 3100 .2byte 0x3100 + c80: 00170213 addi tp,a4,1 + c84: 1100 addi s0,sp,160 + c86: 0005 c.nop 1 + c88: 1331 addi t1,t1,-20 + c8a: 1802 slli a6,a6,0x20 + c8c: 0000 unimp + c8e: 2e12 .2byte 0x2e12 + c90: 3f01 jal ba0 + c92: 0319 addi t1,t1,6 + c94: 3a0e .2byte 0x3a0e + c96: 0121 addi sp,sp,8 + c98: 0b39053b .4byte 0xb39053b + c9c: 13491927 .4byte 0x13491927 + ca0: 0111 addi sp,sp,4 + ca2: 0612 slli a2,a2,0x4 + ca4: 1840 addi s0,sp,52 + ca6: 197a slli s2,s2,0x3e + ca8: 1301 addi t1,t1,-32 + caa: 0000 unimp + cac: 03000513 li a0,48 + cb0: 3a0e .2byte 0x3a0e + cb2: 0121 addi sp,sp,8 + cb4: 0b39053b .4byte 0xb39053b + cb8: 1349 addi t1,t1,-14 + cba: 1702 slli a4,a4,0x20 + cbc: 0000 unimp + cbe: 2e14 .2byte 0x2e14 + cc0: 3101 jal 8c0 + cc2: 12011113 .4byte 0x12011113 + cc6: 4006 .2byte 0x4006 + cc8: 7a18 .2byte 0x7a18 + cca: 0119 addi sp,sp,6 + ccc: 15000013 li zero,336 + cd0: 0101 addi sp,sp,0 + cd2: 1349 addi t1,t1,-14 + cd4: 1301 addi t1,t1,-32 + cd6: 0000 unimp + cd8: 3416 .2byte 0x3416 + cda: 0300 addi s0,sp,384 + cdc: 3a0e .2byte 0x3a0e + cde: 0121 addi sp,sp,8 + ce0: 2139053b .4byte 0x2139053b + ce4: 490d li s2,3 + ce6: 3c193f13 sltiu t5,s2,961 + cea: 0019 c.nop 6 + cec: 1700 addi s0,sp,928 + cee: 012e slli sp,sp,0xb + cf0: 0e03193f 3b0c213a .8byte 0x3b0c213a0e03193f + cf8: 0621390b .4byte 0x621390b + cfc: 193c1927 .4byte 0x193c1927 + d00: 1301 addi t1,t1,-32 + d02: 0000 unimp + d04: 0518 addi a4,sp,640 + d06: 4900 lw s0,16(a0) + d08: 19000013 li zero,400 + d0c: 002e c.slli zero,0xb + d0e: 0e03193f 3b0c213a .8byte 0x3b0c213a0e03193f + d16: 0621390b .4byte 0x621390b + d1a: 13491927 .4byte 0x13491927 + d1e: 193c addi a5,sp,184 + d20: 0000 unimp + d22: 341a .2byte 0x341a + d24: 0300 addi s0,sp,384 + d26: 3a0e .2byte 0x3a0e + d28: 0121 addi sp,sp,8 + d2a: 0b39053b .4byte 0xb39053b + d2e: 1349 addi t1,t1,-14 + d30: 1702 slli a4,a4,0x20 + d32: 0000 unimp + d34: 0300051b .4byte 0x300051b + d38: 3a08 .2byte 0x3a08 + d3a: 0121 addi sp,sp,8 + d3c: 0281213b .4byte 0x281213b + d40: 0b39 addi s6,s6,14 + d42: 1349 addi t1,t1,-14 + d44: 1702 slli a4,a4,0x20 + d46: 0000 unimp + d48: 051c addi a5,sp,640 + d4a: 0300 addi s0,sp,384 + d4c: 3a08 .2byte 0x3a08 + d4e: 0121 addi sp,sp,8 + d50: 0b390b3b .4byte 0xb390b3b + d54: 1349 addi t1,t1,-14 + d56: 0000 unimp + d58: 111d addi sp,sp,-25 + d5a: 2501 jal 135a <_malloc_r+0x4fc> + d5c: 130e slli t1,t1,0x23 + d5e: 1b1f030b .4byte 0x1b1f030b + d62: 551f 1117 1001 .byte 0x1f, 0x55, 0x17, 0x11, 0x01, 0x10 + d68: 1e000017 auipc zero,0x1e000 + d6c: 0024 addi s1,sp,8 + d6e: 0b3e0b0b .4byte 0xb3e0b0b + d72: 00000803 lb a6,0(zero) # 0 <__crt0_entry> + d76: 0f1f 0b00 000b .byte 0x1f, 0x0f, 0x00, 0x0b, 0x0b, 0x00 + d7c: 2000 .2byte 0x2000 + d7e: 0021 c.nop 8 + d80: 1349 addi t1,t1,-14 + d82: 00000b2f .4byte 0xb2f + d86: 1321 addi t1,t1,-24 + d88: 0301 addi t1,t1,0 + d8a: 0b08 addi a0,sp,400 + d8c: 3b0b3a0b .4byte 0x3b0b3a0b + d90: 010b390b .4byte 0x10b390b + d94: 22000013 li zero,544 + d98: 0026 c.slli zero,0x9 + d9a: 0000 unimp + d9c: 03003423 .4byte 0x3003423 + da0: 3a0e .2byte 0x3a0e + da2: 390b3b0b .4byte 0x390b3b0b + da6: 3f13490b .4byte 0x3f13490b + daa: 3c19 jal 7c0 <__neorv32_rte_debug_handler+0x25c> + dac: 0019 c.nop 6 + dae: 2400 .2byte 0x2400 + db0: 0021 c.nop 8 + db2: 0000 unimp + db4: 3425 jal 7dc <__neorv32_rte_debug_handler+0x278> + db6: 0300 addi s0,sp,384 + db8: 3a08 .2byte 0x3a08 + dba: 39053b0b .4byte 0x39053b0b + dbe: 0213490b .4byte 0x213490b + dc2: 0018 .2byte 0x18 + dc4: 2600 .2byte 0x2600 + dc6: 0034 addi a3,sp,8 + dc8: 0b3a0e03 lb t3,179(s4) + dcc: 0b390b3b .4byte 0xb390b3b + dd0: 1349 addi t1,t1,-14 + dd2: 1702 slli a4,a4,0x20 + dd4: 0000 unimp + dd6: 11010b27 .4byte 0x11010b27 + dda: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + ddc: 0106 slli sp,sp,0x1 + dde: 28000013 li zero,640 + de2: 0034 addi a3,sp,8 + de4: 0b3a0e03 lb t3,179(s4) + de8: 0b390b3b .4byte 0xb390b3b + dec: 1349 addi t1,t1,-14 + dee: 1802 slli a6,a6,0x20 + df0: 0000 unimp + df2: 2e29 jal 110c <_malloc_r+0x2ae> + df4: 3f00 .2byte 0x3f00 + df6: 0319 addi t1,t1,6 + df8: 3a0e .2byte 0x3a0e + dfa: 390b3b0b .4byte 0x390b3b0b + dfe: 1113490b .4byte 0x1113490b + e02: 1201 addi tp,tp,-32 # ffffffe0 <__crt0_stack_begin+0x7fffdfe4> + e04: 4006 .2byte 0x4006 + e06: 7a18 .2byte 0x7a18 + e08: 0019 c.nop 6 + e0a: 2a00 .2byte 0x2a00 + e0c: 002e c.slli zero,0xb + e0e: 0e03193f 0b3b0b3a .8byte 0xb3b0b3a0e03193f + e16: 0b39 addi s6,s6,14 + e18: 13491927 .4byte 0x13491927 + e1c: 0111 addi sp,sp,4 + e1e: 0612 slli a2,a2,0x4 + e20: 1840 addi s0,sp,52 + e22: 197a slli s2,s2,0x3e + e24: 0000 unimp + e26: 3f012e2b .4byte 0x3f012e2b + e2a: 0319 addi t1,t1,6 + e2c: 3a0e .2byte 0x3a0e + e2e: 390b3b0b .4byte 0x390b3b0b + e32: 8719270b .4byte 0x8719270b + e36: 1901 addi s2,s2,-32 + e38: 0111 addi sp,sp,4 + e3a: 0612 slli a2,a2,0x4 + e3c: 1840 addi s0,sp,52 + e3e: 197a slli s2,s2,0x3e + e40: 1301 addi t1,t1,-32 + e42: 0000 unimp + e44: 2e2c .2byte 0x2e2c + e46: 3f01 jal d56 + e48: 0319 addi t1,t1,6 + e4a: 3a0e .2byte 0x3a0e + e4c: 390b3b0b .4byte 0x390b3b0b + e50: 1201110b .4byte 0x1201110b + e54: 4006 .2byte 0x4006 + e56: 7a18 .2byte 0x7a18 + e58: 0119 addi sp,sp,6 + e5a: 2d000013 li zero,720 + e5e: 0148 addi a0,sp,132 + e60: 017d addi sp,sp,31 + e62: 0182 c.slli64 gp + e64: 7f19 lui t5,0xfffe6 + e66: 2e000013 li zero,736 + e6a: 0049 c.nop 18 + e6c: 1802 slli a6,a6,0x20 + e6e: 187e slli a6,a6,0x3f + e70: 0000 unimp + e72: 31012e2f .4byte 0x31012e2f + e76: 12011113 .4byte 0x12011113 + e7a: 4006 .2byte 0x4006 + e7c: 7a18 .2byte 0x7a18 + e7e: 0019 c.nop 6 + e80: 0000 unimp + e82: 1101 addi sp,sp,-32 + e84: 1000 addi s0,sp,32 + e86: 12011117 auipc sp,0x12011 + e8a: 1b0e030f .4byte 0x1b0e030f + e8e: 250e .2byte 0x250e + e90: 130e slli t1,t1,0x23 + e92: 0005 c.nop 1 + e94: 0000 unimp + e96: 1101 addi sp,sp,-32 # 12011e66 <__neorv32_ram_size+0x1200fe66> + e98: 1001 c.nop -32 + e9a: 12011117 auipc sp,0x12011 + e9e: 1b0e030f .4byte 0x1b0e030f + ea2: 250e .2byte 0x250e + ea4: 130e slli t1,t1,0x23 + ea6: 0005 c.nop 1 + ea8: 0200 addi s0,sp,256 + eaa: 002e c.slli zero,0xb + eac: 193f0e03 lb t3,403(t5) # fffe6193 <__crt0_stack_begin+0x7ffe4197> + eb0: 0111 addi sp,sp,4 # 12011e9e <__neorv32_ram_size+0x1200fe9e> + eb2: 0f12 slli t5,t5,0x4 + eb4: 0000 unimp + ... + +Disassembly of section .debug_line: + +00000000 <.debug_line>: + 0: 026c addi a1,sp,268 + 2: 0000 unimp + 4: 0005 c.nop 1 + 6: 0004 .2byte 0x4 + 8: 0066 c.slli zero,0x19 + a: 0000 unimp + c: 0101 addi sp,sp,0 + e: fb01 bnez a4,ffffff1e <__crt0_stack_begin+0x7fffdf22> + 10: 0d0e slli s10,s10,0x3 + 12: 0100 addi s0,sp,128 + 14: 0101 addi sp,sp,0 + 16: 0001 nop + 18: 0000 unimp + 1a: 0001 nop + 1c: 0100 addi s0,sp,128 + 1e: 0101 addi sp,sp,0 + 20: 061f 0007 0000 .byte 0x1f, 0x06, 0x07, 0x00, 0x00, 0x00 + 26: 003c addi a5,sp,8 + 28: 0000 unimp + 2a: 0000006b .4byte 0x6b + 2e: 0096 slli ra,ra,0x5 + 30: 0000 unimp + 32: 00cc addi a1,sp,68 + 34: 0000 unimp + 36: 00e6 slli ra,ra,0x19 + 38: 0000 unimp + 3a: 0102 c.slli64 sp + 3c: 021f 0a0f 0000 .byte 0x1f, 0x02, 0x0f, 0x0a, 0x00, 0x00 + ... + 4a: 010d addi sp,sp,3 + 4c: 0000 unimp + 4e: 1e01 addi t3,t3,-32 + 50: 0001 nop + 52: 0200 addi s0,sp,256 + 54: 0128 addi a0,sp,136 + 56: 0000 unimp + 58: 00013103 .4byte 0x13103 + 5c: 0400 addi s0,sp,512 + 5e: 0000013b .4byte 0x13b + 62: 4a04 lw s1,16(a2) + 64: 0001 nop + 66: 0500 addi s0,sp,640 + 68: 00000153 .4byte 0x153 + 6c: 6104 .2byte 0x6104 + 6e: 0001 nop + 70: 0400 addi s0,sp,512 + 72: 2505 jal 692 <__neorv32_rte_debug_handler+0x12e> + 74: 0500 addi s0,sp,640 + 76: 7802 .2byte 0x7802 + 78: 0002 c.slli64 zero + 7a: 0300 addi s0,sp,384 + 7c: 0134 addi a3,sp,136 + 7e: 0305 addi t1,t1,1 + 80: 00090103 lb sp,0(s2) + 84: 0100 addi s0,sp,128 + 86: 0705 addi a4,a4,1 + 88: 00090003 lb zero,0(s2) + 8c: 0100 addi s0,sp,128 + 8e: 1005 c.nop -31 + 90: 0306 slli t1,t1,0x1 + 92: 0900 addi s0,sp,144 + 94: 0000 unimp + 96: 0501 addi a0,a0,0 + 98: 0016 c.slli zero,0x5 + 9a: 0402 c.slli64 s0 + 9c: 0601 addi a2,a2,0 + 9e: 04090003 lb zero,64(s2) + a2: 0100 addi s0,sp,128 + a4: 0105 addi sp,sp,1 + a6: 0306 slli t1,t1,0x1 + a8: 00040903 lb s2,0(s0) + ac: 0501 addi a0,a0,0 + ae: 0005 c.nop 1 + b0: 0402 c.slli64 s0 + b2: 7e030603 lb a2,2016(t1) + b6: 0409 addi s0,s0,2 + b8: 0100 addi s0,sp,128 + ba: 0a05 addi s4,s4,1 + bc: 0200 addi s0,sp,256 + be: 0304 addi s1,sp,384 + c0: 0306 slli t1,t1,0x1 + c2: 0900 addi s0,sp,144 + c4: 0000 unimp + c6: 0501 addi a0,a0,0 + c8: 0402001b .4byte 0x402001b + cc: 7f030603 lb a2,2032(t1) + d0: 0c09 addi s8,s8,2 + d2: 0100 addi s0,sp,128 + d4: 0809 addi a6,a6,2 + d6: 0000 unimp + d8: 0101 addi sp,sp,0 + da: 0c05 addi s8,s8,1 + dc: 0500 addi s0,sp,640 + de: 8802 jr a6 + e0: 0001 nop + e2: 0300 addi s0,sp,384 + e4: 00c2 slli ra,ra,0x10 + e6: 0501 addi a0,a0,0 + e8: 09010303 lb t1,144(sp) + ec: 0000 unimp + ee: 0301 addi t1,t1,0 + f0: 0901 addi s2,s2,0 + f2: 0000 unimp + f4: 0301 addi t1,t1,0 + f6: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + fa: 0501 addi a0,a0,0 + fc: 060c addi a1,sp,768 + fe: 00097b03 .4byte 0x97b03 + 102: 0100 addi s0,sp,128 + 104: 0305 addi t1,t1,1 + 106: 20090503 lb a0,512(s2) + 10a: 0100 addi s0,sp,128 + 10c: 0306 slli t1,t1,0x1 + 10e: 00040903 lb s2,0(s0) + 112: 0301 addi t1,t1,0 + 114: 00140903 lb s2,1(s0) + 118: 0301 addi t1,t1,0 + 11a: 00080903 lb s2,0(a6) + 11e: 0301 addi t1,t1,0 + 120: 0901 addi s2,s2,0 + 122: 000c .2byte 0xc + 124: 0501 addi a0,a0,0 + 126: 063e slli a2,a2,0xf + 128: 00090003 lb zero,0(s2) + 12c: 0100 addi s0,sp,128 + 12e: 0305 addi t1,t1,1 + 130: 04090003 lb zero,64(s2) + 134: 0100 addi s0,sp,128 + 136: 0306 slli t1,t1,0x1 + 138: 0902 c.slli64 s2 + 13a: 000c .2byte 0xc + 13c: 0501 addi a0,a0,0 + 13e: 061e slli a2,a2,0x7 + 140: 00090003 lb zero,0(s2) + 144: 0100 addi s0,sp,128 + 146: 0305 addi t1,t1,1 + 148: 0306 slli t1,t1,0x1 + 14a: 0901 addi s2,s2,0 + 14c: 000c .2byte 0xc + 14e: 0501 addi a0,a0,0 + 150: 09000307 .4byte 0x9000307 + 154: 0000 unimp + 156: 0501 addi a0,a0,0 + 158: 0316 slli t1,t1,0x5 + 15a: 0900 addi s0,sp,144 + 15c: 0000 unimp + 15e: 0501 addi a0,a0,0 + 160: 061e slli a2,a2,0x7 + 162: 00097f03 .4byte 0x97f03 + 166: 0100 addi s0,sp,128 + 168: 0505 addi a0,a0,1 + 16a: 04090d03 lb s10,64(s2) + 16e: 0100 addi s0,sp,128 + 170: 1605 addi a2,a2,-31 + 172: 04097403 .4byte 0x4097403 + 176: 0100 addi s0,sp,128 + 178: 0505 addi a0,a0,1 + 17a: 0306 slli t1,t1,0x1 + 17c: 0901 addi s2,s2,0 + 17e: 0004 .2byte 0x4 + 180: 0301 addi t1,t1,0 + 182: 0902 c.slli64 s2 + 184: 0000 unimp + 186: 0501 addi a0,a0,0 + 188: 0618 addi a4,sp,768 + 18a: 00090003 lb zero,0(s2) + 18e: 0100 addi s0,sp,128 + 190: 0505 addi a0,a0,1 + 192: 0306 slli t1,t1,0x1 + 194: 0902 c.slli64 s2 + 196: 0008 .2byte 0x8 + 198: 0501 addi a0,a0,0 + 19a: 0309 addi t1,t1,2 + 19c: 0900 addi s0,sp,144 + 19e: 0000 unimp + 1a0: 0501 addi a0,a0,0 + 1a2: 0318 addi a4,sp,384 + 1a4: 0900 addi s0,sp,144 + 1a6: 0000 unimp + 1a8: 0501 addi a0,a0,0 + 1aa: 0610 addi a2,sp,768 + 1ac: 00097e03 .4byte 0x97e03 + 1b0: 0100 addi s0,sp,128 + 1b2: 0705 addi a4,a4,1 + 1b4: 0200 addi s0,sp,256 + 1b6: 0304 addi s1,sp,384 + 1b8: 0306 slli t1,t1,0x1 + 1ba: 00040903 lb s2,0(s0) + 1be: 0501 addi a0,a0,0 + 1c0: 0018 .2byte 0x18 + 1c2: 0402 c.slli64 s0 + 1c4: 7f030603 lb a2,2032(t1) + 1c8: 0809 addi a6,a6,2 + 1ca: 0100 addi s0,sp,128 + 1cc: 0705 addi a4,a4,1 + 1ce: 0200 addi s0,sp,256 + 1d0: 0304 addi s1,sp,384 + 1d2: 04090103 lb sp,64(s2) + 1d6: 0100 addi s0,sp,128 + 1d8: 1e05 addi t3,t3,-31 + 1da: 0200 addi s0,sp,256 + 1dc: 0304 addi s1,sp,384 + 1de: 0306 slli t1,t1,0x1 + 1e0: 097f .2byte 0x97f + 1e2: 0004 .2byte 0x4 + 1e4: 0501 addi a0,a0,0 + 1e6: 0018 .2byte 0x18 + 1e8: 0402 c.slli64 s0 + 1ea: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 1ee: 0000 unimp + 1f0: 0501 addi a0,a0,0 + 1f2: 0005 c.nop 1 + 1f4: 0402 c.slli64 s0 + 1f6: 0302 c.slli64 t1 + 1f8: 0904 addi s1,sp,144 + 1fa: 0004 .2byte 0x4 + 1fc: 0501 addi a0,a0,0 + 1fe: 0016 c.slli zero,0x5 + 200: 0402 c.slli64 s0 + 202: 0602 c.slli64 a2 + 204: 00090003 lb zero,0(s2) + 208: 0100 addi s0,sp,128 + 20a: 0505 addi a0,a0,1 + 20c: 0200 addi s0,sp,256 + 20e: 0204 addi s1,sp,256 + 210: 0306 slli t1,t1,0x1 + 212: 0901 addi s2,s2,0 + 214: 0004 .2byte 0x4 + 216: 0001 nop + 218: 0402 c.slli64 s0 + 21a: 0302 c.slli64 t1 + 21c: 0902 c.slli64 s2 + 21e: 0000 unimp + 220: 0501 addi a0,a0,0 + 222: 0016 c.slli zero,0x5 + 224: 0402 c.slli64 s0 + 226: 0602 c.slli64 a2 + 228: 18097403 .4byte 0x18097403 + 22c: 0100 addi s0,sp,128 + 22e: 0505 addi a0,a0,1 + 230: 0200 addi s0,sp,256 + 232: 0204 addi s1,sp,256 + 234: 04090c03 lb s8,64(s2) + 238: 0100 addi s0,sp,128 + 23a: 1e05 addi t3,t3,-31 + 23c: 0200 addi s0,sp,256 + 23e: 0204 addi s1,sp,256 + 240: 0306 slli t1,t1,0x1 + 242: 0974 addi a3,sp,156 + 244: 0004 .2byte 0x4 + 246: 0501 addi a0,a0,0 + 248: 0016 c.slli zero,0x5 + 24a: 0402 c.slli64 s0 + 24c: 0302 c.slli64 t1 + 24e: 0900 addi s0,sp,144 + 250: 0000 unimp + 252: 0501 addi a0,a0,0 + 254: 090e0303 lb t1,144(t3) + 258: 0004 .2byte 0x4 + 25a: 0301 addi t1,t1,0 + 25c: 0901 addi s2,s2,0 + 25e: 000c .2byte 0xc + 260: 0501 addi a0,a0,0 + 262: 0601 addi a2,a2,0 + 264: 00090103 lb sp,0(s2) + 268: 0100 addi s0,sp,128 + 26a: 2809 jal 27c + 26c: 0000 unimp + 26e: 0101 addi sp,sp,0 + 270: 022a slli tp,tp,0xa + 272: 0000 unimp + 274: 0005 c.nop 1 + 276: 0004 .2byte 0x4 + 278: 0049 c.nop 18 + 27a: 0000 unimp + 27c: 0101 addi sp,sp,0 + 27e: fb01 bnez a4,18e + 280: 0d0e slli s10,s10,0x3 + 282: 0100 addi s0,sp,128 + 284: 0101 addi sp,sp,0 + 286: 0001 nop + 288: 0000 unimp + 28a: 0001 nop + 28c: 0100 addi s0,sp,128 + 28e: 0101 addi sp,sp,0 + 290: 051f 0198 0000 .byte 0x1f, 0x05, 0x98, 0x01, 0x00, 0x00 + 296: 000001db .4byte 0x1db + 29a: 003c addi a5,sp,8 + 29c: 0000 unimp + 29e: 0000006b .4byte 0x6b + 2a2: 01f2 slli gp,gp,0x1c + 2a4: 0000 unimp + 2a6: 0102 c.slli64 sp + 2a8: 021f 050f 0188 .byte 0x1f, 0x02, 0x0f, 0x05, 0x88, 0x01 + 2ae: 0000 unimp + 2b0: 8801 andi s0,s0,0 + 2b2: 0001 nop + 2b4: 0100 addi s0,sp,128 + 2b6: 010d addi sp,sp,3 + 2b8: 0000 unimp + 2ba: 1e02 slli t3,t3,0x20 + 2bc: 0001 nop + 2be: 0300 addi s0,sp,384 + 2c0: 0131 addi sp,sp,12 + 2c2: 0000 unimp + 2c4: 0504 addi s1,sp,640 + 2c6: 02050023 sb zero,32(a0) + 2ca: 0000 unimp + 2cc: 0000 unimp + 2ce: 05013303 .4byte 0x5013303 + 2d2: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 2d6: 0000 unimp + 2d8: 0501 addi a0,a0,0 + 2da: 0616 slli a2,a2,0x5 + 2dc: 00090003 lb zero,0(s2) + 2e0: 0100 addi s0,sp,128 + 2e2: 0605 addi a2,a2,1 + 2e4: 00090003 lb zero,0(s2) + 2e8: 0100 addi s0,sp,128 + 2ea: 0105 addi sp,sp,1 + 2ec: 00090603 lb a2,0(s2) + 2f0: 0100 addi s0,sp,128 + 2f2: 0009 c.nop 2 + 2f4: 0000 unimp + 2f6: 0101 addi sp,sp,0 + 2f8: 2c05 jal 528 <__neorv32_rte_print_hex_word+0x34> + 2fa: 0500 addi s0,sp,640 + 2fc: 0002 c.slli64 zero + 2fe: 0000 unimp + 300: 0300 addi s0,sp,384 + 302: 00c5 addi ra,ra,17 + 304: 0501 addi a0,a0,0 + 306: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 30a: 0000 unimp + 30c: 0301 addi t1,t1,0 + 30e: 0905 addi s2,s2,1 + 310: 0000 unimp + 312: 0301 addi t1,t1,0 + 314: 0902 c.slli64 s2 + 316: 0000 unimp + 318: 0501 addi a0,a0,0 + 31a: 0619 addi a2,a2,6 + 31c: 00090003 lb zero,0(s2) + 320: 0100 addi s0,sp,128 + 322: 0305 addi t1,t1,1 + 324: 0306 slli t1,t1,0x1 + 326: 0901 addi s2,s2,0 + 328: 0000 unimp + 32a: 0501 addi a0,a0,0 + 32c: 0619 addi a2,a2,6 + 32e: 00090003 lb zero,0(s2) + 332: 0100 addi s0,sp,128 + 334: 0305 addi t1,t1,1 + 336: 0306 slli t1,t1,0x1 + 338: 0901 addi s2,s2,0 + 33a: 0000 unimp + 33c: 0501 addi a0,a0,0 + 33e: 0619 addi a2,a2,6 + 340: 00090003 lb zero,0(s2) + 344: 0100 addi s0,sp,128 + 346: 0305 addi t1,t1,1 + 348: 0306 slli t1,t1,0x1 + 34a: 0902 c.slli64 s2 + 34c: 0000 unimp + 34e: 0501 addi a0,a0,0 + 350: 0601 addi a2,a2,0 + 352: 00090103 lb sp,0(s2) + 356: 0100 addi s0,sp,128 + 358: 0009 c.nop 2 + 35a: 0000 unimp + 35c: 0101 addi sp,sp,0 + 35e: 2705 jal a7e <__neorv32_uart_touppercase.constprop.0+0x12> + 360: 0500 addi s0,sp,640 + 362: 9802 jalr a6 + 364: 0002 c.slli64 zero + 366: 0300 addi s0,sp,384 + 368: 00dd addi ra,ra,23 + 36a: 0501 addi a0,a0,0 + 36c: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 370: 0000 unimp + 372: 0301 addi t1,t1,0 + 374: 0905 addi s2,s2,1 + 376: 0000 unimp + 378: 0301 addi t1,t1,0 + 37a: 0901 addi s2,s2,0 + 37c: 0000 unimp + 37e: 0501 addi a0,a0,0 + 380: 0305 addi t1,t1,1 + 382: 0901 addi s2,s2,0 + 384: 0000 unimp + 386: 0501 addi a0,a0,0 + 388: 060a slli a2,a2,0x2 + 38a: 00090003 lb zero,0(s2) + 38e: 0100 addi s0,sp,128 + 390: 0505 addi a0,a0,1 + 392: 0306 slli t1,t1,0x1 + 394: 0901 addi s2,s2,0 + 396: 0004 .2byte 0x4 + 398: 0501 addi a0,a0,0 + 39a: 060a slli a2,a2,0x2 + 39c: 00090003 lb zero,0(s2) + 3a0: 0100 addi s0,sp,128 + 3a2: 0505 addi a0,a0,1 + 3a4: 0306 slli t1,t1,0x1 + 3a6: 0901 addi s2,s2,0 + 3a8: 0004 .2byte 0x4 + 3aa: 0501 addi a0,a0,0 + 3ac: 060a slli a2,a2,0x2 + 3ae: 00090003 lb zero,0(s2) + 3b2: 0100 addi s0,sp,128 + 3b4: 0505 addi a0,a0,1 + 3b6: 0306 slli t1,t1,0x1 + 3b8: 0901 addi s2,s2,0 + 3ba: 0004 .2byte 0x4 + 3bc: 0501 addi a0,a0,0 + 3be: 0608 addi a0,sp,768 + 3c0: 00090003 lb zero,0(s2) + 3c4: 0100 addi s0,sp,128 + 3c6: 0305 addi t1,t1,1 + 3c8: 0306 slli t1,t1,0x1 + 3ca: 0905 addi s2,s2,1 + 3cc: 0004 .2byte 0x4 + 3ce: 0301 addi t1,t1,0 + 3d0: 0901 addi s2,s2,0 + 3d2: 0000 unimp + 3d4: 0301 addi t1,t1,0 + 3d6: 0902 c.slli64 s2 + 3d8: 0000 unimp + 3da: 0501 addi a0,a0,0 + 3dc: 0601 addi a2,a2,0 + 3de: 00090103 lb sp,0(s2) + 3e2: 0100 addi s0,sp,128 + 3e4: 0409 addi s0,s0,2 + 3e6: 0000 unimp + 3e8: 0101 addi sp,sp,0 + 3ea: 3205 jal fffffd0a <__crt0_stack_begin+0x7fffdd0e> + 3ec: 0500 addi s0,sp,640 + 3ee: 0002 c.slli64 zero + 3f0: 0000 unimp + 3f2: 0300 addi s0,sp,384 + 3f4: 00fd addi ra,ra,31 + 3f6: 0501 addi a0,a0,0 + 3f8: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 3fc: 0000 unimp + 3fe: 0301 addi t1,t1,0 + 400: 0905 addi s2,s2,1 + 402: 0000 unimp + 404: 0301 addi t1,t1,0 + 406: 0902 c.slli64 s2 + 408: 0000 unimp + 40a: 0501 addi a0,a0,0 + 40c: 061c addi a5,sp,768 + 40e: 00090003 lb zero,0(s2) + 412: 0100 addi s0,sp,128 + 414: 0305 addi t1,t1,1 + 416: 0306 slli t1,t1,0x1 + 418: 0901 addi s2,s2,0 + 41a: 0000 unimp + 41c: 0501 addi a0,a0,0 + 41e: 061c addi a5,sp,768 + 420: 00090003 lb zero,0(s2) + 424: 0100 addi s0,sp,128 + 426: 0305 addi t1,t1,1 + 428: 0306 slli t1,t1,0x1 + 42a: 0901 addi s2,s2,0 + 42c: 0000 unimp + 42e: 0501 addi a0,a0,0 + 430: 061c addi a5,sp,768 + 432: 00090003 lb zero,0(s2) + 436: 0100 addi s0,sp,128 + 438: 0305 addi t1,t1,1 + 43a: 0306 slli t1,t1,0x1 + 43c: 0902 c.slli64 s2 + 43e: 0000 unimp + 440: 0501 addi a0,a0,0 + 442: 0601 addi a2,a2,0 + 444: 00090103 lb sp,0(s2) + 448: 0100 addi s0,sp,128 + 44a: 0009 c.nop 2 + 44c: 0000 unimp + 44e: 0101 addi sp,sp,0 + 450: 2a05 jal 580 <__neorv32_rte_debug_handler+0x1c> + 452: 0500 addi s0,sp,640 + 454: 0002 c.slli64 zero + 456: 0000 unimp + 458: 0300 addi s0,sp,384 + 45a: 05010193 addi gp,sp,80 + 45e: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 462: 0000 unimp + 464: 0301 addi t1,t1,0 + 466: 0905 addi s2,s2,1 + 468: 0000 unimp + 46a: 0501 addi a0,a0,0 + 46c: 00030623 sb zero,12(t1) + 470: 0009 c.nop 2 + 472: 0100 addi s0,sp,128 + 474: 0305 addi t1,t1,1 + 476: 0306 slli t1,t1,0x1 + 478: 0901 addi s2,s2,0 + 47a: 0000 unimp + 47c: 0501 addi a0,a0,0 + 47e: 00030623 sb zero,12(t1) + 482: 0009 c.nop 2 + 484: 0100 addi s0,sp,128 + 486: 0305 addi t1,t1,1 + 488: 0306 slli t1,t1,0x1 + 48a: 0902 c.slli64 s2 + 48c: 0000 unimp + 48e: 0501 addi a0,a0,0 + 490: 0601 addi a2,a2,0 + 492: 00090103 lb sp,0(s2) + 496: 0100 addi s0,sp,128 + 498: 0009 c.nop 2 + 49a: 0000 unimp + 49c: 0101 addi sp,sp,0 + 49e: 00001d5b .4byte 0x1d5b + 4a2: 0005 c.nop 1 + 4a4: 0004 .2byte 0x4 + 4a6: 005d c.nop 23 + 4a8: 0000 unimp + 4aa: 0101 addi sp,sp,0 + 4ac: fb01 bnez a4,3bc <__neorv32_rte_core+0x110> + 4ae: 0d0e slli s10,s10,0x3 + 4b0: 0100 addi s0,sp,128 + 4b2: 0101 addi sp,sp,0 + 4b4: 0001 nop + 4b6: 0000 unimp + 4b8: 0001 nop + 4ba: 0100 addi s0,sp,128 + 4bc: 0101 addi sp,sp,0 + 4be: 051f 0198 0000 .byte 0x1f, 0x05, 0x98, 0x01, 0x00, 0x00 + 4c4: 000001db .4byte 0x1db + 4c8: 01f2 slli gp,gp,0x1c + 4ca: 0000 unimp + 4cc: 003c addi a5,sp,8 + 4ce: 0000 unimp + 4d0: 0000006b .4byte 0x6b + 4d4: 0102 c.slli64 sp + 4d6: 021f 090f 0221 .byte 0x1f, 0x02, 0x0f, 0x09, 0x21, 0x02 + 4dc: 0000 unimp + 4de: 2101 jal 8de + 4e0: 0002 c.slli64 zero + 4e2: 0100 addi s0,sp,128 + 4e4: 0000022f .4byte 0x22f + 4e8: 0d02 c.slli64 s10 + 4ea: 0001 nop + 4ec: 0300 addi s0,sp,384 + 4ee: 011e slli sp,sp,0x7 + 4f0: 0000 unimp + 4f2: 3104 .2byte 0x3104 + 4f4: 0001 nop + 4f6: 0200 addi s0,sp,256 + 4f8: 00000153 .4byte 0x153 + 4fc: 3b02 .2byte 0x3b02 + 4fe: 0001 nop + 500: 0200 addi s0,sp,256 + 502: 023d addi tp,tp,15 # f + 504: 0000 unimp + 506: 0500 addi s0,sp,640 + 508: 0061 c.nop 24 + 50a: 0205 addi tp,tp,1 # 1 + 50c: 02ac addi a1,sp,328 + 50e: 0000 unimp + 510: 0100ff03 .4byte 0x100ff03 + 514: 0305 addi t1,t1,1 + 516: 00090203 lb tp,0(s2) + 51a: 0100 addi s0,sp,128 + 51c: 0204 addi s1,sp,256 + 51e: 0900d503 lhu a0,144(ra) + 522: 0000 unimp + 524: 0301 addi t1,t1,0 + 526: 0902 c.slli64 s2 + 528: 0000 unimp + 52a: 0401 addi s0,s0,0 + 52c: 0501 addi a0,a0,0 + 52e: 0661 addi a2,a2,24 + 530: 097fa703 lw a4,151(t6) + 534: 0000 unimp + 536: 0401 addi s0,s0,0 + 538: 0502 c.slli64 a0 + 53a: 00d90303 lb t1,13(s2) + 53e: 4809 li a6,2 + 540: 0100 addi s0,sp,128 + 542: 0306 slli t1,t1,0x1 + 544: 0902 c.slli64 s2 + 546: 0004 .2byte 0x4 + 548: 0401 addi s0,s0,0 + 54a: 0301 addi t1,t1,0 + 54c: 7faa .2byte 0x7faa + 54e: 0009 c.nop 2 + 550: 0100 addi s0,sp,128 + 552: 00090103 lb sp,0(s2) + 556: 0100 addi s0,sp,128 + 558: 2205 jal 678 <__neorv32_rte_debug_handler+0x114> + 55a: 4c091e03 lh t3,1216(s2) + 55e: 0100 addi s0,sp,128 + 560: 5a05 li s4,-31 + 562: 00090003 lb zero,0(s2) + 566: 0100 addi s0,sp,128 + 568: 0305 addi t1,t1,1 + 56a: 00090403 lb s0,0(s2) + 56e: 0100 addi s0,sp,128 + 570: 00090103 lb sp,0(s2) + 574: 0100 addi s0,sp,128 + 576: 00090103 lb sp,0(s2) + 57a: 0100 addi s0,sp,128 + 57c: 0405 addi s0,s0,1 + 57e: 0306 slli t1,t1,0x1 + 580: 0900 addi s0,sp,144 + 582: 0000 unimp + 584: 0501 addi a0,a0,0 + 586: 04030603 lb a2,64(t1) + 58a: 0409 addi s0,s0,2 + 58c: 0100 addi s0,sp,128 + 58e: 0605 addi a2,a2,1 + 590: 0306 slli t1,t1,0x1 + 592: 0900 addi s0,sp,144 + 594: 0000 unimp + 596: 0501 addi a0,a0,0 + 598: 0622 slli a2,a2,0x8 + 59a: 08095903 lhu s2,128(s2) + 59e: 0100 addi s0,sp,128 + 5a0: 6105 addi sp,sp,32 + 5a2: 00090003 lb zero,0(s2) + 5a6: 0100 addi s0,sp,128 + 5a8: 0305 addi t1,t1,1 + 5aa: 00092103 lw sp,0(s2) + 5ae: 0100 addi s0,sp,128 + 5b0: 00090103 lb sp,0(s2) + 5b4: 0100 addi s0,sp,128 + 5b6: 00090103 lb sp,0(s2) + 5ba: 0100 addi s0,sp,128 + 5bc: 0405 addi s0,s0,1 + 5be: 0306 slli t1,t1,0x1 + 5c0: 0900 addi s0,sp,144 + 5c2: 0000 unimp + 5c4: 0501 addi a0,a0,0 + 5c6: 04030603 lb a2,64(t1) + 5ca: 0c09 addi s8,s8,2 + 5cc: 0100 addi s0,sp,128 + 5ce: 0505 addi a0,a0,1 + 5d0: 00090203 lb tp,0(s2) + 5d4: 0100 addi s0,sp,128 + 5d6: 0204 addi s1,sp,256 + 5d8: 0305 addi t1,t1,1 + 5da: 00092703 lw a4,0(s2) + 5de: 0100 addi s0,sp,128 + 5e0: 00090203 lb tp,0(s2) + 5e4: 0100 addi s0,sp,128 + 5e6: 04090203 lb tp,64(s2) + 5ea: 0100 addi s0,sp,128 + 5ec: 0104 addi s1,sp,128 + 5ee: 0505 addi a0,a0,1 + 5f0: 00095803 lhu a6,0(s2) + 5f4: 0100 addi s0,sp,128 + 5f6: 0204 addi s1,sp,256 + 5f8: 0305 addi t1,t1,1 + 5fa: 00095e03 lhu t3,0(s2) + 5fe: 0100 addi s0,sp,128 + 600: 00090103 lb sp,0(s2) + 604: 0100 addi s0,sp,128 + 606: 00090203 lb tp,0(s2) + 60a: 0100 addi s0,sp,128 + 60c: 0c090203 lb tp,192(s2) + 610: 0100 addi s0,sp,128 + 612: 0104 addi s1,sp,128 + 614: 0505 addi a0,a0,1 + 616: 00091f03 lh t5,0(s2) + 61a: 0100 addi s0,sp,128 + 61c: 0e05 addi t3,t3,1 + 61e: 0306 slli t1,t1,0x1 + 620: 0900 addi s0,sp,144 + 622: 0000 unimp + 624: 0501 addi a0,a0,0 + 626: 0605 addi a2,a2,1 + 628: 04090103 lb sp,64(s2) + 62c: 0100 addi s0,sp,128 + 62e: 0204 addi s1,sp,256 + 630: 0305 addi t1,t1,1 + 632: 00092103 lw sp,0(s2) + 636: 0100 addi s0,sp,128 + 638: 00090203 lb tp,0(s2) + 63c: 0100 addi s0,sp,128 + 63e: 04090203 lb tp,64(s2) + 642: 0100 addi s0,sp,128 + 644: 0104 addi s1,sp,128 + 646: 2805 jal 676 <__neorv32_rte_debug_handler+0x112> + 648: 0306 slli t1,t1,0x1 + 64a: 0000095b .4byte 0x95b + 64e: 0501 addi a0,a0,0 + 650: 0308 addi a0,sp,384 + 652: 0900 addi s0,sp,144 + 654: 0004 .2byte 0x4 + 656: 0501 addi a0,a0,0 + 658: 01030607 .4byte 0x1030607 + 65c: 0409 addi s0,s0,2 + 65e: 0100 addi s0,sp,128 + 660: 0a05 addi s4,s4,1 + 662: 0306 slli t1,t1,0x1 + 664: 0900 addi s0,sp,144 + 666: 0000 unimp + 668: 0501 addi a0,a0,0 + 66a: 0609 addi a2,a2,2 + 66c: 0c090103 lb sp,192(s2) + 670: 0100 addi s0,sp,128 + 672: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 674: 0306 slli t1,t1,0x1 + 676: 0900 addi s0,sp,144 + 678: 0000 unimp + 67a: 0501 addi a0,a0,0 + 67c: 0605 addi a2,a2,1 + 67e: 04090503 lb a0,64(s2) + 682: 0100 addi s0,sp,128 + 684: 0204 addi s1,sp,256 + 686: 0305 addi t1,t1,1 + 688: 00092a03 lw s4,0(s2) + 68c: 0100 addi s0,sp,128 + 68e: 00090203 lb tp,0(s2) + 692: 0100 addi s0,sp,128 + 694: 0104 addi s1,sp,128 + 696: 0105 addi sp,sp,1 + 698: 0306 slli t1,t1,0x1 + 69a: 0956 slli s2,s2,0x15 + 69c: 0004 .2byte 0x4 + 69e: 0501 addi a0,a0,0 + 6a0: 0622 slli a2,a2,0x8 + 6a2: 04094903 lbu s2,64(s2) + 6a6: 0100 addi s0,sp,128 + 6a8: 5d05 li s10,-31 + 6aa: 00090003 lb zero,0(s2) + 6ae: 0100 addi s0,sp,128 + 6b0: 0305 addi t1,t1,1 + 6b2: 00092003 lw zero,0(s2) + 6b6: 0100 addi s0,sp,128 + 6b8: 00090103 lb sp,0(s2) + 6bc: 0100 addi s0,sp,128 + 6be: 00090103 lb sp,0(s2) + 6c2: 0100 addi s0,sp,128 + 6c4: 2e05 jal 9f4 <__neorv32_uart_itoa+0xcc> + 6c6: 0306 slli t1,t1,0x1 + 6c8: 095e slli s2,s2,0x17 + 6ca: 0000 unimp + 6cc: 0501 addi a0,a0,0 + 6ce: 0304 addi s1,sp,384 + 6d0: 0922 slli s2,s2,0x8 + 6d2: 0004 .2byte 0x4 + 6d4: 0501 addi a0,a0,0 + 6d6: 0622 slli a2,a2,0x8 + 6d8: 08095f03 lhu t5,128(s2) + 6dc: 0100 addi s0,sp,128 + 6de: 5e05 li t3,-31 + 6e0: 00090003 lb zero,0(s2) + 6e4: 0100 addi s0,sp,128 + 6e6: 0305 addi t1,t1,1 + 6e8: 00091f03 lh t5,0(s2) + 6ec: 0100 addi s0,sp,128 + 6ee: 00090103 lb sp,0(s2) + 6f2: 0100 addi s0,sp,128 + 6f4: 00090103 lb sp,0(s2) + 6f8: 0100 addi s0,sp,128 + 6fa: 2e05 jal a2a <__neorv32_uart_itoa+0x102> + 6fc: 0306 slli t1,t1,0x1 + 6fe: 095f 0000 0501 .byte 0x5f, 0x09, 0x00, 0x00, 0x01, 0x05 + 704: 0304 addi s1,sp,384 + 706: 0921 addi s2,s2,8 + 708: 0004 .2byte 0x4 + 70a: 0501 addi a0,a0,0 + 70c: 0622 slli a2,a2,0x8 + 70e: 08096003 .4byte 0x8096003 + 712: 0100 addi s0,sp,128 + 714: 5f05 li t5,-31 + 716: 00090003 lb zero,0(s2) + 71a: 0100 addi s0,sp,128 + 71c: 0305 addi t1,t1,1 + 71e: 00091e03 lh t3,0(s2) + 722: 0100 addi s0,sp,128 + 724: 00090103 lb sp,0(s2) + 728: 0100 addi s0,sp,128 + 72a: 00090103 lb sp,0(s2) + 72e: 0100 addi s0,sp,128 + 730: 2e05 jal a60 <__neorv32_uart_tohex+0x30> + 732: 0306 slli t1,t1,0x1 + 734: 0960 addi s0,sp,156 + 736: 0000 unimp + 738: 0501 addi a0,a0,0 + 73a: 0304 addi s1,sp,384 + 73c: 0920 addi s0,sp,152 + 73e: 0004 .2byte 0x4 + 740: 0501 addi a0,a0,0 + 742: 0622 slli a2,a2,0x8 + 744: 08096103 .4byte 0x8096103 + 748: 0100 addi s0,sp,128 + 74a: 6105 addi sp,sp,32 + 74c: 00090003 lb zero,0(s2) + 750: 0100 addi s0,sp,128 + 752: 0305 addi t1,t1,1 + 754: 00091d03 lh s10,0(s2) + 758: 0100 addi s0,sp,128 + 75a: 00090103 lb sp,0(s2) + 75e: 0100 addi s0,sp,128 + 760: 00090103 lb sp,0(s2) + 764: 0100 addi s0,sp,128 + 766: 2e05 jal a96 <__neorv32_uart_touppercase.constprop.0+0x2a> + 768: 0306 slli t1,t1,0x1 + 76a: 0961 addi s2,s2,24 + 76c: 0000 unimp + 76e: 0501 addi a0,a0,0 + 770: 0304 addi s1,sp,384 + 772: 091f 0004 0501 .byte 0x1f, 0x09, 0x04, 0x00, 0x01, 0x05 + 778: 0622 slli a2,a2,0x8 + 77a: 08096203 .4byte 0x8096203 + 77e: 0100 addi s0,sp,128 + 780: 5d05 li s10,-31 + 782: 00090003 lb zero,0(s2) + 786: 0100 addi s0,sp,128 + 788: 0305 addi t1,t1,1 + 78a: 00091c03 lh s8,0(s2) + 78e: 0100 addi s0,sp,128 + 790: 00090103 lb sp,0(s2) + 794: 0100 addi s0,sp,128 + 796: 00090103 lb sp,0(s2) + 79a: 0100 addi s0,sp,128 + 79c: 2e05 jal acc + 79e: 0306 slli t1,t1,0x1 + 7a0: 0962 slli s2,s2,0x18 + 7a2: 0000 unimp + 7a4: 0501 addi a0,a0,0 + 7a6: 0304 addi s1,sp,384 + 7a8: 091e slli s2,s2,0x7 + 7aa: 0004 .2byte 0x4 + 7ac: 0501 addi a0,a0,0 + 7ae: 0622 slli a2,a2,0x8 + 7b0: 08096303 .4byte 0x8096303 + 7b4: 0100 addi s0,sp,128 + 7b6: 6105 addi sp,sp,32 + 7b8: 00090003 lb zero,0(s2) + 7bc: 0100 addi s0,sp,128 + 7be: 0305 addi t1,t1,1 + 7c0: 00091b03 lh s6,0(s2) + 7c4: 0100 addi s0,sp,128 + 7c6: 00090103 lb sp,0(s2) + 7ca: 0100 addi s0,sp,128 + 7cc: 00090103 lb sp,0(s2) + 7d0: 0100 addi s0,sp,128 + 7d2: 2e05 jal b02 + 7d4: 0306 slli t1,t1,0x1 + 7d6: 00000963 beqz zero,7e8 <__neorv32_rte_debug_handler+0x284> + 7da: 0501 addi a0,a0,0 + 7dc: 0304 addi s1,sp,384 + 7de: 091d addi s2,s2,7 + 7e0: 0004 .2byte 0x4 + 7e2: 0501 addi a0,a0,0 + 7e4: 0622 slli a2,a2,0x8 + 7e6: 08096403 .4byte 0x8096403 + 7ea: 0100 addi s0,sp,128 + 7ec: 5d05 li s10,-31 + 7ee: 00090003 lb zero,0(s2) + 7f2: 0100 addi s0,sp,128 + 7f4: 0305 addi t1,t1,1 + 7f6: 00091a03 lh s4,0(s2) + 7fa: 0100 addi s0,sp,128 + 7fc: 00090103 lb sp,0(s2) + 800: 0100 addi s0,sp,128 + 802: 00090103 lb sp,0(s2) + 806: 0100 addi s0,sp,128 + 808: 2e05 jal b38 + 80a: 0306 slli t1,t1,0x1 + 80c: 0964 addi s1,sp,156 + 80e: 0000 unimp + 810: 0501 addi a0,a0,0 + 812: 0304 addi s1,sp,384 + 814: 091c addi a5,sp,144 + 816: 0004 .2byte 0x4 + 818: 0501 addi a0,a0,0 + 81a: 0622 slli a2,a2,0x8 + 81c: 08096503 .4byte 0x8096503 + 820: 0100 addi s0,sp,128 + 822: 5e05 li t3,-31 + 824: 00090003 lb zero,0(s2) + 828: 0100 addi s0,sp,128 + 82a: 0305 addi t1,t1,1 + 82c: 00091903 lh s2,0(s2) + 830: 0100 addi s0,sp,128 + 832: 00090103 lb sp,0(s2) + 836: 0100 addi s0,sp,128 + 838: 00090103 lb sp,0(s2) + 83c: 0100 addi s0,sp,128 + 83e: 2e05 jal b6e + 840: 0306 slli t1,t1,0x1 + 842: 0965 addi s2,s2,25 + 844: 0000 unimp + 846: 0501 addi a0,a0,0 + 848: 0304 addi s1,sp,384 + 84a: 0004091b .4byte 0x4091b + 84e: 0501 addi a0,a0,0 + 850: 0622 slli a2,a2,0x8 + 852: 08096603 .4byte 0x8096603 + 856: 0100 addi s0,sp,128 + 858: 5e05 li t3,-31 + 85a: 00090003 lb zero,0(s2) + 85e: 0100 addi s0,sp,128 + 860: 0305 addi t1,t1,1 + 862: 00091803 lh a6,0(s2) + 866: 0100 addi s0,sp,128 + 868: 00090103 lb sp,0(s2) + 86c: 0100 addi s0,sp,128 + 86e: 00090103 lb sp,0(s2) + 872: 0100 addi s0,sp,128 + 874: 2e05 jal ba4 + 876: 0306 slli t1,t1,0x1 + 878: 0966 slli s2,s2,0x19 + 87a: 0000 unimp + 87c: 0501 addi a0,a0,0 + 87e: 0304 addi s1,sp,384 + 880: 091a slli s2,s2,0x6 + 882: 0004 .2byte 0x4 + 884: 0501 addi a0,a0,0 + 886: 0622 slli a2,a2,0x8 + 888: 08096703 .4byte 0x8096703 + 88c: 0100 addi s0,sp,128 + 88e: 5805 li a6,-31 + 890: 00090003 lb zero,0(s2) + 894: 0100 addi s0,sp,128 + 896: 0305 addi t1,t1,1 + 898: 00091703 lh a4,0(s2) + 89c: 0100 addi s0,sp,128 + 89e: 00090103 lb sp,0(s2) + 8a2: 0100 addi s0,sp,128 + 8a4: 00090103 lb sp,0(s2) + 8a8: 0100 addi s0,sp,128 + 8aa: 2e05 jal bda + 8ac: 0306 slli t1,t1,0x1 + 8ae: 00000967 jalr s2,zero # 0 <__crt0_entry> + 8b2: 0501 addi a0,a0,0 + 8b4: 0304 addi s1,sp,384 + 8b6: 0919 addi s2,s2,6 + 8b8: 0004 .2byte 0x4 + 8ba: 0501 addi a0,a0,0 + 8bc: 04030603 lb a2,64(t1) + 8c0: 0809 addi a6,a6,2 + 8c2: 0100 addi s0,sp,128 + 8c4: 0105 addi sp,sp,1 + 8c6: 0306 slli t1,t1,0x1 + 8c8: 0911 addi s2,s2,4 + 8ca: 0000 unimp + 8cc: 0501 addi a0,a0,0 + 8ce: 0622 slli a2,a2,0x8 + 8d0: 4c095303 lhu t1,1216(s2) + 8d4: 0100 addi s0,sp,128 + 8d6: 5805 li a6,-31 + 8d8: 00090003 lb zero,0(s2) + 8dc: 0100 addi s0,sp,128 + 8de: 0305 addi t1,t1,1 + 8e0: 00091603 lh a2,0(s2) + 8e4: 0100 addi s0,sp,128 + 8e6: 00090103 lb sp,0(s2) + 8ea: 0100 addi s0,sp,128 + 8ec: 00090103 lb sp,0(s2) + 8f0: 0100 addi s0,sp,128 + 8f2: 2e05 jal c22 + 8f4: 0306 slli t1,t1,0x1 + 8f6: 0968 addi a0,sp,156 + 8f8: 0000 unimp + 8fa: 0501 addi a0,a0,0 + 8fc: 0304 addi s1,sp,384 + 8fe: 0918 addi a4,sp,144 + 900: 0004 .2byte 0x4 + 902: 0501 addi a0,a0,0 + 904: 0622 slli a2,a2,0x8 + 906: 08096903 .4byte 0x8096903 + 90a: 0100 addi s0,sp,128 + 90c: 5805 li a6,-31 + 90e: 00090003 lb zero,0(s2) + 912: 0100 addi s0,sp,128 + 914: 0305 addi t1,t1,1 + 916: 00091503 lh a0,0(s2) + 91a: 0100 addi s0,sp,128 + 91c: 00090103 lb sp,0(s2) + 920: 0100 addi s0,sp,128 + 922: 00090103 lb sp,0(s2) + 926: 0100 addi s0,sp,128 + 928: 2e05 jal c58 + 92a: 0306 slli t1,t1,0x1 + 92c: 0969 addi s2,s2,26 + 92e: 0000 unimp + 930: 0501 addi a0,a0,0 + 932: 0304 addi s1,sp,384 + 934: 00040917 auipc s2,0x40 + 938: 0501 addi a0,a0,0 + 93a: 0622 slli a2,a2,0x8 + 93c: 08096a03 .4byte 0x8096a03 + 940: 0100 addi s0,sp,128 + 942: 5b05 li s6,-31 + 944: 00090003 lb zero,0(s2) # 40934 <__neorv32_ram_size+0x3e934> + 948: 0100 addi s0,sp,128 + 94a: 0305 addi t1,t1,1 + 94c: 00091403 lh s0,0(s2) + 950: 0100 addi s0,sp,128 + 952: 00090103 lb sp,0(s2) + 956: 0100 addi s0,sp,128 + 958: 00090103 lb sp,0(s2) + 95c: 0100 addi s0,sp,128 + 95e: 2e05 jal c8e + 960: 0306 slli t1,t1,0x1 + 962: 096a slli s2,s2,0x1a + 964: 0000 unimp + 966: 0501 addi a0,a0,0 + 968: 0304 addi s1,sp,384 + 96a: 0916 slli s2,s2,0x5 + 96c: 0004 .2byte 0x4 + 96e: 0501 addi a0,a0,0 + 970: 0622 slli a2,a2,0x8 + 972: 08096b03 .4byte 0x8096b03 + 976: 0100 addi s0,sp,128 + 978: 5b05 li s6,-31 + 97a: 00090003 lb zero,0(s2) + 97e: 0100 addi s0,sp,128 + 980: 0305 addi t1,t1,1 + 982: 00091303 lh t1,0(s2) + 986: 0100 addi s0,sp,128 + 988: 00090103 lb sp,0(s2) + 98c: 0100 addi s0,sp,128 + 98e: 00090103 lb sp,0(s2) + 992: 0100 addi s0,sp,128 + 994: 2e05 jal cc4 + 996: 0306 slli t1,t1,0x1 + 998: 0000096b .4byte 0x96b + 99c: 0501 addi a0,a0,0 + 99e: 0304 addi s1,sp,384 + 9a0: 0915 addi s2,s2,5 + 9a2: 0000 unimp + 9a4: 0501 addi a0,a0,0 + 9a6: 0622 slli a2,a2,0x8 + 9a8: 08096c03 .4byte 0x8096c03 + 9ac: 0100 addi s0,sp,128 + 9ae: 5b05 li s6,-31 + 9b0: 00090003 lb zero,0(s2) + 9b4: 0100 addi s0,sp,128 + 9b6: 0305 addi t1,t1,1 + 9b8: 00091203 lh tp,0(s2) + 9bc: 0100 addi s0,sp,128 + 9be: 00090103 lb sp,0(s2) + 9c2: 0100 addi s0,sp,128 + 9c4: 00090103 lb sp,0(s2) + 9c8: 0100 addi s0,sp,128 + 9ca: 2e05 jal cfa + 9cc: 0306 slli t1,t1,0x1 + 9ce: 096c addi a1,sp,156 + 9d0: 0000 unimp + 9d2: 0501 addi a0,a0,0 + 9d4: 0304 addi s1,sp,384 + 9d6: 0914 addi a3,sp,144 + 9d8: 0000 unimp + 9da: 0501 addi a0,a0,0 + 9dc: 0622 slli a2,a2,0x8 + 9de: 08096d03 .4byte 0x8096d03 + 9e2: 0100 addi s0,sp,128 + 9e4: 5b05 li s6,-31 + 9e6: 00090003 lb zero,0(s2) + 9ea: 0100 addi s0,sp,128 + 9ec: 0305 addi t1,t1,1 + 9ee: 00091103 lh sp,0(s2) + 9f2: 0100 addi s0,sp,128 + 9f4: 00090103 lb sp,0(s2) + 9f8: 0100 addi s0,sp,128 + 9fa: 00090103 lb sp,0(s2) + 9fe: 0100 addi s0,sp,128 + a00: 2e05 jal d30 + a02: 0306 slli t1,t1,0x1 + a04: 096d addi s2,s2,27 + a06: 0000 unimp + a08: 0501 addi a0,a0,0 + a0a: 0304 addi s1,sp,384 + a0c: 00000913 li s2,0 + a10: 0501 addi a0,a0,0 + a12: 0622 slli a2,a2,0x8 + a14: 08096e03 .4byte 0x8096e03 + a18: 0100 addi s0,sp,128 + a1a: 5b05 li s6,-31 + a1c: 00090003 lb zero,0(s2) + a20: 0100 addi s0,sp,128 + a22: 0305 addi t1,t1,1 + a24: 00091003 lh zero,0(s2) + a28: 0100 addi s0,sp,128 + a2a: 00090103 lb sp,0(s2) + a2e: 0100 addi s0,sp,128 + a30: 00090103 lb sp,0(s2) + a34: 0100 addi s0,sp,128 + a36: 2e05 jal d66 + a38: 0306 slli t1,t1,0x1 + a3a: 096e slli s2,s2,0x1b + a3c: 0000 unimp + a3e: 0501 addi a0,a0,0 + a40: 0304 addi s1,sp,384 + a42: 0912 slli s2,s2,0x4 + a44: 0000 unimp + a46: 0501 addi a0,a0,0 + a48: 0622 slli a2,a2,0x8 + a4a: 08096f03 .4byte 0x8096f03 + a4e: 0100 addi s0,sp,128 + a50: 5b05 li s6,-31 + a52: 00090003 lb zero,0(s2) + a56: 0100 addi s0,sp,128 + a58: 0305 addi t1,t1,1 + a5a: 00090f03 lb t5,0(s2) + a5e: 0100 addi s0,sp,128 + a60: 00090103 lb sp,0(s2) + a64: 0100 addi s0,sp,128 + a66: 00090103 lb sp,0(s2) + a6a: 0100 addi s0,sp,128 + a6c: 2e05 jal d9c <_sbrk> + a6e: 0306 slli t1,t1,0x1 + a70: 0000096f jal s2,a70 <__neorv32_uart_touppercase.constprop.0+0x4> + a74: 0501 addi a0,a0,0 + a76: 0304 addi s1,sp,384 + a78: 0911 addi s2,s2,4 + a7a: 0000 unimp + a7c: 0501 addi a0,a0,0 + a7e: 0622 slli a2,a2,0x8 + a80: 08097003 .4byte 0x8097003 + a84: 0100 addi s0,sp,128 + a86: 5b05 li s6,-31 + a88: 00090003 lb zero,0(s2) + a8c: 0100 addi s0,sp,128 + a8e: 0305 addi t1,t1,1 + a90: 00090e03 lb t3,0(s2) + a94: 0100 addi s0,sp,128 + a96: 00090103 lb sp,0(s2) + a9a: 0100 addi s0,sp,128 + a9c: 00090103 lb sp,0(s2) + aa0: 0100 addi s0,sp,128 + aa2: 2e05 jal dd2 <_sbrk+0x36> + aa4: 0306 slli t1,t1,0x1 + aa6: 0970 addi a2,sp,156 + aa8: 0000 unimp + aaa: 0501 addi a0,a0,0 + aac: 0304 addi s1,sp,384 + aae: 0910 addi a2,sp,144 + ab0: 0000 unimp + ab2: 0501 addi a0,a0,0 + ab4: 0622 slli a2,a2,0x8 + ab6: 08097103 .4byte 0x8097103 + aba: 0100 addi s0,sp,128 + abc: 5b05 li s6,-31 + abe: 00090003 lb zero,0(s2) + ac2: 0100 addi s0,sp,128 + ac4: 0305 addi t1,t1,1 + ac6: 00090d03 lb s10,0(s2) + aca: 0100 addi s0,sp,128 + acc: 00090103 lb sp,0(s2) + ad0: 0100 addi s0,sp,128 + ad2: 00090103 lb sp,0(s2) + ad6: 0100 addi s0,sp,128 + ad8: 2e05 jal e08 <__umodsi3> + ada: 0306 slli t1,t1,0x1 + adc: 0971 addi s2,s2,28 + ade: 0000 unimp + ae0: 0501 addi a0,a0,0 + ae2: 0304 addi s1,sp,384 + ae4: 0000090f .4byte 0x90f + ae8: 0501 addi a0,a0,0 + aea: 0622 slli a2,a2,0x8 + aec: 08097203 .4byte 0x8097203 + af0: 0100 addi s0,sp,128 + af2: 5b05 li s6,-31 + af4: 00090003 lb zero,0(s2) + af8: 0100 addi s0,sp,128 + afa: 0305 addi t1,t1,1 + afc: 00090c03 lb s8,0(s2) + b00: 0100 addi s0,sp,128 + b02: 00090103 lb sp,0(s2) + b06: 0100 addi s0,sp,128 + b08: 00090103 lb sp,0(s2) + b0c: 0100 addi s0,sp,128 + b0e: 2e05 jal e3e <__modsi3+0x12> + b10: 0306 slli t1,t1,0x1 + b12: 0972 slli s2,s2,0x1c + b14: 0000 unimp + b16: 0501 addi a0,a0,0 + b18: 0304 addi s1,sp,384 + b1a: 090e slli s2,s2,0x3 + b1c: 0000 unimp + b1e: 0501 addi a0,a0,0 + b20: 0622 slli a2,a2,0x8 + b22: 08097303 .4byte 0x8097303 + b26: 0100 addi s0,sp,128 + b28: 5b05 li s6,-31 + b2a: 00090003 lb zero,0(s2) + b2e: 0100 addi s0,sp,128 + b30: 0305 addi t1,t1,1 + b32: 00090b03 lb s6,0(s2) + b36: 0100 addi s0,sp,128 + b38: 00090103 lb sp,0(s2) + b3c: 0100 addi s0,sp,128 + b3e: 00090103 lb sp,0(s2) + b42: 0100 addi s0,sp,128 + b44: 2e05 jal e74 <_malloc_r+0x16> + b46: 0306 slli t1,t1,0x1 + b48: 00000973 .4byte 0x973 + b4c: 0501 addi a0,a0,0 + b4e: 0304 addi s1,sp,384 + b50: 090d addi s2,s2,3 + b52: 0000 unimp + b54: 0501 addi a0,a0,0 + b56: 0622 slli a2,a2,0x8 + b58: 08097403 .4byte 0x8097403 + b5c: 0100 addi s0,sp,128 + b5e: 5c05 li s8,-31 + b60: 00090003 lb zero,0(s2) + b64: 0100 addi s0,sp,128 + b66: 0305 addi t1,t1,1 + b68: 00090a03 lb s4,0(s2) + b6c: 0100 addi s0,sp,128 + b6e: 00090103 lb sp,0(s2) + b72: 0100 addi s0,sp,128 + b74: 00090103 lb sp,0(s2) + b78: 0100 addi s0,sp,128 + b7a: 2e05 jal eaa <_malloc_r+0x4c> + b7c: 0306 slli t1,t1,0x1 + b7e: 0974 addi a3,sp,156 + b80: 0000 unimp + b82: 0501 addi a0,a0,0 + b84: 0304 addi s1,sp,384 + b86: 090c addi a1,sp,144 + b88: 0000 unimp + b8a: 0501 addi a0,a0,0 + b8c: 0622 slli a2,a2,0x8 + b8e: 08097503 .4byte 0x8097503 + b92: 0100 addi s0,sp,128 + b94: 5c05 li s8,-31 + b96: 00090003 lb zero,0(s2) + b9a: 0100 addi s0,sp,128 + b9c: 0305 addi t1,t1,1 + b9e: 00090903 lb s2,0(s2) + ba2: 0100 addi s0,sp,128 + ba4: 00090103 lb sp,0(s2) + ba8: 0100 addi s0,sp,128 + baa: 00090103 lb sp,0(s2) + bae: 0100 addi s0,sp,128 + bb0: 2e05 jal ee0 <_malloc_r+0x82> + bb2: 0306 slli t1,t1,0x1 + bb4: 0975 addi s2,s2,29 + bb6: 0000 unimp + bb8: 0501 addi a0,a0,0 + bba: 0304 addi s1,sp,384 + bbc: 0000090b .4byte 0x90b + bc0: 0501 addi a0,a0,0 + bc2: 0622 slli a2,a2,0x8 + bc4: 08097603 .4byte 0x8097603 + bc8: 0100 addi s0,sp,128 + bca: 5c05 li s8,-31 + bcc: 00090003 lb zero,0(s2) + bd0: 0100 addi s0,sp,128 + bd2: 0305 addi t1,t1,1 + bd4: 00090803 lb a6,0(s2) + bd8: 0100 addi s0,sp,128 + bda: 00090103 lb sp,0(s2) + bde: 0100 addi s0,sp,128 + be0: 00090103 lb sp,0(s2) + be4: 0100 addi s0,sp,128 + be6: 2e05 jal f16 <_malloc_r+0xb8> + be8: 0306 slli t1,t1,0x1 + bea: 0976 slli s2,s2,0x1d + bec: 0000 unimp + bee: 0501 addi a0,a0,0 + bf0: 0304 addi s1,sp,384 + bf2: 090a slli s2,s2,0x2 + bf4: 0000 unimp + bf6: 0501 addi a0,a0,0 + bf8: 0622 slli a2,a2,0x8 + bfa: 08097703 .4byte 0x8097703 + bfe: 0100 addi s0,sp,128 + c00: 5c05 li s8,-31 + c02: 00090003 lb zero,0(s2) + c06: 0100 addi s0,sp,128 + c08: 0305 addi t1,t1,1 + c0a: 00090703 lb a4,0(s2) + c0e: 0100 addi s0,sp,128 + c10: 00090103 lb sp,0(s2) + c14: 0100 addi s0,sp,128 + c16: 00090103 lb sp,0(s2) + c1a: 0100 addi s0,sp,128 + c1c: 2e05 jal f4c <_malloc_r+0xee> + c1e: 0306 slli t1,t1,0x1 + c20: 00000977 .4byte 0x977 + c24: 0501 addi a0,a0,0 + c26: 0304 addi s1,sp,384 + c28: 0909 addi s2,s2,2 + c2a: 0000 unimp + c2c: 0501 addi a0,a0,0 + c2e: 0622 slli a2,a2,0x8 + c30: 08097803 .4byte 0x8097803 + c34: 0100 addi s0,sp,128 + c36: 5c05 li s8,-31 + c38: 00090003 lb zero,0(s2) + c3c: 0100 addi s0,sp,128 + c3e: 0305 addi t1,t1,1 + c40: 00090603 lb a2,0(s2) + c44: 0100 addi s0,sp,128 + c46: 00090103 lb sp,0(s2) + c4a: 0100 addi s0,sp,128 + c4c: 00090103 lb sp,0(s2) + c50: 0100 addi s0,sp,128 + c52: 2e05 jal f82 <_malloc_r+0x124> + c54: 0306 slli t1,t1,0x1 + c56: 0978 addi a4,sp,156 + c58: 0000 unimp + c5a: 0501 addi a0,a0,0 + c5c: 0304 addi s1,sp,384 + c5e: 0908 addi a0,sp,144 + c60: 0000 unimp + c62: 0501 addi a0,a0,0 + c64: 0622 slli a2,a2,0x8 + c66: 08097903 .4byte 0x8097903 + c6a: 0100 addi s0,sp,128 + c6c: 5c05 li s8,-31 + c6e: 00090003 lb zero,0(s2) + c72: 0100 addi s0,sp,128 + c74: 0305 addi t1,t1,1 + c76: 00090503 lb a0,0(s2) + c7a: 0100 addi s0,sp,128 + c7c: 00090103 lb sp,0(s2) + c80: 0100 addi s0,sp,128 + c82: 00090103 lb sp,0(s2) + c86: 0100 addi s0,sp,128 + c88: 2e05 jal fb8 <_malloc_r+0x15a> + c8a: 0306 slli t1,t1,0x1 + c8c: 0979 addi s2,s2,30 + c8e: 0000 unimp + c90: 0501 addi a0,a0,0 + c92: 0304 addi s1,sp,384 + c94: 00000907 .4byte 0x907 + c98: 0901 addi s2,s2,0 + c9a: 0008 .2byte 0x8 + c9c: 0100 addi s0,sp,128 + c9e: 0501 addi a0,a0,0 + ca0: 0031 c.nop 12 + ca2: 0205 addi tp,tp,1 # 1 + ca4: 04f4 addi a3,sp,588 + ca6: 0000 unimp + ca8: 0104a703 lw a4,16(s1) + cac: 0305 addi t1,t1,1 + cae: 00090203 lb tp,0(s2) + cb2: 0100 addi s0,sp,128 + cb4: 00090203 lb tp,0(s2) + cb8: 0100 addi s0,sp,128 + cba: 3105 jal 8da + cbc: 0306 slli t1,t1,0x1 + cbe: 097c addi a5,sp,156 + cc0: 0000 unimp + cc2: 0501 addi a0,a0,0 + cc4: 09040303 lb t1,144(s0) + cc8: 000c .2byte 0xc + cca: 0501 addi a0,a0,0 + ccc: 0331 addi t1,t1,12 + cce: 097c addi a5,sp,156 + cd0: 0004 .2byte 0x4 + cd2: 0501 addi a0,a0,0 + cd4: 09040303 lb t1,144(s0) + cd8: 0004 .2byte 0x4 + cda: 0501 addi a0,a0,0 + cdc: 09050323 sb a6,134(a0) + ce0: 0004 .2byte 0x4 + ce2: 0501 addi a0,a0,0 + ce4: 0331 addi t1,t1,12 + ce6: 00040977 .4byte 0x40977 + cea: 0501 addi a0,a0,0 + cec: 09040303 lb t1,144(s0) + cf0: 000c .2byte 0xc + cf2: 0601 addi a2,a2,0 + cf4: 08090203 lb tp,128(s2) + cf8: 0100 addi s0,sp,128 + cfa: 00090103 lb sp,0(s2) + cfe: 0100 addi s0,sp,128 + d00: 0e05 addi t3,t3,1 + d02: 00090003 lb zero,0(s2) + d06: 0100 addi s0,sp,128 + d08: 2305 jal 1228 <_malloc_r+0x3ca> + d0a: 0306 slli t1,t1,0x1 + d0c: 0902 c.slli64 s2 + d0e: 0000 unimp + d10: 0501 addi a0,a0,0 + d12: 030e slli t1,t1,0x3 + d14: 097e slli s2,s2,0x1f + d16: 0004 .2byte 0x4 + d18: 0501 addi a0,a0,0 + d1a: 0005 c.nop 1 + d1c: 0402 c.slli64 s0 + d1e: 01030603 lb a2,16(t1) + d22: 0409 addi s0,s0,2 + d24: 0100 addi s0,sp,128 + d26: 0200 addi s0,sp,256 + d28: 0304 addi s1,sp,384 + d2a: 00090103 lb sp,0(s2) + d2e: 0100 addi s0,sp,128 + d30: 1b05 addi s6,s6,-31 + d32: 0200 addi s0,sp,256 + d34: 0304 addi s1,sp,384 + d36: 0306 slli t1,t1,0x1 + d38: 097f .2byte 0x97f + d3a: 0000 unimp + d3c: 0501 addi a0,a0,0 + d3e: 000e c.slli zero,0x3 + d40: 0402 c.slli64 s0 + d42: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + d46: 0004 .2byte 0x4 + d48: 0501 addi a0,a0,0 + d4a: 04020023 sb zero,64(tp) # 40 + d4e: 09010303 lb t1,144(sp) + d52: 0004 .2byte 0x4 + d54: 0501 addi a0,a0,0 + d56: 0005 c.nop 1 + d58: 0402 c.slli64 s0 + d5a: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + d5e: 0004 .2byte 0x4 + d60: 0501 addi a0,a0,0 + d62: 000e c.slli zero,0x3 + d64: 0402 c.slli64 s0 + d66: 097e0303 lb t1,151(t3) + d6a: 0004 .2byte 0x4 + d6c: 0501 addi a0,a0,0 + d6e: 0005 c.nop 1 + d70: 0402 c.slli64 s0 + d72: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + d76: 0004 .2byte 0x4 + d78: 0501 addi a0,a0,0 + d7a: 04020013 addi zero,tp,64 # 40 + d7e: 7e030603 lb a2,2016(t1) + d82: 0409 addi s0,s0,2 + d84: 0100 addi s0,sp,128 + d86: 0e05 addi t3,t3,1 + d88: 0200 addi s0,sp,256 + d8a: 0304 addi s1,sp,384 + d8c: 00090003 lb zero,0(s2) + d90: 0100 addi s0,sp,128 + d92: 0105 addi sp,sp,1 + d94: 0306 slli t1,t1,0x1 + d96: 0904 addi s1,sp,144 + d98: 0004 .2byte 0x4 + d9a: 0901 addi s2,s2,0 + d9c: 001c .2byte 0x1c + d9e: 0100 addi s0,sp,128 + da0: 0501 addi a0,a0,0 + da2: 0035 c.nop 13 + da4: 0205 addi tp,tp,1 # 1 + da6: 0000 unimp + da8: 0000 unimp + daa: 01049403 lh s0,16(s1) + dae: 0305 addi t1,t1,1 + db0: 00090203 lb tp,0(s2) + db4: 0100 addi s0,sp,128 + db6: 3505 jal bd6 + db8: 0306 slli t1,t1,0x1 + dba: 097e slli s2,s2,0x1f + dbc: 0000 unimp + dbe: 0501 addi a0,a0,0 + dc0: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + dc4: 0000 unimp + dc6: 0501 addi a0,a0,0 + dc8: 0335 addi t1,t1,13 + dca: 097e slli s2,s2,0x1f + dcc: 0000 unimp + dce: 0501 addi a0,a0,0 + dd0: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + dd4: 0000 unimp + dd6: 0601 addi a2,a2,0 + dd8: 00090103 lb sp,0(s2) + ddc: 0100 addi s0,sp,128 + dde: 0505 addi a0,a0,1 + de0: 0306 slli t1,t1,0x1 + de2: 0901 addi s2,s2,0 + de4: 0000 unimp + de6: 0501 addi a0,a0,0 + de8: 0306 slli t1,t1,0x1 + dea: 097f .2byte 0x97f + dec: 0000 unimp + dee: 0501 addi a0,a0,0 + df0: 0605 addi a2,a2,1 + df2: 00090403 lb s0,0(s2) + df6: 0100 addi s0,sp,128 + df8: 0305 addi t1,t1,1 + dfa: 00090203 lb tp,0(s2) + dfe: 0100 addi s0,sp,128 + e00: 0105 addi sp,sp,1 + e02: 0306 slli t1,t1,0x1 + e04: 0901 addi s2,s2,0 + e06: 0000 unimp + e08: 0501 addi a0,a0,0 + e0a: 097f0303 lb t1,151(t5) + e0e: 0000 unimp + e10: 0501 addi a0,a0,0 + e12: 0301 addi t1,t1,0 + e14: 0901 addi s2,s2,0 + e16: 0000 unimp + e18: 0501 addi a0,a0,0 + e1a: 097f0303 lb t1,151(t5) + e1e: 0000 unimp + e20: 0901 addi s2,s2,0 + e22: 0000 unimp + e24: 0100 addi s0,sp,128 + e26: 0501 addi a0,a0,0 + e28: 02050037 lui zero,0x2050 + e2c: 0000 unimp + e2e: 0000 unimp + e30: 01048303 lb t1,16(s1) + e34: 0305 addi t1,t1,1 + e36: 00090203 lb tp,0(s2) + e3a: 0100 addi s0,sp,128 + e3c: 0605 addi a2,a2,1 + e3e: 0306 slli t1,t1,0x1 + e40: 0900 addi s0,sp,144 + e42: 0000 unimp + e44: 0501 addi a0,a0,0 + e46: 0605 addi a2,a2,1 + e48: 00090103 lb sp,0(s2) + e4c: 0100 addi s0,sp,128 + e4e: 0306 slli t1,t1,0x1 + e50: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + e54: 0601 addi a2,a2,0 + e56: 00090003 lb zero,0(s2) + e5a: 0100 addi s0,sp,128 + e5c: 0009 c.nop 2 + e5e: 0000 unimp + e60: 0101 addi sp,sp,0 + e62: 2f05 jal 1592 <_free_r+0xa2> + e64: 0500 addi s0,sp,640 + e66: 6402 .2byte 0x6402 + e68: 0005 c.nop 1 + e6a: 0300 addi s0,sp,384 + e6c: 01c5 addi gp,gp,17 # 35b3 <__neorv32_ram_size+0x15b3> + e6e: 0501 addi a0,a0,0 + e70: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + e74: 0000 unimp + e76: 0501 addi a0,a0,0 + e78: 7e03062f .4byte 0x7e03062f + e7c: 0009 c.nop 2 + e7e: 0100 addi s0,sp,128 + e80: 0705 addi a4,a4,1 + e82: 18090203 lb tp,384(s2) + e86: 0100 addi s0,sp,128 + e88: 0605 addi a2,a2,1 + e8a: 04090003 lb zero,64(s2) + e8e: 0100 addi s0,sp,128 + e90: 0305 addi t1,t1,1 + e92: 0306 slli t1,t1,0x1 + e94: 0905 addi s2,s2,1 + e96: 0004 .2byte 0x4 + e98: 0301 addi t1,t1,0 + e9a: 000c0903 lb s2,0(s8) + e9e: 0401 addi s0,s0,0 + ea0: 0302 c.slli64 t1 + ea2: 00000907 .4byte 0x907 + ea6: 0301 addi t1,t1,0 + ea8: 0902 c.slli64 s2 + eaa: 0000 unimp + eac: 0301 addi t1,t1,0 + eae: 0902 c.slli64 s2 + eb0: 0004 .2byte 0x4 + eb2: 0401 addi s0,s0,0 + eb4: 0301 addi t1,t1,0 + eb6: 0976 slli s2,s2,0x1d + eb8: 0000 unimp + eba: 0501 addi a0,a0,0 + ebc: 0322 slli t1,t1,0x8 + ebe: 091e slli s2,s2,0x7 + ec0: 0044 addi s1,sp,4 + ec2: 0501 addi a0,a0,0 + ec4: 034e slli t1,t1,0x13 + ec6: 0900 addi s0,sp,144 + ec8: 000c .2byte 0xc + eca: 0501 addi a0,a0,0 + ecc: 0378 addi a4,sp,396 + ece: 0900 addi s0,sp,144 + ed0: 0008 .2byte 0x8 + ed2: 0501 addi a0,a0,0 + ed4: 09040303 lb t1,144(s0) + ed8: 0000 unimp + eda: 0301 addi t1,t1,0 + edc: 0910 addi a2,sp,144 + ede: 0000 unimp + ee0: 0301 addi t1,t1,0 + ee2: 0901 addi s2,s2,0 + ee4: 0008 .2byte 0x8 + ee6: 0401 addi s0,s0,0 + ee8: 0302 c.slli64 t1 + eea: 00000953 .4byte 0x953 + eee: 0301 addi t1,t1,0 + ef0: 0902 c.slli64 s2 + ef2: 0000 unimp + ef4: 0301 addi t1,t1,0 + ef6: 0902 c.slli64 s2 + ef8: 0004 .2byte 0x4 + efa: 0401 addi s0,s0,0 + efc: 0301 addi t1,t1,0 + efe: 092a slli s2,s2,0xa + f00: 0000 unimp + f02: 0301 addi t1,t1,0 + f04: 00080903 lb s2,0(a6) + f08: 0501 addi a0,a0,0 + f0a: 0606 slli a2,a2,0x1 + f0c: 00090003 lb zero,0(s2) + f10: 0100 addi s0,sp,128 + f12: 0305 addi t1,t1,1 + f14: 0c094903 lbu s2,192(s2) + f18: 0100 addi s0,sp,128 + f1a: 2205 jal 103a <_malloc_r+0x1dc> + f1c: 0306 slli t1,t1,0x1 + f1e: 091d addi s2,s2,7 + f20: 0010 .2byte 0x10 + f22: 0501 addi a0,a0,0 + f24: 09000343 .4byte 0x9000343 + f28: 000c .2byte 0xc + f2a: 0501 addi a0,a0,0 + f2c: 09000373 .4byte 0x9000373 + f30: 0008 .2byte 0x8 + f32: 0501 addi a0,a0,0 + f34: 09050303 lb t1,144(a0) + f38: 0000 unimp + f3a: 0301 addi t1,t1,0 + f3c: 0910 addi a2,sp,144 + f3e: 0000 unimp + f40: 0301 addi t1,t1,0 + f42: 0901 addi s2,s2,0 + f44: 0008 .2byte 0x8 + f46: 0401 addi s0,s0,0 + f48: 0302 c.slli64 t1 + f4a: 00000953 .4byte 0x953 + f4e: 0301 addi t1,t1,0 + f50: 0902 c.slli64 s2 + f52: 0000 unimp + f54: 0301 addi t1,t1,0 + f56: 0902 c.slli64 s2 + f58: 0004 .2byte 0x4 + f5a: 0401 addi s0,s0,0 + f5c: 0301 addi t1,t1,0 + f5e: 092a slli s2,s2,0xa + f60: 0000 unimp + f62: 0301 addi t1,t1,0 + f64: 00040903 lb s2,0(s0) + f68: 0501 addi a0,a0,0 + f6a: 0308 addi a0,sp,384 + f6c: 0000090b .4byte 0x90b + f70: 0501 addi a0,a0,0 + f72: 0003060b .4byte 0x3060b + f76: 0009 c.nop 2 + f78: 0100 addi s0,sp,128 + f7a: 2205 jal 109a <_malloc_r+0x23c> + f7c: 0306 slli t1,t1,0x1 + f7e: 08097fbf 03060100 .8byte 0x306010008097fbf + f86: 0906 slli s2,s2,0x1 + f88: 0008 .2byte 0x8 + f8a: 0501 addi a0,a0,0 + f8c: 0652 slli a2,a2,0x14 + f8e: 04090003 lb zero,64(s2) + f92: 0100 addi s0,sp,128 + f94: 0305 addi t1,t1,1 + f96: 00091b03 lh s6,0(s2) + f9a: 0100 addi s0,sp,128 + f9c: 00091003 lh zero,0(s2) + fa0: 0100 addi s0,sp,128 + fa2: 08090103 lb sp,128(s2) + fa6: 0100 addi s0,sp,128 + fa8: 0204 addi s1,sp,256 + faa: 00095303 lhu t1,0(s2) + fae: 0100 addi s0,sp,128 + fb0: 00090203 lb tp,0(s2) + fb4: 0100 addi s0,sp,128 + fb6: 04090203 lb tp,64(s2) + fba: 0100 addi s0,sp,128 + fbc: 0104 addi s1,sp,128 + fbe: 00092a03 lw s4,0(s2) + fc2: 0100 addi s0,sp,128 + fc4: 04090303 lb t1,64(s2) + fc8: 0100 addi s0,sp,128 + fca: 0805 addi a6,a6,1 + fcc: 00090b03 lb s6,0(s2) + fd0: 0100 addi s0,sp,128 + fd2: 0505 addi a0,a0,1 + fd4: 00090103 lb sp,0(s2) + fd8: 0100 addi s0,sp,128 + fda: 0c090103 lb sp,192(s2) + fde: 0100 addi s0,sp,128 + fe0: 0204 addi s1,sp,256 + fe2: 0305 addi t1,t1,1 + fe4: 00094203 lbu tp,0(s2) + fe8: 0100 addi s0,sp,128 + fea: 00090203 lb tp,0(s2) + fee: 0100 addi s0,sp,128 + ff0: 0104 addi s1,sp,128 + ff2: 2205 jal 1112 <_malloc_r+0x2b4> + ff4: 08097a03 .4byte 0x8097a03 + ff8: 0100 addi s0,sp,128 + ffa: 0306 slli t1,t1,0x1 + ffc: 0906 slli s2,s2,0x1 + ffe: 0008 .2byte 0x8 + 1000: 0501 addi a0,a0,0 + 1002: 064c addi a1,sp,772 + 1004: 04090003 lb zero,64(s2) + 1008: 0100 addi s0,sp,128 + 100a: 0305 addi t1,t1,1 + 100c: 00091a03 lh s4,0(s2) + 1010: 0100 addi s0,sp,128 + 1012: 0505 addi a0,a0,1 + 1014: 00090103 lb sp,0(s2) + 1018: 0100 addi s0,sp,128 + 101a: 0e05 addi t3,t3,1 + 101c: 0306 slli t1,t1,0x1 + 101e: 0900 addi s0,sp,144 + 1020: 0000 unimp + 1022: 0501 addi a0,a0,0 + 1024: 0605 addi a2,a2,1 + 1026: 04090103 lb sp,64(s2) + 102a: 0100 addi s0,sp,128 + 102c: 0805 addi a6,a6,1 + 102e: 0306 slli t1,t1,0x1 + 1030: 0900 addi s0,sp,144 + 1032: 0000 unimp + 1034: 0501 addi a0,a0,0 + 1036: 01030607 .4byte 0x1030607 + 103a: 0409 addi s0,s0,2 + 103c: 0100 addi s0,sp,128 + 103e: 1305 addi t1,t1,-31 + 1040: 0306 slli t1,t1,0x1 + 1042: 0900 addi s0,sp,144 + 1044: 0000 unimp + 1046: 0501 addi a0,a0,0 + 1048: 030a slli t1,t1,0x2 + 104a: 0900 addi s0,sp,144 + 104c: 0004 .2byte 0x4 + 104e: 0501 addi a0,a0,0 + 1050: 0609 addi a2,a2,2 + 1052: 04090103 lb sp,64(s2) + 1056: 0100 addi s0,sp,128 + 1058: 0705 addi a4,a4,1 + 105a: 0306 slli t1,t1,0x1 + 105c: 00080907 .4byte 0x80907 + 1060: 0501 addi a0,a0,0 + 1062: 05030603 lb a2,80(t1) + 1066: 0409 addi s0,s0,2 + 1068: 0100 addi s0,sp,128 + 106a: 08090103 lb sp,128(s2) + 106e: 0100 addi s0,sp,128 + 1070: 0204 addi s1,sp,256 + 1072: 00095303 lhu t1,0(s2) + 1076: 0100 addi s0,sp,128 + 1078: 00090203 lb tp,0(s2) + 107c: 0100 addi s0,sp,128 + 107e: 04090203 lb tp,64(s2) + 1082: 0100 addi s0,sp,128 + 1084: 0104 addi s1,sp,128 + 1086: 00092a03 lw s4,0(s2) + 108a: 0100 addi s0,sp,128 + 108c: 08090303 lb t1,128(s2) + 1090: 0100 addi s0,sp,128 + 1092: 0605 addi a2,a2,1 + 1094: 0306 slli t1,t1,0x1 + 1096: 0900 addi s0,sp,144 + 1098: 0000 unimp + 109a: 0501 addi a0,a0,0 + 109c: 0622 slli a2,a2,0x8 + 109e: 0c094c03 lbu s8,192(s2) + 10a2: 0100 addi s0,sp,128 + 10a4: 4d05 li s10,1 + 10a6: 0c090003 lb zero,192(s2) + 10aa: 0100 addi s0,sp,128 + 10ac: 0305 addi t1,t1,1 + 10ae: 00091f03 lh t5,0(s2) + 10b2: 0100 addi s0,sp,128 + 10b4: 00091003 lh zero,0(s2) + 10b8: 0100 addi s0,sp,128 + 10ba: 08090103 lb sp,128(s2) + 10be: 0100 addi s0,sp,128 + 10c0: 0204 addi s1,sp,256 + 10c2: 00095303 lhu t1,0(s2) + 10c6: 0100 addi s0,sp,128 + 10c8: 00090203 lb tp,0(s2) + 10cc: 0100 addi s0,sp,128 + 10ce: 04090203 lb tp,64(s2) + 10d2: 0100 addi s0,sp,128 + 10d4: 0104 addi s1,sp,128 + 10d6: 00092a03 lw s4,0(s2) + 10da: 0100 addi s0,sp,128 + 10dc: 08090303 lb t1,128(s2) + 10e0: 0100 addi s0,sp,128 + 10e2: 0505 addi a0,a0,1 + 10e4: 00090103 lb sp,0(s2) + 10e8: 0100 addi s0,sp,128 + 10ea: 0c090103 lb sp,192(s2) + 10ee: 0100 addi s0,sp,128 + 10f0: 0204 addi s1,sp,256 + 10f2: 0305 addi t1,t1,1 + 10f4: 097f8703 lb a4,151(t6) + 10f8: 0000 unimp + 10fa: 0301 addi t1,t1,0 + 10fc: 0901 addi s2,s2,0 + 10fe: 0000 unimp + 1100: 0301 addi t1,t1,0 + 1102: 0902 c.slli64 s2 + 1104: 0000 unimp + 1106: 0301 addi t1,t1,0 + 1108: 0902 c.slli64 s2 + 110a: 000c .2byte 0xc + 110c: 0401 addi s0,s0,0 + 110e: 0501 addi a0,a0,0 + 1110: 0305 addi t1,t1,1 + 1112: 00f5 addi ra,ra,29 + 1114: 0009 c.nop 2 + 1116: 0100 addi s0,sp,128 + 1118: 0204 addi s1,sp,256 + 111a: 0305 addi t1,t1,1 + 111c: 097f8603 lb a2,151(t6) + 1120: 0000 unimp + 1122: 0301 addi t1,t1,0 + 1124: 0901 addi s2,s2,0 + 1126: 0000 unimp + 1128: 0301 addi t1,t1,0 + 112a: 0902 c.slli64 s2 + 112c: 0000 unimp + 112e: 0401 addi s0,s0,0 + 1130: 0501 addi a0,a0,0 + 1132: f7030623 sb a6,-148(t1) + 1136: 0900 addi s0,sp,144 + 1138: 0000 unimp + 113a: 0401 addi s0,s0,0 + 113c: 0502 c.slli64 a0 + 113e: 7f890303 lb t1,2040(s2) + 1142: 0409 addi s0,s0,2 + 1144: 0100 addi s0,sp,128 + 1146: 0104 addi s1,sp,128 + 1148: 0805 addi a6,a6,1 + 114a: 0900f803 .4byte 0x900f803 + 114e: 0004 .2byte 0x4 + 1150: 0401 addi s0,s0,0 + 1152: 0502 c.slli64 a0 + 1154: 7f880303 lb t1,2040(a6) + 1158: 0409 addi s0,s0,2 + 115a: 0100 addi s0,sp,128 + 115c: 0104 addi s1,sp,128 + 115e: 0805 addi a6,a6,1 + 1160: 0900f803 .4byte 0x900f803 + 1164: 0004 .2byte 0x4 + 1166: 0401 addi s0,s0,0 + 1168: 0502 c.slli64 a0 + 116a: 7f880303 lb t1,2040(a6) + 116e: 0409 addi s0,s0,2 + 1170: 0100 addi s0,sp,128 + 1172: 0306 slli t1,t1,0x1 + 1174: 0902 c.slli64 s2 + 1176: 0004 .2byte 0x4 + 1178: 0401 addi s0,s0,0 + 117a: 0501 addi a0,a0,0 + 117c: 0305 addi t1,t1,1 + 117e: 00f6 slli ra,ra,0x1d + 1180: 0009 c.nop 2 + 1182: 0100 addi s0,sp,128 + 1184: 0805 addi a6,a6,1 + 1186: 0306 slli t1,t1,0x1 + 1188: 0900 addi s0,sp,144 + 118a: 0000 unimp + 118c: 0501 addi a0,a0,0 + 118e: 01030607 .4byte 0x1030607 + 1192: 0409 addi s0,s0,2 + 1194: 0100 addi s0,sp,128 + 1196: 0305 addi t1,t1,1 + 1198: 0902b103 .4byte 0x902b103 + 119c: 0000 unimp + 119e: 0301 addi t1,t1,0 + 11a0: 0902 c.slli64 s2 + 11a2: 0000 unimp + 11a4: 0501 addi a0,a0,0 + 11a6: 05030623 sb a6,76(t1) + 11aa: 0809 addi a6,a6,2 + 11ac: 0100 addi s0,sp,128 + 11ae: 0305 addi t1,t1,1 + 11b0: 04097b03 .4byte 0x4097b03 + 11b4: 0100 addi s0,sp,128 + 11b6: 0306 slli t1,t1,0x1 + 11b8: 0902 c.slli64 s2 + 11ba: 0004 .2byte 0x4 + 11bc: 0301 addi t1,t1,0 + 11be: 0901 addi s2,s2,0 + 11c0: 0000 unimp + 11c2: 0501 addi a0,a0,0 + 11c4: 030e slli t1,t1,0x3 + 11c6: 0900 addi s0,sp,144 + 11c8: 0000 unimp + 11ca: 0501 addi a0,a0,0 + 11cc: 7d030603 lb a2,2000(t1) + 11d0: 0009 c.nop 2 + 11d2: 0100 addi s0,sp,128 + 11d4: 2305 jal 16f4 <_free_r+0x204> + 11d6: 04090503 lb a0,64(s2) + 11da: 0100 addi s0,sp,128 + 11dc: 0e05 addi t3,t3,1 + 11de: 04097e03 .4byte 0x4097e03 + 11e2: 0100 addi s0,sp,128 + 11e4: 0505 addi a0,a0,1 + 11e6: 0306 slli t1,t1,0x1 + 11e8: 0901 addi s2,s2,0 + 11ea: 0004 .2byte 0x4 + 11ec: 0301 addi t1,t1,0 + 11ee: 0901 addi s2,s2,0 + 11f0: 0000 unimp + 11f2: 0501 addi a0,a0,0 + 11f4: 7f03061b .4byte 0x7f03061b + 11f8: 0009 c.nop 2 + 11fa: 0100 addi s0,sp,128 + 11fc: 0e05 addi t3,t3,1 + 11fe: 04090003 lb zero,64(s2) + 1202: 0100 addi s0,sp,128 + 1204: 2305 jal 1724 <__fini_array_end+0x4> + 1206: 04090103 lb sp,64(s2) + 120a: 0100 addi s0,sp,128 + 120c: 0505 addi a0,a0,1 + 120e: 04090003 lb zero,64(s2) + 1212: 0100 addi s0,sp,128 + 1214: 0e05 addi t3,t3,1 + 1216: 04097e03 .4byte 0x4097e03 + 121a: 0100 addi s0,sp,128 + 121c: 0505 addi a0,a0,1 + 121e: 04090203 lb tp,64(s2) + 1222: 0100 addi s0,sp,128 + 1224: 1305 addi t1,t1,-31 + 1226: 0306 slli t1,t1,0x1 + 1228: 097e slli s2,s2,0x1f + 122a: 0004 .2byte 0x4 + 122c: 0501 addi a0,a0,0 + 122e: 030e slli t1,t1,0x3 + 1230: 0900 addi s0,sp,144 + 1232: 0000 unimp + 1234: 0501 addi a0,a0,0 + 1236: 7dd60303 lb t1,2013(a2) + 123a: 0409 addi s0,s0,2 + 123c: 0100 addi s0,sp,128 + 123e: 0105 addi sp,sp,1 + 1240: 0306 slli t1,t1,0x1 + 1242: 0901 addi s2,s2,0 + 1244: 0000 unimp + 1246: 0501 addi a0,a0,0 + 1248: 097f0303 lb t1,151(t5) + 124c: 0014 .2byte 0x14 + 124e: 0501 addi a0,a0,0 + 1250: 0301 addi t1,t1,0 + 1252: 0901 addi s2,s2,0 + 1254: 0004 .2byte 0x4 + 1256: 0501 addi a0,a0,0 + 1258: 097f0303 lb t1,151(t5) + 125c: 0000 unimp + 125e: 0501 addi a0,a0,0 + 1260: 0301 addi t1,t1,0 + 1262: 0901 addi s2,s2,0 + 1264: 0004 .2byte 0x4 + 1266: 0501 addi a0,a0,0 + 1268: 097f0303 lb t1,151(t5) + 126c: 0004 .2byte 0x4 + 126e: 0501 addi a0,a0,0 + 1270: 0622 slli a2,a2,0x8 + 1272: 097fbc03 .4byte 0x97fbc03 + 1276: 0004 .2byte 0x4 + 1278: 0301 addi t1,t1,0 + 127a: 0901 addi s2,s2,0 + 127c: 000c .2byte 0xc + 127e: 0301 addi t1,t1,0 + 1280: 0901 addi s2,s2,0 + 1282: 000c .2byte 0xc + 1284: 0301 addi t1,t1,0 + 1286: 0901 addi s2,s2,0 + 1288: 000c .2byte 0xc + 128a: 0301 addi t1,t1,0 + 128c: 0901 addi s2,s2,0 + 128e: 000c .2byte 0xc + 1290: 0301 addi t1,t1,0 + 1292: 0901 addi s2,s2,0 + 1294: 000c .2byte 0xc + 1296: 0301 addi t1,t1,0 + 1298: 0901 addi s2,s2,0 + 129a: 000c .2byte 0xc + 129c: 0301 addi t1,t1,0 + 129e: 0901 addi s2,s2,0 + 12a0: 000c .2byte 0xc + 12a2: 0601 addi a2,a2,0 + 12a4: 08090203 lb tp,128(s2) + 12a8: 0100 addi s0,sp,128 + 12aa: 4e05 li t3,1 + 12ac: 0306 slli t1,t1,0x1 + 12ae: 0900 addi s0,sp,144 + 12b0: 0004 .2byte 0x4 + 12b2: 0501 addi a0,a0,0 + 12b4: 09150303 lb t1,145(a0) + 12b8: 0000 unimp + 12ba: 0301 addi t1,t1,0 + 12bc: 0910 addi a2,sp,144 + 12be: 0000 unimp + 12c0: 0301 addi t1,t1,0 + 12c2: 0901 addi s2,s2,0 + 12c4: 0008 .2byte 0x8 + 12c6: 0401 addi s0,s0,0 + 12c8: 0302 c.slli64 t1 + 12ca: 00000953 .4byte 0x953 + 12ce: 0301 addi t1,t1,0 + 12d0: 0902 c.slli64 s2 + 12d2: 0000 unimp + 12d4: 0301 addi t1,t1,0 + 12d6: 0902 c.slli64 s2 + 12d8: 0004 .2byte 0x4 + 12da: 0401 addi s0,s0,0 + 12dc: 0301 addi t1,t1,0 + 12de: 092a slli s2,s2,0xa + 12e0: 0000 unimp + 12e2: 0401 addi s0,s0,0 + 12e4: 0302 c.slli64 t1 + 12e6: 0956 slli s2,s2,0x15 + 12e8: 0000 unimp + 12ea: 0401 addi s0,s0,0 + 12ec: 0501 addi a0,a0,0 + 12ee: 0605 addi a2,a2,1 + 12f0: 00093a03 .4byte 0x93a03 + 12f4: 0100 addi s0,sp,128 + 12f6: 2205 jal 1416 <_sbrk_r+0x20> + 12f8: 0306 slli t1,t1,0x1 + 12fa: 0948 addi a0,sp,148 + 12fc: 0008 .2byte 0x8 + 12fe: 0301 addi t1,t1,0 + 1300: 0901 addi s2,s2,0 + 1302: 000c .2byte 0xc + 1304: 0501 addi a0,a0,0 + 1306: 0309 addi t1,t1,2 + 1308: 091c addi a5,sp,144 + 130a: 000c .2byte 0xc + 130c: 0501 addi a0,a0,0 + 130e: 09040307 .4byte 0x9040307 + 1312: 000c .2byte 0xc + 1314: 0301 addi t1,t1,0 + 1316: 0912 slli s2,s2,0x4 + 1318: 000c .2byte 0xc + 131a: 0501 addi a0,a0,0 + 131c: 0638 addi a4,sp,776 + 131e: 00090003 lb zero,0(s2) + 1322: 0100 addi s0,sp,128 + 1324: 0705 addi a4,a4,1 + 1326: 04090003 lb zero,64(s2) + 132a: 0100 addi s0,sp,128 + 132c: 0105 addi sp,sp,1 + 132e: 08090a03 lb s4,128(s2) + 1332: 0100 addi s0,sp,128 + 1334: 1c09 addi s8,s8,-30 + 1336: 0000 unimp + 1338: 0101 addi sp,sp,0 + 133a: 4405 li s0,1 + 133c: 0500 addi s0,sp,640 + 133e: 0002 c.slli64 zero + 1340: 0000 unimp + 1342: 0300 addi s0,sp,384 + 1344: 00dd addi ra,ra,23 + 1346: 0501 addi a0,a0,0 + 1348: 09030303 lb t1,144(t1) + 134c: 0000 unimp + 134e: 0501 addi a0,a0,0 + 1350: 0606 slli a2,a2,0x1 + 1352: 00090003 lb zero,0(s2) + 1356: 0100 addi s0,sp,128 + 1358: 0505 addi a0,a0,1 + 135a: 0306 slli t1,t1,0x1 + 135c: 0901 addi s2,s2,0 + 135e: 0000 unimp + 1360: 0501 addi a0,a0,0 + 1362: 0622 slli a2,a2,0x8 + 1364: 00090003 lb zero,0(s2) + 1368: 0100 addi s0,sp,128 + 136a: 0505 addi a0,a0,1 + 136c: 0306 slli t1,t1,0x1 + 136e: 0901 addi s2,s2,0 + 1370: 0000 unimp + 1372: 0501 addi a0,a0,0 + 1374: 060c addi a1,sp,768 + 1376: 00090003 lb zero,0(s2) + 137a: 0100 addi s0,sp,128 + 137c: 0a05 addi s4,s4,1 + 137e: 00090203 lb tp,0(s2) + 1382: 0100 addi s0,sp,128 + 1384: 0105 addi sp,sp,1 + 1386: 00090103 lb sp,0(s2) + 138a: 0100 addi s0,sp,128 + 138c: 0009 c.nop 2 + 138e: 0000 unimp + 1390: 0101 addi sp,sp,0 + 1392: 2f05 jal 1ac2 + 1394: 0500 addi s0,sp,640 + 1396: 3c02 .2byte 0x3c02 + 1398: 0008 .2byte 0x8 + 139a: 0300 addi s0,sp,384 + 139c: 050100ef jal ra,113ec <__neorv32_ram_size+0xf3ec> + 13a0: 09030303 lb t1,144(t1) + 13a4: 0000 unimp + 13a6: 0501 addi a0,a0,0 + 13a8: 0606 slli a2,a2,0x1 + 13aa: 00090003 lb zero,0(s2) + 13ae: 0100 addi s0,sp,128 + 13b0: 0505 addi a0,a0,1 + 13b2: 0306 slli t1,t1,0x1 + 13b4: 0901 addi s2,s2,0 + 13b6: 0008 .2byte 0x8 + 13b8: 0501 addi a0,a0,0 + 13ba: 0622 slli a2,a2,0x8 + 13bc: 00090003 lb zero,0(s2) + 13c0: 0100 addi s0,sp,128 + 13c2: 0505 addi a0,a0,1 + 13c4: 0306 slli t1,t1,0x1 + 13c6: 0901 addi s2,s2,0 + 13c8: 0018 .2byte 0x18 + 13ca: 0501 addi a0,a0,0 + 13cc: 060c addi a1,sp,768 + 13ce: 00090003 lb zero,0(s2) + 13d2: 0100 addi s0,sp,128 + 13d4: 0a05 addi s4,s4,1 + 13d6: 08090203 lb tp,128(s2) + 13da: 0100 addi s0,sp,128 + 13dc: 0105 addi sp,sp,1 + 13de: 04090103 lb sp,64(s2) + 13e2: 0100 addi s0,sp,128 + 13e4: 0409 addi s0,s0,2 + 13e6: 0000 unimp + 13e8: 0101 addi sp,sp,0 + 13ea: 1e05 addi t3,t3,-31 + 13ec: 0500 addi s0,sp,640 + 13ee: 6c02 .2byte 0x6c02 + 13f0: 0008 .2byte 0x8 + 13f2: 0300 addi s0,sp,384 + 13f4: 00c0 addi s0,sp,68 + 13f6: 0501 addi a0,a0,0 + 13f8: 09030303 lb t1,144(t1) + 13fc: 0000 unimp + 13fe: 0401 addi s0,s0,0 + 1400: 0302 c.slli64 t1 + 1402: 000901a3 sb zero,3(s2) + 1406: 0100 addi s0,sp,128 + 1408: 00090203 lb tp,0(s2) + 140c: 0100 addi s0,sp,128 + 140e: 0104 addi s1,sp,128 + 1410: 1e05 addi t3,t3,-31 + 1412: 0306 slli t1,t1,0x1 + 1414: 7ed8 .2byte 0x7ed8 + 1416: 0009 c.nop 2 + 1418: 0100 addi s0,sp,128 + 141a: 0204 addi s1,sp,256 + 141c: 0305 addi t1,t1,1 + 141e: 0901a803 lw a6,144(gp) # 800010d0 <__global_pointer$+0x90> + 1422: 0004 .2byte 0x4 + 1424: 0401 addi s0,s0,0 + 1426: 0501 addi a0,a0,0 + 1428: 031e slli t1,t1,0x7 + 142a: 7ed8 .2byte 0x7ed8 + 142c: 0009 c.nop 2 + 142e: 0100 addi s0,sp,128 + 1430: 0204 addi s1,sp,256 + 1432: 0305 addi t1,t1,1 + 1434: 0901a803 lw a6,144(gp) # 800010d0 <__global_pointer$+0x90> + 1438: 000c .2byte 0xc + 143a: 0401 addi s0,s0,0 + 143c: 0601 addi a2,a2,0 + 143e: 097ede03 lhu t3,151(t4) + 1442: 0008 .2byte 0x8 + 1444: 0401 addi s0,s0,0 + 1446: 0302 c.slli64 t1 + 1448: 01a0 addi s0,sp,200 + 144a: 0009 c.nop 2 + 144c: 0100 addi s0,sp,128 + 144e: 00090203 lb tp,0(s2) + 1452: 0100 addi s0,sp,128 + 1454: 0104 addi s1,sp,128 + 1456: 097ee103 .4byte 0x97ee103 + 145a: 0008 .2byte 0x8 + 145c: 0401 addi s0,s0,0 + 145e: 0302 c.slli64 t1 + 1460: 019d addi gp,gp,7 # 80001047 <__global_pointer$+0x7> + 1462: 0009 c.nop 2 + 1464: 0100 addi s0,sp,128 + 1466: 00090203 lb tp,0(s2) + 146a: 0100 addi s0,sp,128 + 146c: 0104 addi s1,sp,128 + 146e: 097ee403 .4byte 0x97ee403 + 1472: 0004 .2byte 0x4 + 1474: 0501 addi a0,a0,0 + 1476: 061a slli a2,a2,0x6 + 1478: 00090003 lb zero,0(s2) + 147c: 0100 addi s0,sp,128 + 147e: 0305 addi t1,t1,1 + 1480: 0306 slli t1,t1,0x1 + 1482: 00040903 lb s2,0(s0) + 1486: 0301 addi t1,t1,0 + 1488: 0901 addi s2,s2,0 + 148a: 0000 unimp + 148c: 0501 addi a0,a0,0 + 148e: 09000313 li t1,144 + 1492: 0000 unimp + 1494: 0501 addi a0,a0,0 + 1496: 0003060b .4byte 0x3060b + 149a: 0009 c.nop 2 + 149c: 0100 addi s0,sp,128 + 149e: 1305 addi t1,t1,-31 + 14a0: 04090003 lb zero,64(s2) + 14a4: 0100 addi s0,sp,128 + 14a6: 0505 addi a0,a0,1 + 14a8: 0200 addi s0,sp,256 + 14aa: 0304 addi s1,sp,384 + 14ac: 0306 slli t1,t1,0x1 + 14ae: 0901 addi s2,s2,0 + 14b0: 0004 .2byte 0x4 + 14b2: 0501 addi a0,a0,0 + 14b4: 005f 0402 0603 .byte 0x5f, 0x00, 0x02, 0x04, 0x03, 0x06 + 14ba: 04097f03 .4byte 0x4097f03 + 14be: 0100 addi s0,sp,128 + 14c0: 0505 addi a0,a0,1 + 14c2: 0200 addi s0,sp,256 + 14c4: 0304 addi s1,sp,384 + 14c6: 08090103 lb sp,128(s2) + 14ca: 0100 addi s0,sp,128 + 14cc: 5f05 li t5,-31 + 14ce: 0200 addi s0,sp,256 + 14d0: 0304 addi s1,sp,384 + 14d2: 0306 slli t1,t1,0x1 + 14d4: 097f .2byte 0x97f + 14d6: 0004 .2byte 0x4 + 14d8: 0501 addi a0,a0,0 + 14da: 04020013 addi zero,tp,64 # 40 + 14de: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 14e2: 0000 unimp + 14e4: 0501 addi a0,a0,0 + 14e6: 0601 addi a2,a2,0 + 14e8: 04090303 lb t1,64(s2) + 14ec: 0100 addi s0,sp,128 + 14ee: 1409 addi s0,s0,-30 + 14f0: 0000 unimp + 14f2: 0101 addi sp,sp,0 + 14f4: 2905 jal 1924 <__fini_array_end+0x204> + 14f6: 0500 addi s0,sp,640 + 14f8: 0002 c.slli64 zero + 14fa: 0000 unimp + 14fc: 0300 addi s0,sp,384 + 14fe: 04cc addi a1,sp,580 + 1500: 0501 addi a0,a0,0 + 1502: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 1506: 0000 unimp + 1508: 0301 addi t1,t1,0 + 150a: 0901 addi s2,s2,0 + 150c: 0000 unimp + 150e: 0301 addi t1,t1,0 + 1510: 0902 c.slli64 s2 + 1512: 0000 unimp + 1514: 0501 addi a0,a0,0 + 1516: 0629 addi a2,a2,10 + 1518: 00097b03 .4byte 0x97b03 + 151c: 0100 addi s0,sp,128 + 151e: 0705 addi a4,a4,1 + 1520: 00090503 lb a0,0(s2) + 1524: 0100 addi s0,sp,128 + 1526: 0605 addi a2,a2,1 + 1528: 00090003 lb zero,0(s2) + 152c: 0100 addi s0,sp,128 + 152e: 0805 addi a6,a6,1 + 1530: 00090f03 lb t5,0(s2) + 1534: 0100 addi s0,sp,128 + 1536: 0505 addi a0,a0,1 + 1538: 0306 slli t1,t1,0x1 + 153a: 00000977 .4byte 0x977 + 153e: 0401 addi s0,s0,0 + 1540: 0502 c.slli64 a0 + 1542: 7cff0303 lb t1,1999(t5) + 1546: 0009 c.nop 2 + 1548: 0100 addi s0,sp,128 + 154a: 00090203 lb tp,0(s2) + 154e: 0100 addi s0,sp,128 + 1550: 00090203 lb tp,0(s2) + 1554: 0100 addi s0,sp,128 + 1556: 0104 addi s1,sp,128 + 1558: 3305 jal 1278 <_malloc_r+0x41a> + 155a: 0306 slli t1,t1,0x1 + 155c: 02fd addi t0,t0,31 + 155e: 0009 c.nop 2 + 1560: 0100 addi s0,sp,128 + 1562: 0905 addi s2,s2,1 + 1564: 00090003 lb zero,0(s2) + 1568: 0100 addi s0,sp,128 + 156a: 0505 addi a0,a0,1 + 156c: 0306 slli t1,t1,0x1 + 156e: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 1572: 0301 addi t1,t1,0 + 1574: 0901 addi s2,s2,0 + 1576: 0000 unimp + 1578: 0501 addi a0,a0,0 + 157a: 0310 addi a2,sp,384 + 157c: 0900 addi s0,sp,144 + 157e: 0000 unimp + 1580: 0501 addi a0,a0,0 + 1582: 0305 addi t1,t1,1 + 1584: 0905 addi s2,s2,1 + 1586: 0000 unimp + 1588: 0501 addi a0,a0,0 + 158a: 0608 addi a0,sp,768 + 158c: 00090003 lb zero,0(s2) + 1590: 0100 addi s0,sp,128 + 1592: 0705 addi a4,a4,1 + 1594: 0306 slli t1,t1,0x1 + 1596: 0901 addi s2,s2,0 + 1598: 0000 unimp + 159a: 0501 addi a0,a0,0 + 159c: 0305 addi t1,t1,1 + 159e: 0902 c.slli64 s2 + 15a0: 0000 unimp + 15a2: 0301 addi t1,t1,0 + 15a4: 0901 addi s2,s2,0 + 15a6: 0000 unimp + 15a8: 0501 addi a0,a0,0 + 15aa: 0608 addi a0,sp,768 + 15ac: 00090003 lb zero,0(s2) + 15b0: 0100 addi s0,sp,128 + 15b2: 0705 addi a4,a4,1 + 15b4: 0306 slli t1,t1,0x1 + 15b6: 0901 addi s2,s2,0 + 15b8: 0000 unimp + 15ba: 0501 addi a0,a0,0 + 15bc: 09700313 li t1,151 + 15c0: 0000 unimp + 15c2: 0501 addi a0,a0,0 + 15c4: 030e slli t1,t1,0x3 + 15c6: 0900 addi s0,sp,144 + 15c8: 0000 unimp + 15ca: 0501 addi a0,a0,0 + 15cc: 0601 addi a2,a2,0 + 15ce: 00091303 lh t1,0(s2) + 15d2: 0100 addi s0,sp,128 + 15d4: 0009 c.nop 2 + 15d6: 0000 unimp + 15d8: 0101 addi sp,sp,0 + 15da: 2805 jal 160a <_free_r+0x11a> + 15dc: 0500 addi s0,sp,640 + 15de: 0002 c.slli64 zero + 15e0: 0000 unimp + 15e2: 0300 addi s0,sp,384 + 15e4: 029f 0501 0303 .byte 0x9f, 0x02, 0x01, 0x05, 0x03, 0x03 + 15ea: 0902 c.slli64 s2 + 15ec: 0000 unimp + 15ee: 0501 addi a0,a0,0 + 15f0: 0628 addi a0,sp,776 + 15f2: 00097e03 .4byte 0x97e03 + 15f6: 0100 addi s0,sp,128 + 15f8: 0705 addi a4,a4,1 + 15fa: 00090203 lb tp,0(s2) + 15fe: 0100 addi s0,sp,128 + 1600: 0605 addi a2,a2,1 + 1602: 00090003 lb zero,0(s2) + 1606: 0100 addi s0,sp,128 + 1608: 0305 addi t1,t1,1 + 160a: 0306 slli t1,t1,0x1 + 160c: 0904 addi s1,sp,144 + 160e: 0000 unimp + 1610: 0301 addi t1,t1,0 + 1612: 0901 addi s2,s2,0 + 1614: 0000 unimp + 1616: 0301 addi t1,t1,0 + 1618: 0901 addi s2,s2,0 + 161a: 0000 unimp + 161c: 0301 addi t1,t1,0 + 161e: 0902 c.slli64 s2 + 1620: 0000 unimp + 1622: 0301 addi t1,t1,0 + 1624: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 1628: 0301 addi t1,t1,0 + 162a: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 162e: 0501 addi a0,a0,0 + 1630: 0330 addi a2,sp,392 + 1632: 0900 addi s0,sp,144 + 1634: 0000 unimp + 1636: 0401 addi s0,s0,0 + 1638: 0502 c.slli64 a0 + 163a: 7fa70303 lb t1,2042(a4) + 163e: 0009 c.nop 2 + 1640: 0100 addi s0,sp,128 + 1642: 00090203 lb tp,0(s2) + 1646: 0100 addi s0,sp,128 + 1648: 00090203 lb tp,0(s2) + 164c: 0100 addi s0,sp,128 + 164e: 0104 addi s1,sp,128 + 1650: 3005 jal e70 <_malloc_r+0x12> + 1652: 0306 slli t1,t1,0x1 + 1654: 00d5 addi ra,ra,21 + 1656: 0009 c.nop 2 + 1658: 0100 addi s0,sp,128 + 165a: 0305 addi t1,t1,1 + 165c: 0306 slli t1,t1,0x1 + 165e: 0901 addi s2,s2,0 + 1660: 0000 unimp + 1662: 0501 addi a0,a0,0 + 1664: 0645 addi a2,a2,17 + 1666: 00090003 lb zero,0(s2) + 166a: 0100 addi s0,sp,128 + 166c: 0305 addi t1,t1,1 + 166e: 00090003 lb zero,0(s2) + 1672: 0100 addi s0,sp,128 + 1674: 0306 slli t1,t1,0x1 + 1676: 0901 addi s2,s2,0 + 1678: 0000 unimp + 167a: 0501 addi a0,a0,0 + 167c: 0330 addi a2,sp,392 + 167e: 0900 addi s0,sp,144 + 1680: 0000 unimp + 1682: 0501 addi a0,a0,0 + 1684: 065e slli a2,a2,0x17 + 1686: 00090003 lb zero,0(s2) + 168a: 0100 addi s0,sp,128 + 168c: 3005 jal eac <_malloc_r+0x4e> + 168e: 00090003 lb zero,0(s2) + 1692: 0100 addi s0,sp,128 + 1694: 0305 addi t1,t1,1 + 1696: 0306 slli t1,t1,0x1 + 1698: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 169c: 0501 addi a0,a0,0 + 169e: 05030627 .4byte 0x5030627 + 16a2: 0009 c.nop 2 + 16a4: 0100 addi s0,sp,128 + 16a6: 0204 addi s1,sp,256 + 16a8: 0305 addi t1,t1,1 + 16aa: 0306 slli t1,t1,0x1 + 16ac: 7f9d lui t6,0xfffe7 + 16ae: 0009 c.nop 2 + 16b0: 0100 addi s0,sp,128 + 16b2: 00090203 lb tp,0(s2) + 16b6: 0100 addi s0,sp,128 + 16b8: 00090203 lb tp,0(s2) + 16bc: 0100 addi s0,sp,128 + 16be: 00097c03 .4byte 0x97c03 + 16c2: 0100 addi s0,sp,128 + 16c4: 00090203 lb tp,0(s2) + 16c8: 0100 addi s0,sp,128 + 16ca: 00090203 lb tp,0(s2) + 16ce: 0100 addi s0,sp,128 + 16d0: 00097c03 .4byte 0x97c03 + 16d4: 0100 addi s0,sp,128 + 16d6: 00090203 lb tp,0(s2) + 16da: 0100 addi s0,sp,128 + 16dc: 00090203 lb tp,0(s2) + 16e0: 0100 addi s0,sp,128 + 16e2: 00097c03 .4byte 0x97c03 + 16e6: 0100 addi s0,sp,128 + 16e8: 00090203 lb tp,0(s2) + 16ec: 0100 addi s0,sp,128 + 16ee: 00090203 lb tp,0(s2) + 16f2: 0100 addi s0,sp,128 + 16f4: 0104 addi s1,sp,128 + 16f6: 0306 slli t1,t1,0x1 + 16f8: 00da slli ra,ra,0x16 + 16fa: 0009 c.nop 2 + 16fc: 0100 addi s0,sp,128 + 16fe: 0306 slli t1,t1,0x1 + 1700: 0000090b .4byte 0x90b + 1704: 0301 addi t1,t1,0 + 1706: 0901 addi s2,s2,0 + 1708: 0000 unimp + 170a: 0301 addi t1,t1,0 + 170c: 0901 addi s2,s2,0 + 170e: 0000 unimp + 1710: 0301 addi t1,t1,0 + 1712: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 1716: 0301 addi t1,t1,0 + 1718: 0901 addi s2,s2,0 + 171a: 0000 unimp + 171c: 0401 addi s0,s0,0 + 171e: 0302 c.slli64 t1 + 1720: 7f91 lui t6,0xfffe4 + 1722: 0009 c.nop 2 + 1724: 0100 addi s0,sp,128 + 1726: 00090203 lb tp,0(s2) + 172a: 0100 addi s0,sp,128 + 172c: 00090203 lb tp,0(s2) + 1730: 0100 addi s0,sp,128 + 1732: 0104 addi s1,sp,128 + 1734: 0900ec03 .4byte 0x900ec03 + 1738: 0000 unimp + 173a: 0301 addi t1,t1,0 + 173c: 0901 addi s2,s2,0 + 173e: 0000 unimp + 1740: 0501 addi a0,a0,0 + 1742: 0606 slli a2,a2,0x1 + 1744: 00090003 lb zero,0(s2) + 1748: 0100 addi s0,sp,128 + 174a: 0705 addi a4,a4,1 + 174c: 00097f03 .4byte 0x97f03 + 1750: 0100 addi s0,sp,128 + 1752: 0605 addi a2,a2,1 + 1754: 00090103 lb sp,0(s2) + 1758: 0100 addi s0,sp,128 + 175a: 0505 addi a0,a0,1 + 175c: 0306 slli t1,t1,0x1 + 175e: 0901 addi s2,s2,0 + 1760: 0000 unimp + 1762: 0601 addi a2,a2,0 + 1764: 00090303 lb t1,0(s2) + 1768: 0100 addi s0,sp,128 + 176a: 0305 addi t1,t1,1 + 176c: 0306 slli t1,t1,0x1 + 176e: 0904 addi s1,sp,144 + 1770: 0000 unimp + 1772: 0301 addi t1,t1,0 + 1774: 0901 addi s2,s2,0 + 1776: 0000 unimp + 1778: 0401 addi s0,s0,0 + 177a: 0302 c.slli64 t1 + 177c: 7f86 .2byte 0x7f86 + 177e: 0009 c.nop 2 + 1780: 0100 addi s0,sp,128 + 1782: 00090203 lb tp,0(s2) + 1786: 0100 addi s0,sp,128 + 1788: 00090203 lb tp,0(s2) + 178c: 0100 addi s0,sp,128 + 178e: 0104 addi s1,sp,128 + 1790: 0900f703 .4byte 0x900f703 + 1794: 0000 unimp + 1796: 0501 addi a0,a0,0 + 1798: 030e slli t1,t1,0x3 + 179a: 0900 addi s0,sp,144 + 179c: 0000 unimp + 179e: 0501 addi a0,a0,0 + 17a0: 0609 addi a2,a2,2 + 17a2: 00090003 lb zero,0(s2) + 17a6: 0100 addi s0,sp,128 + 17a8: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 17aa: 00090103 lb sp,0(s2) + 17ae: 0100 addi s0,sp,128 + 17b0: 0e05 addi t3,t3,1 + 17b2: 00097f03 .4byte 0x97f03 + 17b6: 0100 addi s0,sp,128 + 17b8: 0505 addi a0,a0,1 + 17ba: 0306 slli t1,t1,0x1 + 17bc: 0901 addi s2,s2,0 + 17be: 0000 unimp + 17c0: 0501 addi a0,a0,0 + 17c2: 0612 slli a2,a2,0x4 + 17c4: 00090003 lb zero,0(s2) + 17c8: 0100 addi s0,sp,128 + 17ca: 0d05 addi s10,s10,1 + 17cc: 00090003 lb zero,0(s2) + 17d0: 0100 addi s0,sp,128 + 17d2: 0805 addi a6,a6,1 + 17d4: 00090003 lb zero,0(s2) + 17d8: 0100 addi s0,sp,128 + 17da: 0705 addi a4,a4,1 + 17dc: 0306 slli t1,t1,0x1 + 17de: 0901 addi s2,s2,0 + 17e0: 0000 unimp + 17e2: 0301 addi t1,t1,0 + 17e4: 0901 addi s2,s2,0 + 17e6: 0000 unimp + 17e8: 0501 addi a0,a0,0 + 17ea: 0609 addi a2,a2,2 + 17ec: 00097f03 .4byte 0x97f03 + 17f0: 0100 addi s0,sp,128 + 17f2: 0705 addi a4,a4,1 + 17f4: 00090103 lb sp,0(s2) + 17f8: 0100 addi s0,sp,128 + 17fa: 0306 slli t1,t1,0x1 + 17fc: 0901 addi s2,s2,0 + 17fe: 0000 unimp + 1800: 0501 addi a0,a0,0 + 1802: 0014 .2byte 0x14 + 1804: 0402 c.slli64 s0 + 1806: 0302 c.slli64 t1 + 1808: 097c addi a5,sp,156 + 180a: 0000 unimp + 180c: 0501 addi a0,a0,0 + 180e: 000e c.slli zero,0x3 + 1810: 0402 c.slli64 s0 + 1812: 0302 c.slli64 t1 + 1814: 0900 addi s0,sp,144 + 1816: 0000 unimp + 1818: 0501 addi a0,a0,0 + 181a: 09090303 lb t1,144(s2) + 181e: 0000 unimp + 1820: 0401 addi s0,s0,0 + 1822: 0302 c.slli64 t1 + 1824: 7efc .2byte 0x7efc + 1826: 0009 c.nop 2 + 1828: 0100 addi s0,sp,128 + 182a: 00090203 lb tp,0(s2) + 182e: 0100 addi s0,sp,128 + 1830: 00090203 lb tp,0(s2) + 1834: 0100 addi s0,sp,128 + 1836: 0104 addi s1,sp,128 + 1838: 09018103 lb sp,144(gp) # 800010d0 <__global_pointer$+0x90> + 183c: 0000 unimp + 183e: 0501 addi a0,a0,0 + 1840: 0003060b .4byte 0x3060b + 1844: 0009 c.nop 2 + 1846: 0100 addi s0,sp,128 + 1848: 0605 addi a2,a2,1 + 184a: 00090003 lb zero,0(s2) + 184e: 0100 addi s0,sp,128 + 1850: 0505 addi a0,a0,1 + 1852: 0306 slli t1,t1,0x1 + 1854: 0901 addi s2,s2,0 + 1856: 0000 unimp + 1858: 0501 addi a0,a0,0 + 185a: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 185e: 0000 unimp + 1860: 0501 addi a0,a0,0 + 1862: 0003060b .4byte 0x3060b + 1866: 0009 c.nop 2 + 1868: 0100 addi s0,sp,128 + 186a: 0605 addi a2,a2,1 + 186c: 00090003 lb zero,0(s2) + 1870: 0100 addi s0,sp,128 + 1872: 0505 addi a0,a0,1 + 1874: 0306 slli t1,t1,0x1 + 1876: 0901 addi s2,s2,0 + 1878: 0000 unimp + 187a: 0501 addi a0,a0,0 + 187c: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 1880: 0000 unimp + 1882: 0501 addi a0,a0,0 + 1884: 0003060b .4byte 0x3060b + 1888: 0009 c.nop 2 + 188a: 0100 addi s0,sp,128 + 188c: 0605 addi a2,a2,1 + 188e: 00090003 lb zero,0(s2) + 1892: 0100 addi s0,sp,128 + 1894: 0505 addi a0,a0,1 + 1896: 0306 slli t1,t1,0x1 + 1898: 0901 addi s2,s2,0 + 189a: 0000 unimp + 189c: 0501 addi a0,a0,0 + 189e: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 18a2: 0000 unimp + 18a4: 0501 addi a0,a0,0 + 18a6: 0003060b .4byte 0x3060b + 18aa: 0009 c.nop 2 + 18ac: 0100 addi s0,sp,128 + 18ae: 0605 addi a2,a2,1 + 18b0: 00090003 lb zero,0(s2) + 18b4: 0100 addi s0,sp,128 + 18b6: 0505 addi a0,a0,1 + 18b8: 0306 slli t1,t1,0x1 + 18ba: 0901 addi s2,s2,0 + 18bc: 0000 unimp + 18be: 0501 addi a0,a0,0 + 18c0: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 18c4: 0000 unimp + 18c6: 0501 addi a0,a0,0 + 18c8: 0003060b .4byte 0x3060b + 18cc: 0009 c.nop 2 + 18ce: 0100 addi s0,sp,128 + 18d0: 0605 addi a2,a2,1 + 18d2: 00090003 lb zero,0(s2) + 18d6: 0100 addi s0,sp,128 + 18d8: 0505 addi a0,a0,1 + 18da: 0306 slli t1,t1,0x1 + 18dc: 0901 addi s2,s2,0 + 18de: 0000 unimp + 18e0: 0501 addi a0,a0,0 + 18e2: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 18e6: 0000 unimp + 18e8: 0501 addi a0,a0,0 + 18ea: 0003060b .4byte 0x3060b + 18ee: 0009 c.nop 2 + 18f0: 0100 addi s0,sp,128 + 18f2: 0605 addi a2,a2,1 + 18f4: 00090003 lb zero,0(s2) + 18f8: 0100 addi s0,sp,128 + 18fa: 0505 addi a0,a0,1 + 18fc: 0306 slli t1,t1,0x1 + 18fe: 0901 addi s2,s2,0 + 1900: 0000 unimp + 1902: 0501 addi a0,a0,0 + 1904: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 1908: 0000 unimp + 190a: 0501 addi a0,a0,0 + 190c: 0003060b .4byte 0x3060b + 1910: 0009 c.nop 2 + 1912: 0100 addi s0,sp,128 + 1914: 0605 addi a2,a2,1 + 1916: 00090003 lb zero,0(s2) + 191a: 0100 addi s0,sp,128 + 191c: 0505 addi a0,a0,1 + 191e: 0306 slli t1,t1,0x1 + 1920: 0901 addi s2,s2,0 + 1922: 0000 unimp + 1924: 0501 addi a0,a0,0 + 1926: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 192a: 0000 unimp + 192c: 0501 addi a0,a0,0 + 192e: 0003060b .4byte 0x3060b + 1932: 0009 c.nop 2 + 1934: 0100 addi s0,sp,128 + 1936: 0605 addi a2,a2,1 + 1938: 00090003 lb zero,0(s2) + 193c: 0100 addi s0,sp,128 + 193e: 0505 addi a0,a0,1 + 1940: 0306 slli t1,t1,0x1 + 1942: 0901 addi s2,s2,0 + 1944: 0000 unimp + 1946: 0501 addi a0,a0,0 + 1948: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 194c: 0000 unimp + 194e: 0501 addi a0,a0,0 + 1950: 0003060b .4byte 0x3060b + 1954: 0009 c.nop 2 + 1956: 0100 addi s0,sp,128 + 1958: 0605 addi a2,a2,1 + 195a: 00090003 lb zero,0(s2) + 195e: 0100 addi s0,sp,128 + 1960: 0505 addi a0,a0,1 + 1962: 0306 slli t1,t1,0x1 + 1964: 0901 addi s2,s2,0 + 1966: 0000 unimp + 1968: 0501 addi a0,a0,0 + 196a: 09040303 lb t1,144(s0) + 196e: 0000 unimp + 1970: 0301 addi t1,t1,0 + 1972: 0901 addi s2,s2,0 + 1974: 0000 unimp + 1976: 0501 addi a0,a0,0 + 1978: 0003060b .4byte 0x3060b + 197c: 0009 c.nop 2 + 197e: 0100 addi s0,sp,128 + 1980: 0605 addi a2,a2,1 + 1982: 00090003 lb zero,0(s2) + 1986: 0100 addi s0,sp,128 + 1988: 0505 addi a0,a0,1 + 198a: 0306 slli t1,t1,0x1 + 198c: 0901 addi s2,s2,0 + 198e: 0000 unimp + 1990: 0501 addi a0,a0,0 + 1992: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 1996: 0000 unimp + 1998: 0501 addi a0,a0,0 + 199a: 0606 slli a2,a2,0x1 + 199c: 00090003 lb zero,0(s2) + 19a0: 0100 addi s0,sp,128 + 19a2: 0505 addi a0,a0,1 + 19a4: 0306 slli t1,t1,0x1 + 19a6: 0901 addi s2,s2,0 + 19a8: 0000 unimp + 19aa: 0501 addi a0,a0,0 + 19ac: 09040303 lb t1,144(s0) + 19b0: 0000 unimp + 19b2: 0301 addi t1,t1,0 + 19b4: 0901 addi s2,s2,0 + 19b6: 0000 unimp + 19b8: 0501 addi a0,a0,0 + 19ba: 061e slli a2,a2,0x7 + 19bc: 00090003 lb zero,0(s2) + 19c0: 0100 addi s0,sp,128 + 19c2: 0305 addi t1,t1,1 + 19c4: 0306 slli t1,t1,0x1 + 19c6: 0901 addi s2,s2,0 + 19c8: 0000 unimp + 19ca: 0501 addi a0,a0,0 + 19cc: 0606 slli a2,a2,0x1 + 19ce: 00090003 lb zero,0(s2) + 19d2: 0100 addi s0,sp,128 + 19d4: 0505 addi a0,a0,1 + 19d6: 0306 slli t1,t1,0x1 + 19d8: 0901 addi s2,s2,0 + 19da: 0000 unimp + 19dc: 0501 addi a0,a0,0 + 19de: 09070303 lb t1,144(a4) + 19e2: 0000 unimp + 19e4: 0301 addi t1,t1,0 + 19e6: 0901 addi s2,s2,0 + 19e8: 0000 unimp + 19ea: 0501 addi a0,a0,0 + 19ec: 0616 slli a2,a2,0x5 + 19ee: 00090003 lb zero,0(s2) + 19f2: 0100 addi s0,sp,128 + 19f4: 0305 addi t1,t1,1 + 19f6: 0306 slli t1,t1,0x1 + 19f8: 0901 addi s2,s2,0 + 19fa: 0000 unimp + 19fc: 0501 addi a0,a0,0 + 19fe: 0606 slli a2,a2,0x1 + 1a00: 00090003 lb zero,0(s2) + 1a04: 0100 addi s0,sp,128 + 1a06: 0505 addi a0,a0,1 + 1a08: 0306 slli t1,t1,0x1 + 1a0a: 0901 addi s2,s2,0 + 1a0c: 0000 unimp + 1a0e: 0501 addi a0,a0,0 + 1a10: 09080303 lb t1,144(a6) + 1a14: 0000 unimp + 1a16: 0301 addi t1,t1,0 + 1a18: 0902 c.slli64 s2 + 1a1a: 0000 unimp + 1a1c: 0301 addi t1,t1,0 + 1a1e: 0901 addi s2,s2,0 + 1a20: 0000 unimp + 1a22: 0501 addi a0,a0,0 + 1a24: 0616 slli a2,a2,0x5 + 1a26: 00090003 lb zero,0(s2) + 1a2a: 0100 addi s0,sp,128 + 1a2c: 1b05 addi s6,s6,-31 + 1a2e: 00090003 lb zero,0(s2) + 1a32: 0100 addi s0,sp,128 + 1a34: 0605 addi a2,a2,1 + 1a36: 00090003 lb zero,0(s2) + 1a3a: 0100 addi s0,sp,128 + 1a3c: 0505 addi a0,a0,1 + 1a3e: 0306 slli t1,t1,0x1 + 1a40: 0901 addi s2,s2,0 + 1a42: 0000 unimp + 1a44: 0501 addi a0,a0,0 + 1a46: 09060303 lb t1,144(a2) + 1a4a: 0000 unimp + 1a4c: 0501 addi a0,a0,0 + 1a4e: 0646 slli a2,a2,0x11 + 1a50: 00090003 lb zero,0(s2) + 1a54: 0100 addi s0,sp,128 + 1a56: 0305 addi t1,t1,1 + 1a58: 00090003 lb zero,0(s2) + 1a5c: 0100 addi s0,sp,128 + 1a5e: 0306 slli t1,t1,0x1 + 1a60: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 1a64: 0301 addi t1,t1,0 + 1a66: 0901 addi s2,s2,0 + 1a68: 0000 unimp + 1a6a: 0501 addi a0,a0,0 + 1a6c: 0616 slli a2,a2,0x5 + 1a6e: 00090003 lb zero,0(s2) + 1a72: 0100 addi s0,sp,128 + 1a74: 1b05 addi s6,s6,-31 + 1a76: 00090003 lb zero,0(s2) + 1a7a: 0100 addi s0,sp,128 + 1a7c: 0605 addi a2,a2,1 + 1a7e: 00090003 lb zero,0(s2) + 1a82: 0100 addi s0,sp,128 + 1a84: 0505 addi a0,a0,1 + 1a86: 0306 slli t1,t1,0x1 + 1a88: 0901 addi s2,s2,0 + 1a8a: 0000 unimp + 1a8c: 0501 addi a0,a0,0 + 1a8e: 063c addi a5,sp,776 + 1a90: 00090003 lb zero,0(s2) + 1a94: 0100 addi s0,sp,128 + 1a96: 0505 addi a0,a0,1 + 1a98: 00090003 lb zero,0(s2) + 1a9c: 0100 addi s0,sp,128 + 1a9e: 0305 addi t1,t1,1 + 1aa0: 0306 slli t1,t1,0x1 + 1aa2: 00000907 .4byte 0x907 + 1aa6: 0501 addi a0,a0,0 + 1aa8: 0646 slli a2,a2,0x11 + 1aaa: 00090003 lb zero,0(s2) + 1aae: 0100 addi s0,sp,128 + 1ab0: 0305 addi t1,t1,1 + 1ab2: 00090003 lb zero,0(s2) + 1ab6: 0100 addi s0,sp,128 + 1ab8: 0306 slli t1,t1,0x1 + 1aba: 0901 addi s2,s2,0 + 1abc: 0000 unimp + 1abe: 0301 addi t1,t1,0 + 1ac0: 0901 addi s2,s2,0 + 1ac2: 0000 unimp + 1ac4: 0501 addi a0,a0,0 + 1ac6: 0616 slli a2,a2,0x5 + 1ac8: 00090003 lb zero,0(s2) + 1acc: 0100 addi s0,sp,128 + 1ace: 1b05 addi s6,s6,-31 + 1ad0: 00090003 lb zero,0(s2) + 1ad4: 0100 addi s0,sp,128 + 1ad6: 0605 addi a2,a2,1 + 1ad8: 00090003 lb zero,0(s2) + 1adc: 0100 addi s0,sp,128 + 1ade: 0505 addi a0,a0,1 + 1ae0: 0306 slli t1,t1,0x1 + 1ae2: 0901 addi s2,s2,0 + 1ae4: 0000 unimp + 1ae6: 0501 addi a0,a0,0 + 1ae8: 063c addi a5,sp,776 + 1aea: 00090003 lb zero,0(s2) + 1aee: 0100 addi s0,sp,128 + 1af0: 0505 addi a0,a0,1 + 1af2: 00090003 lb zero,0(s2) + 1af6: 0100 addi s0,sp,128 + 1af8: 0305 addi t1,t1,1 + 1afa: 0306 slli t1,t1,0x1 + 1afc: 00000907 .4byte 0x907 + 1b00: 0301 addi t1,t1,0 + 1b02: 0901 addi s2,s2,0 + 1b04: 0000 unimp + 1b06: 0501 addi a0,a0,0 + 1b08: 0616 slli a2,a2,0x5 + 1b0a: 00090003 lb zero,0(s2) + 1b0e: 0100 addi s0,sp,128 + 1b10: 1b05 addi s6,s6,-31 + 1b12: 00090003 lb zero,0(s2) + 1b16: 0100 addi s0,sp,128 + 1b18: 0605 addi a2,a2,1 + 1b1a: 00090003 lb zero,0(s2) + 1b1e: 0100 addi s0,sp,128 + 1b20: 0505 addi a0,a0,1 + 1b22: 0306 slli t1,t1,0x1 + 1b24: 0901 addi s2,s2,0 + 1b26: 0000 unimp + 1b28: 0301 addi t1,t1,0 + 1b2a: 0902 c.slli64 s2 + 1b2c: 0000 unimp + 1b2e: 0501 addi a0,a0,0 + 1b30: 062e slli a2,a2,0xb + 1b32: 00090003 lb zero,0(s2) + 1b36: 0100 addi s0,sp,128 + 1b38: 0e05 addi t3,t3,1 + 1b3a: 00090003 lb zero,0(s2) + 1b3e: 0100 addi s0,sp,128 + 1b40: 0505 addi a0,a0,1 + 1b42: 0306 slli t1,t1,0x1 + 1b44: 0901 addi s2,s2,0 + 1b46: 0000 unimp + 1b48: 0501 addi a0,a0,0 + 1b4a: 0608 addi a0,sp,768 + 1b4c: 00090003 lb zero,0(s2) + 1b50: 0100 addi s0,sp,128 + 1b52: 0705 addi a4,a4,1 + 1b54: 0306 slli t1,t1,0x1 + 1b56: 0901 addi s2,s2,0 + 1b58: 0000 unimp + 1b5a: 0501 addi a0,a0,0 + 1b5c: 0619 addi a2,a2,6 + 1b5e: 00090003 lb zero,0(s2) + 1b62: 0100 addi s0,sp,128 + 1b64: 0505 addi a0,a0,1 + 1b66: 0306 slli t1,t1,0x1 + 1b68: 0906 slli s2,s2,0x1 + 1b6a: 0000 unimp + 1b6c: 0501 addi a0,a0,0 + 1b6e: 062e slli a2,a2,0xb + 1b70: 00090003 lb zero,0(s2) + 1b74: 0100 addi s0,sp,128 + 1b76: 3505 jal 1996 <__fini_array_end+0x276> + 1b78: 00090003 lb zero,0(s2) + 1b7c: 0100 addi s0,sp,128 + 1b7e: 0e05 addi t3,t3,1 + 1b80: 00090003 lb zero,0(s2) + 1b84: 0100 addi s0,sp,128 + 1b86: 0505 addi a0,a0,1 + 1b88: 0306 slli t1,t1,0x1 + 1b8a: 0901 addi s2,s2,0 + 1b8c: 0000 unimp + 1b8e: 0501 addi a0,a0,0 + 1b90: 0608 addi a0,sp,768 + 1b92: 00090003 lb zero,0(s2) + 1b96: 0100 addi s0,sp,128 + 1b98: 0705 addi a4,a4,1 + 1b9a: 0306 slli t1,t1,0x1 + 1b9c: 0901 addi s2,s2,0 + 1b9e: 0000 unimp + 1ba0: 0501 addi a0,a0,0 + 1ba2: 0619 addi a2,a2,6 + 1ba4: 00090003 lb zero,0(s2) + 1ba8: 0100 addi s0,sp,128 + 1baa: 0505 addi a0,a0,1 + 1bac: 0306 slli t1,t1,0x1 + 1bae: 0906 slli s2,s2,0x1 + 1bb0: 0000 unimp + 1bb2: 0501 addi a0,a0,0 + 1bb4: 0631 addi a2,a2,12 + 1bb6: 00090003 lb zero,0(s2) + 1bba: 0100 addi s0,sp,128 + 1bbc: 1a05 addi s4,s4,-31 + 1bbe: 00090103 lb sp,0(s2) + 1bc2: 0100 addi s0,sp,128 + 1bc4: 0505 addi a0,a0,1 + 1bc6: 00090203 lb tp,0(s2) + 1bca: 0100 addi s0,sp,128 + 1bcc: 3805 jal 13fc <_sbrk_r+0x6> + 1bce: 00097d03 .4byte 0x97d03 + 1bd2: 0100 addi s0,sp,128 + 1bd4: 0e05 addi t3,t3,1 + 1bd6: 00090003 lb zero,0(s2) + 1bda: 0100 addi s0,sp,128 + 1bdc: 0505 addi a0,a0,1 + 1bde: 0306 slli t1,t1,0x1 + 1be0: 0901 addi s2,s2,0 + 1be2: 0000 unimp + 1be4: 0501 addi a0,a0,0 + 1be6: 061a slli a2,a2,0x6 + 1be8: 00090003 lb zero,0(s2) + 1bec: 0100 addi s0,sp,128 + 1bee: 0505 addi a0,a0,1 + 1bf0: 00090203 lb tp,0(s2) + 1bf4: 0100 addi s0,sp,128 + 1bf6: 1a05 addi s4,s4,-31 + 1bf8: 00097e03 .4byte 0x97e03 + 1bfc: 0100 addi s0,sp,128 + 1bfe: 0505 addi a0,a0,1 + 1c00: 0306 slli t1,t1,0x1 + 1c02: 0902 c.slli64 s2 + 1c04: 0000 unimp + 1c06: 0301 addi t1,t1,0 + 1c08: 0901 addi s2,s2,0 + 1c0a: 0000 unimp + 1c0c: 0501 addi a0,a0,0 + 1c0e: 0608 addi a0,sp,768 + 1c10: 00090003 lb zero,0(s2) + 1c14: 0100 addi s0,sp,128 + 1c16: 0705 addi a4,a4,1 + 1c18: 0306 slli t1,t1,0x1 + 1c1a: 0901 addi s2,s2,0 + 1c1c: 0000 unimp + 1c1e: 0501 addi a0,a0,0 + 1c20: 0605 addi a2,a2,1 + 1c22: 00090a03 lb s4,0(s2) + 1c26: 0100 addi s0,sp,128 + 1c28: 0305 addi t1,t1,1 + 1c2a: 0306 slli t1,t1,0x1 + 1c2c: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 1c30: 0301 addi t1,t1,0 + 1c32: 0901 addi s2,s2,0 + 1c34: 0000 unimp + 1c36: 0501 addi a0,a0,0 + 1c38: 0631 addi a2,a2,12 + 1c3a: 00090003 lb zero,0(s2) + 1c3e: 0100 addi s0,sp,128 + 1c40: 0305 addi t1,t1,1 + 1c42: 00090003 lb zero,0(s2) + 1c46: 0100 addi s0,sp,128 + 1c48: 0306 slli t1,t1,0x1 + 1c4a: 0901 addi s2,s2,0 + 1c4c: 0000 unimp + 1c4e: 0301 addi t1,t1,0 + 1c50: 0901 addi s2,s2,0 + 1c52: 0000 unimp + 1c54: 0501 addi a0,a0,0 + 1c56: 0616 slli a2,a2,0x5 + 1c58: 00090003 lb zero,0(s2) + 1c5c: 0100 addi s0,sp,128 + 1c5e: 1b05 addi s6,s6,-31 + 1c60: 00090003 lb zero,0(s2) + 1c64: 0100 addi s0,sp,128 + 1c66: 0605 addi a2,a2,1 + 1c68: 00090003 lb zero,0(s2) + 1c6c: 0100 addi s0,sp,128 + 1c6e: 0505 addi a0,a0,1 + 1c70: 0306 slli t1,t1,0x1 + 1c72: 0901 addi s2,s2,0 + 1c74: 0000 unimp + 1c76: 0601 addi a2,a2,0 + 1c78: 00090303 lb t1,0(s2) + 1c7c: 0100 addi s0,sp,128 + 1c7e: 0305 addi t1,t1,1 + 1c80: 0306 slli t1,t1,0x1 + 1c82: 0904 addi s1,sp,144 + 1c84: 0000 unimp + 1c86: 0301 addi t1,t1,0 + 1c88: 0902 c.slli64 s2 + 1c8a: 0000 unimp + 1c8c: 0501 addi a0,a0,0 + 1c8e: 00030607 .4byte 0x30607 + 1c92: 0009 c.nop 2 + 1c94: 0100 addi s0,sp,128 + 1c96: 0305 addi t1,t1,1 + 1c98: 0306 slli t1,t1,0x1 + 1c9a: 0901 addi s2,s2,0 + 1c9c: 0000 unimp + 1c9e: 0501 addi a0,a0,0 + 1ca0: 0346 slli t1,t1,0x11 + 1ca2: 0900 addi s0,sp,144 + 1ca4: 0000 unimp + 1ca6: 0501 addi a0,a0,0 + 1ca8: 09010303 lb t1,144(sp) + 1cac: 0000 unimp + 1cae: 0501 addi a0,a0,0 + 1cb0: 0346 slli t1,t1,0x11 + 1cb2: 0900 addi s0,sp,144 + 1cb4: 0000 unimp + 1cb6: 0501 addi a0,a0,0 + 1cb8: 09010303 lb t1,144(sp) + 1cbc: 0000 unimp + 1cbe: 0501 addi a0,a0,0 + 1cc0: 0346 slli t1,t1,0x11 + 1cc2: 0900 addi s0,sp,144 + 1cc4: 0000 unimp + 1cc6: 0501 addi a0,a0,0 + 1cc8: 09010303 lb t1,144(sp) + 1ccc: 0000 unimp + 1cce: 0501 addi a0,a0,0 + 1cd0: 0346 slli t1,t1,0x11 + 1cd2: 0900 addi s0,sp,144 + 1cd4: 0000 unimp + 1cd6: 0501 addi a0,a0,0 + 1cd8: 09010303 lb t1,144(sp) + 1cdc: 0000 unimp + 1cde: 0501 addi a0,a0,0 + 1ce0: 0346 slli t1,t1,0x11 + 1ce2: 0900 addi s0,sp,144 + 1ce4: 0000 unimp + 1ce6: 0501 addi a0,a0,0 + 1ce8: 09010303 lb t1,144(sp) + 1cec: 0000 unimp + 1cee: 0501 addi a0,a0,0 + 1cf0: 0346 slli t1,t1,0x11 + 1cf2: 0900 addi s0,sp,144 + 1cf4: 0000 unimp + 1cf6: 0501 addi a0,a0,0 + 1cf8: 09010303 lb t1,144(sp) + 1cfc: 0000 unimp + 1cfe: 0501 addi a0,a0,0 + 1d00: 0346 slli t1,t1,0x11 + 1d02: 0900 addi s0,sp,144 + 1d04: 0000 unimp + 1d06: 0501 addi a0,a0,0 + 1d08: 09010303 lb t1,144(sp) + 1d0c: 0000 unimp + 1d0e: 0501 addi a0,a0,0 + 1d10: 0346 slli t1,t1,0x11 + 1d12: 0900 addi s0,sp,144 + 1d14: 0000 unimp + 1d16: 0501 addi a0,a0,0 + 1d18: 09010303 lb t1,144(sp) + 1d1c: 0000 unimp + 1d1e: 0501 addi a0,a0,0 + 1d20: 0346 slli t1,t1,0x11 + 1d22: 0900 addi s0,sp,144 + 1d24: 0000 unimp + 1d26: 0501 addi a0,a0,0 + 1d28: 09010303 lb t1,144(sp) + 1d2c: 0000 unimp + 1d2e: 0501 addi a0,a0,0 + 1d30: 0346 slli t1,t1,0x11 + 1d32: 0900 addi s0,sp,144 + 1d34: 0000 unimp + 1d36: 0501 addi a0,a0,0 + 1d38: 09010303 lb t1,144(sp) + 1d3c: 0000 unimp + 1d3e: 0501 addi a0,a0,0 + 1d40: 0346 slli t1,t1,0x11 + 1d42: 0900 addi s0,sp,144 + 1d44: 0000 unimp + 1d46: 0501 addi a0,a0,0 + 1d48: 09010303 lb t1,144(sp) + 1d4c: 0000 unimp + 1d4e: 0501 addi a0,a0,0 + 1d50: 0346 slli t1,t1,0x11 + 1d52: 0900 addi s0,sp,144 + 1d54: 0000 unimp + 1d56: 0501 addi a0,a0,0 + 1d58: 09010303 lb t1,144(sp) + 1d5c: 0000 unimp + 1d5e: 0501 addi a0,a0,0 + 1d60: 0346 slli t1,t1,0x11 + 1d62: 0900 addi s0,sp,144 + 1d64: 0000 unimp + 1d66: 0501 addi a0,a0,0 + 1d68: 09010303 lb t1,144(sp) + 1d6c: 0000 unimp + 1d6e: 0501 addi a0,a0,0 + 1d70: 0346 slli t1,t1,0x11 + 1d72: 0900 addi s0,sp,144 + 1d74: 0000 unimp + 1d76: 0501 addi a0,a0,0 + 1d78: 09010303 lb t1,144(sp) + 1d7c: 0000 unimp + 1d7e: 0501 addi a0,a0,0 + 1d80: 0346 slli t1,t1,0x11 + 1d82: 0900 addi s0,sp,144 + 1d84: 0000 unimp + 1d86: 0501 addi a0,a0,0 + 1d88: 09010303 lb t1,144(sp) + 1d8c: 0000 unimp + 1d8e: 0501 addi a0,a0,0 + 1d90: 0346 slli t1,t1,0x11 + 1d92: 0900 addi s0,sp,144 + 1d94: 0000 unimp + 1d96: 0501 addi a0,a0,0 + 1d98: 0601 addi a2,a2,0 + 1d9a: 00090103 lb sp,0(s2) + 1d9e: 0100 addi s0,sp,128 + 1da0: 4605 li a2,1 + 1da2: 00097f03 .4byte 0x97f03 + 1da6: 0100 addi s0,sp,128 + 1da8: 0105 addi sp,sp,1 + 1daa: 00090103 lb sp,0(s2) + 1dae: 0100 addi s0,sp,128 + 1db0: 4605 li a2,1 + 1db2: 00097f03 .4byte 0x97f03 + 1db6: 0100 addi s0,sp,128 + 1db8: 0105 addi sp,sp,1 + 1dba: 00090103 lb sp,0(s2) + 1dbe: 0100 addi s0,sp,128 + 1dc0: 4605 li a2,1 + 1dc2: 00097f03 .4byte 0x97f03 + 1dc6: 0100 addi s0,sp,128 + 1dc8: 0505 addi a0,a0,1 + 1dca: 0306 slli t1,t1,0x1 + 1dcc: 7ed2 .2byte 0x7ed2 + 1dce: 0009 c.nop 2 + 1dd0: 0100 addi s0,sp,128 + 1dd2: 00093c03 .4byte 0x93c03 + 1dd6: 0100 addi s0,sp,128 + 1dd8: 00090a03 lb s4,0(s2) + 1ddc: 0100 addi s0,sp,128 + 1dde: 00090c03 lb s8,0(s2) + 1de2: 0100 addi s0,sp,128 + 1de4: 4305 li t1,1 + 1de6: 0306 slli t1,t1,0x1 + 1de8: 0900 addi s0,sp,144 + 1dea: 0000 unimp + 1dec: 0501 addi a0,a0,0 + 1dee: 0305 addi t1,t1,1 + 1df0: 0900 addi s0,sp,144 + 1df2: 0000 unimp + 1df4: 0601 addi a2,a2,0 + 1df6: 00090b03 lb s6,0(s2) + 1dfa: 0100 addi s0,sp,128 + 1dfc: 00090a03 lb s4,0(s2) + 1e00: 0100 addi s0,sp,128 + 1e02: 0a05 addi s4,s4,1 + 1e04: 00091f03 lh t5,0(s2) + 1e08: 0100 addi s0,sp,128 + 1e0a: 1f05 addi t5,t5,-31 + 1e0c: 0306 slli t1,t1,0x1 + 1e0e: 0900 addi s0,sp,144 + 1e10: 0000 unimp + 1e12: 0501 addi a0,a0,0 + 1e14: 0326 slli t1,t1,0x9 + 1e16: 0900 addi s0,sp,144 + 1e18: 0000 unimp + 1e1a: 0501 addi a0,a0,0 + 1e1c: 0349 addi t1,t1,18 + 1e1e: 0900 addi s0,sp,144 + 1e20: 0000 unimp + 1e22: 0501 addi a0,a0,0 + 1e24: 030d addi t1,t1,3 + 1e26: 0900 addi s0,sp,144 + 1e28: 0000 unimp + 1e2a: 0501 addi a0,a0,0 + 1e2c: 01030607 .4byte 0x1030607 + 1e30: 0009 c.nop 2 + 1e32: 0100 addi s0,sp,128 + 1e34: 00090303 lb t1,0(s2) + 1e38: 0100 addi s0,sp,128 + 1e3a: 0505 addi a0,a0,1 + 1e3c: 00090403 lb s0,0(s2) + 1e40: 0100 addi s0,sp,128 + 1e42: 00090a03 lb s4,0(s2) + 1e46: 0100 addi s0,sp,128 + 1e48: 0105 addi sp,sp,1 + 1e4a: 0306 slli t1,t1,0x1 + 1e4c: 00000917 auipc s2,0x0 + 1e50: 0901 addi s2,s2,0 # 1e4c <__RODATA_END__+0x37c> + 1e52: 0000 unimp + 1e54: 0100 addi s0,sp,128 + 1e56: 0501 addi a0,a0,0 + 1e58: 0026 c.slli zero,0x9 + 1e5a: 0205 addi tp,tp,1 # 1 + 1e5c: 0000 unimp + 1e5e: 0000 unimp + 1e60: 0104ee03 .4byte 0x104ee03 + 1e64: 0305 addi t1,t1,1 + 1e66: 00090203 lb tp,0(s2) + 1e6a: 0100 addi s0,sp,128 + 1e6c: 2605 jal 218c <__neorv32_ram_size+0x18c> + 1e6e: 0306 slli t1,t1,0x1 + 1e70: 097e slli s2,s2,0x1f + 1e72: 0000 unimp + 1e74: 0501 addi a0,a0,0 + 1e76: 09020307 .4byte 0x9020307 + 1e7a: 0000 unimp + 1e7c: 0501 addi a0,a0,0 + 1e7e: 0306 slli t1,t1,0x1 + 1e80: 0900 addi s0,sp,144 + 1e82: 0000 unimp + 1e84: 0501 addi a0,a0,0 + 1e86: 04030603 lb a2,64(t1) + 1e8a: 0009 c.nop 2 + 1e8c: 0100 addi s0,sp,128 + 1e8e: 0105 addi sp,sp,1 + 1e90: 0306 slli t1,t1,0x1 + 1e92: 0902 c.slli64 s2 + 1e94: 0000 unimp + 1e96: 0501 addi a0,a0,0 + 1e98: 097e0303 lb t1,151(t3) + 1e9c: 0000 unimp + 1e9e: 0501 addi a0,a0,0 + 1ea0: 0301 addi t1,t1,0 + 1ea2: 0902 c.slli64 s2 + 1ea4: 0000 unimp + 1ea6: 0501 addi a0,a0,0 + 1ea8: 097e0303 lb t1,151(t3) + 1eac: 0000 unimp + 1eae: 0501 addi a0,a0,0 + 1eb0: 0301 addi t1,t1,0 + 1eb2: 0902 c.slli64 s2 + 1eb4: 0000 unimp + 1eb6: 0501 addi a0,a0,0 + 1eb8: 097e0303 lb t1,151(t3) + 1ebc: 0000 unimp + 1ebe: 0501 addi a0,a0,0 + 1ec0: 0301 addi t1,t1,0 + 1ec2: 0902 c.slli64 s2 + 1ec4: 0000 unimp + 1ec6: 0901 addi s2,s2,0 + 1ec8: 0000 unimp + 1eca: 0100 addi s0,sp,128 + 1ecc: 0501 addi a0,a0,0 + 1ece: 02050023 sb zero,32(a0) + 1ed2: 0000 unimp + 1ed4: 0000 unimp + 1ed6: 0104fc03 .4byte 0x104fc03 + 1eda: 0305 addi t1,t1,1 + 1edc: 00090203 lb tp,0(s2) + 1ee0: 0100 addi s0,sp,128 + 1ee2: 2305 jal 2402 <__neorv32_ram_size+0x402> + 1ee4: 0306 slli t1,t1,0x1 + 1ee6: 097e slli s2,s2,0x1f + 1ee8: 0000 unimp + 1eea: 0501 addi a0,a0,0 + 1eec: 0312 slli t1,t1,0x4 + 1eee: 0902 c.slli64 s2 + 1ef0: 0000 unimp + 1ef2: 0501 addi a0,a0,0 + 1ef4: 097e0323 sb s7,134(t3) + 1ef8: 0000 unimp + 1efa: 0501 addi a0,a0,0 + 1efc: 0312 slli t1,t1,0x4 + 1efe: 0902 c.slli64 s2 + 1f00: 0000 unimp + 1f02: 0501 addi a0,a0,0 + 1f04: 0c030603 lb a2,192(t1) + 1f08: 0009 c.nop 2 + 1f0a: 0100 addi s0,sp,128 + 1f0c: 00090103 lb sp,0(s2) + 1f10: 0100 addi s0,sp,128 + 1f12: 00090103 lb sp,0(s2) + 1f16: 0100 addi s0,sp,128 + 1f18: 00090203 lb tp,0(s2) + 1f1c: 0100 addi s0,sp,128 + 1f1e: 0705 addi a4,a4,1 + 1f20: 0306 slli t1,t1,0x1 + 1f22: 0900 addi s0,sp,144 + 1f24: 0000 unimp + 1f26: 0501 addi a0,a0,0 + 1f28: 0306 slli t1,t1,0x1 + 1f2a: 0900 addi s0,sp,144 + 1f2c: 0000 unimp + 1f2e: 0501 addi a0,a0,0 + 1f30: 0305 addi t1,t1,1 + 1f32: 0905 addi s2,s2,1 + 1f34: 0000 unimp + 1f36: 0501 addi a0,a0,0 + 1f38: 0310 addi a2,sp,384 + 1f3a: 0901 addi s2,s2,0 + 1f3c: 0000 unimp + 1f3e: 0501 addi a0,a0,0 + 1f40: 0605 addi a2,a2,1 + 1f42: 00097f03 .4byte 0x97f03 + 1f46: 0100 addi s0,sp,128 + 1f48: 00090103 lb sp,0(s2) + 1f4c: 0100 addi s0,sp,128 + 1f4e: 1005 c.nop -31 + 1f50: 00090003 lb zero,0(s2) + 1f54: 0100 addi s0,sp,128 + 1f56: 0505 addi a0,a0,1 + 1f58: 0306 slli t1,t1,0x1 + 1f5a: 097f .2byte 0x97f + 1f5c: 0000 unimp + 1f5e: 0501 addi a0,a0,0 + 1f60: 0901030b .4byte 0x901030b + 1f64: 0000 unimp + 1f66: 0501 addi a0,a0,0 + 1f68: 01030607 .4byte 0x1030607 + 1f6c: 0009 c.nop 2 + 1f6e: 0100 addi s0,sp,128 + 1f70: 0b05 addi s6,s6,1 + 1f72: 0306 slli t1,t1,0x1 + 1f74: 0900 addi s0,sp,144 + 1f76: 0000 unimp + 1f78: 0501 addi a0,a0,0 + 1f7a: 01030607 .4byte 0x1030607 + 1f7e: 0009 c.nop 2 + 1f80: 0100 addi s0,sp,128 + 1f82: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 1f84: 00090003 lb zero,0(s2) + 1f88: 0100 addi s0,sp,128 + 1f8a: 0b05 addi s6,s6,1 + 1f8c: 0306 slli t1,t1,0x1 + 1f8e: 097f .2byte 0x97f + 1f90: 0000 unimp + 1f92: 0501 addi a0,a0,0 + 1f94: 0609 addi a2,a2,2 + 1f96: 00090203 lb tp,0(s2) + 1f9a: 0100 addi s0,sp,128 + 1f9c: 00090103 lb sp,0(s2) + 1fa0: 0100 addi s0,sp,128 + 1fa2: 0c05 addi s8,s8,1 + 1fa4: 0306 slli t1,t1,0x1 + 1fa6: 0900 addi s0,sp,144 + 1fa8: 0000 unimp + 1faa: 0501 addi a0,a0,0 + 1fac: 097f030b .4byte 0x97f030b + 1fb0: 0000 unimp + 1fb2: 0501 addi a0,a0,0 + 1fb4: 030c addi a1,sp,384 + 1fb6: 0901 addi s2,s2,0 + 1fb8: 0000 unimp + 1fba: 0501 addi a0,a0,0 + 1fbc: 030d addi t1,t1,3 + 1fbe: 0901 addi s2,s2,0 + 1fc0: 0000 unimp + 1fc2: 0501 addi a0,a0,0 + 1fc4: 0009 c.nop 2 + 1fc6: 0402 c.slli64 s0 + 1fc8: 0602 c.slli64 a2 + 1fca: 00090203 lb tp,0(s2) + 1fce: 0100 addi s0,sp,128 + 1fd0: 0d05 addi s10,s10,1 + 1fd2: 0200 addi s0,sp,256 + 1fd4: 0204 addi s1,sp,256 + 1fd6: 0306 slli t1,t1,0x1 + 1fd8: 0901 addi s2,s2,0 + 1fda: 0000 unimp + 1fdc: 0501 addi a0,a0,0 + 1fde: 0012 c.slli zero,0x4 + 1fe0: 0402 c.slli64 s0 + 1fe2: 0302 c.slli64 t1 + 1fe4: 097a slli s2,s2,0x1e + 1fe6: 0000 unimp + 1fe8: 0501 addi a0,a0,0 + 1fea: 0009 c.nop 2 + 1fec: 0402 c.slli64 s0 + 1fee: 0302 c.slli64 t1 + 1ff0: 0905 addi s2,s2,1 + 1ff2: 0000 unimp + 1ff4: 0001 nop + 1ff6: 0402 c.slli64 s0 + 1ff8: 0602 c.slli64 a2 + 1ffa: 00090103 lb sp,0(s2) + 1ffe: 0100 addi s0,sp,128 + 2000: 0d05 addi s10,s10,1 + 2002: 0200 addi s0,sp,256 + 2004: 0204 addi s1,sp,256 + 2006: 0306 slli t1,t1,0x1 + 2008: 0900 addi s0,sp,144 + 200a: 0000 unimp + 200c: 0501 addi a0,a0,0 + 200e: 0018 .2byte 0x18 + 2010: 0402 c.slli64 s0 + 2012: 0602 c.slli64 a2 + 2014: 00097a03 .4byte 0x97a03 + 2018: 0100 addi s0,sp,128 + 201a: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 201c: 0200 addi s0,sp,256 + 201e: 0204 addi s1,sp,256 + 2020: 00090003 lb zero,0(s2) + 2024: 0100 addi s0,sp,128 + 2026: 1505 addi a0,a0,-31 + 2028: 0200 addi s0,sp,256 + 202a: 0204 addi s1,sp,256 + 202c: 00097e03 .4byte 0x97e03 + 2030: 0100 addi s0,sp,128 + 2032: 1005 c.nop -31 + 2034: 0200 addi s0,sp,256 + 2036: 0204 addi s1,sp,256 + 2038: 00090003 lb zero,0(s2) + 203c: 0100 addi s0,sp,128 + 203e: 1305 addi t1,t1,-31 + 2040: 0200 addi s0,sp,256 + 2042: 0204 addi s1,sp,256 + 2044: 00097e03 .4byte 0x97e03 + 2048: 0100 addi s0,sp,128 + 204a: 0e05 addi t3,t3,1 + 204c: 0200 addi s0,sp,256 + 204e: 0204 addi s1,sp,256 + 2050: 00090003 lb zero,0(s2) + 2054: 0100 addi s0,sp,128 + 2056: 0305 addi t1,t1,1 + 2058: 00090e03 lb t3,0(s2) + 205c: 0100 addi s0,sp,128 + 205e: 0105 addi sp,sp,1 + 2060: 0306 slli t1,t1,0x1 + 2062: 0901 addi s2,s2,0 + 2064: 0000 unimp + 2066: 0501 addi a0,a0,0 + 2068: 097f0303 lb t1,151(t5) + 206c: 0000 unimp + 206e: 0501 addi a0,a0,0 + 2070: 0301 addi t1,t1,0 + 2072: 0901 addi s2,s2,0 + 2074: 0000 unimp + 2076: 0501 addi a0,a0,0 + 2078: 097f0303 lb t1,151(t5) + 207c: 0000 unimp + 207e: 0501 addi a0,a0,0 + 2080: 0301 addi t1,t1,0 + 2082: 0901 addi s2,s2,0 + 2084: 0000 unimp + 2086: 0901 addi s2,s2,0 + 2088: 0000 unimp + 208a: 0100 addi s0,sp,128 + 208c: 0501 addi a0,a0,0 + 208e: 0026 c.slli zero,0x9 + 2090: 0205 addi tp,tp,1 # 1 + 2092: 0000 unimp + 2094: 0000 unimp + 2096: 0105a703 lw a4,16(a1) + 209a: 0305 addi t1,t1,1 + 209c: 00090203 lb tp,0(s2) + 20a0: 0100 addi s0,sp,128 + 20a2: 2605 jal 23c2 <__neorv32_ram_size+0x3c2> + 20a4: 0306 slli t1,t1,0x1 + 20a6: 097e slli s2,s2,0x1f + 20a8: 0000 unimp + 20aa: 0501 addi a0,a0,0 + 20ac: 09020307 .4byte 0x9020307 + 20b0: 0000 unimp + 20b2: 0501 addi a0,a0,0 + 20b4: 0306 slli t1,t1,0x1 + 20b6: 0900 addi s0,sp,144 + 20b8: 0000 unimp + 20ba: 0501 addi a0,a0,0 + 20bc: 04030603 lb a2,64(t1) + 20c0: 0009 c.nop 2 + 20c2: 0100 addi s0,sp,128 + 20c4: 0105 addi sp,sp,1 + 20c6: 0306 slli t1,t1,0x1 + 20c8: 0920 addi s0,sp,152 + 20ca: 0000 unimp + 20cc: 0501 addi a0,a0,0 + 20ce: 09600303 lb t1,150(zero) # 96 <__crt0_copy_data+0x1a> + 20d2: 0000 unimp + 20d4: 0501 addi a0,a0,0 + 20d6: 0301 addi t1,t1,0 + 20d8: 0920 addi s0,sp,152 + 20da: 0000 unimp + 20dc: 0501 addi a0,a0,0 + 20de: 09600303 lb t1,150(zero) # 96 <__crt0_copy_data+0x1a> + 20e2: 0000 unimp + 20e4: 0501 addi a0,a0,0 + 20e6: 0301 addi t1,t1,0 + 20e8: 0920 addi s0,sp,152 + 20ea: 0000 unimp + 20ec: 0501 addi a0,a0,0 + 20ee: 09600303 lb t1,150(zero) # 96 <__crt0_copy_data+0x1a> + 20f2: 0000 unimp + 20f4: 0501 addi a0,a0,0 + 20f6: 0301 addi t1,t1,0 + 20f8: 0920 addi s0,sp,152 + 20fa: 0000 unimp + 20fc: 0901 addi s2,s2,0 + 20fe: 0000 unimp + 2100: 0100 addi s0,sp,128 + 2102: 0501 addi a0,a0,0 + 2104: 002d c.nop 11 + 2106: 0205 addi tp,tp,1 # 1 + 2108: 0000 unimp + 210a: 0000 unimp + 210c: 0105d503 lhu a0,16(a1) + 2110: 0305 addi t1,t1,1 + 2112: 00090203 lb tp,0(s2) + 2116: 0100 addi s0,sp,128 + 2118: 00091503 lh a0,0(s2) + 211c: 0100 addi s0,sp,128 + 211e: 00090c03 lb s8,0(s2) + 2122: 0100 addi s0,sp,128 + 2124: 00090703 lb a4,0(s2) + 2128: 0100 addi s0,sp,128 + 212a: 0105 addi sp,sp,1 + 212c: 0306 slli t1,t1,0x1 + 212e: 0901 addi s2,s2,0 + 2130: 0000 unimp + 2132: 0901 addi s2,s2,0 + 2134: 0000 unimp + 2136: 0100 addi s0,sp,128 + 2138: 0501 addi a0,a0,0 + 213a: 02050027 .4byte 0x2050027 + 213e: 08c4 addi s1,sp,84 + 2140: 0000 unimp + 2142: 01068903 lb s2,16(a3) + 2146: 0305 addi t1,t1,1 + 2148: 00090203 lb tp,0(s2) + 214c: 0100 addi s0,sp,128 + 214e: 00090103 lb sp,0(s2) + 2152: 0100 addi s0,sp,128 + 2154: 0204 addi s1,sp,256 + 2156: 097bca03 lbu s4,151(s7) + 215a: 0000 unimp + 215c: 0301 addi t1,t1,0 + 215e: 0902 c.slli64 s2 + 2160: 0000 unimp + 2162: 0301 addi t1,t1,0 + 2164: 0902 c.slli64 s2 + 2166: 0004 .2byte 0x4 + 2168: 0401 addi s0,s0,0 + 216a: 0301 addi t1,t1,0 + 216c: 04b5 addi s1,s1,13 + 216e: 0009 c.nop 2 + 2170: 0100 addi s0,sp,128 + 2172: 00090203 lb tp,0(s2) + 2176: 0100 addi s0,sp,128 + 2178: 0c05 addi s8,s8,1 + 217a: 0306 slli t1,t1,0x1 + 217c: 097e slli s2,s2,0x1f + 217e: 0000 unimp + 2180: 0501 addi a0,a0,0 + 2182: 0306 slli t1,t1,0x1 + 2184: 0902 c.slli64 s2 + 2186: 000c .2byte 0xc + 2188: 0501 addi a0,a0,0 + 218a: 0605 addi a2,a2,1 + 218c: 04090403 lb s0,64(s2) + 2190: 0100 addi s0,sp,128 + 2192: 0805 addi a6,a6,1 + 2194: 0306 slli t1,t1,0x1 + 2196: 0900 addi s0,sp,144 + 2198: 0000 unimp + 219a: 0501 addi a0,a0,0 + 219c: 04020027 .4byte 0x4020027 + 21a0: 0301 addi t1,t1,0 + 21a2: 0974 addi a3,sp,156 + 21a4: 0004 .2byte 0x4 + 21a6: 0501 addi a0,a0,0 + 21a8: 0402001b .4byte 0x402001b + 21ac: 0301 addi t1,t1,0 + 21ae: 090c addi a1,sp,144 + 21b0: 000c .2byte 0xc + 21b2: 0501 addi a0,a0,0 + 21b4: 04020017 auipc zero,0x4020 + 21b8: 0301 addi t1,t1,0 + 21ba: 0900 addi s0,sp,144 + 21bc: 0004 .2byte 0x4 + 21be: 0501 addi a0,a0,0 + 21c0: 01030607 .4byte 0x1030607 + 21c4: 1009 c.nop -30 + 21c6: 0100 addi s0,sp,128 + 21c8: 0105 addi sp,sp,1 + 21ca: 0306 slli t1,t1,0x1 + 21cc: 0906 slli s2,s2,0x1 + 21ce: 000c .2byte 0xc + 21d0: 0501 addi a0,a0,0 + 21d2: 030c addi a1,sp,384 + 21d4: 097e slli s2,s2,0x1f + 21d6: 0004 .2byte 0x4 + 21d8: 0501 addi a0,a0,0 + 21da: 0301 addi t1,t1,0 + 21dc: 0902 c.slli64 s2 + 21de: 0004 .2byte 0x4 + 21e0: 0501 addi a0,a0,0 + 21e2: 030c addi a1,sp,384 + 21e4: 0976 slli s2,s2,0x1d + 21e6: 0008 .2byte 0x8 + 21e8: 0301 addi t1,t1,0 + 21ea: 0908 addi a0,sp,144 + 21ec: 0008 .2byte 0x8 + 21ee: 0501 addi a0,a0,0 + 21f0: 0301 addi t1,t1,0 + 21f2: 0902 c.slli64 s2 + 21f4: 0004 .2byte 0x4 + 21f6: 0901 addi s2,s2,0 + 21f8: 0004 .2byte 0x4 + 21fa: 0100 addi s0,sp,128 + 21fc: a401 j 23fc <__neorv32_ram_size+0x3fc> + 21fe: 0015 c.nop 5 + 2200: 0500 addi s0,sp,640 + 2202: 0400 addi s0,sp,512 + 2204: 5200 lw s0,32(a2) + 2206: 0000 unimp + 2208: 0100 addi s0,sp,128 + 220a: 0101 addi sp,sp,0 + 220c: 000d0efb .4byte 0xd0efb + 2210: 0101 addi sp,sp,0 + 2212: 0101 addi sp,sp,0 + 2214: 0000 unimp + 2216: 0100 addi s0,sp,128 + 2218: 0000 unimp + 221a: 0101 addi sp,sp,0 + 221c: 1f01 addi t5,t5,-32 + 221e: 9806 add a6,a6,ra + 2220: 0001 nop + 2222: db00 sw s0,48(a4) + 2224: 0001 nop + 2226: 3c00 .2byte 0x3c00 + 2228: 0000 unimp + 222a: 6b00 .2byte 0x6b00 + 222c: 0000 unimp + 222e: f200 .2byte 0xf200 + 2230: 0001 nop + 2232: 9600 .2byte 0x9600 + 2234: 0000 unimp + 2236: 0200 addi s0,sp,256 + 2238: 1f01 addi t5,t5,-32 + 223a: 0f02 c.slli64 t5 + 223c: 5f06 lw t5,96(sp) + 223e: 0002 c.slli64 zero + 2240: 0100 addi s0,sp,128 + 2242: 025f 0000 0d01 .byte 0x5f, 0x02, 0x00, 0x00, 0x01, 0x0d + 2248: 0001 nop + 224a: 0200 addi s0,sp,256 + 224c: 011e slli sp,sp,0x7 + 224e: 0000 unimp + 2250: 00013103 .4byte 0x13103 + 2254: 0400 addi s0,sp,512 + 2256: 026e slli tp,tp,0x1b + 2258: 0000 unimp + 225a: 0505 addi a0,a0,1 + 225c: 0038 addi a4,sp,8 + 225e: 0205 addi tp,tp,1 # 1 + 2260: 0928 addi a0,sp,152 + 2262: 0000 unimp + 2264: 0106d003 lhu zero,16(a3) + 2268: 0305 addi t1,t1,1 + 226a: 00090203 lb tp,0(s2) + 226e: 0100 addi s0,sp,128 + 2270: 00090103 lb sp,0(s2) + 2274: 0100 addi s0,sp,128 + 2276: 00090103 lb sp,0(s2) + 227a: 0100 addi s0,sp,128 + 227c: 00090203 lb tp,0(s2) + 2280: 0100 addi s0,sp,128 + 2282: 00090103 lb sp,0(s2) + 2286: 0100 addi s0,sp,128 + 2288: 3805 jal 1ab8 + 228a: 0306 slli t1,t1,0x1 + 228c: 0979 addi s2,s2,30 + 228e: 0000 unimp + 2290: 0501 addi a0,a0,0 + 2292: 0319 addi t1,t1,6 + 2294: 0020090b .4byte 0x20090b + 2298: 0501 addi a0,a0,0 + 229a: 0338 addi a4,sp,392 + 229c: 0975 addi s2,s2,29 + 229e: 0004 .2byte 0x4 + 22a0: 0501 addi a0,a0,0 + 22a2: 0907030b .4byte 0x907030b + 22a6: 0008 .2byte 0x8 + 22a8: 0501 addi a0,a0,0 + 22aa: 03030603 lb a2,48(t1) + 22ae: 0409 addi s0,s0,2 + 22b0: 0100 addi s0,sp,128 + 22b2: 0e05 addi t3,t3,1 + 22b4: 00090003 lb zero,0(s2) + 22b8: 0100 addi s0,sp,128 + 22ba: 0b05 addi s6,s6,1 + 22bc: 0306 slli t1,t1,0x1 + 22be: 097d addi s2,s2,31 + 22c0: 0000 unimp + 22c2: 0501 addi a0,a0,0 + 22c4: 0310 addi a2,sp,384 + 22c6: 0904 addi s1,sp,144 + 22c8: 0004 .2byte 0x4 + 22ca: 0501 addi a0,a0,0 + 22cc: 0319 addi t1,t1,6 + 22ce: 0900 addi s0,sp,144 + 22d0: 0004 .2byte 0x4 + 22d2: 0501 addi a0,a0,0 + 22d4: 0005 c.nop 1 + 22d6: 0402 c.slli64 s0 + 22d8: 00030603 lb a2,0(t1) + 22dc: 0409 addi s0,s0,2 + 22de: 0100 addi s0,sp,128 + 22e0: 1b05 addi s6,s6,-31 + 22e2: 0200 addi s0,sp,256 + 22e4: 0304 addi s1,sp,384 + 22e6: 0306 slli t1,t1,0x1 + 22e8: 0900 addi s0,sp,144 + 22ea: 0000 unimp + 22ec: 0501 addi a0,a0,0 + 22ee: 0019 c.nop 6 + 22f0: 0402 c.slli64 s0 + 22f2: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 22f6: 000c .2byte 0xc + 22f8: 0501 addi a0,a0,0 + 22fa: 0010 .2byte 0x10 + 22fc: 0402 c.slli64 s0 + 22fe: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 2302: 0004 .2byte 0x4 + 2304: 0501 addi a0,a0,0 + 2306: 04020007 .4byte 0x4020007 + 230a: 09010303 lb t1,144(sp) + 230e: 0008 .2byte 0x8 + 2310: 0501 addi a0,a0,0 + 2312: 0010 .2byte 0x10 + 2314: 0402 c.slli64 s0 + 2316: 097f0303 lb t1,151(t5) + 231a: 0004 .2byte 0x4 + 231c: 0501 addi a0,a0,0 + 231e: 0005 c.nop 1 + 2320: 0402 c.slli64 s0 + 2322: 01030603 lb a2,16(t1) + 2326: 0409 addi s0,s0,2 + 2328: 0100 addi s0,sp,128 + 232a: 0705 addi a4,a4,1 + 232c: 0200 addi s0,sp,256 + 232e: 0304 addi s1,sp,384 + 2330: 0306 slli t1,t1,0x1 + 2332: 0900 addi s0,sp,144 + 2334: 0000 unimp + 2336: 0501 addi a0,a0,0 + 2338: 000e c.slli zero,0x3 + 233a: 0402 c.slli64 s0 + 233c: 097e0303 lb t1,151(t3) + 2340: 0008 .2byte 0x8 + 2342: 0501 addi a0,a0,0 + 2344: 04020007 .4byte 0x4020007 + 2348: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 234c: 0008 .2byte 0x8 + 234e: 0501 addi a0,a0,0 + 2350: 0014 .2byte 0x14 + 2352: 0402 c.slli64 s0 + 2354: 7e030603 lb a2,2016(t1) + 2358: 0409 addi s0,s0,2 + 235a: 0100 addi s0,sp,128 + 235c: 0e05 addi t3,t3,1 + 235e: 0200 addi s0,sp,256 + 2360: 0304 addi s1,sp,384 + 2362: 00090003 lb zero,0(s2) + 2366: 0100 addi s0,sp,128 + 2368: 0306 slli t1,t1,0x1 + 236a: 0900 addi s0,sp,144 + 236c: 0004 .2byte 0x4 + 236e: 0501 addi a0,a0,0 + 2370: 0309 addi t1,t1,2 + 2372: 0906 slli s2,s2,0x1 + 2374: 0004 .2byte 0x4 + 2376: 0501 addi a0,a0,0 + 2378: 0308 addi a0,sp,384 + 237a: 0901 addi s2,s2,0 + 237c: 0004 .2byte 0x4 + 237e: 0501 addi a0,a0,0 + 2380: 0605 addi a2,a2,1 + 2382: 04090003 lb zero,64(s2) + 2386: 0100 addi s0,sp,128 + 2388: 0805 addi a6,a6,1 + 238a: 0306 slli t1,t1,0x1 + 238c: 0900 addi s0,sp,144 + 238e: 0000 unimp + 2390: 0501 addi a0,a0,0 + 2392: 0314 addi a3,sp,384 + 2394: 097f .2byte 0x97f + 2396: 0008 .2byte 0x8 + 2398: 0501 addi a0,a0,0 + 239a: 0308 addi a0,sp,384 + 239c: 0901 addi s2,s2,0 + 239e: 000c .2byte 0xc + 23a0: 0501 addi a0,a0,0 + 23a2: 04020007 .4byte 0x4020007 + 23a6: 0602 c.slli64 a2 + 23a8: 04090103 lb sp,64(s2) + 23ac: 0100 addi s0,sp,128 + 23ae: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 23b0: 0200 addi s0,sp,256 + 23b2: 0204 addi s1,sp,256 + 23b4: 0306 slli t1,t1,0x1 + 23b6: 0900 addi s0,sp,144 + 23b8: 0000 unimp + 23ba: 0501 addi a0,a0,0 + 23bc: 0014 .2byte 0x14 + 23be: 0402 c.slli64 s0 + 23c0: 0602 c.slli64 a2 + 23c2: 04097e03 .4byte 0x4097e03 + 23c6: 0100 addi s0,sp,128 + 23c8: 0e05 addi t3,t3,1 + 23ca: 0200 addi s0,sp,256 + 23cc: 0204 addi s1,sp,256 + 23ce: 00090003 lb zero,0(s2) + 23d2: 0100 addi s0,sp,128 + 23d4: 0305 addi t1,t1,1 + 23d6: 14090903 lb s2,320(s2) + 23da: 0100 addi s0,sp,128 + 23dc: 0505 addi a0,a0,1 + 23de: 00090103 lb sp,0(s2) + 23e2: 0100 addi s0,sp,128 + 23e4: 1005 c.nop -31 + 23e6: 0306 slli t1,t1,0x1 + 23e8: 0900 addi s0,sp,144 + 23ea: 0000 unimp + 23ec: 0501 addi a0,a0,0 + 23ee: 0308 addi a0,sp,384 + 23f0: 0900 addi s0,sp,144 + 23f2: 0004 .2byte 0x4 + 23f4: 0501 addi a0,a0,0 + 23f6: 01030607 .4byte 0x1030607 + 23fa: 0409 addi s0,s0,2 + 23fc: 0100 addi s0,sp,128 + 23fe: 0c05 addi s8,s8,1 + 2400: 0306 slli t1,t1,0x1 + 2402: 0900 addi s0,sp,144 + 2404: 0000 unimp + 2406: 0501 addi a0,a0,0 + 2408: 0310 addi a2,sp,384 + 240a: 0900 addi s0,sp,144 + 240c: 0004 .2byte 0x4 + 240e: 0501 addi a0,a0,0 + 2410: 030c addi a1,sp,384 + 2412: 0900 addi s0,sp,144 + 2414: 0008 .2byte 0x8 + 2416: 0601 addi a2,a2,0 + 2418: 08090103 lb sp,128(s2) + 241c: 0100 addi s0,sp,128 + 241e: 0305 addi t1,t1,1 + 2420: 08090203 lb tp,128(s2) + 2424: 0100 addi s0,sp,128 + 2426: 0a05 addi s4,s4,1 + 2428: 0306 slli t1,t1,0x1 + 242a: 0900 addi s0,sp,144 + 242c: 0000 unimp + 242e: 0501 addi a0,a0,0 + 2430: 0301 addi t1,t1,0 + 2432: 0901 addi s2,s2,0 + 2434: 0008 .2byte 0x8 + 2436: 0901 addi s2,s2,0 + 2438: 002c addi a1,sp,8 + 243a: 0100 addi s0,sp,128 + 243c: 0501 addi a0,a0,0 + 243e: 0039 c.nop 14 + 2440: 0205 addi tp,tp,1 # 1 + 2442: 0a30 addi a2,sp,280 + 2444: 0000 unimp + 2446: 0106f803 .4byte 0x106f803 + 244a: 0305 addi t1,t1,1 + 244c: 00090203 lb tp,0(s2) + 2450: 0100 addi s0,sp,128 + 2452: 00090203 lb tp,0(s2) + 2456: 0100 addi s0,sp,128 + 2458: 00090103 lb sp,0(s2) + 245c: 0100 addi s0,sp,128 + 245e: 0e05 addi t3,t3,1 + 2460: 00090003 lb zero,0(s2) + 2464: 0100 addi s0,sp,128 + 2466: 1d05 addi s10,s10,-31 + 2468: 0306 slli t1,t1,0x1 + 246a: 0902 c.slli64 s2 + 246c: 0000 unimp + 246e: 0501 addi a0,a0,0 + 2470: 0339 addi t1,t1,14 + 2472: 0979 addi s2,s2,30 + 2474: 0008 .2byte 0x8 + 2476: 0501 addi a0,a0,0 + 2478: 031d addi t1,t1,7 + 247a: 00040907 .4byte 0x40907 + 247e: 0501 addi a0,a0,0 + 2480: 030e slli t1,t1,0x3 + 2482: 097e slli s2,s2,0x1f + 2484: 0004 .2byte 0x4 + 2486: 0501 addi a0,a0,0 + 2488: 0005 c.nop 1 + 248a: 0402 c.slli64 s0 + 248c: 01030603 lb a2,16(t1) + 2490: 0409 addi s0,s0,2 + 2492: 0100 addi s0,sp,128 + 2494: 0200 addi s0,sp,256 + 2496: 0304 addi s1,sp,384 + 2498: 00090103 lb sp,0(s2) + 249c: 0100 addi s0,sp,128 + 249e: 0e05 addi t3,t3,1 + 24a0: 0200 addi s0,sp,256 + 24a2: 0304 addi s1,sp,384 + 24a4: 0306 slli t1,t1,0x1 + 24a6: 097f .2byte 0x97f + 24a8: 0000 unimp + 24aa: 0501 addi a0,a0,0 + 24ac: 0026 c.slli zero,0x9 + 24ae: 0402 c.slli64 s0 + 24b0: 09010303 lb t1,144(sp) + 24b4: 0004 .2byte 0x4 + 24b6: 0501 addi a0,a0,0 + 24b8: 001d c.nop 7 + 24ba: 0402 c.slli64 s0 + 24bc: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 24c0: 0004 .2byte 0x4 + 24c2: 0501 addi a0,a0,0 + 24c4: 000e c.slli zero,0x3 + 24c6: 0402 c.slli64 s0 + 24c8: 09000303 lb t1,144(zero) # 90 <__crt0_copy_data+0x14> + 24cc: 0004 .2byte 0x4 + 24ce: 0001 nop + 24d0: 0402 c.slli64 s0 + 24d2: 097e0303 lb t1,151(t3) + 24d6: 0004 .2byte 0x4 + 24d8: 0001 nop + 24da: 0402 c.slli64 s0 + 24dc: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 24e0: 0008 .2byte 0x8 + 24e2: 0501 addi a0,a0,0 + 24e4: 04020013 addi zero,tp,64 # 40 + 24e8: 7e030603 lb a2,2016(t1) + 24ec: 0409 addi s0,s0,2 + 24ee: 0100 addi s0,sp,128 + 24f0: 0e05 addi t3,t3,1 + 24f2: 0200 addi s0,sp,256 + 24f4: 0304 addi s1,sp,384 + 24f6: 00090003 lb zero,0(s2) + 24fa: 0100 addi s0,sp,128 + 24fc: 0305 addi t1,t1,1 + 24fe: 04090503 lb a0,64(s2) + 2502: 0100 addi s0,sp,128 + 2504: 0a05 addi s4,s4,1 + 2506: 0306 slli t1,t1,0x1 + 2508: 0900 addi s0,sp,144 + 250a: 0000 unimp + 250c: 0501 addi a0,a0,0 + 250e: 0301 addi t1,t1,0 + 2510: 0901 addi s2,s2,0 + 2512: 0004 .2byte 0x4 + 2514: 0901 addi s2,s2,0 + 2516: 0004 .2byte 0x4 + 2518: 0100 addi s0,sp,128 + 251a: 0501 addi a0,a0,0 + 251c: 000d c.nop 3 + 251e: 0205 addi tp,tp,1 # 1 + 2520: 0a6c addi a1,sp,284 + 2522: 0000 unimp + 2524: 01078c03 lb s8,16(a5) + 2528: 0e05 addi t3,t3,1 + 252a: 00090403 lb s0,0(s2) + 252e: 0100 addi s0,sp,128 + 2530: 0805 addi a6,a6,1 + 2532: 0306 slli t1,t1,0x1 + 2534: 0902 c.slli64 s2 + 2536: 0004 .2byte 0x4 + 2538: 0501 addi a0,a0,0 + 253a: 0605 addi a2,a2,1 + 253c: 04097f03 .4byte 0x4097f03 + 2540: 0100 addi s0,sp,128 + 2542: 0905 addi s2,s2,1 + 2544: 0306 slli t1,t1,0x1 + 2546: 0900 addi s0,sp,144 + 2548: 0000 unimp + 254a: 0501 addi a0,a0,0 + 254c: 0605 addi a2,a2,1 + 254e: 04090103 lb sp,64(s2) + 2552: 0100 addi s0,sp,128 + 2554: 1605 addi a2,a2,-31 + 2556: 0306 slli t1,t1,0x1 + 2558: 0900 addi s0,sp,144 + 255a: 0000 unimp + 255c: 0501 addi a0,a0,0 + 255e: 0308 addi a0,sp,384 + 2560: 0900 addi s0,sp,144 + 2562: 0004 .2byte 0x4 + 2564: 0501 addi a0,a0,0 + 2566: 01030607 .4byte 0x1030607 + 256a: 0809 addi a6,a6,2 + 256c: 0100 addi s0,sp,128 + 256e: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 2570: 0306 slli t1,t1,0x1 + 2572: 0900 addi s0,sp,144 + 2574: 0000 unimp + 2576: 0501 addi a0,a0,0 + 2578: 030c addi a1,sp,384 + 257a: 0900 addi s0,sp,144 + 257c: 0004 .2byte 0x4 + 257e: 0501 addi a0,a0,0 + 2580: 0605 addi a2,a2,1 + 2582: 04090203 lb tp,64(s2) + 2586: 0100 addi s0,sp,128 + 2588: 0805 addi a6,a6,1 + 258a: 0306 slli t1,t1,0x1 + 258c: 0900 addi s0,sp,144 + 258e: 0000 unimp + 2590: 0501 addi a0,a0,0 + 2592: 0605 addi a2,a2,1 + 2594: 04090103 lb sp,64(s2) + 2598: 0100 addi s0,sp,128 + 259a: 0e05 addi t3,t3,1 + 259c: 00097a03 .4byte 0x97a03 + 25a0: 0100 addi s0,sp,128 + 25a2: 0105 addi sp,sp,1 + 25a4: 0306 slli t1,t1,0x1 + 25a6: 0908 addi a0,sp,144 + 25a8: 0004 .2byte 0x4 + 25aa: 0901 addi s2,s2,0 + 25ac: 0004 .2byte 0x4 + 25ae: 0100 addi s0,sp,128 + 25b0: 0501 addi a0,a0,0 + 25b2: 02050023 sb zero,32(a0) + 25b6: 0a98 addi a4,sp,336 + 25b8: 0000 unimp + 25ba: 0100de03 lhu t3,16(ra) + 25be: 0305 addi t1,t1,1 + 25c0: 00090203 lb tp,0(s2) + 25c4: 0100 addi s0,sp,128 + 25c6: 1605 addi a2,a2,-31 + 25c8: 0306 slli t1,t1,0x1 + 25ca: 0900 addi s0,sp,144 + 25cc: 0000 unimp + 25ce: 0501 addi a0,a0,0 + 25d0: 0306 slli t1,t1,0x1 + 25d2: 0900 addi s0,sp,144 + 25d4: 0004 .2byte 0x4 + 25d6: 0501 addi a0,a0,0 + 25d8: 0301 addi t1,t1,0 + 25da: 0906 slli s2,s2,0x1 + 25dc: 0004 .2byte 0x4 + 25de: 0901 addi s2,s2,0 + 25e0: 0008 .2byte 0x8 + 25e2: 0100 addi s0,sp,128 + 25e4: 0501 addi a0,a0,0 + 25e6: 0205004f .4byte 0x205004f + 25ea: 0aa8 addi a0,sp,344 + 25ec: 0000 unimp + 25ee: 0100f503 .4byte 0x100f503 + 25f2: 0305 addi t1,t1,1 + 25f4: 00090203 lb tp,0(s2) + 25f8: 0100 addi s0,sp,128 + 25fa: 4f05 li t5,1 + 25fc: 0306 slli t1,t1,0x1 + 25fe: 097e slli s2,s2,0x1f + 2600: 0000 unimp + 2602: 0501 addi a0,a0,0 + 2604: 0316 slli t1,t1,0x5 + 2606: 0902 c.slli64 s2 + 2608: 0010 .2byte 0x10 + 260a: 0501 addi a0,a0,0 + 260c: 02030603 lb a2,32(t1) + 2610: 0409 addi s0,s0,2 + 2612: 0100 addi s0,sp,128 + 2614: 0c05 addi s8,s8,1 + 2616: 0306 slli t1,t1,0x1 + 2618: 0900 addi s0,sp,144 + 261a: 0000 unimp + 261c: 0501 addi a0,a0,0 + 261e: 01030603 lb a2,16(t1) + 2622: 0409 addi s0,s0,2 + 2624: 0100 addi s0,sp,128 + 2626: 00090103 lb sp,0(s2) + 262a: 0100 addi s0,sp,128 + 262c: 00090503 lb a0,0(s2) + 2630: 0100 addi s0,sp,128 + 2632: 4f05 li t5,1 + 2634: 0306 slli t1,t1,0x1 + 2636: 0975 addi s2,s2,29 + 2638: 0000 unimp + 263a: 0501 addi a0,a0,0 + 263c: 0318 addi a4,sp,384 + 263e: 0004090b .4byte 0x4090b + 2642: 0501 addi a0,a0,0 + 2644: 0975034f .4byte 0x975034f + 2648: 0008 .2byte 0x8 + 264a: 0501 addi a0,a0,0 + 264c: 0318 addi a4,sp,384 + 264e: 0004090b .4byte 0x4090b + 2652: 0501 addi a0,a0,0 + 2654: 0305 addi t1,t1,1 + 2656: 0900 addi s0,sp,144 + 2658: 0004 .2byte 0x4 + 265a: 0501 addi a0,a0,0 + 265c: 030c addi a1,sp,384 + 265e: 090a slli s2,s2,0x2 + 2660: 0004 .2byte 0x4 + 2662: 0501 addi a0,a0,0 + 2664: 0305 addi t1,t1,1 + 2666: 0976 slli s2,s2,0x1d + 2668: 0004 .2byte 0x4 + 266a: 0501 addi a0,a0,0 + 266c: 0a030603 lb a2,160(t1) + 2670: 0409 addi s0,s0,2 + 2672: 0100 addi s0,sp,128 + 2674: 0b05 addi s6,s6,1 + 2676: 0306 slli t1,t1,0x1 + 2678: 0971 addi s2,s2,28 + 267a: 0000 unimp + 267c: 0501 addi a0,a0,0 + 267e: 030c addi a1,sp,384 + 2680: 0004090f .4byte 0x4090f + 2684: 0601 addi a2,a2,0 + 2686: 04090003 lb zero,64(s2) + 268a: 0100 addi s0,sp,128 + 268c: 0305 addi t1,t1,1 + 268e: 04090803 lb a6,64(s2) + 2692: 0100 addi s0,sp,128 + 2694: 00090103 lb sp,0(s2) + 2698: 0100 addi s0,sp,128 + 269a: 00090203 lb tp,0(s2) + 269e: 0100 addi s0,sp,128 + 26a0: 00090103 lb sp,0(s2) + 26a4: 0100 addi s0,sp,128 + 26a6: 00090103 lb sp,0(s2) + 26aa: 0100 addi s0,sp,128 + 26ac: 00090203 lb tp,0(s2) + 26b0: 0100 addi s0,sp,128 + 26b2: 00090103 lb sp,0(s2) + 26b6: 0100 addi s0,sp,128 + 26b8: 00090203 lb tp,0(s2) + 26bc: 0100 addi s0,sp,128 + 26be: 0c05 addi s8,s8,1 + 26c0: 0306 slli t1,t1,0x1 + 26c2: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 26c6: 0501 addi a0,a0,0 + 26c8: 0310 addi a2,sp,384 + 26ca: 0901 addi s2,s2,0 + 26cc: 0004 .2byte 0x4 + 26ce: 0501 addi a0,a0,0 + 26d0: 030c addi a1,sp,384 + 26d2: 097c addi a5,sp,156 + 26d4: 0004 .2byte 0x4 + 26d6: 0501 addi a0,a0,0 + 26d8: 01030603 lb a2,16(t1) + 26dc: 0409 addi s0,s0,2 + 26de: 0100 addi s0,sp,128 + 26e0: 00090203 lb tp,0(s2) + 26e4: 0100 addi s0,sp,128 + 26e6: 00090103 lb sp,0(s2) + 26ea: 0100 addi s0,sp,128 + 26ec: 00090b03 lb s6,0(s2) + 26f0: 0100 addi s0,sp,128 + 26f2: 00090303 lb t1,0(s2) + 26f6: 0100 addi s0,sp,128 + 26f8: 0d05 addi s10,s10,1 + 26fa: 0306 slli t1,t1,0x1 + 26fc: 0968 addi a0,sp,156 + 26fe: 0000 unimp + 2700: 0501 addi a0,a0,0 + 2702: 0352 slli t1,t1,0x14 + 2704: 0918 addi a4,sp,144 + 2706: 0004 .2byte 0x4 + 2708: 0501 addi a0,a0,0 + 270a: 0311 addi t1,t1,4 + 270c: 0004096f jal s2,4270c <__neorv32_ram_size+0x4070c> + 2710: 0501 addi a0,a0,0 + 2712: 0352 slli t1,t1,0x14 + 2714: 0911 addi s2,s2,4 + 2716: 0004 .2byte 0x4 + 2718: 0501 addi a0,a0,0 + 271a: 030c addi a1,sp,384 + 271c: 0965 addi s2,s2,25 + 271e: 0004 .2byte 0x4 + 2720: 0501 addi a0,a0,0 + 2722: 0301 addi t1,t1,0 + 2724: 091c addi a5,sp,144 + 2726: 0004 .2byte 0x4 + 2728: 0501 addi a0,a0,0 + 272a: 0352 slli t1,t1,0x14 + 272c: 097f .2byte 0x97f + 272e: 0008 .2byte 0x8 + 2730: 0501 addi a0,a0,0 + 2732: 0316 slli t1,t1,0x5 + 2734: 0900 addi s0,sp,144 + 2736: 000c .2byte 0xc + 2738: 0501 addi a0,a0,0 + 273a: 0301 addi t1,t1,0 + 273c: 0901 addi s2,s2,0 + 273e: 0004 .2byte 0x4 + 2740: 0501 addi a0,a0,0 + 2742: 0605 addi a2,a2,1 + 2744: 0c095c03 lhu s8,192(s2) + 2748: 0100 addi s0,sp,128 + 274a: 0805 addi a6,a6,1 + 274c: 0306 slli t1,t1,0x1 + 274e: 0900 addi s0,sp,144 + 2750: 0000 unimp + 2752: 0501 addi a0,a0,0 + 2754: 01030607 .4byte 0x1030607 + 2758: 0c09 addi s8,s8,2 + 275a: 0100 addi s0,sp,128 + 275c: 0905 addi s2,s2,1 + 275e: 0306 slli t1,t1,0x1 + 2760: 0900 addi s0,sp,144 + 2762: 0000 unimp + 2764: 0501 addi a0,a0,0 + 2766: 0605 addi a2,a2,1 + 2768: 04090303 lb t1,64(s2) + 276c: 0100 addi s0,sp,128 + 276e: 0605 addi a2,a2,1 + 2770: 0306 slli t1,t1,0x1 + 2772: 0900 addi s0,sp,144 + 2774: 0000 unimp + 2776: 0501 addi a0,a0,0 + 2778: 7f030607 .4byte 0x7f030607 + 277c: 0c09 addi s8,s8,2 + 277e: 0100 addi s0,sp,128 + 2780: 0905 addi s2,s2,1 + 2782: 0306 slli t1,t1,0x1 + 2784: 0900 addi s0,sp,144 + 2786: 0000 unimp + 2788: 0901 addi s2,s2,0 + 278a: 0008 .2byte 0x8 + 278c: 0100 addi s0,sp,128 + 278e: 0501 addi a0,a0,0 + 2790: 0022 c.slli zero,0x8 + 2792: 0205 addi tp,tp,1 # 1 + 2794: 0000 unimp + 2796: 0000 unimp + 2798: 0101b503 .4byte 0x101b503 + 279c: 0305 addi t1,t1,1 + 279e: 00090203 lb tp,0(s2) + 27a2: 0100 addi s0,sp,128 + 27a4: 1005 c.nop -31 + 27a6: 0306 slli t1,t1,0x1 + 27a8: 0900 addi s0,sp,144 + 27aa: 0000 unimp + 27ac: 0501 addi a0,a0,0 + 27ae: 0316 slli t1,t1,0x5 + 27b0: 0900 addi s0,sp,144 + 27b2: 0000 unimp + 27b4: 0501 addi a0,a0,0 + 27b6: 0301 addi t1,t1,0 + 27b8: 0901 addi s2,s2,0 + 27ba: 0000 unimp + 27bc: 0901 addi s2,s2,0 + 27be: 0000 unimp + 27c0: 0100 addi s0,sp,128 + 27c2: 0501 addi a0,a0,0 + 27c4: 0021 c.nop 8 + 27c6: 0205 addi tp,tp,1 # 1 + 27c8: 0000 unimp + 27ca: 0000 unimp + 27cc: 0101be03 .4byte 0x101be03 + 27d0: 0305 addi t1,t1,1 + 27d2: 00090203 lb tp,0(s2) + 27d6: 0100 addi s0,sp,128 + 27d8: 1005 c.nop -31 + 27da: 0306 slli t1,t1,0x1 + 27dc: 0900 addi s0,sp,144 + 27de: 0000 unimp + 27e0: 0501 addi a0,a0,0 + 27e2: 0316 slli t1,t1,0x5 + 27e4: 0900 addi s0,sp,144 + 27e6: 0000 unimp + 27e8: 0501 addi a0,a0,0 + 27ea: 0301 addi t1,t1,0 + 27ec: 0901 addi s2,s2,0 + 27ee: 0000 unimp + 27f0: 0901 addi s2,s2,0 + 27f2: 0000 unimp + 27f4: 0100 addi s0,sp,128 + 27f6: 0501 addi a0,a0,0 + 27f8: 0021 c.nop 8 + 27fa: 0205 addi tp,tp,1 # 1 + 27fc: 0b54 addi a3,sp,404 + 27fe: 0000 unimp + 2800: 0101cb03 lbu s6,16(gp) # 80001050 <__global_pointer$+0x10> + 2804: 0305 addi t1,t1,1 + 2806: 00090303 lb t1,0(s2) + 280a: 0100 addi s0,sp,128 + 280c: 1e05 addi t3,t3,-31 + 280e: 0306 slli t1,t1,0x1 + 2810: 0900 addi s0,sp,144 + 2812: 0000 unimp + 2814: 0501 addi a0,a0,0 + 2816: 0038 addi a4,sp,8 + 2818: 0402 c.slli64 s0 + 281a: 0601 addi a2,a2,0 + 281c: 04090003 lb zero,64(s2) + 2820: 0100 addi s0,sp,128 + 2822: 1805 addi a6,a6,-31 + 2824: 0200 addi s0,sp,256 + 2826: 0104 addi s1,sp,128 + 2828: 0306 slli t1,t1,0x1 + 282a: 0900 addi s0,sp,144 + 282c: 0000 unimp + 282e: 0501 addi a0,a0,0 + 2830: 001e c.slli zero,0x7 + 2832: 0402 c.slli64 s0 + 2834: 0301 addi t1,t1,0 + 2836: 0900 addi s0,sp,144 + 2838: 0004 .2byte 0x4 + 283a: 0501 addi a0,a0,0 + 283c: 0038 addi a4,sp,8 + 283e: 0402 c.slli64 s0 + 2840: 0301 addi t1,t1,0 + 2842: 0900 addi s0,sp,144 + 2844: 0004 .2byte 0x4 + 2846: 0501 addi a0,a0,0 + 2848: 01030603 lb a2,16(t1) + 284c: 0409 addi s0,s0,2 + 284e: 0100 addi s0,sp,128 + 2850: 1605 addi a2,a2,-31 + 2852: 0306 slli t1,t1,0x1 + 2854: 0900 addi s0,sp,144 + 2856: 0000 unimp + 2858: 0501 addi a0,a0,0 + 285a: 0301 addi t1,t1,0 + 285c: 0901 addi s2,s2,0 + 285e: 0004 .2byte 0x4 + 2860: 0901 addi s2,s2,0 + 2862: 0004 .2byte 0x4 + 2864: 0100 addi s0,sp,128 + 2866: 0501 addi a0,a0,0 + 2868: 0015 c.nop 5 + 286a: 0205 addi tp,tp,1 # 1 + 286c: 0000 unimp + 286e: 0000 unimp + 2870: 0100c303 lbu t1,16(ra) + 2874: 0305 addi t1,t1,1 + 2876: 00090203 lb tp,0(s2) + 287a: 0100 addi s0,sp,128 + 287c: 1505 addi a0,a0,-31 + 287e: 0306 slli t1,t1,0x1 + 2880: 097e slli s2,s2,0x1f + 2882: 0000 unimp + 2884: 0501 addi a0,a0,0 + 2886: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 288a: 0000 unimp + 288c: 0501 addi a0,a0,0 + 288e: 0315 addi t1,t1,5 + 2890: 097e slli s2,s2,0x1f + 2892: 0000 unimp + 2894: 0501 addi a0,a0,0 + 2896: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 289a: 0000 unimp + 289c: 0601 addi a2,a2,0 + 289e: 00090103 lb sp,0(s2) + 28a2: 0100 addi s0,sp,128 + 28a4: 0105 addi sp,sp,1 + 28a6: 0306 slli t1,t1,0x1 + 28a8: 0901 addi s2,s2,0 + 28aa: 0000 unimp + 28ac: 0901 addi s2,s2,0 + 28ae: 0000 unimp + 28b0: 0100 addi s0,sp,128 + 28b2: 0501 addi a0,a0,0 + 28b4: 0021 c.nop 8 + 28b6: 0205 addi tp,tp,1 # 1 + 28b8: 0000 unimp + 28ba: 0000 unimp + 28bc: 0101da03 lhu s4,16(gp) # 80001050 <__global_pointer$+0x10> + 28c0: 0305 addi t1,t1,1 + 28c2: 00090203 lb tp,0(s2) + 28c6: 0100 addi s0,sp,128 + 28c8: 0c05 addi s8,s8,1 + 28ca: 0306 slli t1,t1,0x1 + 28cc: 0900 addi s0,sp,144 + 28ce: 0000 unimp + 28d0: 0501 addi a0,a0,0 + 28d2: 02030603 lb a2,32(t1) + 28d6: 0009 c.nop 2 + 28d8: 0100 addi s0,sp,128 + 28da: 0c05 addi s8,s8,1 + 28dc: 0306 slli t1,t1,0x1 + 28de: 0902 c.slli64 s2 + 28e0: 0000 unimp + 28e2: 0501 addi a0,a0,0 + 28e4: 0306 slli t1,t1,0x1 + 28e6: 097e slli s2,s2,0x1f + 28e8: 0000 unimp + 28ea: 0501 addi a0,a0,0 + 28ec: 002e c.slli zero,0xb + 28ee: 0402 c.slli64 s0 + 28f0: 0301 addi t1,t1,0 + 28f2: 0900 addi s0,sp,144 + 28f4: 0000 unimp + 28f6: 0501 addi a0,a0,0 + 28f8: 0301 addi t1,t1,0 + 28fa: 0905 addi s2,s2,1 + 28fc: 0000 unimp + 28fe: 0901 addi s2,s2,0 + 2900: 0000 unimp + 2902: 0100 addi s0,sp,128 + 2904: 0501 addi a0,a0,0 + 2906: 001f 0205 0000 .byte 0x1f, 0x00, 0x05, 0x02, 0x00, 0x00 + 290c: 0000 unimp + 290e: 0101ed03 .4byte 0x101ed03 + 2912: 0305 addi t1,t1,1 + 2914: 00090303 lb t1,0(s2) + 2918: 0100 addi s0,sp,128 + 291a: 0505 addi a0,a0,1 + 291c: 00090103 lb sp,0(s2) + 2920: 0100 addi s0,sp,128 + 2922: 0705 addi a4,a4,1 + 2924: 0306 slli t1,t1,0x1 + 2926: 0900 addi s0,sp,144 + 2928: 0000 unimp + 292a: 0501 addi a0,a0,0 + 292c: 0605 addi a2,a2,1 + 292e: 00090103 lb sp,0(s2) + 2932: 0100 addi s0,sp,128 + 2934: 0805 addi a6,a6,1 + 2936: 0306 slli t1,t1,0x1 + 2938: 0900 addi s0,sp,144 + 293a: 0000 unimp + 293c: 0501 addi a0,a0,0 + 293e: 01030607 .4byte 0x1030607 + 2942: 0009 c.nop 2 + 2944: 0100 addi s0,sp,128 + 2946: 0105 addi sp,sp,1 + 2948: 0306 slli t1,t1,0x1 + 294a: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 294e: 0901 addi s2,s2,0 + 2950: 0000 unimp + 2952: 0100 addi s0,sp,128 + 2954: 0501 addi a0,a0,0 + 2956: 02050013 addi zero,a0,32 + 295a: 0000 unimp + 295c: 0000 unimp + 295e: 0100cf03 lbu t5,16(ra) + 2962: 0305 addi t1,t1,1 + 2964: 00090203 lb tp,0(s2) + 2968: 0100 addi s0,sp,128 + 296a: 1305 addi t1,t1,-31 + 296c: 0306 slli t1,t1,0x1 + 296e: 097e slli s2,s2,0x1f + 2970: 0000 unimp + 2972: 0501 addi a0,a0,0 + 2974: 0902030f .4byte 0x902030f + 2978: 0000 unimp + 297a: 0501 addi a0,a0,0 + 297c: 0301 addi t1,t1,0 + 297e: 0901 addi s2,s2,0 + 2980: 0000 unimp + 2982: 0901 addi s2,s2,0 + 2984: 0000 unimp + 2986: 0100 addi s0,sp,128 + 2988: 0501 addi a0,a0,0 + 298a: 0029 c.nop 10 + 298c: 0205 addi tp,tp,1 # 1 + 298e: 0000 unimp + 2990: 0000 unimp + 2992: 01028603 lb a2,16(t0) + 2996: 0305 addi t1,t1,1 + 2998: 00090203 lb tp,0(s2) + 299c: 0100 addi s0,sp,128 + 299e: 0c05 addi s8,s8,1 + 29a0: 0306 slli t1,t1,0x1 + 29a2: 0900 addi s0,sp,144 + 29a4: 0000 unimp + 29a6: 0501 addi a0,a0,0 + 29a8: 03030603 lb a2,48(t1) + 29ac: 0009 c.nop 2 + 29ae: 0100 addi s0,sp,128 + 29b0: 0b05 addi s6,s6,1 + 29b2: 0306 slli t1,t1,0x1 + 29b4: 0900 addi s0,sp,144 + 29b6: 0000 unimp + 29b8: 0501 addi a0,a0,0 + 29ba: 03030603 lb a2,48(t1) + 29be: 0009 c.nop 2 + 29c0: 0100 addi s0,sp,128 + 29c2: 0605 addi a2,a2,1 + 29c4: 0306 slli t1,t1,0x1 + 29c6: 0900 addi s0,sp,144 + 29c8: 0000 unimp + 29ca: 0501 addi a0,a0,0 + 29cc: 05030603 lb a2,80(t1) + 29d0: 0009 c.nop 2 + 29d2: 0100 addi s0,sp,128 + 29d4: 0f05 addi t5,t5,1 + 29d6: 0306 slli t1,t1,0x1 + 29d8: 0900 addi s0,sp,144 + 29da: 0000 unimp + 29dc: 0501 addi a0,a0,0 + 29de: 030c addi a1,sp,384 + 29e0: 0901 addi s2,s2,0 + 29e2: 0000 unimp + 29e4: 0501 addi a0,a0,0 + 29e6: 0306 slli t1,t1,0x1 + 29e8: 097f .2byte 0x97f + 29ea: 0000 unimp + 29ec: 0501 addi a0,a0,0 + 29ee: 05030603 lb a2,80(t1) + 29f2: 0009 c.nop 2 + 29f4: 0100 addi s0,sp,128 + 29f6: 0f05 addi t5,t5,1 + 29f8: 0306 slli t1,t1,0x1 + 29fa: 0900 addi s0,sp,144 + 29fc: 0000 unimp + 29fe: 0501 addi a0,a0,0 + 2a00: 030c addi a1,sp,384 + 2a02: 0901 addi s2,s2,0 + 2a04: 0000 unimp + 2a06: 0501 addi a0,a0,0 + 2a08: 0306 slli t1,t1,0x1 + 2a0a: 097f .2byte 0x97f + 2a0c: 0000 unimp + 2a0e: 0501 addi a0,a0,0 + 2a10: 05030603 lb a2,80(t1) + 2a14: 0009 c.nop 2 + 2a16: 0100 addi s0,sp,128 + 2a18: 0f05 addi t5,t5,1 + 2a1a: 0306 slli t1,t1,0x1 + 2a1c: 0900 addi s0,sp,144 + 2a1e: 0000 unimp + 2a20: 0501 addi a0,a0,0 + 2a22: 030c addi a1,sp,384 + 2a24: 0901 addi s2,s2,0 + 2a26: 0000 unimp + 2a28: 0501 addi a0,a0,0 + 2a2a: 0306 slli t1,t1,0x1 + 2a2c: 097f .2byte 0x97f + 2a2e: 0000 unimp + 2a30: 0501 addi a0,a0,0 + 2a32: 030a slli t1,t1,0x2 + 2a34: 0904 addi s1,sp,144 + 2a36: 0000 unimp + 2a38: 0501 addi a0,a0,0 + 2a3a: 096e030b .4byte 0x96e030b + 2a3e: 0000 unimp + 2a40: 0501 addi a0,a0,0 + 2a42: 0301 addi t1,t1,0 + 2a44: 00000913 li s2,0 + 2a48: 0901 addi s2,s2,0 + 2a4a: 0000 unimp + 2a4c: 0100 addi s0,sp,128 + 2a4e: 0501 addi a0,a0,0 + 2a50: 02050027 .4byte 0x2050027 + 2a54: 0000 unimp + 2a56: 0000 unimp + 2a58: 0102ad03 lw s10,16(t0) + 2a5c: 0305 addi t1,t1,1 + 2a5e: 00090203 lb tp,0(s2) + 2a62: 0100 addi s0,sp,128 + 2a64: 1405 addi s0,s0,-31 + 2a66: 0306 slli t1,t1,0x1 + 2a68: 0900 addi s0,sp,144 + 2a6a: 0000 unimp + 2a6c: 0501 addi a0,a0,0 + 2a6e: 0306 slli t1,t1,0x1 + 2a70: 0900 addi s0,sp,144 + 2a72: 0000 unimp + 2a74: 0501 addi a0,a0,0 + 2a76: 0301 addi t1,t1,0 + 2a78: 0906 slli s2,s2,0x1 + 2a7a: 0000 unimp + 2a7c: 0901 addi s2,s2,0 + 2a7e: 0000 unimp + 2a80: 0100 addi s0,sp,128 + 2a82: 0501 addi a0,a0,0 + 2a84: 002c addi a1,sp,8 + 2a86: 0205 addi tp,tp,1 # 1 + 2a88: 0000 unimp + 2a8a: 0000 unimp + 2a8c: 0102c003 lbu zero,16(t0) + 2a90: 0305 addi t1,t1,1 + 2a92: 00090203 lb tp,0(s2) + 2a96: 0100 addi s0,sp,128 + 2a98: 1d05 addi s10,s10,-31 + 2a9a: 0306 slli t1,t1,0x1 + 2a9c: 0900 addi s0,sp,144 + 2a9e: 0000 unimp + 2aa0: 0501 addi a0,a0,0 + 2aa2: 0301 addi t1,t1,0 + 2aa4: 0901 addi s2,s2,0 + 2aa6: 0000 unimp + 2aa8: 0901 addi s2,s2,0 + 2aaa: 0000 unimp + 2aac: 0100 addi s0,sp,128 + 2aae: 0501 addi a0,a0,0 + 2ab0: 0028 addi a0,sp,8 + 2ab2: 0205 addi tp,tp,1 # 1 + 2ab4: 0b6c addi a1,sp,412 + 2ab6: 0000 unimp + 2ab8: 0102cd03 lbu s10,16(t0) + 2abc: 0305 addi t1,t1,1 + 2abe: 00090203 lb tp,0(s2) + 2ac2: 0100 addi s0,sp,128 + 2ac4: 00090103 lb sp,0(s2) + 2ac8: 0100 addi s0,sp,128 + 2aca: 2805 jal 2afa <__neorv32_ram_size+0xafa> + 2acc: 0306 slli t1,t1,0x1 + 2ace: 097d addi s2,s2,31 + 2ad0: 0000 unimp + 2ad2: 0301 addi t1,t1,0 + 2ad4: 0900 addi s0,sp,144 + 2ad6: 0014 .2byte 0x14 + 2ad8: 0501 addi a0,a0,0 + 2ada: 0308 addi a0,sp,384 + 2adc: 0904 addi s1,sp,144 + 2ade: 0004 .2byte 0x4 + 2ae0: 0501 addi a0,a0,0 + 2ae2: 060a slli a2,a2,0x2 + 2ae4: 04097f03 .4byte 0x4097f03 + 2ae8: 0100 addi s0,sp,128 + 2aea: 0d05 addi s10,s10,1 + 2aec: 0306 slli t1,t1,0x1 + 2aee: 0900 addi s0,sp,144 + 2af0: 0000 unimp + 2af2: 0501 addi a0,a0,0 + 2af4: 0311 addi t1,t1,4 + 2af6: 0900 addi s0,sp,144 + 2af8: 0004 .2byte 0x4 + 2afa: 0501 addi a0,a0,0 + 2afc: 030a slli t1,t1,0x2 + 2afe: 0900 addi s0,sp,144 + 2b00: 0004 .2byte 0x4 + 2b02: 0501 addi a0,a0,0 + 2b04: 0301 addi t1,t1,0 + 2b06: 0906 slli s2,s2,0x1 + 2b08: 0004 .2byte 0x4 + 2b0a: 0501 addi a0,a0,0 + 2b0c: 0605 addi a2,a2,1 + 2b0e: 18097b03 .4byte 0x18097b03 + 2b12: 0100 addi s0,sp,128 + 2b14: 0805 addi a6,a6,1 + 2b16: 0306 slli t1,t1,0x1 + 2b18: 0900 addi s0,sp,144 + 2b1a: 0000 unimp + 2b1c: 0501 addi a0,a0,0 + 2b1e: 01030607 .4byte 0x1030607 + 2b22: 0409 addi s0,s0,2 + 2b24: 0100 addi s0,sp,128 + 2b26: 0505 addi a0,a0,1 + 2b28: 08090203 lb tp,128(s2) + 2b2c: 0100 addi s0,sp,128 + 2b2e: 0c09 addi s8,s8,2 + 2b30: 0000 unimp + 2b32: 0101 addi sp,sp,0 + 2b34: 3405 jal 2554 <__neorv32_ram_size+0x554> + 2b36: 0500 addi s0,sp,640 + 2b38: c402 sw zero,8(sp) + 2b3a: 0300000b .4byte 0x300000b + 2b3e: 02ea slli t0,t0,0x1a + 2b40: 0501 addi a0,a0,0 + 2b42: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 2b46: 0000 unimp + 2b48: 0301 addi t1,t1,0 + 2b4a: 0901 addi s2,s2,0 + 2b4c: 0000 unimp + 2b4e: 0301 addi t1,t1,0 + 2b50: 0902 c.slli64 s2 + 2b52: 0000 unimp + 2b54: 0301 addi t1,t1,0 + 2b56: 0901 addi s2,s2,0 + 2b58: 0000 unimp + 2b5a: 0501 addi a0,a0,0 + 2b5c: 0634 addi a3,sp,776 + 2b5e: 00097a03 .4byte 0x97a03 + 2b62: 0100 addi s0,sp,128 + 2b64: 0305 addi t1,t1,1 + 2b66: 08090603 lb a2,128(s2) + 2b6a: 0100 addi s0,sp,128 + 2b6c: 3405 jal 258c <__neorv32_ram_size+0x58c> + 2b6e: 04097a03 .4byte 0x4097a03 + 2b72: 0100 addi s0,sp,128 + 2b74: 2c090003 lb zero,704(s2) + 2b78: 0100 addi s0,sp,128 + 2b7a: 0305 addi t1,t1,1 + 2b7c: 1c090603 lb a2,448(s2) + 2b80: 0100 addi s0,sp,128 + 2b82: 0306 slli t1,t1,0x1 + 2b84: 0902 c.slli64 s2 + 2b86: 0004 .2byte 0x4 + 2b88: 0501 addi a0,a0,0 + 2b8a: 0608 addi a0,sp,768 + 2b8c: 00090103 lb sp,0(s2) + 2b90: 0100 addi s0,sp,128 + 2b92: 0a05 addi s4,s4,1 + 2b94: 04092703 lw a4,64(s2) + 2b98: 0100 addi s0,sp,128 + 2b9a: 0705 addi a4,a4,1 + 2b9c: 04095b03 lhu s6,64(s2) + 2ba0: 0100 addi s0,sp,128 + 2ba2: 0a05 addi s4,s4,1 + 2ba4: 0306 slli t1,t1,0x1 + 2ba6: 097d addi s2,s2,31 + 2ba8: 0018 .2byte 0x18 + 2baa: 0501 addi a0,a0,0 + 2bac: 060d addi a2,a2,3 + 2bae: 00090003 lb zero,0(s2) + 2bb2: 0100 addi s0,sp,128 + 2bb4: 0a05 addi s4,s4,1 + 2bb6: 04090003 lb zero,64(s2) + 2bba: 0100 addi s0,sp,128 + 2bbc: 0105 addi sp,sp,1 + 2bbe: 04092f03 lw t5,64(s2) + 2bc2: 0100 addi s0,sp,128 + 2bc4: 0505 addi a0,a0,1 + 2bc6: 0306 slli t1,t1,0x1 + 2bc8: 0952 slli s2,s2,0x14 + 2bca: 0034 addi a3,sp,8 + 2bcc: 0501 addi a0,a0,0 + 2bce: 0608 addi a0,sp,768 + 2bd0: 00090003 lb zero,0(s2) + 2bd4: 0100 addi s0,sp,128 + 2bd6: 0705 addi a4,a4,1 + 2bd8: 0306 slli t1,t1,0x1 + 2bda: 0901 addi s2,s2,0 + 2bdc: 0004 .2byte 0x4 + 2bde: 0501 addi a0,a0,0 + 2be0: 0609 addi a2,a2,2 + 2be2: 00090003 lb zero,0(s2) + 2be6: 0100 addi s0,sp,128 + 2be8: 0705 addi a4,a4,1 + 2bea: 0306 slli t1,t1,0x1 + 2bec: 0901 addi s2,s2,0 + 2bee: 0004 .2byte 0x4 + 2bf0: 0501 addi a0,a0,0 + 2bf2: 091f030b .4byte 0x91f030b + 2bf6: 0018 .2byte 0x18 + 2bf8: 0301 addi t1,t1,0 + 2bfa: 0901 addi s2,s2,0 + 2bfc: 0008 .2byte 0x8 + 2bfe: 0501 addi a0,a0,0 + 2c00: 60030607 .4byte 0x60030607 + 2c04: 0809 addi a6,a6,2 + 2c06: 0100 addi s0,sp,128 + 2c08: 0b05 addi s6,s6,1 + 2c0a: 0306 slli t1,t1,0x1 + 2c0c: 0909 addi s2,s2,2 + 2c0e: 000c .2byte 0xc + 2c10: 0501 addi a0,a0,0 + 2c12: 060d addi a2,a2,3 + 2c14: 00090003 lb zero,0(s2) + 2c18: 0100 addi s0,sp,128 + 2c1a: 0b05 addi s6,s6,1 + 2c1c: 0306 slli t1,t1,0x1 + 2c1e: 0901 addi s2,s2,0 + 2c20: 0008 .2byte 0x8 + 2c22: 0501 addi a0,a0,0 + 2c24: 060d addi a2,a2,3 + 2c26: 00097f03 .4byte 0x97f03 + 2c2a: 0100 addi s0,sp,128 + 2c2c: 0e05 addi t3,t3,1 + 2c2e: 08090103 lb sp,128(s2) + 2c32: 0100 addi s0,sp,128 + 2c34: 0d05 addi s10,s10,1 + 2c36: 0306 slli t1,t1,0x1 + 2c38: 0901 addi s2,s2,0 + 2c3a: 0004 .2byte 0x4 + 2c3c: 0601 addi a2,a2,0 + 2c3e: 00090103 lb sp,0(s2) + 2c42: 0100 addi s0,sp,128 + 2c44: 0f05 addi t5,t5,1 + 2c46: 04097f03 .4byte 0x4097f03 + 2c4a: 0100 addi s0,sp,128 + 2c4c: 0d05 addi s10,s10,1 + 2c4e: 0306 slli t1,t1,0x1 + 2c50: 0901 addi s2,s2,0 + 2c52: 0004 .2byte 0x4 + 2c54: 0501 addi a0,a0,0 + 2c56: 0902030b .4byte 0x902030b + 2c5a: 0004 .2byte 0x4 + 2c5c: 0601 addi a2,a2,0 + 2c5e: 08090403 lb s0,128(s2) + 2c62: 0100 addi s0,sp,128 + 2c64: 0306 slli t1,t1,0x1 + 2c66: 0901 addi s2,s2,0 + 2c68: 0004 .2byte 0x4 + 2c6a: 0501 addi a0,a0,0 + 2c6c: 6d030607 .4byte 0x6d030607 + 2c70: 0809 addi a6,a6,2 + 2c72: 0100 addi s0,sp,128 + 2c74: 0b05 addi s6,s6,1 + 2c76: 0306 slli t1,t1,0x1 + 2c78: 0902 c.slli64 s2 + 2c7a: 000c .2byte 0xc + 2c7c: 0501 addi a0,a0,0 + 2c7e: 061e slli a2,a2,0x7 + 2c80: 00090003 lb zero,0(s2) + 2c84: 0100 addi s0,sp,128 + 2c86: 0b05 addi s6,s6,1 + 2c88: 04090003 lb zero,64(s2) + 2c8c: 0100 addi s0,sp,128 + 2c8e: 1e05 addi t3,t3,-31 + 2c90: 04090003 lb zero,64(s2) + 2c94: 0100 addi s0,sp,128 + 2c96: 0b05 addi s6,s6,1 + 2c98: 08091103 lh sp,128(s2) + 2c9c: 0100 addi s0,sp,128 + 2c9e: 0306 slli t1,t1,0x1 + 2ca0: 0901 addi s2,s2,0 + 2ca2: 0004 .2byte 0x4 + 2ca4: 0501 addi a0,a0,0 + 2ca6: 0612 slli a2,a2,0x4 + 2ca8: 00096b03 .4byte 0x96b03 + 2cac: 0100 addi s0,sp,128 + 2cae: 0b05 addi s6,s6,1 + 2cb0: 0306 slli t1,t1,0x1 + 2cb2: 0906 slli s2,s2,0x1 + 2cb4: 0008 .2byte 0x8 + 2cb6: 0501 addi a0,a0,0 + 2cb8: 0624 addi s1,sp,776 + 2cba: 00090003 lb zero,0(s2) + 2cbe: 0100 addi s0,sp,128 + 2cc0: 0b05 addi s6,s6,1 + 2cc2: 04090003 lb zero,64(s2) + 2cc6: 0100 addi s0,sp,128 + 2cc8: 2405 jal 2ee8 <__neorv32_ram_size+0xee8> + 2cca: 04090003 lb zero,64(s2) + 2cce: 0100 addi s0,sp,128 + 2cd0: 0b05 addi s6,s6,1 + 2cd2: 08091b03 lh s6,128(s2) + 2cd6: 0100 addi s0,sp,128 + 2cd8: 0306 slli t1,t1,0x1 + 2cda: 0901 addi s2,s2,0 + 2cdc: 0004 .2byte 0x4 + 2cde: 0301 addi t1,t1,0 + 2ce0: 0971 addi s2,s2,28 + 2ce2: 0004 .2byte 0x4 + 2ce4: 0301 addi t1,t1,0 + 2ce6: 0906 slli s2,s2,0x1 + 2ce8: 0018 .2byte 0x18 + 2cea: 0301 addi t1,t1,0 + 2cec: 0901 addi s2,s2,0 + 2cee: 0018 .2byte 0x18 + 2cf0: 0501 addi a0,a0,0 + 2cf2: 030d addi t1,t1,3 + 2cf4: 0901 addi s2,s2,0 + 2cf6: 0000 unimp + 2cf8: 0501 addi a0,a0,0 + 2cfa: 097e030b .4byte 0x97e030b + 2cfe: 000c .2byte 0xc + 2d00: 0301 addi t1,t1,0 + 2d02: 0901 addi s2,s2,0 + 2d04: 0018 .2byte 0x18 + 2d06: 0301 addi t1,t1,0 + 2d08: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 2d0c: 0501 addi a0,a0,0 + 2d0e: 09090307 .4byte 0x9090307 + 2d12: 0004 .2byte 0x4 + 2d14: 0501 addi a0,a0,0 + 2d16: 060a slli a2,a2,0x2 + 2d18: 00090003 lb zero,0(s2) + 2d1c: 0100 addi s0,sp,128 + 2d1e: 0905 addi s2,s2,1 + 2d20: 0306 slli t1,t1,0x1 + 2d22: 0901 addi s2,s2,0 + 2d24: 0004 .2byte 0x4 + 2d26: 0501 addi a0,a0,0 + 2d28: 02030607 .4byte 0x2030607 + 2d2c: 0809 addi a6,a6,2 + 2d2e: 0100 addi s0,sp,128 + 2d30: 1605 addi a2,a2,-31 + 2d32: 04095503 lhu a0,64(s2) + 2d36: 0100 addi s0,sp,128 + 2d38: 0705 addi a4,a4,1 + 2d3a: 0306 slli t1,t1,0x1 + 2d3c: 0004092b .4byte 0x4092b + 2d40: 0901 addi s2,s2,0 + 2d42: 0008 .2byte 0x8 + 2d44: 0100 addi s0,sp,128 + 2d46: 0501 addi a0,a0,0 + 2d48: 003e c.slli zero,0xf + 2d4a: 0205 addi tp,tp,1 # 1 + 2d4c: 0000 unimp + 2d4e: 0000 unimp + 2d50: 0103ae03 lw t3,16(t2) + 2d54: 0305 addi t1,t1,1 + 2d56: 00090203 lb tp,0(s2) + 2d5a: 0100 addi s0,sp,128 + 2d5c: 00090103 lb sp,0(s2) + 2d60: 0100 addi s0,sp,128 + 2d62: 3e05 jal 2892 <__neorv32_ram_size+0x892> + 2d64: 0306 slli t1,t1,0x1 + 2d66: 097d addi s2,s2,31 + 2d68: 0000 unimp + 2d6a: 0301 addi t1,t1,0 + 2d6c: 0900 addi s0,sp,144 + 2d6e: 0000 unimp + 2d70: 0501 addi a0,a0,0 + 2d72: 09030307 .4byte 0x9030307 + 2d76: 0000 unimp + 2d78: 0501 addi a0,a0,0 + 2d7a: 0308 addi a0,sp,384 + 2d7c: 0904 addi s1,sp,144 + 2d7e: 0000 unimp + 2d80: 0501 addi a0,a0,0 + 2d82: 030d addi t1,t1,3 + 2d84: 0909 addi s2,s2,2 + 2d86: 0000 unimp + 2d88: 0301 addi t1,t1,0 + 2d8a: 0902 c.slli64 s2 + 2d8c: 0000 unimp + 2d8e: 0501 addi a0,a0,0 + 2d90: 033d addi t1,t1,15 + 2d92: 0900 addi s0,sp,144 + 2d94: 0000 unimp + 2d96: 0501 addi a0,a0,0 + 2d98: 73030603 lb a2,1840(t1) + 2d9c: 0009 c.nop 2 + 2d9e: 0100 addi s0,sp,128 + 2da0: 0505 addi a0,a0,1 + 2da2: 00090103 lb sp,0(s2) + 2da6: 0100 addi s0,sp,128 + 2da8: 0905 addi s2,s2,1 + 2daa: 0306 slli t1,t1,0x1 + 2dac: 0900 addi s0,sp,144 + 2dae: 0000 unimp + 2db0: 0501 addi a0,a0,0 + 2db2: 0605 addi a2,a2,1 + 2db4: 00090103 lb sp,0(s2) + 2db8: 0100 addi s0,sp,128 + 2dba: 0805 addi a6,a6,1 + 2dbc: 0306 slli t1,t1,0x1 + 2dbe: 0900 addi s0,sp,144 + 2dc0: 0000 unimp + 2dc2: 0501 addi a0,a0,0 + 2dc4: 01030607 .4byte 0x1030607 + 2dc8: 0009 c.nop 2 + 2dca: 0100 addi s0,sp,128 + 2dcc: 0a05 addi s4,s4,1 + 2dce: 0306 slli t1,t1,0x1 + 2dd0: 0900 addi s0,sp,144 + 2dd2: 0000 unimp + 2dd4: 0501 addi a0,a0,0 + 2dd6: 0609 addi a2,a2,2 + 2dd8: 00090103 lb sp,0(s2) + 2ddc: 0100 addi s0,sp,128 + 2dde: 0c05 addi s8,s8,1 + 2de0: 0306 slli t1,t1,0x1 + 2de2: 0900 addi s0,sp,144 + 2de4: 0000 unimp + 2de6: 0501 addi a0,a0,0 + 2de8: 0103060b .4byte 0x103060b + 2dec: 0009 c.nop 2 + 2dee: 0100 addi s0,sp,128 + 2df0: 0905 addi s2,s2,1 + 2df2: 00090203 lb tp,0(s2) + 2df6: 0100 addi s0,sp,128 + 2df8: 0f05 addi t5,t5,1 + 2dfa: 0306 slli t1,t1,0x1 + 2dfc: 0900 addi s0,sp,144 + 2dfe: 0000 unimp + 2e00: 0501 addi a0,a0,0 + 2e02: 0609 addi a2,a2,2 + 2e04: 00090103 lb sp,0(s2) + 2e08: 0100 addi s0,sp,128 + 2e0a: 0f05 addi t5,t5,1 + 2e0c: 0306 slli t1,t1,0x1 + 2e0e: 0900 addi s0,sp,144 + 2e10: 0000 unimp + 2e12: 0501 addi a0,a0,0 + 2e14: 060a slli a2,a2,0x2 + 2e16: 00090303 lb t1,0(s2) + 2e1a: 0100 addi s0,sp,128 + 2e1c: 0d05 addi s10,s10,1 + 2e1e: 0306 slli t1,t1,0x1 + 2e20: 0900 addi s0,sp,144 + 2e22: 0000 unimp + 2e24: 0501 addi a0,a0,0 + 2e26: 060a slli a2,a2,0x2 + 2e28: 00090203 lb tp,0(s2) + 2e2c: 0100 addi s0,sp,128 + 2e2e: 1905 addi s2,s2,-31 + 2e30: 0306 slli t1,t1,0x1 + 2e32: 0900 addi s0,sp,144 + 2e34: 0000 unimp + 2e36: 0501 addi a0,a0,0 + 2e38: 030d addi t1,t1,3 + 2e3a: 0900 addi s0,sp,144 + 2e3c: 0000 unimp + 2e3e: 0501 addi a0,a0,0 + 2e40: 04020027 .4byte 0x4020027 + 2e44: 0301 addi t1,t1,0 + 2e46: 0900 addi s0,sp,144 + 2e48: 0000 unimp + 2e4a: 0501 addi a0,a0,0 + 2e4c: 01030607 .4byte 0x1030607 + 2e50: 0009 c.nop 2 + 2e52: 0100 addi s0,sp,128 + 2e54: 0a05 addi s4,s4,1 + 2e56: 0306 slli t1,t1,0x1 + 2e58: 0900 addi s0,sp,144 + 2e5a: 0000 unimp + 2e5c: 0501 addi a0,a0,0 + 2e5e: 0609 addi a2,a2,2 + 2e60: 00090103 lb sp,0(s2) + 2e64: 0100 addi s0,sp,128 + 2e66: 0705 addi a4,a4,1 + 2e68: 00090203 lb tp,0(s2) + 2e6c: 0100 addi s0,sp,128 + 2e6e: 1105 addi sp,sp,-31 + 2e70: 0306 slli t1,t1,0x1 + 2e72: 0900 addi s0,sp,144 + 2e74: 0000 unimp + 2e76: 0501 addi a0,a0,0 + 2e78: 030e slli t1,t1,0x3 + 2e7a: 0900 addi s0,sp,144 + 2e7c: 0000 unimp + 2e7e: 0501 addi a0,a0,0 + 2e80: 01030607 .4byte 0x1030607 + 2e84: 0009 c.nop 2 + 2e86: 0100 addi s0,sp,128 + 2e88: 0905 addi s2,s2,1 + 2e8a: 0306 slli t1,t1,0x1 + 2e8c: 0000096f jal s2,2e8c <__neorv32_ram_size+0xe8c> + 2e90: 0501 addi a0,a0,0 + 2e92: 030d addi t1,t1,3 + 2e94: 0911 addi s2,s2,4 + 2e96: 0000 unimp + 2e98: 0501 addi a0,a0,0 + 2e9a: 6e030603 lb a2,1760(t1) + 2e9e: 0009 c.nop 2 + 2ea0: 0100 addi s0,sp,128 + 2ea2: 0505 addi a0,a0,1 + 2ea4: 00090103 lb sp,0(s2) + 2ea8: 0100 addi s0,sp,128 + 2eaa: 00090103 lb sp,0(s2) + 2eae: 0100 addi s0,sp,128 + 2eb0: 0e05 addi t3,t3,1 + 2eb2: 0306 slli t1,t1,0x1 + 2eb4: 0000090f .4byte 0x90f + 2eb8: 0501 addi a0,a0,0 + 2eba: 0308 addi a0,sp,384 + 2ebc: 0971 addi s2,s2,28 + 2ebe: 0000 unimp + 2ec0: 0501 addi a0,a0,0 + 2ec2: 13030603 lb a2,304(t1) + 2ec6: 0009 c.nop 2 + 2ec8: 0100 addi s0,sp,128 + 2eca: 0b05 addi s6,s6,1 + 2ecc: 0306 slli t1,t1,0x1 + 2ece: 0900 addi s0,sp,144 + 2ed0: 0000 unimp + 2ed2: 0501 addi a0,a0,0 + 2ed4: 02030603 lb a2,32(t1) + 2ed8: 0009 c.nop 2 + 2eda: 0100 addi s0,sp,128 + 2edc: 0105 addi sp,sp,1 + 2ede: 0306 slli t1,t1,0x1 + 2ee0: 0901 addi s2,s2,0 + 2ee2: 0000 unimp + 2ee4: 0901 addi s2,s2,0 + 2ee6: 0000 unimp + 2ee8: 0100 addi s0,sp,128 + 2eea: 0501 addi a0,a0,0 + 2eec: 02050023 sb zero,32(a0) + 2ef0: 0000 unimp + 2ef2: 0000 unimp + 2ef4: 0103d803 lhu a6,16(t2) + 2ef8: 0305 addi t1,t1,1 + 2efa: 00090203 lb tp,0(s2) + 2efe: 0100 addi s0,sp,128 + 2f00: 1605 addi a2,a2,-31 + 2f02: 0306 slli t1,t1,0x1 + 2f04: 0900 addi s0,sp,144 + 2f06: 0000 unimp + 2f08: 0501 addi a0,a0,0 + 2f0a: 0306 slli t1,t1,0x1 + 2f0c: 0900 addi s0,sp,144 + 2f0e: 0000 unimp + 2f10: 0501 addi a0,a0,0 + 2f12: 0301 addi t1,t1,0 + 2f14: 0906 slli s2,s2,0x1 + 2f16: 0000 unimp + 2f18: 0901 addi s2,s2,0 + 2f1a: 0000 unimp + 2f1c: 0100 addi s0,sp,128 + 2f1e: 0501 addi a0,a0,0 + 2f20: 0205004f .4byte 0x205004f + 2f24: 0000 unimp + 2f26: 0000 unimp + 2f28: 0103ef03 .4byte 0x103ef03 + 2f2c: 0305 addi t1,t1,1 + 2f2e: 00090203 lb tp,0(s2) + 2f32: 0100 addi s0,sp,128 + 2f34: 4f05 li t5,1 + 2f36: 0306 slli t1,t1,0x1 + 2f38: 097e slli s2,s2,0x1f + 2f3a: 0000 unimp + 2f3c: 0501 addi a0,a0,0 + 2f3e: 0316 slli t1,t1,0x5 + 2f40: 0902 c.slli64 s2 + 2f42: 0000 unimp + 2f44: 0501 addi a0,a0,0 + 2f46: 02030603 lb a2,32(t1) + 2f4a: 0009 c.nop 2 + 2f4c: 0100 addi s0,sp,128 + 2f4e: 0c05 addi s8,s8,1 + 2f50: 0306 slli t1,t1,0x1 + 2f52: 0900 addi s0,sp,144 + 2f54: 0000 unimp + 2f56: 0501 addi a0,a0,0 + 2f58: 01030603 lb a2,16(t1) + 2f5c: 0009 c.nop 2 + 2f5e: 0100 addi s0,sp,128 + 2f60: 00090103 lb sp,0(s2) + 2f64: 0100 addi s0,sp,128 + 2f66: 00090503 lb a0,0(s2) + 2f6a: 0100 addi s0,sp,128 + 2f6c: 4f05 li t5,1 + 2f6e: 0306 slli t1,t1,0x1 + 2f70: 0975 addi s2,s2,29 + 2f72: 0000 unimp + 2f74: 0501 addi a0,a0,0 + 2f76: 0318 addi a4,sp,384 + 2f78: 0000090b .4byte 0x90b + 2f7c: 0501 addi a0,a0,0 + 2f7e: 0975034f .4byte 0x975034f + 2f82: 0000 unimp + 2f84: 0501 addi a0,a0,0 + 2f86: 0318 addi a4,sp,384 + 2f88: 0000090b .4byte 0x90b + 2f8c: 0501 addi a0,a0,0 + 2f8e: 0305 addi t1,t1,1 + 2f90: 0900 addi s0,sp,144 + 2f92: 0000 unimp + 2f94: 0501 addi a0,a0,0 + 2f96: 030c addi a1,sp,384 + 2f98: 090a slli s2,s2,0x2 + 2f9a: 0000 unimp + 2f9c: 0501 addi a0,a0,0 + 2f9e: 0305 addi t1,t1,1 + 2fa0: 0976 slli s2,s2,0x1d + 2fa2: 0000 unimp + 2fa4: 0501 addi a0,a0,0 + 2fa6: 0a030603 lb a2,160(t1) + 2faa: 0009 c.nop 2 + 2fac: 0100 addi s0,sp,128 + 2fae: 0b05 addi s6,s6,1 + 2fb0: 0306 slli t1,t1,0x1 + 2fb2: 0971 addi s2,s2,28 + 2fb4: 0000 unimp + 2fb6: 0501 addi a0,a0,0 + 2fb8: 030c addi a1,sp,384 + 2fba: 0000090f .4byte 0x90f + 2fbe: 0601 addi a2,a2,0 + 2fc0: 00090003 lb zero,0(s2) + 2fc4: 0100 addi s0,sp,128 + 2fc6: 0305 addi t1,t1,1 + 2fc8: 00090803 lb a6,0(s2) + 2fcc: 0100 addi s0,sp,128 + 2fce: 00090103 lb sp,0(s2) + 2fd2: 0100 addi s0,sp,128 + 2fd4: 00090203 lb tp,0(s2) + 2fd8: 0100 addi s0,sp,128 + 2fda: 00090103 lb sp,0(s2) + 2fde: 0100 addi s0,sp,128 + 2fe0: 00090103 lb sp,0(s2) + 2fe4: 0100 addi s0,sp,128 + 2fe6: 00090203 lb tp,0(s2) + 2fea: 0100 addi s0,sp,128 + 2fec: 00090103 lb sp,0(s2) + 2ff0: 0100 addi s0,sp,128 + 2ff2: 00090203 lb tp,0(s2) + 2ff6: 0100 addi s0,sp,128 + 2ff8: 0c05 addi s8,s8,1 + 2ffa: 0306 slli t1,t1,0x1 + 2ffc: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 3000: 0501 addi a0,a0,0 + 3002: 0310 addi a2,sp,384 + 3004: 0901 addi s2,s2,0 + 3006: 0000 unimp + 3008: 0501 addi a0,a0,0 + 300a: 030c addi a1,sp,384 + 300c: 097c addi a5,sp,156 + 300e: 0000 unimp + 3010: 0501 addi a0,a0,0 + 3012: 01030603 lb a2,16(t1) + 3016: 0009 c.nop 2 + 3018: 0100 addi s0,sp,128 + 301a: 00090203 lb tp,0(s2) + 301e: 0100 addi s0,sp,128 + 3020: 00090103 lb sp,0(s2) + 3024: 0100 addi s0,sp,128 + 3026: 00090803 lb a6,0(s2) + 302a: 0100 addi s0,sp,128 + 302c: 00090303 lb t1,0(s2) + 3030: 0100 addi s0,sp,128 + 3032: 0d05 addi s10,s10,1 + 3034: 0306 slli t1,t1,0x1 + 3036: 0000096b .4byte 0x96b + 303a: 0501 addi a0,a0,0 + 303c: 0352 slli t1,t1,0x14 + 303e: 0915 addi s2,s2,5 + 3040: 0000 unimp + 3042: 0501 addi a0,a0,0 + 3044: 0311 addi t1,t1,4 + 3046: 0972 slli s2,s2,0x1c + 3048: 0000 unimp + 304a: 0501 addi a0,a0,0 + 304c: 0352 slli t1,t1,0x14 + 304e: 090e slli s2,s2,0x3 + 3050: 0000 unimp + 3052: 0501 addi a0,a0,0 + 3054: 030c addi a1,sp,384 + 3056: 0968 addi a0,sp,156 + 3058: 0000 unimp + 305a: 0501 addi a0,a0,0 + 305c: 0301 addi t1,t1,0 + 305e: 0919 addi s2,s2,6 + 3060: 0000 unimp + 3062: 0501 addi a0,a0,0 + 3064: 0352 slli t1,t1,0x14 + 3066: 097f .2byte 0x97f + 3068: 0000 unimp + 306a: 0501 addi a0,a0,0 + 306c: 0316 slli t1,t1,0x5 + 306e: 0900 addi s0,sp,144 + 3070: 0000 unimp + 3072: 0501 addi a0,a0,0 + 3074: 0301 addi t1,t1,0 + 3076: 0901 addi s2,s2,0 + 3078: 0000 unimp + 307a: 0501 addi a0,a0,0 + 307c: 0605 addi a2,a2,1 + 307e: 00095f03 lhu t5,0(s2) + 3082: 0100 addi s0,sp,128 + 3084: 0805 addi a6,a6,1 + 3086: 0306 slli t1,t1,0x1 + 3088: 0900 addi s0,sp,144 + 308a: 0000 unimp + 308c: 0501 addi a0,a0,0 + 308e: 01030607 .4byte 0x1030607 + 3092: 0009 c.nop 2 + 3094: 0100 addi s0,sp,128 + 3096: 0905 addi s2,s2,1 + 3098: 0306 slli t1,t1,0x1 + 309a: 0900 addi s0,sp,144 + 309c: 0000 unimp + 309e: 0501 addi a0,a0,0 + 30a0: 0605 addi a2,a2,1 + 30a2: 00090303 lb t1,0(s2) + 30a6: 0100 addi s0,sp,128 + 30a8: 0605 addi a2,a2,1 + 30aa: 0306 slli t1,t1,0x1 + 30ac: 0900 addi s0,sp,144 + 30ae: 0000 unimp + 30b0: 0501 addi a0,a0,0 + 30b2: 7f030607 .4byte 0x7f030607 + 30b6: 0009 c.nop 2 + 30b8: 0100 addi s0,sp,128 + 30ba: 0905 addi s2,s2,1 + 30bc: 0306 slli t1,t1,0x1 + 30be: 0900 addi s0,sp,144 + 30c0: 0000 unimp + 30c2: 0901 addi s2,s2,0 + 30c4: 0000 unimp + 30c6: 0100 addi s0,sp,128 + 30c8: 0501 addi a0,a0,0 + 30ca: 0022 c.slli zero,0x8 + 30cc: 0205 addi tp,tp,1 # 1 + 30ce: 0000 unimp + 30d0: 0000 unimp + 30d2: 0104ac03 lw s8,16(s1) + 30d6: 0305 addi t1,t1,1 + 30d8: 00090203 lb tp,0(s2) + 30dc: 0100 addi s0,sp,128 + 30de: 1005 c.nop -31 + 30e0: 0306 slli t1,t1,0x1 + 30e2: 0900 addi s0,sp,144 + 30e4: 0000 unimp + 30e6: 0501 addi a0,a0,0 + 30e8: 0316 slli t1,t1,0x5 + 30ea: 0900 addi s0,sp,144 + 30ec: 0000 unimp + 30ee: 0501 addi a0,a0,0 + 30f0: 0301 addi t1,t1,0 + 30f2: 0901 addi s2,s2,0 + 30f4: 0000 unimp + 30f6: 0901 addi s2,s2,0 + 30f8: 0000 unimp + 30fa: 0100 addi s0,sp,128 + 30fc: 0501 addi a0,a0,0 + 30fe: 0021 c.nop 8 + 3100: 0205 addi tp,tp,1 # 1 + 3102: 0000 unimp + 3104: 0000 unimp + 3106: 0104b503 .4byte 0x104b503 + 310a: 0305 addi t1,t1,1 + 310c: 00090203 lb tp,0(s2) + 3110: 0100 addi s0,sp,128 + 3112: 1005 c.nop -31 + 3114: 0306 slli t1,t1,0x1 + 3116: 0900 addi s0,sp,144 + 3118: 0000 unimp + 311a: 0501 addi a0,a0,0 + 311c: 0316 slli t1,t1,0x5 + 311e: 0900 addi s0,sp,144 + 3120: 0000 unimp + 3122: 0501 addi a0,a0,0 + 3124: 0301 addi t1,t1,0 + 3126: 0901 addi s2,s2,0 + 3128: 0000 unimp + 312a: 0901 addi s2,s2,0 + 312c: 0000 unimp + 312e: 0100 addi s0,sp,128 + 3130: 0501 addi a0,a0,0 + 3132: 0021 c.nop 8 + 3134: 0205 addi tp,tp,1 # 1 + 3136: 0000 unimp + 3138: 0000 unimp + 313a: 0104c203 lbu tp,16(s1) + 313e: 0305 addi t1,t1,1 + 3140: 00090303 lb t1,0(s2) + 3144: 0100 addi s0,sp,128 + 3146: 1e05 addi t3,t3,-31 + 3148: 0306 slli t1,t1,0x1 + 314a: 0900 addi s0,sp,144 + 314c: 0000 unimp + 314e: 0501 addi a0,a0,0 + 3150: 0038 addi a4,sp,8 + 3152: 0402 c.slli64 s0 + 3154: 0601 addi a2,a2,0 + 3156: 00090003 lb zero,0(s2) + 315a: 0100 addi s0,sp,128 + 315c: 1805 addi a6,a6,-31 + 315e: 0200 addi s0,sp,256 + 3160: 0104 addi s1,sp,128 + 3162: 0306 slli t1,t1,0x1 + 3164: 0900 addi s0,sp,144 + 3166: 0000 unimp + 3168: 0501 addi a0,a0,0 + 316a: 001e c.slli zero,0x7 + 316c: 0402 c.slli64 s0 + 316e: 0301 addi t1,t1,0 + 3170: 0900 addi s0,sp,144 + 3172: 0000 unimp + 3174: 0501 addi a0,a0,0 + 3176: 0038 addi a4,sp,8 + 3178: 0402 c.slli64 s0 + 317a: 0301 addi t1,t1,0 + 317c: 0900 addi s0,sp,144 + 317e: 0000 unimp + 3180: 0501 addi a0,a0,0 + 3182: 01030603 lb a2,16(t1) + 3186: 0009 c.nop 2 + 3188: 0100 addi s0,sp,128 + 318a: 1605 addi a2,a2,-31 + 318c: 0306 slli t1,t1,0x1 + 318e: 0900 addi s0,sp,144 + 3190: 0000 unimp + 3192: 0501 addi a0,a0,0 + 3194: 0301 addi t1,t1,0 + 3196: 0901 addi s2,s2,0 + 3198: 0000 unimp + 319a: 0901 addi s2,s2,0 + 319c: 0000 unimp + 319e: 0100 addi s0,sp,128 + 31a0: 0501 addi a0,a0,0 + 31a2: 0021 c.nop 8 + 31a4: 0205 addi tp,tp,1 # 1 + 31a6: 0000 unimp + 31a8: 0000 unimp + 31aa: 0104d103 lhu sp,16(s1) + 31ae: 0305 addi t1,t1,1 + 31b0: 00090203 lb tp,0(s2) + 31b4: 0100 addi s0,sp,128 + 31b6: 0c05 addi s8,s8,1 + 31b8: 0306 slli t1,t1,0x1 + 31ba: 0900 addi s0,sp,144 + 31bc: 0000 unimp + 31be: 0501 addi a0,a0,0 + 31c0: 02030603 lb a2,32(t1) + 31c4: 0009 c.nop 2 + 31c6: 0100 addi s0,sp,128 + 31c8: 0c05 addi s8,s8,1 + 31ca: 0306 slli t1,t1,0x1 + 31cc: 0902 c.slli64 s2 + 31ce: 0000 unimp + 31d0: 0501 addi a0,a0,0 + 31d2: 0306 slli t1,t1,0x1 + 31d4: 097e slli s2,s2,0x1f + 31d6: 0000 unimp + 31d8: 0501 addi a0,a0,0 + 31da: 002e c.slli zero,0xb + 31dc: 0402 c.slli64 s0 + 31de: 0301 addi t1,t1,0 + 31e0: 0900 addi s0,sp,144 + 31e2: 0000 unimp + 31e4: 0501 addi a0,a0,0 + 31e6: 0301 addi t1,t1,0 + 31e8: 0905 addi s2,s2,1 + 31ea: 0000 unimp + 31ec: 0901 addi s2,s2,0 + 31ee: 0000 unimp + 31f0: 0100 addi s0,sp,128 + 31f2: 0501 addi a0,a0,0 + 31f4: 001f 0205 0000 .byte 0x1f, 0x00, 0x05, 0x02, 0x00, 0x00 + 31fa: 0000 unimp + 31fc: 0104e403 .4byte 0x104e403 + 3200: 0305 addi t1,t1,1 + 3202: 00090303 lb t1,0(s2) + 3206: 0100 addi s0,sp,128 + 3208: 0505 addi a0,a0,1 + 320a: 00090103 lb sp,0(s2) + 320e: 0100 addi s0,sp,128 + 3210: 0705 addi a4,a4,1 + 3212: 0306 slli t1,t1,0x1 + 3214: 0900 addi s0,sp,144 + 3216: 0000 unimp + 3218: 0501 addi a0,a0,0 + 321a: 0605 addi a2,a2,1 + 321c: 00090103 lb sp,0(s2) + 3220: 0100 addi s0,sp,128 + 3222: 0805 addi a6,a6,1 + 3224: 0306 slli t1,t1,0x1 + 3226: 0900 addi s0,sp,144 + 3228: 0000 unimp + 322a: 0501 addi a0,a0,0 + 322c: 01030607 .4byte 0x1030607 + 3230: 0009 c.nop 2 + 3232: 0100 addi s0,sp,128 + 3234: 0105 addi sp,sp,1 + 3236: 0306 slli t1,t1,0x1 + 3238: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 323c: 0901 addi s2,s2,0 + 323e: 0000 unimp + 3240: 0100 addi s0,sp,128 + 3242: 0501 addi a0,a0,0 + 3244: 0029 c.nop 10 + 3246: 0205 addi tp,tp,1 # 1 + 3248: 0000 unimp + 324a: 0000 unimp + 324c: 0104fd03 .4byte 0x104fd03 + 3250: 0305 addi t1,t1,1 + 3252: 00090203 lb tp,0(s2) + 3256: 0100 addi s0,sp,128 + 3258: 0c05 addi s8,s8,1 + 325a: 0306 slli t1,t1,0x1 + 325c: 0900 addi s0,sp,144 + 325e: 0000 unimp + 3260: 0501 addi a0,a0,0 + 3262: 03030603 lb a2,48(t1) + 3266: 0009 c.nop 2 + 3268: 0100 addi s0,sp,128 + 326a: 0b05 addi s6,s6,1 + 326c: 0306 slli t1,t1,0x1 + 326e: 0900 addi s0,sp,144 + 3270: 0000 unimp + 3272: 0501 addi a0,a0,0 + 3274: 03030603 lb a2,48(t1) + 3278: 0009 c.nop 2 + 327a: 0100 addi s0,sp,128 + 327c: 0605 addi a2,a2,1 + 327e: 0306 slli t1,t1,0x1 + 3280: 0900 addi s0,sp,144 + 3282: 0000 unimp + 3284: 0501 addi a0,a0,0 + 3286: 05030603 lb a2,80(t1) + 328a: 0009 c.nop 2 + 328c: 0100 addi s0,sp,128 + 328e: 0f05 addi t5,t5,1 + 3290: 0306 slli t1,t1,0x1 + 3292: 0900 addi s0,sp,144 + 3294: 0000 unimp + 3296: 0501 addi a0,a0,0 + 3298: 030c addi a1,sp,384 + 329a: 0901 addi s2,s2,0 + 329c: 0000 unimp + 329e: 0501 addi a0,a0,0 + 32a0: 0306 slli t1,t1,0x1 + 32a2: 097f .2byte 0x97f + 32a4: 0000 unimp + 32a6: 0501 addi a0,a0,0 + 32a8: 05030603 lb a2,80(t1) + 32ac: 0009 c.nop 2 + 32ae: 0100 addi s0,sp,128 + 32b0: 0f05 addi t5,t5,1 + 32b2: 0306 slli t1,t1,0x1 + 32b4: 0900 addi s0,sp,144 + 32b6: 0000 unimp + 32b8: 0501 addi a0,a0,0 + 32ba: 030c addi a1,sp,384 + 32bc: 0901 addi s2,s2,0 + 32be: 0000 unimp + 32c0: 0501 addi a0,a0,0 + 32c2: 0306 slli t1,t1,0x1 + 32c4: 097f .2byte 0x97f + 32c6: 0000 unimp + 32c8: 0501 addi a0,a0,0 + 32ca: 05030603 lb a2,80(t1) + 32ce: 0009 c.nop 2 + 32d0: 0100 addi s0,sp,128 + 32d2: 0f05 addi t5,t5,1 + 32d4: 0306 slli t1,t1,0x1 + 32d6: 0900 addi s0,sp,144 + 32d8: 0000 unimp + 32da: 0501 addi a0,a0,0 + 32dc: 030c addi a1,sp,384 + 32de: 0901 addi s2,s2,0 + 32e0: 0000 unimp + 32e2: 0501 addi a0,a0,0 + 32e4: 0306 slli t1,t1,0x1 + 32e6: 097f .2byte 0x97f + 32e8: 0000 unimp + 32ea: 0501 addi a0,a0,0 + 32ec: 030a slli t1,t1,0x2 + 32ee: 0904 addi s1,sp,144 + 32f0: 0000 unimp + 32f2: 0501 addi a0,a0,0 + 32f4: 096e030b .4byte 0x96e030b + 32f8: 0000 unimp + 32fa: 0501 addi a0,a0,0 + 32fc: 0301 addi t1,t1,0 + 32fe: 00000913 li s2,0 + 3302: 0901 addi s2,s2,0 + 3304: 0000 unimp + 3306: 0100 addi s0,sp,128 + 3308: 0501 addi a0,a0,0 + 330a: 02050027 .4byte 0x2050027 + 330e: 0000 unimp + 3310: 0000 unimp + 3312: 0105a403 lw s0,16(a1) + 3316: 0305 addi t1,t1,1 + 3318: 00090203 lb tp,0(s2) + 331c: 0100 addi s0,sp,128 + 331e: 1405 addi s0,s0,-31 + 3320: 0306 slli t1,t1,0x1 + 3322: 0900 addi s0,sp,144 + 3324: 0000 unimp + 3326: 0501 addi a0,a0,0 + 3328: 0306 slli t1,t1,0x1 + 332a: 0900 addi s0,sp,144 + 332c: 0000 unimp + 332e: 0501 addi a0,a0,0 + 3330: 0301 addi t1,t1,0 + 3332: 0906 slli s2,s2,0x1 + 3334: 0000 unimp + 3336: 0901 addi s2,s2,0 + 3338: 0000 unimp + 333a: 0100 addi s0,sp,128 + 333c: 0501 addi a0,a0,0 + 333e: 002c addi a1,sp,8 + 3340: 0205 addi tp,tp,1 # 1 + 3342: 0000 unimp + 3344: 0000 unimp + 3346: 0105b703 .4byte 0x105b703 + 334a: 0305 addi t1,t1,1 + 334c: 00090203 lb tp,0(s2) + 3350: 0100 addi s0,sp,128 + 3352: 1d05 addi s10,s10,-31 + 3354: 0306 slli t1,t1,0x1 + 3356: 0900 addi s0,sp,144 + 3358: 0000 unimp + 335a: 0501 addi a0,a0,0 + 335c: 0301 addi t1,t1,0 + 335e: 0901 addi s2,s2,0 + 3360: 0000 unimp + 3362: 0901 addi s2,s2,0 + 3364: 0000 unimp + 3366: 0100 addi s0,sp,128 + 3368: 0501 addi a0,a0,0 + 336a: 0028 addi a0,sp,8 + 336c: 0205 addi tp,tp,1 # 1 + 336e: 0000 unimp + 3370: 0000 unimp + 3372: 0105c403 lbu s0,16(a1) + 3376: 0305 addi t1,t1,1 + 3378: 00090203 lb tp,0(s2) + 337c: 0100 addi s0,sp,128 + 337e: 00090103 lb sp,0(s2) + 3382: 0100 addi s0,sp,128 + 3384: 2805 jal 33b4 <__neorv32_ram_size+0x13b4> + 3386: 0306 slli t1,t1,0x1 + 3388: 097d addi s2,s2,31 + 338a: 0000 unimp + 338c: 0301 addi t1,t1,0 + 338e: 0900 addi s0,sp,144 + 3390: 0000 unimp + 3392: 0501 addi a0,a0,0 + 3394: 0308 addi a0,sp,384 + 3396: 0904 addi s1,sp,144 + 3398: 0000 unimp + 339a: 0501 addi a0,a0,0 + 339c: 060a slli a2,a2,0x2 + 339e: 00097f03 .4byte 0x97f03 + 33a2: 0100 addi s0,sp,128 + 33a4: 0d05 addi s10,s10,1 + 33a6: 0306 slli t1,t1,0x1 + 33a8: 0900 addi s0,sp,144 + 33aa: 0000 unimp + 33ac: 0501 addi a0,a0,0 + 33ae: 0311 addi t1,t1,4 + 33b0: 0900 addi s0,sp,144 + 33b2: 0000 unimp + 33b4: 0501 addi a0,a0,0 + 33b6: 030a slli t1,t1,0x2 + 33b8: 0900 addi s0,sp,144 + 33ba: 0000 unimp + 33bc: 0501 addi a0,a0,0 + 33be: 0301 addi t1,t1,0 + 33c0: 0906 slli s2,s2,0x1 + 33c2: 0000 unimp + 33c4: 0501 addi a0,a0,0 + 33c6: 0605 addi a2,a2,1 + 33c8: 00097b03 .4byte 0x97b03 + 33cc: 0100 addi s0,sp,128 + 33ce: 0805 addi a6,a6,1 + 33d0: 0306 slli t1,t1,0x1 + 33d2: 0900 addi s0,sp,144 + 33d4: 0000 unimp + 33d6: 0501 addi a0,a0,0 + 33d8: 01030607 .4byte 0x1030607 + 33dc: 0009 c.nop 2 + 33de: 0100 addi s0,sp,128 + 33e0: 0505 addi a0,a0,1 + 33e2: 00090203 lb tp,0(s2) + 33e6: 0100 addi s0,sp,128 + 33e8: 0009 c.nop 2 + 33ea: 0000 unimp + 33ec: 0101 addi sp,sp,0 + 33ee: 3405 jal 2e0e <__neorv32_ram_size+0xe0e> + 33f0: 0500 addi s0,sp,640 + 33f2: 0002 c.slli64 zero + 33f4: 0000 unimp + 33f6: 0300 addi s0,sp,384 + 33f8: 05e1 addi a1,a1,24 + 33fa: 0501 addi a0,a0,0 + 33fc: 09020303 lb t1,144(tp) # 90 <__crt0_copy_data+0x14> + 3400: 0000 unimp + 3402: 0301 addi t1,t1,0 + 3404: 0901 addi s2,s2,0 + 3406: 0000 unimp + 3408: 0301 addi t1,t1,0 + 340a: 0902 c.slli64 s2 + 340c: 0000 unimp + 340e: 0301 addi t1,t1,0 + 3410: 0901 addi s2,s2,0 + 3412: 0000 unimp + 3414: 0501 addi a0,a0,0 + 3416: 0634 addi a3,sp,776 + 3418: 00097a03 .4byte 0x97a03 + 341c: 0100 addi s0,sp,128 + 341e: 0305 addi t1,t1,1 + 3420: 00090603 lb a2,0(s2) + 3424: 0100 addi s0,sp,128 + 3426: 3405 jal 2e46 <__neorv32_ram_size+0xe46> + 3428: 00097a03 .4byte 0x97a03 + 342c: 0100 addi s0,sp,128 + 342e: 00090003 lb zero,0(s2) + 3432: 0100 addi s0,sp,128 + 3434: 0305 addi t1,t1,1 + 3436: 00090603 lb a2,0(s2) + 343a: 0100 addi s0,sp,128 + 343c: 0306 slli t1,t1,0x1 + 343e: 0902 c.slli64 s2 + 3440: 0000 unimp + 3442: 0501 addi a0,a0,0 + 3444: 0608 addi a0,sp,768 + 3446: 00090103 lb sp,0(s2) + 344a: 0100 addi s0,sp,128 + 344c: 0a05 addi s4,s4,1 + 344e: 00092703 lw a4,0(s2) + 3452: 0100 addi s0,sp,128 + 3454: 0705 addi a4,a4,1 + 3456: 00095b03 lhu s6,0(s2) + 345a: 0100 addi s0,sp,128 + 345c: 0a05 addi s4,s4,1 + 345e: 0306 slli t1,t1,0x1 + 3460: 097d addi s2,s2,31 + 3462: 0000 unimp + 3464: 0501 addi a0,a0,0 + 3466: 060d addi a2,a2,3 + 3468: 00090003 lb zero,0(s2) + 346c: 0100 addi s0,sp,128 + 346e: 0a05 addi s4,s4,1 + 3470: 00090003 lb zero,0(s2) + 3474: 0100 addi s0,sp,128 + 3476: 0105 addi sp,sp,1 + 3478: 00092f03 lw t5,0(s2) + 347c: 0100 addi s0,sp,128 + 347e: 0505 addi a0,a0,1 + 3480: 0306 slli t1,t1,0x1 + 3482: 0952 slli s2,s2,0x14 + 3484: 0000 unimp + 3486: 0501 addi a0,a0,0 + 3488: 0608 addi a0,sp,768 + 348a: 00090003 lb zero,0(s2) + 348e: 0100 addi s0,sp,128 + 3490: 0705 addi a4,a4,1 + 3492: 0306 slli t1,t1,0x1 + 3494: 0901 addi s2,s2,0 + 3496: 0000 unimp + 3498: 0501 addi a0,a0,0 + 349a: 0609 addi a2,a2,2 + 349c: 00090003 lb zero,0(s2) + 34a0: 0100 addi s0,sp,128 + 34a2: 0705 addi a4,a4,1 + 34a4: 0306 slli t1,t1,0x1 + 34a6: 0901 addi s2,s2,0 + 34a8: 0000 unimp + 34aa: 0501 addi a0,a0,0 + 34ac: 091f030b .4byte 0x91f030b + 34b0: 0000 unimp + 34b2: 0301 addi t1,t1,0 + 34b4: 0901 addi s2,s2,0 + 34b6: 0000 unimp + 34b8: 0501 addi a0,a0,0 + 34ba: 60030607 .4byte 0x60030607 + 34be: 0009 c.nop 2 + 34c0: 0100 addi s0,sp,128 + 34c2: 0b05 addi s6,s6,1 + 34c4: 0306 slli t1,t1,0x1 + 34c6: 0909 addi s2,s2,2 + 34c8: 0000 unimp + 34ca: 0501 addi a0,a0,0 + 34cc: 060d addi a2,a2,3 + 34ce: 00090003 lb zero,0(s2) + 34d2: 0100 addi s0,sp,128 + 34d4: 0b05 addi s6,s6,1 + 34d6: 0306 slli t1,t1,0x1 + 34d8: 0901 addi s2,s2,0 + 34da: 0000 unimp + 34dc: 0501 addi a0,a0,0 + 34de: 060d addi a2,a2,3 + 34e0: 00097f03 .4byte 0x97f03 + 34e4: 0100 addi s0,sp,128 + 34e6: 0e05 addi t3,t3,1 + 34e8: 00090103 lb sp,0(s2) + 34ec: 0100 addi s0,sp,128 + 34ee: 0d05 addi s10,s10,1 + 34f0: 0306 slli t1,t1,0x1 + 34f2: 0901 addi s2,s2,0 + 34f4: 0000 unimp + 34f6: 0601 addi a2,a2,0 + 34f8: 00090103 lb sp,0(s2) + 34fc: 0100 addi s0,sp,128 + 34fe: 0f05 addi t5,t5,1 + 3500: 00097f03 .4byte 0x97f03 + 3504: 0100 addi s0,sp,128 + 3506: 0d05 addi s10,s10,1 + 3508: 0306 slli t1,t1,0x1 + 350a: 0901 addi s2,s2,0 + 350c: 0000 unimp + 350e: 0501 addi a0,a0,0 + 3510: 0902030b .4byte 0x902030b + 3514: 0000 unimp + 3516: 0601 addi a2,a2,0 + 3518: 00090403 lb s0,0(s2) + 351c: 0100 addi s0,sp,128 + 351e: 0306 slli t1,t1,0x1 + 3520: 0901 addi s2,s2,0 + 3522: 0000 unimp + 3524: 0501 addi a0,a0,0 + 3526: 6d030607 .4byte 0x6d030607 + 352a: 0009 c.nop 2 + 352c: 0100 addi s0,sp,128 + 352e: 0b05 addi s6,s6,1 + 3530: 0306 slli t1,t1,0x1 + 3532: 0902 c.slli64 s2 + 3534: 0000 unimp + 3536: 0501 addi a0,a0,0 + 3538: 061e slli a2,a2,0x7 + 353a: 00090003 lb zero,0(s2) + 353e: 0100 addi s0,sp,128 + 3540: 0b05 addi s6,s6,1 + 3542: 00090003 lb zero,0(s2) + 3546: 0100 addi s0,sp,128 + 3548: 1e05 addi t3,t3,-31 + 354a: 00090003 lb zero,0(s2) + 354e: 0100 addi s0,sp,128 + 3550: 0b05 addi s6,s6,1 + 3552: 00091103 lh sp,0(s2) + 3556: 0100 addi s0,sp,128 + 3558: 0306 slli t1,t1,0x1 + 355a: 0901 addi s2,s2,0 + 355c: 0000 unimp + 355e: 0501 addi a0,a0,0 + 3560: 0612 slli a2,a2,0x4 + 3562: 00096b03 .4byte 0x96b03 + 3566: 0100 addi s0,sp,128 + 3568: 0b05 addi s6,s6,1 + 356a: 0306 slli t1,t1,0x1 + 356c: 0906 slli s2,s2,0x1 + 356e: 0000 unimp + 3570: 0501 addi a0,a0,0 + 3572: 0624 addi s1,sp,776 + 3574: 00090003 lb zero,0(s2) + 3578: 0100 addi s0,sp,128 + 357a: 0b05 addi s6,s6,1 + 357c: 00090003 lb zero,0(s2) + 3580: 0100 addi s0,sp,128 + 3582: 2405 jal 37a2 <__neorv32_ram_size+0x17a2> + 3584: 00090003 lb zero,0(s2) + 3588: 0100 addi s0,sp,128 + 358a: 0b05 addi s6,s6,1 + 358c: 00091b03 lh s6,0(s2) + 3590: 0100 addi s0,sp,128 + 3592: 0306 slli t1,t1,0x1 + 3594: 0901 addi s2,s2,0 + 3596: 0000 unimp + 3598: 0301 addi t1,t1,0 + 359a: 0971 addi s2,s2,28 + 359c: 0000 unimp + 359e: 0301 addi t1,t1,0 + 35a0: 0906 slli s2,s2,0x1 + 35a2: 0000 unimp + 35a4: 0301 addi t1,t1,0 + 35a6: 0901 addi s2,s2,0 + 35a8: 0000 unimp + 35aa: 0501 addi a0,a0,0 + 35ac: 030d addi t1,t1,3 + 35ae: 0901 addi s2,s2,0 + 35b0: 0000 unimp + 35b2: 0501 addi a0,a0,0 + 35b4: 097e030b .4byte 0x97e030b + 35b8: 0000 unimp + 35ba: 0301 addi t1,t1,0 + 35bc: 0901 addi s2,s2,0 + 35be: 0000 unimp + 35c0: 0301 addi t1,t1,0 + 35c2: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 35c6: 0501 addi a0,a0,0 + 35c8: 09090307 .4byte 0x9090307 + 35cc: 0000 unimp + 35ce: 0501 addi a0,a0,0 + 35d0: 060a slli a2,a2,0x2 + 35d2: 00090003 lb zero,0(s2) + 35d6: 0100 addi s0,sp,128 + 35d8: 0905 addi s2,s2,1 + 35da: 0306 slli t1,t1,0x1 + 35dc: 0901 addi s2,s2,0 + 35de: 0000 unimp + 35e0: 0501 addi a0,a0,0 + 35e2: 02030607 .4byte 0x2030607 + 35e6: 0009 c.nop 2 + 35e8: 0100 addi s0,sp,128 + 35ea: 1605 addi a2,a2,-31 + 35ec: 00095503 lhu a0,0(s2) + 35f0: 0100 addi s0,sp,128 + 35f2: 0705 addi a4,a4,1 + 35f4: 0306 slli t1,t1,0x1 + 35f6: 0000092b .4byte 0x92b + 35fa: 0901 addi s2,s2,0 + 35fc: 0000 unimp + 35fe: 0100 addi s0,sp,128 + 3600: 0501 addi a0,a0,0 + 3602: 003e c.slli zero,0xf + 3604: 0205 addi tp,tp,1 # 1 + 3606: 0000 unimp + 3608: 0000 unimp + 360a: 0106a503 lw a0,16(a3) + 360e: 0305 addi t1,t1,1 + 3610: 00090203 lb tp,0(s2) + 3614: 0100 addi s0,sp,128 + 3616: 00090103 lb sp,0(s2) + 361a: 0100 addi s0,sp,128 + 361c: 3e05 jal 314c <__neorv32_ram_size+0x114c> + 361e: 0306 slli t1,t1,0x1 + 3620: 097d addi s2,s2,31 + 3622: 0000 unimp + 3624: 0301 addi t1,t1,0 + 3626: 0900 addi s0,sp,144 + 3628: 0000 unimp + 362a: 0501 addi a0,a0,0 + 362c: 09030307 .4byte 0x9030307 + 3630: 0000 unimp + 3632: 0501 addi a0,a0,0 + 3634: 0308 addi a0,sp,384 + 3636: 0904 addi s1,sp,144 + 3638: 0000 unimp + 363a: 0501 addi a0,a0,0 + 363c: 030d addi t1,t1,3 + 363e: 0909 addi s2,s2,2 + 3640: 0000 unimp + 3642: 0301 addi t1,t1,0 + 3644: 0902 c.slli64 s2 + 3646: 0000 unimp + 3648: 0501 addi a0,a0,0 + 364a: 033d addi t1,t1,15 + 364c: 0900 addi s0,sp,144 + 364e: 0000 unimp + 3650: 0501 addi a0,a0,0 + 3652: 73030603 lb a2,1840(t1) + 3656: 0009 c.nop 2 + 3658: 0100 addi s0,sp,128 + 365a: 0505 addi a0,a0,1 + 365c: 00090103 lb sp,0(s2) + 3660: 0100 addi s0,sp,128 + 3662: 0905 addi s2,s2,1 + 3664: 0306 slli t1,t1,0x1 + 3666: 0900 addi s0,sp,144 + 3668: 0000 unimp + 366a: 0501 addi a0,a0,0 + 366c: 0605 addi a2,a2,1 + 366e: 00090103 lb sp,0(s2) + 3672: 0100 addi s0,sp,128 + 3674: 0805 addi a6,a6,1 + 3676: 0306 slli t1,t1,0x1 + 3678: 0900 addi s0,sp,144 + 367a: 0000 unimp + 367c: 0501 addi a0,a0,0 + 367e: 01030607 .4byte 0x1030607 + 3682: 0009 c.nop 2 + 3684: 0100 addi s0,sp,128 + 3686: 0a05 addi s4,s4,1 + 3688: 0306 slli t1,t1,0x1 + 368a: 0900 addi s0,sp,144 + 368c: 0000 unimp + 368e: 0501 addi a0,a0,0 + 3690: 0609 addi a2,a2,2 + 3692: 00090103 lb sp,0(s2) + 3696: 0100 addi s0,sp,128 + 3698: 0c05 addi s8,s8,1 + 369a: 0306 slli t1,t1,0x1 + 369c: 0900 addi s0,sp,144 + 369e: 0000 unimp + 36a0: 0501 addi a0,a0,0 + 36a2: 0103060b .4byte 0x103060b + 36a6: 0009 c.nop 2 + 36a8: 0100 addi s0,sp,128 + 36aa: 0905 addi s2,s2,1 + 36ac: 00090203 lb tp,0(s2) + 36b0: 0100 addi s0,sp,128 + 36b2: 0f05 addi t5,t5,1 + 36b4: 0306 slli t1,t1,0x1 + 36b6: 0900 addi s0,sp,144 + 36b8: 0000 unimp + 36ba: 0501 addi a0,a0,0 + 36bc: 0609 addi a2,a2,2 + 36be: 00090103 lb sp,0(s2) + 36c2: 0100 addi s0,sp,128 + 36c4: 0f05 addi t5,t5,1 + 36c6: 0306 slli t1,t1,0x1 + 36c8: 0900 addi s0,sp,144 + 36ca: 0000 unimp + 36cc: 0501 addi a0,a0,0 + 36ce: 060a slli a2,a2,0x2 + 36d0: 00090303 lb t1,0(s2) + 36d4: 0100 addi s0,sp,128 + 36d6: 0d05 addi s10,s10,1 + 36d8: 0306 slli t1,t1,0x1 + 36da: 0900 addi s0,sp,144 + 36dc: 0000 unimp + 36de: 0501 addi a0,a0,0 + 36e0: 060a slli a2,a2,0x2 + 36e2: 00090203 lb tp,0(s2) + 36e6: 0100 addi s0,sp,128 + 36e8: 1905 addi s2,s2,-31 + 36ea: 0306 slli t1,t1,0x1 + 36ec: 0900 addi s0,sp,144 + 36ee: 0000 unimp + 36f0: 0501 addi a0,a0,0 + 36f2: 030d addi t1,t1,3 + 36f4: 0900 addi s0,sp,144 + 36f6: 0000 unimp + 36f8: 0501 addi a0,a0,0 + 36fa: 04020027 .4byte 0x4020027 + 36fe: 0301 addi t1,t1,0 + 3700: 0900 addi s0,sp,144 + 3702: 0000 unimp + 3704: 0501 addi a0,a0,0 + 3706: 01030607 .4byte 0x1030607 + 370a: 0009 c.nop 2 + 370c: 0100 addi s0,sp,128 + 370e: 0a05 addi s4,s4,1 + 3710: 0306 slli t1,t1,0x1 + 3712: 0900 addi s0,sp,144 + 3714: 0000 unimp + 3716: 0501 addi a0,a0,0 + 3718: 0609 addi a2,a2,2 + 371a: 00090103 lb sp,0(s2) + 371e: 0100 addi s0,sp,128 + 3720: 0705 addi a4,a4,1 + 3722: 00090203 lb tp,0(s2) + 3726: 0100 addi s0,sp,128 + 3728: 1105 addi sp,sp,-31 + 372a: 0306 slli t1,t1,0x1 + 372c: 0900 addi s0,sp,144 + 372e: 0000 unimp + 3730: 0501 addi a0,a0,0 + 3732: 030e slli t1,t1,0x3 + 3734: 0900 addi s0,sp,144 + 3736: 0000 unimp + 3738: 0501 addi a0,a0,0 + 373a: 01030607 .4byte 0x1030607 + 373e: 0009 c.nop 2 + 3740: 0100 addi s0,sp,128 + 3742: 0905 addi s2,s2,1 + 3744: 0306 slli t1,t1,0x1 + 3746: 0000096f jal s2,3746 <__neorv32_ram_size+0x1746> + 374a: 0501 addi a0,a0,0 + 374c: 030d addi t1,t1,3 + 374e: 0911 addi s2,s2,4 + 3750: 0000 unimp + 3752: 0501 addi a0,a0,0 + 3754: 6e030603 lb a2,1760(t1) + 3758: 0009 c.nop 2 + 375a: 0100 addi s0,sp,128 + 375c: 0505 addi a0,a0,1 + 375e: 00090103 lb sp,0(s2) + 3762: 0100 addi s0,sp,128 + 3764: 00090103 lb sp,0(s2) + 3768: 0100 addi s0,sp,128 + 376a: 0e05 addi t3,t3,1 + 376c: 0306 slli t1,t1,0x1 + 376e: 0000090f .4byte 0x90f + 3772: 0501 addi a0,a0,0 + 3774: 0308 addi a0,sp,384 + 3776: 0971 addi s2,s2,28 + 3778: 0000 unimp + 377a: 0501 addi a0,a0,0 + 377c: 13030603 lb a2,304(t1) + 3780: 0009 c.nop 2 + 3782: 0100 addi s0,sp,128 + 3784: 0b05 addi s6,s6,1 + 3786: 0306 slli t1,t1,0x1 + 3788: 0900 addi s0,sp,144 + 378a: 0000 unimp + 378c: 0501 addi a0,a0,0 + 378e: 02030603 lb a2,32(t1) + 3792: 0009 c.nop 2 + 3794: 0100 addi s0,sp,128 + 3796: 0105 addi sp,sp,1 + 3798: 0306 slli t1,t1,0x1 + 379a: 0901 addi s2,s2,0 + 379c: 0000 unimp + 379e: 0901 addi s2,s2,0 + 37a0: 0000 unimp + 37a2: 0100 addi s0,sp,128 + 37a4: db01 beqz a4,36b4 <__neorv32_ram_size+0x16b4> + 37a6: 05000007 .4byte 0x5000007 + 37aa: 0400 addi s0,sp,512 + 37ac: 7a00 .2byte 0x7a00 + 37ae: 0000 unimp + 37b0: 0100 addi s0,sp,128 + 37b2: 0101 addi sp,sp,0 + 37b4: 000d0efb .4byte 0xd0efb + 37b8: 0101 addi sp,sp,0 + 37ba: 0101 addi sp,sp,0 + 37bc: 0000 unimp + 37be: 0100 addi s0,sp,128 + 37c0: 0000 unimp + 37c2: 0101 addi sp,sp,0 + 37c4: 1f01 addi t5,t5,-32 + 37c6: 9806 add a6,a6,ra + 37c8: 0001 nop + 37ca: db00 sw s0,48(a4) + 37cc: 0001 nop + 37ce: 3c00 .2byte 0x3c00 + 37d0: 0000 unimp + 37d2: 9600 .2byte 0x9600 + 37d4: 0000 unimp + 37d6: 6b00 .2byte 0x6b00 + 37d8: 0000 unimp + 37da: f200 .2byte 0xf200 + 37dc: 0001 nop + 37de: 0200 addi s0,sp,256 + 37e0: 1f01 addi t5,t5,-32 + 37e2: 0f02 c.slli64 t5 + 37e4: 8e0e mv t3,gp + 37e6: 0002 c.slli64 zero + 37e8: 0100 addi s0,sp,128 + 37ea: 028e slli t0,t0,0x3 + 37ec: 0000 unimp + 37ee: 0d01 addi s10,s10,0 + 37f0: 0001 nop + 37f2: 0200 addi s0,sp,256 + 37f4: 0128 addi a0,sp,136 + 37f6: 0000 unimp + 37f8: 00011503 lh a0,0(sp) + 37fc: 0400 addi s0,sp,512 + 37fe: 0299 addi t0,t0,6 + 3800: 0000 unimp + 3802: a404 .2byte 0xa404 + 3804: 0002 c.slli64 zero + 3806: 0400 addi s0,sp,512 + 3808: 0116 slli sp,sp,0x5 + 380a: 0000 unimp + 380c: b004 .2byte 0xb004 + 380e: 0002 c.slli64 zero + 3810: 0400 addi s0,sp,512 + 3812: 000002b7 lui t0,0x0 + 3816: bf04 .2byte 0xbf04 + 3818: 0002 c.slli64 zero + 381a: 0400 addi s0,sp,512 + 381c: 000002c7 .4byte 0x2c7 + 3820: 3b04 .2byte 0x3b04 + 3822: 0001 nop + 3824: 0500 addi s0,sp,640 + 3826: 000002cf .4byte 0x2cf + 382a: 0504 addi s1,sp,640 + 382c: 0001 nop + 382e: 0205 addi tp,tp,1 # 1 + 3830: 0000 unimp + 3832: 0000 unimp + 3834: 05013b03 .4byte 0x5013b03 + 3838: 09010303 lb t1,144(sp) + 383c: 0000 unimp + 383e: 0501 addi a0,a0,0 + 3840: 0601 addi a2,a2,0 + 3842: 00097f03 .4byte 0x97f03 + 3846: 0100 addi s0,sp,128 + 3848: 0705 addi a4,a4,1 + 384a: 00090103 lb sp,0(s2) + 384e: 0100 addi s0,sp,128 + 3850: 0605 addi a2,a2,1 + 3852: 00090003 lb zero,0(s2) + 3856: 0100 addi s0,sp,128 + 3858: 0505 addi a0,a0,1 + 385a: 0306 slli t1,t1,0x1 + 385c: 0901 addi s2,s2,0 + 385e: 0000 unimp + 3860: 0501 addi a0,a0,0 + 3862: 0601 addi a2,a2,0 + 3864: 00090203 lb tp,0(s2) + 3868: 0100 addi s0,sp,128 + 386a: 0505 addi a0,a0,1 + 386c: 00097e03 .4byte 0x97e03 + 3870: 0100 addi s0,sp,128 + 3872: 0105 addi sp,sp,1 + 3874: 00090203 lb tp,0(s2) + 3878: 0100 addi s0,sp,128 + 387a: 0505 addi a0,a0,1 + 387c: 00097e03 .4byte 0x97e03 + 3880: 0100 addi s0,sp,128 + 3882: 0105 addi sp,sp,1 + 3884: 00090203 lb tp,0(s2) + 3888: 0100 addi s0,sp,128 + 388a: 0505 addi a0,a0,1 + 388c: 00097e03 .4byte 0x97e03 + 3890: 0100 addi s0,sp,128 + 3892: 0105 addi sp,sp,1 + 3894: 00090203 lb tp,0(s2) + 3898: 0100 addi s0,sp,128 + 389a: 0009 c.nop 2 + 389c: 0000 unimp + 389e: 0101 addi sp,sp,0 + 38a0: 0105 addi sp,sp,1 + 38a2: 0500 addi s0,sp,640 + 38a4: 0002 c.slli64 zero + 38a6: 0000 unimp + 38a8: 0300 addi s0,sp,384 + 38aa: 00c2 slli ra,ra,0x10 + 38ac: 0501 addi a0,a0,0 + 38ae: 0305 addi t1,t1,1 + 38b0: 0901 addi s2,s2,0 + 38b2: 0000 unimp + 38b4: 0501 addi a0,a0,0 + 38b6: 0003060b .4byte 0x3060b + 38ba: 0009 c.nop 2 + 38bc: 0100 addi s0,sp,128 + 38be: 0505 addi a0,a0,1 + 38c0: 0306 slli t1,t1,0x1 + 38c2: 0901 addi s2,s2,0 + 38c4: 0000 unimp + 38c6: 0501 addi a0,a0,0 + 38c8: 0601 addi a2,a2,0 + 38ca: 00090103 lb sp,0(s2) + 38ce: 0100 addi s0,sp,128 + 38d0: 0009 c.nop 2 + 38d2: 0000 unimp + 38d4: 0101 addi sp,sp,0 + 38d6: 0105 addi sp,sp,1 + 38d8: 0500 addi s0,sp,640 + 38da: 0002 c.slli64 zero + 38dc: 0000 unimp + 38de: 0300 addi s0,sp,384 + 38e0: 00c8 addi a0,sp,68 + 38e2: 0501 addi a0,a0,0 + 38e4: 0305 addi t1,t1,1 + 38e6: 0901 addi s2,s2,0 + 38e8: 0000 unimp + 38ea: 0501 addi a0,a0,0 + 38ec: 0003060b .4byte 0x3060b + 38f0: 0009 c.nop 2 + 38f2: 0100 addi s0,sp,128 + 38f4: 0505 addi a0,a0,1 + 38f6: 0306 slli t1,t1,0x1 + 38f8: 0901 addi s2,s2,0 + 38fa: 0000 unimp + 38fc: 0501 addi a0,a0,0 + 38fe: 0601 addi a2,a2,0 + 3900: 00090103 lb sp,0(s2) + 3904: 0100 addi s0,sp,128 + 3906: 0009 c.nop 2 + 3908: 0000 unimp + 390a: 0101 addi sp,sp,0 + 390c: 0105 addi sp,sp,1 + 390e: 0500 addi s0,sp,640 + 3910: 0002 c.slli64 zero + 3912: 0000 unimp + 3914: 0300 addi s0,sp,384 + 3916: 00ce slli ra,ra,0x13 + 3918: 0501 addi a0,a0,0 + 391a: 0305 addi t1,t1,1 + 391c: 0901 addi s2,s2,0 + 391e: 0000 unimp + 3920: 0501 addi a0,a0,0 + 3922: 0003060b .4byte 0x3060b + 3926: 0009 c.nop 2 + 3928: 0100 addi s0,sp,128 + 392a: 0505 addi a0,a0,1 + 392c: 0306 slli t1,t1,0x1 + 392e: 0901 addi s2,s2,0 + 3930: 0000 unimp + 3932: 0501 addi a0,a0,0 + 3934: 0601 addi a2,a2,0 + 3936: 00090103 lb sp,0(s2) + 393a: 0100 addi s0,sp,128 + 393c: 0009 c.nop 2 + 393e: 0000 unimp + 3940: 0101 addi sp,sp,0 + 3942: 0105 addi sp,sp,1 + 3944: 0500 addi s0,sp,640 + 3946: 0002 c.slli64 zero + 3948: 0000 unimp + 394a: 0300 addi s0,sp,384 + 394c: 00d4 addi a3,sp,68 + 394e: 0501 addi a0,a0,0 + 3950: 0305 addi t1,t1,1 + 3952: 0901 addi s2,s2,0 + 3954: 0000 unimp + 3956: 0501 addi a0,a0,0 + 3958: 0003060b .4byte 0x3060b + 395c: 0009 c.nop 2 + 395e: 0100 addi s0,sp,128 + 3960: 0505 addi a0,a0,1 + 3962: 0306 slli t1,t1,0x1 + 3964: 0901 addi s2,s2,0 + 3966: 0000 unimp + 3968: 0501 addi a0,a0,0 + 396a: 0601 addi a2,a2,0 + 396c: 00090103 lb sp,0(s2) + 3970: 0100 addi s0,sp,128 + 3972: 0009 c.nop 2 + 3974: 0000 unimp + 3976: 0101 addi sp,sp,0 + 3978: 0105 addi sp,sp,1 + 397a: 0500 addi s0,sp,640 + 397c: 0002 c.slli64 zero + 397e: 0000 unimp + 3980: 0300 addi s0,sp,384 + 3982: 00da slli ra,ra,0x16 + 3984: 0501 addi a0,a0,0 + 3986: 0305 addi t1,t1,1 + 3988: 0901 addi s2,s2,0 + 398a: 0000 unimp + 398c: 0501 addi a0,a0,0 + 398e: 0003060b .4byte 0x3060b + 3992: 0009 c.nop 2 + 3994: 0100 addi s0,sp,128 + 3996: 0505 addi a0,a0,1 + 3998: 0306 slli t1,t1,0x1 + 399a: 0901 addi s2,s2,0 + 399c: 0000 unimp + 399e: 0501 addi a0,a0,0 + 39a0: 0601 addi a2,a2,0 + 39a2: 00090103 lb sp,0(s2) + 39a6: 0100 addi s0,sp,128 + 39a8: 0009 c.nop 2 + 39aa: 0000 unimp + 39ac: 0101 addi sp,sp,0 + 39ae: 0105 addi sp,sp,1 + 39b0: 0500 addi s0,sp,640 + 39b2: 0002 c.slli64 zero + 39b4: 0000 unimp + 39b6: 0300 addi s0,sp,384 + 39b8: 00e0 addi s0,sp,76 + 39ba: 0501 addi a0,a0,0 + 39bc: 0305 addi t1,t1,1 + 39be: 0901 addi s2,s2,0 + 39c0: 0000 unimp + 39c2: 0501 addi a0,a0,0 + 39c4: 0601 addi a2,a2,0 + 39c6: 00090103 lb sp,0(s2) + 39ca: 0100 addi s0,sp,128 + 39cc: 0009 c.nop 2 + 39ce: 0000 unimp + 39d0: 0101 addi sp,sp,0 + 39d2: 0105 addi sp,sp,1 + 39d4: 0500 addi s0,sp,640 + 39d6: 0002 c.slli64 zero + 39d8: 0000 unimp + 39da: 0300 addi s0,sp,384 + 39dc: 00e5 addi ra,ra,25 + 39de: 0501 addi a0,a0,0 + 39e0: 0305 addi t1,t1,1 + 39e2: 0901 addi s2,s2,0 + 39e4: 0000 unimp + 39e6: 0501 addi a0,a0,0 + 39e8: 0003060b .4byte 0x3060b + 39ec: 0009 c.nop 2 + 39ee: 0100 addi s0,sp,128 + 39f0: 0505 addi a0,a0,1 + 39f2: 0306 slli t1,t1,0x1 + 39f4: 0901 addi s2,s2,0 + 39f6: 0000 unimp + 39f8: 0501 addi a0,a0,0 + 39fa: 0601 addi a2,a2,0 + 39fc: 00090103 lb sp,0(s2) + 3a00: 0100 addi s0,sp,128 + 3a02: 0009 c.nop 2 + 3a04: 0000 unimp + 3a06: 0101 addi sp,sp,0 + 3a08: 0105 addi sp,sp,1 + 3a0a: 0500 addi s0,sp,640 + 3a0c: 0002 c.slli64 zero + 3a0e: 0000 unimp + 3a10: 0300 addi s0,sp,384 + 3a12: 050100eb .4byte 0x50100eb + 3a16: 0305 addi t1,t1,1 + 3a18: 0902 c.slli64 s2 + 3a1a: 0000 unimp + 3a1c: 0001 nop + 3a1e: 0402 c.slli64 s0 + 3a20: 0301 addi t1,t1,0 + 3a22: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 3a26: 0501 addi a0,a0,0 + 3a28: 000a c.slli zero,0x2 + 3a2a: 0402 c.slli64 s0 + 3a2c: 0301 addi t1,t1,0 + 3a2e: 0900 addi s0,sp,144 + 3a30: 0000 unimp + 3a32: 0901 addi s2,s2,0 + 3a34: 0000 unimp + 3a36: 0100 addi s0,sp,128 + 3a38: 0501 addi a0,a0,0 + 3a3a: 0001 nop + 3a3c: 0205 addi tp,tp,1 # 1 + 3a3e: 0000 unimp + 3a40: 0000 unimp + 3a42: 0100f403 .4byte 0x100f403 + 3a46: 0505 addi a0,a0,1 + 3a48: 00090103 lb sp,0(s2) + 3a4c: 0100 addi s0,sp,128 + 3a4e: 0b05 addi s6,s6,1 + 3a50: 0306 slli t1,t1,0x1 + 3a52: 0900 addi s0,sp,144 + 3a54: 0000 unimp + 3a56: 0501 addi a0,a0,0 + 3a58: 0605 addi a2,a2,1 + 3a5a: 00090103 lb sp,0(s2) + 3a5e: 0100 addi s0,sp,128 + 3a60: 0105 addi sp,sp,1 + 3a62: 0306 slli t1,t1,0x1 + 3a64: 0901 addi s2,s2,0 + 3a66: 0000 unimp + 3a68: 0901 addi s2,s2,0 + 3a6a: 0000 unimp + 3a6c: 0100 addi s0,sp,128 + 3a6e: 0501 addi a0,a0,0 + 3a70: 0001 nop + 3a72: 0205 addi tp,tp,1 # 1 + 3a74: 0000 unimp + 3a76: 0000 unimp + 3a78: 0100fa03 .4byte 0x100fa03 + 3a7c: 0505 addi a0,a0,1 + 3a7e: 00090103 lb sp,0(s2) + 3a82: 0100 addi s0,sp,128 + 3a84: 0b05 addi s6,s6,1 + 3a86: 0306 slli t1,t1,0x1 + 3a88: 0900 addi s0,sp,144 + 3a8a: 0000 unimp + 3a8c: 0501 addi a0,a0,0 + 3a8e: 0605 addi a2,a2,1 + 3a90: 00090103 lb sp,0(s2) + 3a94: 0100 addi s0,sp,128 + 3a96: 0105 addi sp,sp,1 + 3a98: 0306 slli t1,t1,0x1 + 3a9a: 0901 addi s2,s2,0 + 3a9c: 0000 unimp + 3a9e: 0901 addi s2,s2,0 + 3aa0: 0000 unimp + 3aa2: 0100 addi s0,sp,128 + 3aa4: 0501 addi a0,a0,0 + 3aa6: 0001 nop + 3aa8: 0205 addi tp,tp,1 # 1 + 3aaa: 0000 unimp + 3aac: 0000 unimp + 3aae: 01018003 lb zero,16(gp) # 80001050 <__global_pointer$+0x10> + 3ab2: 0505 addi a0,a0,1 + 3ab4: 00090103 lb sp,0(s2) + 3ab8: 0100 addi s0,sp,128 + 3aba: 1105 addi sp,sp,-31 + 3abc: 0306 slli t1,t1,0x1 + 3abe: 0900 addi s0,sp,144 + 3ac0: 0000 unimp + 3ac2: 0501 addi a0,a0,0 + 3ac4: 0605 addi a2,a2,1 + 3ac6: 00090103 lb sp,0(s2) + 3aca: 0100 addi s0,sp,128 + 3acc: 0105 addi sp,sp,1 + 3ace: 0306 slli t1,t1,0x1 + 3ad0: 0901 addi s2,s2,0 + 3ad2: 0000 unimp + 3ad4: 0901 addi s2,s2,0 + 3ad6: 0000 unimp + 3ad8: 0100 addi s0,sp,128 + 3ada: 0501 addi a0,a0,0 + 3adc: 0001 nop + 3ade: 0205 addi tp,tp,1 # 1 + 3ae0: 0000 unimp + 3ae2: 0000 unimp + 3ae4: 01018603 lb a2,16(gp) # 80001050 <__global_pointer$+0x10> + 3ae8: 0505 addi a0,a0,1 + 3aea: 00090103 lb sp,0(s2) + 3aee: 0100 addi s0,sp,128 + 3af0: 0b05 addi s6,s6,1 + 3af2: 0306 slli t1,t1,0x1 + 3af4: 0900 addi s0,sp,144 + 3af6: 0000 unimp + 3af8: 0501 addi a0,a0,0 + 3afa: 0605 addi a2,a2,1 + 3afc: 00090103 lb sp,0(s2) + 3b00: 0100 addi s0,sp,128 + 3b02: 0105 addi sp,sp,1 + 3b04: 0306 slli t1,t1,0x1 + 3b06: 0901 addi s2,s2,0 + 3b08: 0000 unimp + 3b0a: 0901 addi s2,s2,0 + 3b0c: 0000 unimp + 3b0e: 0100 addi s0,sp,128 + 3b10: 0501 addi a0,a0,0 + 3b12: 0005 c.nop 1 + 3b14: 0205 addi tp,tp,1 # 1 + 3b16: 0000 unimp + 3b18: 0000 unimp + 3b1a: 01018b03 lb s6,16(gp) # 80001050 <__global_pointer$+0x10> + 3b1e: 0009 c.nop 2 + 3b20: 0000 unimp + 3b22: 0101 addi sp,sp,0 + 3b24: 0105 addi sp,sp,1 + 3b26: 0500 addi s0,sp,640 + 3b28: 0002 c.slli64 zero + 3b2a: 0000 unimp + 3b2c: 0300 addi s0,sp,384 + 3b2e: 0192 slli gp,gp,0x4 + 3b30: 0501 addi a0,a0,0 + 3b32: 0305 addi t1,t1,1 + 3b34: 0901 addi s2,s2,0 + 3b36: 0000 unimp + 3b38: 0501 addi a0,a0,0 + 3b3a: 0003060b .4byte 0x3060b + 3b3e: 0009 c.nop 2 + 3b40: 0100 addi s0,sp,128 + 3b42: 0505 addi a0,a0,1 + 3b44: 0306 slli t1,t1,0x1 + 3b46: 0901 addi s2,s2,0 + 3b48: 0000 unimp + 3b4a: 0501 addi a0,a0,0 + 3b4c: 0601 addi a2,a2,0 + 3b4e: 00090103 lb sp,0(s2) + 3b52: 0100 addi s0,sp,128 + 3b54: 0009 c.nop 2 + 3b56: 0000 unimp + 3b58: 0101 addi sp,sp,0 + 3b5a: 0105 addi sp,sp,1 + 3b5c: 0500 addi s0,sp,640 + 3b5e: 0002 c.slli64 zero + 3b60: 0000 unimp + 3b62: 0300 addi s0,sp,384 + 3b64: 0198 addi a4,sp,192 + 3b66: 0501 addi a0,a0,0 + 3b68: 0305 addi t1,t1,1 + 3b6a: 0901 addi s2,s2,0 + 3b6c: 0000 unimp + 3b6e: 0501 addi a0,a0,0 + 3b70: 0601 addi a2,a2,0 + 3b72: 00090103 lb sp,0(s2) + 3b76: 0100 addi s0,sp,128 + 3b78: 0009 c.nop 2 + 3b7a: 0000 unimp + 3b7c: 0101 addi sp,sp,0 + 3b7e: 0105 addi sp,sp,1 + 3b80: 0500 addi s0,sp,640 + 3b82: 0002 c.slli64 zero + 3b84: 0000 unimp + 3b86: 0300 addi s0,sp,384 + 3b88: 019d addi gp,gp,7 # 80001047 <__global_pointer$+0x7> + 3b8a: 0501 addi a0,a0,0 + 3b8c: 0305 addi t1,t1,1 + 3b8e: 0901 addi s2,s2,0 + 3b90: 0000 unimp + 3b92: 0501 addi a0,a0,0 + 3b94: 0003060b .4byte 0x3060b + 3b98: 0009 c.nop 2 + 3b9a: 0100 addi s0,sp,128 + 3b9c: 0505 addi a0,a0,1 + 3b9e: 0306 slli t1,t1,0x1 + 3ba0: 0901 addi s2,s2,0 + 3ba2: 0000 unimp + 3ba4: 0501 addi a0,a0,0 + 3ba6: 0601 addi a2,a2,0 + 3ba8: 00090103 lb sp,0(s2) + 3bac: 0100 addi s0,sp,128 + 3bae: 0009 c.nop 2 + 3bb0: 0000 unimp + 3bb2: 0101 addi sp,sp,0 + 3bb4: 0105 addi sp,sp,1 + 3bb6: 0500 addi s0,sp,640 + 3bb8: 0002 c.slli64 zero + 3bba: 0000 unimp + 3bbc: 0300 addi s0,sp,384 + 3bbe: 050101a3 sb a6,67(sp) + 3bc2: 0305 addi t1,t1,1 + 3bc4: 0901 addi s2,s2,0 + 3bc6: 0000 unimp + 3bc8: 0501 addi a0,a0,0 + 3bca: 0612 slli a2,a2,0x4 + 3bcc: 00090003 lb zero,0(s2) + 3bd0: 0100 addi s0,sp,128 + 3bd2: 0105 addi sp,sp,1 + 3bd4: 00090103 lb sp,0(s2) + 3bd8: 0100 addi s0,sp,128 + 3bda: 0009 c.nop 2 + 3bdc: 0000 unimp + 3bde: 0101 addi sp,sp,0 + 3be0: 0105 addi sp,sp,1 + 3be2: 0500 addi s0,sp,640 + 3be4: 0002 c.slli64 zero + 3be6: 0000 unimp + 3be8: 0300 addi s0,sp,384 + 3bea: 01a8 addi a0,sp,200 + 3bec: 0501 addi a0,a0,0 + 3bee: 0305 addi t1,t1,1 + 3bf0: 0901 addi s2,s2,0 + 3bf2: 0000 unimp + 3bf4: 0501 addi a0,a0,0 + 3bf6: 0003060b .4byte 0x3060b + 3bfa: 0009 c.nop 2 + 3bfc: 0100 addi s0,sp,128 + 3bfe: 0505 addi a0,a0,1 + 3c00: 0306 slli t1,t1,0x1 + 3c02: 0901 addi s2,s2,0 + 3c04: 0000 unimp + 3c06: 0501 addi a0,a0,0 + 3c08: 0601 addi a2,a2,0 + 3c0a: 00090103 lb sp,0(s2) + 3c0e: 0100 addi s0,sp,128 + 3c10: 0009 c.nop 2 + 3c12: 0000 unimp + 3c14: 0101 addi sp,sp,0 + 3c16: 0105 addi sp,sp,1 + 3c18: 0500 addi s0,sp,640 + 3c1a: 0002 c.slli64 zero + 3c1c: 0000 unimp + 3c1e: 0300 addi s0,sp,384 + 3c20: 01ae slli gp,gp,0xb + 3c22: 0501 addi a0,a0,0 + 3c24: 0305 addi t1,t1,1 + 3c26: 0901 addi s2,s2,0 + 3c28: 0000 unimp + 3c2a: 0501 addi a0,a0,0 + 3c2c: 0003060b .4byte 0x3060b + 3c30: 0009 c.nop 2 + 3c32: 0100 addi s0,sp,128 + 3c34: 0505 addi a0,a0,1 + 3c36: 0306 slli t1,t1,0x1 + 3c38: 0901 addi s2,s2,0 + 3c3a: 0000 unimp + 3c3c: 0501 addi a0,a0,0 + 3c3e: 0601 addi a2,a2,0 + 3c40: 00090103 lb sp,0(s2) + 3c44: 0100 addi s0,sp,128 + 3c46: 0009 c.nop 2 + 3c48: 0000 unimp + 3c4a: 0101 addi sp,sp,0 + 3c4c: 0105 addi sp,sp,1 + 3c4e: 0500 addi s0,sp,640 + 3c50: 0002 c.slli64 zero + 3c52: 0000 unimp + 3c54: 0300 addi s0,sp,384 + 3c56: 01b4 addi a3,sp,200 + 3c58: 0501 addi a0,a0,0 + 3c5a: 0305 addi t1,t1,1 + 3c5c: 0901 addi s2,s2,0 + 3c5e: 0000 unimp + 3c60: 0501 addi a0,a0,0 + 3c62: 0601 addi a2,a2,0 + 3c64: 00090103 lb sp,0(s2) + 3c68: 0100 addi s0,sp,128 + 3c6a: 0009 c.nop 2 + 3c6c: 0000 unimp + 3c6e: 0101 addi sp,sp,0 + 3c70: 0505 addi a0,a0,1 + 3c72: 0500 addi s0,sp,640 + 3c74: 0002 c.slli64 zero + 3c76: 0000 unimp + 3c78: 0300 addi s0,sp,384 + 3c7a: 01b8 addi a4,sp,200 + 3c7c: 0901 addi s2,s2,0 + 3c7e: 0000 unimp + 3c80: 0100 addi s0,sp,128 + 3c82: 0501 addi a0,a0,0 + 3c84: 0001 nop + 3c86: 0205 addi tp,tp,1 # 1 + 3c88: 0000 unimp + 3c8a: 0000 unimp + 3c8c: 0101bf03 .4byte 0x101bf03 + 3c90: 0505 addi a0,a0,1 + 3c92: 00090103 lb sp,0(s2) + 3c96: 0100 addi s0,sp,128 + 3c98: 0105 addi sp,sp,1 + 3c9a: 0306 slli t1,t1,0x1 + 3c9c: 0901 addi s2,s2,0 + 3c9e: 0000 unimp + 3ca0: 0901 addi s2,s2,0 + 3ca2: 0000 unimp + 3ca4: 0100 addi s0,sp,128 + 3ca6: 0501 addi a0,a0,0 + 3ca8: 0005 c.nop 1 + 3caa: 0205 addi tp,tp,1 # 1 + 3cac: 0000 unimp + 3cae: 0000 unimp + 3cb0: 0101c303 lbu t1,16(gp) # 80001050 <__global_pointer$+0x10> + 3cb4: 0009 c.nop 2 + 3cb6: 0000 unimp + 3cb8: 0101 addi sp,sp,0 + 3cba: 0105 addi sp,sp,1 + 3cbc: 0500 addi s0,sp,640 + 3cbe: 0002 c.slli64 zero + 3cc0: 0000 unimp + 3cc2: 0300 addi s0,sp,384 + 3cc4: 01ca slli gp,gp,0x12 + 3cc6: 0501 addi a0,a0,0 + 3cc8: 0305 addi t1,t1,1 + 3cca: 0901 addi s2,s2,0 + 3ccc: 0000 unimp + 3cce: 0301 addi t1,t1,0 + 3cd0: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 3cd4: 0501 addi a0,a0,0 + 3cd6: 0601 addi a2,a2,0 + 3cd8: 00097c03 .4byte 0x97c03 + 3cdc: 0100 addi s0,sp,128 + 3cde: 0905 addi s2,s2,1 + 3ce0: 00090403 lb s0,0(s2) + 3ce4: 0100 addi s0,sp,128 + 3ce6: 0805 addi a6,a6,1 + 3ce8: 00090003 lb zero,0(s2) + 3cec: 0100 addi s0,sp,128 + 3cee: 0105 addi sp,sp,1 + 3cf0: 00090b03 lb s6,0(s2) + 3cf4: 0100 addi s0,sp,128 + 3cf6: 0905 addi s2,s2,1 + 3cf8: 0306 slli t1,t1,0x1 + 3cfa: 0979 addi s2,s2,30 + 3cfc: 0000 unimp + 3cfe: 0501 addi a0,a0,0 + 3d00: 0612 slli a2,a2,0x4 + 3d02: 00090003 lb zero,0(s2) + 3d06: 0100 addi s0,sp,128 + 3d08: 1705 addi a4,a4,-31 + 3d0a: 00090003 lb zero,0(s2) + 3d0e: 0100 addi s0,sp,128 + 3d10: 1505 addi a0,a0,-31 + 3d12: 00090003 lb zero,0(s2) + 3d16: 0100 addi s0,sp,128 + 3d18: 0905 addi s2,s2,1 + 3d1a: 0306 slli t1,t1,0x1 + 3d1c: 0901 addi s2,s2,0 + 3d1e: 0000 unimp + 3d20: 0301 addi t1,t1,0 + 3d22: 0901 addi s2,s2,0 + 3d24: 0000 unimp + 3d26: 0501 addi a0,a0,0 + 3d28: 0312 slli t1,t1,0x4 + 3d2a: 097d addi s2,s2,31 + 3d2c: 0000 unimp + 3d2e: 0501 addi a0,a0,0 + 3d30: 0305 addi t1,t1,1 + 3d32: 00000907 .4byte 0x907 + 3d36: 0501 addi a0,a0,0 + 3d38: 060c addi a1,sp,768 + 3d3a: 00090003 lb zero,0(s2) + 3d3e: 0100 addi s0,sp,128 + 3d40: 0009 c.nop 2 + 3d42: 0000 unimp + 3d44: 0101 addi sp,sp,0 + 3d46: 0105 addi sp,sp,1 + 3d48: 0500 addi s0,sp,640 + 3d4a: 0002 c.slli64 zero + 3d4c: 0000 unimp + 3d4e: 0300 addi s0,sp,384 + 3d50: 01dc addi a5,sp,196 + 3d52: 0501 addi a0,a0,0 + 3d54: 0305 addi t1,t1,1 + 3d56: 0901 addi s2,s2,0 + 3d58: 0000 unimp + 3d5a: 0501 addi a0,a0,0 + 3d5c: 0611 addi a2,a2,4 + 3d5e: 00090003 lb zero,0(s2) + 3d62: 0100 addi s0,sp,128 + 3d64: 0505 addi a0,a0,1 + 3d66: 0306 slli t1,t1,0x1 + 3d68: 0901 addi s2,s2,0 + 3d6a: 0000 unimp + 3d6c: 0501 addi a0,a0,0 + 3d6e: 0601 addi a2,a2,0 + 3d70: 00090303 lb t1,0(s2) + 3d74: 0100 addi s0,sp,128 + 3d76: 0009 c.nop 2 + 3d78: 0000 unimp + 3d7a: 0101 addi sp,sp,0 + 3d7c: 0605 addi a2,a2,1 + 3d7e: 0500 addi s0,sp,640 + 3d80: 0002 c.slli64 zero + 3d82: 0000 unimp + 3d84: 0300 addi s0,sp,384 + 3d86: 090101e3 beq sp,a6,4608 <__neorv32_ram_size+0x2608> + 3d8a: 0000 unimp + 3d8c: 0100 addi s0,sp,128 + 3d8e: 0501 addi a0,a0,0 + 3d90: 0001 nop + 3d92: 0205 addi tp,tp,1 # 1 + 3d94: 0000 unimp + 3d96: 0000 unimp + 3d98: 0101ea03 .4byte 0x101ea03 + 3d9c: 0505 addi a0,a0,1 + 3d9e: 00090103 lb sp,0(s2) + 3da2: 0100 addi s0,sp,128 + 3da4: 0105 addi sp,sp,1 + 3da6: 0306 slli t1,t1,0x1 + 3da8: 0901 addi s2,s2,0 + 3daa: 0000 unimp + 3dac: 0901 addi s2,s2,0 + 3dae: 0000 unimp + 3db0: 0100 addi s0,sp,128 + 3db2: 0501 addi a0,a0,0 + 3db4: 0001 nop + 3db6: 0205 addi tp,tp,1 # 1 + 3db8: 0000 unimp + 3dba: 0000 unimp + 3dbc: 0101ef03 .4byte 0x101ef03 + 3dc0: 0505 addi a0,a0,1 + 3dc2: 00090103 lb sp,0(s2) + 3dc6: 0100 addi s0,sp,128 + 3dc8: 0b05 addi s6,s6,1 + 3dca: 0306 slli t1,t1,0x1 + 3dcc: 0900 addi s0,sp,144 + 3dce: 0000 unimp + 3dd0: 0501 addi a0,a0,0 + 3dd2: 0605 addi a2,a2,1 + 3dd4: 00090103 lb sp,0(s2) + 3dd8: 0100 addi s0,sp,128 + 3dda: 0105 addi sp,sp,1 + 3ddc: 0306 slli t1,t1,0x1 + 3dde: 0901 addi s2,s2,0 + 3de0: 0000 unimp + 3de2: 0901 addi s2,s2,0 + 3de4: 0000 unimp + 3de6: 0100 addi s0,sp,128 + 3de8: 0501 addi a0,a0,0 + 3dea: 0005 c.nop 1 + 3dec: 0205 addi tp,tp,1 # 1 + 3dee: 0000 unimp + 3df0: 0000 unimp + 3df2: 0101f403 .4byte 0x101f403 + 3df6: 0009 c.nop 2 + 3df8: 0000 unimp + 3dfa: 0101 addi sp,sp,0 + 3dfc: 0105 addi sp,sp,1 + 3dfe: 0500 addi s0,sp,640 + 3e00: 0002 c.slli64 zero + 3e02: 0000 unimp + 3e04: 0300 addi s0,sp,384 + 3e06: 050101fb .4byte 0x50101fb + 3e0a: 0305 addi t1,t1,1 + 3e0c: 0901 addi s2,s2,0 + 3e0e: 0000 unimp + 3e10: 0501 addi a0,a0,0 + 3e12: 0003060b .4byte 0x3060b + 3e16: 0009 c.nop 2 + 3e18: 0100 addi s0,sp,128 + 3e1a: 0505 addi a0,a0,1 + 3e1c: 0306 slli t1,t1,0x1 + 3e1e: 0901 addi s2,s2,0 + 3e20: 0000 unimp + 3e22: 0501 addi a0,a0,0 + 3e24: 0601 addi a2,a2,0 + 3e26: 00090103 lb sp,0(s2) + 3e2a: 0100 addi s0,sp,128 + 3e2c: 0009 c.nop 2 + 3e2e: 0000 unimp + 3e30: 0101 addi sp,sp,0 + 3e32: 0105 addi sp,sp,1 + 3e34: 0500 addi s0,sp,640 + 3e36: 0002 c.slli64 zero + 3e38: 0000 unimp + 3e3a: 0300 addi s0,sp,384 + 3e3c: 0281 addi t0,t0,0 # 0 <__crt0_entry> + 3e3e: 0501 addi a0,a0,0 + 3e40: 0305 addi t1,t1,1 + 3e42: 0902 c.slli64 s2 + 3e44: 0000 unimp + 3e46: 0501 addi a0,a0,0 + 3e48: 0601 addi a2,a2,0 + 3e4a: 00097e03 .4byte 0x97e03 + 3e4e: 0100 addi s0,sp,128 + 3e50: 0505 addi a0,a0,1 + 3e52: 0306 slli t1,t1,0x1 + 3e54: 00000903 lb s2,0(zero) # 0 <__crt0_entry> + 3e58: 0501 addi a0,a0,0 + 3e5a: 0601 addi a2,a2,0 + 3e5c: 00097d03 .4byte 0x97d03 + 3e60: 0100 addi s0,sp,128 + 3e62: 0905 addi s2,s2,1 + 3e64: 00090303 lb t1,0(s2) + 3e68: 0100 addi s0,sp,128 + 3e6a: 1105 addi sp,sp,-31 + 3e6c: 00097f03 .4byte 0x97f03 + 3e70: 0100 addi s0,sp,128 + 3e72: 0805 addi a6,a6,1 + 3e74: 00090103 lb sp,0(s2) + 3e78: 0100 addi s0,sp,128 + 3e7a: 0105 addi sp,sp,1 + 3e7c: 00090903 lb s2,0(s2) + 3e80: 0100 addi s0,sp,128 + 3e82: 0905 addi s2,s2,1 + 3e84: 0306 slli t1,t1,0x1 + 3e86: 0979 addi s2,s2,30 + 3e88: 0000 unimp + 3e8a: 0501 addi a0,a0,0 + 3e8c: 061d addi a2,a2,7 + 3e8e: 00090003 lb zero,0(s2) + 3e92: 0100 addi s0,sp,128 + 3e94: 0905 addi s2,s2,1 + 3e96: 00090003 lb zero,0(s2) + 3e9a: 0100 addi s0,sp,128 + 3e9c: 1205 addi tp,tp,-31 # ffffffe1 <__crt0_stack_begin+0x7fffdfe5> + 3e9e: 0306 slli t1,t1,0x1 + 3ea0: 097f .2byte 0x97f + 3ea2: 0000 unimp + 3ea4: 0501 addi a0,a0,0 + 3ea6: 09030307 .4byte 0x9030307 + 3eaa: 0000 unimp + 3eac: 0501 addi a0,a0,0 + 3eae: 060e slli a2,a2,0x3 + 3eb0: 00090003 lb zero,0(s2) + 3eb4: 0100 addi s0,sp,128 + 3eb6: 0009 c.nop 2 + 3eb8: 0000 unimp + 3eba: 0101 addi sp,sp,0 + 3ebc: 0105 addi sp,sp,1 + 3ebe: 0500 addi s0,sp,640 + 3ec0: 0002 c.slli64 zero + 3ec2: 0000 unimp + 3ec4: 0300 addi s0,sp,384 + 3ec6: 0294 addi a3,sp,320 + 3ec8: 0501 addi a0,a0,0 + 3eca: 0305 addi t1,t1,1 + 3ecc: 0901 addi s2,s2,0 + 3ece: 0000 unimp + 3ed0: 0501 addi a0,a0,0 + 3ed2: 0609 addi a2,a2,2 + 3ed4: 00090003 lb zero,0(s2) + 3ed8: 0100 addi s0,sp,128 + 3eda: 0505 addi a0,a0,1 + 3edc: 0306 slli t1,t1,0x1 + 3ede: 0901 addi s2,s2,0 + 3ee0: 0000 unimp + 3ee2: 0501 addi a0,a0,0 + 3ee4: 0601 addi a2,a2,0 + 3ee6: 00090103 lb sp,0(s2) + 3eea: 0100 addi s0,sp,128 + 3eec: 0009 c.nop 2 + 3eee: 0000 unimp + 3ef0: 0101 addi sp,sp,0 + 3ef2: 0105 addi sp,sp,1 + 3ef4: 0500 addi s0,sp,640 + 3ef6: 9c02 jalr s8 + 3ef8: 000d c.nop 3 + 3efa: 0300 addi s0,sp,384 + 3efc: 029a slli t0,t0,0x6 + 3efe: 0501 addi a0,a0,0 + 3f00: 0305 addi t1,t1,1 + 3f02: 0901 addi s2,s2,0 + 3f04: 0000 unimp + 3f06: 0501 addi a0,a0,0 + 3f08: 0608 addi a0,sp,768 + 3f0a: 00090203 lb tp,0(s2) + 3f0e: 0100 addi s0,sp,128 + 3f10: 0b05 addi s6,s6,1 + 3f12: 00097e03 .4byte 0x97e03 + 3f16: 0100 addi s0,sp,128 + 3f18: 0805 addi a6,a6,1 + 3f1a: 04090203 lb tp,64(s2) + 3f1e: 0100 addi s0,sp,128 + 3f20: 0105 addi sp,sp,1 + 3f22: 08097d03 .4byte 0x8097d03 + 3f26: 0100 addi s0,sp,128 + 3f28: 0b05 addi s6,s6,1 + 3f2a: 04090103 lb sp,64(s2) + 3f2e: 0100 addi s0,sp,128 + 3f30: 0505 addi a0,a0,1 + 3f32: 0306 slli t1,t1,0x1 + 3f34: 0902 c.slli64 s2 + 3f36: 0004 .2byte 0x4 + 3f38: 0501 addi a0,a0,0 + 3f3a: 0608 addi a0,sp,768 + 3f3c: 00090003 lb zero,0(s2) + 3f40: 0100 addi s0,sp,128 + 3f42: 0505 addi a0,a0,1 + 3f44: 0306 slli t1,t1,0x1 + 3f46: 0904 addi s1,sp,144 + 3f48: 0004 .2byte 0x4 + 3f4a: 0501 addi a0,a0,0 + 3f4c: 060e slli a2,a2,0x3 + 3f4e: 00090003 lb zero,0(s2) + 3f52: 0100 addi s0,sp,128 + 3f54: 0805 addi a6,a6,1 + 3f56: 08090003 lb zero,128(s2) + 3f5a: 0100 addi s0,sp,128 + 3f5c: 0905 addi s2,s2,1 + 3f5e: 0306 slli t1,t1,0x1 + 3f60: 0901 addi s2,s2,0 + 3f62: 0004 .2byte 0x4 + 3f64: 0501 addi a0,a0,0 + 3f66: 060d addi a2,a2,3 + 3f68: 00090003 lb zero,0(s2) + 3f6c: 0100 addi s0,sp,128 + 3f6e: 1005 c.nop -31 + 3f70: 0c097c03 .4byte 0xc097c03 + 3f74: 0100 addi s0,sp,128 + 3f76: 0105 addi sp,sp,1 + 3f78: 04090903 lb s2,64(s2) + 3f7c: 0100 addi s0,sp,128 + 3f7e: 0409 addi s0,s0,2 + 3f80: 0000 unimp + 3f82: 0101 addi sp,sp,0 + 3f84: 0246 slli tp,tp,0x11 + 3f86: 0000 unimp + 3f88: 0005 c.nop 1 + 3f8a: 0004 .2byte 0x4 + 3f8c: 002a c.slli zero,0xa + 3f8e: 0000 unimp + 3f90: 0101 addi sp,sp,0 + 3f92: fb01 bnez a4,3ea2 <__neorv32_ram_size+0x1ea2> + 3f94: 0d0e slli s10,s10,0x3 + 3f96: 0100 addi s0,sp,128 + 3f98: 0101 addi sp,sp,0 + 3f9a: 0001 nop + 3f9c: 0000 unimp + 3f9e: 0001 nop + 3fa0: 0100 addi s0,sp,128 + 3fa2: 0101 addi sp,sp,0 + 3fa4: 011f 0198 0000 .byte 0x1f, 0x01, 0x98, 0x01, 0x00, 0x00 + 3faa: 0102 c.slli64 sp + 3fac: 021f 020f 02d8 .byte 0x1f, 0x02, 0x0f, 0x02, 0xd8, 0x02 + 3fb2: 0000 unimp + 3fb4: d800 sw s0,48(s0) + 3fb6: 0002 c.slli64 zero + 3fb8: 0000 unimp + 3fba: 0500 addi s0,sp,640 + 3fbc: 0002 c.slli64 zero + 3fbe: 0000 unimp + 3fc0: 0300 addi s0,sp,384 + 3fc2: 0134 addi a3,sp,136 + 3fc4: 04090703 lb a4,64(s2) + 3fc8: 0100 addi s0,sp,128 + 3fca: 04090103 lb sp,64(s2) + 3fce: 0100 addi s0,sp,128 + 3fd0: 08090103 lb sp,128(s2) + 3fd4: 0100 addi s0,sp,128 + 3fd6: 04090a03 lb s4,64(s2) + 3fda: 0100 addi s0,sp,128 + 3fdc: 08090103 lb sp,128(s2) + 3fe0: 0100 addi s0,sp,128 + 3fe2: 08090803 lb a6,128(s2) + 3fe6: 0100 addi s0,sp,128 + 3fe8: 04090103 lb sp,64(s2) + 3fec: 0100 addi s0,sp,128 + 3fee: 04090103 lb sp,64(s2) + 3ff2: 0100 addi s0,sp,128 + 3ff4: 04090103 lb sp,64(s2) + 3ff8: 0100 addi s0,sp,128 + 3ffa: 04090103 lb sp,64(s2) + 3ffe: 0100 addi s0,sp,128 + 4000: 04090103 lb sp,64(s2) + 4004: 0100 addi s0,sp,128 + 4006: 04090803 lb a6,64(s2) + 400a: 0100 addi s0,sp,128 + 400c: 04090103 lb sp,64(s2) + 4010: 0100 addi s0,sp,128 + 4012: 04090103 lb sp,64(s2) + 4016: 0100 addi s0,sp,128 + 4018: 04090103 lb sp,64(s2) + 401c: 0100 addi s0,sp,128 + 401e: 04090103 lb sp,64(s2) + 4022: 0100 addi s0,sp,128 + 4024: 04090103 lb sp,64(s2) + 4028: 0100 addi s0,sp,128 + 402a: 04090103 lb sp,64(s2) + 402e: 0100 addi s0,sp,128 + 4030: 04090103 lb sp,64(s2) + 4034: 0100 addi s0,sp,128 + 4036: 04090103 lb sp,64(s2) + 403a: 0100 addi s0,sp,128 + 403c: 04090103 lb sp,64(s2) + 4040: 0100 addi s0,sp,128 + 4042: 04090103 lb sp,64(s2) + 4046: 0100 addi s0,sp,128 + 4048: 04090103 lb sp,64(s2) + 404c: 0100 addi s0,sp,128 + 404e: 04090103 lb sp,64(s2) + 4052: 0100 addi s0,sp,128 + 4054: 04090103 lb sp,64(s2) + 4058: 0100 addi s0,sp,128 + 405a: 04090103 lb sp,64(s2) + 405e: 0100 addi s0,sp,128 + 4060: 04090103 lb sp,64(s2) + 4064: 0100 addi s0,sp,128 + 4066: 04090803 lb a6,64(s2) + 406a: 0100 addi s0,sp,128 + 406c: 08090103 lb sp,128(s2) + 4070: 0100 addi s0,sp,128 + 4072: 08090103 lb sp,128(s2) + 4076: 0100 addi s0,sp,128 + 4078: 08090103 lb sp,128(s2) + 407c: 0100 addi s0,sp,128 + 407e: 04090303 lb t1,64(s2) + 4082: 0100 addi s0,sp,128 + 4084: 04090103 lb sp,64(s2) + 4088: 0100 addi s0,sp,128 + 408a: 04090103 lb sp,64(s2) + 408e: 0100 addi s0,sp,128 + 4090: 04090103 lb sp,64(s2) + 4094: 0100 addi s0,sp,128 + 4096: 04090103 lb sp,64(s2) + 409a: 0100 addi s0,sp,128 + 409c: 04090103 lb sp,64(s2) + 40a0: 0100 addi s0,sp,128 + 40a2: 04090903 lb s2,64(s2) + 40a6: 0100 addi s0,sp,128 + 40a8: 08090103 lb sp,128(s2) + 40ac: 0100 addi s0,sp,128 + 40ae: 04090303 lb t1,64(s2) + 40b2: 0100 addi s0,sp,128 + 40b4: 04090103 lb sp,64(s2) + 40b8: 0100 addi s0,sp,128 + 40ba: 04090103 lb sp,64(s2) + 40be: 0100 addi s0,sp,128 + 40c0: 04090103 lb sp,64(s2) + 40c4: 0100 addi s0,sp,128 + 40c6: 04090a03 lb s4,64(s2) + 40ca: 0100 addi s0,sp,128 + 40cc: 08090103 lb sp,128(s2) + 40d0: 0100 addi s0,sp,128 + 40d2: 08090303 lb t1,128(s2) + 40d6: 0100 addi s0,sp,128 + 40d8: 04090103 lb sp,64(s2) + 40dc: 0100 addi s0,sp,128 + 40de: 04090103 lb sp,64(s2) + 40e2: 0100 addi s0,sp,128 + 40e4: 04090103 lb sp,64(s2) + 40e8: 0100 addi s0,sp,128 + 40ea: 04090103 lb sp,64(s2) + 40ee: 0100 addi s0,sp,128 + 40f0: 04090a03 lb s4,64(s2) + 40f4: 0100 addi s0,sp,128 + 40f6: 04090103 lb sp,64(s2) + 40fa: 0100 addi s0,sp,128 + 40fc: 04090103 lb sp,64(s2) + 4100: 0100 addi s0,sp,128 + 4102: 04090303 lb t1,64(s2) + 4106: 0100 addi s0,sp,128 + 4108: 04090103 lb sp,64(s2) + 410c: 0100 addi s0,sp,128 + 410e: 04090803 lb a6,64(s2) + 4112: 0100 addi s0,sp,128 + 4114: 08090103 lb sp,128(s2) + 4118: 0100 addi s0,sp,128 + 411a: 08090303 lb t1,128(s2) + 411e: 0100 addi s0,sp,128 + 4120: 04090103 lb sp,64(s2) + 4124: 0100 addi s0,sp,128 + 4126: 04090103 lb sp,64(s2) + 412a: 0100 addi s0,sp,128 + 412c: 04090103 lb sp,64(s2) + 4130: 0100 addi s0,sp,128 + 4132: 04090103 lb sp,64(s2) + 4136: 0100 addi s0,sp,128 + 4138: 04090c03 lb s8,64(s2) + 413c: 0100 addi s0,sp,128 + 413e: 04090103 lb sp,64(s2) + 4142: 0100 addi s0,sp,128 + 4144: 04090103 lb sp,64(s2) + 4148: 0100 addi s0,sp,128 + 414a: 04090a03 lb s4,64(s2) + 414e: 0100 addi s0,sp,128 + 4150: 04090103 lb sp,64(s2) + 4154: 0100 addi s0,sp,128 + 4156: 04090a03 lb s4,64(s2) + 415a: 0100 addi s0,sp,128 + 415c: 04090103 lb sp,64(s2) + 4160: 0100 addi s0,sp,128 + 4162: 04090103 lb sp,64(s2) + 4166: 0100 addi s0,sp,128 + 4168: 04090203 lb tp,64(s2) + 416c: 0100 addi s0,sp,128 + 416e: 04090103 lb sp,64(s2) + 4172: 0100 addi s0,sp,128 + 4174: 04090303 lb t1,64(s2) + 4178: 0100 addi s0,sp,128 + 417a: 04090103 lb sp,64(s2) + 417e: 0100 addi s0,sp,128 + 4180: 04090103 lb sp,64(s2) + 4184: 0100 addi s0,sp,128 + 4186: 04090203 lb tp,64(s2) + 418a: 0100 addi s0,sp,128 + 418c: 04090103 lb sp,64(s2) + 4190: 0100 addi s0,sp,128 + 4192: 04090203 lb tp,64(s2) + 4196: 0100 addi s0,sp,128 + 4198: 04090103 lb sp,64(s2) + 419c: 0100 addi s0,sp,128 + 419e: 04090203 lb tp,64(s2) + 41a2: 0100 addi s0,sp,128 + 41a4: 04090103 lb sp,64(s2) + 41a8: 0100 addi s0,sp,128 + 41aa: 04090103 lb sp,64(s2) + 41ae: 0100 addi s0,sp,128 + 41b0: 04090303 lb t1,64(s2) + 41b4: 0100 addi s0,sp,128 + 41b6: 04090103 lb sp,64(s2) + 41ba: 0100 addi s0,sp,128 + 41bc: 04090103 lb sp,64(s2) + 41c0: 0100 addi s0,sp,128 + 41c2: 04090203 lb tp,64(s2) + 41c6: 0100 addi s0,sp,128 + 41c8: 0409 addi s0,s0,2 + 41ca: 0000 unimp + 41cc: 0101 addi sp,sp,0 + 41ce: 0000014f .4byte 0x14f + 41d2: 0005 c.nop 1 + 41d4: 0004 .2byte 0x4 + 41d6: 002e c.slli zero,0xb + 41d8: 0000 unimp + 41da: 0101 addi sp,sp,0 + 41dc: fb01 bnez a4,40ec <__neorv32_ram_size+0x20ec> + 41de: 0d0e slli s10,s10,0x3 + 41e0: 0100 addi s0,sp,128 + 41e2: 0101 addi sp,sp,0 + 41e4: 0001 nop + 41e6: 0000 unimp + 41e8: 0001 nop + 41ea: 0100 addi s0,sp,128 + 41ec: 0101 addi sp,sp,0 + 41ee: 021f 02df 0000 .byte 0x1f, 0x02, 0xdf, 0x02, 0x00, 0x00 + 41f4: 0331 addi t1,t1,12 + 41f6: 0000 unimp + 41f8: 0102 c.slli64 sp + 41fa: 021f 020f 0368 .byte 0x1f, 0x02, 0x0f, 0x02, 0x68, 0x03 + 4200: 0000 unimp + 4202: 6801 .2byte 0x6801 + 4204: 01000003 lb zero,16(zero) # 10 + 4208: 0500 addi s0,sp,640 + 420a: d402 sw zero,40(sp) + 420c: 000d c.nop 3 + 420e: 0300 addi s0,sp,384 + 4210: 00c4 addi s1,sp,68 + 4212: 0301 addi t1,t1,0 + 4214: 0901 addi s2,s2,0 + 4216: 0004 .2byte 0x4 + 4218: 0301 addi t1,t1,0 + 421a: 0904 addi s1,sp,144 + 421c: 0004 .2byte 0x4 + 421e: 0301 addi t1,t1,0 + 4220: 0901 addi s2,s2,0 + 4222: 0002 c.slli64 zero + 4224: 0301 addi t1,t1,0 + 4226: 0901 addi s2,s2,0 + 4228: 0002 c.slli64 zero + 422a: 0301 addi t1,t1,0 + 422c: 0901 addi s2,s2,0 + 422e: 0002 c.slli64 zero + 4230: 0301 addi t1,t1,0 + 4232: 0901 addi s2,s2,0 + 4234: 0002 c.slli64 zero + 4236: 0301 addi t1,t1,0 + 4238: 0901 addi s2,s2,0 + 423a: 0002 c.slli64 zero + 423c: 0301 addi t1,t1,0 + 423e: 0902 c.slli64 s2 + 4240: 0004 .2byte 0x4 + 4242: 0301 addi t1,t1,0 + 4244: 0901 addi s2,s2,0 + 4246: 0004 .2byte 0x4 + 4248: 0301 addi t1,t1,0 + 424a: 0901 addi s2,s2,0 + 424c: 0002 c.slli64 zero + 424e: 0301 addi t1,t1,0 + 4250: 0901 addi s2,s2,0 + 4252: 0002 c.slli64 zero + 4254: 0301 addi t1,t1,0 + 4256: 0902 c.slli64 s2 + 4258: 0004 .2byte 0x4 + 425a: 0301 addi t1,t1,0 + 425c: 0902 c.slli64 s2 + 425e: 0002 c.slli64 zero + 4260: 0301 addi t1,t1,0 + 4262: 0901 addi s2,s2,0 + 4264: 0004 .2byte 0x4 + 4266: 0301 addi t1,t1,0 + 4268: 0901 addi s2,s2,0 + 426a: 0002 c.slli64 zero + 426c: 0301 addi t1,t1,0 + 426e: 0902 c.slli64 s2 + 4270: 0002 c.slli64 zero + 4272: 0301 addi t1,t1,0 + 4274: 0901 addi s2,s2,0 + 4276: 0002 c.slli64 zero + 4278: 0301 addi t1,t1,0 + 427a: 0901 addi s2,s2,0 + 427c: 0002 c.slli64 zero + 427e: 0301 addi t1,t1,0 + 4280: 0902 c.slli64 s2 + 4282: 0002 c.slli64 zero + 4284: 0301 addi t1,t1,0 + 4286: 0906 slli s2,s2,0x1 + 4288: 0002 c.slli64 zero + 428a: 0301 addi t1,t1,0 + 428c: 0901 addi s2,s2,0 + 428e: 0002 c.slli64 zero + 4290: 0301 addi t1,t1,0 + 4292: 0901 addi s2,s2,0 + 4294: 0002 c.slli64 zero + 4296: 0301 addi t1,t1,0 + 4298: 0901 addi s2,s2,0 + 429a: 0002 c.slli64 zero + 429c: 0301 addi t1,t1,0 + 429e: 0905 addi s2,s2,1 + 42a0: 0002 c.slli64 zero + 42a2: 0301 addi t1,t1,0 + 42a4: 0902 c.slli64 s2 + 42a6: 0004 .2byte 0x4 + 42a8: 0301 addi t1,t1,0 + 42aa: 0902 c.slli64 s2 + 42ac: 0004 .2byte 0x4 + 42ae: 0301 addi t1,t1,0 + 42b0: 0901 addi s2,s2,0 + 42b2: 0004 .2byte 0x4 + 42b4: 0301 addi t1,t1,0 + 42b6: 0902 c.slli64 s2 + 42b8: 0002 c.slli64 zero + 42ba: 0301 addi t1,t1,0 + 42bc: 0902 c.slli64 s2 + 42be: 0004 .2byte 0x4 + 42c0: 0301 addi t1,t1,0 + 42c2: 0901 addi s2,s2,0 + 42c4: 0002 c.slli64 zero + 42c6: 0301 addi t1,t1,0 + 42c8: 0901 addi s2,s2,0 + 42ca: 0002 c.slli64 zero + 42cc: 0301 addi t1,t1,0 + 42ce: 0901 addi s2,s2,0 + 42d0: 0004 .2byte 0x4 + 42d2: 0301 addi t1,t1,0 + 42d4: 0904 addi s1,sp,144 + 42d6: 0002 c.slli64 zero + 42d8: 0301 addi t1,t1,0 + 42da: 0901 addi s2,s2,0 + 42dc: 0002 c.slli64 zero + 42de: 0301 addi t1,t1,0 + 42e0: 0901 addi s2,s2,0 + 42e2: 0004 .2byte 0x4 + 42e4: 0301 addi t1,t1,0 + 42e6: 0902 c.slli64 s2 + 42e8: 0004 .2byte 0x4 + 42ea: 0301 addi t1,t1,0 + 42ec: 0901 addi s2,s2,0 + 42ee: 0002 c.slli64 zero + 42f0: 0301 addi t1,t1,0 + 42f2: 0901 addi s2,s2,0 + 42f4: 0002 c.slli64 zero + 42f6: 0301 addi t1,t1,0 + 42f8: 0902 c.slli64 s2 + 42fa: 0002 c.slli64 zero + 42fc: 0301 addi t1,t1,0 + 42fe: 0901 addi s2,s2,0 + 4300: 0004 .2byte 0x4 + 4302: 0301 addi t1,t1,0 + 4304: 0902 c.slli64 s2 + 4306: 0004 .2byte 0x4 + 4308: 0301 addi t1,t1,0 + 430a: 0901 addi s2,s2,0 + 430c: 0004 .2byte 0x4 + 430e: 0301 addi t1,t1,0 + 4310: 0901 addi s2,s2,0 + 4312: 0002 c.slli64 zero + 4314: 0301 addi t1,t1,0 + 4316: 0901 addi s2,s2,0 + 4318: 0004 .2byte 0x4 + 431a: 0901 addi s2,s2,0 + 431c: 0002 c.slli64 zero + 431e: 0100 addi s0,sp,128 + 4320: 01 Address 0x0000000000004320 is out of bounds. + + +Disassembly of section .debug_frame: + +00000000 <.debug_frame>: + 0: 000c .2byte 0xc + 2: 0000 unimp + 4: ffff .2byte 0xffff + 6: ffff .2byte 0xffff + 8: 7c010003 lb zero,1984(sp) + c: 0d01 addi s10,s10,0 + e: 0002 c.slli64 zero + 10: 000c .2byte 0xc + 12: 0000 unimp + 14: 0000 unimp + 16: 0000 unimp + 18: 0278 addi a4,sp,268 + 1a: 0000 unimp + 1c: 0020 addi s0,sp,8 + 1e: 0000 unimp + 20: 0030 addi a2,sp,8 + 22: 0000 unimp + 24: 0000 unimp + 26: 0000 unimp + 28: 0188 addi a0,sp,192 + 2a: 0000 unimp + 2c: 00f0 addi a2,sp,76 + 2e: 0000 unimp + 30: 0e44 addi s1,sp,788 + 32: 5c20 lw s0,120(s0) + 34: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 36: 0288 addi a0,sp,320 + 38: 0492 slli s1,s1,0x4 + 3a: 0694 addi a3,sp,832 + 3c: 0795 addi a5,a5,5 + 3e: 0389 addi t2,t2,2 + 40: ac020593 addi a1,tp,-1344 # fffffac0 <__crt0_stack_begin+0x7fffdac4> + 44: 44c1 li s1,16 + 46: 44c8 lw a0,12(s1) + 48: 44c9 li s1,18 + 4a: 44d2 lw s1,20(sp) + 4c: 44d444d3 .4byte 0x44d444d3 + 50: 48d5 li a7,21 + 52: 000e c.slli zero,0x3 + 54: 000c .2byte 0xc + 56: 0000 unimp + 58: ffff .2byte 0xffff + 5a: ffff .2byte 0xffff + 5c: 7c010003 lb zero,1984(sp) + 60: 0d01 addi s10,s10,0 + 62: 0002 c.slli64 zero + 64: 000c .2byte 0xc + 66: 0000 unimp + 68: 0054 addi a3,sp,4 + ... + 72: 0000 unimp + 74: 000c .2byte 0xc + 76: 0000 unimp + 78: 0054 addi a3,sp,4 + ... + 82: 0000 unimp + 84: 000c .2byte 0xc + 86: 0000 unimp + 88: 0054 addi a3,sp,4 + 8a: 0000 unimp + 8c: 0298 addi a4,sp,320 + 8e: 0000 unimp + 90: 0014 .2byte 0x14 + 92: 0000 unimp + 94: 000c .2byte 0xc + 96: 0000 unimp + 98: 0054 addi a3,sp,4 + ... + a2: 0000 unimp + a4: 000c .2byte 0xc + a6: 0000 unimp + a8: 0054 addi a3,sp,4 + ... + b2: 0000 unimp + b4: 000c .2byte 0xc + b6: 0000 unimp + b8: ffff .2byte 0xffff + ba: ffff .2byte 0xffff + bc: 7c010003 lb zero,1984(sp) + c0: 0d01 addi s10,s10,0 + c2: 0002 c.slli64 zero + c4: 0060 addi s0,sp,12 + c6: 0000 unimp + c8: 00b4 addi a3,sp,72 + ca: 0000 unimp + cc: 02ac addi a1,sp,328 + ce: 0000 unimp + d0: 0248 addi a0,sp,260 + d2: 0000 unimp + d4: 0e44 addi s1,sp,788 + d6: 0250 addi a2,sp,260 + d8: 8144 .2byte 0x8144 + da: 8501 c.srai64 a0 + dc: 8602 jr a2 + de: 88048703 lb a4,-1920(s1) + e2: 8a05 andi a2,a2,1 + e4: 8b06 mv s6,ra + e6: 8d088c07 .4byte 0x8d088c07 + ea: 8e09 sub a2,a2,a0 + ec: 8f0a mv t5,sp + ee: 910c900b .4byte 0x910c900b + f2: 9c0d .2byte 0x9c0d + f4: 9d0e add s10,s10,gp + f6: 9f109e0f .4byte 0x9f109e0f + fa: 0311 addi t1,t1,4 + fc: 011c addi a5,sp,128 + fe: c80a sw sp,16(sp) + 100: c144 sw s1,4(a0) + 102: c544 sw s1,12(a0) + 104: c644 sw s1,12(a2) + 106: c744 sw s1,12(a4) + 108: ca44 sw s1,20(a2) + 10a: cb44 sw s1,20(a4) + 10c: cc44 sw s1,28(s0) + 10e: cd44 sw s1,28(a0) + 110: ce44 sw s1,28(a2) + 112: cf44 sw s1,28(a4) + 114: d044 sw s1,36(s0) + 116: d144 sw s1,36(a0) + 118: dc44 sw s1,60(s0) + 11a: dd44 sw s1,60(a0) + 11c: de44 sw s1,60(a2) + 11e: df44 sw s1,60(a4) + 120: 0e44 addi s1,sp,788 + 122: 4400 lw s0,8(s0) + 124: 0000000b .4byte 0xb + 128: 002c addi a1,sp,8 + 12a: 0000 unimp + 12c: 00b4 addi a3,sp,72 + 12e: 0000 unimp + 130: 04f4 addi a3,sp,588 + 132: 0000 unimp + 134: 0070 addi a2,sp,12 + 136: 0000 unimp + 138: 0e44 addi s1,sp,788 + 13a: 4420 lw s0,72(s0) + 13c: 0492 slli s1,s1,0x4 + 13e: 8950 .2byte 0x8950 + 140: 02885003 lhu zero,40(a6) + 144: 01810593 addi a1,sp,24 + 148: c170 sw a2,68(a0) + 14a: c844 sw s1,20(s0) + 14c: c944 sw s1,20(a0) + 14e: d244 sw s1,36(a2) + 150: d344 sw s1,36(a4) + 152: 0e44 addi s1,sp,788 + 154: 0000 unimp + 156: 0000 unimp + 158: 001c .2byte 0x1c + 15a: 0000 unimp + 15c: 00b4 addi a3,sp,72 + ... + 166: 0000 unimp + 168: 0e44 addi s1,sp,788 + 16a: 4410 lw a2,8(s0) + 16c: 0288 addi a0,sp,320 + 16e: 814c .2byte 0x814c + 170: 4001 c.li zero,0 + 172: 44c8 lw a0,12(s1) + 174: 48c1 li a7,16 + 176: 000e c.slli zero,0x3 + 178: 000c .2byte 0xc + 17a: 0000 unimp + 17c: 00b4 addi a3,sp,72 + ... + 186: 0000 unimp + 188: 003c addi a5,sp,8 + 18a: 0000 unimp + 18c: 00b4 addi a3,sp,72 + 18e: 0000 unimp + 190: 0564 addi s1,sp,652 + 192: 0000 unimp + 194: 02d8 addi a4,sp,324 + 196: 0000 unimp + 198: 0e44 addi s1,sp,788 + 19a: 5420 lw s0,104(s0) + 19c: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 19e: 0288 addi a0,sp,320 + 1a0: 0389 addi t2,t2,2 + 1a2: 0492 slli s1,s1,0x4 + 1a4: d4030593 addi a1,t1,-704 + 1a8: 0a01 addi s4,s4,0 + 1aa: 44c8 lw a0,12(s1) + 1ac: 44c1 li s1,16 + 1ae: 44c9 li s1,18 + 1b0: 44d2 lw s1,20(sp) + 1b2: 000e4cd3 .4byte 0xe4cd3 + 1b6: 0b44 addi s1,sp,404 + 1b8: b402 .2byte 0xb402 + 1ba: 44c1 li s1,16 + 1bc: 44c8 lw a0,12(s1) + 1be: 44c9 li s1,18 + 1c0: 44d2 lw s1,20(sp) + 1c2: 000e44d3 .4byte 0xe44d3 + 1c6: 0000 unimp + 1c8: 000c .2byte 0xc + 1ca: 0000 unimp + 1cc: 00b4 addi a3,sp,72 + ... + 1d6: 0000 unimp + 1d8: 000c .2byte 0xc + 1da: 0000 unimp + 1dc: 00b4 addi a3,sp,72 + 1de: 0000 unimp + 1e0: 083c addi a5,sp,24 + 1e2: 0000 unimp + 1e4: 0030 addi a2,sp,8 + 1e6: 0000 unimp + 1e8: 0020 addi s0,sp,8 + 1ea: 0000 unimp + 1ec: 00b4 addi a3,sp,72 + 1ee: 0000 unimp + 1f0: 086c addi a1,sp,28 + 1f2: 0000 unimp + 1f4: 0058 addi a4,sp,4 + 1f6: 0000 unimp + 1f8: 0e44 addi s1,sp,788 + 1fa: 4c10 lw a2,24(s0) + 1fc: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 1fe: 0288 addi a0,sp,320 + 200: 0389 addi t2,t2,2 + 202: c178 sw a4,68(a0) + 204: c844 sw s1,20(s0) + 206: c944 sw s1,20(a0) + 208: 0e44 addi s1,sp,788 + 20a: 0000 unimp + 20c: 0028 addi a0,sp,8 + 20e: 0000 unimp + 210: 00b4 addi a3,sp,72 + ... + 21a: 0000 unimp + 21c: 0e44 addi s1,sp,788 + 21e: 5420 lw s0,104(s0) + 220: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 222: 0288 addi a0,sp,320 + 224: 0389 addi t2,t2,2 + 226: 0492 slli s1,s1,0x4 + 228: 00020593 mv a1,tp + 22c: 44c1 li s1,16 + 22e: 44c8 lw a0,12(s1) + 230: 44c9 li s1,18 + 232: 44d2 lw s1,20(sp) + 234: 000e44d3 .4byte 0xe44d3 + 238: 003c addi a5,sp,8 + 23a: 0000 unimp + 23c: 00b4 addi a3,sp,72 + ... + 246: 0000 unimp + 248: 0e44 addi s1,sp,788 + 24a: 5430 lw a2,104(s0) + 24c: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 24e: 0288 addi a0,sp,320 + 250: 0389 addi t2,t2,2 + 252: 0492 slli s1,s1,0x4 + 254: 00030593 mv a1,t1 + 258: 0a00 addi s0,sp,272 + 25a: 44c8 lw a0,12(s1) + 25c: 44c1 li s1,16 + 25e: 44c9 li s1,18 + 260: 44d2 lw s1,20(sp) + 262: 000e40d3 .4byte 0xe40d3 + 266: 0b40 addi s0,sp,404 + 268: 0002 c.slli64 zero + 26a: 44c1 li s1,16 + 26c: 44c8 lw a0,12(s1) + 26e: 44c9 li s1,18 + 270: 44d2 lw s1,20(sp) + 272: 000e44d3 .4byte 0xe44d3 + 276: 0000 unimp + 278: 0020 addi s0,sp,8 + 27a: 0000 unimp + 27c: 00b4 addi a3,sp,72 + ... + 286: 0000 unimp + 288: 0e44 addi s1,sp,788 + 28a: 4410 lw a2,8(s0) + 28c: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 28e: 0a40 addi s0,sp,276 + 290: 40c1 li ra,16 + 292: 000e c.slli zero,0x3 + 294: 0b40 addi s0,sp,404 + 296: c144 sw s1,4(a0) + 298: 0e44 addi s1,sp,788 + 29a: 0000 unimp + 29c: 0054 addi a3,sp,4 + 29e: 0000 unimp + 2a0: 00b4 addi a3,sp,72 + ... + 2aa: 0000 unimp + 2ac: 0e44 addi s1,sp,788 + 2ae: 01b0 addi a2,sp,200 + 2b0: 8140 .2byte 0x8140 + 2b2: 8801 andi s0,s0,0 + 2b4: 8902 jr s2 + 2b6: 93049203 lh tp,-1744(s1) + 2ba: 9405 srai s0,s0,0x21 + 2bc: 9506 add a0,a0,ra + 2be: 97089607 .4byte 0x97089607 + 2c2: 0209 addi tp,tp,2 # 2 + 2c4: 0a00 addi s0,sp,272 + 2c6: 44c8 lw a0,12(s1) + 2c8: 44c1 li s1,16 + 2ca: 44c9 li s1,18 + 2cc: 44d2 lw s1,20(sp) + 2ce: 44d444d3 .4byte 0x44d444d3 + 2d2: 44d6 lw s1,84(sp) + 2d4: 44d548d7 .4byte 0x44d548d7 + 2d8: 000e c.slli zero,0x3 + 2da: 0b40 addi s0,sp,404 + 2dc: c144 sw s1,4(a0) + 2de: c844 sw s1,20(s0) + 2e0: c944 sw s1,20(a0) + 2e2: d244 sw s1,36(a2) + 2e4: d344 sw s1,36(a4) + 2e6: d444 sw s1,44(s0) + 2e8: d544 sw s1,44(a0) + 2ea: d644 sw s1,44(a2) + 2ec: d744 sw s1,44(a4) + 2ee: 0e44 addi s1,sp,788 + 2f0: 0000 unimp + 2f2: 0000 unimp + 2f4: 0020 addi s0,sp,8 + 2f6: 0000 unimp + 2f8: 00b4 addi a3,sp,72 + ... + 302: 0000 unimp + 304: 0e44 addi s1,sp,788 + 306: 4410 lw a2,8(s0) + 308: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 30a: 0a40 addi s0,sp,276 + 30c: 40c1 li ra,16 + 30e: 000e c.slli zero,0x3 + 310: 0b40 addi s0,sp,404 + 312: c144 sw s1,4(a0) + 314: 0e44 addi s1,sp,788 + 316: 0000 unimp + 318: 000c .2byte 0xc + 31a: 0000 unimp + 31c: 00b4 addi a3,sp,72 + ... + 326: 0000 unimp + 328: 0018 .2byte 0x18 + 32a: 0000 unimp + 32c: 00b4 addi a3,sp,72 + 32e: 0000 unimp + 330: 08c4 addi s1,sp,84 + 332: 0000 unimp + 334: 0064 addi s1,sp,12 + 336: 0000 unimp + 338: 0e5c addi a5,sp,788 + 33a: 4820 lw s0,80(s0) + 33c: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 33e: c164 sw s1,68(a0) + 340: 0e48 addi a0,sp,788 + 342: 0000 unimp + 344: 000c .2byte 0xc + 346: 0000 unimp + 348: ffff .2byte 0xffff + 34a: ffff .2byte 0xffff + 34c: 7c010003 lb zero,1984(sp) + 350: 0d01 addi s10,s10,0 + 352: 0002 c.slli64 zero + 354: 0034 addi a3,sp,8 + 356: 0000 unimp + 358: 0344 addi s1,sp,388 + 35a: 0000 unimp + 35c: 0928 addi a0,sp,152 + 35e: 0000 unimp + 360: 0108 addi a0,sp,128 + 362: 0000 unimp + 364: 0e44 addi s1,sp,788 + 366: 5c30 lw a2,120(s0) + 368: 0288 addi a0,sp,320 + 36a: 0389 addi t2,t2,2 + 36c: 0492 slli s1,s1,0x4 + 36e: 06940593 addi a1,s0,105 + 372: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 374: 0795 addi a5,a5,5 + 376: c002 sw zero,0(sp) + 378: c10a sw sp,128(sp) + 37a: c844 sw s1,20(s0) + 37c: c944 sw s1,20(a0) + 37e: d244 sw s1,36(a2) + 380: d344 sw s1,36(a4) + 382: d444 sw s1,44(s0) + 384: d544 sw s1,44(a0) + 386: 0e44 addi s1,sp,788 + 388: 4400 lw s0,8(s0) + 38a: 000c000b .4byte 0xc000b + 38e: 0000 unimp + 390: 0344 addi s1,sp,388 + 392: 0000 unimp + 394: 0a30 addi a2,sp,280 + 396: 0000 unimp + 398: 003c addi a5,sp,8 + 39a: 0000 unimp + 39c: 000c .2byte 0xc + 39e: 0000 unimp + 3a0: 0344 addi s1,sp,388 + 3a2: 0000 unimp + 3a4: 0a6c addi a1,sp,284 + 3a6: 0000 unimp + 3a8: 002c addi a1,sp,8 + 3aa: 0000 unimp + 3ac: 000c .2byte 0xc + 3ae: 0000 unimp + 3b0: 0344 addi s1,sp,388 + 3b2: 0000 unimp + 3b4: 0a98 addi a4,sp,336 + 3b6: 0000 unimp + 3b8: 0010 .2byte 0x10 + 3ba: 0000 unimp + 3bc: 0024 addi s1,sp,8 + 3be: 0000 unimp + 3c0: 0344 addi s1,sp,388 + 3c2: 0000 unimp + 3c4: 0aa8 addi a0,sp,344 + 3c6: 0000 unimp + 3c8: 00ac addi a1,sp,72 + 3ca: 0000 unimp + 3cc: 0e44 addi s1,sp,788 + 3ce: 4c10 lw a2,24(s0) + 3d0: 0288 addi a0,sp,320 + 3d2: 0389 addi t2,t2,2 + 3d4: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 3d6: 5802 lw a6,32(sp) + 3d8: c10a sw sp,128(sp) + 3da: c844 sw s1,20(s0) + 3dc: c954 sw a3,20(a0) + 3de: 0e44 addi s1,sp,788 + 3e0: 4400 lw s0,8(s0) + 3e2: 000c000b .4byte 0xc000b + 3e6: 0000 unimp + 3e8: 0344 addi s1,sp,388 + ... + 3f2: 0000 unimp + 3f4: 000c .2byte 0xc + 3f6: 0000 unimp + 3f8: 0344 addi s1,sp,388 + ... + 402: 0000 unimp + 404: 000c .2byte 0xc + 406: 0000 unimp + 408: 0344 addi s1,sp,388 + 40a: 0000 unimp + 40c: 0b54 addi a3,sp,404 + 40e: 0000 unimp + 410: 0018 .2byte 0x18 + 412: 0000 unimp + 414: 001c .2byte 0x1c + 416: 0000 unimp + 418: 0344 addi s1,sp,388 + ... + 422: 0000 unimp + 424: 0e44 addi s1,sp,788 + 426: 4410 lw a2,8(s0) + 428: 0288 addi a0,sp,320 + 42a: 814c .2byte 0x814c + 42c: 4001 c.li zero,0 + 42e: 48c1 li a7,16 + 430: 44c8 lw a0,12(s1) + 432: 000e c.slli zero,0x3 + 434: 000c .2byte 0xc + 436: 0000 unimp + 438: 0344 addi s1,sp,388 + ... + 442: 0000 unimp + 444: 000c .2byte 0xc + 446: 0000 unimp + 448: 0344 addi s1,sp,388 + ... + 452: 0000 unimp + 454: 0018 .2byte 0x18 + 456: 0000 unimp + 458: 0344 addi s1,sp,388 + ... + 462: 0000 unimp + 464: 0e44 addi s1,sp,788 + 466: 4410 lw a2,8(s0) + 468: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 46a: c140 sw s0,4(a0) + 46c: 0e44 addi s1,sp,788 + 46e: 0000 unimp + 470: 000c .2byte 0xc + 472: 0000 unimp + 474: 0344 addi s1,sp,388 + ... + 47e: 0000 unimp + 480: 000c .2byte 0xc + 482: 0000 unimp + 484: 0344 addi s1,sp,388 + ... + 48e: 0000 unimp + 490: 000c .2byte 0xc + 492: 0000 unimp + 494: 0344 addi s1,sp,388 + ... + 49e: 0000 unimp + 4a0: 0028 addi a0,sp,8 + 4a2: 0000 unimp + 4a4: 0344 addi s1,sp,388 + 4a6: 0000 unimp + 4a8: 0b6c addi a1,sp,412 + 4aa: 0000 unimp + 4ac: 0058 addi a4,sp,4 + 4ae: 0000 unimp + 4b0: 0e44 addi s1,sp,788 + 4b2: 5010 lw a2,32(s0) + 4b4: 0288 addi a0,sp,320 + 4b6: 0492 slli s1,s1,0x4 + 4b8: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 4ba: 0389 addi t2,t2,2 + 4bc: 0a58 addi a4,sp,276 + 4be: 44c1 li s1,16 + 4c0: 44c8 lw a0,12(s1) + 4c2: 44c9 li s1,18 + 4c4: 44d2 lw s1,20(sp) + 4c6: 000e c.slli zero,0x3 + 4c8: 0b44 addi s1,sp,404 + 4ca: 0000 unimp + 4cc: 0044 addi s1,sp,4 + 4ce: 0000 unimp + 4d0: 0344 addi s1,sp,388 + 4d2: 0000 unimp + 4d4: 0bc4 addi s1,sp,468 + 4d6: 0000 unimp + 4d8: 01d8 addi a4,sp,196 + 4da: 0000 unimp + 4dc: 0e44 addi s1,sp,788 + 4de: 7460 .2byte 0x7460 + 4e0: 0b89 addi s7,s7,2 + 4e2: 0c92 slli s9,s9,0x4 + 4e4: 0e940d93 addi s11,s0,233 + 4e8: 0f95 addi t6,t6,5 # fffe4005 <__crt0_stack_begin+0x7ffe2009> + 4ea: 1096 slli ra,ra,0x25 + 4ec: 12981197 auipc gp,0x12981 + 4f0: 1399 addi t2,t2,-26 + 4f2: 0981 addi s3,s3,0 + 4f4: 0a88 addi a0,sp,336 + 4f6: 4c02 lw s8,0(sp) + 4f8: c10a sw sp,128(sp) + 4fa: c844 sw s1,20(s0) + 4fc: c944 sw s1,20(a0) + 4fe: d244 sw s1,36(a2) + 500: d344 sw s1,36(a4) + 502: d444 sw s1,44(s0) + 504: d544 sw s1,44(a0) + 506: d644 sw s1,44(a2) + 508: d744 sw s1,44(a4) + 50a: d844 sw s1,52(s0) + 50c: d944 sw s1,52(a0) + 50e: 0e44 addi s1,sp,788 + 510: 4400 lw s0,8(s0) + 512: 0038000b .4byte 0x38000b + 516: 0000 unimp + 518: 0344 addi s1,sp,388 + ... + 522: 0000 unimp + 524: 0e44 addi s1,sp,788 + 526: 6440 .2byte 0x6440 + 528: 0289 addi t0,t0,2 + 52a: 0392 slli t2,t2,0x4 + 52c: 05940493 addi s1,s0,89 + 530: 0695 addi a3,a3,5 + 532: 0796 slli a5,a5,0x5 + 534: 01810897 auipc a7,0x1810 + 538: 0998 addi a4,sp,208 + 53a: 0002 c.slli64 zero + 53c: 44c1 li s1,16 + 53e: 44c9 li s1,18 + 540: 44d444d3 .4byte 0x44d444d3 + 544: 44d5 li s1,21 + 546: 44d6 lw s1,84(sp) + 548: 48d844d7 .4byte 0x48d844d7 + 54c: 44d2 lw s1,20(sp) + 54e: 000e c.slli zero,0x3 + 550: 000c .2byte 0xc + 552: 0000 unimp + 554: 0344 addi s1,sp,388 + ... + 55e: 0000 unimp + 560: 0024 addi s1,sp,8 + 562: 0000 unimp + 564: 0344 addi s1,sp,388 + ... + 56e: 0000 unimp + 570: 0e44 addi s1,sp,788 + 572: 4c10 lw a2,24(s0) + 574: 0288 addi a0,sp,320 + 576: 0389 addi t2,t2,2 + 578: 0181 addi gp,gp,0 # 129814ec <__neorv32_ram_size+0x1297f4ec> + 57a: 0002 c.slli64 zero + 57c: c10a sw sp,128(sp) + 57e: c844 sw s1,20(s0) + 580: c940 sw s0,20(a0) + 582: 0e44 addi s1,sp,788 + 584: 4400 lw s0,8(s0) + 586: 000c000b .4byte 0xc000b + 58a: 0000 unimp + 58c: 0344 addi s1,sp,388 + ... + 596: 0000 unimp + 598: 000c .2byte 0xc + 59a: 0000 unimp + 59c: 0344 addi s1,sp,388 + ... + 5a6: 0000 unimp + 5a8: 000c .2byte 0xc + 5aa: 0000 unimp + 5ac: 0344 addi s1,sp,388 + ... + 5b6: 0000 unimp + 5b8: 000c .2byte 0xc + 5ba: 0000 unimp + 5bc: 0344 addi s1,sp,388 + ... + 5c6: 0000 unimp + 5c8: 000c .2byte 0xc + 5ca: 0000 unimp + 5cc: 0344 addi s1,sp,388 + ... + 5d6: 0000 unimp + 5d8: 000c .2byte 0xc + 5da: 0000 unimp + 5dc: 0344 addi s1,sp,388 + ... + 5e6: 0000 unimp + 5e8: 000c .2byte 0xc + 5ea: 0000 unimp + 5ec: 0344 addi s1,sp,388 + ... + 5f6: 0000 unimp + 5f8: 000c .2byte 0xc + 5fa: 0000 unimp + 5fc: 0344 addi s1,sp,388 + ... + 606: 0000 unimp + 608: 0028 addi a0,sp,8 + 60a: 0000 unimp + 60c: 0344 addi s1,sp,388 + ... + 616: 0000 unimp + 618: 0e44 addi s1,sp,788 + 61a: 5010 lw a2,32(s0) + 61c: 0288 addi a0,sp,320 + 61e: 0492 slli s1,s1,0x4 + 620: 0181 addi gp,gp,0 # 80001040 <__global_pointer$> + 622: 0389 addi t2,t2,2 + 624: 0a40 addi s0,sp,276 + 626: 44c1 li s1,16 + 628: 44c8 lw a0,12(s1) + 62a: 44c9 li s1,18 + 62c: 44d2 lw s1,20(sp) + 62e: 000e c.slli zero,0x3 + 630: 0b44 addi s1,sp,404 + 632: 0000 unimp + 634: 0044 addi s1,sp,4 + 636: 0000 unimp + 638: 0344 addi s1,sp,388 + ... + 642: 0000 unimp + 644: 0e44 addi s1,sp,788 + 646: 7460 .2byte 0x7460 + 648: 0b89 addi s7,s7,2 + 64a: 0c92 slli s9,s9,0x4 + 64c: 0e940d93 addi s11,s0,233 + 650: 0f95 addi t6,t6,5 + 652: 1096 slli ra,ra,0x25 + 654: 12981197 auipc gp,0x12981 + 658: 1399 addi t2,t2,-26 + 65a: 0981 addi s3,s3,0 + 65c: 0a88 addi a0,sp,336 + 65e: 0002 c.slli64 zero + 660: c10a sw sp,128(sp) + 662: c844 sw s1,20(s0) + 664: c944 sw s1,20(a0) + 666: d244 sw s1,36(a2) + 668: d344 sw s1,36(a4) + 66a: d444 sw s1,44(s0) + 66c: d544 sw s1,44(a0) + 66e: d644 sw s1,44(a2) + 670: d744 sw s1,44(a4) + 672: d844 sw s1,52(s0) + 674: d944 sw s1,52(a0) + 676: 0e44 addi s1,sp,788 + 678: 4400 lw s0,8(s0) + 67a: 0038000b .4byte 0x38000b + 67e: 0000 unimp + 680: 0344 addi s1,sp,388 + ... + 68a: 0000 unimp + 68c: 0e44 addi s1,sp,788 + 68e: 6440 .2byte 0x6440 + 690: 0289 addi t0,t0,2 + 692: 0392 slli t2,t2,0x4 + 694: 05940493 addi s1,s0,89 + 698: 0695 addi a3,a3,5 + 69a: 0796 slli a5,a5,0x5 + 69c: 01810897 auipc a7,0x1810 + 6a0: 0998 addi a4,sp,208 + 6a2: 0002 c.slli64 zero + 6a4: 44c1 li s1,16 + 6a6: 44c9 li s1,18 + 6a8: 44d444d3 .4byte 0x44d444d3 + 6ac: 44d5 li s1,21 + 6ae: 44d6 lw s1,84(sp) + 6b0: 48d844d7 .4byte 0x48d844d7 + 6b4: 44d2 lw s1,20(sp) + 6b6: 000e c.slli zero,0x3 + 6b8: 000c .2byte 0xc + 6ba: 0000 unimp + 6bc: ffff .2byte 0xffff + 6be: ffff .2byte 0xffff + 6c0: 7c010003 lb zero,1984(sp) + 6c4: 0d01 addi s10,s10,0 + 6c6: 0002 c.slli64 zero + 6c8: 0020 addi s0,sp,8 + 6ca: 0000 unimp + 6cc: 06b8 addi a4,sp,840 + ... + 6d6: 0000 unimp + 6d8: 0e44 addi s1,sp,788 + 6da: 4410 lw a2,8(s0) + 6dc: 0181 addi gp,gp,0 # 12981654 <__neorv32_ram_size+0x1297f654> + 6de: 0a40 addi s0,sp,276 + 6e0: 40c1 li ra,16 + 6e2: 000e c.slli zero,0x3 + 6e4: 0b40 addi s0,sp,404 + 6e6: c144 sw s1,4(a0) + 6e8: 0e44 addi s1,sp,788 + 6ea: 0000 unimp + 6ec: 000c .2byte 0xc + 6ee: 0000 unimp + 6f0: 06b8 addi a4,sp,840 + ... + 6fa: 0000 unimp + 6fc: 000c .2byte 0xc + 6fe: 0000 unimp + 700: 06b8 addi a4,sp,840 + ... + 70a: 0000 unimp + 70c: 000c .2byte 0xc + 70e: 0000 unimp + 710: 06b8 addi a4,sp,840 + ... + 71a: 0000 unimp + 71c: 000c .2byte 0xc + 71e: 0000 unimp + 720: 06b8 addi a4,sp,840 + ... + 72a: 0000 unimp + 72c: 000c .2byte 0xc + 72e: 0000 unimp + 730: 06b8 addi a4,sp,840 + ... + 73a: 0000 unimp + 73c: 000c .2byte 0xc + 73e: 0000 unimp + 740: 06b8 addi a4,sp,840 + ... + 74a: 0000 unimp + 74c: 000c .2byte 0xc + 74e: 0000 unimp + 750: 06b8 addi a4,sp,840 + ... + 75a: 0000 unimp + 75c: 000c .2byte 0xc + 75e: 0000 unimp + 760: 06b8 addi a4,sp,840 + ... + 76a: 0000 unimp + 76c: 000c .2byte 0xc + 76e: 0000 unimp + 770: 06b8 addi a4,sp,840 + ... + 77a: 0000 unimp + 77c: 000c .2byte 0xc + 77e: 0000 unimp + 780: 06b8 addi a4,sp,840 + ... + 78a: 0000 unimp + 78c: 000c .2byte 0xc + 78e: 0000 unimp + 790: 06b8 addi a4,sp,840 + ... + 79a: 0000 unimp + 79c: 000c .2byte 0xc + 79e: 0000 unimp + 7a0: 06b8 addi a4,sp,840 + ... + 7aa: 0000 unimp + 7ac: 000c .2byte 0xc + 7ae: 0000 unimp + 7b0: 06b8 addi a4,sp,840 + ... + 7ba: 0000 unimp + 7bc: 000c .2byte 0xc + 7be: 0000 unimp + 7c0: 06b8 addi a4,sp,840 + ... + 7ca: 0000 unimp + 7cc: 000c .2byte 0xc + 7ce: 0000 unimp + 7d0: 06b8 addi a4,sp,840 + ... + 7da: 0000 unimp + 7dc: 000c .2byte 0xc + 7de: 0000 unimp + 7e0: 06b8 addi a4,sp,840 + ... + 7ea: 0000 unimp + 7ec: 000c .2byte 0xc + 7ee: 0000 unimp + 7f0: 06b8 addi a4,sp,840 + ... + 7fa: 0000 unimp + 7fc: 000c .2byte 0xc + 7fe: 0000 unimp + 800: 06b8 addi a4,sp,840 + ... + 80a: 0000 unimp + 80c: 000c .2byte 0xc + 80e: 0000 unimp + 810: 06b8 addi a4,sp,840 + ... + 81a: 0000 unimp + 81c: 000c .2byte 0xc + 81e: 0000 unimp + 820: 06b8 addi a4,sp,840 + ... + 82a: 0000 unimp + 82c: 000c .2byte 0xc + 82e: 0000 unimp + 830: 06b8 addi a4,sp,840 + ... + 83a: 0000 unimp + 83c: 000c .2byte 0xc + 83e: 0000 unimp + 840: 06b8 addi a4,sp,840 + ... + 84a: 0000 unimp + 84c: 000c .2byte 0xc + 84e: 0000 unimp + 850: 06b8 addi a4,sp,840 + ... + 85a: 0000 unimp + 85c: 0028 addi a0,sp,8 + 85e: 0000 unimp + 860: 06b8 addi a4,sp,840 + ... + 86a: 0000 unimp + 86c: 0e44 addi s1,sp,788 + 86e: 4c10 lw a2,24(s0) + 870: 0288 addi a0,sp,320 + 872: 0389 addi t2,t2,2 + 874: 0492 slli s1,s1,0x4 + 876: 814c .2byte 0x814c + 878: 4001 c.li zero,0 + 87a: c10a sw sp,128(sp) + 87c: c844 sw s1,20(s0) + 87e: c944 sw s1,20(a0) + 880: d244 sw s1,36(a2) + 882: 0e44 addi s1,sp,788 + 884: 4400 lw s0,8(s0) + 886: 000c000b .4byte 0xc000b + 88a: 0000 unimp + 88c: 06b8 addi a4,sp,840 + ... + 896: 0000 unimp + 898: 000c .2byte 0xc + 89a: 0000 unimp + 89c: 06b8 addi a4,sp,840 + ... + 8a6: 0000 unimp + 8a8: 000c .2byte 0xc + 8aa: 0000 unimp + 8ac: 06b8 addi a4,sp,840 + ... + 8b6: 0000 unimp + 8b8: 000c .2byte 0xc + 8ba: 0000 unimp + 8bc: 06b8 addi a4,sp,840 + ... + 8c6: 0000 unimp + 8c8: 000c .2byte 0xc + 8ca: 0000 unimp + 8cc: 06b8 addi a4,sp,840 + ... + 8d6: 0000 unimp + 8d8: 000c .2byte 0xc + 8da: 0000 unimp + 8dc: 06b8 addi a4,sp,840 + ... + 8e6: 0000 unimp + 8e8: 0028 addi a0,sp,8 + 8ea: 0000 unimp + 8ec: 06b8 addi a4,sp,840 + ... + 8f6: 0000 unimp + 8f8: 0e44 addi s1,sp,788 + 8fa: 4c10 lw a2,24(s0) + 8fc: 0288 addi a0,sp,320 + 8fe: 0389 addi t2,t2,2 + 900: 0492 slli s1,s1,0x4 + 902: 814c .2byte 0x814c + 904: 4001 c.li zero,0 + 906: c10a sw sp,128(sp) + 908: c844 sw s1,20(s0) + 90a: c944 sw s1,20(a0) + 90c: d244 sw s1,36(a2) + 90e: 0e44 addi s1,sp,788 + 910: 4400 lw s0,8(s0) + 912: 000c000b .4byte 0xc000b + 916: 0000 unimp + 918: 06b8 addi a4,sp,840 + ... + 922: 0000 unimp + 924: 000c .2byte 0xc + 926: 0000 unimp + 928: 06b8 addi a4,sp,840 + 92a: 0000 unimp + 92c: 0d9c addi a5,sp,720 + 92e: 0000 unimp + 930: 0038 addi a4,sp,8 + ... + +Disassembly of section .debug_str: + +00000000 <.debug_str>: + 0: 5f5f 6975 746e .byte 0x5f, 0x5f, 0x75, 0x69, 0x6e, 0x74 + 6: 5f38 lw a4,120(a4) + 8: 0074 addi a3,sp,12 + a: 454e lw a0,208(sp) + c: 3356524f .4byte 0x3356524f + 10: 5f32 lw t5,44(sp) + 12: 4155 li sp,21 + 14: 5452 lw s0,52(sp) + 16: 465f 4f4c 5f57 .byte 0x5f, 0x46, 0x4c, 0x4f, 0x57, 0x5f + 1c: 544e4f43 .4byte 0x544e4f43 + 20: 4f52 lw t5,20(sp) + 22: 5f4c lw a1,60(a4) + 24: 6e65 lui t3,0x19 + 26: 6d75 lui s10,0x1d + 28: 4600 lw s0,8(a2) + 2a: 4f4c lw a1,28(a4) + 2c: 4f435f57 .4byte 0x4f435f57 + 30: 544e lw s0,240(sp) + 32: 4f52 lw t5,20(sp) + 34: 5f4c lw a1,60(a4) + 36: 00535443 .4byte 0x535443 + 3a: 726f6873 csrrsi a6,mhpmevent6h,30 + 3e: 2074 .2byte 0x2074 + 40: 6e75 lui t3,0x1d + 42: 6e676973 csrrsi s2,0x6e6,14 + 46: 6465 lui s0,0x19 + 48: 6920 .2byte 0x6920 + 4a: 746e .2byte 0x746e + 4c: 4900 lw s0,16(a0) + 4e: 454d li a0,19 + 50: 5f4d li t5,-13 + 52: 455a4953 .4byte 0x455a4953 + 56: 6e00 .2byte 0x6e00 + 58: 6f65 lui t5,0x19 + 5a: 7672 .2byte 0x7672 + 5c: 755f3233 .4byte 0x755f3233 + 60: 7261 lui tp,0xffff8 + 62: 3074 .2byte 0x3074 + 64: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 6a: 0066 c.slli zero,0x19 + 6c: 4c46 lw s8,80(sp) + 6e: 435f574f .4byte 0x435f574f + 72: 52544e4f .4byte 0x52544e4f + 76: 4e5f4c4f .4byte 0x4e5f4c4f + 7a: 00454e4f .4byte 0x454e4f + 7e: 5f6e lw t5,248(sp) + 80: 616d addi sp,sp,240 + 82: 0078 addi a4,sp,12 + 84: 54535543 .4byte 0x54535543 + 88: 495f4d4f .4byte 0x495f4d4f + 8c: 0044 addi s1,sp,4 + 8e: 4d44 lw s1,28(a0) + 90: 4d45 li s10,17 + 92: 535f 5a49 0045 .byte 0x5f, 0x53, 0x49, 0x5a, 0x45, 0x00 + 98: 656e .2byte 0x656e + 9a: 3376726f jal tp,67bd0 <__neorv32_ram_size+0x65bd0> + 9e: 5f32 lw t5,44(sp) + a0: 69737973 csrrci s2,0x697,6 + a4: 666e .2byte 0x666e + a6: 00745f6f jal t5,458ac <__neorv32_ram_size+0x438ac> + aa: 5344 lw s1,36(a4) + ac: 4150 lw a2,4(a0) + ae: 425f4543 .4byte 0x425f4543 + b2: 5341 li t1,-16 + b4: 0045 c.nop 17 + b6: 6f6c .2byte 0x6f6c + b8: 676e .2byte 0x676e + ba: 6c20 .2byte 0x6c20 + bc: 20676e6f jal t3,762c2 <__neorv32_ram_size+0x742c2> + c0: 6e75 lui t3,0x1d + c2: 6e676973 csrrsi s2,0x6e6,14 + c6: 6465 lui s0,0x19 + c8: 6920 .2byte 0x6920 + ca: 746e .2byte 0x746e + cc: 6e00 .2byte 0x6e00 + ce: 6f65 lui t5,0x19 + d0: 7672 .2byte 0x7672 + d2: 755f3233 .4byte 0x755f3233 + d6: 7261 lui tp,0xffff8 + d8: 3074 .2byte 0x3074 + da: 705f 7475 0073 .byte 0x5f, 0x70, 0x75, 0x74, 0x73, 0x00 + e0: 6e66 .2byte 0x6e66 + e2: 6d5f 6d65 7500 .byte 0x5f, 0x6d, 0x65, 0x6d, 0x00, 0x75 + e8: 736e .2byte 0x736e + ea: 6769 lui a4,0x1a + ec: 656e .2byte 0x656e + ee: 2064 .2byte 0x2064 + f0: 72616863 bltu sp,t1,820 <__neorv32_rte_debug_handler+0x2bc> + f4: 6e00 .2byte 0x6e00 + f6: 6f65 lui t5,0x19 + f8: 7672 .2byte 0x7672 + fa: 725f3233 .4byte 0x725f3233 + fe: 6574 .2byte 0x6574 + 100: 735f 7465 7075 .byte 0x5f, 0x73, 0x65, 0x74, 0x75, 0x70 + 106: 6e00 .2byte 0x6e00 + 108: 6f65 lui t5,0x19 + 10a: 7672 .2byte 0x7672 + 10c: 725f3233 .4byte 0x725f3233 + 110: 6574 .2byte 0x6574 + 112: 635f 6568 6b63 .byte 0x5f, 0x63, 0x68, 0x65, 0x63, 0x6b + 118: 695f 6173 4700 .byte 0x5f, 0x69, 0x73, 0x61, 0x00, 0x47 + 11e: 554e lw a0,240(sp) + 120: 4320 lw s0,64(a4) + 122: 3731 jal 2e + 124: 3120 .2byte 0x3120 + 126: 2e32 .2byte 0x2e32 + 128: 2e32 .2byte 0x2e32 + 12a: 2030 .2byte 0x2030 + 12c: 6d2d lui s10,0xb + 12e: 6261 lui tp,0x18 + 130: 3d69 jal ffffffca <__crt0_stack_begin+0x7fffdfce> + 132: 6c69 lui s8,0x1a + 134: 3370 .2byte 0x3370 + 136: 2032 .2byte 0x2032 + 138: 6d2d lui s10,0xb + 13a: 6f6e .2byte 0x6f6e + 13c: 662d lui a2,0xb + 13e: 6964 .2byte 0x6964 + 140: 2076 .2byte 0x2076 + 142: 6d2d lui s10,0xb + 144: 7574 .2byte 0x7574 + 146: 656e .2byte 0x656e + 148: 723d lui tp,0xfffef + 14a: 656b636f jal t1,b67a0 <__neorv32_ram_size+0xb47a0> + 14e: 2074 .2byte 0x2074 + 150: 6d2d lui s10,0xb + 152: 7369 lui t1,0xffffa + 154: 2d61 jal 7ec <__neorv32_rte_debug_handler+0x288> + 156: 63657073 csrci 0x636,10 + 15a: 323d jal fffffa88 <__crt0_stack_begin+0x7fffda8c> + 15c: 322e .2byte 0x322e + 15e: 2d20 .2byte 0x2d20 + 160: 616d addi sp,sp,240 + 162: 6372 .2byte 0x6372 + 164: 3d68 .2byte 0x3d68 + 166: 7672 .2byte 0x7672 + 168: 20693233 .4byte 0x20693233 + 16c: 672d lui a4,0xb + 16e: 2d20 .2byte 0x2d20 + 170: 2d20734f .4byte 0x2d20734f + 174: 6666 .2byte 0x6666 + 176: 6e75 lui t3,0x1d + 178: 6f697463 bgeu s2,s6,860 + 17c: 2d6e .2byte 0x2d6e + 17e: 74636573 csrrsi a0,0x746,6 + 182: 6f69 lui t5,0x1a + 184: 736e .2byte 0x736e + 186: 2d20 .2byte 0x2d20 + 188: 6466 .2byte 0x6466 + 18a: 7461 lui s0,0xffff8 + 18c: 2d61 jal 824 <__neorv32_rte_debug_handler+0x2c0> + 18e: 74636573 csrrsi a0,0x746,6 + 192: 6f69 lui t5,0x1a + 194: 736e .2byte 0x736e + 196: 5f00 lw s0,56(a4) + 198: 755f 6e69 3374 .byte 0x5f, 0x75, 0x69, 0x6e, 0x74, 0x33 + 19e: 5f32 lw t5,44(sp) + 1a0: 0074 addi a3,sp,12 + 1a2: 6e45 lui t3,0x11 + 1a4: 5f64 lw s1,124(a4) + 1a6: 6954 .2byte 0x6954 + 1a8: 656d lui a0,0x1b + 1aa: 4e00 lw s0,24(a2) + 1ac: 4f45 li t5,17 + 1ae: 5652 lw a2,52(sp) + 1b0: 555f3233 .4byte 0x555f3233 + 1b4: 5241 li tp,-16 + 1b6: 5f54 lw a3,60(a4) + 1b8: 4150 lw a2,4(a0) + 1ba: 4952 lw s2,20(sp) + 1bc: 5954 lw a3,52(a0) + 1be: 655f 756e 006d .byte 0x5f, 0x65, 0x6e, 0x75, 0x6d, 0x00 + 1c4: 616d addi sp,sp,240 + 1c6: 6e69 lui t3,0x1a + 1c8: 4200 lw s0,0(a2) + 1ca: 6765 lui a4,0x19 + 1cc: 6e69 lui t3,0x1a + 1ce: 545f 6d69 0065 .byte 0x5f, 0x54, 0x69, 0x6d, 0x65, 0x00 + 1d4: 7355 lui t1,0xffff5 + 1d6: 7265 lui tp,0xffff9 + 1d8: 545f 6d69 0065 .byte 0x5f, 0x54, 0x69, 0x6d, 0x65, 0x00 + 1de: 4c46 lw s8,80(sp) + 1e0: 435f574f .4byte 0x435f574f + 1e4: 52544e4f .4byte 0x52544e4f + 1e8: 525f4c4f .4byte 0x525f4c4f + 1ec: 5354 lw a3,36(a4) + 1ee: 5000 lw s0,32(s0) + 1f0: 5241 li tp,-16 + 1f2: 5449 li s0,-14 + 1f4: 5f59 li t5,-10 + 1f6: 0044444f .4byte 0x44444f + 1fa: 6f6c .2byte 0x6f6c + 1fc: 676e .2byte 0x676e + 1fe: 6c20 .2byte 0x6c20 + 200: 20676e6f jal t3,76406 <__neorv32_ram_size+0x74406> + 204: 6e69 lui t3,0x1a + 206: 0074 addi a3,sp,12 + 208: 4c46 lw s8,80(sp) + 20a: 435f574f .4byte 0x435f574f + 20e: 52544e4f .4byte 0x52544e4f + 212: 525f4c4f .4byte 0x525f4c4f + 216: 5354 lw a3,36(a4) + 218: 00535443 .4byte 0x535443 + 21c: 4150 lw a2,4(a0) + 21e: 4952 lw s2,20(sp) + 220: 5954 lw a3,52(a0) + 222: 455f 4556 004e .byte 0x5f, 0x45, 0x56, 0x45, 0x4e, 0x00 + 228: 726f6873 csrrsi a6,mhpmevent6h,30 + 22c: 2074 .2byte 0x2074 + 22e: 6e69 lui t3,0x1a + 230: 0074 addi a3,sp,12 + 232: 5349 li t1,-14 + 234: 4150 lw a2,4(a0) + 236: 425f4543 .4byte 0x425f4543 + 23a: 5341 li t1,-16 + 23c: 0045 c.nop 17 + 23e: 5f5f 6975 746e .byte 0x5f, 0x5f, 0x75, 0x69, 0x6e, 0x74 + 244: 3436 .2byte 0x3436 + 246: 745f 6e00 6f65 .byte 0x5f, 0x74, 0x00, 0x6e, 0x65, 0x6f + 24c: 7672 .2byte 0x7672 + 24e: 755f3233 .4byte 0x755f3233 + 252: 7261 lui tp,0xffff8 + 254: 3074 .2byte 0x3074 + 256: 735f 7465 7075 .byte 0x5f, 0x73, 0x65, 0x74, 0x75, 0x70 + 25c: 6c00 .2byte 0x6c00 + 25e: 20676e6f jal t3,76464 <__neorv32_ram_size+0x74464> + 262: 6f64 .2byte 0x6f64 + 264: 6275 lui tp,0x1d + 266: 656c .2byte 0x656c + 268: 6e00 .2byte 0x6e00 + 26a: 6f65 lui t5,0x19 + 26c: 7672 .2byte 0x7672 + 26e: 6d5f3233 .4byte 0x6d5f3233 + 272: 6974 .2byte 0x6974 + 274: 656d lui a0,0x1b + 276: 675f 7465 745f .byte 0x5f, 0x67, 0x65, 0x74, 0x5f, 0x74 + 27c: 6d69 lui s10,0x1a + 27e: 0065 c.nop 25 + 280: 4150 lw a2,4(a0) + 282: 4952 lw s2,20(sp) + 284: 5954 lw a3,52(a0) + 286: 4e5f 4e4f 0045 .byte 0x5f, 0x4e, 0x4f, 0x4e, 0x45, 0x00 + 28c: 616d addi sp,sp,240 + 28e: 6c6c .2byte 0x6c6c + 290: 6e00636f jal t1,6970 <__neorv32_ram_size+0x4970> + 294: 6f65 lui t5,0x19 + 296: 7672 .2byte 0x7672 + 298: 6d5f3233 .4byte 0x6d5f3233 + 29c: 6974 .2byte 0x6974 + 29e: 656d lui a0,0x1b + 2a0: 735f 7465 745f .byte 0x5f, 0x73, 0x65, 0x74, 0x5f, 0x74 + 2a6: 6d69 lui s10,0x1a + 2a8: 6365 lui t1,0x19 + 2aa: 706d c.lui zero,0xffffb + 2ac: 4e00 lw s0,24(a2) + 2ae: 4f45 li t5,17 + 2b0: 5652 lw a2,52(sp) + 2b2: 535f3233 .4byte 0x535f3233 + 2b6: 5359 li t1,-10 + 2b8: 4e49 li t3,18 + 2ba: 4f46 lw t5,80(sp) + 2bc: 535f 434f 655f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x65 + 2c2: 756e .2byte 0x756e + 2c4: 006d c.nop 27 + 2c6: 4954 lw a3,20(a0) + 2c8: 454d li a0,19 + 2ca: 4c5f 004f 5953 .byte 0x5f, 0x4c, 0x4f, 0x00, 0x53, 0x59 + 2d0: 464e4953 .4byte 0x464e4953 + 2d4: 4f535f4f .4byte 0x4f535f4f + 2d8: 454d5f43 .4byte 0x454d5f43 + 2dc: 5f4d li t5,-13 + 2de: 4e49 li t3,18 + 2e0: 5f54 lw a3,60(a4) + 2e2: 4d49 li s10,18 + 2e4: 4d45 li s10,17 + 2e6: 5300 lw s0,32(a4) + 2e8: 5359 li t1,-10 + 2ea: 4e49 li t3,18 + 2ec: 4f46 lw t5,80(sp) + 2ee: 535f 434f 4d5f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x4d + 2f4: 4d45 li s10,17 + 2f6: 495f 544e 445f .byte 0x5f, 0x49, 0x4e, 0x54, 0x5f, 0x44 + 2fc: 454d li a0,19 + 2fe: 004d c.nop 19 + 300: 49535953 .4byte 0x49535953 + 304: 464e lw a2,208(sp) + 306: 4f535f4f .4byte 0x4f535f4f + 30a: 4f495f43 .4byte 0x4f495f43 + 30e: 4d5f 4954 454d .byte 0x5f, 0x4d, 0x54, 0x49, 0x4d, 0x45 + 314: 5300 lw s0,32(a4) + 316: 5359 li t1,-10 + 318: 4e49 li t3,18 + 31a: 4f46 lw t5,80(sp) + 31c: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 322: 49535f53 .4byte 0x49535f53 + 326: 004d c.nop 19 + 328: 656e .2byte 0x656e + 32a: 3376726f jal tp,67e60 <__neorv32_ram_size+0x65e60> + 32e: 5f32 lw t5,44(sp) + 330: 746d lui s0,0xffffb + 332: 6d69 lui s10,0x1a + 334: 5f65 li t5,-7 + 336: 5f746573 csrrsi a0,0x5f7,8 + 33a: 6974 .2byte 0x6974 + 33c: 656d lui a0,0x1b + 33e: 5300 lw s0,32(a4) + 340: 5359 li t1,-10 + 342: 4e49 li t3,18 + 344: 4f46 lw t5,80(sp) + 346: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 34c: 57505f4f .4byte 0x57505f4f + 350: 004d c.nop 19 + 352: 49535953 .4byte 0x49535953 + 356: 464e lw a2,208(sp) + 358: 4f535f4f .4byte 0x4f535f4f + 35c: 4f495f43 .4byte 0x4f495f43 + 360: 585f 5049 5300 .byte 0x5f, 0x58, 0x49, 0x50, 0x00, 0x53 + 366: 5359 li t1,-10 + 368: 4e49 li t3,18 + 36a: 4f46 lw t5,80(sp) + 36c: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 372: 4e4f5f4f .4byte 0x4e4f5f4f + 376: 5745 li a4,-15 + 378: 5249 li tp,-14 + 37a: 0045 c.nop 17 + 37c: 656e .2byte 0x656e + 37e: 3376726f jal tp,67eb4 <__neorv32_ram_size+0x65eb4> + 382: 5f32 lw t5,44(sp) + 384: 746d lui s0,0xffffb + 386: 6d69 lui s10,0x1a + 388: 5f65 li t5,-7 + 38a: 0074 addi a3,sp,12 + 38c: 49535953 .4byte 0x49535953 + 390: 464e lw a2,208(sp) + 392: 4f535f4f .4byte 0x4f535f4f + 396: 4f495f43 .4byte 0x4f495f43 + 39a: 545f 4e52 0047 .byte 0x5f, 0x54, 0x52, 0x4e, 0x47, 0x00 + 3a0: 49535953 .4byte 0x49535953 + 3a4: 464e lw a2,208(sp) + 3a6: 4f535f4f .4byte 0x4f535f4f + 3aa: 434f5f43 .4byte 0x434f5f43 + 3ae: 0044 addi s1,sp,4 + 3b0: 49535953 .4byte 0x49535953 + 3b4: 464e lw a2,208(sp) + 3b6: 4f535f4f .4byte 0x4f535f4f + 3ba: 43495f43 .4byte 0x43495f43 + 3be: 4341 li t1,16 + 3c0: 4548 lw a0,12(a0) + 3c2: 5300 lw s0,32(a4) + 3c4: 5359 li t1,-10 + 3c6: 4e49 li t3,18 + 3c8: 4f46 lw t5,80(sp) + 3ca: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 3d0: 57545f4f .4byte 0x57545f4f + 3d4: 0049 c.nop 18 + 3d6: 49535953 .4byte 0x49535953 + 3da: 464e lw a2,208(sp) + 3dc: 4f535f4f .4byte 0x4f535f4f + 3e0: 4f495f43 .4byte 0x4f495f43 + 3e4: 4e5f 4f45 454c .byte 0x5f, 0x4e, 0x45, 0x4f, 0x4c, 0x45 + 3ea: 0044 addi s1,sp,4 + 3ec: 656e .2byte 0x656e + 3ee: 3376726f jal tp,67f24 <__neorv32_ram_size+0x65f24> + 3f2: 5f32 lw t5,44(sp) + 3f4: 746d lui s0,0xffffb + 3f6: 6d69 lui s10,0x1a + 3f8: 5f65 li t5,-7 + 3fa: 7661 lui a2,0xffff8 + 3fc: 6961 lui s2,0x18 + 3fe: 616c .2byte 0x616c + 400: 6c62 .2byte 0x6c62 + 402: 0065 c.nop 25 + 404: 49535953 .4byte 0x49535953 + 408: 464e lw a2,208(sp) + 40a: 4f535f4f .4byte 0x4f535f4f + 40e: 4f495f43 .4byte 0x4f495f43 + 412: 535f 494c 4b4e .byte 0x5f, 0x53, 0x4c, 0x49, 0x4e, 0x4b + 418: 5300 lw s0,32(a4) + 41a: 5359 li t1,-10 + 41c: 4e49 li t3,18 + 41e: 4f46 lw t5,80(sp) + 420: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 426: 49585f4f .4byte 0x49585f4f + 42a: 5152 lw sp,52(sp) + 42c: 7500 .2byte 0x7500 + 42e: 6e69 lui t3,0x1a + 430: 3674 .2byte 0x3674 + 432: 0034 addi a3,sp,8 + 434: 49535953 .4byte 0x49535953 + 438: 464e lw a2,208(sp) + 43a: 4f535f4f .4byte 0x4f535f4f + 43e: 4f425f43 .4byte 0x4f425f43 + 442: 4f4c544f .4byte 0x4f4c544f + 446: 4441 li s0,16 + 448: 5245 li tp,-15 + 44a: 5300 lw s0,32(a4) + 44c: 5359 li t1,-10 + 44e: 4e49 li t3,18 + 450: 4f46 lw t5,80(sp) + 452: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 458: 50535f4f .4byte 0x50535f4f + 45c: 0049 c.nop 18 + 45e: 6c637963 bgeu t1,t1,b30 + 462: 7365 lui t1,0xffff9 + 464: 6e00 .2byte 0x6e00 + 466: 6f65 lui t5,0x19 + 468: 7672 .2byte 0x7672 + 46a: 6d5f3233 .4byte 0x6d5f3233 + 46e: 6974 .2byte 0x6974 + 470: 656d lui a0,0x1b + 472: 675f 7465 745f .byte 0x5f, 0x67, 0x65, 0x74, 0x5f, 0x74 + 478: 6d69 lui s10,0x1a + 47a: 6365 lui t1,0x19 + 47c: 706d c.lui zero,0xffffb + 47e: 5300 lw s0,32(a4) + 480: 5359 li t1,-10 + 482: 4e49 li t3,18 + 484: 4f46 lw t5,80(sp) + 486: 535f 434f 4d5f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x4d + 48c: 4d45 li s10,17 + 48e: 455f 5458 455f .byte 0x5f, 0x45, 0x58, 0x54, 0x5f, 0x45 + 494: 444e lw s0,208(sp) + 496: 4149 li sp,18 + 498: 004e c.slli zero,0x13 + 49a: 6d74 .2byte 0x6d74 + 49c: 3170 .2byte 0x3170 + 49e: 7400 .2byte 0x7400 + 4a0: 706d c.lui zero,0xffffb + 4a2: 0032 c.slli zero,0xc + 4a4: 6d74 .2byte 0x6d74 + 4a6: 3370 .2byte 0x3370 + 4a8: 7500 .2byte 0x7500 + 4aa: 6e69 lui t3,0x1a + 4ac: 3374 .2byte 0x3374 + 4ae: 0032 c.slli zero,0xc + 4b0: 49535953 .4byte 0x49535953 + 4b4: 464e lw a2,208(sp) + 4b6: 4f535f4f .4byte 0x4f535f4f + 4ba: 4f495f43 .4byte 0x4f495f43 + 4be: 555f 5241 3054 .byte 0x5f, 0x55, 0x41, 0x52, 0x54, 0x30 + 4c4: 5300 lw s0,32(a4) + 4c6: 5359 li t1,-10 + 4c8: 4e49 li t3,18 + 4ca: 4f46 lw t5,80(sp) + 4cc: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 4d2: 41555f4f .4byte 0x41555f4f + 4d6: 5452 lw s0,52(sp) + 4d8: 0031 c.nop 12 + 4da: 4954 lw a3,20(a0) + 4dc: 454d li a0,19 + 4de: 5f504d43 .4byte 0x5f504d43 + 4e2: 4948 lw a0,20(a0) + 4e4: 5300 lw s0,32(a4) + 4e6: 5359 li t1,-10 + 4e8: 4e49 li t3,18 + 4ea: 4f46 lw t5,80(sp) + 4ec: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 4f2: 50475f4f .4byte 0x50475f4f + 4f6: 4d54 lw a3,28(a0) + 4f8: 0052 c.slli zero,0x14 + 4fa: 49535953 .4byte 0x49535953 + 4fe: 464e lw a2,208(sp) + 500: 4f535f4f .4byte 0x4f535f4f + 504: 454d5f43 .4byte 0x454d5f43 + 508: 5f4d li t5,-13 + 50a: 5845 li a6,-15 + 50c: 0054 addi a3,sp,4 + 50e: 49535953 .4byte 0x49535953 + 512: 464e lw a2,208(sp) + 514: 4f535f4f .4byte 0x4f535f4f + 518: 4f495f43 .4byte 0x4f495f43 + 51c: 435f 5346 5300 .byte 0x5f, 0x43, 0x46, 0x53, 0x00, 0x53 + 522: 5359 li t1,-10 + 524: 4e49 li t3,18 + 526: 4f46 lw t5,80(sp) + 528: 535f 434f 495f .byte 0x5f, 0x53, 0x4f, 0x43, 0x5f, 0x49 + 52e: 50475f4f .4byte 0x50475f4f + 532: 4f49 li t5,18 + 534: 5400 lw s0,40(s0) + 536: 4d49 li s10,18 + 538: 4345 li t1,17 + 53a: 504d c.li zero,-13 + 53c: 4c5f 004f 5953 .byte 0x5f, 0x4c, 0x4f, 0x00, 0x53, 0x59 + 542: 464e4953 .4byte 0x464e4953 + 546: 4f535f4f .4byte 0x4f535f4f + 54a: 4f495f43 .4byte 0x4f495f43 + 54e: 575f 5444 5400 .byte 0x5f, 0x57, 0x44, 0x54, 0x00, 0x54 + 554: 4d49 li s10,18 + 556: 5f45 li t5,-15 + 558: 4948 lw a0,20(a0) + 55a: 4300 lw s0,0(a4) + 55c: 4d5f5253 .4byte 0x4d5f5253 + 560: 5048 lw a0,36(s0) + 562: 434d li t1,19 + 564: 544e554f .4byte 0x544e554f + 568: 5245 li tp,-15 + 56a: 3432 .2byte 0x3432 + 56c: 0048 addi a0,sp,4 + 56e: 656e .2byte 0x656e + 570: 3376726f jal tp,680a6 <__neorv32_ram_size+0x660a6> + 574: 5f32 lw t5,44(sp) + 576: 7472 .2byte 0x7472 + 578: 5f65 li t5,-7 + 57a: 7270 .2byte 0x7270 + 57c: 6e69 lui t3,0x1a + 57e: 5f74 lw a3,124(a4) + 580: 6f6c .2byte 0x6f6c + 582: 6e006f67 .4byte 0x6e006f67 + 586: 6f65 lui t5,0x19 + 588: 7672 .2byte 0x7672 + 58a: 725f3233 .4byte 0x725f3233 + 58e: 6574 .2byte 0x6574 + 590: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 596: 6c5f 6369 6e65 .byte 0x5f, 0x6c, 0x69, 0x63, 0x65, 0x6e + 59c: 52006573 csrrsi a0,0x520,0 + 5a0: 4554 lw a3,12(a0) + 5a2: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 5a8: 454d li a0,19 + 5aa: 564e lw a2,240(sp) + 5ac: 435f 4c41 004c .byte 0x5f, 0x43, 0x41, 0x4c, 0x4c, 0x00 + 5b2: 5f525343 .4byte 0x5f525343 + 5b6: 494d li s2,19 + 5b8: 534e lw t1,240(sp) + 5ba: 5254 lw a3,36(a2) + 5bc: 5445 li s0,-15 + 5be: 4300 lw s0,0(a4) + 5c0: 485f5253 .4byte 0x485f5253 + 5c4: 4d50 lw a2,28(a0) + 5c6: 4e554f43 .4byte 0x4e554f43 + 5ca: 4554 lw a3,12(a0) + 5cc: 3252 .2byte 0x3252 + 5ce: 4834 lw a3,80(s0) + 5d0: 4300 lw s0,0(a4) + 5d2: 485f5253 .4byte 0x485f5253 + 5d6: 4d50 lw a2,28(a0) + 5d8: 4e554f43 .4byte 0x4e554f43 + 5dc: 4554 lw a3,12(a0) + 5de: 3552 .2byte 0x3552 + 5e0: 0048 addi a0,sp,4 + 5e2: 5f525343 .4byte 0x5f525343 + 5e6: 534d li t1,-13 + 5e8: 4154 lw a3,4(a0) + 5ea: 5554 lw a3,44(a0) + 5ec: 43004853 .4byte 0x43004853 + 5f0: 4d5f5253 .4byte 0x4d5f5253 + 5f4: 4958 lw a4,20(a0) + 5f6: 465f4153 .4byte 0x465f4153 + 5fa: 5341 li t1,-16 + 5fc: 4d54 lw a3,28(a0) + 5fe: 4c55 li s8,21 + 600: 4300 lw s0,0(a4) + 602: 545f5253 .4byte 0x545f5253 + 606: 4e49 li t3,18 + 608: 4f46 lw t5,80(sp) + 60a: 4e00 lw s0,24(a2) + 60c: 4f45 li t5,17 + 60e: 5652 lw a2,52(sp) + 610: 455f3233 .4byte 0x455f3233 + 614: 4358 lw a4,4(a4) + 616: 5045 c.li zero,-15 + 618: 4954 lw a3,20(a0) + 61a: 435f4e4f .4byte 0x435f4e4f + 61e: 5345444f .4byte 0x5345444f + 622: 655f 756e 006d .byte 0x5f, 0x65, 0x6e, 0x75, 0x6d, 0x00 + 628: 5254 lw a3,36(a2) + 62a: 5041 c.li zero,-16 + 62c: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 632: 5242 lw tp,48(sp) + 634: 4145 li sp,17 + 636: 494f504b .4byte 0x494f504b + 63a: 544e lw s0,240(sp) + 63c: 4300 lw s0,0(a4) + 63e: 4d5f5253 .4byte 0x4d5f5253 + 642: 5048 lw a0,36(s0) + 644: 434d li t1,19 + 646: 544e554f .4byte 0x544e554f + 64a: 5245 li tp,-15 + 64c: 3532 .2byte 0x3532 + 64e: 0048 addi a0,sp,4 + 650: 5f525343 .4byte 0x5f525343 + 654: 5246 lw tp,112(sp) + 656: 004d c.nop 19 + 658: 5f525343 .4byte 0x5f525343 + 65c: 5048 lw a0,36(s0) + 65e: 434d li t1,19 + 660: 544e554f .4byte 0x544e554f + 664: 5245 li tp,-15 + 666: 3532 .2byte 0x3532 + 668: 0048 addi a0,sp,4 + 66a: 5f525343 .4byte 0x5f525343 + 66e: 5048 lw a0,36(s0) + 670: 434d li t1,19 + 672: 544e554f .4byte 0x544e554f + 676: 5245 li tp,-15 + 678: 4836 lw a6,76(sp) + 67a: 7200 .2byte 0x7200 + 67c: 6574 .2byte 0x6574 + 67e: 6d5f 7065 0063 .byte 0x5f, 0x6d, 0x65, 0x70, 0x63, 0x00 + 684: 49535953 .4byte 0x49535953 + 688: 464e lw a2,208(sp) + 68a: 41435f4f .4byte 0x41435f4f + 68e: 5f454843 .4byte 0x5f454843 + 692: 4349 li t1,18 + 694: 415f 5353 434f .byte 0x5f, 0x41, 0x53, 0x53, 0x4f, 0x43 + 69a: 4149 li sp,18 + 69c: 4954 lw a3,20(a0) + 69e: 4956 lw s2,84(sp) + 6a0: 5954 lw a3,52(a0) + 6a2: 335f 4300 5253 .byte 0x5f, 0x33, 0x00, 0x43, 0x53, 0x52 + 6a8: 4d5f 5048 434d .byte 0x5f, 0x4d, 0x48, 0x50, 0x4d, 0x43 + 6ae: 544e554f .4byte 0x544e554f + 6b2: 5245 li tp,-15 + 6b4: 3031 jal fffffec0 <__crt0_stack_begin+0x7fffdec4> + 6b6: 4300 lw s0,0(a4) + 6b8: 4d5f5253 .4byte 0x4d5f5253 + 6bc: 5048 lw a0,36(s0) + 6be: 434d li t1,19 + 6c0: 544e554f .4byte 0x544e554f + 6c4: 5245 li tp,-15 + 6c6: 3131 jal 2d2 <__neorv32_rte_core+0x26> + 6c8: 4300 lw s0,0(a4) + 6ca: 4d5f5253 .4byte 0x4d5f5253 + 6ce: 5048 lw a0,36(s0) + 6d0: 434d li t1,19 + 6d2: 544e554f .4byte 0x544e554f + 6d6: 5245 li tp,-15 + 6d8: 3231 jal ffffffe4 <__crt0_stack_begin+0x7fffdfe8> + 6da: 4300 lw s0,0(a4) + 6dc: 4d5f5253 .4byte 0x4d5f5253 + 6e0: 5048 lw a0,36(s0) + 6e2: 434d li t1,19 + 6e4: 544e554f .4byte 0x544e554f + 6e8: 5245 li tp,-15 + 6ea: 3331 jal 3f6 <__neorv32_rte_core+0x14a> + 6ec: 4300 lw s0,0(a4) + 6ee: 4d5f5253 .4byte 0x4d5f5253 + 6f2: 5048 lw a0,36(s0) + 6f4: 434d li t1,19 + 6f6: 544e554f .4byte 0x544e554f + 6fa: 5245 li tp,-15 + 6fc: 3431 jal 108 <__crt0_call_destructors+0x4> + 6fe: 4300 lw s0,0(a4) + 700: 4d5f5253 .4byte 0x4d5f5253 + 704: 5048 lw a0,36(s0) + 706: 434d li t1,19 + 708: 544e554f .4byte 0x544e554f + 70c: 5245 li tp,-15 + 70e: 3531 jal 51a <__neorv32_rte_print_hex_word+0x26> + 710: 4300 lw s0,0(a4) + 712: 4d5f5253 .4byte 0x4d5f5253 + 716: 5048 lw a0,36(s0) + 718: 434d li t1,19 + 71a: 544e554f .4byte 0x544e554f + 71e: 5245 li tp,-15 + 720: 3631 jal 22c + 722: 4300 lw s0,0(a4) + 724: 4d5f5253 .4byte 0x4d5f5253 + 728: 5048 lw a0,36(s0) + 72a: 434d li t1,19 + 72c: 544e554f .4byte 0x544e554f + 730: 5245 li tp,-15 + 732: 3731 jal 63e <__neorv32_rte_debug_handler+0xda> + 734: 4300 lw s0,0(a4) + 736: 4d5f5253 .4byte 0x4d5f5253 + 73a: 5048 lw a0,36(s0) + 73c: 434d li t1,19 + 73e: 544e554f .4byte 0x544e554f + 742: 5245 li tp,-15 + 744: 3831 jal ffffff60 <__crt0_stack_begin+0x7fffdf64> + 746: 4300 lw s0,0(a4) + 748: 4d5f5253 .4byte 0x4d5f5253 + 74c: 5048 lw a0,36(s0) + 74e: 434d li t1,19 + 750: 544e554f .4byte 0x544e554f + 754: 5245 li tp,-15 + 756: 3931 jal 372 <__neorv32_rte_core+0xc6> + 758: 6300 .2byte 0x6300 + 75a: 695f7273 csrrci tp,0x695,30 + 75e: 0064 addi s1,sp,12 + 760: 5f525343 .4byte 0x5f525343 + 764: 484d li a6,19 + 766: 4d50 lw a2,28(a0) + 768: 4e554f43 .4byte 0x4e554f43 + 76c: 4554 lw a3,12(a0) + 76e: 3252 .2byte 0x3252 + 770: 4836 lw a6,76(sp) + 772: 4300 lw s0,0(a4) + 774: 4d5f5253 .4byte 0x4d5f5253 + 778: 5048 lw a0,36(s0) + 77a: 434d li t1,19 + 77c: 544e554f .4byte 0x544e554f + 780: 5245 li tp,-15 + 782: 00483033 sltu zero,a6,tp + 786: 5f525343 .4byte 0x5f525343 + 78a: 5048 lw a0,36(s0) + 78c: 434d li t1,19 + 78e: 544e554f .4byte 0x544e554f + 792: 5245 li tp,-15 + 794: 3632 .2byte 0x3632 + 796: 0048 addi a0,sp,4 + 798: 74617473 csrrci s0,0x746,2 + 79c: 0065 c.nop 25 + 79e: 5f525343 .4byte 0x5f525343 + 7a2: 5344 lw s1,36(a4) + 7a4: 54415243 .4byte 0x54415243 + 7a8: 00304843 .4byte 0x304843 + 7ac: 5f525343 .4byte 0x5f525343 + 7b0: 5048 lw a0,36(s0) + 7b2: 434d li t1,19 + 7b4: 544e554f .4byte 0x544e554f + 7b8: 5245 li tp,-15 + 7ba: 43004837 lui a6,0x43004 + 7be: 485f5253 .4byte 0x485f5253 + 7c2: 4d50 lw a2,28(a0) + 7c4: 4e554f43 .4byte 0x4e554f43 + 7c8: 4554 lw a3,12(a0) + 7ca: 3352 .2byte 0x3352 + 7cc: 4830 lw a2,80(s0) + 7ce: 4300 lw s0,0(a4) + 7d0: 4d5f5253 .4byte 0x4d5f5253 + 7d4: 4549 li a0,18 + 7d6: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + 7dc: 4530 lw a2,72(a0) + 7de: 4300 lw s0,0(a4) + 7e0: 4d5f5253 .4byte 0x4d5f5253 + 7e4: 5349 li t1,-14 + 7e6: 5f41 li t5,-16 + 7e8: 584d li a6,-13 + 7ea: 5f4c lw a1,60(a4) + 7ec: 4948 lw a0,20(a0) + 7ee: 5400 lw s0,40(s0) + 7f0: 4152 lw sp,20(sp) + 7f2: 5f50 lw a2,60(a4) + 7f4: 45444f43 .4byte 0x45444f43 + 7f8: 535f 4d5f 5349 .byte 0x5f, 0x53, 0x5f, 0x4d, 0x49, 0x53 + 7fe: 4c41 li s8,16 + 800: 4749 li a4,18 + 802: 454e lw a0,208(sp) + 804: 0044 addi s1,sp,4 + 806: 5f525343 .4byte 0x5f525343 + 80a: 484d li a6,19 + 80c: 4d50 lw a2,28(a0) + 80e: 4e554f43 .4byte 0x4e554f43 + 812: 4554 lw a3,12(a0) + 814: 3252 .2byte 0x3252 + 816: 0030 addi a2,sp,8 + 818: 5f525343 .4byte 0x5f525343 + 81c: 484d li a6,19 + 81e: 4d50 lw a2,28(a0) + 820: 4e554f43 .4byte 0x4e554f43 + 824: 4554 lw a3,12(a0) + 826: 3252 .2byte 0x3252 + 828: 0031 c.nop 12 + 82a: 5f525343 .4byte 0x5f525343 + 82e: 484d li a6,19 + 830: 4d50 lw a2,28(a0) + 832: 4e554f43 .4byte 0x4e554f43 + 836: 4554 lw a3,12(a0) + 838: 3252 .2byte 0x3252 + 83a: 0032 c.slli zero,0xc + 83c: 5f525343 .4byte 0x5f525343 + 840: 484d li a6,19 + 842: 4d50 lw a2,28(a0) + 844: 4e554f43 .4byte 0x4e554f43 + 848: 4554 lw a3,12(a0) + 84a: 3252 .2byte 0x3252 + 84c: 53430033 .4byte 0x53430033 + 850: 5f52 lw t5,52(sp) + 852: 484d li a6,19 + 854: 4d50 lw a2,28(a0) + 856: 4e554f43 .4byte 0x4e554f43 + 85a: 4554 lw a3,12(a0) + 85c: 3252 .2byte 0x3252 + 85e: 0034 addi a3,sp,8 + 860: 5f525343 .4byte 0x5f525343 + 864: 484d li a6,19 + 866: 4d50 lw a2,28(a0) + 868: 4e554f43 .4byte 0x4e554f43 + 86c: 4554 lw a3,12(a0) + 86e: 3252 .2byte 0x3252 + 870: 0035 c.nop 13 + 872: 5f525343 .4byte 0x5f525343 + 876: 484d li a6,19 + 878: 4d50 lw a2,28(a0) + 87a: 4e554f43 .4byte 0x4e554f43 + 87e: 4554 lw a3,12(a0) + 880: 3252 .2byte 0x3252 + 882: 0036 c.slli zero,0xd + 884: 5f525343 .4byte 0x5f525343 + 888: 484d li a6,19 + 88a: 4d50 lw a2,28(a0) + 88c: 4e554f43 .4byte 0x4e554f43 + 890: 4554 lw a3,12(a0) + 892: 3252 .2byte 0x3252 + 894: 53430037 lui zero,0x53430 + 898: 5f52 lw t5,52(sp) + 89a: 484d li a6,19 + 89c: 4d50 lw a2,28(a0) + 89e: 4e554f43 .4byte 0x4e554f43 + 8a2: 4554 lw a3,12(a0) + 8a4: 3252 .2byte 0x3252 + 8a6: 0038 addi a4,sp,8 + 8a8: 5f525343 .4byte 0x5f525343 + 8ac: 484d li a6,19 + 8ae: 4d50 lw a2,28(a0) + 8b0: 4e554f43 .4byte 0x4e554f43 + 8b4: 4554 lw a3,12(a0) + 8b6: 3252 .2byte 0x3252 + 8b8: 0039 c.nop 14 + 8ba: 454e lw a0,208(sp) + 8bc: 3356524f .4byte 0x3356524f + 8c0: 5f32 lw t5,44(sp) + 8c2: 5f525343 .4byte 0x5f525343 + 8c6: 494d li s2,19 + 8c8: 5f45 li t5,-15 + 8ca: 6e65 lui t3,0x19 + 8cc: 6d75 lui s10,0x1d + 8ce: 5300 lw s0,32(a4) + 8d0: 5359 li t1,-10 + 8d2: 4e49 li t3,18 + 8d4: 4f46 lw t5,80(sp) + 8d6: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 8dc: 495f 5f43 554e .byte 0x5f, 0x49, 0x43, 0x5f, 0x4e, 0x55 + 8e2: 5f4d li t5,-13 + 8e4: 4c42 lw s8,16(sp) + 8e6: 534b434f .4byte 0x534b434f + 8ea: 305f 4300 5253 .byte 0x5f, 0x30, 0x00, 0x43, 0x53, 0x52 + 8f0: 435f 4359 454c .byte 0x5f, 0x43, 0x59, 0x43, 0x4c, 0x45 + 8f6: 0048 addi a0,sp,4 + 8f8: 49535953 .4byte 0x49535953 + 8fc: 464e lw a2,208(sp) + 8fe: 41435f4f .4byte 0x41435f4f + 902: 5f454843 .4byte 0x5f454843 + 906: 4349 li t1,18 + 908: 4e5f 4d55 425f .byte 0x5f, 0x4e, 0x55, 0x4d, 0x5f, 0x42 + 90e: 4f4c lw a1,28(a4) + 910: 5f534b43 .4byte 0x5f534b43 + 914: 0032 c.slli zero,0xc + 916: 49535953 .4byte 0x49535953 + 91a: 464e lw a2,208(sp) + 91c: 41435f4f .4byte 0x41435f4f + 920: 5f454843 .4byte 0x5f454843 + 924: 4349 li t1,18 + 926: 4e5f 4d55 425f .byte 0x5f, 0x4e, 0x55, 0x4d, 0x5f, 0x42 + 92c: 4f4c lw a1,28(a4) + 92e: 5f534b43 .4byte 0x5f534b43 + 932: 54520033 .4byte 0x54520033 + 936: 5f45 li t5,-15 + 938: 5254 lw a3,36(a2) + 93a: 5041 c.li zero,-16 + 93c: 4c5f 4d5f 5349 .byte 0x5f, 0x4c, 0x5f, 0x4d, 0x49, 0x53 + 942: 4c41 li s8,16 + 944: 4749 li a4,18 + 946: 454e lw a0,208(sp) + 948: 0044 addi s1,sp,4 + 94a: 5f525343 .4byte 0x5f525343 + 94e: 484d li a6,19 + 950: 4d50 lw a2,28(a0) + 952: 4e554f43 .4byte 0x4e554f43 + 956: 4554 lw a3,12(a0) + 958: 3252 .2byte 0x3252 + 95a: 43004837 lui a6,0x43004 + 95e: 4d5f5253 .4byte 0x4d5f5253 + 962: 544e4f43 .4byte 0x544e4f43 + 966: 5845 li a6,-15 + 968: 0054 addi a3,sp,4 + 96a: 5f525343 .4byte 0x5f525343 + 96e: 584d li a6,-13 + 970: 5349 li t1,-14 + 972: 0041 c.nop 16 + 974: 5f525343 .4byte 0x5f525343 + 978: 484d li a6,19 + 97a: 4d50 lw a2,28(a0) + 97c: 4e554f43 .4byte 0x4e554f43 + 980: 4554 lw a3,12(a0) + 982: 3352 .2byte 0x3352 + 984: 4831 li a6,12 + 986: 4300 lw s0,0(a4) + 988: 485f5253 .4byte 0x485f5253 + 98c: 4d50 lw a2,28(a0) + 98e: 4e554f43 .4byte 0x4e554f43 + 992: 4554 lw a3,12(a0) + 994: 3252 .2byte 0x3252 + 996: 43004837 lui a6,0x43004 + 99a: 445f5253 .4byte 0x445f5253 + 99e: 00525343 .4byte 0x525343 + 9a2: 5f525343 .4byte 0x5f525343 + 9a6: 5048 lw a0,36(s0) + 9a8: 434d li t1,19 + 9aa: 544e554f .4byte 0x544e554f + 9ae: 5245 li tp,-15 + 9b0: 4838 lw a4,80(s0) + 9b2: 4300 lw s0,0(a4) + 9b4: 485f5253 .4byte 0x485f5253 + 9b8: 4d50 lw a2,28(a0) + 9ba: 4e554f43 .4byte 0x4e554f43 + 9be: 4554 lw a3,12(a0) + 9c0: 3352 .2byte 0x3352 + 9c2: 4831 li a6,12 + 9c4: 4300 lw s0,0(a4) + 9c6: 4d5f5253 .4byte 0x4d5f5253 + 9ca: 4549 li a0,18 + 9cc: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + 9d2: 4531 li a0,12 + 9d4: 4300 lw s0,0(a4) + 9d6: 485f5253 .4byte 0x485f5253 + 9da: 4d50 lw a2,28(a0) + 9dc: 4e554f43 .4byte 0x4e554f43 + 9e0: 4554 lw a3,12(a0) + 9e2: 3152 .2byte 0x3152 + 9e4: 53430037 lui zero,0x53430 + 9e8: 5f52 lw t5,52(sp) + 9ea: 544d li s0,-13 + 9ec: 4156 lw sp,84(sp) + 9ee: 004c addi a1,sp,4 + 9f0: 5f525343 .4byte 0x5f525343 + 9f4: 4346 lw t1,80(sp) + 9f6: 43005253 .4byte 0x43005253 + 9fa: 4d5f5253 .4byte 0x4d5f5253 + 9fe: 5048 lw a0,36(s0) + a00: 434d li t1,19 + a02: 544e554f .4byte 0x544e554f + a06: 5245 li tp,-15 + a08: 43003033 .4byte 0x43003033 + a0c: 4d5f5253 .4byte 0x4d5f5253 + a10: 5048 lw a0,36(s0) + a12: 434d li t1,19 + a14: 544e554f .4byte 0x544e554f + a18: 5245 li tp,-15 + a1a: 43003133 .4byte 0x43003133 + a1e: 4d5f5253 .4byte 0x4d5f5253 + a22: 5048 lw a0,36(s0) + a24: 434d li t1,19 + a26: 544e554f .4byte 0x544e554f + a2a: 5245 li tp,-15 + a2c: 43004833 .4byte 0x43004833 + a30: 4d5f5253 .4byte 0x4d5f5253 + a34: 5048 lw a0,36(s0) + a36: 434d li t1,19 + a38: 544e554f .4byte 0x544e554f + a3c: 5245 li tp,-15 + a3e: 3832 .2byte 0x3832 + a40: 0048 addi a0,sp,4 + a42: 5f525343 .4byte 0x5f525343 + a46: 4e49 li t3,18 + a48: 45525453 .4byte 0x45525453 + a4c: 4854 lw a3,20(s0) + a4e: 6e00 .2byte 0x6e00 + a50: 6f65 lui t5,0x19 + a52: 7672 .2byte 0x7672 + a54: 635f3233 .4byte 0x635f3233 + a58: 7570 .2byte 0x7570 + a5a: 6c5f 616f 5f64 .byte 0x5f, 0x6c, 0x6f, 0x61, 0x64, 0x5f + a60: 6e75 lui t3,0x1d + a62: 6e676973 csrrsi s2,0x6e6,14 + a66: 6465 lui s0,0x19 + a68: 685f 6c61 0066 .byte 0x5f, 0x68, 0x61, 0x6c, 0x66, 0x00 + a6e: 5f525343 .4byte 0x5f525343 + a72: 5048 lw a0,36(s0) + a74: 434d li t1,19 + a76: 544e554f .4byte 0x544e554f + a7a: 5245 li tp,-15 + a7c: 3832 .2byte 0x3832 + a7e: 0048 addi a0,sp,4 + a80: 656e .2byte 0x656e + a82: 3376726f jal tp,685b8 <__neorv32_ram_size+0x665b8> + a86: 5f32 lw t5,44(sp) + a88: 7562 .2byte 0x7562 + a8a: 65656b73 csrrsi s6,0x656,10 + a8e: 6570 .2byte 0x6570 + a90: 5f72 lw t5,60(sp) + a92: 0074 addi a3,sp,12 + a94: 5f525343 .4byte 0x5f525343 + a98: 5048 lw a0,36(s0) + a9a: 434d li t1,19 + a9c: 544e554f .4byte 0x544e554f + aa0: 5245 li tp,-15 + aa2: 4839 li a6,14 + aa4: 6e00 .2byte 0x6e00 + aa6: 6f65 lui t5,0x19 + aa8: 7672 .2byte 0x7672 + aaa: 635f3233 .4byte 0x635f3233 + aae: 7570 .2byte 0x7570 + ab0: 705f 706d 675f .byte 0x5f, 0x70, 0x6d, 0x70, 0x5f, 0x67 + ab6: 7465 lui s0,0xffff9 + ab8: 6e5f 6d75 725f .byte 0x5f, 0x6e, 0x75, 0x6d, 0x5f, 0x72 + abe: 6765 lui a4,0x19 + ac0: 6f69 lui t5,0x1a + ac2: 736e .2byte 0x736e + ac4: 4300 lw s0,0(a4) + ac6: 4d5f5253 .4byte 0x4d5f5253 + aca: 4549 li a0,18 + acc: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + ad2: 4532 lw a0,12(sp) + ad4: 7200 .2byte 0x7200 + ad6: 6574 .2byte 0x6574 + ad8: 6d5f 6163 7375 .byte 0x5f, 0x6d, 0x63, 0x61, 0x75, 0x73 + ade: 0065 c.nop 25 + ae0: 5f525343 .4byte 0x5f525343 + ae4: 494d li s2,19 + ae6: 0045 c.nop 17 + ae8: 5f525343 .4byte 0x5f525343 + aec: 494d li s2,19 + aee: 0050 addi a2,sp,4 + af0: 6572 .2byte 0x6572 + af2: 61645f67 .4byte 0x61645f67 + af6: 6174 .2byte 0x6174 + af8: 4300 lw s0,0(a4) + afa: 4d5f5253 .4byte 0x4d5f5253 + afe: 4c435943 .4byte 0x4c435943 + b02: 0045 c.nop 17 + b04: 5254 lw a3,36(a2) + b06: 5041 c.li zero,-16 + b08: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + b0e: 4946 lw s2,80(sp) + b10: 5152 lw sp,52(sp) + b12: 315f 0030 5254 .byte 0x5f, 0x31, 0x30, 0x00, 0x54, 0x52 + b18: 5041 c.li zero,-16 + b1a: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + b20: 4946 lw s2,80(sp) + b22: 5152 lw sp,52(sp) + b24: 315f 0031 5254 .byte 0x5f, 0x31, 0x31, 0x00, 0x54, 0x52 + b2a: 5041 c.li zero,-16 + b2c: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + b32: 4946 lw s2,80(sp) + b34: 5152 lw sp,52(sp) + b36: 315f 0032 5254 .byte 0x5f, 0x31, 0x32, 0x00, 0x54, 0x52 + b3c: 5041 c.li zero,-16 + b3e: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + b44: 4946 lw s2,80(sp) + b46: 5152 lw sp,52(sp) + b48: 315f 0033 5343 .byte 0x5f, 0x31, 0x33, 0x00, 0x43, 0x53 + b4e: 5f52 lw t5,52(sp) + b50: 484d li a6,19 + b52: 4d50 lw a2,28(a0) + b54: 4e554f43 .4byte 0x4e554f43 + b58: 4554 lw a3,12(a0) + b5a: 3452 .2byte 0x3452 + b5c: 0048 addi a0,sp,4 + b5e: 5254 lw a3,36(a2) + b60: 5041 c.li zero,-16 + b62: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + b68: 4946 lw s2,80(sp) + b6a: 5152 lw sp,52(sp) + b6c: 315f 0035 5343 .byte 0x5f, 0x31, 0x35, 0x00, 0x43, 0x53 + b72: 5f52 lw t5,52(sp) + b74: 484d li a6,19 + b76: 4d50 lw a2,28(a0) + b78: 4e554f43 .4byte 0x4e554f43 + b7c: 4554 lw a3,12(a0) + b7e: 3252 .2byte 0x3252 + b80: 4839 li a6,14 + b82: 4300 lw s0,0(a4) + b84: 485f5253 .4byte 0x485f5253 + b88: 4d50 lw a2,28(a0) + b8a: 4e554f43 .4byte 0x4e554f43 + b8e: 4554 lw a3,12(a0) + b90: 3252 .2byte 0x3252 + b92: 4839 li a6,14 + b94: 4300 lw s0,0(a4) + b96: 4d5f5253 .4byte 0x4d5f5253 + b9a: 4549 li a0,18 + b9c: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + ba2: 43004533 .4byte 0x43004533 + ba6: 485f5253 .4byte 0x485f5253 + baa: 4d50 lw a2,28(a0) + bac: 4e554f43 .4byte 0x4e554f43 + bb0: 4554 lw a3,12(a0) + bb2: 3252 .2byte 0x3252 + bb4: 0036 c.slli zero,0xd + bb6: 5f525343 .4byte 0x5f525343 + bba: 5048 lw a0,36(s0) + bbc: 434d li t1,19 + bbe: 544e554f .4byte 0x544e554f + bc2: 5245 li tp,-15 + bc4: 3732 .2byte 0x3732 + bc6: 4300 lw s0,0(a4) + bc8: 505f5253 .4byte 0x505f5253 + bcc: 504d c.li zero,-13 + bce: 4441 li s0,16 + bd0: 5244 lw s1,36(a2) + bd2: 3031 jal 3de <__neorv32_rte_core+0x132> + bd4: 4300 lw s0,0(a4) + bd6: 505f5253 .4byte 0x505f5253 + bda: 504d c.li zero,-13 + bdc: 4441 li s0,16 + bde: 5244 lw s1,36(a2) + be0: 3131 jal 7ec <__neorv32_rte_debug_handler+0x288> + be2: 4300 lw s0,0(a4) + be4: 505f5253 .4byte 0x505f5253 + be8: 504d c.li zero,-13 + bea: 4441 li s0,16 + bec: 5244 lw s1,36(a2) + bee: 3231 jal 4fa <__neorv32_rte_print_hex_word+0x6> + bf0: 4300 lw s0,0(a4) + bf2: 505f5253 .4byte 0x505f5253 + bf6: 504d c.li zero,-13 + bf8: 4441 li s0,16 + bfa: 5244 lw s1,36(a2) + bfc: 3331 jal 908 + bfe: 4300 lw s0,0(a4) + c00: 505f5253 .4byte 0x505f5253 + c04: 504d c.li zero,-13 + c06: 4441 li s0,16 + c08: 5244 lw s1,36(a2) + c0a: 3431 jal 616 <__neorv32_rte_debug_handler+0xb2> + c0c: 4300 lw s0,0(a4) + c0e: 4d5f5253 .4byte 0x4d5f5253 + c12: 4e45 li t3,17 + c14: 4356 lw t1,84(sp) + c16: 4746 lw a4,80(sp) + c18: 5200 lw s0,32(a2) + c1a: 4554 lw a3,12(a0) + c1c: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + c22: 454d li a0,19 + c24: 0049 c.nop 18 + c26: 5f525343 .4byte 0x5f525343 + c2a: 4354 lw a3,4(a4) + c2c: 52544e4f .4byte 0x52544e4f + c30: 43004c4f .4byte 0x43004c4f + c34: 4d5f5253 .4byte 0x4d5f5253 + c38: 4549 li a0,18 + c3a: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + c40: 4534 lw a3,72(a0) + c42: 4300 lw s0,0(a4) + c44: 4d5f5253 .4byte 0x4d5f5253 + c48: 5349 li t1,-14 + c4a: 5f41 li t5,-16 + c4c: 584d li a6,-13 + c4e: 5f4c lw a1,60(a4) + c50: 4f4c lw a1,28(a4) + c52: 4300 lw s0,0(a4) + c54: 485f5253 .4byte 0x485f5253 + c58: 4d50 lw a2,28(a0) + c5a: 4e554f43 .4byte 0x4e554f43 + c5e: 4554 lw a3,12(a0) + c60: 3152 .2byte 0x3152 + c62: 4836 lw a6,76(sp) + c64: 4300 lw s0,0(a4) + c66: 4d5f5253 .4byte 0x4d5f5253 + c6a: 5048 lw a0,36(s0) + c6c: 434d li t1,19 + c6e: 544e554f .4byte 0x544e554f + c72: 5245 li tp,-15 + c74: 4836 lw a6,76(sp) + c76: 4300 lw s0,0(a4) + c78: 4d5f5253 .4byte 0x4d5f5253 + c7c: 5048 lw a0,36(s0) + c7e: 434d li t1,19 + c80: 544e554f .4byte 0x544e554f + c84: 5245 li tp,-15 + c86: 53430033 .4byte 0x53430033 + c8a: 5f52 lw t5,52(sp) + c8c: 484d li a6,19 + c8e: 4d50 lw a2,28(a0) + c90: 4e554f43 .4byte 0x4e554f43 + c94: 4554 lw a3,12(a0) + c96: 3452 .2byte 0x3452 + c98: 4300 lw s0,0(a4) + c9a: 4d5f5253 .4byte 0x4d5f5253 + c9e: 5048 lw a0,36(s0) + ca0: 434d li t1,19 + ca2: 544e554f .4byte 0x544e554f + ca6: 5245 li tp,-15 + ca8: 0035 c.nop 13 + caa: 5f525343 .4byte 0x5f525343 + cae: 484d li a6,19 + cb0: 4d50 lw a2,28(a0) + cb2: 4e554f43 .4byte 0x4e554f43 + cb6: 4554 lw a3,12(a0) + cb8: 3652 .2byte 0x3652 + cba: 4300 lw s0,0(a4) + cbc: 4d5f5253 .4byte 0x4d5f5253 + cc0: 5048 lw a0,36(s0) + cc2: 434d li t1,19 + cc4: 544e554f .4byte 0x544e554f + cc8: 5245 li tp,-15 + cca: 53430037 lui zero,0x53430 + cce: 5f52 lw t5,52(sp) + cd0: 484d li a6,19 + cd2: 4d50 lw a2,28(a0) + cd4: 4e554f43 .4byte 0x4e554f43 + cd8: 4554 lw a3,12(a0) + cda: 3852 .2byte 0x3852 + cdc: 4300 lw s0,0(a4) + cde: 4d5f5253 .4byte 0x4d5f5253 + ce2: 5048 lw a0,36(s0) + ce4: 434d li t1,19 + ce6: 544e554f .4byte 0x544e554f + cea: 5245 li tp,-15 + cec: 0039 c.nop 14 + cee: 5f525343 .4byte 0x5f525343 + cf2: 4e4f4353 .4byte 0x4e4f4353 + cf6: 4554 lw a3,12(a0) + cf8: 5458 lw a4,44(s0) + cfa: 4300 lw s0,0(a4) + cfc: 4d5f5253 .4byte 0x4d5f5253 + d00: 4549 li a0,18 + d02: 465f 5249 3151 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x31 + d08: 4535 li a0,13 + d0a: 4300 lw s0,0(a4) + d0c: 4d5f5253 .4byte 0x4d5f5253 + d10: 5654 lw a3,44(a2) + d12: 4345 li t1,17 + d14: 4300 lw s0,0(a4) + d16: 505f5253 .4byte 0x505f5253 + d1a: 504d c.li zero,-13 + d1c: 4441 li s0,16 + d1e: 5244 lw s1,36(a2) + d20: 0039 c.nop 14 + d22: 5f727363 bgeu tp,s7,1308 <_malloc_r+0x4aa> + d26: 6164 .2byte 0x6164 + d28: 6174 .2byte 0x6174 + d2a: 4300 lw s0,0(a4) + d2c: 4d5f5253 .4byte 0x4d5f5253 + d30: 4958 lw a4,20(a0) + d32: 5a5f4153 .4byte 0x5a5f4153 + d36: 4946 lw s2,80(sp) + d38: 584e lw a6,240(sp) + d3a: 6e00 .2byte 0x6e00 + d3c: 6f65 lui t5,0x19 + d3e: 7672 .2byte 0x7672 + d40: 725f3233 .4byte 0x725f3233 + d44: 6574 .2byte 0x6574 + d46: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + d4c: 685f 5f77 6f63 .byte 0x5f, 0x68, 0x77, 0x5f, 0x63, 0x6f + d52: 666e .2byte 0x666e + d54: 6769 lui a4,0x1a + d56: 4e00 lw s0,24(a2) + d58: 4f45 li t5,17 + d5a: 5652 lw a2,52(sp) + d5c: 435f3233 .4byte 0x435f3233 + d60: 4d5f5253 .4byte 0x4d5f5253 + d64: 5349 li t1,-14 + d66: 5f41 li t5,-16 + d68: 6e65 lui t3,0x19 + d6a: 6d75 lui s10,0x1d + d6c: 4300 lw s0,0(a4) + d6e: 4d5f5253 .4byte 0x4d5f5253 + d72: 5048 lw a0,36(s0) + d74: 434d li t1,19 + d76: 544e554f .4byte 0x544e554f + d7a: 5245 li tp,-15 + d7c: 6e004837 lui a6,0x6e004 + d80: 6f65 lui t5,0x19 + d82: 7672 .2byte 0x7672 + d84: 635f3233 .4byte 0x635f3233 + d88: 7570 .2byte 0x7570 + d8a: 685f 6d70 675f .byte 0x5f, 0x68, 0x70, 0x6d, 0x5f, 0x67 + d90: 7465 lui s0,0xffff9 + d92: 6e5f 6d75 635f .byte 0x5f, 0x6e, 0x75, 0x6d, 0x5f, 0x63 + d98: 746e756f jal a0,e84de <__neorv32_ram_size+0xe64de> + d9c: 7265 lui tp,0xffff9 + d9e: 656e0073 .4byte 0x656e0073 + da2: 3376726f jal tp,688d8 <__neorv32_ram_size+0x668d8> + da6: 5f32 lw t5,44(sp) + da8: 7472 .2byte 0x7472 + daa: 5f65 li t5,-7 + dac: 7270 .2byte 0x7270 + dae: 6e69 lui t3,0x1a + db0: 5f74 lw a3,124(a4) + db2: 64657263 bgeu a0,t1,13f6 <_sbrk_r> + db6: 7469 lui s0,0xffffa + db8: 53430073 .4byte 0x53430073 + dbc: 5f52 lw t5,52(sp) + dbe: 5048 lw a0,36(s0) + dc0: 434d li t1,19 + dc2: 544e554f .4byte 0x544e554f + dc6: 5245 li tp,-15 + dc8: 3731 jal cd4 + dca: 0048 addi a0,sp,4 + dcc: 5f5f 6975 746e .byte 0x5f, 0x5f, 0x75, 0x69, 0x6e, 0x74 + dd2: 3631 jal 8de + dd4: 745f 4300 5253 .byte 0x5f, 0x74, 0x00, 0x43, 0x53, 0x52 + dda: 4d5f 5048 434d .byte 0x5f, 0x4d, 0x48, 0x50, 0x4d, 0x43 + de0: 544e554f .4byte 0x544e554f + de4: 5245 li tp,-15 + de6: 4838 lw a4,80(s0) + de8: 4300 lw s0,0(a4) + dea: 4d5f5253 .4byte 0x4d5f5253 + dee: 5241 li tp,-16 + df0: 44494843 .4byte 0x44494843 + df4: 6800 .2byte 0x6800 + df6: 7865 lui a6,0xffff9 + df8: 735f 6d79 6f62 .byte 0x5f, 0x73, 0x79, 0x6d, 0x62, 0x6f + dfe: 736c .2byte 0x736c + e00: 4300 lw s0,0(a4) + e02: 4d5f5253 .4byte 0x4d5f5253 + e06: 4549 li a0,18 + e08: 465f 5249 3051 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x30 + e0e: 0045 c.nop 17 + e10: 49535953 .4byte 0x49535953 + e14: 464e lw a2,208(sp) + e16: 41435f4f .4byte 0x41435f4f + e1a: 5f454843 .4byte 0x5f454843 + e1e: 4349 li t1,18 + e20: 4e5f 4d55 425f .byte 0x5f, 0x4e, 0x55, 0x4d, 0x5f, 0x42 + e26: 4f4c lw a1,28(a4) + e28: 5f534b43 .4byte 0x5f534b43 + e2c: 0031 c.nop 12 + e2e: 5254 lw a3,36(a2) + e30: 5041 c.li zero,-16 + e32: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + e38: 5f49 li t5,-14 + e3a: 494d li s2,19 + e3c: 494c4153 .4byte 0x494c4153 + e40: 44454e47 .4byte 0x44454e47 + e44: 4300 lw s0,0(a4) + e46: 4d5f5253 .4byte 0x4d5f5253 + e4a: 5048 lw a0,36(s0) + e4c: 434d li t1,19 + e4e: 544e554f .4byte 0x544e554f + e52: 5245 li tp,-15 + e54: 4839 li a6,14 + e56: 4300 lw s0,0(a4) + e58: 4d5f5253 .4byte 0x4d5f5253 + e5c: 5349 li t1,-14 + e5e: 5f41 li t5,-16 + e60: 0044 addi s1,sp,4 + e62: 5f525343 .4byte 0x5f525343 + e66: 494d li s2,19 + e68: 5f45 li t5,-15 + e6a: 4946 lw s2,80(sp) + e6c: 5152 lw sp,52(sp) + e6e: 4531 li a0,12 + e70: 4300 lw s0,0(a4) + e72: 4d5f5253 .4byte 0x4d5f5253 + e76: 5349 li t1,-14 + e78: 5f41 li t5,-16 + e7a: 0045 c.nop 17 + e7c: 656e .2byte 0x656e + e7e: 3376726f jal tp,689b4 <__neorv32_ram_size+0x669b4> + e82: 5f32 lw t5,44(sp) + e84: 6175 addi sp,sp,368 + e86: 7472 .2byte 0x7472 + e88: 5f30 lw a2,120(a4) + e8a: 7661 lui a2,0xffff8 + e8c: 6961 lui s2,0x18 + e8e: 616c .2byte 0x616c + e90: 6c62 .2byte 0x6c62 + e92: 0065 c.nop 25 + e94: 5f525343 .4byte 0x5f525343 + e98: 494d li s2,19 + e9a: 465f4153 .4byte 0x465f4153 + e9e: 4300 lw s0,0(a4) + ea0: 4d5f5253 .4byte 0x4d5f5253 + ea4: 4958 lw a4,20(a0) + ea6: 5a5f4153 .4byte 0x5a5f4153 + eaa: 4649 li a2,18 + eac: 4e45 li t3,17 + eae: 00494543 .4byte 0x494543 + eb2: 5f525343 .4byte 0x5f525343 + eb6: 494d li s2,19 + eb8: 495f4153 .4byte 0x495f4153 + ebc: 6e00 .2byte 0x6e00 + ebe: 6f65 lui t5,0x19 + ec0: 7672 .2byte 0x7672 + ec2: 635f3233 .4byte 0x635f3233 + ec6: 7570 .2byte 0x7570 + ec8: 685f 6d70 675f .byte 0x5f, 0x68, 0x70, 0x6d, 0x5f, 0x67 + ece: 7465 lui s0,0xffff9 + ed0: 735f 7a69 0065 .byte 0x5f, 0x73, 0x69, 0x7a, 0x65, 0x00 + ed6: 5f525343 .4byte 0x5f525343 + eda: 494d li s2,19 + edc: 4d5f4153 .4byte 0x4d5f4153 + ee0: 5f00 lw s0,56(a4) + ee2: 6e5f 6f65 7672 .byte 0x5f, 0x6e, 0x65, 0x6f, 0x72, 0x76 + ee8: 725f3233 .4byte 0x725f3233 + eec: 6574 .2byte 0x6574 + eee: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + ef4: 635f 6568 6b63 .byte 0x5f, 0x63, 0x68, 0x65, 0x63, 0x6b + efa: 6f62 .2byte 0x6f62 + efc: 0078 addi a4,sp,12 + efe: 5f525343 .4byte 0x5f525343 + f02: 434d li t1,19 + f04: 544e554f .4byte 0x544e554f + f08: 5245 li tp,-15 + f0a: 4e45 li t3,17 + f0c: 5f00 lw s0,56(a4) + f0e: 6e5f 6f65 7672 .byte 0x5f, 0x6e, 0x65, 0x6f, 0x72, 0x76 + f14: 725f3233 .4byte 0x725f3233 + f18: 6574 .2byte 0x6574 + f1a: 635f 726f 0065 .byte 0x5f, 0x63, 0x6f, 0x72, 0x65, 0x00 + f20: 5f525343 .4byte 0x5f525343 + f24: 564d li a2,-13 + f26: 4e45 li t3,17 + f28: 4f44 lw s1,28(a4) + f2a: 4952 lw s2,20(sp) + f2c: 0044 addi s1,sp,4 + f2e: 5254 lw a3,36(a2) + f30: 5041 c.li zero,-16 + f32: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + f38: 4946 lw s2,80(sp) + f3a: 5152 lw sp,52(sp) + f3c: 305f 5400 4152 .byte 0x5f, 0x30, 0x00, 0x54, 0x52, 0x41 + f42: 5f50 lw a2,60(a4) + f44: 45444f43 .4byte 0x45444f43 + f48: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + f4e: 0031 c.nop 12 + f50: 5254 lw a3,36(a2) + f52: 5041 c.li zero,-16 + f54: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + f5a: 4946 lw s2,80(sp) + f5c: 5152 lw sp,52(sp) + f5e: 325f 5400 4152 .byte 0x5f, 0x32, 0x00, 0x54, 0x52, 0x41 + f64: 5f50 lw a2,60(a4) + f66: 45444f43 .4byte 0x45444f43 + f6a: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + f70: 52540033 .4byte 0x52540033 + f74: 5041 c.li zero,-16 + f76: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + f7c: 4946 lw s2,80(sp) + f7e: 5152 lw sp,52(sp) + f80: 345f 5400 4152 .byte 0x5f, 0x34, 0x00, 0x54, 0x52, 0x41 + f86: 5f50 lw a2,60(a4) + f88: 45444f43 .4byte 0x45444f43 + f8c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + f92: 0035 c.nop 13 + f94: 5254 lw a3,36(a2) + f96: 5041 c.li zero,-16 + f98: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + f9e: 4946 lw s2,80(sp) + fa0: 5152 lw sp,52(sp) + fa2: 365f 5400 4152 .byte 0x5f, 0x36, 0x00, 0x54, 0x52, 0x41 + fa8: 5f50 lw a2,60(a4) + faa: 45444f43 .4byte 0x45444f43 + fae: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + fb4: 53430037 lui zero,0x53430 + fb8: 5f52 lw t5,52(sp) + fba: 494d li s2,19 + fbc: 5f45 li t5,-15 + fbe: 4946 lw s2,80(sp) + fc0: 5152 lw sp,52(sp) + fc2: 4532 lw a0,12(sp) + fc4: 4e00 lw s0,24(a2) + fc6: 4f45 li t5,17 + fc8: 5652 lw a2,52(sp) + fca: 435f3233 .4byte 0x435f3233 + fce: 655f5253 .4byte 0x655f5253 + fd2: 756e .2byte 0x756e + fd4: 006d c.nop 27 + fd6: 5254 lw a3,36(a2) + fd8: 5041 c.li zero,-16 + fda: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + fe0: 43415f53 .4byte 0x43415f53 + fe4: 53534543 .4byte 0x53534543 + fe8: 6900 .2byte 0x6900 + fea: 646e .2byte 0x646e + fec: 7865 lui a6,0xffff9 + fee: 7200 .2byte 0x7200 + ff0: 6574 .2byte 0x6574 + ff2: 745f 6172 5f70 .byte 0x5f, 0x74, 0x72, 0x61, 0x70, 0x5f + ff8: 6e69 lui t3,0x1a + ffa: 43007473 csrrci s0,0x430,0 + ffe: 4d5f5253 .4byte 0x4d5f5253 + 1002: 4e45 li t3,17 + 1004: 4356 lw t1,84(sp) + 1006: 4746 lw a4,80(sp) + 1008: 0048 addi a0,sp,4 + 100a: 5f525343 .4byte 0x5f525343 + 100e: 494d li s2,19 + 1010: 5f45 li t5,-15 + 1012: 4946 lw s2,80(sp) + 1014: 5152 lw sp,52(sp) + 1016: 5f004533 .4byte 0x5f004533 + 101a: 6e5f 6f65 7672 .byte 0x5f, 0x6e, 0x65, 0x6f, 0x72, 0x76 + 1020: 725f3233 .4byte 0x725f3233 + 1024: 6574 .2byte 0x6574 + 1026: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 102c: 685f 7865 775f .byte 0x5f, 0x68, 0x65, 0x78, 0x5f, 0x77 + 1032: 0064726f jal tp,48038 <__neorv32_ram_size+0x46038> + 1036: 6168 .2byte 0x6168 + 1038: 646e .2byte 0x646e + 103a: 656c .2byte 0x656c + 103c: 5f72 lw t5,60(sp) + 103e: 6e70 .2byte 0x6e70 + 1040: 0074 addi a3,sp,12 + 1042: 5f525343 .4byte 0x5f525343 + 1046: 494d li s2,19 + 1048: 415f4153 .4byte 0x415f4153 + 104c: 4300 lw s0,0(a4) + 104e: 4d5f5253 .4byte 0x4d5f5253 + 1052: 5349 li t1,-14 + 1054: 5f41 li t5,-16 + 1056: 0042 c.slli zero,0x10 + 1058: 5f525343 .4byte 0x5f525343 + 105c: 494d li s2,19 + 105e: 435f4153 .4byte 0x435f4153 + 1062: 4300 lw s0,0(a4) + 1064: 4d5f5253 .4byte 0x4d5f5253 + 1068: 5048 lw a0,36(s0) + 106a: 454d li a0,19 + 106c: 4556 lw a0,84(sp) + 106e: 544e lw s0,240(sp) + 1070: 3031 jal 87c + 1072: 4300 lw s0,0(a4) + 1074: 4d5f5253 .4byte 0x4d5f5253 + 1078: 5048 lw a0,36(s0) + 107a: 454d li a0,19 + 107c: 4556 lw a0,84(sp) + 107e: 544e lw s0,240(sp) + 1080: 3131 jal c8c + 1082: 4300 lw s0,0(a4) + 1084: 4d5f5253 .4byte 0x4d5f5253 + 1088: 5048 lw a0,36(s0) + 108a: 454d li a0,19 + 108c: 4556 lw a0,84(sp) + 108e: 544e lw s0,240(sp) + 1090: 3231 jal 99c <__neorv32_uart_itoa+0x74> + 1092: 4300 lw s0,0(a4) + 1094: 4d5f5253 .4byte 0x4d5f5253 + 1098: 5048 lw a0,36(s0) + 109a: 454d li a0,19 + 109c: 4556 lw a0,84(sp) + 109e: 544e lw s0,240(sp) + 10a0: 3331 jal dac <_sbrk+0x10> + 10a2: 4300 lw s0,0(a4) + 10a4: 4d5f5253 .4byte 0x4d5f5253 + 10a8: 5048 lw a0,36(s0) + 10aa: 454d li a0,19 + 10ac: 4556 lw a0,84(sp) + 10ae: 544e lw s0,240(sp) + 10b0: 3431 jal abc + 10b2: 4300 lw s0,0(a4) + 10b4: 4d5f5253 .4byte 0x4d5f5253 + 10b8: 5048 lw a0,36(s0) + 10ba: 454d li a0,19 + 10bc: 4556 lw a0,84(sp) + 10be: 544e lw s0,240(sp) + 10c0: 3531 jal ecc <_malloc_r+0x6e> + 10c2: 4300 lw s0,0(a4) + 10c4: 4d5f5253 .4byte 0x4d5f5253 + 10c8: 5048 lw a0,36(s0) + 10ca: 454d li a0,19 + 10cc: 4556 lw a0,84(sp) + 10ce: 544e lw s0,240(sp) + 10d0: 3631 jal bdc + 10d2: 4300 lw s0,0(a4) + 10d4: 4d5f5253 .4byte 0x4d5f5253 + 10d8: 5048 lw a0,36(s0) + 10da: 454d li a0,19 + 10dc: 4556 lw a0,84(sp) + 10de: 544e lw s0,240(sp) + 10e0: 3731 jal fec <_malloc_r+0x18e> + 10e2: 4300 lw s0,0(a4) + 10e4: 4d5f5253 .4byte 0x4d5f5253 + 10e8: 5048 lw a0,36(s0) + 10ea: 454d li a0,19 + 10ec: 4556 lw a0,84(sp) + 10ee: 544e lw s0,240(sp) + 10f0: 3831 jal 90c + 10f2: 4300 lw s0,0(a4) + 10f4: 4d5f5253 .4byte 0x4d5f5253 + 10f8: 5048 lw a0,36(s0) + 10fa: 454d li a0,19 + 10fc: 4556 lw a0,84(sp) + 10fe: 544e lw s0,240(sp) + 1100: 3931 jal d1c + 1102: 6e00 .2byte 0x6e00 + 1104: 6f65 lui t5,0x19 + 1106: 7672 .2byte 0x7672 + 1108: 635f3233 .4byte 0x635f3233 + 110c: 7570 .2byte 0x7570 + 110e: 635f 7273 725f .byte 0x5f, 0x63, 0x73, 0x72, 0x5f, 0x72 + 1114: 6165 addi sp,sp,112 + 1116: 0064 addi s1,sp,12 + 1118: 5f525343 .4byte 0x5f525343 + 111c: 494d li s2,19 + 111e: 555f4153 .4byte 0x555f4153 + 1122: 5200 lw s0,32(a2) + 1124: 4554 lw a3,12(a0) + 1126: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 112c: 5242 lw tp,48(sp) + 112e: 4145 li sp,17 + 1130: 494f504b .4byte 0x494f504b + 1134: 544e lw s0,240(sp) + 1136: 4300 lw s0,0(a4) + 1138: 4d5f5253 .4byte 0x4d5f5253 + 113c: 5349 li t1,-14 + 113e: 5f41 li t5,-16 + 1140: 0058 addi a4,sp,4 + 1142: 656c6973 csrrsi s2,0x656,24 + 1146: 746e .2byte 0x746e + 1148: 4300 lw s0,0(a4) + 114a: 4d5f5253 .4byte 0x4d5f5253 + 114e: 4549 li a0,18 + 1150: 465f 5249 3451 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x34 + 1156: 0045 c.nop 17 + 1158: 5f525343 .4byte 0x5f525343 + 115c: 5354 lw a3,36(a4) + 115e: 4c45 li s8,17 + 1160: 4345 li t1,17 + 1162: 0054 addi a3,sp,4 + 1164: 5f525343 .4byte 0x5f525343 + 1168: 434d li t1,19 + 116a: 4359 li t1,22 + 116c: 454c lw a1,12(a0) + 116e: 0048 addi a0,sp,4 + 1170: 5f525343 .4byte 0x5f525343 + 1174: 484d li a6,19 + 1176: 4d50 lw a2,28(a0) + 1178: 5645 li a2,-15 + 117a: 4e45 li t3,17 + 117c: 3254 .2byte 0x3254 + 117e: 0030 addi a2,sp,8 + 1180: 5f525343 .4byte 0x5f525343 + 1184: 484d li a6,19 + 1186: 4d50 lw a2,28(a0) + 1188: 5645 li a2,-15 + 118a: 4e45 li t3,17 + 118c: 3254 .2byte 0x3254 + 118e: 0031 c.nop 12 + 1190: 5f525343 .4byte 0x5f525343 + 1194: 484d li a6,19 + 1196: 4d50 lw a2,28(a0) + 1198: 5645 li a2,-15 + 119a: 4e45 li t3,17 + 119c: 3254 .2byte 0x3254 + 119e: 0032 c.slli zero,0xc + 11a0: 5f525343 .4byte 0x5f525343 + 11a4: 484d li a6,19 + 11a6: 4d50 lw a2,28(a0) + 11a8: 5645 li a2,-15 + 11aa: 4e45 li t3,17 + 11ac: 3254 .2byte 0x3254 + 11ae: 53430033 .4byte 0x53430033 + 11b2: 5f52 lw t5,52(sp) + 11b4: 484d li a6,19 + 11b6: 4d50 lw a2,28(a0) + 11b8: 5645 li a2,-15 + 11ba: 4e45 li t3,17 + 11bc: 3254 .2byte 0x3254 + 11be: 0034 addi a3,sp,8 + 11c0: 5f525343 .4byte 0x5f525343 + 11c4: 484d li a6,19 + 11c6: 4d50 lw a2,28(a0) + 11c8: 5645 li a2,-15 + 11ca: 4e45 li t3,17 + 11cc: 3254 .2byte 0x3254 + 11ce: 0035 c.nop 13 + 11d0: 5f525343 .4byte 0x5f525343 + 11d4: 484d li a6,19 + 11d6: 4d50 lw a2,28(a0) + 11d8: 5645 li a2,-15 + 11da: 4e45 li t3,17 + 11dc: 3254 .2byte 0x3254 + 11de: 0036 c.slli zero,0xd + 11e0: 5f525343 .4byte 0x5f525343 + 11e4: 484d li a6,19 + 11e6: 4d50 lw a2,28(a0) + 11e8: 5645 li a2,-15 + 11ea: 4e45 li t3,17 + 11ec: 3254 .2byte 0x3254 + 11ee: 53430037 lui zero,0x53430 + 11f2: 5f52 lw t5,52(sp) + 11f4: 484d li a6,19 + 11f6: 4d50 lw a2,28(a0) + 11f8: 5645 li a2,-15 + 11fa: 4e45 li t3,17 + 11fc: 3254 .2byte 0x3254 + 11fe: 0038 addi a4,sp,8 + 1200: 5f525343 .4byte 0x5f525343 + 1204: 484d li a6,19 + 1206: 4d50 lw a2,28(a0) + 1208: 5645 li a2,-15 + 120a: 4e45 li t3,17 + 120c: 3254 .2byte 0x3254 + 120e: 0039 c.nop 14 + 1210: 5254 lw a3,36(a2) + 1212: 5041 c.li zero,-16 + 1214: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 121a: 534d li t1,-13 + 121c: 0049 c.nop 18 + 121e: 5254 lw a3,36(a2) + 1220: 5041 c.li zero,-16 + 1222: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 1228: 454d li a0,19 + 122a: 0049 c.nop 18 + 122c: 5f525343 .4byte 0x5f525343 + 1230: 584d li a6,-13 + 1232: 5349 li t1,-14 + 1234: 5f41 li t5,-16 + 1236: 4146 lw sp,80(sp) + 1238: 48535453 .4byte 0x48535453 + 123c: 4649 li a2,18 + 123e: 0054 addi a3,sp,4 + 1240: 5f525343 .4byte 0x5f525343 + 1244: 494d li s2,19 + 1246: 5f45 li t5,-15 + 1248: 4946 lw s2,80(sp) + 124a: 5152 lw sp,52(sp) + 124c: 4535 li a0,13 + 124e: 5300 lw s0,32(a4) + 1250: 5359 li t1,-10 + 1252: 4e49 li t3,18 + 1254: 4f46 lw t5,80(sp) + 1256: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 125c: 495f 5f43 4c42 .byte 0x5f, 0x49, 0x43, 0x5f, 0x42, 0x4c + 1262: 5f4b434f .4byte 0x5f4b434f + 1266: 455a4953 .4byte 0x455a4953 + 126a: 305f 5300 5359 .byte 0x5f, 0x30, 0x00, 0x53, 0x59, 0x53 + 1270: 4e49 li t3,18 + 1272: 4f46 lw t5,80(sp) + 1274: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 127a: 495f 5f43 4c42 .byte 0x5f, 0x49, 0x43, 0x5f, 0x42, 0x4c + 1280: 5f4b434f .4byte 0x5f4b434f + 1284: 455a4953 .4byte 0x455a4953 + 1288: 315f 5300 5359 .byte 0x5f, 0x31, 0x00, 0x53, 0x59, 0x53 + 128e: 4e49 li t3,18 + 1290: 4f46 lw t5,80(sp) + 1292: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 1298: 495f 5f43 4c42 .byte 0x5f, 0x49, 0x43, 0x5f, 0x42, 0x4c + 129e: 5f4b434f .4byte 0x5f4b434f + 12a2: 455a4953 .4byte 0x455a4953 + 12a6: 325f 5300 5359 .byte 0x5f, 0x32, 0x00, 0x53, 0x59, 0x53 + 12ac: 4e49 li t3,18 + 12ae: 4f46 lw t5,80(sp) + 12b0: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 12b6: 495f 5f43 4c42 .byte 0x5f, 0x49, 0x43, 0x5f, 0x42, 0x4c + 12bc: 5f4b434f .4byte 0x5f4b434f + 12c0: 455a4953 .4byte 0x455a4953 + 12c4: 335f 5200 4554 .byte 0x5f, 0x33, 0x00, 0x52, 0x54, 0x45 + 12ca: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 12d0: 494d5f53 .4byte 0x494d5f53 + 12d4: 494c4153 .4byte 0x494c4153 + 12d8: 44454e47 .4byte 0x44454e47 + 12dc: 4300 lw s0,0(a4) + 12de: 4d5f5253 .4byte 0x4d5f5253 + 12e2: 5048 lw a0,36(s0) + 12e4: 454d li a0,19 + 12e6: 4556 lw a0,84(sp) + 12e8: 544e lw s0,240(sp) + 12ea: 43003033 .4byte 0x43003033 + 12ee: 4d5f5253 .4byte 0x4d5f5253 + 12f2: 5048 lw a0,36(s0) + 12f4: 454d li a0,19 + 12f6: 4556 lw a0,84(sp) + 12f8: 544e lw s0,240(sp) + 12fa: 69003133 .4byte 0x69003133 + 12fe: 73615f63 bge sp,s6,1a3c <__fini_array_end+0x31c> + 1302: 69636f73 csrrsi t5,0x696,6 + 1306: 7461 lui s0,0xffff8 + 1308: 7669 lui a2,0xffffa + 130a: 7469 lui s0,0xffffa + 130c: 0079 c.nop 30 + 130e: 6572 .2byte 0x6572 + 1310: 64615f67 .4byte 0x64615f67 + 1314: 7264 .2byte 0x7264 + 1316: 4300 lw s0,0(a4) + 1318: 4d5f5253 .4byte 0x4d5f5253 + 131c: 4549 li a0,18 + 131e: 465f 5249 3651 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x36 + 1324: 0045 c.nop 17 + 1326: 7068 .2byte 0x7068 + 1328: 5f6d li t5,-5 + 132a: 756e .2byte 0x756e + 132c: 006d c.nop 27 + 132e: 5f525343 .4byte 0x5f525343 + 1332: 494d li s2,19 + 1334: 5f45 li t5,-15 + 1336: 4946 lw s2,80(sp) + 1338: 5152 lw sp,52(sp) + 133a: 5f004537 lui a0,0x5f004 + 133e: 6d5f 6c75 6973 .byte 0x5f, 0x6d, 0x75, 0x6c, 0x73, 0x69 + 1344: 454e0033 .4byte 0x454e0033 + 1348: 3356524f .4byte 0x3356524f + 134c: 5f32 lw t5,44(sp) + 134e: 5542 lw a0,48(sp) + 1350: 45454b53 .4byte 0x45454b53 + 1354: 4550 lw a2,12(a0) + 1356: 5f52 lw t5,52(sp) + 1358: 4c525443 .4byte 0x4c525443 + 135c: 655f 756e 006d .byte 0x5f, 0x65, 0x6e, 0x75, 0x6d, 0x00 + 1362: 5f525343 .4byte 0x5f525343 + 1366: 484d li a6,19 + 1368: 4d50 lw a2,28(a0) + 136a: 5645 li a2,-15 + 136c: 4e45 li t3,17 + 136e: 3354 .2byte 0x3354 + 1370: 4300 lw s0,0(a4) + 1372: 4d5f5253 .4byte 0x4d5f5253 + 1376: 5048 lw a0,36(s0) + 1378: 454d li a0,19 + 137a: 4556 lw a0,84(sp) + 137c: 544e lw s0,240(sp) + 137e: 0034 addi a3,sp,8 + 1380: 5f525343 .4byte 0x5f525343 + 1384: 484d li a6,19 + 1386: 4d50 lw a2,28(a0) + 1388: 5645 li a2,-15 + 138a: 4e45 li t3,17 + 138c: 3554 .2byte 0x3554 + 138e: 4300 lw s0,0(a4) + 1390: 4d5f5253 .4byte 0x4d5f5253 + 1394: 5048 lw a0,36(s0) + 1396: 454d li a0,19 + 1398: 4556 lw a0,84(sp) + 139a: 544e lw s0,240(sp) + 139c: 0036 c.slli zero,0xd + 139e: 5f525343 .4byte 0x5f525343 + 13a2: 484d li a6,19 + 13a4: 4d50 lw a2,28(a0) + 13a6: 5645 li a2,-15 + 13a8: 4e45 li t3,17 + 13aa: 3754 .2byte 0x3754 + 13ac: 4300 lw s0,0(a4) + 13ae: 4d5f5253 .4byte 0x4d5f5253 + 13b2: 5048 lw a0,36(s0) + 13b4: 454d li a0,19 + 13b6: 4556 lw a0,84(sp) + 13b8: 544e lw s0,240(sp) + 13ba: 0038 addi a4,sp,8 + 13bc: 5f525343 .4byte 0x5f525343 + 13c0: 484d li a6,19 + 13c2: 4d50 lw a2,28(a0) + 13c4: 5645 li a2,-15 + 13c6: 4e45 li t3,17 + 13c8: 3954 .2byte 0x3954 + 13ca: 4300 lw s0,0(a4) + 13cc: 5254 lw a3,36(a2) + 13ce: 004c addi a1,sp,4 + 13d0: 5f525343 .4byte 0x5f525343 + 13d4: 5044 lw s1,36(s0) + 13d6: 53430043 .4byte 0x53430043 + 13da: 5f52 lw t5,52(sp) + 13dc: 494d li s2,19 + 13de: 5f45 li t5,-15 + 13e0: 4946 lw s2,80(sp) + 13e2: 5152 lw sp,52(sp) + 13e4: 4538 lw a4,72(a0) + 13e6: 4300 lw s0,0(a4) + 13e8: 4d5f5253 .4byte 0x4d5f5253 + 13ec: 5048 lw a0,36(s0) + 13ee: 434d li t1,19 + 13f0: 544e554f .4byte 0x544e554f + 13f4: 5245 li tp,-15 + 13f6: 3332 .2byte 0x3332 + 13f8: 0048 addi a0,sp,4 + 13fa: 656e .2byte 0x656e + 13fc: 3376726f jal tp,68f32 <__neorv32_ram_size+0x66f32> + 1400: 5f32 lw t5,44(sp) + 1402: 6175 addi sp,sp,368 + 1404: 7472 .2byte 0x7472 + 1406: 5f30 lw a2,120(a4) + 1408: 7570 .2byte 0x7570 + 140a: 6374 .2byte 0x6374 + 140c: 4300 lw s0,0(a4) + 140e: 505f5253 .4byte 0x505f5253 + 1412: 504d c.li zero,-13 + 1414: 4441 li s0,16 + 1416: 5244 lw s1,36(a2) + 1418: 3531 jal 1224 <_malloc_r+0x3c6> + 141a: 5400 lw s0,40(s0) + 141c: 4152 lw sp,20(sp) + 141e: 5f50 lw a2,60(a4) + 1420: 45444f43 .4byte 0x45444f43 + 1424: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 142a: 0038 addi a4,sp,8 + 142c: 5254 lw a3,36(a2) + 142e: 5041 c.li zero,-16 + 1430: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 1436: 4946 lw s2,80(sp) + 1438: 5152 lw sp,52(sp) + 143a: 395f 6900 5f63 .byte 0x5f, 0x39, 0x00, 0x69, 0x63, 0x5f + 1440: 756e .2byte 0x756e + 1442: 5f6d li t5,-5 + 1444: 6c62 .2byte 0x6c62 + 1446: 736b636f jal t1,b7b7c <__neorv32_ram_size+0xb5b7c> + 144a: 4300 lw s0,0(a4) + 144c: 4d5f5253 .4byte 0x4d5f5253 + 1450: 5048 lw a0,36(s0) + 1452: 434d li t1,19 + 1454: 544e554f .4byte 0x544e554f + 1458: 5245 li tp,-15 + 145a: 4835 li a6,13 + 145c: 6d00 .2byte 0x6d00 + 145e: 7369 lui t1,0xffffa + 1460: 5f61 li t5,-8 + 1462: 7768 .2byte 0x7768 + 1464: 6e00 .2byte 0x6e00 + 1466: 6f65 lui t5,0x19 + 1468: 7672 .2byte 0x7672 + 146a: 725f3233 .4byte 0x725f3233 + 146e: 6574 .2byte 0x6574 + 1470: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 1476: 685f 5f77 6576 .byte 0x5f, 0x68, 0x77, 0x5f, 0x76, 0x65 + 147c: 7372 .2byte 0x7372 + 147e: 6f69 lui t5,0x1a + 1480: 006e c.slli zero,0x1b + 1482: 5f525343 .4byte 0x5f525343 + 1486: 494d li s2,19 + 1488: 5f45 li t5,-15 + 148a: 4946 lw s2,80(sp) + 148c: 5152 lw sp,52(sp) + 148e: 4539 li a0,14 + 1490: 5f00 lw s0,56(a4) + 1492: 6e5f 6f65 7672 .byte 0x5f, 0x6e, 0x65, 0x6f, 0x72, 0x76 + 1498: 725f3233 .4byte 0x725f3233 + 149c: 6574 .2byte 0x6574 + 149e: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 14a4: 745f 7572 5f65 .byte 0x5f, 0x74, 0x72, 0x75, 0x65, 0x5f + 14aa: 6166 .2byte 0x6166 + 14ac: 736c .2byte 0x736c + 14ae: 0065 c.nop 25 + 14b0: 5254 lw a3,36(a2) + 14b2: 5041 c.li zero,-16 + 14b4: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 14ba: 5f49 li t5,-14 + 14bc: 4c49 li s8,18 + 14be: 454c lw a1,12(a0) + 14c0: 004c4147 .4byte 0x4c4147 + 14c4: 5f525343 .4byte 0x5f525343 + 14c8: 4646 lw a2,80(sp) + 14ca: 414c lw a1,4(a0) + 14cc: 6e005347 .4byte 0x6e005347 + 14d0: 6f65 lui t5,0x19 + 14d2: 7672 .2byte 0x7672 + 14d4: 635f3233 .4byte 0x635f3233 + 14d8: 7570 .2byte 0x7570 + 14da: 705f 706d 675f .byte 0x5f, 0x70, 0x6d, 0x70, 0x5f, 0x67 + 14e0: 7465 lui s0,0xffff9 + 14e2: 675f 6172 756e .byte 0x5f, 0x67, 0x72, 0x61, 0x6e, 0x75 + 14e8: 616c .2byte 0x616c + 14ea: 6972 .2byte 0x6972 + 14ec: 7974 .2byte 0x7974 + 14ee: 5400 lw s0,40(s0) + 14f0: 4152 lw sp,20(sp) + 14f2: 5f50 lw a2,60(a4) + 14f4: 45444f43 .4byte 0x45444f43 + 14f8: 4c5f 415f 4343 .byte 0x5f, 0x4c, 0x5f, 0x41, 0x43, 0x43 + 14fe: 5345 li t1,-15 + 1500: 53430053 .4byte 0x53430053 + 1504: 5f52 lw t5,52(sp) + 1506: 584d li a6,-13 + 1508: 5349 li t1,-14 + 150a: 5f41 li t5,-16 + 150c: 52544453 .4byte 0x52544453 + 1510: 4749 li a4,18 + 1512: 5300 lw s0,32(a4) + 1514: 5359 li t1,-10 + 1516: 4e49 li t3,18 + 1518: 4f46 lw t5,80(sp) + 151a: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 1520: 495f 5f43 4552 .byte 0x5f, 0x49, 0x43, 0x5f, 0x52, 0x45 + 1526: 4c50 lw a2,28(s0) + 1528: 4341 li t1,16 + 152a: 4d45 li s10,17 + 152c: 4e45 li t3,17 + 152e: 5f54 lw a3,60(a4) + 1530: 0030 addi a2,sp,8 + 1532: 49535953 .4byte 0x49535953 + 1536: 464e lw a2,208(sp) + 1538: 41435f4f .4byte 0x41435f4f + 153c: 5f454843 .4byte 0x5f454843 + 1540: 4349 li t1,18 + 1542: 525f 5045 414c .byte 0x5f, 0x52, 0x45, 0x50, 0x4c, 0x41 + 1548: 454d4543 .4byte 0x454d4543 + 154c: 544e lw s0,240(sp) + 154e: 315f 5300 5359 .byte 0x5f, 0x31, 0x00, 0x53, 0x59, 0x53 + 1554: 4e49 li t3,18 + 1556: 4f46 lw t5,80(sp) + 1558: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 155e: 495f 5f43 4552 .byte 0x5f, 0x49, 0x43, 0x5f, 0x52, 0x45 + 1564: 4c50 lw a2,28(s0) + 1566: 4341 li t1,16 + 1568: 4d45 li s10,17 + 156a: 4e45 li t3,17 + 156c: 5f54 lw a3,60(a4) + 156e: 0032 c.slli zero,0xc + 1570: 49535953 .4byte 0x49535953 + 1574: 464e lw a2,208(sp) + 1576: 41435f4f .4byte 0x41435f4f + 157a: 5f454843 .4byte 0x5f454843 + 157e: 4349 li t1,18 + 1580: 525f 5045 414c .byte 0x5f, 0x52, 0x45, 0x50, 0x4c, 0x41 + 1586: 454d4543 .4byte 0x454d4543 + 158a: 544e lw s0,240(sp) + 158c: 335f 4300 5253 .byte 0x5f, 0x33, 0x00, 0x43, 0x53, 0x52 + 1592: 4d5f 4958 4153 .byte 0x5f, 0x4d, 0x58, 0x49, 0x53, 0x41 + 1598: 5a5f 4849 4d50 .byte 0x5f, 0x5a, 0x49, 0x48, 0x50, 0x4d + 159e: 5f00 lw s0,56(a4) + 15a0: 6e5f 6f65 7672 .byte 0x5f, 0x6e, 0x65, 0x6f, 0x72, 0x76 + 15a6: 725f3233 .4byte 0x725f3233 + 15aa: 6574 .2byte 0x6574 + 15ac: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 15b2: 685f 7865 685f .byte 0x5f, 0x68, 0x65, 0x78, 0x5f, 0x68 + 15b8: 6c61 lui s8,0x18 + 15ba: 0066 c.slli zero,0x19 + 15bc: 5254 lw a3,36(a2) + 15be: 5041 c.li zero,-16 + 15c0: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 15c6: 4555 li a0,21 + 15c8: 564e lw a2,240(sp) + 15ca: 435f 4c41 004c .byte 0x5f, 0x43, 0x41, 0x4c, 0x4c, 0x00 + 15d0: 49535953 .4byte 0x49535953 + 15d4: 464e lw a2,208(sp) + 15d6: 41435f4f .4byte 0x41435f4f + 15da: 5f454843 .4byte 0x5f454843 + 15de: 4349 li t1,18 + 15e0: 415f 5353 434f .byte 0x5f, 0x41, 0x53, 0x53, 0x4f, 0x43 + 15e6: 4149 li sp,18 + 15e8: 4954 lw a3,20(a0) + 15ea: 4956 lw s2,84(sp) + 15ec: 5954 lw a3,52(a0) + 15ee: 305f 5300 5359 .byte 0x5f, 0x30, 0x00, 0x53, 0x59, 0x53 + 15f4: 4e49 li t3,18 + 15f6: 4f46 lw t5,80(sp) + 15f8: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 15fe: 495f 5f43 5341 .byte 0x5f, 0x49, 0x43, 0x5f, 0x41, 0x53 + 1604: 49434f53 .4byte 0x49434f53 + 1608: 5441 li s0,-16 + 160a: 5649 li a2,-14 + 160c: 5449 li s0,-14 + 160e: 5f59 li t5,-10 + 1610: 0031 c.nop 12 + 1612: 49535953 .4byte 0x49535953 + 1616: 464e lw a2,208(sp) + 1618: 41435f4f .4byte 0x41435f4f + 161c: 5f454843 .4byte 0x5f454843 + 1620: 4349 li t1,18 + 1622: 415f 5353 434f .byte 0x5f, 0x41, 0x53, 0x53, 0x4f, 0x43 + 1628: 4149 li sp,18 + 162a: 4954 lw a3,20(a0) + 162c: 4956 lw s2,84(sp) + 162e: 5954 lw a3,52(a0) + 1630: 325f 4300 5253 .byte 0x5f, 0x32, 0x00, 0x43, 0x53, 0x52 + 1636: 4d5f 4353 4152 .byte 0x5f, 0x4d, 0x53, 0x43, 0x52, 0x41 + 163c: 4354 lw a3,4(a4) + 163e: 0048 addi a0,sp,4 + 1640: 5f525343 .4byte 0x5f525343 + 1644: 5048 lw a0,36(s0) + 1646: 434d li t1,19 + 1648: 544e554f .4byte 0x544e554f + 164c: 5245 li tp,-15 + 164e: 53430033 .4byte 0x53430033 + 1652: 5f52 lw t5,52(sp) + 1654: 5048 lw a0,36(s0) + 1656: 434d li t1,19 + 1658: 544e554f .4byte 0x544e554f + 165c: 5245 li tp,-15 + 165e: 0034 addi a3,sp,8 + 1660: 5f525343 .4byte 0x5f525343 + 1664: 5048 lw a0,36(s0) + 1666: 434d li t1,19 + 1668: 544e554f .4byte 0x544e554f + 166c: 5245 li tp,-15 + 166e: 0035 c.nop 13 + 1670: 5f525343 .4byte 0x5f525343 + 1674: 5048 lw a0,36(s0) + 1676: 434d li t1,19 + 1678: 544e554f .4byte 0x544e554f + 167c: 5245 li tp,-15 + 167e: 0036 c.slli zero,0xd + 1680: 5f525343 .4byte 0x5f525343 + 1684: 5048 lw a0,36(s0) + 1686: 434d li t1,19 + 1688: 544e554f .4byte 0x544e554f + 168c: 5245 li tp,-15 + 168e: 53430037 lui zero,0x53430 + 1692: 5f52 lw t5,52(sp) + 1694: 5048 lw a0,36(s0) + 1696: 434d li t1,19 + 1698: 544e554f .4byte 0x544e554f + 169c: 5245 li tp,-15 + 169e: 0038 addi a4,sp,8 + 16a0: 5f525343 .4byte 0x5f525343 + 16a4: 5048 lw a0,36(s0) + 16a6: 434d li t1,19 + 16a8: 544e554f .4byte 0x544e554f + 16ac: 5245 li tp,-15 + 16ae: 0039 c.nop 14 + 16b0: 5f525343 .4byte 0x5f525343 + 16b4: 484d li a6,19 + 16b6: 4d50 lw a2,28(a0) + 16b8: 4e554f43 .4byte 0x4e554f43 + 16bc: 4554 lw a3,12(a0) + 16be: 3152 .2byte 0x3152 + 16c0: 4830 lw a2,80(s0) + 16c2: 4300 lw s0,0(a4) + 16c4: 485f5253 .4byte 0x485f5253 + 16c8: 4d50 lw a2,28(a0) + 16ca: 4e554f43 .4byte 0x4e554f43 + 16ce: 4554 lw a3,12(a0) + 16d0: 3152 .2byte 0x3152 + 16d2: 4830 lw a2,80(s0) + 16d4: 4200 lw s0,0(a2) + 16d6: 5355 li t1,-11 + 16d8: 5045454b .4byte 0x5045454b + 16dc: 5245 li tp,-15 + 16de: 455f 5252 465f .byte 0x5f, 0x45, 0x52, 0x52, 0x5f, 0x46 + 16e4: 414c lw a1,4(a0) + 16e6: 52540047 .4byte 0x52540047 + 16ea: 5041 c.li zero,-16 + 16ec: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 16f2: 4946 lw s2,80(sp) + 16f4: 5152 lw sp,52(sp) + 16f6: 315f 0034 5343 .byte 0x5f, 0x31, 0x34, 0x00, 0x43, 0x53 + 16fc: 5f52 lw t5,52(sp) + 16fe: 494d li s2,19 + 1700: 504d c.li zero,-13 + 1702: 4449 li s0,18 + 1704: 4e00 lw s0,24(a2) + 1706: 4f45 li t5,17 + 1708: 5652 lw a2,52(sp) + 170a: 435f3233 .4byte 0x435f3233 + 170e: 585f5253 .4byte 0x585f5253 + 1712: 5349 li t1,-14 + 1714: 5f41 li t5,-16 + 1716: 6e65 lui t3,0x19 + 1718: 6d75 lui s10,0x1d + 171a: 4300 lw s0,0(a4) + 171c: 4d5f5253 .4byte 0x4d5f5253 + 1720: 5048 lw a0,36(s0) + 1722: 434d li t1,19 + 1724: 544e554f .4byte 0x544e554f + 1728: 5245 li tp,-15 + 172a: 3131 jal 1336 <_malloc_r+0x4d8> + 172c: 0048 addi a0,sp,4 + 172e: 5254 lw a3,36(a2) + 1730: 5041 c.li zero,-16 + 1732: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 1738: 5f49 li t5,-14 + 173a: 4341 li t1,16 + 173c: 53534543 .4byte 0x53534543 + 1740: 5f00 lw s0,56(a4) + 1742: 625f 6975 746c .byte 0x5f, 0x62, 0x75, 0x69, 0x6c, 0x74 + 1748: 6e69 lui t3,0x1a + 174a: 6d5f 6d65 7063 .byte 0x5f, 0x6d, 0x65, 0x6d, 0x63, 0x70 + 1750: 0079 c.nop 30 + 1752: 5f525343 .4byte 0x5f525343 + 1756: 5048 lw a0,36(s0) + 1758: 434d li t1,19 + 175a: 544e554f .4byte 0x544e554f + 175e: 5245 li tp,-15 + 1760: 3131 jal 136c <_malloc_r+0x50e> + 1762: 0048 addi a0,sp,4 + 1764: 5254 lw a3,36(a2) + 1766: 5041 c.li zero,-16 + 1768: 435f 444f 5f45 .byte 0x5f, 0x43, 0x4f, 0x44, 0x45, 0x5f + 176e: 5f4c lw a1,60(a4) + 1770: 494d li s2,19 + 1772: 494c4153 .4byte 0x494c4153 + 1776: 44454e47 .4byte 0x44454e47 + 177a: 6d00 .2byte 0x6d00 + 177c: 7369 lui t1,0xffffa + 177e: 5f61 li t5,-8 + 1780: 43006363 bltu zero,a6,1ba6 <__RODATA_END__+0xd6> + 1784: 4d5f5253 .4byte 0x4d5f5253 + 1788: 4958 lw a4,20(a0) + 178a: 5a5f4153 .4byte 0x5a5f4153 + 178e: 4349 li t1,18 + 1790: 43005253 .4byte 0x43005253 + 1794: 495f5253 .4byte 0x495f5253 + 1798: 534e lw t1,240(sp) + 179a: 5254 lw a3,36(a2) + 179c: 5445 li s0,-15 + 179e: 4300 lw s0,0(a4) + 17a0: 4d5f5253 .4byte 0x4d5f5253 + 17a4: 4e49 li t3,18 + 17a6: 45525453 .4byte 0x45525453 + 17aa: 4854 lw a3,20(s0) + 17ac: 4300 lw s0,0(a4) + 17ae: 435f5253 .4byte 0x435f5253 + 17b2: 4359 li t1,22 + 17b4: 454c lw a1,12(a0) + 17b6: 7400 .2byte 0x7400 + 17b8: 6172 .2byte 0x6172 + 17ba: 5f70 lw a2,124(a4) + 17bc: 73756163 bltu a0,s7,1ede <__RODATA_END__+0x40e> + 17c0: 0065 c.nop 25 + 17c2: 5f525343 .4byte 0x5f525343 + 17c6: 484d li a6,19 + 17c8: 4d50 lw a2,28(a0) + 17ca: 4e554f43 .4byte 0x4e554f43 + 17ce: 4554 lw a3,12(a0) + 17d0: 3152 .2byte 0x3152 + 17d2: 4832 lw a6,12(sp) + 17d4: 5200 lw s0,32(a2) + 17d6: 4554 lw a3,12(a0) + 17d8: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 17de: 5f49 li t5,-14 + 17e0: 4c49 li s8,18 + 17e2: 454c lw a1,12(a0) + 17e4: 004c4147 .4byte 0x4c4147 + 17e8: 656e .2byte 0x656e + 17ea: 3376726f jal tp,69320 <__neorv32_ram_size+0x67320> + 17ee: 5f32 lw t5,44(sp) + 17f0: 7472 .2byte 0x7472 + 17f2: 5f65 li t5,-7 + 17f4: 5f746567 .4byte 0x5f746567 + 17f8: 706d6f63 bltu s10,t1,1f16 <__RODATA_END__+0x446> + 17fc: 6c69 lui s8,0x1a + 17fe: 7265 lui tp,0xffff9 + 1800: 695f 6173 4300 .byte 0x5f, 0x69, 0x73, 0x61, 0x00, 0x43 + 1806: 485f5253 .4byte 0x485f5253 + 180a: 4d50 lw a2,28(a0) + 180c: 4e554f43 .4byte 0x4e554f43 + 1810: 4554 lw a3,12(a0) + 1812: 3152 .2byte 0x3152 + 1814: 4832 lw a6,12(sp) + 1816: 4300 lw s0,0(a4) + 1818: 4d5f5253 .4byte 0x4d5f5253 + 181c: 4549 li a0,18 + 181e: 4d5f 4953 0045 .byte 0x5f, 0x4d, 0x53, 0x49, 0x45, 0x00 + 1824: 5f5f 6e69 3174 .byte 0x5f, 0x5f, 0x69, 0x6e, 0x74, 0x31 + 182a: 5f36 lw t5,108(sp) + 182c: 0074 addi a3,sp,12 + 182e: 5f525343 .4byte 0x5f525343 + 1832: 484d li a6,19 + 1834: 4d50 lw a2,28(a0) + 1836: 4e554f43 .4byte 0x4e554f43 + 183a: 4554 lw a3,12(a0) + 183c: 3152 .2byte 0x3152 + 183e: 43004833 .4byte 0x43004833 + 1842: 545f5253 .4byte 0x545f5253 + 1846: 4144 lw s1,4(a0) + 1848: 4154 lw a3,4(a0) + 184a: 0031 c.nop 12 + 184c: 7562 .2byte 0x7562 + 184e: 72655f73 csrrwi t5,mhpmevent6h,10 + 1852: 0072 c.slli zero,0x1c + 1854: 5f525343 .4byte 0x5f525343 + 1858: 5048 lw a0,36(s0) + 185a: 434d li t1,19 + 185c: 544e554f .4byte 0x544e554f + 1860: 5245 li tp,-15 + 1862: 3331 jal 156e <_free_r+0x7e> + 1864: 0048 addi a0,sp,4 + 1866: 5452 lw s0,52(sp) + 1868: 5f45 li t5,-15 + 186a: 5254 lw a3,36(a2) + 186c: 5041 c.li zero,-16 + 186e: 555f 4e45 5f56 .byte 0x5f, 0x55, 0x45, 0x4e, 0x56, 0x5f + 1874: 4c4c4143 .4byte 0x4c4c4143 + 1878: 4300 lw s0,0(a4) + 187a: 4d5f5253 .4byte 0x4d5f5253 + 187e: 4958 lw a4,20(a0) + 1880: 5a5f4153 .4byte 0x5a5f4153 + 1884: 4349 li t1,18 + 1886: 544e lw s0,240(sp) + 1888: 0052 c.slli zero,0x14 + 188a: 6e69 lui t3,0x1a + 188c: 5f727473 csrrci s0,0x5f7,4 + 1890: 6968 .2byte 0x6968 + 1892: 4e00 lw s0,24(a2) + 1894: 4f45 li t5,17 + 1896: 5652 lw a2,52(sp) + 1898: 525f3233 .4byte 0x525f3233 + 189c: 4554 lw a3,12(a0) + 189e: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 18a4: 6e65 lui t3,0x19 + 18a6: 6d75 lui s10,0x1d + 18a8: 6d00 .2byte 0x6d00 + 18aa: 7369 lui t1,0xffffa + 18ac: 5f61 li t5,-8 + 18ae: 52007773 csrrci a4,0x520,0 + 18b2: 4554 lw a3,12(a0) + 18b4: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 18ba: 4946 lw s2,80(sp) + 18bc: 5152 lw sp,52(sp) + 18be: 315f 0030 5452 .byte 0x5f, 0x31, 0x30, 0x00, 0x52, 0x54 + 18c4: 5f45 li t5,-15 + 18c6: 5254 lw a3,36(a2) + 18c8: 5041 c.li zero,-16 + 18ca: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 18d0: 3131 jal 14dc <_malloc_trim_r+0xb0> + 18d2: 5200 lw s0,32(a2) + 18d4: 4554 lw a3,12(a0) + 18d6: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 18dc: 4946 lw s2,80(sp) + 18de: 5152 lw sp,52(sp) + 18e0: 315f 0032 5452 .byte 0x5f, 0x31, 0x32, 0x00, 0x52, 0x54 + 18e6: 5f45 li t5,-15 + 18e8: 5254 lw a3,36(a2) + 18ea: 5041 c.li zero,-16 + 18ec: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 18f2: 3331 jal 15fe <_free_r+0x10e> + 18f4: 5200 lw s0,32(a2) + 18f6: 4554 lw a3,12(a0) + 18f8: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 18fe: 4946 lw s2,80(sp) + 1900: 5152 lw sp,52(sp) + 1902: 315f 0034 5452 .byte 0x5f, 0x31, 0x34, 0x00, 0x52, 0x54 + 1908: 5f45 li t5,-15 + 190a: 5254 lw a3,36(a2) + 190c: 5041 c.li zero,-16 + 190e: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1914: 3531 jal 1720 <__fini_array_end> + 1916: 6900 .2byte 0x6900 + 1918: 6c625f63 bge tp,t1,1ff6 <__RODATA_END__+0x526> + 191c: 5f6b636f jal t1,b7f12 <__neorv32_ram_size+0xb5f12> + 1920: 657a6973 csrrsi s2,0x657,20 + 1924: 4300 lw s0,0(a4) + 1926: 4d5f5253 .4byte 0x4d5f5253 + 192a: 5048 lw a0,36(s0) + 192c: 434d li t1,19 + 192e: 544e554f .4byte 0x544e554f + 1932: 5245 li tp,-15 + 1934: 3431 jal 1340 <_malloc_r+0x4e2> + 1936: 0048 addi a0,sp,4 + 1938: 5452 lw s0,52(sp) + 193a: 5f45 li t5,-15 + 193c: 5254 lw a3,36(a2) + 193e: 5041 c.li zero,-16 + 1940: 495f 4d5f 5349 .byte 0x5f, 0x49, 0x5f, 0x4d, 0x49, 0x53 + 1946: 4c41 li s8,16 + 1948: 4749 li a4,18 + 194a: 454e lw a0,208(sp) + 194c: 0044 addi s1,sp,4 + 194e: 5f525343 .4byte 0x5f525343 + 1952: 5048 lw a0,36(s0) + 1954: 434d li t1,19 + 1956: 544e554f .4byte 0x544e554f + 195a: 5245 li tp,-15 + 195c: 3431 jal 1368 <_malloc_r+0x50a> + 195e: 0048 addi a0,sp,4 + 1960: 63656863 bltu a0,s6,1f90 <__RODATA_END__+0x4c0> + 1964: 656e006b .4byte 0x656e006b + 1968: 3376726f jal tp,6949e <__neorv32_ram_size+0x6749e> + 196c: 5f32 lw t5,44(sp) + 196e: 7472 .2byte 0x7472 + 1970: 5f65 li t5,-7 + 1972: 6168 .2byte 0x6168 + 1974: 646e .2byte 0x646e + 1976: 656c .2byte 0x656c + 1978: 5f72 lw t5,60(sp) + 197a: 6e75 lui t3,0x1d + 197c: 6e69 lui t3,0x1a + 197e: 6c617473 csrrci s0,0x6c6,2 + 1982: 006c addi a1,sp,12 + 1984: 5f5f 656e 726f .byte 0x5f, 0x5f, 0x6e, 0x65, 0x6f, 0x72 + 198a: 3376 .2byte 0x3376 + 198c: 5f32 lw t5,44(sp) + 198e: 7472 .2byte 0x7472 + 1990: 5f65 li t5,-7 + 1992: 6576 .2byte 0x6576 + 1994: 726f7463 bgeu t5,t1,20bc <__neorv32_ram_size+0xbc> + 1998: 6c5f 7475 4300 .byte 0x5f, 0x6c, 0x75, 0x74, 0x00, 0x43 + 199e: 4d5f5253 .4byte 0x4d5f5253 + 19a2: 4958 lw a4,20(a0) + 19a4: 5a5f4153 .4byte 0x5a5f4153 + 19a8: 4d4d li s10,19 + 19aa: 4c55 li s8,21 + 19ac: 5200 lw s0,32(a2) + 19ae: 4554 lw a3,12(a0) + 19b0: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 19b6: 5f49 li t5,-14 + 19b8: 4341 li t1,16 + 19ba: 53534543 .4byte 0x53534543 + 19be: 4300 lw s0,0(a4) + 19c0: 4d5f5253 .4byte 0x4d5f5253 + 19c4: 54415453 .4byte 0x54415453 + 19c8: 5355 li t1,-11 + 19ca: 5200 lw s0,32(a2) + 19cc: 4554 lw a3,12(a0) + 19ce: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 19d4: 43415f53 .4byte 0x43415f53 + 19d8: 53534543 .4byte 0x53534543 + 19dc: 4300 lw s0,0(a4) + 19de: 4d5f5253 .4byte 0x4d5f5253 + 19e2: 5048 lw a0,36(s0) + 19e4: 434d li t1,19 + 19e6: 544e554f .4byte 0x544e554f + 19ea: 5245 li tp,-15 + 19ec: 3531 jal 17f8 <__fini_array_end+0xd8> + 19ee: 0048 addi a0,sp,4 + 19f0: 656e .2byte 0x656e + 19f2: 3376726f jal tp,69528 <__neorv32_ram_size+0x67528> + 19f6: 5f32 lw t5,44(sp) + 19f8: 7472 .2byte 0x7472 + 19fa: 5f65 li t5,-7 + 19fc: 6168 .2byte 0x6168 + 19fe: 646e .2byte 0x646e + 1a00: 656c .2byte 0x656c + 1a02: 5f72 lw t5,60(sp) + 1a04: 6e69 lui t3,0x1a + 1a06: 6c617473 csrrci s0,0x6c6,2 + 1a0a: 006c addi a1,sp,12 + 1a0c: 5f525343 .4byte 0x5f525343 + 1a10: 584d li a6,-13 + 1a12: 5349 li t1,-14 + 1a14: 5f41 li t5,-16 + 1a16: 585a lw a6,180(sp) + 1a18: 00554643 .4byte 0x554643 + 1a1c: 5f525343 .4byte 0x5f525343 + 1a20: 5048 lw a0,36(s0) + 1a22: 434d li t1,19 + 1a24: 544e554f .4byte 0x544e554f + 1a28: 5245 li tp,-15 + 1a2a: 3531 jal 1836 <__fini_array_end+0x116> + 1a2c: 0048 addi a0,sp,4 + 1a2e: 5f525343 .4byte 0x5f525343 + 1a32: 584d li a6,-13 + 1a34: 5349 li t1,-14 + 1a36: 5f41 li t5,-16 + 1a38: 4d50 lw a2,28(a0) + 1a3a: 0050 addi a2,sp,4 + 1a3c: 5f525343 .4byte 0x5f525343 + 1a40: 584d li a6,-13 + 1a42: 5349 li t1,-14 + 1a44: 5f41 li t5,-16 + 1a46: 58454453 .4byte 0x58454453 + 1a4a: 0054 addi a3,sp,4 + 1a4c: 5f525343 .4byte 0x5f525343 + 1a50: 494d li s2,19 + 1a52: 42004153 .4byte 0x42004153 + 1a56: 5355 li t1,-11 + 1a58: 5045454b .4byte 0x5045454b + 1a5c: 5245 li tp,-15 + 1a5e: 455f 5252 545f .byte 0x5f, 0x45, 0x52, 0x52, 0x5f, 0x54 + 1a64: 5059 c.li zero,-10 + 1a66: 0045 c.nop 17 + 1a68: 5f525343 .4byte 0x5f525343 + 1a6c: 484d li a6,19 + 1a6e: 4d50 lw a2,28(a0) + 1a70: 4e554f43 .4byte 0x4e554f43 + 1a74: 4554 lw a3,12(a0) + 1a76: 3152 .2byte 0x3152 + 1a78: 4836 lw a6,76(sp) + 1a7a: 4300 lw s0,0(a4) + 1a7c: 485f5253 .4byte 0x485f5253 + 1a80: 4d50 lw a2,28(a0) + 1a82: 4e554f43 .4byte 0x4e554f43 + 1a86: 4554 lw a3,12(a0) + 1a88: 3152 .2byte 0x3152 + 1a8a: 0030 addi a2,sp,8 + 1a8c: 5f525343 .4byte 0x5f525343 + 1a90: 5048 lw a0,36(s0) + 1a92: 434d li t1,19 + 1a94: 544e554f .4byte 0x544e554f + 1a98: 5245 li tp,-15 + 1a9a: 3131 jal 16a6 <_free_r+0x1b6> + 1a9c: 4300 lw s0,0(a4) + 1a9e: 485f5253 .4byte 0x485f5253 + 1aa2: 4d50 lw a2,28(a0) + 1aa4: 4e554f43 .4byte 0x4e554f43 + 1aa8: 4554 lw a3,12(a0) + 1aaa: 3152 .2byte 0x3152 + 1aac: 0032 c.slli zero,0xc + 1aae: 5f525343 .4byte 0x5f525343 + 1ab2: 5048 lw a0,36(s0) + 1ab4: 434d li t1,19 + 1ab6: 544e554f .4byte 0x544e554f + 1aba: 5245 li tp,-15 + 1abc: 3331 jal 17c8 <__fini_array_end+0xa8> + 1abe: 4300 lw s0,0(a4) + 1ac0: 485f5253 .4byte 0x485f5253 + 1ac4: 4d50 lw a2,28(a0) + 1ac6: 4e554f43 .4byte 0x4e554f43 + 1aca: 4554 lw a3,12(a0) + 1acc: 3152 .2byte 0x3152 + 1ace: 0034 addi a3,sp,8 + 1ad0: 5f525343 .4byte 0x5f525343 + 1ad4: 5048 lw a0,36(s0) + 1ad6: 434d li t1,19 + 1ad8: 544e554f .4byte 0x544e554f + 1adc: 5245 li tp,-15 + 1ade: 3531 jal 18ea <__fini_array_end+0x1ca> + 1ae0: 4300 lw s0,0(a4) + 1ae2: 485f5253 .4byte 0x485f5253 + 1ae6: 4d50 lw a2,28(a0) + 1ae8: 4e554f43 .4byte 0x4e554f43 + 1aec: 4554 lw a3,12(a0) + 1aee: 3152 .2byte 0x3152 + 1af0: 0036 c.slli zero,0xd + 1af2: 5f525343 .4byte 0x5f525343 + 1af6: 484d li a6,19 + 1af8: 4d50 lw a2,28(a0) + 1afa: 4e554f43 .4byte 0x4e554f43 + 1afe: 4554 lw a3,12(a0) + 1b00: 3252 .2byte 0x3252 + 1b02: 4830 lw a2,80(s0) + 1b04: 4300 lw s0,0(a4) + 1b06: 485f5253 .4byte 0x485f5253 + 1b0a: 4d50 lw a2,28(a0) + 1b0c: 4e554f43 .4byte 0x4e554f43 + 1b10: 4554 lw a3,12(a0) + 1b12: 3152 .2byte 0x3152 + 1b14: 0038 addi a4,sp,8 + 1b16: 5f525343 .4byte 0x5f525343 + 1b1a: 5048 lw a0,36(s0) + 1b1c: 434d li t1,19 + 1b1e: 544e554f .4byte 0x544e554f + 1b22: 5245 li tp,-15 + 1b24: 3931 jal 1740 <__fini_array_end+0x20> + 1b26: 5400 lw s0,40(s0) + 1b28: 4152 lw sp,20(sp) + 1b2a: 5f50 lw a2,60(a4) + 1b2c: 45444f43 .4byte 0x45444f43 + 1b30: 4d5f 4e45 5f56 .byte 0x5f, 0x4d, 0x45, 0x4e, 0x56, 0x5f + 1b36: 4c4c4143 .4byte 0x4c4c4143 + 1b3a: 5200 lw s0,32(a2) + 1b3c: 4554 lw a3,12(a0) + 1b3e: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 1b44: 5f4c lw a1,60(a4) + 1b46: 4341 li t1,16 + 1b48: 53534543 .4byte 0x53534543 + 1b4c: 4300 lw s0,0(a4) + 1b4e: 485f5253 .4byte 0x485f5253 + 1b52: 4d50 lw a2,28(a0) + 1b54: 4e554f43 .4byte 0x4e554f43 + 1b58: 4554 lw a3,12(a0) + 1b5a: 3252 .2byte 0x3252 + 1b5c: 4830 lw a2,80(s0) + 1b5e: 5200 lw s0,32(a2) + 1b60: 4554 lw a3,12(a0) + 1b62: 545f 4152 5f50 .byte 0x5f, 0x54, 0x52, 0x41, 0x50, 0x5f + 1b68: 534d li t1,-13 + 1b6a: 0049 c.nop 18 + 1b6c: 5f525343 .4byte 0x5f525343 + 1b70: 484d li a6,19 + 1b72: 5241 li tp,-16 + 1b74: 4954 lw a3,20(a0) + 1b76: 0044 addi s1,sp,4 + 1b78: 5f525343 .4byte 0x5f525343 + 1b7c: 434d li t1,19 + 1b7e: 5541 li a0,-16 + 1b80: 43004553 .4byte 0x43004553 + 1b84: 545f5253 .4byte 0x545f5253 + 1b88: 4144 lw s1,4(a0) + 1b8a: 4154 lw a3,4(a0) + 1b8c: 0032 c.slli zero,0xc + 1b8e: 5f525343 .4byte 0x5f525343 + 1b92: 4454 lw a3,12(s0) + 1b94: 5441 li s0,-16 + 1b96: 3341 jal 1916 <__fini_array_end+0x1f6> + 1b98: 4300 lw s0,0(a4) + 1b9a: 4d5f5253 .4byte 0x4d5f5253 + 1b9e: 5048 lw a0,36(s0) + 1ba0: 434d li t1,19 + 1ba2: 544e554f .4byte 0x544e554f + 1ba6: 5245 li tp,-15 + 1ba8: 3731 jal 1ab4 + 1baa: 0048 addi a0,sp,4 + 1bac: 5f525343 .4byte 0x5f525343 + 1bb0: 5048 lw a0,36(s0) + 1bb2: 434d li t1,19 + 1bb4: 544e554f .4byte 0x544e554f + 1bb8: 5245 li tp,-15 + 1bba: 3032 .2byte 0x3032 + 1bbc: 4300 lw s0,0(a4) + 1bbe: 485f5253 .4byte 0x485f5253 + 1bc2: 4d50 lw a2,28(a0) + 1bc4: 4e554f43 .4byte 0x4e554f43 + 1bc8: 4554 lw a3,12(a0) + 1bca: 3252 .2byte 0x3252 + 1bcc: 0031 c.nop 12 + 1bce: 5f525343 .4byte 0x5f525343 + 1bd2: 5048 lw a0,36(s0) + 1bd4: 434d li t1,19 + 1bd6: 544e554f .4byte 0x544e554f + 1bda: 5245 li tp,-15 + 1bdc: 3232 .2byte 0x3232 + 1bde: 4300 lw s0,0(a4) + 1be0: 485f5253 .4byte 0x485f5253 + 1be4: 4d50 lw a2,28(a0) + 1be6: 4e554f43 .4byte 0x4e554f43 + 1bea: 4554 lw a3,12(a0) + 1bec: 3252 .2byte 0x3252 + 1bee: 53430033 .4byte 0x53430033 + 1bf2: 5f52 lw t5,52(sp) + 1bf4: 5048 lw a0,36(s0) + 1bf6: 434d li t1,19 + 1bf8: 544e554f .4byte 0x544e554f + 1bfc: 5245 li tp,-15 + 1bfe: 3432 .2byte 0x3432 + 1c00: 4300 lw s0,0(a4) + 1c02: 485f5253 .4byte 0x485f5253 + 1c06: 4d50 lw a2,28(a0) + 1c08: 4e554f43 .4byte 0x4e554f43 + 1c0c: 4554 lw a3,12(a0) + 1c0e: 3252 .2byte 0x3252 + 1c10: 0035 c.nop 13 + 1c12: 5f525343 .4byte 0x5f525343 + 1c16: 484d li a6,19 + 1c18: 4d50 lw a2,28(a0) + 1c1a: 4e554f43 .4byte 0x4e554f43 + 1c1e: 4554 lw a3,12(a0) + 1c20: 3252 .2byte 0x3252 + 1c22: 4831 li a6,12 + 1c24: 4300 lw s0,0(a4) + 1c26: 485f5253 .4byte 0x485f5253 + 1c2a: 4d50 lw a2,28(a0) + 1c2c: 4e554f43 .4byte 0x4e554f43 + 1c30: 4554 lw a3,12(a0) + 1c32: 3252 .2byte 0x3252 + 1c34: 0038 addi a4,sp,8 + 1c36: 5f525343 .4byte 0x5f525343 + 1c3a: 5048 lw a0,36(s0) + 1c3c: 434d li t1,19 + 1c3e: 544e554f .4byte 0x544e554f + 1c42: 5245 li tp,-15 + 1c44: 3932 .2byte 0x3932 + 1c46: 7000 .2byte 0x7000 + 1c48: 706d c.lui zero,0xffffb + 1c4a: 6e5f 6d75 725f .byte 0x5f, 0x6e, 0x75, 0x6d, 0x5f, 0x72 + 1c50: 6765 lui a4,0x19 + 1c52: 6f69 lui t5,0x1a + 1c54: 736e .2byte 0x736e + 1c56: 4300 lw s0,0(a4) + 1c58: 485f5253 .4byte 0x485f5253 + 1c5c: 4d50 lw a2,28(a0) + 1c5e: 4e554f43 .4byte 0x4e554f43 + 1c62: 4554 lw a3,12(a0) + 1c64: 3252 .2byte 0x3252 + 1c66: 4831 li a6,12 + 1c68: 4e00 lw s0,24(a2) + 1c6a: 4f45 li t5,17 + 1c6c: 5652 lw a2,52(sp) + 1c6e: 535f3233 .4byte 0x535f3233 + 1c72: 5359 li t1,-10 + 1c74: 4e49 li t3,18 + 1c76: 4f46 lw t5,80(sp) + 1c78: 435f 4341 4548 .byte 0x5f, 0x43, 0x41, 0x43, 0x48, 0x45 + 1c7e: 655f 756e 006d .byte 0x5f, 0x65, 0x6e, 0x75, 0x6d, 0x00 + 1c84: 5452 lw s0,52(sp) + 1c86: 5f45 li t5,-15 + 1c88: 5254 lw a3,36(a2) + 1c8a: 5041 c.li zero,-16 + 1c8c: 4d5f 4954 6900 .byte 0x5f, 0x4d, 0x54, 0x49, 0x00, 0x69 + 1c92: 736e .2byte 0x736e + 1c94: 7274 .2byte 0x7274 + 1c96: 6c5f 006f 6572 .byte 0x5f, 0x6c, 0x6f, 0x00, 0x72, 0x65 + 1c9c: 76726573 csrrsi a0,0x767,4 + 1ca0: 6465 lui s0,0x19 + 1ca2: 4300 lw s0,0(a4) + 1ca4: 4d5f5253 .4byte 0x4d5f5253 + 1ca8: 464e4f43 .4byte 0x464e4f43 + 1cac: 4749 li a4,18 + 1cae: 5450 lw a2,44(s0) + 1cb0: 0052 c.slli zero,0x14 + 1cb2: 5f525343 .4byte 0x5f525343 + 1cb6: 494d li s2,19 + 1cb8: 5f45 li t5,-15 + 1cba: 454d li a0,19 + 1cbc: 4549 li a0,18 + 1cbe: 4300 lw s0,0(a4) + 1cc0: 4d5f5253 .4byte 0x4d5f5253 + 1cc4: 4958 lw a4,20(a0) + 1cc6: 495f4153 .4byte 0x495f4153 + 1cca: 49535f53 .4byte 0x49535f53 + 1cce: 004d c.nop 19 + 1cd0: 5f5f 656e 726f .byte 0x5f, 0x5f, 0x6e, 0x65, 0x6f, 0x72 + 1cd6: 3376 .2byte 0x3376 + 1cd8: 5f32 lw t5,44(sp) + 1cda: 7472 .2byte 0x7472 + 1cdc: 5f65 li t5,-7 + 1cde: 6564 .2byte 0x6564 + 1ce0: 7562 .2byte 0x7562 + 1ce2: 61685f67 .4byte 0x61685f67 + 1ce6: 646e .2byte 0x646e + 1ce8: 656c .2byte 0x656c + 1cea: 0072 c.slli zero,0x1c + 1cec: 5f525343 .4byte 0x5f525343 + 1cf0: 484d li a6,19 + 1cf2: 4d50 lw a2,28(a0) + 1cf4: 4e554f43 .4byte 0x4e554f43 + 1cf8: 4554 lw a3,12(a0) + 1cfa: 3152 .2byte 0x3152 + 1cfc: 4838 lw a4,80(s0) + 1cfe: 4300 lw s0,0(a4) + 1d00: 485f5253 .4byte 0x485f5253 + 1d04: 4d50 lw a2,28(a0) + 1d06: 4e554f43 .4byte 0x4e554f43 + 1d0a: 4554 lw a3,12(a0) + 1d0c: 3352 .2byte 0x3352 + 1d0e: 0030 addi a2,sp,8 + 1d10: 5f525343 .4byte 0x5f525343 + 1d14: 5048 lw a0,36(s0) + 1d16: 434d li t1,19 + 1d18: 544e554f .4byte 0x544e554f + 1d1c: 5245 li tp,-15 + 1d1e: 43003133 .4byte 0x43003133 + 1d22: 4d5f5253 .4byte 0x4d5f5253 + 1d26: 5048 lw a0,36(s0) + 1d28: 434d li t1,19 + 1d2a: 544e554f .4byte 0x544e554f + 1d2e: 5245 li tp,-15 + 1d30: 3232 .2byte 0x3232 + 1d32: 0048 addi a0,sp,4 + 1d34: 5f525343 .4byte 0x5f525343 + 1d38: 5048 lw a0,36(s0) + 1d3a: 434d li t1,19 + 1d3c: 544e554f .4byte 0x544e554f + 1d40: 5245 li tp,-15 + 1d42: 3831 jal 155e <_free_r+0x6e> + 1d44: 0048 addi a0,sp,4 + 1d46: 7472 .2byte 0x7472 + 1d48: 5f65 li t5,-7 + 1d4a: 6168 .2byte 0x6168 + 1d4c: 646e .2byte 0x646e + 1d4e: 656c .2byte 0x656c + 1d50: 0072 c.slli zero,0x1c + 1d52: 5f525343 .4byte 0x5f525343 + 1d56: 5048 lw a0,36(s0) + 1d58: 434d li t1,19 + 1d5a: 544e554f .4byte 0x544e554f + 1d5e: 5245 li tp,-15 + 1d60: 3232 .2byte 0x3232 + 1d62: 0048 addi a0,sp,4 + 1d64: 5f525343 .4byte 0x5f525343 + 1d68: 5048 lw a0,36(s0) + 1d6a: 434d li t1,19 + 1d6c: 544e554f .4byte 0x544e554f + 1d70: 5245 li tp,-15 + 1d72: 43004833 .4byte 0x43004833 + 1d76: 4d5f5253 .4byte 0x4d5f5253 + 1d7a: 4549 li a0,18 + 1d7c: 4d5f 4954 0045 .byte 0x5f, 0x4d, 0x54, 0x49, 0x45, 0x00 + 1d82: 5f525343 .4byte 0x5f525343 + 1d86: 434d li t1,19 + 1d88: 544e554f .4byte 0x544e554f + 1d8c: 4e49 li t3,18 + 1d8e: 4948 lw a0,20(a0) + 1d90: 4942 lw s2,16(sp) + 1d92: 0054 addi a3,sp,4 + 1d94: 656e .2byte 0x656e + 1d96: 3376726f jal tp,698cc <__neorv32_ram_size+0x678cc> + 1d9a: 5f32 lw t5,44(sp) + 1d9c: 5f757063 bgeu a0,s7,237c <__neorv32_ram_size+0x37c> + 1da0: 5f727363 bgeu tp,s7,2386 <__neorv32_ram_size+0x386> + 1da4: 74697277 .4byte 0x74697277 + 1da8: 0065 c.nop 25 + 1daa: 5f525343 .4byte 0x5f525343 + 1dae: 454d li a0,19 + 1db0: 4350 lw a2,4(a4) + 1db2: 5f00 lw s0,56(a4) + 1db4: 695f 746e 3233 .byte 0x5f, 0x69, 0x6e, 0x74, 0x33, 0x32 + 1dba: 745f 5400 4152 .byte 0x5f, 0x74, 0x00, 0x54, 0x52, 0x41 + 1dc0: 5f50 lw a2,60(a4) + 1dc2: 45444f43 .4byte 0x45444f43 + 1dc6: 4d5f 4954 4300 .byte 0x5f, 0x4d, 0x54, 0x49, 0x00, 0x43 + 1dcc: 505f5253 .4byte 0x505f5253 + 1dd0: 504d c.li zero,-13 + 1dd2: 30474643 .4byte 0x30474643 + 1dd6: 4300 lw s0,0(a4) + 1dd8: 505f5253 .4byte 0x505f5253 + 1ddc: 504d c.li zero,-13 + 1dde: 31474643 .4byte 0x31474643 + 1de2: 4300 lw s0,0(a4) + 1de4: 505f5253 .4byte 0x505f5253 + 1de8: 504d c.li zero,-13 + 1dea: 32474643 .4byte 0x32474643 + 1dee: 4300 lw s0,0(a4) + 1df0: 505f5253 .4byte 0x505f5253 + 1df4: 504d c.li zero,-13 + 1df6: 33474643 .4byte 0x33474643 + 1dfa: 4300 lw s0,0(a4) + 1dfc: 4d5f5253 .4byte 0x4d5f5253 + 1e00: 5048 lw a0,36(s0) + 1e02: 434d li t1,19 + 1e04: 544e554f .4byte 0x544e554f + 1e08: 5245 li tp,-15 + 1e0a: 3931 jal 1a26 <__fini_array_end+0x306> + 1e0c: 0048 addi a0,sp,4 + 1e0e: 5f525343 .4byte 0x5f525343 + 1e12: 4d50 lw a2,28(a0) + 1e14: 4150 lw a2,4(a0) + 1e16: 4444 lw s1,12(s0) + 1e18: 3052 .2byte 0x3052 + 1e1a: 4300 lw s0,0(a4) + 1e1c: 505f5253 .4byte 0x505f5253 + 1e20: 504d c.li zero,-13 + 1e22: 4441 li s0,16 + 1e24: 5244 lw s1,36(a2) + 1e26: 0031 c.nop 12 + 1e28: 5f525343 .4byte 0x5f525343 + 1e2c: 4d50 lw a2,28(a0) + 1e2e: 4150 lw a2,4(a0) + 1e30: 4444 lw s1,12(s0) + 1e32: 3252 .2byte 0x3252 + 1e34: 4300 lw s0,0(a4) + 1e36: 505f5253 .4byte 0x505f5253 + 1e3a: 504d c.li zero,-13 + 1e3c: 4441 li s0,16 + 1e3e: 5244 lw s1,36(a2) + 1e40: 53430033 .4byte 0x53430033 + 1e44: 5f52 lw t5,52(sp) + 1e46: 4d50 lw a2,28(a0) + 1e48: 4150 lw a2,4(a0) + 1e4a: 4444 lw s1,12(s0) + 1e4c: 3452 .2byte 0x3452 + 1e4e: 4300 lw s0,0(a4) + 1e50: 505f5253 .4byte 0x505f5253 + 1e54: 504d c.li zero,-13 + 1e56: 4441 li s0,16 + 1e58: 5244 lw s1,36(a2) + 1e5a: 0035 c.nop 13 + 1e5c: 5f525343 .4byte 0x5f525343 + 1e60: 4d50 lw a2,28(a0) + 1e62: 4150 lw a2,4(a0) + 1e64: 4444 lw s1,12(s0) + 1e66: 3652 .2byte 0x3652 + 1e68: 4300 lw s0,0(a4) + 1e6a: 505f5253 .4byte 0x505f5253 + 1e6e: 504d c.li zero,-13 + 1e70: 4441 li s0,16 + 1e72: 5244 lw s1,36(a2) + 1e74: 53430037 lui zero,0x53430 + 1e78: 5f52 lw t5,52(sp) + 1e7a: 4d50 lw a2,28(a0) + 1e7c: 4150 lw a2,4(a0) + 1e7e: 4444 lw s1,12(s0) + 1e80: 3852 .2byte 0x3852 + 1e82: 4300 lw s0,0(a4) + 1e84: 485f5253 .4byte 0x485f5253 + 1e88: 4d50 lw a2,28(a0) + 1e8a: 4e554f43 .4byte 0x4e554f43 + 1e8e: 4554 lw a3,12(a0) + 1e90: 3152 .2byte 0x3152 + 1e92: 4839 li a6,14 + 1e94: 4300 lw s0,0(a4) + 1e96: 485f5253 .4byte 0x485f5253 + 1e9a: 4d50 lw a2,28(a0) + 1e9c: 4e554f43 .4byte 0x4e554f43 + 1ea0: 4554 lw a3,12(a0) + 1ea2: 3252 .2byte 0x3252 + 1ea4: 43004833 .4byte 0x43004833 + 1ea8: 485f5253 .4byte 0x485f5253 + 1eac: 4d50 lw a2,28(a0) + 1eae: 4e554f43 .4byte 0x4e554f43 + 1eb2: 4554 lw a3,12(a0) + 1eb4: 3452 .2byte 0x3452 + 1eb6: 0048 addi a0,sp,4 + 1eb8: 6f6c .2byte 0x6f6c + 1eba: 645f6f67 .4byte 0x645f6f67 + 1ebe: 7461 lui s0,0xffff8 + 1ec0: 5f61 li t5,-8 + 1ec2: 54520063 beq tp,t0,2402 <__neorv32_ram_size+0x402> + 1ec6: 5f45 li t5,-15 + 1ec8: 5254 lw a3,36(a2) + 1eca: 5041 c.li zero,-16 + 1ecc: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1ed2: 0030 addi a2,sp,8 + 1ed4: 5452 lw s0,52(sp) + 1ed6: 5f45 li t5,-15 + 1ed8: 5254 lw a3,36(a2) + 1eda: 5041 c.li zero,-16 + 1edc: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1ee2: 0031 c.nop 12 + 1ee4: 5452 lw s0,52(sp) + 1ee6: 5f45 li t5,-15 + 1ee8: 5254 lw a3,36(a2) + 1eea: 5041 c.li zero,-16 + 1eec: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1ef2: 0032 c.slli zero,0xc + 1ef4: 5452 lw s0,52(sp) + 1ef6: 5f45 li t5,-15 + 1ef8: 5254 lw a3,36(a2) + 1efa: 5041 c.li zero,-16 + 1efc: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f02: 54520033 .4byte 0x54520033 + 1f06: 5f45 li t5,-15 + 1f08: 5254 lw a3,36(a2) + 1f0a: 5041 c.li zero,-16 + 1f0c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f12: 0034 addi a3,sp,8 + 1f14: 5452 lw s0,52(sp) + 1f16: 5f45 li t5,-15 + 1f18: 5254 lw a3,36(a2) + 1f1a: 5041 c.li zero,-16 + 1f1c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f22: 0035 c.nop 13 + 1f24: 5452 lw s0,52(sp) + 1f26: 5f45 li t5,-15 + 1f28: 5254 lw a3,36(a2) + 1f2a: 5041 c.li zero,-16 + 1f2c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f32: 0036 c.slli zero,0xd + 1f34: 5452 lw s0,52(sp) + 1f36: 5f45 li t5,-15 + 1f38: 5254 lw a3,36(a2) + 1f3a: 5041 c.li zero,-16 + 1f3c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f42: 54520037 lui zero,0x54520 + 1f46: 5f45 li t5,-15 + 1f48: 5254 lw a3,36(a2) + 1f4a: 5041 c.li zero,-16 + 1f4c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f52: 0038 addi a4,sp,8 + 1f54: 5452 lw s0,52(sp) + 1f56: 5f45 li t5,-15 + 1f58: 5254 lw a3,36(a2) + 1f5a: 5041 c.li zero,-16 + 1f5c: 465f 5249 5f51 .byte 0x5f, 0x46, 0x49, 0x52, 0x51, 0x5f + 1f62: 0039 c.nop 14 + 1f64: 656e .2byte 0x656e + 1f66: 3376726f jal tp,69a9c <__neorv32_ram_size+0x67a9c> + 1f6a: 5f32 lw t5,44(sp) + 1f6c: 6175 addi sp,sp,368 + 1f6e: 7472 .2byte 0x7472 + 1f70: 5f30 lw a2,120(a4) + 1f72: 72616863 bltu sp,t1,26a2 <__neorv32_ram_size+0x6a2> + 1f76: 725f 6365 6965 .byte 0x5f, 0x72, 0x65, 0x63, 0x65, 0x69 + 1f7c: 6576 .2byte 0x6576 + 1f7e: 5f64 lw s1,124(a4) + 1f80: 00746567 .4byte 0x746567 + 1f84: 5f5f 6d75 646f .byte 0x5f, 0x5f, 0x75, 0x6d, 0x6f, 0x64 + 1f8a: 00336973 csrrsi s2,fcsr,6 + 1f8e: 4155 li sp,21 + 1f90: 5452 lw s0,52(sp) + 1f92: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 1f98: 5452 lw s0,52(sp) + 1f9a: 4e455f53 .4byte 0x4e455f53 + 1f9e: 5500 lw s0,40(a0) + 1fa0: 5241 li tp,-16 + 1fa2: 5f54 lw a3,60(a4) + 1fa4: 4c525443 .4byte 0x4c525443 + 1fa8: 545f 5f58 5546 .byte 0x5f, 0x54, 0x58, 0x5f, 0x46, 0x55 + 1fae: 4c4c lw a1,28(s0) + 1fb0: 6e00 .2byte 0x6e00 + 1fb2: 6f65 lui t5,0x19 + 1fb4: 7672 .2byte 0x7672 + 1fb6: 755f3233 .4byte 0x755f3233 + 1fba: 7261 lui tp,0xffff8 + 1fbc: 3074 .2byte 0x3074 + 1fbe: 745f 6e00 6f65 .byte 0x5f, 0x74, 0x00, 0x6e, 0x65, 0x6f + 1fc4: 7672 .2byte 0x7672 + 1fc6: 755f3233 .4byte 0x755f3233 + 1fca: 7261 lui tp,0xffff8 + 1fcc: 3074 .2byte 0x3074 + 1fce: 655f 616e 6c62 .byte 0x5f, 0x65, 0x6e, 0x61, 0x62, 0x6c + 1fd4: 0065 c.nop 25 + 1fd6: 6170 .2byte 0x6170 + 1fd8: 6972 .2byte 0x6972 + 1fda: 7974 .2byte 0x7974 + 1fdc: 635f 6e6f 6966 .byte 0x5f, 0x63, 0x6f, 0x6e, 0x66, 0x69 + 1fe2: 5f5f0067 jr 1525(t5) # 195f5 <__neorv32_ram_size+0x175f5> + 1fe6: 656e .2byte 0x656e + 1fe8: 3376726f jal tp,69b1e <__neorv32_ram_size+0x67b1e> + 1fec: 5f32 lw t5,44(sp) + 1fee: 6175 addi sp,sp,368 + 1ff0: 7472 .2byte 0x7472 + 1ff2: 695f 6f74 0061 .byte 0x5f, 0x69, 0x74, 0x6f, 0x61, 0x00 + 1ff8: 4155 li sp,21 + 1ffa: 5452 lw s0,52(sp) + 1ffc: 445f 5441 5f41 .byte 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f + 2002: 534c lw a1,36(a4) + 2004: 0042 c.slli zero,0x10 + 2006: 6162 .2byte 0x6162 + 2008: 6475 lui s0,0x1d + 200a: 705f 7372 0063 .byte 0x5f, 0x70, 0x72, 0x73, 0x63, 0x00 + 2010: 656e .2byte 0x656e + 2012: 3376726f jal tp,69b48 <__neorv32_ram_size+0x67b48> + 2016: 5f32 lw t5,44(sp) + 2018: 6175 addi sp,sp,368 + 201a: 7472 .2byte 0x7472 + 201c: 5f30 lw a2,120(a4) + 201e: 6964 .2byte 0x6964 + 2020: 6c626173 csrrsi sp,0x6c6,4 + 2024: 0065 c.nop 25 + 2026: 656e .2byte 0x656e + 2028: 3376726f jal tp,69b5e <__neorv32_ram_size+0x67b5e> + 202c: 5f32 lw t5,44(sp) + 202e: 6175 addi sp,sp,368 + 2030: 7472 .2byte 0x7472 + 2032: 5f31 li t5,-20 + 2034: 72616863 bltu sp,t1,2764 <__neorv32_ram_size+0x764> + 2038: 725f 6365 6965 .byte 0x5f, 0x72, 0x65, 0x63, 0x65, 0x69 + 203e: 6576 .2byte 0x6576 + 2040: 0064 addi s1,sp,12 + 2042: 6162 .2byte 0x6162 + 2044: 6475 lui s0,0x1d + 2046: 6172 .2byte 0x6172 + 2048: 6574 .2byte 0x6574 + 204a: 5500 lw s0,40(a0) + 204c: 5241 li tp,-16 + 204e: 5f54 lw a3,60(a4) + 2050: 4c525443 .4byte 0x4c525443 + 2054: 425f 5541 3044 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x30 + 205a: 0030 addi a2,sp,8 + 205c: 4155 li sp,21 + 205e: 5452 lw s0,52(sp) + 2060: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2066: 4142 lw sp,16(sp) + 2068: 4455 li s0,21 + 206a: 3130 .2byte 0x3130 + 206c: 5500 lw s0,40(a0) + 206e: 5241 li tp,-16 + 2070: 5f54 lw a3,60(a4) + 2072: 4c525443 .4byte 0x4c525443 + 2076: 545f 5f58 5249 .byte 0x5f, 0x54, 0x58, 0x5f, 0x49, 0x52 + 207c: 0051 c.nop 20 + 207e: 4155 li sp,21 + 2080: 5452 lw s0,52(sp) + 2082: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2088: 4142 lw sp,16(sp) + 208a: 4455 li s0,21 + 208c: 3330 .2byte 0x3330 + 208e: 5500 lw s0,40(a0) + 2090: 5241 li tp,-16 + 2092: 5f54 lw a3,60(a4) + 2094: 4c525443 .4byte 0x4c525443 + 2098: 425f 5541 3044 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x30 + 209e: 0034 addi a3,sp,8 + 20a0: 4155 li sp,21 + 20a2: 5452 lw s0,52(sp) + 20a4: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 20aa: 4142 lw sp,16(sp) + 20ac: 4455 li s0,21 + 20ae: 3530 .2byte 0x3530 + 20b0: 5500 lw s0,40(a0) + 20b2: 5241 li tp,-16 + 20b4: 5f54 lw a3,60(a4) + 20b6: 4c525443 .4byte 0x4c525443 + 20ba: 425f 5541 3044 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x30 + 20c0: 0036 c.slli zero,0xd + 20c2: 4155 li sp,21 + 20c4: 5452 lw s0,52(sp) + 20c6: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 20cc: 4142 lw sp,16(sp) + 20ce: 4455 li s0,21 + 20d0: 3730 .2byte 0x3730 + 20d2: 5500 lw s0,40(a0) + 20d4: 5241 li tp,-16 + 20d6: 5f54 lw a3,60(a4) + 20d8: 4c525443 .4byte 0x4c525443 + 20dc: 425f 5541 3044 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x30 + 20e2: 0038 addi a4,sp,8 + 20e4: 4155 li sp,21 + 20e6: 5452 lw s0,52(sp) + 20e8: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 20ee: 4142 lw sp,16(sp) + 20f0: 4455 li s0,21 + 20f2: 3930 .2byte 0x3930 + 20f4: 5f00 lw s0,56(a4) + 20f6: 625f 6975 746c .byte 0x5f, 0x62, 0x75, 0x69, 0x6c, 0x74 + 20fc: 6e69 lui t3,0x1a + 20fe: 765f 5f61 696c .byte 0x5f, 0x76, 0x61, 0x5f, 0x6c, 0x69 + 2104: 6e007473 csrrci s0,0x6e0,0 + 2108: 6f65 lui t5,0x19 + 210a: 7672 .2byte 0x7672 + 210c: 755f3233 .4byte 0x755f3233 + 2110: 7261 lui tp,0xffff8 + 2112: 3074 .2byte 0x3074 + 2114: 675f 7465 0063 .byte 0x5f, 0x67, 0x65, 0x74, 0x63, 0x00 + 211a: 7570 .2byte 0x7570 + 211c: 6374 .2byte 0x6374 + 211e: 6168 .2byte 0x6168 + 2120: 0072 c.slli zero,0x1c + 2122: 656e .2byte 0x656e + 2124: 3376726f jal tp,69c5a <__neorv32_ram_size+0x67c5a> + 2128: 5f32 lw t5,44(sp) + 212a: 6175 addi sp,sp,368 + 212c: 7472 .2byte 0x7472 + 212e: 5f31 li t5,-20 + 2130: 75746573 csrrsi a0,0x757,8 + 2134: 0070 addi a2,sp,12 + 2136: 7562 .2byte 0x7562 + 2138: 6666 .2byte 0x6666 + 213a: 7265 lui tp,0xffff9 + 213c: 0031 c.nop 12 + 213e: 4155 li sp,21 + 2140: 5452 lw s0,52(sp) + 2142: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2148: 4e45 li t3,17 + 214a: 6e00 .2byte 0x6e00 + 214c: 6f65 lui t5,0x19 + 214e: 7672 .2byte 0x7672 + 2150: 755f3233 .4byte 0x755f3233 + 2154: 7261 lui tp,0xffff8 + 2156: 3174 .2byte 0x3174 + 2158: 635f 6168 5f72 .byte 0x5f, 0x63, 0x68, 0x61, 0x72, 0x5f + 215e: 6572 .2byte 0x6572 + 2160: 76696563 bltu s2,t1,28ca <__neorv32_ram_size+0x8ca> + 2164: 6465 lui s0,0x19 + 2166: 675f 7465 7000 .byte 0x5f, 0x67, 0x65, 0x74, 0x00, 0x70 + 216c: 7261 lui tp,0xffff8 + 216e: 7469 lui s0,0xffffa + 2170: 0079 c.nop 30 + 2172: 656e .2byte 0x656e + 2174: 3376726f jal tp,69caa <__neorv32_ram_size+0x67caa> + 2178: 5f32 lw t5,44(sp) + 217a: 6175 addi sp,sp,368 + 217c: 7472 .2byte 0x7472 + 217e: 5f31 li t5,-20 + 2180: 6964 .2byte 0x6964 + 2182: 6c626173 csrrsi sp,0x6c6,4 + 2186: 0065 c.nop 25 + 2188: 4155 li sp,21 + 218a: 5452 lw s0,52(sp) + 218c: 445f 5441 5f41 .byte 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f + 2192: 4550 lw a2,12(a0) + 2194: 5252 lw tp,52(sp) + 2196: 5500 lw s0,40(a0) + 2198: 5241 li tp,-16 + 219a: 5f54 lw a3,60(a4) + 219c: 4c525443 .4byte 0x4c525443 + 21a0: 505f 5352 3043 .byte 0x5f, 0x50, 0x52, 0x53, 0x43, 0x30 + 21a6: 5500 lw s0,40(a0) + 21a8: 5241 li tp,-16 + 21aa: 5f54 lw a3,60(a4) + 21ac: 4c525443 .4byte 0x4c525443 + 21b0: 505f 5352 3143 .byte 0x5f, 0x50, 0x52, 0x53, 0x43, 0x31 + 21b6: 5500 lw s0,40(a0) + 21b8: 5241 li tp,-16 + 21ba: 5f54 lw a3,60(a4) + 21bc: 4c525443 .4byte 0x4c525443 + 21c0: 505f 5352 3243 .byte 0x5f, 0x50, 0x52, 0x53, 0x43, 0x32 + 21c6: 6e00 .2byte 0x6e00 + 21c8: 6f65 lui t5,0x19 + 21ca: 7672 .2byte 0x7672 + 21cc: 755f3233 .4byte 0x755f3233 + 21d0: 7261 lui tp,0xffff8 + 21d2: 3074 .2byte 0x3074 + 21d4: 675f 7465 5f63 .byte 0x5f, 0x67, 0x65, 0x74, 0x63, 0x5f + 21da: 65666173 csrrsi sp,0x656,12 + 21de: 7500 .2byte 0x7500 + 21e0: 7261 lui tp,0xffff8 + 21e2: 5f74 lw a3,124(a4) + 21e4: 7872 .2byte 0x7872 + 21e6: 5500 lw s0,40(a0) + 21e8: 5241 li tp,-16 + 21ea: 5f54 lw a3,60(a4) + 21ec: 4c525443 .4byte 0x4c525443 + 21f0: 425f 5541 3144 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x31 + 21f6: 0031 c.nop 12 + 21f8: 656e .2byte 0x656e + 21fa: 3376726f jal tp,69d30 <__neorv32_ram_size+0x67d30> + 21fe: 5f32 lw t5,44(sp) + 2200: 6175 addi sp,sp,368 + 2202: 7472 .2byte 0x7472 + 2204: 5f31 li t5,-20 + 2206: 7661 lui a2,0xffff8 + 2208: 6961 lui s2,0x18 + 220a: 616c .2byte 0x616c + 220c: 6c62 .2byte 0x6c62 + 220e: 0065 c.nop 25 + 2210: 656e .2byte 0x656e + 2212: 3376726f jal tp,69d48 <__neorv32_ram_size+0x67d48> + 2216: 5f32 lw t5,44(sp) + 2218: 6175 addi sp,sp,368 + 221a: 7472 .2byte 0x7472 + 221c: 5f31 li t5,-20 + 221e: 63746567 .4byte 0x63746567 + 2222: 6500 .2byte 0x6500 + 2224: 006f6863 bltu t5,t1,2234 <__neorv32_ram_size+0x234> + 2228: 4155 li sp,21 + 222a: 5452 lw s0,52(sp) + 222c: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2232: 4d50 lw a2,28(a0) + 2234: 3045444f .4byte 0x3045444f + 2238: 5500 lw s0,40(a0) + 223a: 5241 li tp,-16 + 223c: 5f54 lw a3,60(a4) + 223e: 4c525443 .4byte 0x4c525443 + 2242: 505f 4f4d 4544 .byte 0x5f, 0x50, 0x4d, 0x4f, 0x44, 0x45 + 2248: 0031 c.nop 12 + 224a: 5f5f 656e 726f .byte 0x5f, 0x5f, 0x6e, 0x65, 0x6f, 0x72 + 2250: 3376 .2byte 0x3376 + 2252: 5f32 lw t5,44(sp) + 2254: 6175 addi sp,sp,368 + 2256: 7472 .2byte 0x7472 + 2258: 745f 756f 7070 .byte 0x5f, 0x74, 0x6f, 0x75, 0x70, 0x70 + 225e: 7265 lui tp,0xffff9 + 2260: 65736163 bltu t1,s7,28a2 <__neorv32_ram_size+0x8a2> + 2264: 5500 lw s0,40(a0) + 2266: 5241 li tp,-16 + 2268: 5f54 lw a3,60(a4) + 226a: 4144 lw s1,4(a0) + 226c: 4154 lw a3,4(a0) + 226e: 465f 5245 0052 .byte 0x5f, 0x46, 0x45, 0x52, 0x52, 0x00 + 2274: 4155 li sp,21 + 2276: 5452 lw s0,52(sp) + 2278: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 227e: 4142 lw sp,16(sp) + 2280: 4455 li s0,21 + 2282: 3230 .2byte 0x3230 + 2284: 5500 lw s0,40(a0) + 2286: 5241 li tp,-16 + 2288: 5f54 lw a3,60(a4) + 228a: 4c525443 .4byte 0x4c525443 + 228e: 525f 5f58 4148 .byte 0x5f, 0x52, 0x58, 0x5f, 0x48, 0x41 + 2294: 464c lw a1,12(a2) + 2296: 5500 lw s0,40(a0) + 2298: 5241 li tp,-16 + 229a: 5f54 lw a3,60(a4) + 229c: 4144 lw s1,4(a0) + 229e: 4154 lw a3,4(a0) + 22a0: 415f 4156 4c49 .byte 0x5f, 0x41, 0x56, 0x41, 0x49, 0x4c + 22a6: 5500 lw s0,40(a0) + 22a8: 5241 li tp,-16 + 22aa: 5f54 lw a3,60(a4) + 22ac: 4c525443 .4byte 0x4c525443 + 22b0: 545f 5f58 4148 .byte 0x5f, 0x54, 0x58, 0x5f, 0x48, 0x41 + 22b6: 464c lw a1,12(a2) + 22b8: 5500 lw s0,40(a0) + 22ba: 5241 li tp,-16 + 22bc: 5f54 lw a3,60(a4) + 22be: 4c525443 .4byte 0x4c525443 + 22c2: 545f 5f58 5542 .byte 0x5f, 0x54, 0x58, 0x5f, 0x42, 0x55 + 22c8: 44005953 .4byte 0x44005953 + 22cc: 5441 li s0,-16 + 22ce: 0041 c.nop 16 + 22d0: 656e .2byte 0x656e + 22d2: 3376726f jal tp,69e08 <__neorv32_ram_size+0x67e08> + 22d6: 5f32 lw t5,44(sp) + 22d8: 6175 addi sp,sp,368 + 22da: 7472 .2byte 0x7472 + 22dc: 5f31 li t5,-20 + 22de: 7570 .2byte 0x7570 + 22e0: 6374 .2byte 0x6374 + 22e2: 5500 lw s0,40(a0) + 22e4: 5241 li tp,-16 + 22e6: 5f54 lw a3,60(a4) + 22e8: 4c525443 .4byte 0x4c525443 + 22ec: 525f 5f58 4d45 .byte 0x5f, 0x52, 0x58, 0x5f, 0x45, 0x4d + 22f2: 5450 lw a2,44(s0) + 22f4: 0059 c.nop 22 + 22f6: 656e .2byte 0x656e + 22f8: 3376726f jal tp,69e2e <__neorv32_ram_size+0x67e2e> + 22fc: 5f32 lw t5,44(sp) + 22fe: 6175 addi sp,sp,368 + 2300: 7472 .2byte 0x7472 + 2302: 5f31 li t5,-20 + 2304: 7570 .2byte 0x7570 + 2306: 7374 .2byte 0x7374 + 2308: 6e00 .2byte 0x6e00 + 230a: 6f65 lui t5,0x19 + 230c: 7672 .2byte 0x7672 + 230e: 755f3233 .4byte 0x755f3233 + 2312: 7261 lui tp,0xffff8 + 2314: 3174 .2byte 0x3174 + 2316: 655f 616e 6c62 .byte 0x5f, 0x65, 0x6e, 0x61, 0x62, 0x6c + 231c: 0065 c.nop 25 + 231e: 4155 li sp,21 + 2320: 5452 lw s0,52(sp) + 2322: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2328: 5f4d4953 .4byte 0x5f4d4953 + 232c: 4f4d li t5,19 + 232e: 4544 lw s1,12(a0) + 2330: 6e00 .2byte 0x6e00 + 2332: 6f65 lui t5,0x19 + 2334: 7672 .2byte 0x7672 + 2336: 755f3233 .4byte 0x755f3233 + 233a: 7261 lui tp,0xffff8 + 233c: 3174 .2byte 0x3174 + 233e: 705f 6972 746e .byte 0x5f, 0x70, 0x72, 0x69, 0x6e, 0x74 + 2344: 0066 c.slli zero,0x19 + 2346: 6175 addi sp,sp,368 + 2348: 7472 .2byte 0x7472 + 234a: 655f 006e 656e .byte 0x5f, 0x65, 0x6e, 0x00, 0x6e, 0x65 + 2350: 3376726f jal tp,69e86 <__neorv32_ram_size+0x67e86> + 2354: 5f32 lw t5,44(sp) + 2356: 6175 addi sp,sp,368 + 2358: 7472 .2byte 0x7472 + 235a: 5f30 lw a2,120(a4) + 235c: 72616863 bltu sp,t1,2a8c <__neorv32_ram_size+0xa8c> + 2360: 725f 6365 6965 .byte 0x5f, 0x72, 0x65, 0x63, 0x65, 0x69 + 2366: 6576 .2byte 0x6576 + 2368: 0064 addi s1,sp,12 + 236a: 5f6b6c63 bltu s6,s6,2962 <__neorv32_ram_size+0x962> + 236e: 7270 .2byte 0x7270 + 2370: 6e006373 csrrsi t1,0x6e0,0 + 2374: 6f65 lui t5,0x19 + 2376: 7672 .2byte 0x7672 + 2378: 755f3233 .4byte 0x755f3233 + 237c: 7261 lui tp,0xffff8 + 237e: 3174 .2byte 0x3174 + 2380: 735f 6163 006e .byte 0x5f, 0x73, 0x63, 0x61, 0x6e, 0x00 + 2386: 6c66 .2byte 0x6c66 + 2388: 635f776f jal a4,fa1bc <__neorv32_ram_size+0xf81bc> + 238c: 6e006e6f jal t3,8a6c <__neorv32_ram_size+0x6a6c> + 2390: 6d75 lui s10,0x1d + 2392: 745f 706d 5500 .byte 0x5f, 0x74, 0x6d, 0x70, 0x00, 0x55 + 2398: 5241 li tp,-16 + 239a: 5f54 lw a3,60(a4) + 239c: 4c525443 .4byte 0x4c525443 + 23a0: 435f 5354 6e00 .byte 0x5f, 0x43, 0x54, 0x53, 0x00, 0x6e + 23a6: 6d75 lui s10,0x1d + 23a8: 6562 .2byte 0x6562 + 23aa: 7372 .2byte 0x7372 + 23ac: 5500 lw s0,40(a0) + 23ae: 5241 li tp,-16 + 23b0: 5f54 lw a3,60(a4) + 23b2: 4144 lw s1,4(a0) + 23b4: 4154 lw a3,4(a0) + 23b6: 4f5f 4556 5252 .byte 0x5f, 0x4f, 0x56, 0x45, 0x52, 0x52 + 23bc: 6600 .2byte 0x6600 + 23be: 616d726f jal tp,d99d4 <__neorv32_ram_size+0xd79d4> + 23c2: 0074 addi a3,sp,12 + 23c4: 4155 li sp,21 + 23c6: 5452 lw s0,52(sp) + 23c8: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 23ce: 5f535443 .4byte 0x5f535443 + 23d2: 4e45 li t3,17 + 23d4: 5f00 lw s0,56(a4) + 23d6: 675f 756e 5f63 .byte 0x5f, 0x67, 0x6e, 0x75, 0x63, 0x5f + 23dc: 6176 .2byte 0x6176 + 23de: 6c5f 7369 0074 .byte 0x5f, 0x6c, 0x69, 0x73, 0x74, 0x00 + 23e4: 656e .2byte 0x656e + 23e6: 3376726f jal tp,69f1c <__neorv32_ram_size+0x67f1c> + 23ea: 5f32 lw t5,44(sp) + 23ec: 6175 addi sp,sp,368 + 23ee: 7472 .2byte 0x7472 + 23f0: 5f31 li t5,-20 + 23f2: 63746567 .4byte 0x63746567 + 23f6: 735f 6661 0065 .byte 0x5f, 0x73, 0x61, 0x66, 0x65, 0x00 + 23fc: 5f5f 656e 726f .byte 0x5f, 0x5f, 0x6e, 0x65, 0x6f, 0x72 + 2402: 3376 .2byte 0x3376 + 2404: 5f32 lw t5,44(sp) + 2406: 6175 addi sp,sp,368 + 2408: 7472 .2byte 0x7472 + 240a: 745f 686f 7865 .byte 0x5f, 0x74, 0x6f, 0x68, 0x65, 0x78 + 2410: 6c00 .2byte 0x6c00 + 2412: 6e65 lui t3,0x19 + 2414: 00687467 .4byte 0x687467 + 2418: 656e .2byte 0x656e + 241a: 3376726f jal tp,69f50 <__neorv32_ram_size+0x67f50> + 241e: 5f32 lw t5,44(sp) + 2420: 6175 addi sp,sp,368 + 2422: 7472 .2byte 0x7472 + 2424: 5f30 lw a2,120(a4) + 2426: 6e616373 csrrsi t1,0x6e6,2 + 242a: 6200 .2byte 0x6200 + 242c: 6675 lui a2,0x1d + 242e: 6566 .2byte 0x6566 + 2430: 0072 c.slli zero,0x1c + 2432: 6c727463 bgeu tp,t2,2afa <__neorv32_ram_size+0xafa> + 2436: 6700 .2byte 0x6700 + 2438: 7465 lui s0,0xffff9 + 243a: 72616863 bltu sp,t1,2b6a <__neorv32_ram_size+0xb6a> + 243e: 5500 lw s0,40(a0) + 2440: 5241 li tp,-16 + 2442: 5f54 lw a3,60(a4) + 2444: 4c525443 .4byte 0x4c525443 + 2448: 525f 5f58 5546 .byte 0x5f, 0x52, 0x58, 0x5f, 0x46, 0x55 + 244e: 4c4c lw a1,28(s0) + 2450: 6e00 .2byte 0x6e00 + 2452: 6f65 lui t5,0x19 + 2454: 7672 .2byte 0x7672 + 2456: 755f3233 .4byte 0x755f3233 + 245a: 7261 lui tp,0xffff8 + 245c: 3074 .2byte 0x3074 + 245e: 745f 5f78 7562 .byte 0x5f, 0x74, 0x78, 0x5f, 0x62, 0x75 + 2464: 4e007973 csrrci s2,0x4e0,0 + 2468: 4f45 li t5,17 + 246a: 5652 lw a2,52(sp) + 246c: 555f3233 .4byte 0x555f3233 + 2470: 5241 li tp,-16 + 2472: 5f54 lw a3,60(a4) + 2474: 4c525443 .4byte 0x4c525443 + 2478: 655f 756e 006d .byte 0x5f, 0x65, 0x6e, 0x75, 0x6d, 0x00 + 247e: 656e .2byte 0x656e + 2480: 3376726f jal tp,69fb6 <__neorv32_ram_size+0x67fb6> + 2484: 5f32 lw t5,44(sp) + 2486: 6175 addi sp,sp,368 + 2488: 7472 .2byte 0x7472 + 248a: 5f31 li t5,-20 + 248c: 0074 addi a3,sp,12 + 248e: 4155 li sp,21 + 2490: 5452 lw s0,52(sp) + 2492: 435f 5254 5f4c .byte 0x5f, 0x43, 0x54, 0x52, 0x4c, 0x5f + 2498: 5854 lw a3,52(s0) + 249a: 455f 504d 5954 .byte 0x5f, 0x45, 0x4d, 0x50, 0x54, 0x59 + 24a0: 6d00 .2byte 0x6d00 + 24a2: 7861 lui a6,0xffff8 + 24a4: 735f 7a69 0065 .byte 0x5f, 0x73, 0x69, 0x7a, 0x65, 0x00 + 24aa: 4155 li sp,21 + 24ac: 5452 lw s0,52(sp) + 24ae: 445f 5441 5f41 .byte 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f + 24b4: 534d li t1,-13 + 24b6: 0042 c.slli zero,0x10 + 24b8: 454e lw a0,208(sp) + 24ba: 3356524f .4byte 0x3356524f + 24be: 5f32 lw t5,44(sp) + 24c0: 4155 li sp,21 + 24c2: 5452 lw s0,52(sp) + 24c4: 445f 5441 5f41 .byte 0x5f, 0x44, 0x41, 0x54, 0x41, 0x5f + 24ca: 6e65 lui t3,0x19 + 24cc: 6d75 lui s10,0x1d + 24ce: 5500 lw s0,40(a0) + 24d0: 5241 li tp,-16 + 24d2: 5f54 lw a3,60(a4) + 24d4: 4c525443 .4byte 0x4c525443 + 24d8: 525f 5f58 5249 .byte 0x5f, 0x52, 0x58, 0x5f, 0x49, 0x52 + 24de: 0051 c.nop 20 + 24e0: 5f6d6973 csrrsi s2,0x5f6,26 + 24e4: 6f6d lui t5,0x1b + 24e6: 6564 .2byte 0x6564 + 24e8: 6300 .2byte 0x6300 + 24ea: 6f6c .2byte 0x6f6c + 24ec: 73006b63 bltu zero,a6,2c22 <__neorv32_ram_size+0xc22> + 24f0: 7274 .2byte 0x7274 + 24f2: 6e69 lui t3,0x1a + 24f4: 75625f67 .4byte 0x75625f67 + 24f8: 0066 c.slli zero,0x19 + 24fa: 6c66 .2byte 0x6c66 + 24fc: 635f776f jal a4,fa330 <__neorv32_ram_size+0xf8330> + 2500: 72746e6f jal t3,49426 <__neorv32_ram_size+0x47426> + 2504: 55006c6f jal s8,8a54 <__neorv32_ram_size+0x6a54> + 2508: 5241 li tp,-16 + 250a: 5f54 lw a3,60(a4) + 250c: 4c525443 .4byte 0x4c525443 + 2510: 425f 5541 3144 .byte 0x5f, 0x42, 0x41, 0x55, 0x44, 0x31 + 2516: 0030 addi a2,sp,8 + 2518: 656e .2byte 0x656e + 251a: 3376726f jal tp,6a050 <__neorv32_ram_size+0x68050> + 251e: 5f32 lw t5,44(sp) + 2520: 6175 addi sp,sp,368 + 2522: 7472 .2byte 0x7472 + 2524: 5f31 li t5,-20 + 2526: 7874 .2byte 0x7874 + 2528: 625f 7375 0079 .byte 0x5f, 0x62, 0x75, 0x73, 0x79, 0x00 + 252e: 6361 lui t1,0x18 + 2530: 6974 .2byte 0x6974 + 2532: 656d lui a0,0x1b + 2534: 5f00 lw s0,56(a4) + 2536: 6f5f 6666 745f .byte 0x5f, 0x6f, 0x66, 0x66, 0x5f, 0x74 + 253c: 5f00 lw s0,56(a4) + 253e: 675f 6469 745f .byte 0x5f, 0x67, 0x69, 0x64, 0x5f, 0x74 + 2544: 7200 .2byte 0x7200 + 2546: 746d lui s0,0xffffb + 2548: 0070 addi a2,sp,12 + 254a: 635f7473 csrrci s0,0x635,30 + 254e: 6974 .2byte 0x6974 + 2550: 006d c.nop 27 + 2552: 6f5f 6570 616e .byte 0x5f, 0x6f, 0x70, 0x65, 0x6e, 0x61 + 2558: 0074 addi a3,sp,12 + 255a: 665f 7473 7461 .byte 0x5f, 0x66, 0x73, 0x74, 0x61, 0x74 + 2560: 7461 lui s0,0xffff8 + 2562: 6400 .2byte 0x6400 + 2564: 6c667473 csrrci s0,0x6c6,12 + 2568: 6761 lui a4,0x18 + 256a: 7500 .2byte 0x7500 + 256c: 696e .2byte 0x696e + 256e: 706d c.lui zero,0xffffb + 2570: 656c .2byte 0x656c + 2572: 656d lui a0,0x1b + 2574: 746e .2byte 0x746e + 2576: 6465 lui s0,0x19 + 2578: 735f 7379 6163 .byte 0x5f, 0x73, 0x79, 0x73, 0x63, 0x61 + 257e: 6c6c .2byte 0x6c6c + 2580: 7000 .2byte 0x7000 + 2582: 7461 lui s0,0xffff8 + 2584: 0068 addi a0,sp,12 + 2586: 616e .2byte 0x616e + 2588: 6f6e .2byte 0x6f6e + 258a: 65656c73 csrrsi s8,0x656,10 + 258e: 0070 addi a2,sp,12 + 2590: 6d74 .2byte 0x6d74 + 2592: 75635f73 csrrwi t5,0x756,6 + 2596: 6974 .2byte 0x6974 + 2598: 656d lui a0,0x1b + 259a: 5f00 lw s0,56(a4) + 259c: 685f 6165 5f70 .byte 0x5f, 0x68, 0x65, 0x61, 0x70, 0x5f + 25a2: 6e65 lui t3,0x19 + 25a4: 0064 addi s1,sp,12 + 25a6: 5f5f 6e69 5f74 .byte 0x5f, 0x5f, 0x69, 0x6e, 0x74, 0x5f + 25ac: 656c .2byte 0x656c + 25ae: 7361 lui t1,0xffff8 + 25b0: 3674 .2byte 0x3674 + 25b2: 5f34 lw a3,120(a4) + 25b4: 0074 addi a3,sp,12 + 25b6: 695f7473 csrrci s0,0x695,30 + 25ba: 6f6e .2byte 0x6f6e + 25bc: 5f00 lw s0,56(a4) + 25be: 6d5f 646f 5f65 .byte 0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x5f + 25c4: 0074 addi a3,sp,12 + 25c6: 665f 6361 6563 .byte 0x5f, 0x66, 0x61, 0x63, 0x63, 0x65 + 25cc: 74617373 csrrci t1,0x746,2 + 25d0: 6700 .2byte 0x6700 + 25d2: 6f72 .2byte 0x6f72 + 25d4: 7075 c.lui zero,0xffffd + 25d6: 5f00 lw s0,56(a4) + 25d8: 625f 6b6c 6e63 .byte 0x5f, 0x62, 0x6c, 0x6b, 0x63, 0x6e + 25de: 5f74 lw a3,124(a4) + 25e0: 0074 addi a3,sp,12 + 25e2: 735f 7379 6f63 .byte 0x5f, 0x73, 0x79, 0x73, 0x63, 0x6f + 25e8: 666e .2byte 0x666e + 25ea: 7400 .2byte 0x7400 + 25ec: 736d lui t1,0xffffb + 25ee: 735f 6974 656d .byte 0x5f, 0x73, 0x74, 0x69, 0x6d, 0x65 + 25f4: 5f00 lw s0,56(a4) + 25f6: 736c .2byte 0x736c + 25f8: 6565 lui a0,0x19 + 25fa: 665f006b .4byte 0x665f006b + 25fe: 74617473 csrrci s0,0x746,2 + 2602: 5f00 lw s0,56(a4) + 2604: 70746567 .4byte 0x70746567 + 2608: 6469 lui s0,0x1a + 260a: 7300 .2byte 0x7300 + 260c: 5f74 lw a3,124(a4) + 260e: 7461 lui s0,0xffff8 + 2610: 6d69 lui s10,0x1a + 2612: 6300 .2byte 0x6300 + 2614: 6f6c .2byte 0x6f6c + 2616: 745f6b63 bltu t5,t0,2d6c <__neorv32_ram_size+0xd6c> + 261a: 7200 .2byte 0x7200 + 261c: 7471 lui s0,0xffffc + 261e: 0070 addi a2,sp,12 + 2620: 6974 .2byte 0x6974 + 2622: 656d lui a0,0x1b + 2624: 6f7a .2byte 0x6f7a + 2626: 656e .2byte 0x656e + 2628: 6d00 .2byte 0x6d00 + 262a: 6c69 lui s8,0x1a + 262c: 696c .2byte 0x696c + 262e: 6d74 .2byte 0x6d74 + 2630: 7300 .2byte 0x7300 + 2632: 5f74 lw a3,124(a4) + 2634: 6c62 .2byte 0x6c62 + 2636: 736b636f jal t1,b8d6c <__neorv32_ram_size+0xb6d6c> + 263a: 7300 .2byte 0x7300 + 263c: 5f74 lw a3,124(a4) + 263e: 6975 lui s2,0x1d + 2640: 0064 addi s1,sp,12 + 2642: 735f7473 csrrci s0,mhpmevent21h,30 + 2646: 6170 .2byte 0x6170 + 2648: 6572 .2byte 0x6572 + 264a: 0034 addi a3,sp,8 + 264c: 635f 6f68 6e77 .byte 0x5f, 0x63, 0x68, 0x6f, 0x77, 0x6e + 2652: 5f00 lw s0,56(a4) + 2654: 736f6c63 bltu t5,s6,2d8c <__neorv32_ram_size+0xd8c> + 2658: 0065 c.nop 25 + 265a: 7475 lui s0,0xffffd + 265c: 6d69 lui s10,0x1a + 265e: 7562 .2byte 0x7562 + 2660: 0066 c.slli zero,0x19 + 2662: 5f5f 7573 6573 .byte 0x5f, 0x5f, 0x73, 0x75, 0x73, 0x65 + 2668: 646e6f63 bltu t3,t1,2cc6 <__neorv32_ram_size+0xcc6> + 266c: 00745f73 csrrwi t5,0x7,8 + 2670: 655f 6978 0074 .byte 0x5f, 0x65, 0x78, 0x69, 0x74, 0x00 + 2676: 5f646c6f jal s8,48c6c <__neorv32_ram_size+0x46c6c> + 267a: 7262 .2byte 0x7262 + 267c: 5f5f006b .4byte 0x5f5f006b + 2680: 6c6e .2byte 0x6c6e + 2682: 6e69 lui t3,0x1a + 2684: 00745f6b .4byte 0x745f6b + 2688: 72616863 bltu sp,t1,2db8 <__neorv32_ram_size+0xdb8> + 268c: 705f 7274 5f00 .byte 0x5f, 0x70, 0x74, 0x72, 0x00, 0x5f + 2692: 63746567 .4byte 0x63746567 + 2696: 5f006477 .4byte 0x5f006477 + 269a: 7369 lui t1,0xffffa + 269c: 7461 lui s0,0xffff8 + 269e: 7974 .2byte 0x7974 + 26a0: 7400 .2byte 0x7400 + 26a2: 6d69 lui s10,0x1a + 26a4: 7665 lui a2,0xffff9 + 26a6: 6c61 lui s8,0x18 + 26a8: 6500 .2byte 0x6500 + 26aa: 7272 .2byte 0x7272 + 26ac: 6f6e .2byte 0x6f6e + 26ae: 7300 .2byte 0x7300 + 26b0: 5f74 lw a3,124(a4) + 26b2: 657a6973 csrrsi s2,0x657,20 + 26b6: 7000 .2byte 0x7000 + 26b8: 7274 .2byte 0x7274 + 26ba: 6964 .2byte 0x6964 + 26bc: 6666 .2byte 0x6666 + 26be: 745f 5f00 6863 .byte 0x5f, 0x74, 0x00, 0x5f, 0x63, 0x68 + 26c4: 6964 .2byte 0x6964 + 26c6: 0072 c.slli zero,0x1c + 26c8: 7674 .2byte 0x7674 + 26ca: 6e5f 6573 0063 .byte 0x5f, 0x6e, 0x73, 0x65, 0x63, 0x00 + 26d0: 5f5f 6564 5f76 .byte 0x5f, 0x5f, 0x64, 0x65, 0x76, 0x5f + 26d6: 0074 addi a3,sp,12 + 26d8: 735f 6174 0074 .byte 0x5f, 0x73, 0x74, 0x61, 0x74, 0x00 + 26de: 7674 .2byte 0x7674 + 26e0: 735f 6365 5f00 .byte 0x5f, 0x73, 0x65, 0x63, 0x00, 0x5f + 26e6: 6f66 .2byte 0x6f66 + 26e8: 6b72 .2byte 0x6b72 + 26ea: 5f00 lw s0,56(a4) + 26ec: 74696177 .4byte 0x74696177 + 26f0: 5f00 lw s0,56(a4) + 26f2: 625f 6b6c 6973 .byte 0x5f, 0x62, 0x6c, 0x6b, 0x73, 0x69 + 26f8: 657a .2byte 0x657a + 26fa: 745f 6f00 646c .byte 0x5f, 0x74, 0x00, 0x6f, 0x6c, 0x64 + 2700: 6e5f 6d61 0065 .byte 0x5f, 0x6e, 0x61, 0x6d, 0x65, 0x00 + 2706: 7065 c.lui zero,0xffff9 + 2708: 7274 .2byte 0x7274 + 270a: 5f00 lw s0,56(a4) + 270c: 6f6d6863 bltu s10,s6,2dfc <__neorv32_ram_size+0xdfc> + 2710: 0064 addi s1,sp,12 + 2712: 6e5f7473 csrrci s0,0x6e5,30 + 2716: 696c .2byte 0x696c + 2718: 6b6e .2byte 0x6b6e + 271a: 5f00 lw s0,56(a4) + 271c: 7466 .2byte 0x7466 + 271e: 6d69 lui s10,0x1a + 2720: 0065 c.nop 25 + 2722: 655f 6578 7663 .byte 0x5f, 0x65, 0x78, 0x65, 0x63, 0x76 + 2728: 0065 c.nop 25 + 272a: 7865 lui a6,0xffff9 + 272c: 7469 lui s0,0xffffa + 272e: 735f 6174 7574 .byte 0x5f, 0x73, 0x74, 0x61, 0x74, 0x75 + 2734: 69660073 .4byte 0x69660073 + 2738: 656c .2byte 0x656c + 273a: 7300 .2byte 0x7300 + 273c: 5f74 lw a3,124(a4) + 273e: 6c62 .2byte 0x6c62 + 2740: 7a69736b .4byte 0x7a69736b + 2744: 0065 c.nop 25 + 2746: 6d74 .2byte 0x6d74 + 2748: 74755f73 csrrwi t5,0x747,10 + 274c: 6d69 lui s10,0x1a + 274e: 0065 c.nop 25 + 2750: 6974 .2byte 0x6974 + 2752: 656d lui a0,0x1b + 2754: 63657073 csrci 0x636,10 + 2758: 7200 .2byte 0x7200 + 275a: 6165 addi sp,sp,112 + 275c: 5f64 lw s1,124(a4) + 275e: 00746e63 bltu s0,t2,277a <__neorv32_ram_size+0x77a> + 2762: 5f5f 6e69 5f6f .byte 0x5f, 0x5f, 0x69, 0x6e, 0x6f, 0x5f + 2768: 0074 addi a3,sp,12 + 276a: 7674 .2byte 0x7674 + 276c: 755f 6573 0063 .byte 0x5f, 0x75, 0x73, 0x65, 0x63, 0x00 + 2772: 656e776f jal a4,e9dc8 <__neorv32_ram_size+0xe7dc8> + 2776: 0072 c.slli zero,0x1c + 2778: 725f7473 csrrci s0,mhpmevent5h,30 + 277c: 6564 .2byte 0x6564 + 277e: 0076 c.slli zero,0x1d + 2780: 6964 .2byte 0x6964 + 2782: 6672 .2byte 0x6672 + 2784: 0064 addi s1,sp,12 + 2786: 6f5f 6570 006e .byte 0x5f, 0x6f, 0x70, 0x65, 0x6e, 0x00 + 278c: 6f6d lui t5,0x1b + 278e: 7464 .2byte 0x7464 + 2790: 6d69 lui s10,0x1a + 2792: 0065 c.nop 25 + 2794: 5f5f 6975 5f64 .byte 0x5f, 0x5f, 0x75, 0x69, 0x64, 0x5f + 279a: 0074 addi a3,sp,12 + 279c: 6d5f7473 csrrci s0,0x6d5,30 + 27a0: 0065646f jal s0,587a6 <__neorv32_ram_size+0x567a6> + 27a4: 656e .2byte 0x656e + 27a6: 616e5f77 .4byte 0x616e5f77 + 27aa: 656d lui a0,0x1b + 27ac: 5f00 lw s0,56(a4) + 27ae: 6c6c696b .4byte 0x6c6c696b + 27b2: 7300 .2byte 0x7300 + 27b4: 5f74 lw a3,124(a4) + 27b6: 00646967 .4byte 0x646967 + 27ba: 615f 6363 7365 .byte 0x5f, 0x61, 0x63, 0x63, 0x65, 0x73 + 27c0: 6d740073 .4byte 0x6d740073 + 27c4: 73635f73 csrrwi t5,mhpmevent22h,6 + 27c8: 6974 .2byte 0x6974 + 27ca: 656d lui a0,0x1b + 27cc: 5f00 lw s0,56(a4) + 27ce: 74746567 .4byte 0x74746567 + 27d2: 6d69 lui s10,0x1a + 27d4: 6f65 lui t5,0x19 + 27d6: 6466 .2byte 0x6466 + 27d8: 7961 lui s2,0xffff8 + 27da: 6100 .2byte 0x6100 + 27dc: 6772 .2byte 0x6772 + 27de: 0076 c.slli zero,0x1d + 27e0: 5f5f 6568 7061 .byte 0x5f, 0x5f, 0x68, 0x65, 0x61, 0x70 + 27e6: 735f 6174 7472 .byte 0x5f, 0x73, 0x74, 0x61, 0x72, 0x74 + 27ec: 7400 .2byte 0x7400 + 27ee: 6d69 lui s10,0x1a + 27f0: 6265 lui tp,0x19 + 27f2: 7300 .2byte 0x7300 + 27f4: 5f74 lw a3,124(a4) + 27f6: 6564 .2byte 0x6564 + 27f8: 0076 c.slli zero,0x1d + 27fa: 735f 6973 657a .byte 0x5f, 0x73, 0x73, 0x69, 0x7a, 0x65 + 2800: 745f 5f00 6974 .byte 0x5f, 0x74, 0x00, 0x5f, 0x74, 0x69 + 2806: 656d lui a0,0x1b + 2808: 6c660073 .4byte 0x6c660073 + 280c: 6761 lui a4,0x18 + 280e: 74730073 .4byte 0x74730073 + 2812: 6d5f 6974 006d .byte 0x5f, 0x6d, 0x74, 0x69, 0x6d, 0x00 + 2818: 755f 6c6e 6e69 .byte 0x5f, 0x75, 0x6e, 0x6c, 0x69, 0x6e + 281e: 6c5f006b .4byte 0x6c5f006b + 2822: 6e69 lui t3,0x1a + 2824: 6c5f006b .4byte 0x6c5f006b + 2828: 74617473 csrrci s0,0x746,2 + 282c: 6900 .2byte 0x6900 + 282e: 636e .2byte 0x636e + 2830: 0072 c.slli zero,0x1c + 2832: 735f 7262 006b .byte 0x5f, 0x73, 0x62, 0x72, 0x6b, 0x00 + 2838: 30747263 bgeu s0,t2,2b3c <__neorv32_ram_size+0xb3c> + 283c: 532e lw t1,232(sp) + 283e: 2f00 .2byte 0x2f00 + 2840: 6f68 .2byte 0x6f68 + 2842: 656d lui a0,0x1b + 2844: 7465732f .4byte 0x7465732f + 2848: 2f69 jal 2fe2 <__neorv32_ram_size+0xfe2> + 284a: 6544 .2byte 0x6544 + 284c: 6f746b73 csrrsi s6,0x6f7,8 + 2850: 2f70 .2byte 0x2f70 + 2852: 7250 .2byte 0x7250 + 2854: 74656a6f jal s4,58f9a <__neorv32_ram_size+0x56f9a> + 2858: 535f 5445 5f49 .byte 0x5f, 0x53, 0x45, 0x54, 0x49, 0x5f + 285e: 4952 lw s2,20(sp) + 2860: 562d4353 .4byte 0x562d4353 + 2864: 6f656e2f .4byte 0x6f656e2f + 2868: 7672 .2byte 0x7672 + 286a: 732f3233 .4byte 0x732f3233 + 286e: 78652f77 .4byte 0x78652f77 + 2872: 6d61 lui s10,0x18 + 2874: 6c70 .2byte 0x6c70 + 2876: 2f65 jal 302e <__neorv32_ram_size+0x102e> + 2878: 6864 .2byte 0x6864 + 287a: 7972 .2byte 0x7972 + 287c: 6e6f7473 csrrci s0,0x6e6,30 + 2880: 0065 c.nop 25 + 2882: 20554e47 .4byte 0x20554e47 + 2886: 5341 li t1,-16 + 2888: 3220 .2byte 0x3220 + 288a: 332e .2byte 0x332e + 288c: 0039 c.nop 14 + 288e: 6d6f682f .4byte 0x6d6f682f + 2892: 2f65 jal 304a <__neorv32_ram_size+0x104a> + 2894: 69746573 csrrsi a0,0x697,8 + 2898: 7369722f .4byte 0x7369722f + 289c: 672d7663 bgeu s10,s2,2f08 <__neorv32_ram_size+0xf08> + 28a0: 756e .2byte 0x756e + 28a2: 742d lui s0,0xfffeb + 28a4: 636c6f6f jal t5,c8eda <__neorv32_ram_size+0xc6eda> + 28a8: 6168 .2byte 0x6168 + 28aa: 6e69 lui t3,0x1a + 28ac: 6363672f .4byte 0x6363672f + 28b0: 62696c2f .4byte 0x62696c2f + 28b4: 2f636367 .4byte 0x2f636367 + 28b8: 666e6f63 bltu t3,t1,2f36 <__neorv32_ram_size+0xf36> + 28bc: 6769 lui a4,0x1a + 28be: 7369722f .4byte 0x7369722f + 28c2: 642f7663 bgeu t5,sp,2f0e <__neorv32_ram_size+0xf0e> + 28c6: 7669 lui a2,0xffffa + 28c8: 532e lw t1,232(sp) + 28ca: 2f00 .2byte 0x2f00 + 28cc: 6f68 .2byte 0x6f68 + 28ce: 656d lui a0,0x1b + 28d0: 7465732f .4byte 0x7465732f + 28d4: 2f69 jal 306e <__neorv32_ram_size+0x106e> + 28d6: 6972 .2byte 0x6972 + 28d8: 2d766373 csrrsi t1,0x2d7,12 + 28dc: 2d756e67 .4byte 0x2d756e67 + 28e0: 6f74 .2byte 0x6f74 + 28e2: 68636c6f jal s8,38f68 <__neorv32_ram_size+0x36f68> + 28e6: 6961 lui s2,0x18 + 28e8: 2f6e .2byte 0x2f6e + 28ea: 7562 .2byte 0x7562 + 28ec: 6c69 lui s8,0x1a + 28ee: 2d64 .2byte 0x2d64 + 28f0: 2d636367 .4byte 0x2d636367 + 28f4: 656e .2byte 0x656e + 28f6: 62696c77 .4byte 0x62696c77 + 28fa: 732d lui t1,0xfffeb + 28fc: 6174 .2byte 0x6174 + 28fe: 2f326567 .4byte 0x2f326567 + 2902: 6972 .2byte 0x6972 + 2904: 33766373 csrrsi t1,mhpmevent23,12 + 2908: 2d32 .2byte 0x2d32 + 290a: 6e75 lui t3,0x1d + 290c: 776f6e6b .4byte 0x776f6e6b + 2910: 2d6e .2byte 0x2d6e + 2912: 6c65 lui s8,0x19 + 2914: 2f66 .2byte 0x2f66 + 2916: 696c .2byte 0x696c + 2918: 6762 .2byte 0x6762 + 291a: 5f006363 bltu zero,a6,2f00 <__neorv32_ram_size+0xf00> + 291e: 645f 7669 6973 .byte 0x5f, 0x64, 0x69, 0x76, 0x73, 0x69 + 2924: 5f5f0033 .4byte 0x5f5f0033 + 2928: 6968 .2byte 0x6968 + 292a: 6464 .2byte 0x6464 + 292c: 6e65 lui t3,0x19 + 292e: 5f5f 755f 6964 .byte 0x5f, 0x5f, 0x5f, 0x75, 0x64, 0x69 + 2934: 7376 .2byte 0x7376 + 2936: 3369 jal 26c0 <__neorv32_ram_size+0x6c0> + 2938: 5f00 lw s0,56(a4) + 293a: 6d5f 646f 6973 .byte 0x5f, 0x6d, 0x6f, 0x64, 0x73, 0x69 + 2940: 33 00 Address 0x0000000000002940 is out of bounds. + + +Disassembly of section .debug_loclists: + +00000000 <.debug_loclists>: + 0: 000000c7 .4byte 0xc7 + 4: 0005 c.nop 1 + 6: 0004 .2byte 0x4 + 8: 0000 unimp + a: 0000 unimp + c: 00020407 .4byte 0x20407 + 10: 5c00 lw s0,56(s0) + 12: 0002 c.slli64 zero + 14: 0100 addi s0,sp,128 + 16: 0059 c.nop 22 + 18: 00022007 .4byte 0x22007 + 1c: 2800 .2byte 0x2800 + 1e: 0002 c.slli64 zero + 20: 0100 addi s0,sp,128 + 22: 005a c.slli zero,0x16 + 24: 00022007 .4byte 0x22007 + 28: 2800 .2byte 0x2800 + 2a: 0002 c.slli64 zero + 2c: 0600 addi s0,sp,768 + 2e: 007a c.slli zero,0x1e + 30: 0079 c.nop 30 + 32: 9f1c .2byte 0x9f1c + 34: 00022807 .4byte 0x22807 + 38: 2b00 .2byte 0x2b00 + 3a: 0002 c.slli64 zero + 3c: 0100 addi s0,sp,128 + 3e: 005a c.slli zero,0x16 + 40: 0001fc07 .4byte 0x1fc07 + 44: 3c00 .2byte 0x3c00 + 46: 0002 c.slli64 zero + 48: 0100 addi s0,sp,128 + 4a: 0758 addi a4,sp,900 + 4c: 023c addi a5,sp,264 + 4e: 0000 unimp + 50: 0000023f 3f075b01 .8byte 0x3f075b010000023f + 58: 0002 c.slli64 zero + 5a: 5800 lw s0,48(s0) + 5c: 0002 c.slli64 zero + 5e: 0300 addi s0,sp,384 + 60: 4078 lw a4,68(s0) + 62: 009f f007 0001 .byte 0x9f, 0x00, 0x07, 0xf0, 0x01, 0x00 + 68: fc00 .2byte 0xfc00 + 6a: 0001 nop + 6c: 0100 addi s0,sp,128 + 6e: 075a slli a4,a4,0x16 + 70: 01fc addi a5,sp,204 + 72: 0000 unimp + 74: 0260 addi s0,sp,268 + 76: 0000 unimp + 78: 6201 .2byte 0x6201 + 7a: 0700 addi s0,sp,896 + 7c: 01f0 addi a2,sp,204 + 7e: 0000 unimp + 80: 01fc addi a5,sp,204 + 82: 0000 unimp + 84: 3002 .2byte 0x3002 + 86: 009f 0407 0002 .byte 0x9f, 0x00, 0x07, 0x04, 0x02, 0x00 + 8c: 0800 addi s0,sp,16 + 8e: 0002 c.slli64 zero + 90: 0200 addi s0,sp,256 + 92: 9f30 .2byte 0x9f30 + 94: 00020807 .4byte 0x20807 + 98: 1400 addi s0,sp,544 + 9a: 0002 c.slli64 zero + 9c: 0500 addi s0,sp,640 + 9e: 833a mv t1,a4 + a0: 1c00 addi s0,sp,560 + a2: 079f 0214 0000 .byte 0x9f, 0x07, 0x14, 0x02, 0x00, 0x00 + a8: 0218 addi a4,sp,256 + aa: 0000 unimp + ac: 3905 jal fffffcdc <__crt0_stack_begin+0x7fffdce0> + ae: 9f1c0083 lb ra,-1551(s8) # 189f1 <__neorv32_ram_size+0x169f1> + b2: 0700 addi s0,sp,896 + b4: 0278 addi a4,sp,268 + b6: 0000 unimp + b8: 027c addi a5,sp,268 + ba: 0000 unimp + bc: 3002 .2byte 0x3002 + be: 079f 027c 0000 .byte 0x9f, 0x07, 0x7c, 0x02, 0x00, 0x00 + c4: 0298 addi a4,sp,320 + c6: 0000 unimp + c8: 5f01 li t5,-32 + ca: 0300 addi s0,sp,384 + cc: 0009 c.nop 2 + ce: 0500 addi s0,sp,640 + d0: 0400 addi s0,sp,512 + d2: 0000 unimp + d4: 0000 unimp + d6: 0700 addi s0,sp,896 + d8: 08c4 addi s1,sp,84 + da: 0000 unimp + dc: 000008eb .4byte 0x8eb + e0: 5a01 li s4,-32 + e2: 0008eb07 .4byte 0x8eb07 + e6: 1800 addi s0,sp,48 + e8: 0009 c.nop 2 + ea: 0400 addi s0,sp,512 + ec: 9f5a01a3 sb s5,-1565(s4) + f0: 00091807 .4byte 0x91807 + f4: 1c00 addi s0,sp,560 + f6: 0009 c.nop 2 + f8: 0100 addi s0,sp,128 + fa: 075a slli a4,a4,0x16 + fc: 091c addi a5,sp,144 + fe: 0000 unimp + 100: 0920 addi s0,sp,152 + 102: 0000 unimp + 104: a304 .2byte 0xa304 + 106: 5a01 li s4,-32 + 108: 079f 0920 0000 .byte 0x9f, 0x07, 0x20, 0x09, 0x00, 0x00 + 10e: 0924 addi s1,sp,152 + 110: 0000 unimp + 112: 5a01 li s4,-32 + 114: 00092407 .4byte 0x92407 + 118: 2800 .2byte 0x2800 + 11a: 0009 c.nop 2 + 11c: 0400 addi s0,sp,512 + 11e: 9f5a01a3 sb s5,-1565(s4) + 122: 0700 addi s0,sp,896 + 124: 08c8 addi a0,sp,84 + 126: 0000 unimp + 128: 000008eb .4byte 0x8eb + 12c: 5c01 li s8,-32 + 12e: 0008eb07 .4byte 0x8eb07 + 132: 1400 addi s0,sp,544 + 134: 0009 c.nop 2 + 136: 0200 addi s0,sp,256 + 138: 6c91 lui s9,0x4 + 13a: 00091407 .4byte 0x91407 + 13e: 1800 addi s0,sp,48 + 140: 0009 c.nop 2 + 142: 0200 addi s0,sp,256 + 144: 6c72 .2byte 0x6c72 + 146: 00091807 .4byte 0x91807 + 14a: 2800 .2byte 0x2800 + 14c: 0009 c.nop 2 + 14e: 0100 addi s0,sp,128 + 150: 005c addi a5,sp,4 + 152: 0008c807 .4byte 0x8c807 + 156: eb00 .2byte 0xeb00 + 158: 0008 .2byte 0x8 + 15a: 0900 addi s0,sp,144 + 15c: 007c addi a5,sp,12 + 15e: 000c .2byte 0xc + 160: 0001 nop + 162: 1a40 addi s0,sp,308 + 164: 079f 08eb 0000 .byte 0x9f, 0x07, 0xeb, 0x08, 0x00, 0x00 + 16a: 0914 addi a3,sp,144 + 16c: 0000 unimp + 16e: 910a add sp,sp,sp + 170: 066c addi a1,sp,780 + 172: 000c .2byte 0xc + 174: 0001 nop + 176: 1a40 addi s0,sp,308 + 178: 079f 0914 0000 .byte 0x9f, 0x07, 0x14, 0x09, 0x00, 0x00 + 17e: 0918 addi a4,sp,144 + 180: 0000 unimp + 182: 720a .2byte 0x720a + 184: 066c addi a1,sp,780 + 186: 000c .2byte 0xc + 188: 0001 nop + 18a: 1a40 addi s0,sp,308 + 18c: 079f 0918 0000 .byte 0x9f, 0x07, 0x18, 0x09, 0x00, 0x00 + 192: 0928 addi a0,sp,152 + 194: 0000 unimp + 196: 7c09 lui s8,0xfffe2 + 198: 0c00 addi s0,sp,528 + 19a: 0100 addi s0,sp,128 + 19c: 4000 lw s0,0(s0) + 19e: 9f1a add t5,t5,t1 + 1a0: 0700 addi s0,sp,896 + 1a2: 08c4 addi s1,sp,84 + 1a4: 0000 unimp + 1a6: 08c8 addi a0,sp,84 + 1a8: 0000 unimp + 1aa: 0a04 addi s1,sp,272 + 1ac: 0301 addi t1,t1,0 # fffeb000 <__crt0_stack_begin+0x7ffe9004> + 1ae: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1b4: 0000 unimp + 1b6: 0000 unimp + 1b8: 0200 addi s0,sp,256 + 1ba: 9f30 .2byte 0x9f30 + 1bc: 00000007 .4byte 0x7 + 1c0: 0000 unimp + 1c2: 0000 unimp + 1c4: 0100 addi s0,sp,128 + 1c6: 0062 c.slli zero,0x18 + 1c8: 00000007 .4byte 0x7 + 1cc: 0000 unimp + 1ce: 0000 unimp + 1d0: 0200 addi s0,sp,256 + 1d2: 9f30 .2byte 0x9f30 + 1d4: 00000007 .4byte 0x7 + 1d8: 0000 unimp + 1da: 0000 unimp + 1dc: 0500 addi s0,sp,640 + 1de: 8440 .2byte 0x8440 + 1e0: 1c00 addi s0,sp,560 + 1e2: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 1e8: 0000 unimp + 1ea: 0000 unimp + 1ec: 3f05 jal 11c <__crt0_call_destructors_loop+0x8> + 1ee: 0084 addi s1,sp,64 + 1f0: 9f1c .2byte 0x9f1c + 1f2: 0700 addi s0,sp,896 + ... + 1fc: 5901 li s2,-32 + 1fe: 00000007 .4byte 0x7 + 202: 0000 unimp + 204: 0000 unimp + 206: 0100 addi s0,sp,128 + 208: 0059 c.nop 22 + 20a: 00000007 .4byte 0x7 + 20e: 0000 unimp + 210: 0000 unimp + 212: 0300 addi s0,sp,384 + 214: 2008 .2byte 0x2008 + 216: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 21c: 0000 unimp + 21e: 0000 unimp + 220: 5a01 li s4,-32 + 222: 0700 addi s0,sp,896 + 224: 04f4 addi a3,sp,588 + 226: 0000 unimp + 228: 0504 addi s1,sp,640 + 22a: 0000 unimp + 22c: 5a01 li s4,-32 + 22e: 00050407 .4byte 0x50407 + 232: 5800 lw s0,48(s0) + 234: 0005 c.nop 1 + 236: 0100 addi s0,sp,128 + 238: 0762 slli a4,a4,0x18 + 23a: 0558 addi a4,sp,644 + 23c: 0000 unimp + 23e: 0564 addi s1,sp,652 + 240: 0000 unimp + 242: a304 .2byte 0xa304 + 244: 5a01 li s4,-32 + 246: 009f 2407 0005 .byte 0x9f, 0x00, 0x07, 0x24, 0x05, 0x00 + 24c: 2c00 .2byte 0x2c00 + 24e: 0005 c.nop 1 + 250: 0200 addi s0,sp,256 + 252: 9f30 .2byte 0x9f30 + 254: 0700 addi s0,sp,896 + 256: 052c addi a1,sp,648 + 258: 0000 unimp + 25a: 0540 addi s0,sp,644 + 25c: 0000 unimp + 25e: 8208 .2byte 0x8208 + 260: 7800 .2byte 0x7800 + 262: 2500 .2byte 0x2500 + 264: 079f1a3f 00000540 .8byte 0x540079f1a3f + 26c: 0550 addi a2,sp,644 + 26e: 0000 unimp + 270: 8208 .2byte 0x8208 + 272: 7800 .2byte 0x7800 + 274: 2504 .2byte 0x2504 + 276: 009f1a3f 00000007 .8byte 0x7009f1a3f + 27e: 0000 unimp + 280: 0000 unimp + 282: 0100 addi s0,sp,128 + 284: 075a slli a4,a4,0x16 + ... + 28e: 5801 li a6,-32 + 290: 00000007 .4byte 0x7 + 294: 0000 unimp + 296: 0000 unimp + 298: 0400 addi s0,sp,512 + 29a: 9f5a01a3 sb s5,-1565(s4) + 29e: 0700 addi s0,sp,896 + ... + 2a8: 7f05 lui t5,0xfffe1 + 2aa: 4e00 lw s0,24(a2) + 2ac: 9f25 .2byte 0x9f25 + 2ae: 00000007 .4byte 0x7 + 2b2: 0000 unimp + 2b4: 0000 unimp + 2b6: 0100 addi s0,sp,128 + 2b8: 075f 0000 0000 .byte 0x5f, 0x07, 0x00, 0x00, 0x00, 0x00 + 2be: 0000 unimp + 2c0: 0000 unimp + 2c2: 6201 .2byte 0x6201 + 2c4: 00000007 .4byte 0x7 + 2c8: 0000 unimp + 2ca: 0000 unimp + 2cc: 0100 addi s0,sp,128 + 2ce: 0758 addi a4,sp,900 + ... + 2d8: 5801 li a6,-32 + 2da: 00000007 .4byte 0x7 + 2de: 0000 unimp + 2e0: 0000 unimp + 2e2: 0100 addi s0,sp,128 + 2e4: 075f 0000 0000 .byte 0x5f, 0x07, 0x00, 0x00, 0x00, 0x00 + 2ea: 0000 unimp + 2ec: 0000 unimp + 2ee: 5801 li a6,-32 + 2f0: 00000007 .4byte 0x7 + 2f4: 0000 unimp + 2f6: 0000 unimp + 2f8: 0100 addi s0,sp,128 + 2fa: 0058 addi a4,sp,4 + 2fc: 00000007 .4byte 0x7 + 300: 0000 unimp + 302: 0000 unimp + 304: 0200 addi s0,sp,256 + 306: 9f30 .2byte 0x9f30 + 308: 00000007 .4byte 0x7 + 30c: 0000 unimp + 30e: 0000 unimp + 310: 0100 addi s0,sp,128 + 312: 0058 addi a4,sp,4 + 314: 00000007 .4byte 0x7 + 318: 0000 unimp + 31a: 0000 unimp + 31c: 0400 addi s0,sp,512 + 31e: c178 sw a4,68(a0) + 320: 9f00 .2byte 0x9f00 + 322: 0700 addi s0,sp,896 + ... + 32c: 5a01 li s4,-32 + 32e: 00000007 .4byte 0x7 + 332: 0000 unimp + 334: 0000 unimp + 336: 0200 addi s0,sp,256 + 338: 5491 li s1,-28 + 33a: 00000007 .4byte 0x7 + 33e: 0000 unimp + 340: 0000 unimp + 342: 0100 addi s0,sp,128 + 344: 075a slli a4,a4,0x16 + ... + 34e: 9102 jalr sp + 350: 0054 addi a3,sp,4 + 352: 00000007 .4byte 0x7 + 356: 0000 unimp + 358: 0000 unimp + 35a: 0100 addi s0,sp,128 + 35c: 075a slli a4,a4,0x16 + ... + 366: 9102 jalr sp + 368: 0754 addi a3,sp,900 + ... + 372: 5a01 li s4,-32 + 374: 00000007 .4byte 0x7 + 378: 0000 unimp + 37a: 0000 unimp + 37c: 0200 addi s0,sp,256 + 37e: 5491 li s1,-28 + 380: 00000007 .4byte 0x7 + 384: 0000 unimp + 386: 0000 unimp + 388: 0200 addi s0,sp,256 + 38a: 5491 li s1,-28 + 38c: 0700 addi s0,sp,896 + ... + 396: 5e01 li t3,-32 + 398: 00000007 .4byte 0x7 + 39c: 0000 unimp + 39e: 0000 unimp + 3a0: 0200 addi s0,sp,256 + 3a2: 5891 li a7,-28 + 3a4: 00000007 .4byte 0x7 + 3a8: 0000 unimp + 3aa: 0000 unimp + 3ac: 0200 addi s0,sp,256 + 3ae: 5891 li a7,-28 + 3b0: 0700 addi s0,sp,896 + ... + 3ba: 5d01 li s10,-32 + 3bc: 00000007 .4byte 0x7 + 3c0: 0000 unimp + 3c2: 0000 unimp + 3c4: 0200 addi s0,sp,256 + 3c6: 5491 li s1,-28 + 3c8: 00000007 .4byte 0x7 + 3cc: 0000 unimp + 3ce: 0000 unimp + 3d0: 0200 addi s0,sp,256 + 3d2: 5491 li s1,-28 + 3d4: 0700 addi s0,sp,896 + ... + 3de: 5801 li a6,-32 + 3e0: 00000007 .4byte 0x7 + 3e4: 0000 unimp + 3e6: 0000 unimp + 3e8: 0100 addi s0,sp,128 + 3ea: 075c addi a5,sp,900 + ... + 3f4: 9102 jalr sp + 3f6: 075c addi a5,sp,900 + ... + 400: 9102 jalr sp + 402: 005c addi a5,sp,4 + 404: 00000007 .4byte 0x7 + 408: 0000 unimp + 40a: 0000 unimp + 40c: 0400 addi s0,sp,512 + 40e: c00a sw sp,0(sp) + 410: 07009f0f .4byte 0x7009f0f + ... + 41c: 0a04 addi s1,sp,272 + 41e: 0f14 addi a3,sp,912 + 420: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 426: 0000 unimp + 428: 0000 unimp + 42a: 0400 addi s0,sp,512 + 42c: 110a slli sp,sp,0x22 + 42e: 07009f0f .4byte 0x7009f0f + ... + 43a: 0a04 addi s1,sp,272 + 43c: 0f12 slli t5,t5,0x4 + 43e: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 444: 0000 unimp + 446: 0000 unimp + 448: 0400 addi s0,sp,512 + 44a: 130a slli t1,t1,0x22 + 44c: 07009f0f .4byte 0x7009f0f + ... + 458: 0a04 addi s1,sp,272 + 45a: 0301 addi t1,t1,0 + 45c: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 462: 0000 unimp + 464: 0000 unimp + 466: 0400 addi s0,sp,512 + 468: 010a slli sp,sp,0x2 + 46a: 07009f03 lh t5,112(ra) + ... + 476: 0a04 addi s1,sp,272 + 478: 0fc0 addi s0,sp,980 + 47a: 009f f807 0002 .byte 0x9f, 0x00, 0x07, 0xf8, 0x02, 0x00 + 480: 1000 addi s0,sp,32 + 482: 0004 .2byte 0x4 + 484: 0100 addi s0,sp,128 + 486: 0758 addi a4,sp,900 + 488: 0458 addi a4,sp,516 + 48a: 0000 unimp + 48c: 04f4 addi a3,sp,588 + 48e: 0000 unimp + 490: 5801 li a6,-32 + 492: 0700 addi s0,sp,896 + 494: 0344 addi s1,sp,388 + 496: 0000 unimp + 498: 0350 addi a2,sp,388 + 49a: 0000 unimp + 49c: 0306 slli t1,t1,0x1 + 49e: 0564 addi s1,sp,652 + 4a0: 0000 unimp + 4a2: 079f 0350 0000 .byte 0x9f, 0x07, 0x50, 0x03, 0x00, 0x00 + 4a8: 0358 addi a4,sp,388 + 4aa: 0000 unimp + 4ac: 0305 addi t1,t1,1 + 4ae: 0850 addi a2,sp,20 + 4b0: 8000 .2byte 0x8000 + 4b2: 00035807 .4byte 0x35807 + 4b6: 5b00 lw s0,48(a4) + 4b8: 01000003 lb zero,16(zero) # 10 + 4bc: 075f 0394 0000 .byte 0x5f, 0x07, 0x94, 0x03, 0x00, 0x00 + 4c2: 03a0 addi s0,sp,456 + 4c4: 0000 unimp + 4c6: 0305 addi t1,t1,1 + 4c8: 0854 addi a3,sp,20 + 4ca: 8000 .2byte 0x8000 + 4cc: 0003a007 .4byte 0x3a007 + 4d0: ac00 .2byte 0xac00 + 4d2: 05000003 lb zero,80(zero) # 50 + 4d6: 00085803 lhu a6,0(a6) # ffff9000 <__crt0_stack_begin+0x7fff7004> + 4da: 0780 addi s0,sp,960 + 4dc: 03ac addi a1,sp,456 + 4de: 0000 unimp + 4e0: 03b8 addi a4,sp,456 + 4e2: 0000 unimp + 4e4: 0305 addi t1,t1,1 + 4e6: 085c addi a5,sp,20 + 4e8: 8000 .2byte 0x8000 + 4ea: 0003b807 .4byte 0x3b807 + 4ee: c400 sw s0,8(s0) + 4f0: 05000003 lb zero,80(zero) # 50 + 4f4: 00086003 .4byte 0x86003 + 4f8: 0780 addi s0,sp,960 + 4fa: 03c4 addi s1,sp,452 + 4fc: 0000 unimp + 4fe: 03d0 addi a2,sp,452 + 500: 0000 unimp + 502: 0305 addi t1,t1,1 + 504: 0864 addi s1,sp,28 + 506: 8000 .2byte 0x8000 + 508: 0003d007 .4byte 0x3d007 + 50c: dc00 sw s0,56(s0) + 50e: 05000003 lb zero,80(zero) # 50 + 512: 00086803 .4byte 0x86803 + 516: 0780 addi s0,sp,960 + 518: 03dc addi a5,sp,452 + 51a: 0000 unimp + 51c: 03e8 addi a0,sp,460 + 51e: 0000 unimp + 520: 0305 addi t1,t1,1 + 522: 086c addi a1,sp,28 + 524: 8000 .2byte 0x8000 + 526: 0003e807 .4byte 0x3e807 + 52a: f400 .2byte 0xf400 + 52c: 05000003 lb zero,80(zero) # 50 + 530: 00087003 .4byte 0x87003 + 534: 0780 addi s0,sp,960 + 536: 03f4 addi a3,sp,460 + 538: 0000 unimp + 53a: 0400 addi s0,sp,512 + 53c: 0000 unimp + 53e: 0305 addi t1,t1,1 + 540: 0874 addi a3,sp,28 + 542: 8000 .2byte 0x8000 + 544: 00040007 .4byte 0x40007 + 548: 0800 addi s0,sp,16 + 54a: 0004 .2byte 0x4 + 54c: 0500 addi s0,sp,640 + 54e: 00087803 .4byte 0x87803 + 552: 0780 addi s0,sp,960 + 554: 0408 addi a0,sp,512 + 556: 0000 unimp + 558: 0000040b .4byte 0x40b + 55c: 5f01 li t5,-32 + 55e: 00045807 .4byte 0x45807 + 562: 6400 .2byte 0x6400 + 564: 0004 .2byte 0x4 + 566: 0500 addi s0,sp,640 + 568: 00087c03 .4byte 0x87c03 + 56c: 0780 addi s0,sp,960 + 56e: 0464 addi s1,sp,524 + 570: 0000 unimp + 572: 0470 addi a2,sp,524 + 574: 0000 unimp + 576: 0305 addi t1,t1,1 + 578: 0880 addi s0,sp,80 + 57a: 8000 .2byte 0x8000 + 57c: 00047007 .4byte 0x47007 + 580: 7c00 .2byte 0x7c00 + 582: 0004 .2byte 0x4 + 584: 0500 addi s0,sp,640 + 586: 00088403 lb s0,0(a7) # 181069c <__neorv32_ram_size+0x180e69c> + 58a: 0780 addi s0,sp,960 + 58c: 047c addi a5,sp,524 + 58e: 0000 unimp + 590: 0484 addi s1,sp,576 + 592: 0000 unimp + 594: 0305 addi t1,t1,1 + 596: 0888 addi a0,sp,80 + 598: 8000 .2byte 0x8000 + 59a: 00048407 .4byte 0x48407 + 59e: 8c00 .2byte 0x8c00 + 5a0: 0004 .2byte 0x4 + 5a2: 0500 addi s0,sp,640 + 5a4: 00088c03 lb s8,0(a7) + 5a8: 0780 addi s0,sp,960 + 5aa: 048c addi a1,sp,576 + 5ac: 0000 unimp + 5ae: 0494 addi a3,sp,576 + 5b0: 0000 unimp + 5b2: 0305 addi t1,t1,1 + 5b4: 0890 addi a2,sp,80 + 5b6: 8000 .2byte 0x8000 + 5b8: 00049407 .4byte 0x49407 + 5bc: 9c00 .2byte 0x9c00 + 5be: 0004 .2byte 0x4 + 5c0: 0500 addi s0,sp,640 + 5c2: 00089403 lh s0,0(a7) + 5c6: 0780 addi s0,sp,960 + 5c8: 049c addi a5,sp,576 + 5ca: 0000 unimp + 5cc: 04a4 addi s1,sp,584 + 5ce: 0000 unimp + 5d0: 0305 addi t1,t1,1 + 5d2: 0898 addi a4,sp,80 + 5d4: 8000 .2byte 0x8000 + 5d6: 0004a407 .4byte 0x4a407 + 5da: ac00 .2byte 0xac00 + 5dc: 0004 .2byte 0x4 + 5de: 0500 addi s0,sp,640 + 5e0: 00089c03 lh s8,0(a7) + 5e4: 0780 addi s0,sp,960 + 5e6: 04ac addi a1,sp,584 + 5e8: 0000 unimp + 5ea: 04b4 addi a3,sp,584 + 5ec: 0000 unimp + 5ee: 0305 addi t1,t1,1 + 5f0: 08a0 addi s0,sp,88 + 5f2: 8000 .2byte 0x8000 + 5f4: 0004b407 .4byte 0x4b407 + 5f8: bc00 .2byte 0xbc00 + 5fa: 0004 .2byte 0x4 + 5fc: 0500 addi s0,sp,640 + 5fe: 0008a403 lw s0,0(a7) + 602: 0780 addi s0,sp,960 + 604: 04bc addi a5,sp,584 + 606: 0000 unimp + 608: 04c4 addi s1,sp,580 + 60a: 0000 unimp + 60c: 0305 addi t1,t1,1 + 60e: 08a8 addi a0,sp,88 + 610: 8000 .2byte 0x8000 + 612: 0004c407 .4byte 0x4c407 + 616: cc00 sw s0,24(s0) + 618: 0004 .2byte 0x4 + 61a: 0500 addi s0,sp,640 + 61c: 0008ac03 lw s8,0(a7) + 620: 0780 addi s0,sp,960 + 622: 04cc addi a1,sp,580 + 624: 0000 unimp + 626: 04d4 addi a3,sp,580 + 628: 0000 unimp + 62a: 0305 addi t1,t1,1 + 62c: 08b0 addi a2,sp,88 + 62e: 8000 .2byte 0x8000 + 630: 0004d407 .4byte 0x4d407 + 634: dc00 sw s0,56(s0) + 636: 0004 .2byte 0x4 + 638: 0500 addi s0,sp,640 + 63a: 0008b403 .4byte 0x8b403 + 63e: 0780 addi s0,sp,960 + 640: 04dc addi a5,sp,580 + 642: 0000 unimp + 644: 04e4 addi s1,sp,588 + 646: 0000 unimp + 648: 0305 addi t1,t1,1 + 64a: 08b8 addi a4,sp,88 + 64c: 8000 .2byte 0x8000 + 64e: 0004e407 .4byte 0x4e407 + 652: ec00 .2byte 0xec00 + 654: 0004 .2byte 0x4 + 656: 0500 addi s0,sp,640 + 658: 0008bc03 .4byte 0x8bc03 + 65c: 0780 addi s0,sp,960 + 65e: 04ec addi a1,sp,588 + 660: 0000 unimp + 662: 04f4 addi a3,sp,588 + 664: 0000 unimp + 666: 0305 addi t1,t1,1 + 668: 08c0 addi s0,sp,84 + 66a: 8000 .2byte 0x8000 + 66c: 0700 addi s0,sp,896 + 66e: 0360 addi s0,sp,396 + 670: 0000 unimp + 672: 0370 addi a2,sp,396 + 674: 0000 unimp + 676: 5e01 li t3,-32 + 678: 00037007 .4byte 0x37007 + 67c: 9400 .2byte 0x9400 + 67e: 01000003 lb zero,16(zero) # 10 + 682: 005c addi a5,sp,4 + 684: 00035c07 .4byte 0x35c07 + 688: 6000 .2byte 0x6000 + 68a: 04000003 lb zero,64(zero) # 40 + 68e: 410a lw sp,128(sp) + 690: 07009f03 lh t5,112(ra) + 694: 0360 addi s0,sp,396 + 696: 0000 unimp + 698: 036c addi a1,sp,396 + 69a: 0000 unimp + 69c: 5e01 li t3,-32 + 69e: 0700 addi s0,sp,896 + 6a0: 0360 addi s0,sp,396 + 6a2: 0000 unimp + 6a4: 0394 addi a3,sp,448 + 6a6: 0000 unimp + 6a8: 5e01 li t3,-32 + 6aa: 0700 addi s0,sp,896 + 6ac: 0370 addi a2,sp,396 + 6ae: 0000 unimp + 6b0: 0374 addi a3,sp,396 + 6b2: 0000 unimp + 6b4: 0a04 addi s1,sp,272 + 6b6: 0301 addi t1,t1,0 + 6b8: 009f 8c07 0003 .byte 0x9f, 0x00, 0x07, 0x8c, 0x03, 0x00 + 6be: 9000 .2byte 0x9000 + 6c0: 01000003 lb zero,16(zero) # 10 + 6c4: 005c addi a5,sp,4 + 6c6: 00038c07 .4byte 0x38c07 + 6ca: 9000 .2byte 0x9000 + 6cc: 04000003 lb zero,64(zero) # 40 + 6d0: 410a lw sp,128(sp) + 6d2: 07009f03 lh t5,112(ra) + 6d6: 038c addi a1,sp,448 + 6d8: 0000 unimp + 6da: 0394 addi a3,sp,448 + 6dc: 0000 unimp + 6de: 5c01 li s8,-32 + 6e0: 0700 addi s0,sp,896 + 6e2: 02ac addi a1,sp,328 + 6e4: 0000 unimp + 6e6: 02f8 addi a4,sp,332 + 6e8: 0000 unimp + 6ea: 0a04 addi s1,sp,272 + 6ec: 0342 slli t1,t1,0x10 + 6ee: 009f 3c07 0008 .byte 0x9f, 0x00, 0x07, 0x3c, 0x08, 0x00 + 6f4: 4c00 lw s0,24(s0) + 6f6: 0008 .2byte 0x8 + 6f8: 0100 addi s0,sp,128 + 6fa: 075a slli a4,a4,0x16 + 6fc: 084c addi a1,sp,20 + 6fe: 0000 unimp + 700: 0864 addi s1,sp,28 + 702: 0000 unimp + 704: a304 .2byte 0xa304 + 706: 5a01 li s4,-32 + 708: 079f 0864 0000 .byte 0x9f, 0x07, 0x64, 0x08, 0x00, 0x00 + 70e: 0868 addi a0,sp,28 + 710: 0000 unimp + 712: 5a01 li s4,-32 + 714: 00086807 .4byte 0x86807 + 718: 6c00 .2byte 0x6c00 + 71a: 0008 .2byte 0x8 + 71c: 0400 addi s0,sp,512 + 71e: 9f5a01a3 sb s5,-1565(s4) + 722: 0700 addi s0,sp,896 + ... + 72c: 5a01 li s4,-32 + 72e: 00000007 .4byte 0x7 + 732: 0000 unimp + 734: 0000 unimp + 736: 0400 addi s0,sp,512 + 738: 9f5a01a3 sb s5,-1565(s4) + 73c: 00000007 .4byte 0x7 + 740: 0000 unimp + 742: 0000 unimp + 744: 0100 addi s0,sp,128 + 746: 075a slli a4,a4,0x16 + ... + 750: a304 .2byte 0xa304 + 752: 5a01 li s4,-32 + 754: 009f 9407 0008 .byte 0x9f, 0x00, 0x07, 0x94, 0x08, 0x00 + 75a: 9c00 .2byte 0x9c00 + 75c: 0008 .2byte 0x8 + 75e: 0200 addi s0,sp,256 + 760: 9f30 .2byte 0x9f30 + 762: 00089c07 .4byte 0x89c07 + 766: a400 .2byte 0xa400 + 768: 0008 .2byte 0x8 + 76a: 0100 addi s0,sp,128 + 76c: 0758 addi a4,sp,900 + 76e: 08ac addi a1,sp,88 + 770: 0000 unimp + 772: 08b8 addi a4,sp,88 + 774: 0000 unimp + 776: 5801 li a6,-32 + 778: 0700 addi s0,sp,896 + 77a: 086c addi a1,sp,28 + 77c: 0000 unimp + 77e: 0884 addi s1,sp,80 + 780: 0000 unimp + 782: 0306 slli t1,t1,0x1 + 784: 02ac addi a1,sp,328 + 786: 0000 unimp + 788: 009f 6c07 0008 .byte 0x9f, 0x00, 0x07, 0x6c, 0x08, 0x00 + 78e: 8400 .2byte 0x8400 + 790: 0008 .2byte 0x8 + 792: 0400 addi s0,sp,512 + 794: 050a slli a0,a0,0x2 + 796: 07009f03 lh t5,112(ra) + 79a: 0884 addi s1,sp,80 + 79c: 0000 unimp + 79e: 088c addi a1,sp,80 + 7a0: 0000 unimp + 7a2: 3002 .2byte 0x3002 + 7a4: 009f 8407 0008 .byte 0x9f, 0x00, 0x07, 0x84, 0x08, 0x00 + 7aa: 8c00 .2byte 0x8c00 + 7ac: 0008 .2byte 0x8 + 7ae: 0400 addi s0,sp,512 + 7b0: 040a slli s0,s0,0x2 + 7b2: 07009f03 lh t5,112(ra) + 7b6: 088c addi a1,sp,80 + 7b8: 0000 unimp + 7ba: 0890 addi a2,sp,80 + 7bc: 0000 unimp + 7be: 3002 .2byte 0x3002 + 7c0: 009f 8c07 0008 .byte 0x9f, 0x00, 0x07, 0x8c, 0x08, 0x00 + 7c6: 9000 .2byte 0x9000 + 7c8: 0008 .2byte 0x8 + 7ca: 0400 addi s0,sp,512 + 7cc: 440a lw s0,128(sp) + 7ce: 07009f03 lh t5,112(ra) + ... + 7da: 5a01 li s4,-32 + 7dc: 00000007 .4byte 0x7 + 7e0: 0000 unimp + 7e2: 0000 unimp + 7e4: 0400 addi s0,sp,512 + 7e6: 9f5a01a3 sb s5,-1565(s4) + 7ea: 00000007 .4byte 0x7 + 7ee: 0000 unimp + 7f0: 0000 unimp + 7f2: 0100 addi s0,sp,128 + 7f4: 075a slli a4,a4,0x16 + ... + 7fe: a304 .2byte 0xa304 + 800: 5a01 li s4,-32 + 802: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 808: 0000 unimp + 80a: 0000 unimp + 80c: 0100 addi s0,sp,128 + 80e: 075a slli a4,a4,0x16 + ... + 818: a304 .2byte 0xa304 + 81a: 5a01 li s4,-32 + 81c: 009f 9407 0005 .byte 0x9f, 0x00, 0x07, 0x94, 0x05, 0x00 + 822: f000 .2byte 0xf000 + 824: 0006 c.slli zero,0x1 + 826: 0100 addi s0,sp,128 + 828: 0759 addi a4,a4,22 # 1a016 <__neorv32_ram_size+0x18016> + 82a: 0770 addi a2,sp,908 + 82c: 0000 unimp + 82e: 07dc addi a5,sp,964 + 830: 0000 unimp + 832: 5901 li s2,-32 + 834: 0007e407 .4byte 0x7e407 + 838: 1400 addi s0,sp,544 + 83a: 0008 .2byte 0x8 + 83c: 0100 addi s0,sp,128 + 83e: 0059 c.nop 22 + 840: 0005f807 .4byte 0x5f807 + 844: 0c00 addi s0,sp,528 + 846: 0006 c.slli zero,0x1 + 848: 0100 addi s0,sp,128 + 84a: 0758 addi a4,sp,900 + 84c: 063c addi a5,sp,776 + 84e: 0000 unimp + 850: 0000063f 60075a01 .8byte 0x60075a010000063f + 858: 0006 c.slli zero,0x1 + 85a: 6300 .2byte 0x6300 + 85c: 0006 c.slli zero,0x1 + 85e: 0100 addi s0,sp,128 + 860: 075a slli a4,a4,0x16 + 862: 06ac addi a1,sp,840 + 864: 0000 unimp + 866: 06c0 addi s0,sp,836 + 868: 0000 unimp + 86a: 5801 li a6,-32 + 86c: 0006d807 .4byte 0x6d807 + 870: 2800 .2byte 0x2800 + 872: 01000007 .4byte 0x1000007 + 876: 0758 addi a4,sp,900 + 878: 0814 addi a3,sp,16 + 87a: 0000 unimp + 87c: 0820 addi s0,sp,24 + 87e: 0000 unimp + 880: 5801 li a6,-32 + 882: 0700 addi s0,sp,896 + 884: 0590 addi a2,sp,704 + 886: 0000 unimp + 888: 0594 addi a3,sp,704 + 88a: 0000 unimp + 88c: 0a04 addi s1,sp,272 + 88e: 0342 slli t1,t1,0x10 + 890: 009f f407 0005 .byte 0x9f, 0x00, 0x07, 0xf4, 0x05, 0x00 + 896: f800 .2byte 0xf800 + 898: 0005 c.nop 1 + 89a: 0400 addi s0,sp,512 + 89c: 410a lw sp,128(sp) + 89e: 38079f03 lh t5,896(a5) + 8a2: 0006 c.slli zero,0x1 + 8a4: 3c00 .2byte 0x3c00 + 8a6: 0006 c.slli zero,0x1 + 8a8: 0400 addi s0,sp,512 + 8aa: 410a lw sp,128(sp) + 8ac: 5c079f03 lh t5,1472(a5) + 8b0: 0006 c.slli zero,0x1 + 8b2: 6000 .2byte 0x6000 + 8b4: 0006 c.slli zero,0x1 + 8b6: 0400 addi s0,sp,512 + 8b8: 410a lw sp,128(sp) + 8ba: a8079f03 lh t5,-1408(a5) + 8be: 0006 c.slli zero,0x1 + 8c0: ac00 .2byte 0xac00 + 8c2: 0006 c.slli zero,0x1 + 8c4: 0400 addi s0,sp,512 + 8c6: 410a lw sp,128(sp) + 8c8: d4079f03 lh t5,-704(a5) + 8cc: 0006 c.slli zero,0x1 + 8ce: d800 sw s0,48(s0) + 8d0: 0006 c.slli zero,0x1 + 8d2: 0400 addi s0,sp,512 + 8d4: 410a lw sp,128(sp) + 8d6: d8079f03 lh t5,-640(a5) + 8da: dc000007 .4byte 0xdc000007 + 8de: 04000007 .4byte 0x4000007 + 8e2: 410a lw sp,128(sp) + 8e4: 07009f03 lh t5,112(ra) + 8e8: 0670 addi a2,sp,780 + 8ea: 0000 unimp + 8ec: 0678 addi a4,sp,780 + 8ee: 0000 unimp + 8f0: 0a04 addi s1,sp,272 + 8f2: 009f0343 .4byte 0x9f0343 + 8f6: 00068807 .4byte 0x68807 + 8fa: 9000 .2byte 0x9000 + 8fc: 0006 c.slli zero,0x1 + 8fe: 0100 addi s0,sp,128 + 900: 075f 0808 0000 .byte 0x5f, 0x07, 0x08, 0x08, 0x00, 0x00 + 906: 0814 addi a3,sp,16 + 908: 0000 unimp + 90a: 5f01 li t5,-32 + 90c: 0700 addi s0,sp,896 + 90e: 06ec addi a1,sp,844 + 910: 0000 unimp + 912: 06f8 addi a4,sp,844 + 914: 0000 unimp + 916: 5801 li a6,-32 + 918: 0700 addi s0,sp,896 + 91a: 06ec addi a1,sp,844 + 91c: 0000 unimp + 91e: 0728 addi a0,sp,904 + 920: 0000 unimp + 922: 5801 li a6,-32 + 924: 00081407 .4byte 0x81407 + 928: 2000 .2byte 0x2000 + 92a: 0008 .2byte 0x8 + 92c: 0100 addi s0,sp,128 + 92e: 0058 addi a4,sp,4 + 930: 0006f807 .4byte 0x6f807 + 934: fc00 .2byte 0xfc00 + 936: 0006 c.slli zero,0x1 + 938: 0300 addi s0,sp,384 + 93a: 0278 addi a4,sp,268 + 93c: 079f 06fc 0000 .byte 0x9f, 0x07, 0xfc, 0x06, 0x00, 0x00 + 942: 0700 addi s0,sp,896 + 944: 0000 unimp + 946: 5a01 li s4,-32 + 948: 00070007 .4byte 0x70007 + 94c: 1000 addi s0,sp,32 + 94e: 03000007 .4byte 0x3000007 + 952: 0278 addi a4,sp,268 + 954: 009f f807 0006 .byte 0x9f, 0x00, 0x07, 0xf8, 0x06, 0x00 + 95a: fc00 .2byte 0xfc00 + 95c: 0006 c.slli zero,0x1 + 95e: 0300 addi s0,sp,384 + 960: 0278 addi a4,sp,268 + 962: 079f 06fc 0000 .byte 0x9f, 0x07, 0xfc, 0x06, 0x00, 0x00 + 968: 0700 addi s0,sp,896 + 96a: 0000 unimp + 96c: 5a01 li s4,-32 + 96e: 00070007 .4byte 0x70007 + 972: 2800 .2byte 0x2800 + 974: 03000007 .4byte 0x3000007 + 978: 0278 addi a4,sp,268 + 97a: 079f 0814 0000 .byte 0x9f, 0x07, 0x14, 0x08, 0x00, 0x00 + 980: 0820 addi s0,sp,24 + 982: 0000 unimp + 984: 9f027803 .4byte 0x9f027803 + 988: 0700 addi s0,sp,896 + 98a: 0724 addi s1,sp,904 + 98c: 0000 unimp + 98e: 0730 addi a2,sp,904 + 990: 0000 unimp + 992: 3002 .2byte 0x3002 + 994: 009f 3007 0007 .byte 0x9f, 0x00, 0x07, 0x30, 0x07, 0x00 + 99a: 4400 lw s0,8(s0) + 99c: 0c000007 .4byte 0xc000007 + 9a0: 0079 c.nop 30 + 9a2: ff0a .2byte 0xff0a + 9a4: 1aff .2byte 0x1aff + 9a6: 0078 addi a4,sp,12 + 9a8: 3f26 .2byte 0x3f26 + 9aa: 9f1a add t5,t5,t1 + 9ac: 00074407 .4byte 0x74407 + 9b0: 4c00 lw s0,24(s0) + 9b2: 0c000007 .4byte 0xc000007 + 9b6: 0079 c.nop 30 + 9b8: ff0a .2byte 0xff0a + 9ba: 1aff .2byte 0x1aff + 9bc: 0478 addi a4,sp,524 + 9be: 3f26 .2byte 0x3f26 + 9c0: 9f1a add t5,t5,t1 + 9c2: 0700 addi s0,sp,896 + ... + 9cc: 0a04 addi s1,sp,272 + 9ce: 009f0f13 addi t5,t5,9 # fffe1009 <__crt0_stack_begin+0x7ffdf00d> + 9d2: 07e2 slli a5,a5,0x18 + 9d4: 0000 unimp + 9d6: 0005 c.nop 1 + 9d8: 0004 .2byte 0x4 + 9da: 0000 unimp + 9dc: 0000 unimp + 9de: 000a3007 .4byte 0xa3007 + 9e2: 4400 lw s0,8(s0) + 9e4: 000a c.slli zero,0x2 + 9e6: 0200 addi s0,sp,256 + 9e8: 9f30 .2byte 0x9f30 + 9ea: 000a4407 .4byte 0xa4407 + 9ee: 5c00 lw s0,56(s0) + 9f0: 000a c.slli zero,0x2 + 9f2: 0800 addi s0,sp,16 + 9f4: 007d007b .4byte 0x7d007b + 9f8: 231c .2byte 0x231c + 9fa: 5c079f07 .4byte 0x5c079f07 + 9fe: 000a c.slli zero,0x2 + a00: 6000 .2byte 0x6000 + a02: 000a c.slli zero,0x2 + a04: 0800 addi s0,sp,16 + a06: 007d007b .4byte 0x7d007b + a0a: 231c .2byte 0x231c + a0c: 9f06 add t5,t5,ra + a0e: 0700 addi s0,sp,896 + a10: 0a44 addi s1,sp,276 + a12: 0000 unimp + a14: 0a58 addi a4,sp,276 + a16: 0000 unimp + a18: 7a06 .2byte 0x7a06 + a1a: 7e00 .2byte 0x7e00 + a1c: 2500 .2byte 0x2500 + a1e: 079f 0a58 0000 .byte 0x9f, 0x07, 0x58, 0x0a, 0x00, 0x00 + a24: 0a6c addi a1,sp,284 + a26: 0000 unimp + a28: 7a06 .2byte 0x7a06 + a2a: 7e00 .2byte 0x7e00 + a2c: 257c .2byte 0x257c + a2e: 009f 2807 0009 .byte 0x9f, 0x00, 0x07, 0x28, 0x09, 0x00 + a34: 6400 .2byte 0x6400 + a36: 0009 c.nop 2 + a38: 0100 addi s0,sp,128 + a3a: 075a slli a4,a4,0x16 + a3c: 0964 addi s1,sp,156 + a3e: 0000 unimp + a40: 0a10 addi a2,sp,272 + a42: 0000 unimp + a44: 5901 li s2,-32 + a46: 000a1007 .4byte 0xa1007 + a4a: 2800 .2byte 0x2800 + a4c: 000a c.slli zero,0x2 + a4e: 0100 addi s0,sp,128 + a50: 075a slli a4,a4,0x16 + a52: 0a28 addi a0,sp,280 + a54: 0000 unimp + a56: 0a30 addi a2,sp,280 + a58: 0000 unimp + a5a: 5901 li s2,-32 + a5c: 0700 addi s0,sp,896 + a5e: 0928 addi a0,sp,152 + a60: 0000 unimp + a62: 0964 addi s1,sp,156 + a64: 0000 unimp + a66: 5b01 li s6,-32 + a68: 00096407 .4byte 0x96407 + a6c: 0000 unimp + a6e: 000a c.slli zero,0x2 + a70: 0100 addi s0,sp,128 + a72: 0758 addi a4,sp,900 + a74: 0a00 addi s0,sp,272 + a76: 0000 unimp + a78: 0a28 addi a0,sp,280 + a7a: 0000 unimp + a7c: a304 .2byte 0xa304 + a7e: 5b01 li s6,-32 + a80: 079f 0a28 0000 .byte 0x9f, 0x07, 0x28, 0x0a, 0x00, 0x00 + a86: 0a30 addi a2,sp,280 + a88: 0000 unimp + a8a: 5801 li a6,-32 + a8c: 0700 addi s0,sp,896 + a8e: 0958 addi a4,sp,148 + a90: 0000 unimp + a92: 0964 addi s1,sp,156 + a94: 0000 unimp + a96: 3002 .2byte 0x3002 + a98: 079f 0964 0000 .byte 0x9f, 0x07, 0x64, 0x09, 0x00, 0x00 + a9e: 0990 addi a2,sp,208 + aa0: 0000 unimp + aa2: 6301 .2byte 0x6301 + aa4: 0009b407 .4byte 0x9b407 + aa8: b800 .2byte 0xb800 + aaa: 0009 c.nop 2 + aac: 0100 addi s0,sp,128 + aae: 075e slli a4,a4,0x17 + ab0: 09b8 addi a4,sp,216 + ab2: 0000 unimp + ab4: 09c4 addi s1,sp,212 + ab6: 0000 unimp + ab8: 9f7f7f03 .4byte 0x9f7f7f03 + abc: 0009c407 .4byte 0x9c407 + ac0: d000 sw s0,32(s0) + ac2: 0009 c.nop 2 + ac4: 0300 addi s0,sp,384 + ac6: 7e7f .2byte 0x7e7f + ac8: 009f d807 0009 .byte 0x9f, 0x00, 0x07, 0xd8, 0x09, 0x00 + ace: e400 .2byte 0xe400 + ad0: 0009 c.nop 2 + ad2: 0100 addi s0,sp,128 + ad4: 075e slli a4,a4,0x17 + ad6: 09e4 addi s1,sp,220 + ad8: 0000 unimp + ada: 09f4 addi a3,sp,220 + adc: 0000 unimp + ade: 5c01 li s8,-32 + ae0: 0009f407 .4byte 0x9f407 + ae4: 3000 .2byte 0x3000 + ae6: 000a c.slli zero,0x2 + ae8: 0100 addi s0,sp,128 + aea: 005e c.slli zero,0x17 + aec: 00000007 .4byte 0x7 + af0: 0000 unimp + af2: 0000 unimp + af4: 0100 addi s0,sp,128 + af6: 075a slli a4,a4,0x16 + ... + b00: 5901 li s2,-32 + b02: 00000007 .4byte 0x7 + b06: 0000 unimp + b08: 0000 unimp + b0a: 0100 addi s0,sp,128 + b0c: 0768 addi a0,sp,908 + ... + b16: 5901 li s2,-32 + b18: 0700 addi s0,sp,896 + ... + b22: 5b01 li s6,-32 + b24: 00000007 .4byte 0x7 + b28: 0000 unimp + b2a: 0000 unimp + b2c: 0300 addi s0,sp,384 + b2e: 0184 addi s1,sp,192 + b30: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + b36: 0000 unimp + b38: 0000 unimp + b3a: a304 .2byte 0xa304 + b3c: 5b01 li s6,-32 + b3e: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + b44: 0000 unimp + b46: 0000 unimp + b48: 0100 addi s0,sp,128 + b4a: 075c addi a5,sp,900 + ... + b54: 6301 .2byte 0x6301 + b56: 00000007 .4byte 0x7 + b5a: 0000 unimp + b5c: 0000 unimp + b5e: 0400 addi s0,sp,512 + b60: 9f5c01a3 sb s5,-1565(s8) # fffe19e3 <__crt0_stack_begin+0x7ffdf9e7> + b64: 0700 addi s0,sp,896 + ... + b6e: 3002 .2byte 0x3002 + b70: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + b76: 0000 unimp + b78: 0000 unimp + b7a: 5a01 li s4,-32 + b7c: 00000007 .4byte 0x7 + b80: 0000 unimp + b82: 0000 unimp + b84: 0100 addi s0,sp,128 + b86: 075a slli a4,a4,0x16 + ... + b90: 5a01 li s4,-32 + b92: 0700 addi s0,sp,896 + ... + b9c: 3002 .2byte 0x3002 + b9e: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + ba4: 0000 unimp + ba6: 0000 unimp + ba8: 6201 .2byte 0x6201 + baa: 00000007 .4byte 0x7 + bae: 0000 unimp + bb0: 0000 unimp + bb2: 0100 addi s0,sp,128 + bb4: 005a c.slli zero,0x16 + bb6: 00000007 .4byte 0x7 + bba: 0000 unimp + bbc: 0000 unimp + bbe: 0100 addi s0,sp,128 + bc0: 075a slli a4,a4,0x16 + ... + bca: 9f017903 .4byte 0x9f017903 + bce: 00000007 .4byte 0x7 + bd2: 0000 unimp + bd4: 0000 unimp + bd6: 0300 addi s0,sp,384 + bd8: 0179 addi sp,sp,30 + bda: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + be0: 0000 unimp + be2: 0000 unimp + be4: 9f027903 .4byte 0x9f027903 + be8: 00000007 .4byte 0x7 + bec: 0000 unimp + bee: 0000 unimp + bf0: 0100 addi s0,sp,128 + bf2: 0759 addi a4,a4,22 + ... + bfc: 9f027903 .4byte 0x9f027903 + c00: 00000007 .4byte 0x7 + c04: 0000 unimp + c06: 0000 unimp + c08: 0300 addi s0,sp,384 + c0a: 0179 addi sp,sp,30 + c0c: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + c12: 0000 unimp + c14: 0000 unimp + c16: 5901 li s2,-32 + c18: 0700 addi s0,sp,896 + ... + c22: 5801 li a6,-32 + c24: 00000007 .4byte 0x7 + c28: 0000 unimp + c2a: 0000 unimp + c2c: 0200 addi s0,sp,256 + c2e: 0079 c.nop 30 + c30: 00000007 .4byte 0x7 + c34: 0000 unimp + c36: 0000 unimp + c38: 0100 addi s0,sp,128 + c3a: 0758 addi a4,sp,900 + ... + c44: 7902 .2byte 0x7902 + c46: 0701 addi a4,a4,0 + ... + c50: 5801 li a6,-32 + c52: 00000007 .4byte 0x7 + c56: 0000 unimp + c58: 0000 unimp + c5a: 0100 addi s0,sp,128 + c5c: 0058 addi a4,sp,4 + c5e: 00000007 .4byte 0x7 + c62: 0000 unimp + c64: 0000 unimp + c66: 0100 addi s0,sp,128 + c68: 0058 addi a4,sp,4 + c6a: 00000007 .4byte 0x7 + c6e: 0000 unimp + c70: 0000 unimp + c72: 0100 addi s0,sp,128 + c74: 075a slli a4,a4,0x16 + ... + c7e: 5801 li a6,-32 + c80: 00000007 .4byte 0x7 + c84: 0000 unimp + c86: 0000 unimp + c88: 0100 addi s0,sp,128 + c8a: 0058 addi a4,sp,4 + c8c: 00000007 .4byte 0x7 + c90: 0000 unimp + c92: 0000 unimp + c94: 0200 addi s0,sp,256 + c96: 9f30 .2byte 0x9f30 + c98: 00000007 .4byte 0x7 + c9c: 0000 unimp + c9e: 0000 unimp + ca0: 0100 addi s0,sp,128 + ca2: 0759 addi a4,a4,22 + ... + cac: 5901 li s2,-32 + cae: 0700 addi s0,sp,896 + ... + cb8: 5a01 li s4,-32 + cba: 00000007 .4byte 0x7 + cbe: 0000 unimp + cc0: 0000 unimp + cc2: 0400 addi s0,sp,512 + cc4: 9f5a01a3 sb s5,-1565(s4) + cc8: 00000007 .4byte 0x7 + ccc: 0000 unimp + cce: 0000 unimp + cd0: 0100 addi s0,sp,128 + cd2: 075a slli a4,a4,0x16 + ... + cdc: a304 .2byte 0xa304 + cde: 5a01 li s4,-32 + ce0: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + ce6: 0000 unimp + ce8: 0000 unimp + cea: 0100 addi s0,sp,128 + cec: 075f 0000 0000 .byte 0x5f, 0x07, 0x00, 0x00, 0x00, 0x00 + cf2: 0000 unimp + cf4: 0000 unimp + cf6: 5f01 li t5,-32 + cf8: 0700 addi s0,sp,896 + ... + d02: 5a01 li s4,-32 + d04: 0700 addi s0,sp,896 + ... + d0e: 5f01 li t5,-32 + d10: 0700 addi s0,sp,896 + ... + d1a: 5a01 li s4,-32 + d1c: 00000007 .4byte 0x7 + d20: 0000 unimp + d22: 0000 unimp + d24: 0400 addi s0,sp,512 + d26: 9f5a01a3 sb s5,-1565(s4) + d2a: 0700 addi s0,sp,896 + ... + d34: 5b01 li s6,-32 + d36: 00000007 .4byte 0x7 + d3a: 0000 unimp + d3c: 0000 unimp + d3e: 0400 addi s0,sp,512 + d40: 9f5b01a3 sb s5,-1565(s6) + d44: 0700 addi s0,sp,896 + ... + d4e: 5c01 li s8,-32 + d50: 00000007 .4byte 0x7 + d54: 0000 unimp + d56: 0000 unimp + d58: 0400 addi s0,sp,512 + d5a: 9f5c01a3 sb s5,-1565(s8) + d5e: 0700 addi s0,sp,896 + ... + d68: 5f01 li t5,-32 + d6a: 0700 addi s0,sp,896 + ... + d74: 3002 .2byte 0x3002 + d76: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + d7c: 0000 unimp + d7e: 0000 unimp + d80: 5a01 li s4,-32 + d82: 0700 addi s0,sp,896 + ... + d8c: 3002 .2byte 0x3002 + d8e: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + d94: 0000 unimp + d96: 0000 unimp + d98: 5e01 li t3,-32 + d9a: 00000007 .4byte 0x7 + d9e: 0000 unimp + da0: 0000 unimp + da2: 0100 addi s0,sp,128 + da4: 075e slli a4,a4,0x17 + ... + dae: 5e01 li t3,-32 + db0: 0700 addi s0,sp,896 + ... + dba: 7e05 lui t3,0xfffe1 + dbc: 4800 lw s0,16(s0) + dbe: 9f24 .2byte 0x9f24 + dc0: 00000007 .4byte 0x7 + dc4: 0000 unimp + dc6: 0000 unimp + dc8: 0100 addi s0,sp,128 + dca: 005e c.slli zero,0x17 + dcc: 00000007 .4byte 0x7 + dd0: 0000 unimp + dd2: 0000 unimp + dd4: 0300 addi s0,sp,384 + dd6: 7f7a .2byte 0x7f7a + dd8: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + dde: 0000 unimp + de0: 0000 unimp + de2: 5f01 li t5,-32 + de4: 00000007 .4byte 0x7 + de8: 0000 unimp + dea: 0000 unimp + dec: 0300 addi s0,sp,384 + dee: 7f7a .2byte 0x7f7a + df0: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + df6: 0000 unimp + df8: 0000 unimp + dfa: 0400 addi s0,sp,512 + dfc: 4840 lw s0,20(s0) + dfe: 9f24 .2byte 0x9f24 + e00: 0700 addi s0,sp,896 + ... + e0a: 7805 lui a6,0xfffe1 + e0c: 4600 lw s0,8(a2) + e0e: 9f24 .2byte 0x9f24 + e10: 00000007 .4byte 0x7 + e14: 0000 unimp + e16: 0000 unimp + e18: 0100 addi s0,sp,128 + e1a: 0058 addi a4,sp,4 + e1c: 00000007 .4byte 0x7 + e20: 0000 unimp + e22: 0000 unimp + e24: 0200 addi s0,sp,256 + e26: 9f30 .2byte 0x9f30 + e28: 0700 addi s0,sp,896 + ... + e32: 5a01 li s4,-32 + e34: 00000007 .4byte 0x7 + e38: 0000 unimp + e3a: 0000 unimp + e3c: 0100 addi s0,sp,128 + e3e: 0759 addi a4,a4,22 + ... + e48: 6801 .2byte 0x6801 + e4a: 00000007 .4byte 0x7 + e4e: 0000 unimp + e50: 0000 unimp + e52: 0100 addi s0,sp,128 + e54: 0059 c.nop 22 + e56: 00000007 .4byte 0x7 + e5a: 0000 unimp + e5c: 0000 unimp + e5e: 0100 addi s0,sp,128 + e60: 0000075b .4byte 0x75b + e64: 0000 unimp + e66: 0000 unimp + e68: 0000 unimp + e6a: 9f018403 lb s0,-1552(gp) # 80000a30 <__BSS_END__+0x144> + e6e: 00000007 .4byte 0x7 + e72: 0000 unimp + e74: 0000 unimp + e76: 0400 addi s0,sp,512 + e78: 9f5b01a3 sb s5,-1565(s6) + e7c: 0700 addi s0,sp,896 + ... + e86: 5c01 li s8,-32 + e88: 00000007 .4byte 0x7 + e8c: 0000 unimp + e8e: 0000 unimp + e90: 0100 addi s0,sp,128 + e92: 00000763 beqz zero,ea0 <_malloc_r+0x42> + e96: 0000 unimp + e98: 0000 unimp + e9a: 0000 unimp + e9c: a304 .2byte 0xa304 + e9e: 5c01 li s8,-32 + ea0: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + ea6: 0000 unimp + ea8: 0000 unimp + eaa: 0200 addi s0,sp,256 + eac: 9f30 .2byte 0x9f30 + eae: 00000007 .4byte 0x7 + eb2: 0000 unimp + eb4: 0000 unimp + eb6: 0100 addi s0,sp,128 + eb8: 075a slli a4,a4,0x16 + ... + ec2: 5a01 li s4,-32 + ec4: 00000007 .4byte 0x7 + ec8: 0000 unimp + eca: 0000 unimp + ecc: 0100 addi s0,sp,128 + ece: 005a c.slli zero,0x16 + ed0: 00000007 .4byte 0x7 + ed4: 0000 unimp + ed6: 0000 unimp + ed8: 0200 addi s0,sp,256 + eda: 9f30 .2byte 0x9f30 + edc: 00000007 .4byte 0x7 + ee0: 0000 unimp + ee2: 0000 unimp + ee4: 0100 addi s0,sp,128 + ee6: 0762 slli a4,a4,0x18 + ... + ef0: 5a01 li s4,-32 + ef2: 0700 addi s0,sp,896 + ef4: 0bc4 addi s1,sp,468 + ef6: 0000 unimp + ef8: 0c3c addi a5,sp,536 + efa: 0000 unimp + efc: 5a01 li s4,-32 + efe: 000c3c07 .4byte 0xc3c07 + f02: 5000 lw s0,32(s0) + f04: 000c .2byte 0xc + f06: 0300 addi s0,sp,384 + f08: 0179 addi sp,sp,30 + f0a: 079f 0c78 0000 .byte 0x9f, 0x07, 0x78, 0x0c, 0x00, 0x00 + f10: 0c7c addi a5,sp,540 + f12: 0000 unimp + f14: 9f017903 .4byte 0x9f017903 + f18: 000c7c07 .4byte 0xc7c07 + f1c: 0c00 addi s0,sp,528 + f1e: 000d c.nop 3 + f20: 0300 addi s0,sp,384 + f22: 0279 addi tp,tp,30 # 1901e <__neorv32_ram_size+0x1701e> + f24: 079f 0d0c 0000 .byte 0x9f, 0x07, 0x0c, 0x0d, 0x00, 0x00 + f2a: 0d10 addi a2,sp,656 + f2c: 0000 unimp + f2e: 5901 li s2,-32 + f30: 000d1007 .4byte 0xd1007 + f34: 8000 .2byte 0x8000 + f36: 000d c.nop 3 + f38: 0300 addi s0,sp,384 + f3a: 0279 addi tp,tp,30 # 1e + f3c: 079f 0d80 0000 .byte 0x9f, 0x07, 0x80, 0x0d, 0x00, 0x00 + f42: 0d94 addi a3,sp,720 + f44: 0000 unimp + f46: 9f017903 .4byte 0x9f017903 + f4a: 000d9407 .4byte 0xd9407 + f4e: 9c00 .2byte 0x9c00 + f50: 000d c.nop 3 + f52: 0100 addi s0,sp,128 + f54: 0059 c.nop 22 + f56: 000c4007 .4byte 0xc4007 + f5a: 4c00 lw s0,24(s0) + f5c: 000c .2byte 0xc + f5e: 0100 addi s0,sp,128 + f60: 0758 addi a4,sp,900 + f62: 0c4c addi a1,sp,532 + f64: 0000 unimp + f66: 0c50 addi a2,sp,532 + f68: 0000 unimp + f6a: 7902 .2byte 0x7902 + f6c: 0700 addi s0,sp,896 + f6e: 0c78 addi a4,sp,540 + f70: 0000 unimp + f72: 0cbc addi a5,sp,600 + f74: 0000 unimp + f76: 5801 li a6,-32 + f78: 000cbc07 .4byte 0xcbc07 + f7c: d300 sw s0,32(a4) + f7e: 000c .2byte 0xc + f80: 0200 addi s0,sp,256 + f82: 0179 addi sp,sp,30 + f84: 000ce807 .4byte 0xce807 + f88: 0400 addi s0,sp,512 + f8a: 000d c.nop 3 + f8c: 0100 addi s0,sp,128 + f8e: 0758 addi a4,sp,900 + f90: 0d10 addi a2,sp,656 + f92: 0000 unimp + f94: 0d9c addi a5,sp,720 + f96: 0000 unimp + f98: 5801 li a6,-32 + f9a: 0700 addi s0,sp,896 + f9c: 0cd0 addi a2,sp,596 + f9e: 0000 unimp + fa0: 0cdc addi a5,sp,596 + fa2: 0000 unimp + fa4: 5801 li a6,-32 + fa6: 0700 addi s0,sp,896 + fa8: 0b6c addi a1,sp,412 + faa: 0000 unimp + fac: 0b88 addi a0,sp,464 + fae: 0000 unimp + fb0: 5a01 li s4,-32 + fb2: 000b8807 .4byte 0xb8807 + fb6: 9c00 .2byte 0x9c00 + fb8: 0100000b .4byte 0x100000b + fbc: 0758 addi a4,sp,900 + fbe: 0bac addi a1,sp,472 + fc0: 0000 unimp + fc2: 0bc4 addi s1,sp,468 + fc4: 0000 unimp + fc6: 5801 li a6,-32 + fc8: 0700 addi s0,sp,896 + fca: 0b6c addi a1,sp,412 + fcc: 0000 unimp + fce: 0b88 addi a0,sp,464 + fd0: 0000 unimp + fd2: 3002 .2byte 0x3002 + fd4: 079f 0b90 0000 .byte 0x9f, 0x07, 0x90, 0x0b, 0x00, 0x00 + fda: 0ba0 addi s0,sp,472 + fdc: 0000 unimp + fde: 5901 li s2,-32 + fe0: 000bac07 .4byte 0xbac07 + fe4: c400 sw s0,8(s0) + fe6: 0100000b .4byte 0x100000b + fea: 0059 c.nop 22 + fec: 00000007 .4byte 0x7 + ff0: 0000 unimp + ff2: 0000 unimp + ff4: 0100 addi s0,sp,128 + ff6: 075a slli a4,a4,0x16 + ... + 1000: a304 .2byte 0xa304 + 1002: 5a01 li s4,-32 + 1004: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 100a: 0000 unimp + 100c: 0000 unimp + 100e: 5a01 li s4,-32 + 1010: 00000007 .4byte 0x7 + 1014: 0000 unimp + 1016: 0000 unimp + 1018: 0400 addi s0,sp,512 + 101a: 9f5a01a3 sb s5,-1565(s4) + 101e: 0700 addi s0,sp,896 + ... + 1028: 5f01 li t5,-32 + 102a: 00000007 .4byte 0x7 + 102e: 0000 unimp + 1030: 0000 unimp + 1032: 0100 addi s0,sp,128 + 1034: 005f 0007 0000 .byte 0x5f, 0x00, 0x07, 0x00, 0x00, 0x00 + 103a: 0000 unimp + 103c: 0000 unimp + 103e: 0100 addi s0,sp,128 + 1040: 005a c.slli zero,0x16 + 1042: 00000007 .4byte 0x7 + 1046: 0000 unimp + 1048: 0000 unimp + 104a: 0100 addi s0,sp,128 + 104c: 005f a807 000a .byte 0x5f, 0x00, 0x07, 0xa8, 0x0a, 0x00 + 1052: cc00 sw s0,24(s0) + 1054: 000a c.slli zero,0x2 + 1056: 0100 addi s0,sp,128 + 1058: 075a slli a4,a4,0x16 + 105a: 0acc addi a1,sp,340 + 105c: 0000 unimp + 105e: 0b54 addi a3,sp,404 + 1060: 0000 unimp + 1062: a304 .2byte 0xa304 + 1064: 5a01 li s4,-32 + 1066: 009f a807 000a .byte 0x9f, 0x00, 0x07, 0xa8, 0x0a, 0x00 + 106c: c800 sw s0,16(s0) + 106e: 000a c.slli zero,0x2 + 1070: 0100 addi s0,sp,128 + 1072: 0ac8075b .4byte 0xac8075b + 1076: 0000 unimp + 1078: 0b54 addi a3,sp,404 + 107a: 0000 unimp + 107c: a304 .2byte 0xa304 + 107e: 5b01 li s6,-32 + 1080: 009f a807 000a .byte 0x9f, 0x00, 0x07, 0xa8, 0x0a, 0x00 + 1086: d300 sw s0,32(a4) + 1088: 000a c.slli zero,0x2 + 108a: 0100 addi s0,sp,128 + 108c: 075c addi a5,sp,900 + 108e: 00000ad3 .4byte 0xad3 + 1092: 0b54 addi a3,sp,404 + 1094: 0000 unimp + 1096: a304 .2byte 0xa304 + 1098: 5c01 li s8,-32 + 109a: 009f c007 000a .byte 0x9f, 0x00, 0x07, 0xc0, 0x0a, 0x00 + 10a0: d300 sw s0,32(a4) + 10a2: 000a c.slli zero,0x2 + 10a4: 0100 addi s0,sp,128 + 10a6: 005f c007 000a .byte 0x5f, 0x00, 0x07, 0xc0, 0x0a, 0x00 + 10ac: e000 .2byte 0xe000 + 10ae: 000a c.slli zero,0x2 + 10b0: 0200 addi s0,sp,256 + 10b2: 9f30 .2byte 0x9f30 + 10b4: 000ae007 .4byte 0xae007 + 10b8: 5400 lw s0,40(s0) + 10ba: 0100000b .4byte 0x100000b + 10be: 005a c.slli zero,0x16 + 10c0: 000ac007 .4byte 0xac007 + 10c4: e800 .2byte 0xe800 + 10c6: 000a c.slli zero,0x2 + 10c8: 0200 addi s0,sp,256 + 10ca: 9f30 .2byte 0x9f30 + 10cc: 000ae807 .4byte 0xae807 + 10d0: 0c00 addi s0,sp,528 + 10d2: 0100000b .4byte 0x100000b + 10d6: 075e slli a4,a4,0x17 + 10d8: 0b30 addi a2,sp,408 + 10da: 0000 unimp + 10dc: 0b44 addi s1,sp,404 + 10de: 0000 unimp + 10e0: 5e01 li t3,-32 + 10e2: 000b4807 .4byte 0xb4807 + 10e6: 5400 lw s0,40(s0) + 10e8: 0100000b .4byte 0x100000b + 10ec: 005e c.slli zero,0x17 + 10ee: 000aec07 .4byte 0xaec07 + 10f2: 0c00 addi s0,sp,528 + 10f4: 0500000b .4byte 0x500000b + 10f8: 007e c.slli zero,0x1f + 10fa: 2448 .2byte 0x2448 + 10fc: 079f 0b0c 0000 .byte 0x9f, 0x07, 0x0c, 0x0b, 0x00, 0x00 + 1102: 0b1c addi a5,sp,400 + 1104: 0000 unimp + 1106: 5e01 li t3,-32 + 1108: 0700 addi s0,sp,896 + 110a: 0aec addi a1,sp,348 + 110c: 0000 unimp + 110e: 0afc addi a5,sp,348 + 1110: 0000 unimp + 1112: 9f7f7a03 .4byte 0x9f7f7a03 + 1116: 000afc07 .4byte 0xafc07 + 111a: 0000 unimp + 111c: 0100000b .4byte 0x100000b + 1120: 075f 0b00 0000 .byte 0x5f, 0x07, 0x00, 0x0b, 0x00, 0x00 + 1126: 0b30 addi a2,sp,408 + 1128: 0000 unimp + 112a: 9f7f7a03 .4byte 0x9f7f7a03 + 112e: 0700 addi s0,sp,896 + 1130: 0aec addi a1,sp,348 + 1132: 0000 unimp + 1134: 0b30 addi a2,sp,408 + 1136: 0000 unimp + 1138: 4004 lw s1,0(s0) + 113a: 2448 .2byte 0x2448 + 113c: 009f f807 000a .byte 0x9f, 0x00, 0x07, 0xf8, 0x0a, 0x00 + 1142: 0400 addi s0,sp,512 + 1144: 0500000b .4byte 0x500000b + 1148: 0078 addi a4,sp,12 + 114a: 2446 .2byte 0x2446 + 114c: 079f 0b04 0000 .byte 0x9f, 0x07, 0x04, 0x0b, 0x00, 0x00 + 1152: 0b14 addi a3,sp,400 + 1154: 0000 unimp + 1156: 5801 li a6,-32 + 1158: 0700 addi s0,sp,896 + 115a: 0af8 addi a4,sp,348 + 115c: 0000 unimp + 115e: 0b30 addi a2,sp,408 + 1160: 0000 unimp + 1162: 3002 .2byte 0x3002 + 1164: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 116a: 0000 unimp + 116c: 0000 unimp + 116e: 0100 addi s0,sp,128 + 1170: 075a slli a4,a4,0x16 + ... + 117a: 5801 li a6,-32 + 117c: 00000007 .4byte 0x7 + 1180: 0000 unimp + 1182: 0000 unimp + 1184: 0100 addi s0,sp,128 + 1186: 005a c.slli zero,0x16 + 1188: 000a6c07 .4byte 0xa6c07 + 118c: 9000 .2byte 0x9000 + 118e: 000a c.slli zero,0x2 + 1190: 0100 addi s0,sp,128 + 1192: 075a slli a4,a4,0x16 + 1194: 0a90 addi a2,sp,336 + 1196: 0000 unimp + 1198: 0a98 addi a4,sp,336 + 119a: 0000 unimp + 119c: 5a01 li s4,-32 + 119e: 0700 addi s0,sp,896 + 11a0: 0a78 addi a4,sp,284 + 11a2: 0000 unimp + 11a4: 0a88 addi a0,sp,336 + 11a6: 0000 unimp + 11a8: 5f01 li t5,-32 + 11aa: 000a8807 .4byte 0xa8807 + 11ae: 8c00 .2byte 0x8c00 + 11b0: 000a c.slli zero,0x2 + 11b2: 0300 addi s0,sp,384 + 11b4: 207f .2byte 0x207f + 11b6: 009f 03b2 0000 .byte 0x9f, 0x00, 0xb2, 0x03, 0x00, 0x00 + 11bc: 0005 c.nop 1 + 11be: 0004 .2byte 0x4 + 11c0: 0000 unimp + 11c2: 0000 unimp + 11c4: 000d9c07 .4byte 0xd9c07 + 11c8: b000 .2byte 0xb000 + 11ca: 000d c.nop 3 + 11cc: 0100 addi s0,sp,128 + 11ce: 075a slli a4,a4,0x16 + 11d0: 0db0 addi a2,sp,728 + 11d2: 0000 unimp + 11d4: 0dd4 addi a3,sp,724 + 11d6: 0000 unimp + 11d8: 5e01 li t3,-32 + 11da: 0700 addi s0,sp,896 + 11dc: 0db0 addi a2,sp,728 + 11de: 0000 unimp + 11e0: 0dd0 addi a2,sp,724 + 11e2: 0000 unimp + 11e4: 5a01 li s4,-32 + 11e6: 000dd007 .4byte 0xdd007 + 11ea: d400 sw s0,40(s0) + 11ec: 000d c.nop 3 + 11ee: 0500 addi s0,sp,640 + 11f0: 00083003 .4byte 0x83003 + 11f4: 0080 addi s0,sp,64 + 11f6: 00000007 .4byte 0x7 + 11fa: 0000 unimp + 11fc: 0000 unimp + 11fe: 0100 addi s0,sp,128 + 1200: 075a slli a4,a4,0x16 + ... + 120a: 0305 addi t1,t1,1 + 120c: 0830 addi a2,sp,24 + 120e: 8000 .2byte 0x8000 + 1210: 0700 addi s0,sp,896 + ... + 121a: 5a01 li s4,-32 + 121c: 00000007 .4byte 0x7 + 1220: 0000 unimp + 1222: 0000 unimp + 1224: 0400 addi s0,sp,512 + 1226: 9f5a01a3 sb s5,-1565(s4) + 122a: 0700 addi s0,sp,896 + ... + 1234: 5b01 li s6,-32 + 1236: 00000007 .4byte 0x7 + 123a: 0000 unimp + 123c: 0000 unimp + 123e: 0100 addi s0,sp,128 + 1240: 0758 addi a4,sp,900 + ... + 124a: 5801 li a6,-32 + 124c: 0700 addi s0,sp,896 + ... + 1256: 5c01 li s8,-32 + 1258: 00000007 .4byte 0x7 + 125c: 0000 unimp + 125e: 0000 unimp + 1260: 0100 addi s0,sp,128 + 1262: 0759 addi a4,a4,22 + ... + 126c: a304 .2byte 0xa304 + 126e: 5c01 li s8,-32 + 1270: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 1276: 0000 unimp + 1278: 0000 unimp + 127a: 5901 li s2,-32 + 127c: 0700 addi s0,sp,896 + ... + 1286: 7b06 .2byte 0x7b06 + 1288: 7c00 .2byte 0x7c00 + 128a: 2200 .2byte 0x2200 + 128c: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 1292: 0000 unimp + 1294: 0000 unimp + 1296: 7806 .2byte 0x7806 + 1298: 7900 .2byte 0x7900 + 129a: 2200 .2byte 0x2200 + 129c: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 12a2: 0000 unimp + 12a4: 0000 unimp + 12a6: 6201 .2byte 0x6201 + 12a8: 00000007 .4byte 0x7 + 12ac: 0000 unimp + 12ae: 0000 unimp + 12b0: 0800 addi s0,sp,16 + 12b2: a35b01a3 sb s5,-1501(s6) + 12b6: 5c01 li s8,-32 + 12b8: 9f22 add t5,t5,s0 + 12ba: 00000007 .4byte 0x7 + 12be: 0000 unimp + 12c0: 0000 unimp + 12c2: 0100 addi s0,sp,128 + 12c4: 0062 c.slli zero,0x18 + 12c6: 00000007 .4byte 0x7 + 12ca: 0000 unimp + 12cc: 0000 unimp + 12ce: 0100 addi s0,sp,128 + 12d0: 075a slli a4,a4,0x16 + ... + 12da: a304 .2byte 0xa304 + 12dc: 5a01 li s4,-32 + 12de: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 12e4: 0000 unimp + 12e6: 0000 unimp + 12e8: 0100 addi s0,sp,128 + 12ea: 075a slli a4,a4,0x16 + ... + 12f4: a304 .2byte 0xa304 + 12f6: 5a01 li s4,-32 + 12f8: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 12fe: 0000 unimp + 1300: 0000 unimp + 1302: 0100 addi s0,sp,128 + 1304: 075a slli a4,a4,0x16 + ... + 130e: a304 .2byte 0xa304 + 1310: 5a01 li s4,-32 + 1312: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1318: 0000 unimp + 131a: 0000 unimp + 131c: 0100 addi s0,sp,128 + 131e: 075a slli a4,a4,0x16 + ... + 1328: a304 .2byte 0xa304 + 132a: 5a01 li s4,-32 + 132c: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1332: 0000 unimp + 1334: 0000 unimp + 1336: 0100 addi s0,sp,128 + 1338: 075a slli a4,a4,0x16 + ... + 1342: a304 .2byte 0xa304 + 1344: 5a01 li s4,-32 + 1346: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 134c: 0000 unimp + 134e: 0000 unimp + 1350: 0100 addi s0,sp,128 + 1352: 0000075b .4byte 0x75b + 1356: 0000 unimp + 1358: 0000 unimp + 135a: 0000 unimp + 135c: 5801 li a6,-32 + 135e: 00000007 .4byte 0x7 + 1362: 0000 unimp + 1364: 0000 unimp + 1366: 0400 addi s0,sp,512 + 1368: 9f5b01a3 sb s5,-1565(s6) + 136c: 0700 addi s0,sp,896 + ... + 1376: 5c01 li s8,-32 + 1378: 00000007 .4byte 0x7 + 137c: 0000 unimp + 137e: 0000 unimp + 1380: 0100 addi s0,sp,128 + 1382: 0759 addi a4,a4,22 + ... + 138c: 5901 li s2,-32 + 138e: 0700 addi s0,sp,896 + ... + 1398: 3002 .2byte 0x3002 + 139a: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 13a0: 0000 unimp + 13a2: 0000 unimp + 13a4: 5901 li s2,-32 + 13a6: 0700 addi s0,sp,896 + ... + 13b0: 5a01 li s4,-32 + 13b2: 00000007 .4byte 0x7 + 13b6: 0000 unimp + 13b8: 0000 unimp + 13ba: 0400 addi s0,sp,512 + 13bc: 9f5a01a3 sb s5,-1565(s4) + 13c0: 0700 addi s0,sp,896 + ... + 13ca: 5a01 li s4,-32 + 13cc: 00000007 .4byte 0x7 + 13d0: 0000 unimp + 13d2: 0000 unimp + 13d4: 0400 addi s0,sp,512 + 13d6: 9f5a01a3 sb s5,-1565(s4) + 13da: 0700 addi s0,sp,896 + ... + 13e4: 5a01 li s4,-32 + 13e6: 00000007 .4byte 0x7 + 13ea: 0000 unimp + 13ec: 0000 unimp + 13ee: 0400 addi s0,sp,512 + 13f0: 9f5a01a3 sb s5,-1565(s4) + 13f4: 0700 addi s0,sp,896 + ... + 13fe: 5a01 li s4,-32 + 1400: 00000007 .4byte 0x7 + 1404: 0000 unimp + 1406: 0000 unimp + 1408: 0400 addi s0,sp,512 + 140a: 9f5a01a3 sb s5,-1565(s4) + 140e: 0700 addi s0,sp,896 + ... + 1418: 5a01 li s4,-32 + 141a: 00000007 .4byte 0x7 + 141e: 0000 unimp + 1420: 0000 unimp + 1422: 0300 addi s0,sp,384 + 1424: 017a slli sp,sp,0x1e + 1426: 079f 0000 0000 .byte 0x9f, 0x07, 0x00, 0x00, 0x00, 0x00 + 142c: 0000 unimp + 142e: 0000 unimp + 1430: a304 .2byte 0xa304 + 1432: 5a01 li s4,-32 + 1434: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 143a: 0000 unimp + 143c: 0000 unimp + 143e: 0100 addi s0,sp,128 + 1440: 075a slli a4,a4,0x16 + ... + 144a: a304 .2byte 0xa304 + 144c: 5a01 li s4,-32 + 144e: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1454: 0000 unimp + 1456: 0000 unimp + 1458: 0100 addi s0,sp,128 + 145a: 075a slli a4,a4,0x16 + ... + 1464: a304 .2byte 0xa304 + 1466: 5a01 li s4,-32 + 1468: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 146e: 0000 unimp + 1470: 0000 unimp + 1472: 0100 addi s0,sp,128 + 1474: 075a slli a4,a4,0x16 + ... + 147e: a304 .2byte 0xa304 + 1480: 5a01 li s4,-32 + 1482: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1488: 0000 unimp + 148a: 0000 unimp + 148c: 0100 addi s0,sp,128 + 148e: 075a slli a4,a4,0x16 + ... + 1498: a304 .2byte 0xa304 + 149a: 5a01 li s4,-32 + 149c: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 14a2: 0000 unimp + 14a4: 0000 unimp + 14a6: 0100 addi s0,sp,128 + 14a8: 075a slli a4,a4,0x16 + ... + 14b2: a304 .2byte 0xa304 + 14b4: 5a01 li s4,-32 + 14b6: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 14bc: 0000 unimp + 14be: 0000 unimp + 14c0: 0100 addi s0,sp,128 + 14c2: 075a slli a4,a4,0x16 + ... + 14cc: a304 .2byte 0xa304 + 14ce: 5a01 li s4,-32 + 14d0: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 14d6: 0000 unimp + 14d8: 0000 unimp + 14da: 0100 addi s0,sp,128 + 14dc: 075a slli a4,a4,0x16 + ... + 14e6: a304 .2byte 0xa304 + 14e8: 5a01 li s4,-32 + 14ea: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 14f0: 0000 unimp + 14f2: 0000 unimp + 14f4: 0100 addi s0,sp,128 + 14f6: 075a slli a4,a4,0x16 + ... + 1500: a304 .2byte 0xa304 + 1502: 5a01 li s4,-32 + 1504: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 150a: 0000 unimp + 150c: 0000 unimp + 150e: 0100 addi s0,sp,128 + 1510: 075a slli a4,a4,0x16 + ... + 151a: a304 .2byte 0xa304 + 151c: 5a01 li s4,-32 + 151e: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1524: 0000 unimp + 1526: 0000 unimp + 1528: 0100 addi s0,sp,128 + 152a: 075a slli a4,a4,0x16 + ... + 1534: a304 .2byte 0xa304 + 1536: 5a01 li s4,-32 + 1538: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 153e: 0000 unimp + 1540: 0000 unimp + 1542: 0100 addi s0,sp,128 + 1544: 075a slli a4,a4,0x16 + ... + 154e: a304 .2byte 0xa304 + 1550: 5a01 li s4,-32 + 1552: 009f 0007 0000 .byte 0x9f, 0x00, 0x07, 0x00, 0x00, 0x00 + 1558: 0000 unimp + 155a: 0000 unimp + 155c: 0100 addi s0,sp,128 + 155e: 075a slli a4,a4,0x16 + ... + 1568: a304 .2byte 0xa304 + 156a: 5a01 li s4,-32 + 156c: 9f 00 Address 0x000000000000156c is out of bounds. + + +Disassembly of section .debug_rnglists: + +00000000 <.debug_rnglists>: + 0: 0054 addi a3,sp,4 + 2: 0000 unimp + 4: 0005 c.nop 1 + 6: 0004 .2byte 0x4 + 8: 0000 unimp + a: 0000 unimp + c: 7806 .2byte 0x7806 + e: 0002 c.slli64 zero + 10: 8000 .2byte 0x8000 + 12: 0002 c.slli64 zero + 14: 0600 addi s0,sp,768 + 16: 0284 addi s1,sp,320 + 18: 0000 unimp + 1a: 0298 addi a4,sp,320 + 1c: 0000 unimp + 1e: 0600 addi s0,sp,768 + 20: 01f0 addi a2,sp,204 + 22: 0000 unimp + 24: 01f0 addi a2,sp,204 + 26: 0000 unimp + 28: f406 .2byte 0xf406 + 2a: 0001 nop + 2c: 4400 lw s0,8(s0) + 2e: 0002 c.slli64 zero + 30: 0000 unimp + 32: 0406 slli s0,s0,0x1 + 34: 0002 c.slli64 zero + 36: 0400 addi s0,sp,512 + 38: 0002 c.slli64 zero + 3a: 0600 addi s0,sp,768 + 3c: 0208 addi a0,sp,256 + 3e: 0000 unimp + 40: 021c addi a5,sp,256 + 42: 0000 unimp + 44: 0600 addi s0,sp,768 + 46: 0278 addi a4,sp,268 + 48: 0000 unimp + 4a: 0298 addi a4,sp,320 + 4c: 0000 unimp + 4e: 8806 mv a6,ra + 50: 0001 nop + 52: 7800 .2byte 0x7800 + 54: 0002 c.slli64 zero + 56: 0000 unimp + 58: 0036 c.slli zero,0xd + 5a: 0000 unimp + 5c: 0005 c.nop 1 + 5e: 0004 .2byte 0x4 + 60: 0000 unimp + 62: 0000 unimp + 64: 0006 c.slli zero,0x1 + 66: 0000 unimp + 68: 0000 unimp + 6a: 0000 unimp + 6c: 0600 addi s0,sp,768 + ... + 76: 9806 add a6,a6,ra + 78: 0002 c.slli64 zero + 7a: ac00 .2byte 0xac00 + 7c: 0002 c.slli64 zero + 7e: 0600 addi s0,sp,768 + ... + 88: 0006 c.slli zero,0x1 + ... + 92: 01d6 slli gp,gp,0x15 + 94: 0000 unimp + 96: 0005 c.nop 1 + 98: 0004 .2byte 0x4 + 9a: 0000 unimp + 9c: 0000 unimp + 9e: ac06 .2byte 0xac06 + a0: 0002 c.slli64 zero + a2: ac00 .2byte 0xac00 + a4: 0002 c.slli64 zero + a6: 0600 addi s0,sp,768 + a8: 02f4 addi a3,sp,332 + aa: 0000 unimp + ac: 02f8 addi a4,sp,332 + ae: 0000 unimp + b0: 0600 addi s0,sp,768 + b2: 050c addi a1,sp,640 + b4: 0000 unimp + b6: 0510 addi a2,sp,640 + b8: 0000 unimp + ba: 2406 .2byte 0x2406 + bc: 0005 c.nop 1 + be: 2800 .2byte 0x2800 + c0: 0005 c.nop 1 + c2: 0600 addi s0,sp,768 + c4: 052c addi a1,sp,648 + c6: 0000 unimp + c8: 053c addi a5,sp,648 + ca: 0000 unimp + cc: 4006 .2byte 0x4006 + ce: 0005 c.nop 1 + d0: 4400 lw s0,8(s0) + d2: 0005 c.nop 1 + d4: 0000 unimp + d6: 8406 mv s0,ra + d8: 0005 c.nop 1 + da: 4c00 lw s0,24(s0) + dc: 06000007 .4byte 0x6000007 + e0: 0760 addi s0,sp,908 + e2: 0000 unimp + e4: 0764 addi s1,sp,908 + e6: 0000 unimp + e8: 6406 .2byte 0x6406 + ea: 68000007 .4byte 0x68000007 + ee: 06000007 .4byte 0x6000007 + f2: 076c addi a1,sp,908 + f4: 0000 unimp + f6: 0820 addi s0,sp,24 + f8: 0000 unimp + fa: 0600 addi s0,sp,768 + fc: 05f4 addi a3,sp,716 + fe: 0000 unimp + 100: 05f8 addi a4,sp,716 + 102: 0000 unimp + 104: 3806 .2byte 0x3806 + 106: 0006 c.slli zero,0x1 + 108: 3c00 .2byte 0x3c00 + 10a: 0006 c.slli zero,0x1 + 10c: 0600 addi s0,sp,768 + 10e: 065c addi a5,sp,772 + 110: 0000 unimp + 112: 0660 addi s0,sp,780 + 114: 0000 unimp + 116: a806 .2byte 0xa806 + 118: 0006 c.slli zero,0x1 + 11a: ac00 .2byte 0xac00 + 11c: 0006 c.slli zero,0x1 + 11e: 0600 addi s0,sp,768 + 120: 06d4 addi a3,sp,836 + 122: 0000 unimp + 124: 06d8 addi a4,sp,836 + 126: 0000 unimp + 128: d806 sw ra,48(sp) + 12a: dc000007 .4byte 0xdc000007 + 12e: 00000007 .4byte 0x7 + 132: 7006 .2byte 0x7006 + 134: 0006 c.slli zero,0x1 + 136: 7800 .2byte 0x7800 + 138: 0006 c.slli zero,0x1 + 13a: 0600 addi s0,sp,768 + 13c: 07dc addi a5,sp,964 + 13e: 0000 unimp + 140: 07dc addi a5,sp,964 + 142: 0000 unimp + 144: 0600 addi s0,sp,768 + 146: 0684 addi s1,sp,832 + 148: 0000 unimp + 14a: 06a0 addi s0,sp,840 + 14c: 0000 unimp + 14e: fc06 .2byte 0xfc06 + 150: 14000007 .4byte 0x14000007 + 154: 0008 .2byte 0x8 + 156: 0000 unimp + 158: e006 .2byte 0xe006 + 15a: 0006 c.slli zero,0x1 + 15c: 4c00 lw s0,24(s0) + 15e: 06000007 .4byte 0x6000007 + 162: 0814 addi a3,sp,16 + 164: 0000 unimp + 166: 0820 addi s0,sp,24 + 168: 0000 unimp + 16a: 0600 addi s0,sp,768 + 16c: 06f8 addi a4,sp,844 + 16e: 0000 unimp + 170: 06f8 addi a4,sp,844 + 172: 0000 unimp + 174: fc06 .2byte 0xfc06 + 176: 0006 c.slli zero,0x1 + 178: 0000 unimp + 17a: 06000007 .4byte 0x6000007 + 17e: 0704 addi s1,sp,896 + 180: 0000 unimp + 182: 0708 addi a0,sp,896 + 184: 0000 unimp + 186: 0c06 slli s8,s8,0x1 + 188: 10000007 .4byte 0x10000007 + 18c: 00000007 .4byte 0x7 + 190: 1c06 slli s8,s8,0x21 + 192: 20000007 .4byte 0x20000007 + 196: 06000007 .4byte 0x6000007 + 19a: 0728 addi a0,sp,904 + 19c: 0000 unimp + 19e: 072c addi a1,sp,904 + 1a0: 0000 unimp + 1a2: 3006 .2byte 0x3006 + 1a4: 40000007 .4byte 0x40000007 + 1a8: 06000007 .4byte 0x6000007 + 1ac: 0744 addi s1,sp,900 + 1ae: 0000 unimp + 1b0: 0748 addi a0,sp,900 + 1b2: 0000 unimp + 1b4: 0600 addi s0,sp,768 + 1b6: 086c addi a1,sp,28 + 1b8: 0000 unimp + 1ba: 086c addi a1,sp,28 + 1bc: 0000 unimp + 1be: 7006 .2byte 0x7006 + 1c0: 0008 .2byte 0x8 + 1c2: 7000 .2byte 0x7000 + 1c4: 0008 .2byte 0x8 + 1c6: 0600 addi s0,sp,768 + 1c8: 087c addi a5,sp,28 + 1ca: 0000 unimp + 1cc: 0884 addi s1,sp,80 + 1ce: 0000 unimp + 1d0: 0600 addi s0,sp,768 + ... + 1da: 0006 c.slli zero,0x1 + ... + 1e4: ac06 .2byte 0xac06 + 1e6: 0002 c.slli64 zero + 1e8: f400 .2byte 0xf400 + 1ea: 0004 .2byte 0x4 + 1ec: 0600 addi s0,sp,768 + 1ee: 04f4 addi a3,sp,588 + 1f0: 0000 unimp + 1f2: 0564 addi s1,sp,652 + 1f4: 0000 unimp + 1f6: 0006 c.slli zero,0x1 + 1f8: 0000 unimp + 1fa: 0000 unimp + 1fc: 0000 unimp + 1fe: 0600 addi s0,sp,768 + ... + 208: 6406 .2byte 0x6406 + 20a: 0005 c.nop 1 + 20c: 3c00 .2byte 0x3c00 + 20e: 0008 .2byte 0x8 + 210: 0600 addi s0,sp,768 + ... + 21a: 3c06 .2byte 0x3c06 + 21c: 0008 .2byte 0x8 + 21e: 6c00 .2byte 0x6c00 + 220: 0008 .2byte 0x8 + 222: 0600 addi s0,sp,768 + 224: 086c addi a1,sp,28 + 226: 0000 unimp + 228: 08c4 addi s1,sp,84 + 22a: 0000 unimp + 22c: 0006 c.slli zero,0x1 + 22e: 0000 unimp + 230: 0000 unimp + 232: 0000 unimp + 234: 0600 addi s0,sp,768 + ... + 23e: 0006 c.slli zero,0x1 + 240: 0000 unimp + 242: 0000 unimp + 244: 0000 unimp + 246: 0600 addi s0,sp,768 + ... + 250: 0006 c.slli zero,0x1 + 252: 0000 unimp + 254: 0000 unimp + 256: 0000 unimp + 258: 0600 addi s0,sp,768 + ... + 262: c406 sw ra,8(sp) + 264: 0008 .2byte 0x8 + 266: 2800 .2byte 0x2800 + 268: 0009 c.nop 2 + 26a: 0000 unimp + 26c: 0145 addi sp,sp,17 + 26e: 0000 unimp + 270: 0005 c.nop 1 + 272: 0004 .2byte 0x4 + 274: 0000 unimp + 276: 0000 unimp + 278: 3006 .2byte 0x3006 + 27a: 000a c.slli zero,0x2 + 27c: 3800 .2byte 0x3800 + 27e: 000a c.slli zero,0x2 + 280: 0600 addi s0,sp,768 + 282: 0a3c addi a5,sp,280 + 284: 0000 unimp + 286: 0a40 addi s0,sp,276 + 288: 0000 unimp + 28a: 4406 lw s0,64(sp) + 28c: 000a c.slli zero,0x2 + 28e: 5400 lw s0,40(s0) + 290: 000a c.slli zero,0x2 + 292: 0600 addi s0,sp,768 + 294: 0a5c addi a5,sp,276 + 296: 0000 unimp + 298: 0a60 addi s0,sp,284 + 29a: 0000 unimp + 29c: 0600 addi s0,sp,768 + 29e: 0928 addi a0,sp,152 + 2a0: 0000 unimp + 2a2: 0a30 addi a2,sp,280 + 2a4: 0000 unimp + 2a6: 3006 .2byte 0x3006 + 2a8: 000a c.slli zero,0x2 + 2aa: 6c00 .2byte 0x6c00 + 2ac: 000a c.slli zero,0x2 + 2ae: 0600 addi s0,sp,768 + 2b0: 0a6c addi a1,sp,284 + 2b2: 0000 unimp + 2b4: 0a98 addi a4,sp,336 + 2b6: 0000 unimp + 2b8: 9806 add a6,a6,ra + 2ba: 000a c.slli zero,0x2 + 2bc: a800 .2byte 0xa800 + 2be: 000a c.slli zero,0x2 + 2c0: 0600 addi s0,sp,768 + 2c2: 0aa8 addi a0,sp,344 + 2c4: 0000 unimp + 2c6: 0b54 addi a3,sp,404 + 2c8: 0000 unimp + 2ca: 0006 c.slli zero,0x1 + 2cc: 0000 unimp + 2ce: 0000 unimp + 2d0: 0000 unimp + 2d2: 0600 addi s0,sp,768 + ... + 2dc: 5406 lw s0,96(sp) + 2de: 6c00000b .4byte 0x6c00000b + 2e2: 0600000b .4byte 0x600000b + ... + 2ee: 0006 c.slli zero,0x1 + 2f0: 0000 unimp + 2f2: 0000 unimp + 2f4: 0000 unimp + 2f6: 0600 addi s0,sp,768 + ... + 300: 0006 c.slli zero,0x1 + 302: 0000 unimp + 304: 0000 unimp + 306: 0000 unimp + 308: 0600 addi s0,sp,768 + ... + 312: 0006 c.slli zero,0x1 + 314: 0000 unimp + 316: 0000 unimp + 318: 0000 unimp + 31a: 0600 addi s0,sp,768 + ... + 324: 6c06 .2byte 0x6c06 + 326: c400000b .4byte 0xc400000b + 32a: 0600000b .4byte 0x600000b + 32e: 0bc4 addi s1,sp,468 + 330: 0000 unimp + 332: 0d9c addi a5,sp,720 + 334: 0000 unimp + 336: 0006 c.slli zero,0x1 + 338: 0000 unimp + 33a: 0000 unimp + 33c: 0000 unimp + 33e: 0600 addi s0,sp,768 + ... + 348: 0006 c.slli zero,0x1 + 34a: 0000 unimp + 34c: 0000 unimp + 34e: 0000 unimp + 350: 0600 addi s0,sp,768 + ... + 35a: 0006 c.slli zero,0x1 + 35c: 0000 unimp + 35e: 0000 unimp + 360: 0000 unimp + 362: 0600 addi s0,sp,768 + ... + 36c: 0006 c.slli zero,0x1 + 36e: 0000 unimp + 370: 0000 unimp + 372: 0000 unimp + 374: 0600 addi s0,sp,768 + ... + 37e: 0006 c.slli zero,0x1 + 380: 0000 unimp + 382: 0000 unimp + 384: 0000 unimp + 386: 0600 addi s0,sp,768 + ... + 390: 0006 c.slli zero,0x1 + 392: 0000 unimp + 394: 0000 unimp + 396: 0000 unimp + 398: 0600 addi s0,sp,768 + ... + 3a2: 0006 c.slli zero,0x1 + 3a4: 0000 unimp + 3a6: 0000 unimp + 3a8: 0000 unimp + 3aa: 0600 addi s0,sp,768 + ... + 3b4: 3b00 .2byte 0x3b00 + 3b6: 0001 nop + 3b8: 0500 addi s0,sp,640 + 3ba: 0400 addi s0,sp,512 + 3bc: 0000 unimp + 3be: 0000 unimp + 3c0: 0600 addi s0,sp,768 + ... + 3ca: 0006 c.slli zero,0x1 + 3cc: 0000 unimp + 3ce: 0000 unimp + 3d0: 0000 unimp + 3d2: 0600 addi s0,sp,768 + ... + 3dc: 0006 c.slli zero,0x1 + 3de: 0000 unimp + 3e0: 0000 unimp + 3e2: 0000 unimp + 3e4: 0600 addi s0,sp,768 + ... + 3ee: 0006 c.slli zero,0x1 + 3f0: 0000 unimp + 3f2: 0000 unimp + 3f4: 0000 unimp + 3f6: 0600 addi s0,sp,768 + ... + 400: 0006 c.slli zero,0x1 + 402: 0000 unimp + 404: 0000 unimp + 406: 0000 unimp + 408: 0600 addi s0,sp,768 + ... + 412: 0006 c.slli zero,0x1 + 414: 0000 unimp + 416: 0000 unimp + 418: 0000 unimp + 41a: 0600 addi s0,sp,768 + ... + 424: 0006 c.slli zero,0x1 + 426: 0000 unimp + 428: 0000 unimp + 42a: 0000 unimp + 42c: 0600 addi s0,sp,768 + ... + 436: 0006 c.slli zero,0x1 + 438: 0000 unimp + 43a: 0000 unimp + 43c: 0000 unimp + 43e: 0600 addi s0,sp,768 + ... + 448: 0006 c.slli zero,0x1 + 44a: 0000 unimp + 44c: 0000 unimp + 44e: 0000 unimp + 450: 0600 addi s0,sp,768 + ... + 45a: 0006 c.slli zero,0x1 + 45c: 0000 unimp + 45e: 0000 unimp + 460: 0000 unimp + 462: 0600 addi s0,sp,768 + ... + 46c: 0006 c.slli zero,0x1 + 46e: 0000 unimp + 470: 0000 unimp + 472: 0000 unimp + 474: 0600 addi s0,sp,768 + ... + 47e: 0006 c.slli zero,0x1 + 480: 0000 unimp + 482: 0000 unimp + 484: 0000 unimp + 486: 0600 addi s0,sp,768 + ... + 490: 0006 c.slli zero,0x1 + 492: 0000 unimp + 494: 0000 unimp + 496: 0000 unimp + 498: 0600 addi s0,sp,768 + ... + 4a2: 0006 c.slli zero,0x1 + 4a4: 0000 unimp + 4a6: 0000 unimp + 4a8: 0000 unimp + 4aa: 0600 addi s0,sp,768 + ... + 4b4: 0006 c.slli zero,0x1 + 4b6: 0000 unimp + 4b8: 0000 unimp + 4ba: 0000 unimp + 4bc: 0600 addi s0,sp,768 + ... + 4c6: 0006 c.slli zero,0x1 + 4c8: 0000 unimp + 4ca: 0000 unimp + 4cc: 0000 unimp + 4ce: 0600 addi s0,sp,768 + ... + 4d8: 0006 c.slli zero,0x1 + 4da: 0000 unimp + 4dc: 0000 unimp + 4de: 0000 unimp + 4e0: 0600 addi s0,sp,768 + ... + 4ea: 9c06 add s8,s8,ra + 4ec: 000d c.nop 3 + 4ee: d400 sw s0,40(s0) + 4f0: 000d c.nop 3 + ... + +Disassembly of section .debug_line_str: + +00000000 <.debug_line_str>: + 0: 616d addi sp,sp,240 + 2: 6e69 lui t3,0x1a + 4: 632e .2byte 0x632e + 6: 2f00 .2byte 0x2f00 + 8: 6f68 .2byte 0x6f68 + a: 656d lui a0,0x1b + c: 7465732f .4byte 0x7465732f + 10: 2f69 jal 7aa <__neorv32_rte_debug_handler+0x246> + 12: 6544 .2byte 0x6544 + 14: 6f746b73 csrrsi s6,0x6f7,8 + 18: 2f70 .2byte 0x2f70 + 1a: 7250 .2byte 0x7250 + 1c: 74656a6f jal s4,56762 <__neorv32_ram_size+0x54762> + 20: 535f 5445 5f49 .byte 0x5f, 0x53, 0x45, 0x54, 0x49, 0x5f + 26: 4952 lw s2,20(sp) + 28: 562d4353 .4byte 0x562d4353 + 2c: 6e61622f .4byte 0x6e61622f + 30: 7764 .2byte 0x7764 + 32: 6469 lui s0,0x1a + 34: 6874 .2byte 0x6874 + 36: 745f 7365 0074 .byte 0x5f, 0x74, 0x65, 0x73, 0x74, 0x00 + 3c: 74706f2f .4byte 0x74706f2f + 40: 7369722f .4byte 0x7369722f + 44: 722f7663 bgeu t5,sp,770 <__neorv32_rte_debug_handler+0x20c> + 48: 7369 lui t1,0xffffa + 4a: 32337663 bgeu t1,gp,376 <__neorv32_rte_core+0xca> + 4e: 752d lui a0,0xfffeb + 50: 6b6e .2byte 0x6b6e + 52: 6f6e .2byte 0x6f6e + 54: 652d6e77 .4byte 0x652d6e77 + 58: 666c .2byte 0x666c + 5a: 636e692f .4byte 0x636e692f + 5e: 756c .2byte 0x756c + 60: 6564 .2byte 0x6564 + 62: 63616d2f .4byte 0x63616d2f + 66: 6968 .2byte 0x6968 + 68: 656e .2byte 0x656e + 6a: 2f00 .2byte 0x2f00 + 6c: 2f74706f j 47b62 <__neorv32_ram_size+0x45b62> + 70: 6972 .2byte 0x6972 + 72: 2f766373 csrrsi t1,0x2f7,12 + 76: 6972 .2byte 0x6972 + 78: 33766373 csrrsi t1,mhpmevent23,12 + 7c: 2d32 .2byte 0x2d32 + 7e: 6e75 lui t3,0x1d + 80: 776f6e6b .4byte 0x776f6e6b + 84: 2d6e .2byte 0x2d6e + 86: 6c65 lui s8,0x19 + 88: 2f66 .2byte 0x2f66 + 8a: 6e69 lui t3,0x1a + 8c: 64756c63 bltu a0,t2,6e4 <__neorv32_rte_debug_handler+0x180> + 90: 2f65 jal 848 + 92: 00737973 csrrci s2,0x7,6 + 96: 74706f2f .4byte 0x74706f2f + 9a: 7369722f .4byte 0x7369722f + 9e: 6c2f7663 bgeu t5,sp,76a <__neorv32_rte_debug_handler+0x206> + a2: 6269 lui tp,0x1a + a4: 6363672f .4byte 0x6363672f + a8: 7369722f .4byte 0x7369722f + ac: 32337663 bgeu t1,gp,3d8 <__neorv32_rte_core+0x12c> + b0: 752d lui a0,0xfffeb + b2: 6b6e .2byte 0x6b6e + b4: 6f6e .2byte 0x6f6e + b6: 652d6e77 .4byte 0x652d6e77 + ba: 666c .2byte 0x666c + bc: 2e32312f .4byte 0x2e32312f + c0: 2e32 .2byte 0x2e32 + c2: 2f30 .2byte 0x2f30 + c4: 6e69 lui t3,0x1a + c6: 64756c63 bltu a0,t2,71e <__neorv32_rte_debug_handler+0x1ba> + ca: 0065 c.nop 25 + cc: 2e2e .2byte 0x2e2e + ce: 6f656e2f .4byte 0x6f656e2f + d2: 7672 .2byte 0x7672 + d4: 732f3233 .4byte 0x732f3233 + d8: 696c2f77 .4byte 0x696c2f77 + dc: 2f62 .2byte 0x2f62 + de: 6e69 lui t3,0x1a + e0: 64756c63 bltu a0,t2,738 <__neorv32_rte_debug_handler+0x1d4> + e4: 0065 c.nop 25 + e6: 74706f2f .4byte 0x74706f2f + ea: 7369722f .4byte 0x7369722f + ee: 722f7663 bgeu t5,sp,81a <__neorv32_rte_debug_handler+0x2b6> + f2: 7369 lui t1,0xffffa + f4: 32337663 bgeu t1,gp,420 <__neorv32_rte_core+0x174> + f8: 752d lui a0,0xfffeb + fa: 6b6e .2byte 0x6b6e + fc: 6f6e .2byte 0x6f6e + fe: 652d6e77 .4byte 0x652d6e77 + 102: 666c .2byte 0x666c + 104: 636e692f .4byte 0x636e692f + 108: 756c .2byte 0x756c + 10a: 6564 .2byte 0x6564 + 10c: 5f00 lw s0,56(a4) + 10e: 6564 .2byte 0x6564 + 110: 6166 .2byte 0x6166 + 112: 6c75 lui s8,0x1d + 114: 5f74 lw a3,124(a4) + 116: 7974 .2byte 0x7974 + 118: 6570 .2byte 0x6570 + 11a: 00682e73 csrrs t3,0x6,a6 + 11e: 735f 6474 6e69 .byte 0x5f, 0x73, 0x74, 0x64, 0x69, 0x6e + 124: 2e74 .2byte 0x2e74 + 126: 0068 addi a0,sp,12 + 128: 64647473 csrrci s0,0x646,8 + 12c: 6665 lui a2,0x19 + 12e: 682e .2byte 0x682e + 130: 6e00 .2byte 0x6e00 + 132: 6f65 lui t5,0x19 + 134: 7672 .2byte 0x7672 + 136: 682e3233 .4byte 0x682e3233 + 13a: 6e00 .2byte 0x6e00 + 13c: 6f65 lui t5,0x19 + 13e: 7672 .2byte 0x7672 + 140: 755f3233 .4byte 0x755f3233 + 144: 7261 lui tp,0xffff8 + 146: 2e74 .2byte 0x2e74 + 148: 0068 addi a0,sp,12 + 14a: 6c647473 csrrci s0,0x6c6,8 + 14e: 6269 lui tp,0x1a + 150: 682e .2byte 0x682e + 152: 6e00 .2byte 0x6e00 + 154: 6f65 lui t5,0x19 + 156: 7672 .2byte 0x7672 + 158: 725f3233 .4byte 0x725f3233 + 15c: 6574 .2byte 0x6574 + 15e: 682e .2byte 0x682e + 160: 6e00 .2byte 0x6e00 + 162: 6f65 lui t5,0x19 + 164: 7672 .2byte 0x7672 + 166: 6d5f3233 .4byte 0x6d5f3233 + 16a: 6974 .2byte 0x6974 + 16c: 656d lui a0,0x1b + 16e: 682e .2byte 0x682e + 170: 2e00 .2byte 0x2e00 + 172: 2f2e .2byte 0x2f2e + 174: 2e2e .2byte 0x2e2e + 176: 2f2e2e2f .4byte 0x2f2e2e2f + 17a: 6c2f7773 csrrci a4,0x6c2,30 + 17e: 6269 lui tp,0x1a + 180: 756f732f .4byte 0x756f732f + 184: 6372 .2byte 0x6372 + 186: 2f65 jal 93e <__neorv32_uart_itoa+0x16> + 188: 656e .2byte 0x656e + 18a: 3376726f jal tp,67cc0 <__neorv32_ram_size+0x65cc0> + 18e: 5f32 lw t5,44(sp) + 190: 746d lui s0,0xffffb + 192: 6d69 lui s10,0x1a + 194: 2e65 jal 54c <__neorv32_rte_print_hex_word+0x58> + 196: 682f0063 beq t5,sp,816 <__neorv32_rte_debug_handler+0x2b2> + 19a: 2f656d6f jal s10,56490 <__neorv32_ram_size+0x54490> + 19e: 69746573 csrrsi a0,0x697,8 + 1a2: 7365442f .4byte 0x7365442f + 1a6: 706f746b .4byte 0x706f746b + 1aa: 6f72502f .4byte 0x6f72502f + 1ae: 656a .2byte 0x656a + 1b0: 5f74 lw a3,124(a4) + 1b2: 49544553 .4byte 0x49544553 + 1b6: 525f 5349 2d43 .byte 0x5f, 0x52, 0x49, 0x53, 0x43, 0x2d + 1bc: 2f56 .2byte 0x2f56 + 1be: 656e .2byte 0x656e + 1c0: 3376726f jal tp,67cf6 <__neorv32_ram_size+0x65cf6> + 1c4: 2f32 .2byte 0x2f32 + 1c6: 652f7773 csrrci a4,0x652,30 + 1ca: 6178 .2byte 0x6178 + 1cc: 706d c.lui zero,0xffffb + 1ce: 656c .2byte 0x656c + 1d0: 7268642f .4byte 0x7268642f + 1d4: 7379 lui t1,0xffffe + 1d6: 6f74 .2byte 0x6f74 + 1d8: 656e .2byte 0x656e + 1da: 2e00 .2byte 0x2e00 + 1dc: 2f2e .2byte 0x2f2e + 1de: 2e2e .2byte 0x2e2e + 1e0: 2f2e2e2f .4byte 0x2f2e2e2f + 1e4: 6c2f7773 csrrci a4,0x6c2,30 + 1e8: 6269 lui tp,0x1a + 1ea: 756f732f .4byte 0x756f732f + 1ee: 6372 .2byte 0x6372 + 1f0: 0065 c.nop 25 + 1f2: 2e2e .2byte 0x2e2e + 1f4: 2f2e2e2f .4byte 0x2f2e2e2f + 1f8: 2e2e .2byte 0x2e2e + 1fa: 2f77732f .4byte 0x2f77732f + 1fe: 696c .2byte 0x696c + 200: 2f62 .2byte 0x2f62 + 202: 6e69 lui t3,0x1a + 204: 64756c63 bltu a0,t2,85c + 208: 0065 c.nop 25 + 20a: 2e2e .2byte 0x2e2e + 20c: 2f2e2e2f .4byte 0x2f2e2e2f + 210: 2e2e .2byte 0x2e2e + 212: 2f77732f .4byte 0x2f77732f + 216: 696c .2byte 0x696c + 218: 2f62 .2byte 0x2f62 + 21a: 72756f73 csrrsi t5,mhpmevent7h,10 + 21e: 6e2f6563 bltu t5,sp,908 + 222: 6f65 lui t5,0x19 + 224: 7672 .2byte 0x7672 + 226: 725f3233 .4byte 0x725f3233 + 22a: 6574 .2byte 0x6574 + 22c: 632e .2byte 0x632e + 22e: 6e00 .2byte 0x6e00 + 230: 6f65 lui t5,0x19 + 232: 7672 .2byte 0x7672 + 234: 635f3233 .4byte 0x635f3233 + 238: 7570 .2byte 0x7570 + 23a: 682e .2byte 0x682e + 23c: 3c00 .2byte 0x3c00 + 23e: 7562 .2byte 0x7562 + 240: 6c69 lui s8,0x1a + 242: 2d74 .2byte 0x2d74 + 244: 6e69 lui t3,0x1a + 246: 003e c.slli zero,0xf + 248: 2e2e .2byte 0x2e2e + 24a: 2f2e2e2f .4byte 0x2f2e2e2f + 24e: 2e2e .2byte 0x2e2e + 250: 2f77732f .4byte 0x2f77732f + 254: 696c .2byte 0x696c + 256: 2f62 .2byte 0x2f62 + 258: 72756f73 csrrsi t5,mhpmevent7h,10 + 25c: 6e2f6563 bltu t5,sp,946 <__neorv32_uart_itoa+0x1e> + 260: 6f65 lui t5,0x19 + 262: 7672 .2byte 0x7672 + 264: 755f3233 .4byte 0x755f3233 + 268: 7261 lui tp,0xffff8 + 26a: 2e74 .2byte 0x2e74 + 26c: 74730063 beq t1,t2,9ac <__neorv32_uart_itoa+0x84> + 270: 6164 .2byte 0x6164 + 272: 6772 .2byte 0x6772 + 274: 682e .2byte 0x682e + 276: 2e00 .2byte 0x2e00 + 278: 2f2e .2byte 0x2f2e + 27a: 2e2e .2byte 0x2e2e + 27c: 2f2e2e2f .4byte 0x2f2e2e2f + 280: 6c2f7773 csrrci a4,0x6c2,30 + 284: 6269 lui tp,0x1a + 286: 756f732f .4byte 0x756f732f + 28a: 6372 .2byte 0x6372 + 28c: 2f65 jal a44 <__neorv32_uart_tohex+0x14> + 28e: 63737973 csrrci s2,0x637,6 + 292: 6c61 lui s8,0x18 + 294: 736c .2byte 0x736c + 296: 632e .2byte 0x632e + 298: 5f00 lw s0,56(a4) + 29a: 6974 .2byte 0x6974 + 29c: 656d lui a0,0x1b + 29e: 6176 .2byte 0x6176 + 2a0: 2e6c .2byte 0x2e6c + 2a2: 0068 addi a0,sp,12 + 2a4: 745f 6d69 7365 .byte 0x5f, 0x74, 0x69, 0x6d, 0x65, 0x73 + 2aa: 6570 .2byte 0x6570 + 2ac: 00682e63 .4byte 0x682e63 + 2b0: 74617473 csrrci s0,0x746,2 + 2b4: 682e .2byte 0x682e + 2b6: 7400 .2byte 0x7400 + 2b8: 6d69 lui s10,0x1a + 2ba: 6265 lui tp,0x19 + 2bc: 682e .2byte 0x682e + 2be: 7400 .2byte 0x7400 + 2c0: 6d69 lui s10,0x1a + 2c2: 7365 lui t1,0xffff9 + 2c4: 682e .2byte 0x682e + 2c6: 7500 .2byte 0x7500 + 2c8: 6974 .2byte 0x6974 + 2ca: 656d lui a0,0x1b + 2cc: 682e .2byte 0x682e + 2ce: 7500 .2byte 0x7500 + 2d0: 696e .2byte 0x696e + 2d2: 2e647473 csrrci s0,0x2e6,8 + 2d6: 0068 addi a0,sp,12 + 2d8: 30747263 bgeu s0,t2,5dc <__neorv32_rte_debug_handler+0x78> + 2dc: 532e lw t1,232(sp) + 2de: 2f00 .2byte 0x2f00 + 2e0: 6f68 .2byte 0x6f68 + 2e2: 656d lui a0,0x1b + 2e4: 7465732f .4byte 0x7465732f + 2e8: 2f69 jal a82 <__neorv32_uart_touppercase.constprop.0+0x16> + 2ea: 6972 .2byte 0x6972 + 2ec: 2d766373 csrrsi t1,0x2d7,12 + 2f0: 2d756e67 .4byte 0x2d756e67 + 2f4: 6f74 .2byte 0x6f74 + 2f6: 68636c6f jal s8,3697c <__neorv32_ram_size+0x3497c> + 2fa: 6961 lui s2,0x18 + 2fc: 2f6e .2byte 0x2f6e + 2fe: 7562 .2byte 0x7562 + 300: 6c69 lui s8,0x1a + 302: 2d64 .2byte 0x2d64 + 304: 2d636367 .4byte 0x2d636367 + 308: 656e .2byte 0x656e + 30a: 62696c77 .4byte 0x62696c77 + 30e: 732d lui t1,0xfffeb + 310: 6174 .2byte 0x6174 + 312: 2f326567 .4byte 0x2f326567 + 316: 6972 .2byte 0x6972 + 318: 33766373 csrrsi t1,mhpmevent23,12 + 31c: 2d32 .2byte 0x2d32 + 31e: 6e75 lui t3,0x1d + 320: 776f6e6b .4byte 0x776f6e6b + 324: 2d6e .2byte 0x2d6e + 326: 6c65 lui s8,0x19 + 328: 2f66 .2byte 0x2f66 + 32a: 696c .2byte 0x696c + 32c: 6762 .2byte 0x6762 + 32e: 2f006363 bltu zero,a6,614 <__neorv32_rte_debug_handler+0xb0> + 332: 6f68 .2byte 0x6f68 + 334: 656d lui a0,0x1b + 336: 7465732f .4byte 0x7465732f + 33a: 2f69 jal ad4 + 33c: 6972 .2byte 0x6972 + 33e: 2d766373 csrrsi t1,0x2d7,12 + 342: 2d756e67 .4byte 0x2d756e67 + 346: 6f74 .2byte 0x6f74 + 348: 68636c6f jal s8,369ce <__neorv32_ram_size+0x349ce> + 34c: 6961 lui s2,0x18 + 34e: 2f6e .2byte 0x2f6e + 350: 2f636367 .4byte 0x2f636367 + 354: 696c .2byte 0x696c + 356: 6762 .2byte 0x6762 + 358: 632f6363 bltu t5,s2,97e <__neorv32_uart_itoa+0x56> + 35c: 69666e6f jal t3,669f2 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zY#=Sw@N6{&9!RC%jzE7^77d8eEx8)^6!KrutW%dmO*Sv;Vx;ey)rDhxSn}92zS`oS zl)Bfr&m;MvE diff --git a/neorv32/rtl/core/neorv32_top.vhd.bak b/neorv32/rtl/core/neorv32_top.vhd.bak new file mode 100644 index 000000000..061ac4ee8 --- /dev/null +++ b/neorv32/rtl/core/neorv32_top.vhd.bak @@ -0,0 +1,1740 @@ +-- ################################################################################################# +-- # << The NEORV32 RISC-V Processor - Top Entity >> # +-- # ********************************************************************************************* # +-- # Check out the processor's online documentation for more information: # +-- # HQ: https://github.com/stnolting/neorv32 # +-- # Data Sheet: https://stnolting.github.io/neorv32 # +-- # User Guide: https://stnolting.github.io/neorv32/ug # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; +use neorv32.neorv32_package.all; + +entity neorv32_top is + generic ( + -- General -- + CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + CUSTOM_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID + INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit? + + -- Tuning Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + CPU_IPB_ENTRIES : natural := 1; -- entries in instruction prefetch buffer, has to be a power of 2, min 1 + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16) + PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory (IMEM) -- + MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory (DMEM) -- + MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes + + -- Internal Instruction Cache (iCACHE) -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface (WISHBONE) -- + MEM_EXT_EN : boolean := false; -- implement external memory bus interface? + MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled) + MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian + MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false + MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false + + -- Stream link interface (SLINK) -- + SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) + SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) + SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two + + -- External Interrupts Controller (XIRQ) -- + XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + + -- Processor peripherals -- + IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 + IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 + IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)? + IO_SPI_FIFO : natural := 0; -- SPI RTX fifo depth, has to be zero or a power of two + IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? + IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1 + IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic + IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits + IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two + IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? + IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)? + IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)? + ); + port ( + -- Global control -- + clk_i : in std_ulogic; -- global clock, rising edge + rstn_i : in std_ulogic; -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional) + jtag_tck_i : in std_ulogic := 'U'; -- serial clock + jtag_tdi_i : in std_ulogic := 'U'; -- serial data input + jtag_tdo_o : out std_ulogic; -- serial data output + jtag_tms_i : in std_ulogic := 'U'; -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o : out std_ulogic_vector(02 downto 0); -- request tag + wb_adr_o : out std_ulogic_vector(31 downto 0); -- address + wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => 'U'); -- read data + wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data + wb_we_o : out std_ulogic; -- read/write + wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable + wb_stb_o : out std_ulogic; -- strobe + wb_cyc_o : out std_ulogic; -- valid cycle + wb_ack_i : in std_ulogic := 'L'; -- transfer acknowledge + wb_err_i : in std_ulogic := 'L'; -- transfer error + + -- Advanced memory control signals -- + fence_o : out std_ulogic; -- indicates an executed FENCE operation + fencei_o : out std_ulogic; -- indicates an executed FENCEI operation + + -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- + xip_csn_o : out std_ulogic; -- chip-select, low-active + xip_clk_o : out std_ulogic; -- serial clock + xip_sdi_i : in std_ulogic := 'L'; -- device data input + xip_sdo_o : out std_ulogic; -- controller data output + + -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- + slink_tx_dat_o : out sdata_8x32_t; -- output data + slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output + slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send + slink_tx_lst_o : out std_ulogic_vector(7 downto 0); -- last data of packet + + -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- + slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data + slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input + slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive + slink_rx_lst_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- last data of packet + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output + gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o : out std_ulogic; -- UART0 send data + uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data + uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o : out std_ulogic; -- UART1 send data + uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data + uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o : out std_ulogic; -- SPI serial clock + spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in + spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out + spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io : inout std_logic; -- twi serial data line + twi_scl_io : inout std_logic; -- twi serial clock line + + -- 1-Wire Interface (available if IO_ONEWIRE_EN = true) -- + onewire_io : inout std_logic; -- 1-wire bus + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o : out std_ulogic_vector(59 downto 0); -- pwm channels + + -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- + cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit + cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o : out std_ulogic; -- async serial data line + + -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- + xirq_i : in std_ulogic_vector(31 downto 0) := (others => 'L'); -- IRQ channels + + -- CPU interrupts -- + mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt + mext_irq_i : in std_ulogic := 'L' -- machine external interrupt + ); +end neorv32_top; + +architecture neorv32_top_rtl of neorv32_top is + + -- CPU boot configuration -- + constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(INT_BOOTLOADER_EN, boot_rom_base_c, ispace_base_c); + + -- alignment check for internal memories -- + constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0'); + constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0'); + + -- helpers -- + constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all? + + -- reset generator -- + signal rstn_ext_sreg : std_ulogic_vector(3 downto 0); + signal rstn_int_sreg : std_ulogic_vector(3 downto 0); + signal rstn_ext : std_ulogic; + signal rstn_int : std_ulogic; + signal rstn_wdt : std_ulogic; + + -- clock generator -- + signal clk_div : std_ulogic_vector(11 downto 0); + signal clk_div_ff : std_ulogic_vector(11 downto 0); + signal clk_gen : std_ulogic_vector(07 downto 0); + signal clk_gen_en : std_ulogic_vector(10 downto 0); + signal clk_gen_en_ff : std_ulogic; + -- + signal wdt_cg_en : std_ulogic; + signal uart0_cg_en : std_ulogic; + signal uart1_cg_en : std_ulogic; + signal spi_cg_en : std_ulogic; + signal twi_cg_en : std_ulogic; + signal pwm_cg_en : std_ulogic; + signal cfs_cg_en : std_ulogic; + signal neoled_cg_en : std_ulogic; + signal gptmr_cg_en : std_ulogic; + signal xip_cg_en : std_ulogic; + signal onewire_cg_en : std_ulogic; + + -- CPU status -- + type cpu_status_t is record + debug : std_ulogic; -- set when in debug mode + sleep : std_ulogic; -- set when in sleep mode + end record; + signal cpu_s : cpu_status_t; + + -- bus interface - instruction fetch -- + type bus_i_interface_t is record + addr : std_ulogic_vector(31 downto 0); -- bus access address + rdata : std_ulogic_vector(31 downto 0); -- bus read data + re : std_ulogic; -- read request + ack : std_ulogic; -- bus transfer acknowledge + err : std_ulogic; -- bus transfer error + fence : std_ulogic; -- fence.i instruction executed + src : std_ulogic; -- access source (1=instruction fetch, 0=data access) + cached : std_ulogic; -- cached transfer + priv : std_ulogic; -- set when in privileged machine mode + end record; + signal cpu_i, i_cache : bus_i_interface_t; + + -- bus interface - data access -- + type bus_d_interface_t is record + addr : std_ulogic_vector(31 downto 0); -- bus access address + rdata : std_ulogic_vector(31 downto 0); -- bus read data + wdata : std_ulogic_vector(31 downto 0); -- bus write data + ben : std_ulogic_vector(03 downto 0); -- byte enable + we : std_ulogic; -- write request + re : std_ulogic; -- read request + ack : std_ulogic; -- bus transfer acknowledge + err : std_ulogic; -- bus transfer error + fence : std_ulogic; -- fence instruction executed + src : std_ulogic; -- access source (1=instruction fetch, 0=data access) + cached : std_ulogic; -- cached transfer + priv : std_ulogic; -- set when in privileged machine mode + end record; + signal cpu_d, p_bus : bus_d_interface_t; + + -- bus access error (from BUSKEEPER) -- + signal bus_error : std_ulogic; + + -- debug core interface (DCI) -- + signal dci_ndmrstn : std_ulogic; + signal dci_halt_req : std_ulogic; + + -- debug module interface (DMI) -- + type dmi_t is record + req_valid : std_ulogic; + req_ready : std_ulogic; -- DMI is allowed to make new requests when set + req_address : std_ulogic_vector(05 downto 0); + req_op : std_ulogic_vector(01 downto 0); + req_data : std_ulogic_vector(31 downto 0); + rsp_valid : std_ulogic; -- response valid when set + rsp_ready : std_ulogic; -- ready to receive respond + rsp_data : std_ulogic_vector(31 downto 0); + rsp_op : std_ulogic_vector(01 downto 0); + end record; + signal dmi : dmi_t; + + -- io space access -- + signal io_acc : std_ulogic; + signal io_rden : std_ulogic; + signal io_wren : std_ulogic; + + -- module response bus - entry type -- + type resp_bus_entry_t is record + rdata : std_ulogic_vector(31 downto 0); + ack : std_ulogic; + err : std_ulogic; + end record; + + -- termination for unused/unimplemented bus endpoints -- + constant resp_bus_entry_terminate_c : resp_bus_entry_t := (rdata => (others => '0'), ack => '0', err => '0'); + + -- module response bus - device ID -- + type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO, + RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI, RESP_TWI, RESP_PWM, RESP_WDT, + RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ, + RESP_GPTMR, RESP_XIP_CT, RESP_XIP_ACC, RESP_ONEWIRE); + + -- module response bus -- + type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t; + signal resp_bus : resp_bus_t := (others => resp_bus_entry_terminate_c); + + -- IRQs -- + signal fast_irq : std_ulogic_vector(15 downto 0); + signal mtime_irq : std_ulogic; + signal wdt_irq : std_ulogic; + signal uart0_rxd_irq : std_ulogic; + signal uart0_txd_irq : std_ulogic; + signal uart1_rxd_irq : std_ulogic; + signal uart1_txd_irq : std_ulogic; + signal spi_irq : std_ulogic; + signal twi_irq : std_ulogic; + signal cfs_irq : std_ulogic; + signal neoled_irq : std_ulogic; + signal slink_tx_irq : std_ulogic; + signal slink_rx_irq : std_ulogic; + signal xirq_irq : std_ulogic; + signal gptmr_irq : std_ulogic; + signal onewire_irq : std_ulogic; + + -- tri-state drivers -- + signal twi_sda_i, twi_sda_o : std_ulogic; + signal twi_scl_i, twi_scl_o : std_ulogic; + signal onewire_i, onewire_o : std_ulogic; + + -- misc -- + signal ext_timeout : std_ulogic; + signal ext_access : std_ulogic; + signal xip_access : std_ulogic; + signal xip_enable : std_ulogic; + signal xip_page : std_ulogic_vector(3 downto 0); + +begin + + -- Processor IO/Peripherals Configuration ------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert false report + "NEORV32 PROCESSOR CONFIG NOTE: Peripherals = " & + cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") & + cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") & + cond_sel_string_f(IO_UART0_EN, "UART0 ", "") & + cond_sel_string_f(IO_UART1_EN, "UART1 ", "") & + cond_sel_string_f(IO_SPI_EN, "SPI ", "") & + cond_sel_string_f(IO_TWI_EN, "TWI ", "") & + cond_sel_string_f(boolean(IO_PWM_NUM_CH > 0), "PWM ", "") & + cond_sel_string_f(IO_WDT_EN, "WDT ", "") & + cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") & + cond_sel_string_f(IO_CFS_EN, "CFS ", "") & + cond_sel_string_f(io_slink_en_c, "SLINK ", "") & + cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") & + cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") & + cond_sel_string_f(IO_GPTMR_EN, "GPTMR ", "") & + cond_sel_string_f(IO_XIP_EN, "XIP ", "") & + cond_sel_string_f(IO_ONEWIRE_EN, "ONEWIRE ", "") & + "" + severity note; + + + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + -- boot configuration -- + assert not (INT_BOOTLOADER_EN = true) report + "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration: Indirect boot via bootloader (processor-internal BOOTROM)." severity note; + assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = true)) report + "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration = direct boot from memory (processor-internal IMEM)." severity note; + assert not ((INT_BOOTLOADER_EN = false) and (MEM_INT_IMEM_EN = false)) report + "NEORV32 PROCESSOR CONFIG NOTE: Boot configuration = direct boot from memory (processor-external memory)." severity note; + -- + assert not ((MEM_EXT_EN = false) and (MEM_INT_DMEM_EN = false)) report + "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal IMEM." severity error; + assert not ((MEM_EXT_EN = false) and (MEM_INT_IMEM_EN = false) and (INT_BOOTLOADER_EN = false)) report + "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal IMEM and bootloader." severity error; + + -- memory size -- + assert not ((MEM_INT_DMEM_EN = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report + "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; + assert not ((MEM_INT_IMEM_EN = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report + "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; + + -- memory layout -- + assert not (ispace_base_c(1 downto 0) /= "00") report + "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 32-bit-aligned." severity error; + assert not (dspace_base_c(1 downto 0) /= "00") report + "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 32-bit-aligned." severity error; + assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_EN = true)) report + "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error; + assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_EN = true)) report + "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error; + -- + assert not (ispace_base_c /= x"00000000") report + "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for INSTRUCTION ADDRESS SPACE. Make sure this is sync with the software framework." severity warning; + assert not (dspace_base_c /= x"80000000") report + "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for DATA ADDRESS SPACE. Make sure this is sync with the software framework." severity warning; + + -- on-chip debugger -- + assert not (ON_CHIP_DEBUGGER_EN = true) report + "NEORV32 PROCESSOR CONFIG NOTE: Implementing on-chip debugger (OCD)." severity note; + + -- instruction cache -- + assert not ((ICACHE_EN = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report + "NEORV32 CPU CONFIG WARNING! The is required to perform i-cache memory sync operations." severity warning; + + +-- **************************************************************************************************************************** +-- Clock and Reset System +-- **************************************************************************************************************************** + + + -- Reset Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + reset_generator: process(rstn_i, clk_i) + begin + if (rstn_i = '0') then + rstn_ext_sreg <= (others => '0'); + rstn_int_sreg <= (others => '0'); + rstn_ext <= '0'; + rstn_int <= '0'; + elsif falling_edge(clk_i) then -- inverted clock to release reset _before_ all FFs trigger (rising edge) + -- external reset -- + rstn_ext_sreg <= rstn_ext_sreg(rstn_ext_sreg'left-1 downto 0) & '1'; -- active for at least clock cycles + -- internal reset -- + if (rstn_wdt = '0') or (dci_ndmrstn = '0') then -- sync reset sources + rstn_int_sreg <= (others => '0'); + else + rstn_int_sreg <= rstn_int_sreg(rstn_int_sreg'left-1 downto 0) & '1'; -- active for at least clock cycles + end if; + -- reset nets -- + rstn_ext <= and_reduce_f(rstn_ext_sreg); -- external reset (via reset pin) + rstn_int <= and_reduce_f(rstn_int_sreg); -- internal reset (via reset pin, WDT or OCD) + end if; + end process reset_generator; + + + -- Clock Generator ------------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + clock_generator: process(rstn_int, clk_i) + begin + if (rstn_int = '0') then + clk_gen_en_ff <= '0'; + clk_div <= (others => '0'); + clk_div_ff <= (others => '0'); + elsif rising_edge(clk_i) then + clk_gen_en_ff <= or_reduce_f(clk_gen_en); + if (clk_gen_en_ff = '1') then + clk_div <= std_ulogic_vector(unsigned(clk_div) + 1); + else -- reset if disabled + clk_div <= (others => '0'); + end if; + clk_div_ff <= clk_div; + end if; + end process clock_generator; + + -- clock enables: rising edge detectors -- + clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2 + clk_gen(clk_div4_c) <= clk_div(1) and (not clk_div_ff(1)); -- CLK/4 + clk_gen(clk_div8_c) <= clk_div(2) and (not clk_div_ff(2)); -- CLK/8 + clk_gen(clk_div64_c) <= clk_div(5) and (not clk_div_ff(5)); -- CLK/64 + clk_gen(clk_div128_c) <= clk_div(6) and (not clk_div_ff(6)); -- CLK/128 + clk_gen(clk_div1024_c) <= clk_div(9) and (not clk_div_ff(9)); -- CLK/1024 + clk_gen(clk_div2048_c) <= clk_div(10) and (not clk_div_ff(10)); -- CLK/2048 + clk_gen(clk_div4096_c) <= clk_div(11) and (not clk_div_ff(11)); -- CLK/4096 + + -- fresh clocks anyone? -- + clk_gen_en(0) <= wdt_cg_en; + clk_gen_en(1) <= uart0_cg_en; + clk_gen_en(2) <= uart1_cg_en; + clk_gen_en(3) <= spi_cg_en; + clk_gen_en(4) <= twi_cg_en; + clk_gen_en(5) <= pwm_cg_en; + clk_gen_en(6) <= cfs_cg_en; + clk_gen_en(7) <= neoled_cg_en; + clk_gen_en(8) <= gptmr_cg_en; + clk_gen_en(9) <= xip_cg_en; + clk_gen_en(10) <= onewire_cg_en; + + +-- **************************************************************************************************************************** +-- CPU Core Complex +-- **************************************************************************************************************************** + + + -- CPU Core ------------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cpu_inst: neorv32_cpu + generic map ( + -- General -- + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id + CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address + CPU_DEBUG_PARK_ADDR => dm_park_entry_c, -- cpu debug mode parking loop entry address + CPU_DEBUG_EXC_ADDR => dm_exc_entry_c, -- cpu debug mode exception entry address + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? + CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? + CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit? + CPU_EXTENSION_RISCV_Sdext => ON_CHIP_DEBUGGER_EN, -- implement external debug mode extension? + CPU_EXTENSION_RISCV_Sdtrig => ON_CHIP_DEBUGGER_EN, -- implement debug mode trigger module extension? + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries is instruction prefetch buffer, has to be a power of 1 + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH -- total size of HPM counters (0..64) + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_int, -- global reset, low-active, async + sleep_o => cpu_s.sleep, -- cpu is in sleep mode when set + debug_o => cpu_s.debug, -- cpu is in debug mode when set + -- instruction bus interface -- + i_bus_addr_o => cpu_i.addr, -- bus access address + i_bus_rdata_i => cpu_i.rdata, -- bus read data + i_bus_re_o => cpu_i.re, -- read request + i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge + i_bus_err_i => cpu_i.err, -- bus transfer error + i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation + i_bus_priv_o => cpu_i.priv, -- current effective privilege level + -- data bus interface -- + d_bus_addr_o => cpu_d.addr, -- bus access address + d_bus_rdata_i => cpu_d.rdata, -- bus read data + d_bus_wdata_o => cpu_d.wdata, -- bus write data + d_bus_ben_o => cpu_d.ben, -- byte enable + d_bus_we_o => cpu_d.we, -- write request + d_bus_re_o => cpu_d.re, -- read request + d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge + d_bus_err_i => cpu_d.err, -- bus transfer error + d_bus_fence_o => cpu_d.fence, -- executed FENCE operation + d_bus_priv_o => cpu_d.priv, -- current effective privilege level + -- non-maskable interrupt -- + msw_irq_i => msw_irq_i, -- machine software interrupt + mext_irq_i => mext_irq_i, -- machine external interrupt request + mtime_irq_i => mtime_irq, -- machine timer interrupt + -- fast interrupts (custom) -- + firq_i => fast_irq, -- fast interrupt trigger + -- debug mode (halt) request -- + db_halt_req_i => dci_halt_req + ); + + -- misc -- + cpu_i.src <= '1'; -- initialized but unused + cpu_d.src <= '0'; -- initialized but unused + cpu_i.cached <= '0'; -- initialized but unused + cpu_d.cached <= '0'; -- no data cache available yet + + -- advanced memory control -- + fence_o <= cpu_d.fence; -- indicates an executed FENCE operation + fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation + + -- fast interrupt requests (FIRQs) - triggers are SINGLE-SHOT -- + fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog + fast_irq(01) <= cfs_irq; -- custom functions subsystem + fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX + fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX + fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX + fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX + fast_irq(06) <= spi_irq; -- SPI transfer done + fast_irq(07) <= twi_irq; -- TWI transfer done + fast_irq(08) <= xirq_irq; -- external interrupt controller + fast_irq(09) <= neoled_irq; -- NEOLED buffer IRQ + fast_irq(10) <= slink_rx_irq; -- SLINK RX + fast_irq(11) <= slink_tx_irq; -- SLINK TX + fast_irq(12) <= gptmr_irq; -- general purpose timer match + fast_irq(13) <= onewire_irq; -- ONEWIRE operation done + -- + fast_irq(14) <= '0'; -- reserved + fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved + + + -- CPU Instruction Cache ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_icache_inst_true: + if (ICACHE_EN = true) generate + neorv32_icache_inst: neorv32_icache + generic map ( + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 + ICACHE_NUM_SETS => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2 + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_int, -- global reset, low-active, async + clear_i => cpu_i.fence, -- cache clear + miss_o => open, -- cache miss + -- host controller interface -- + host_addr_i => cpu_i.addr, -- bus access address + host_rdata_o => cpu_i.rdata, -- bus read data + host_re_i => cpu_i.re, -- read enable + host_ack_o => cpu_i.ack, -- bus transfer acknowledge + host_err_o => cpu_i.err, -- bus transfer error + -- peripheral bus interface -- + bus_cached_o => i_cache.cached, -- set if cached (!) access in progress + bus_addr_o => i_cache.addr, -- bus access address + bus_rdata_i => i_cache.rdata, -- bus read data + bus_re_o => i_cache.re, -- read enable + bus_ack_i => i_cache.ack, -- bus transfer acknowledge + bus_err_i => i_cache.err -- bus transfer error + ); + i_cache.priv <= cpu_i.priv; + end generate; + + neorv32_icache_inst_false: + if (ICACHE_EN = false) generate + i_cache.addr <= cpu_i.addr; + cpu_i.rdata <= i_cache.rdata; + i_cache.re <= cpu_i.re; + cpu_i.ack <= i_cache.ack; + cpu_i.err <= i_cache.err; + i_cache.cached <= '0'; -- single transfer (uncached) + i_cache.priv <= cpu_i.priv; + end generate; + + -- yet unused -- + i_cache.fence <= '0'; + i_cache.src <= '0'; + + + -- CPU Bus Switch ------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_busswitch_inst: neorv32_busswitch + generic map ( + PORT_CA_READ_ONLY => false, -- set if controller port A is read-only + PORT_CB_READ_ONLY => true -- set if controller port B is read-only + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_int, -- global reset, low-active, async + -- controller interface a -- + ca_bus_priv_i => cpu_d.priv, -- current privilege level + ca_bus_cached_i => cpu_d.cached, -- set if cached transfer + ca_bus_addr_i => cpu_d.addr, -- bus access address + ca_bus_rdata_o => cpu_d.rdata, -- bus read data + ca_bus_wdata_i => cpu_d.wdata, -- bus write data + ca_bus_ben_i => cpu_d.ben, -- byte enable + ca_bus_we_i => cpu_d.we, -- write enable + ca_bus_re_i => cpu_d.re, -- read enable + ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge + ca_bus_err_o => cpu_d.err, -- bus transfer error + -- controller interface b -- + cb_bus_priv_i => i_cache.priv, -- current privilege level + cb_bus_cached_i => i_cache.cached, -- set if cached transfer + cb_bus_addr_i => i_cache.addr, -- bus access address + cb_bus_rdata_o => i_cache.rdata, -- bus read data + cb_bus_wdata_i => (others => '0'), + cb_bus_ben_i => (others => '0'), + cb_bus_we_i => '0', + cb_bus_re_i => i_cache.re, -- read enable + cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge + cb_bus_err_o => i_cache.err, -- bus transfer error + -- peripheral bus -- + p_bus_priv_o => p_bus.priv, -- current privilege level + p_bus_cached_o => p_bus.cached, -- set if cached transfer + p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) + p_bus_addr_o => p_bus.addr, -- bus access address + p_bus_rdata_i => p_bus.rdata, -- bus read data + p_bus_wdata_o => p_bus.wdata, -- bus write data + p_bus_ben_o => p_bus.ben, -- byte enable + p_bus_we_o => p_bus.we, -- write enable + p_bus_re_o => p_bus.re, -- read enable + p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge + p_bus_err_i => bus_error -- bus transfer error + ); + + -- any fence operation? -- + p_bus.fence <= cpu_i.fence or cpu_d.fence; + + -- bus response -- + bus_response: process(resp_bus) + variable rdata_v : std_ulogic_vector(31 downto 0); + variable ack_v : std_ulogic; + variable err_v : std_ulogic; + begin + rdata_v := (others => '0'); + ack_v := '0'; + err_v := '0'; + -- OR all response signals: only the module that has actually + -- been accessed is allowed to *set* its bus output signals + for i in resp_bus'range loop + rdata_v := rdata_v or resp_bus(i).rdata; -- read data + ack_v := ack_v or resp_bus(i).ack; -- acknowledge + err_v := err_v or resp_bus(i).err; -- error + end loop; -- i + p_bus.rdata <= rdata_v; -- processor bus: CPU transfer data input + p_bus.ack <= ack_v; -- processor bus: CPU transfer ACK input + p_bus.err <= err_v; -- processor bus: CPU transfer data bus error input + end process; + + + -- Bus Keeper (BUSKEEPER) ----------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_bus_keeper_inst: neorv32_bus_keeper + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, use as async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- byte write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_BUSKEEPER).rdata, -- data out + ack_o => resp_bus(RESP_BUSKEEPER).ack, -- transfer acknowledge + err_o => bus_error, -- transfer error + -- bus monitoring -- + bus_addr_i => p_bus.addr, -- address + bus_rden_i => p_bus.re, -- read enable + bus_wren_i => p_bus.we, -- write enable + bus_ack_i => p_bus.ack, -- transfer acknowledge from bus system + bus_err_i => p_bus.err, -- transfer error from bus system + bus_tmo_i => ext_timeout, -- transfer timeout (external interface) + bus_ext_i => ext_access, -- external bus access + bus_xip_i => xip_access -- pending XIP access + ); + + -- unused, BUSKEEPER issues error to **directly** the CPU -- + resp_bus(RESP_BUSKEEPER).err <= '0'; + + +-- **************************************************************************************************************************** +-- Memory System +-- **************************************************************************************************************************** + + + -- Processor-Internal Instruction Memory (IMEM) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_int_imem_inst_true: + if (MEM_INT_IMEM_EN = true) and (MEM_INT_IMEM_SIZE > 0) generate + neorv32_int_imem_inst: neorv32_imem + generic map ( + IMEM_BASE => imem_base_c, -- memory base address + IMEM_SIZE => MEM_INT_IMEM_SIZE, -- processor-internal instruction memory size in bytes + IMEM_AS_IROM => not INT_BOOTLOADER_EN -- implement IMEM as pre-initialized read-only memory? + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_IMEM).rdata, -- data out + ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge + err_o => resp_bus(RESP_IMEM).err -- transfer error + ); + end generate; + + neorv32_int_imem_inst_false: + if (MEM_INT_IMEM_EN = false) or (MEM_INT_IMEM_SIZE = 0) generate + resp_bus(RESP_IMEM) <= resp_bus_entry_terminate_c; + end generate; + + + -- Processor-Internal Data Memory (DMEM) -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_int_dmem_inst_true: + if (MEM_INT_DMEM_EN = true) and (MEM_INT_DMEM_SIZE > 0) generate + neorv32_int_dmem_inst: neorv32_dmem + generic map ( + DMEM_BASE => dmem_base_c, -- memory base address + DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_DMEM).rdata, -- data out + ack_o => resp_bus(RESP_DMEM).ack -- transfer acknowledge + ); + resp_bus(RESP_DMEM).err <= '0'; -- no access error possible + end generate; + + neorv32_int_dmem_inst_false: + if (MEM_INT_DMEM_EN = false) or (MEM_INT_DMEM_SIZE = 0) generate + resp_bus(RESP_DMEM) <= resp_bus_entry_terminate_c; + end generate; + + + -- Processor-Internal Bootloader ROM (BOOTROM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_boot_rom_inst_true: + if (INT_BOOTLOADER_EN = true) generate + neorv32_boot_rom_inst: neorv32_boot_rom + generic map ( + BOOTROM_BASE => boot_rom_base_c -- boot ROM base address + ) + port map ( + clk_i => clk_i, -- global clock line + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + addr_i => p_bus.addr, -- address + data_o => resp_bus(RESP_BOOTROM).rdata, -- data out + ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge + err_o => resp_bus(RESP_BOOTROM).err -- transfer error + ); + end generate; + + neorv32_boot_rom_inst_false: + if (INT_BOOTLOADER_EN = false) generate + resp_bus(RESP_BOOTROM) <= resp_bus_entry_terminate_c; + end generate; + + + -- External Wishbone Gateway (WISHBONE) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_wishbone_inst_true: + if (MEM_EXT_EN = true) generate + neorv32_wishbone_inst: neorv32_wishbone + generic map ( + -- Internal instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Interface Configuration -- + BUS_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception + PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode + BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian + ASYNC_RX => MEM_EXT_ASYNC_RX, -- use register buffer for RX data when false + ASYNC_TX => MEM_EXT_ASYNC_TX -- use register buffer for TX data when false + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + -- host access -- + src_i => p_bus.src, -- access type (0: data, 1:instruction) + addr_i => p_bus.addr, -- address + rden_i => p_bus.re, -- read enable + wren_i => p_bus.we, -- write enable + ben_i => p_bus.ben, -- byte write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_WISHBONE).rdata, -- data out + ack_o => resp_bus(RESP_WISHBONE).ack, -- transfer acknowledge + err_o => resp_bus(RESP_WISHBONE).err, -- transfer error + tmo_o => ext_timeout, -- transfer timeout + priv_i => p_bus.priv, -- current CPU privilege level + ext_o => ext_access, -- active external access + -- xip configuration -- + xip_en_i => xip_enable, -- XIP module enabled + xip_page_i => xip_page, -- XIP memory page + -- wishbone interface -- + wb_tag_o => wb_tag_o, -- request tag + wb_adr_o => wb_adr_o, -- address + wb_dat_i => wb_dat_i, -- read data + wb_dat_o => wb_dat_o, -- write data + wb_we_o => wb_we_o, -- read/write + wb_sel_o => wb_sel_o, -- byte enable + wb_stb_o => wb_stb_o, -- strobe + wb_cyc_o => wb_cyc_o, -- valid cycle + wb_ack_i => wb_ack_i, -- transfer acknowledge + wb_err_i => wb_err_i -- transfer error + ); + end generate; + + neorv32_wishbone_inst_false: + if (MEM_EXT_EN = false) generate + resp_bus(RESP_WISHBONE) <= resp_bus_entry_terminate_c; + ext_timeout <= '0'; + ext_access <= '0'; + -- + wb_adr_o <= (others => '0'); + wb_dat_o <= (others => '0'); + wb_we_o <= '0'; + wb_sel_o <= (others => '0'); + wb_stb_o <= '0'; + wb_cyc_o <= '0'; + wb_tag_o <= (others => '0'); + end generate; + + + -- Execute In Place Module (XIP) ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_xip_inst_true: + if (IO_XIP_EN = true) generate + neorv32_xip_inst: neorv32_xip + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + -- host access: control register access port -- + ct_addr_i => p_bus.addr, -- address + ct_rden_i => io_rden, -- read enable + ct_wren_i => io_wren, -- write enable + ct_data_i => p_bus.wdata, -- data in + ct_data_o => resp_bus(RESP_XIP_CT).rdata, -- data out + ct_ack_o => resp_bus(RESP_XIP_CT).ack, -- transfer acknowledge + -- host access: transparent SPI access port (read-only) -- + acc_addr_i => p_bus.addr, -- address + acc_rden_i => p_bus.re, -- read enable + acc_wren_i => p_bus.we, -- write enable + acc_data_o => resp_bus(RESP_XIP_ACC).rdata, -- data out + acc_ack_o => resp_bus(RESP_XIP_ACC).ack, -- transfer acknowledge + acc_err_o => resp_bus(RESP_XIP_ACC).err, -- transfer error + -- status -- + xip_en_o => xip_enable, -- XIP enable + xip_acc_o => xip_access, -- pending XIP access + xip_page_o => xip_page, -- XIP page + -- clock generator -- + clkgen_en_o => xip_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- SPI device interface -- + spi_csn_o => xip_csn_o, -- chip-select, low-active + spi_clk_o => xip_clk_o, -- serial clock + spi_data_i => xip_sdi_i, -- device data output + spi_data_o => xip_sdo_o -- controller data output + ); + resp_bus(RESP_XIP_CT).err <= '0'; -- no access error possible + end generate; + + neorv32_xip_inst_false: + if (IO_XIP_EN = false) generate + resp_bus(RESP_XIP_CT) <= resp_bus_entry_terminate_c; + resp_bus(RESP_XIP_ACC) <= resp_bus_entry_terminate_c; + -- + xip_enable <= '0'; + xip_access <= '0'; + xip_page <= (others => '0'); + xip_cg_en <= '0'; + xip_csn_o <= '1'; + xip_clk_o <= '0'; + xip_sdo_o <= '0'; + end generate; + + +-- **************************************************************************************************************************** +-- IO/Peripheral Modules +-- **************************************************************************************************************************** + + + -- IO Access? ----------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + io_acc <= '1' when (p_bus.addr(31 downto index_size_f(io_size_c)) = io_base_c(31 downto index_size_f(io_size_c))) else '0'; + io_rden <= '1' when (io_acc = '1') and (p_bus.re = '1') and (p_bus.src = '0') else '0'; -- PMA: read access only from data interface + io_wren <= '1' when (io_acc = '1') and (p_bus.we = '1') and (p_bus.ben = "1111") else '0'; -- PMA: full-word write accesses only (reduces HW complexity) + + + -- Custom Functions Subsystem (CFS) ------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_cfs_inst_true: + if (IO_CFS_EN = true) generate + neorv32_cfs_inst: neorv32_cfs + generic map ( + CFS_CONFIG => IO_CFS_CONFIG, -- custom CFS configuration generic + CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits + CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, use as async + priv_i => p_bus.priv, -- current CPU privilege mode + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- word write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_CFS).rdata, -- data out + ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge + err_o => resp_bus(RESP_CFS).err, -- access error + -- clock generator -- + clkgen_en_o => cfs_cg_en, -- enable clock generator + clkgen_i => clk_gen, -- "clock" inputs + -- interrupt -- + irq_o => cfs_irq, -- interrupt request + -- custom io (conduit) -- + cfs_in_i => cfs_in_i, -- custom inputs + cfs_out_o => cfs_out_o -- custom outputs + ); + end generate; + + neorv32_cfs_inst_false: + if (IO_CFS_EN = false) generate + resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c; + -- + cfs_cg_en <= '0'; + cfs_irq <= '0'; + cfs_out_o <= (others => '0'); + end generate; + + + -- General Purpose Input/Output Port (GPIO) ----------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_gpio_inst_true: + if (IO_GPIO_EN = true) generate + neorv32_gpio_inst: neorv32_gpio + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_GPIO).rdata, -- data out + ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge + err_o => resp_bus(RESP_GPIO).err, -- transfer error + -- parallel io -- + gpio_o => gpio_o, + gpio_i => gpio_i + ); + end generate; + + neorv32_gpio_inst_false: + if (IO_GPIO_EN = false) generate + resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c; + -- + gpio_o <= (others => '0'); + end generate; + + + -- Watch Dog Timer (WDT) ------------------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_wdt_inst_true: + if (IO_WDT_EN = true) generate + neorv32_wdt_inst: neorv32_wdt + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_ext_i => rstn_ext, -- external reset line, low-active, async + rstn_int_i => rstn_int, -- internal reset line, low-active, async + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + addr_i => p_bus.addr, -- address + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_WDT).rdata, -- data out + ack_o => resp_bus(RESP_WDT).ack, -- transfer acknowledge + -- CPU status -- + cpu_debug_i => cpu_s.debug, -- CPU is in debug mode + cpu_sleep_i => cpu_s.sleep, -- CPU is in sleep mode + -- clock generator -- + clkgen_en_o => wdt_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- timeout event -- + irq_o => wdt_irq, -- timeout IRQ + rstn_o => rstn_wdt -- timeout reset, low_active, sync + ); + resp_bus(RESP_WDT).err <= '0'; -- no access error possible + end generate; + + neorv32_wdt_inst_false: + if (IO_WDT_EN = false) generate + resp_bus(RESP_WDT) <= resp_bus_entry_terminate_c; + -- + wdt_irq <= '0'; + rstn_wdt <= '1'; + wdt_cg_en <= '0'; + end generate; + + + -- Machine System Timer (MTIME) ----------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_mtime_inst_true: + if (IO_MTIME_EN = true) generate + neorv32_mtime_inst: neorv32_mtime + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_MTIME).rdata, -- data out + ack_o => resp_bus(RESP_MTIME).ack, -- transfer acknowledge + -- interrupt -- + irq_o => mtime_irq -- interrupt request + ); + resp_bus(RESP_MTIME).err <= '0'; -- no access error possible + end generate; + + neorv32_mtime_inst_false: + if (IO_MTIME_EN = false) generate + resp_bus(RESP_MTIME) <= resp_bus_entry_terminate_c; + -- + mtime_irq <= mtime_irq_i; -- use external machine timer interrupt + end generate; + + + -- Primary Universal Asynchronous Receiver/Transmitter (UART0) ---------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_uart0_inst_true: + if (IO_UART0_EN = true) generate + neorv32_uart0_inst: neorv32_uart + generic map ( + UART_PRIMARY => true, -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO => IO_UART0_TX_FIFO -- TX fifo depth, has to be a power of two, min 1 + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_UART0).rdata, -- data out + ack_o => resp_bus(RESP_UART0).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => uart0_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + uart_txd_o => uart0_txd_o, + uart_rxd_i => uart0_rxd_i, + -- hardware flow control -- + uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt + irq_txd_o => uart0_txd_irq -- uart transmission done interrupt + ); + resp_bus(RESP_UART0).err <= '0'; -- no access error possible + end generate; + + neorv32_uart0_inst_false: + if (IO_UART0_EN = false) generate + resp_bus(RESP_UART0) <= resp_bus_entry_terminate_c; + -- + uart0_txd_o <= '0'; + uart0_rts_o <= '0'; + uart0_cg_en <= '0'; + uart0_rxd_irq <= '0'; + uart0_txd_irq <= '0'; + end generate; + + + -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) -------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_uart1_inst_true: + if (IO_UART1_EN = true) generate + neorv32_uart1_inst: neorv32_uart + generic map ( + UART_PRIMARY => false, -- true = primary UART (UART0), false = secondary UART (UART1) + UART_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 + UART_TX_FIFO => IO_UART1_TX_FIFO -- TX fifo depth, has to be a power of two, min 1 + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_UART1).rdata, -- data out + ack_o => resp_bus(RESP_UART1).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => uart1_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + uart_txd_o => uart1_txd_o, + uart_rxd_i => uart1_rxd_i, + -- hardware flow control -- + uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional + uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional + -- interrupts -- + irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt + irq_txd_o => uart1_txd_irq -- uart transmission done interrupt + ); + resp_bus(RESP_UART1).err <= '0'; -- no access error possible + end generate; + + neorv32_uart1_inst_false: + if (IO_UART1_EN = false) generate + resp_bus(RESP_UART1) <= resp_bus_entry_terminate_c; + -- + uart1_txd_o <= '0'; + uart1_rts_o <= '0'; + uart1_cg_en <= '0'; + uart1_rxd_irq <= '0'; + uart1_txd_irq <= '0'; + end generate; + + + -- Serial Peripheral Interface (SPI) ------------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_spi_inst_true: + if (IO_SPI_EN = true) generate + neorv32_spi_inst: neorv32_spi + generic map ( + IO_SPI_FIFO => IO_SPI_FIFO -- SPI RTX fifo depth, has to be zero or a power of two + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_SPI).rdata, -- data out + ack_o => resp_bus(RESP_SPI).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => spi_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines -- + spi_sck_o => spi_sck_o, -- SPI serial clock + spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in + spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out + spi_csn_o => spi_csn_o, -- SPI CS + -- interrupt -- + irq_o => spi_irq -- transmission done interrupt + ); + resp_bus(RESP_SPI).err <= '0'; -- no access error possible + end generate; + + neorv32_spi_inst_false: + if (IO_SPI_EN = false) generate + resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c; + -- + spi_sck_o <= '0'; + spi_sdo_o <= '0'; + spi_csn_o <= (others => '1'); -- CS lines are low-active + spi_cg_en <= '0'; + spi_irq <= '0'; + end generate; + + + -- Two-Wire Interface (TWI) --------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_twi_inst_true: + if (IO_TWI_EN = true) generate + neorv32_twi_inst: neorv32_twi + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_TWI).rdata, -- data out + ack_o => resp_bus(RESP_TWI).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => twi_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines (require external tri-state drivers) -- + twi_sda_i => twi_sda_i, -- serial data line input + twi_sda_o => twi_sda_o, -- serial data line output + twi_scl_i => twi_scl_i, -- serial clock line input + twi_scl_o => twi_scl_o, -- serial clock line output + -- interrupt -- + irq_o => twi_irq -- transfer done IRQ + ); + resp_bus(RESP_TWI).err <= '0'; -- no access error possible + + -- tri-state drivers -- + twi_sda_io <= '0' when (twi_sda_o = '0') else 'Z'; -- module can only pull the line low actively + twi_scl_io <= '0' when (twi_scl_o = '0') else 'Z'; + twi_sda_i <= to_stdulogic(to_bit(twi_sda_io)); -- "to_bit" to avoid hardware-vs-simulation mismatch + twi_scl_i <= to_stdulogic(to_bit(twi_scl_io)); + end generate; + + neorv32_twi_inst_false: + if (IO_TWI_EN = false) generate + resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c; + -- + twi_sda_io <= 'Z'; + twi_scl_io <= 'Z'; + twi_cg_en <= '0'; + twi_irq <= '0'; + end generate; + + + -- Pulse-Width Modulation Controller (PWM) ------------------------------------------------ + -- ------------------------------------------------------------------------------------------- + neorv32_pwm_inst_true: + if (IO_PWM_NUM_CH > 0) generate + neorv32_pwm_inst: neorv32_pwm + generic map ( + NUM_CHANNELS => IO_PWM_NUM_CH -- number of PWM channels (0..60) + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_PWM).rdata, -- data out + ack_o => resp_bus(RESP_PWM).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => pwm_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- pwm output channels -- + pwm_o => pwm_o + ); + resp_bus(RESP_PWM).err <= '0'; -- no access error possible + end generate; + + neorv32_pwm_inst_false: + if (IO_PWM_NUM_CH = 0) generate + resp_bus(RESP_PWM) <= resp_bus_entry_terminate_c; + -- + pwm_cg_en <= '0'; + pwm_o <= (others => '0'); + end generate; + + + -- True Random Number Generator (TRNG) ---------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_trng_inst_true: + if (IO_TRNG_EN = true) generate + neorv32_trng_inst: neorv32_trng + generic map ( + IO_TRNG_FIFO => IO_TRNG_FIFO -- RND fifo depth, has to be a power of two, min 1 + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_TRNG).rdata, -- data out + ack_o => resp_bus(RESP_TRNG).ack -- transfer acknowledge + ); + resp_bus(RESP_TRNG).err <= '0'; -- no access error possible + end generate; + + neorv32_trng_inst_false: + if (IO_TRNG_EN = false) generate + resp_bus(RESP_TRNG) <= resp_bus_entry_terminate_c; + end generate; + + + -- Smart LED (WS2811/WS2812) Interface (NEOLED) ------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_neoled_inst_true: + if (IO_NEOLED_EN = true) generate + neorv32_neoled_inst: neorv32_neoled + generic map ( + FIFO_DEPTH => IO_NEOLED_TX_FIFO -- TX FIFO depth (1..32k, power of two) + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_NEOLED).rdata, -- data out + ack_o => resp_bus(RESP_NEOLED).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => neoled_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- interrupt -- + irq_o => neoled_irq, -- interrupt request + -- NEOLED output -- + neoled_o => neoled_o -- serial async data line + ); + resp_bus(RESP_NEOLED).err <= '0'; -- no access error possible + end generate; + + neorv32_neoled_inst_false: + if (IO_NEOLED_EN = false) generate + resp_bus(RESP_NEOLED) <= resp_bus_entry_terminate_c; + -- + neoled_cg_en <= '0'; + neoled_irq <= '0'; + neoled_o <= '0'; + end generate; + + + -- Stream Link Interface (SLINK) ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_slink_inst_true: + if (io_slink_en_c = true) generate + neorv32_slink_inst: neorv32_slink + generic map ( + SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8) + SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8) + SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two + SLINK_RX_FIFO => SLINK_RX_FIFO -- RX fifo depth, has to be a power of two + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_SLINK).rdata, -- data out + ack_o => resp_bus(RESP_SLINK).ack, -- transfer acknowledge + -- interrupt -- + irq_tx_o => slink_tx_irq, + irq_rx_o => slink_rx_irq, + -- TX stream interfaces -- + slink_tx_dat_o => slink_tx_dat_o, -- output data + slink_tx_val_o => slink_tx_val_o, -- valid output + slink_tx_rdy_i => slink_tx_rdy_i, -- ready to send + slink_tx_lst_o => slink_tx_lst_o, -- last data of packet + -- RX stream interfaces -- + slink_rx_dat_i => slink_rx_dat_i, -- input data + slink_rx_val_i => slink_rx_val_i, -- valid input + slink_rx_rdy_o => slink_rx_rdy_o, -- ready to receive + slink_rx_lst_i => slink_rx_lst_i -- last data of packet + ); + resp_bus(RESP_SLINK).err <= '0'; -- no access error possible + end generate; + + neorv32_slink_inst_false: + if (io_slink_en_c = false) generate + resp_bus(RESP_SLINK) <= resp_bus_entry_terminate_c; + -- + slink_tx_irq <= '0'; + slink_rx_irq <= '0'; + slink_tx_dat_o <= (others => (others => '0')); + slink_tx_val_o <= (others => '0'); + slink_tx_lst_o <= (others => '0'); + slink_rx_rdy_o <= (others => '0'); + end generate; + + + -- External Interrupt Controller (XIRQ) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_xirq_inst_true: + if (XIRQ_NUM_CH > 0) generate + neorv32_slink_inst: neorv32_xirq + generic map ( + XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32) + XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE, -- trigger type: 0=level, 1=edge + XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_XIRQ).rdata, -- data out + ack_o => resp_bus(RESP_XIRQ).ack, -- transfer acknowledge + -- external interrupt lines -- + xirq_i => xirq_i, + -- CPU interrupt -- + cpu_irq_o => xirq_irq + ); + resp_bus(RESP_XIRQ).err <= '0'; -- no access error possible + end generate; + + neorv32_xirq_inst_false: + if (XIRQ_NUM_CH = 0) generate + resp_bus(RESP_XIRQ) <= resp_bus_entry_terminate_c; + -- + xirq_irq <= '0'; + end generate; + + + -- General Purpose Timer (GPTMR) ---------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_gptmr_inst_true: + if (IO_GPTMR_EN = true) generate + neorv32_gptmr_inst: neorv32_gptmr + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_GPTMR).rdata, -- data out + ack_o => resp_bus(RESP_GPTMR).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => gptmr_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- interrupt -- + irq_o => gptmr_irq -- timer match interrupt + ); + resp_bus(RESP_GPTMR).err <= '0'; -- no access error possible + end generate; + + neorv32_gptmr_inst_false: + if (IO_GPTMR_EN = false) generate + resp_bus(RESP_GPTMR) <= resp_bus_entry_terminate_c; + -- + gptmr_cg_en <= '0'; + gptmr_irq <= '0'; + end generate; + + + -- 1-Wire Interface Controller (ONEWIRE) -------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_onewire_inst_true: + if (IO_ONEWIRE_EN = true) generate + neorv32_onewire_inst: neorv32_onewire + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_int, -- global reset line, low-active, async + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_i => p_bus.wdata, -- data in + data_o => resp_bus(RESP_ONEWIRE).rdata, -- data out + ack_o => resp_bus(RESP_ONEWIRE).ack, -- transfer acknowledge + -- clock generator -- + clkgen_en_o => onewire_cg_en, -- enable clock generator + clkgen_i => clk_gen, + -- com lines (require external tri-state drivers) -- + onewire_i => onewire_i, -- 1-wire line state + onewire_o => onewire_o, -- 1-wire line pull-down + -- interrupt -- + irq_o => onewire_irq -- transfer done IRQ + ); + resp_bus(RESP_ONEWIRE).err <= '0'; -- no access error possible + + -- tri-state driver -- + onewire_io <= '0' when (onewire_o = '0') else 'Z'; -- module can only pull the line low actively + onewire_i <= to_stdulogic(to_bit(onewire_io)); -- "to_bit" to avoid hardware-vs-simulation mismatch + end generate; + + neorv32_onewire_inst_false: + if (IO_ONEWIRE_EN = false) generate + resp_bus(RESP_ONEWIRE) <= resp_bus_entry_terminate_c; + -- + onewire_io <= 'Z'; + onewire_cg_en <= '0'; + onewire_irq <= '0'; + end generate; + + + -- System Configuration Information Memory (SYSINFO) -------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_sysinfo_inst: neorv32_sysinfo + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + CUSTOM_ID => CUSTOM_ID, -- custom user-defined ID + INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- implement processor-internal bootloader? + -- Physical memory protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16) + -- internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity (min 1), has to be a power 2 + -- External memory interface -- + MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? + MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian + -- On-Chip Debugger -- + ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD? + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? + IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? + IO_SLINK_EN => io_slink_en_c, -- implement stream link interface? + IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? + IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement + IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? + IO_XIP_EN => IO_XIP_EN, -- implement execute in place module (XIP)? + IO_ONEWIRE_EN => IO_ONEWIRE_EN -- implement 1-wire interface (ONEWIRE)? + ) + port map ( + -- host access -- + clk_i => clk_i, -- global clock line + addr_i => p_bus.addr, -- address + rden_i => io_rden, -- read enable + wren_i => io_wren, -- write enable + data_o => resp_bus(RESP_SYSINFO).rdata, -- data out + ack_o => resp_bus(RESP_SYSINFO).ack, -- transfer acknowledge + err_o => resp_bus(RESP_SYSINFO).err -- transfer error + ); + + +-- **************************************************************************************************************************** +-- On-Chip Debugger Complex +-- **************************************************************************************************************************** + + neorv32_neorv32_ocd_inst_true: + if (ON_CHIP_DEBUGGER_EN = true) generate + + -- On-Chip Debugger - Debug Module (DM) --------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_debug_dm_inst: neorv32_debug_dm + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_ext, -- external reset, low-active + -- debug module interface (DMI) -- + dmi_req_valid_i => dmi.req_valid, + dmi_req_ready_o => dmi.req_ready, + dmi_req_address_i => dmi.req_address, + dmi_req_data_i => dmi.req_data, + dmi_req_op_i => dmi.req_op, + dmi_rsp_valid_o => dmi.rsp_valid, + dmi_rsp_ready_i => dmi.rsp_ready, + dmi_rsp_data_o => dmi.rsp_data, + dmi_rsp_op_o => dmi.rsp_op, + -- CPU bus access -- + cpu_debug_i => cpu_s.debug, -- CPU is in debug mode + cpu_addr_i => p_bus.addr, -- address + cpu_rden_i => p_bus.re, -- read enable + cpu_wren_i => p_bus.we, -- write enable + cpu_ben_i => p_bus.ben, -- byte write enable + cpu_data_i => p_bus.wdata, -- data in + cpu_data_o => resp_bus(RESP_OCD).rdata, -- data out + cpu_ack_o => resp_bus(RESP_OCD).ack, -- transfer acknowledge + -- CPU control -- + cpu_ndmrstn_o => dci_ndmrstn, -- soc reset + cpu_halt_req_o => dci_halt_req -- request hart to halt (enter debug mode) + ); + resp_bus(RESP_OCD).err <= '0'; -- no access error possible + + + -- On-Chip Debugger - Debug Transport Module (DTM) ---------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_debug_dtm_inst: neorv32_debug_dtm + generic map ( + IDCODE_VERSION => jtag_tap_idcode_version_c, -- version + IDCODE_PARTID => jtag_tap_idcode_partid_c, -- part number + IDCODE_MANID => jtag_tap_idcode_manid_c -- manufacturer id + ) + port map ( + -- global control -- + clk_i => clk_i, -- global clock line + rstn_i => rstn_ext, -- external reset, low-active + -- jtag connection -- + jtag_trst_i => jtag_trst_i, + jtag_tck_i => jtag_tck_i, + jtag_tdi_i => jtag_tdi_i, + jtag_tdo_o => jtag_tdo_o, + jtag_tms_i => jtag_tms_i, + -- debug module interface (DMI) -- + dmi_req_valid_o => dmi.req_valid, + dmi_req_ready_i => dmi.req_ready, + dmi_req_address_o => dmi.req_address, + dmi_req_data_o => dmi.req_data, + dmi_req_op_o => dmi.req_op, + dmi_rsp_valid_i => dmi.rsp_valid, + dmi_rsp_ready_o => dmi.rsp_ready, + dmi_rsp_data_i => dmi.rsp_data, + dmi_rsp_op_i => dmi.rsp_op + ); + + end generate; + + neorv32_debug_ocd_inst_false: + if (ON_CHIP_DEBUGGER_EN = false) generate + jtag_tdo_o <= jtag_tdi_i; -- JTAG feed-through + resp_bus(RESP_OCD) <= resp_bus_entry_terminate_c; + dci_ndmrstn <= '1'; + dci_halt_req <= '0'; + end generate; + + +end neorv32_top_rtl; diff --git a/proj_quartus/.qsys_edit/preferences.xml b/proj_quartus/.qsys_edit/preferences.xml index 40ee597c2..932626f62 100644 --- a/proj_quartus/.qsys_edit/preferences.xml +++ b/proj_quartus/.qsys_edit/preferences.xml @@ -3,11 +3,10 @@ - + - + diff --git a/proj_quartus/db/altsyncram_2aq1.tdf b/proj_quartus/db/altsyncram_2aq1.tdf new file mode 100644 index 000000000..41f67cc23 --- /dev/null +++ b/proj_quartus/db/altsyncram_2aq1.tdf @@ -0,0 +1,532 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 NUMWORDS_B=16384 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=14 WIDTHAD_B=14 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_5la (data[0..0], enable) +RETURNS ( eq[1..0]); +FUNCTION mux_lfb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 4 M10K 16 reg 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_2aq1 +( + address_a[13..0] : input; + address_b[13..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[0..0] : dffe; + decode2 : decode_5la; + mux3 : mux_lfb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 16384, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[13..0] : WIRE; + address_b_sel[0..0] : WIRE; + address_b_wire[13..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[0..0] = address_a_wire[13..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[15..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[15..0].portawe = ( decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[15..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[15..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[0..0] = address_b[13..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/altsyncram_6gq1.tdf b/proj_quartus/db/altsyncram_6gq1.tdf new file mode 100644 index 000000000..eeeb2a999 --- /dev/null +++ b/proj_quartus/db/altsyncram_6gq1.tdf @@ -0,0 +1,59460 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=2097152 NUMWORDS_B=2097152 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=21 WIDTHAD_B=21 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_noa (data[7..0], enable) +RETURNS ( eq[255..0]); +FUNCTION mux_7jb (data[2047..0], sel[7..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 972 M10K 2048 reg 8 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_6gq1 +( + address_a[20..0] : input; + address_b[20..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[7..0] : dffe; + decode2 : decode_noa; + mux3 : mux_7jb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a64 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a65 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a66 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a67 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a68 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a69 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a70 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a71 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a72 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a73 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a74 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a75 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a76 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a77 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a78 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a79 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a80 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a81 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a82 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a83 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a84 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a85 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a86 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a87 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a88 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a89 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a90 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a91 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a92 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a93 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a94 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a95 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a96 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a97 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a98 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a99 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a100 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a101 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a102 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a103 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a104 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a105 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a106 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a107 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a108 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a109 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a110 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a111 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a112 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a113 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a114 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a115 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a116 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a117 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a118 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a119 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a120 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a121 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a122 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a123 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a124 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a125 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a126 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a127 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a128 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a129 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a130 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a131 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a132 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a133 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a134 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a135 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a136 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a137 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a138 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a139 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a140 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a141 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a142 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a143 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a144 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a145 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a146 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a147 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a148 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a149 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a150 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a151 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a152 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a153 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a154 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a155 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a156 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a157 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a158 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a159 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a160 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a161 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a162 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a163 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a164 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a165 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a166 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a167 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a168 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a169 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a170 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a171 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a172 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a173 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a174 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a175 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a176 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a177 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a178 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a179 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a180 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a181 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a182 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a183 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a184 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a185 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a186 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a187 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a188 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a189 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a190 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a191 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a192 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a193 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a194 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a195 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a196 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a197 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a198 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a199 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a200 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a201 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a202 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a203 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a204 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a205 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a206 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a207 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a208 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a209 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a210 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a211 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a212 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a213 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a214 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a215 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a216 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a217 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a218 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a219 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a220 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a221 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a222 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a223 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a224 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a225 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a226 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a227 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a228 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a229 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a230 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a231 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a232 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a233 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a234 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a235 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a236 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a237 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a238 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a239 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a240 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a241 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a242 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a243 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a244 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a245 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a246 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a247 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a248 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a249 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a250 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a251 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a252 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a253 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a254 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a255 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a256 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a257 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a258 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a259 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a260 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a261 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a262 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a263 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a264 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a265 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a266 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a267 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a268 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a269 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a270 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a271 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a272 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a273 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a274 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a275 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a276 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a277 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a278 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a279 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a280 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a281 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a282 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a283 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a284 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a285 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a286 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a287 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a288 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a289 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a290 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a291 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a292 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a293 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a294 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a295 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a296 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a297 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a298 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a299 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a300 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a301 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a302 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a303 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a304 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a305 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a306 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a307 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a308 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a309 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a310 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a311 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a312 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a313 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a314 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a315 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a316 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a317 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a318 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a319 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a320 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a321 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a322 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a323 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a324 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a325 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a326 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a327 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a328 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a329 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a330 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a331 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a332 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a333 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a334 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a335 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a336 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a337 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a338 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a339 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a340 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a341 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a342 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a343 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a344 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a345 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a346 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a347 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a348 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a349 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a350 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a351 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a352 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a353 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a354 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a355 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a356 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a357 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a358 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a359 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a360 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a361 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a362 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a363 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a364 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a365 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a366 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a367 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a368 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a369 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a370 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a371 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a372 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a373 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a374 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a375 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a376 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a377 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a378 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a379 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a380 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a381 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a382 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a383 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a384 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a385 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a386 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a387 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a388 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a389 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a390 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a391 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a392 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a393 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a394 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a395 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a396 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a397 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a398 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a399 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a400 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a401 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a402 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a403 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a404 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a405 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a406 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a407 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a408 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a409 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a410 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a411 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a412 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a413 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a414 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a415 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a416 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a417 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a418 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a419 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a420 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a421 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a422 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a423 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a424 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a425 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a426 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a427 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a428 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a429 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a430 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a431 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a432 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a433 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a434 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a435 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a436 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a437 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a438 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a439 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a440 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a441 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a442 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a443 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a444 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a445 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a446 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a447 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a448 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a449 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a450 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a451 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a452 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a453 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a454 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a455 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a456 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a457 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a458 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a459 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a460 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a461 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a462 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a463 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a464 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a465 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a466 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a467 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a468 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a469 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a470 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a471 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a472 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a473 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a474 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a475 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a476 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a477 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a478 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a479 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a480 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a481 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a482 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a483 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a484 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a485 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a486 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a487 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a488 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a489 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a490 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a491 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a492 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a493 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a494 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a495 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a496 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a497 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a498 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a499 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a500 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a501 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a502 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a503 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a504 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a505 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a506 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a507 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a508 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a509 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a510 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a511 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a512 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a513 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a514 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a515 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a516 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a517 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a518 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a519 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 524288, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 532479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 524288, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 532479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a520 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a521 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a522 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a523 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a524 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a525 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a526 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a527 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 532480, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 540671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 532480, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 540671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a528 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a529 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a530 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a531 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a532 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a533 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a534 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a535 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 540672, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 548863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 540672, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 548863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a536 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a537 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a538 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a539 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a540 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a541 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a542 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a543 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 548864, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 557055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 548864, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 557055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a544 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a545 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a546 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a547 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a548 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a549 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a550 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a551 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 557056, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 565247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 557056, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 565247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a552 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a553 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a554 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a555 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a556 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a557 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a558 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a559 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 565248, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 573439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 565248, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 573439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a560 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a561 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a562 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a563 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a564 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a565 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a566 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a567 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 573440, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 581631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 573440, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 581631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a568 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a569 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a570 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a571 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a572 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a573 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a574 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a575 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 581632, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 589823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 581632, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 589823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a576 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a577 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a578 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a579 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a580 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a581 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a582 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a583 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 589824, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 598015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 589824, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 598015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a584 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a585 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a586 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a587 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a588 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a589 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a590 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a591 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 598016, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 606207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 598016, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 606207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a592 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a593 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a594 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a595 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a596 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a597 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a598 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a599 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 606208, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 614399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 606208, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 614399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a600 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a601 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a602 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a603 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a604 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a605 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a606 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a607 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 614400, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 622591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 614400, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 622591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a608 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a609 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a610 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a611 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a612 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a613 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a614 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a615 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 622592, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 630783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 622592, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 630783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a616 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a617 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a618 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a619 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a620 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a621 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a622 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a623 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 630784, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 638975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 630784, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 638975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a624 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a625 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a626 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a627 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a628 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a629 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a630 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a631 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 638976, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 647167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 638976, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 647167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a632 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a633 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a634 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a635 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a636 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a637 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a638 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a639 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 647168, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 655359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 647168, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 655359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a640 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a641 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a642 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a643 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a644 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a645 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a646 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a647 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 655360, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 663551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 655360, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 663551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a648 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a649 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a650 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a651 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a652 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a653 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a654 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a655 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 663552, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 671743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 663552, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 671743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a656 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a657 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a658 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a659 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a660 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a661 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a662 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a663 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 671744, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 679935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 671744, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 679935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a664 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a665 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a666 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a667 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a668 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a669 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a670 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a671 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 679936, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 688127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 679936, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 688127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a672 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a673 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a674 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a675 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a676 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a677 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a678 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a679 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 688128, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 696319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 688128, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 696319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a680 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a681 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a682 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a683 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a684 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a685 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a686 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a687 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 696320, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 704511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 696320, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 704511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a688 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a689 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a690 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a691 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a692 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a693 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a694 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a695 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 704512, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 712703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 704512, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 712703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a696 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a697 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a698 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a699 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a700 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a701 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a702 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a703 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 712704, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 720895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 712704, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 720895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a704 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a705 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a706 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a707 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a708 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a709 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a710 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a711 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 720896, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 729087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 720896, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 729087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a712 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a713 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a714 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a715 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a716 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a717 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a718 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a719 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 729088, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 737279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 729088, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 737279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a720 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a721 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a722 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a723 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a724 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a725 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a726 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a727 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 737280, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 745471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 737280, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 745471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a728 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a729 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a730 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a731 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a732 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a733 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a734 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a735 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 745472, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 753663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 745472, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 753663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a736 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a737 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a738 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a739 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a740 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a741 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a742 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a743 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 753664, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 761855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 753664, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 761855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a744 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a745 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a746 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a747 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a748 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a749 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a750 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a751 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 761856, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 770047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 761856, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 770047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a752 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a753 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a754 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a755 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a756 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a757 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a758 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a759 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 770048, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 778239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 770048, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 778239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a760 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a761 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a762 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a763 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a764 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a765 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a766 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a767 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 778240, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 786431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 778240, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 786431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a768 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a769 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a770 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a771 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a772 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a773 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a774 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a775 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 786432, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 794623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 786432, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 794623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a776 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a777 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a778 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a779 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a780 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a781 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a782 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a783 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 794624, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 802815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 794624, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 802815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a784 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a785 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a786 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a787 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a788 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a789 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a790 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a791 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 802816, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 811007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 802816, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 811007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a792 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a793 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a794 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a795 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a796 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a797 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a798 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a799 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 811008, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 819199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 811008, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 819199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a800 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a801 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a802 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a803 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a804 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a805 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a806 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a807 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 819200, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 827391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 819200, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 827391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a808 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a809 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a810 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a811 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a812 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a813 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a814 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a815 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 827392, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 835583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 827392, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 835583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a816 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a817 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a818 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a819 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a820 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a821 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a822 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a823 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 835584, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 843775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 835584, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 843775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a824 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a825 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a826 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a827 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a828 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a829 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a830 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a831 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 843776, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 851967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 843776, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 851967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a832 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a833 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a834 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a835 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a836 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a837 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a838 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a839 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 851968, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 860159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 851968, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 860159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a840 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a841 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a842 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a843 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a844 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a845 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a846 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a847 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 860160, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 868351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 860160, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 868351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a848 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a849 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a850 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a851 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a852 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a853 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a854 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a855 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 868352, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 876543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 868352, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 876543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a856 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a857 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a858 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a859 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a860 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a861 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a862 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a863 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 876544, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 884735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 876544, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 884735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a864 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a865 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a866 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a867 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a868 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a869 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a870 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a871 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 884736, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 892927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 884736, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 892927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a872 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a873 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a874 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a875 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a876 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a877 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a878 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a879 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 892928, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 901119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 892928, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 901119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a880 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a881 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a882 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a883 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a884 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a885 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a886 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a887 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 901120, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 909311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 901120, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 909311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a888 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a889 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a890 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a891 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a892 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a893 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a894 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a895 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 909312, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 917503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 909312, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 917503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a896 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a897 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a898 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a899 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a900 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a901 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a902 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a903 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 917504, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 925695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 917504, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 925695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a904 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a905 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a906 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a907 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a908 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a909 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a910 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a911 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 925696, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 933887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 925696, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 933887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a912 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a913 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a914 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a915 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a916 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a917 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a918 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a919 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 933888, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 942079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 933888, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 942079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a920 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a921 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a922 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a923 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a924 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a925 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a926 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a927 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 942080, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 950271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 942080, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 950271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a928 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a929 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a930 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a931 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a932 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a933 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a934 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a935 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 950272, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 958463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 950272, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 958463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a936 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a937 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a938 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a939 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a940 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a941 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a942 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a943 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 958464, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 966655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 958464, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 966655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a944 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a945 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a946 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a947 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a948 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a949 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a950 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a951 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 966656, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 974847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 966656, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 974847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a952 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a953 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a954 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a955 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a956 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a957 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a958 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a959 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 974848, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 983039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 974848, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 983039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a960 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a961 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a962 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a963 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a964 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a965 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a966 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a967 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 983040, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 991231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 983040, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 991231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a968 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a969 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a970 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a971 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a972 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a973 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a974 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a975 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 991232, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 999423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 991232, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 999423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a976 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a977 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a978 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a979 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a980 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a981 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a982 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a983 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 999424, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1007615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 999424, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1007615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a984 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a985 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a986 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a987 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a988 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a989 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a990 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a991 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1007616, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1015807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1007616, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1015807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a992 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a993 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a994 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a995 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a996 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a997 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a998 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a999 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1015808, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1023999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1015808, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1023999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1000 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1001 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1002 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1003 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1004 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1005 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1006 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1007 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1024000, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1032191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1024000, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1032191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1008 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1009 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1010 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1011 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1012 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1013 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1014 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1015 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1032192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1040383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1032192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1040383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1016 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1017 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1018 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1019 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1020 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1021 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1022 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1023 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1040384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1048575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1040384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1048575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1024 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1025 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1026 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1027 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1028 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1029 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1030 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1031 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1048576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1056767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1048576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1056767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1032 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1033 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1034 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1035 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1036 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1037 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1038 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1039 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1056768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1064959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1056768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1064959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1040 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1041 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1042 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1043 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1044 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1045 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1046 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1047 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1064960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1073151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1064960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1073151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1048 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1049 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1050 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1051 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1052 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1053 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1054 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1055 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1073152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1081343, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1073152, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1081343, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1056 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1057 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1058 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1059 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1060 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1061 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1062 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1063 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1081344, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1089535, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1081344, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1089535, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1064 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1065 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1066 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1067 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1068 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1069 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1070 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1071 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1089536, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1097727, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1089536, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1097727, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1072 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1073 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1074 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1075 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1076 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1077 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1078 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1079 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1097728, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1105919, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1097728, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1105919, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1080 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1081 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1082 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1083 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1084 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1085 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1086 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1087 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1105920, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1114111, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1105920, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1114111, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1088 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1089 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1090 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1091 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1092 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1093 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1094 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1095 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1114112, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1122303, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1114112, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1122303, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1096 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1097 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1098 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1099 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1100 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1101 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1102 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1103 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1122304, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1130495, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1122304, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1130495, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1104 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1105 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1106 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1107 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1108 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1109 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1110 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1111 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1130496, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1138687, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1130496, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1138687, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1112 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1113 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1114 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1115 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1116 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1117 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1118 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1119 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1138688, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1146879, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1138688, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1146879, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1120 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1121 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1122 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1123 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1124 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1125 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1126 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1127 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1146880, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1155071, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1146880, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1155071, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1128 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1129 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1130 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1131 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1132 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1133 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1134 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1135 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1155072, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1163263, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1155072, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1163263, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1136 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1137 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1138 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1139 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1140 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1141 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1142 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1143 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1163264, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1171455, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1163264, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1171455, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1144 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1145 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1146 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1147 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1148 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1149 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1150 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1151 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1171456, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1179647, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1171456, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1179647, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1152 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1153 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1154 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1155 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1156 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1157 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1158 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1159 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1179648, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1187839, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1179648, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1187839, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1160 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1161 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1162 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1163 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1164 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1165 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1166 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1167 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1187840, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1196031, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1187840, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1196031, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1168 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1169 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1170 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1171 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1172 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1173 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1174 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1175 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1196032, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1204223, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1196032, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1204223, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1176 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1177 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1178 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1179 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1180 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1181 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1182 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1183 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1204224, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1212415, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1204224, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1212415, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1184 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1185 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1186 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1187 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1188 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1189 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1190 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1191 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1212416, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1220607, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1212416, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1220607, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1192 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1193 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1194 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1195 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1196 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1197 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1198 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1199 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1220608, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1228799, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1220608, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1228799, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1200 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1201 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1202 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1203 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1204 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1205 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1206 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1207 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1228800, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1236991, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1228800, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1236991, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1208 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1209 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1210 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1211 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1212 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1213 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1214 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1215 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1236992, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1245183, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1236992, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1245183, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1216 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1217 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1218 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1219 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1220 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1221 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1222 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1223 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1245184, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1253375, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1245184, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1253375, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1224 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1225 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1226 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1227 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1228 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1229 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1230 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1231 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1253376, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1261567, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1253376, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1261567, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1232 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1233 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1234 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1235 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1236 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1237 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1238 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1239 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1261568, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1269759, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1261568, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1269759, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1240 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1241 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1242 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1243 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1244 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1245 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1246 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1247 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1269760, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1277951, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1269760, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1277951, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1248 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1249 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1250 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1251 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1252 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1253 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1254 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1255 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1277952, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1286143, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1277952, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1286143, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1256 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1257 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1258 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1259 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1260 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1261 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1262 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1263 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1286144, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1294335, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1286144, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1294335, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1264 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1265 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1266 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1267 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1268 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1269 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1270 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1271 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1294336, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1302527, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1294336, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1302527, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1272 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1273 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1274 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1275 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1276 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1277 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1278 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1279 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1302528, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1310719, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1302528, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1310719, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1280 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1281 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1282 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1283 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1284 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1285 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1286 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1287 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1310720, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1318911, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1310720, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1318911, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1288 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1289 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1290 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1291 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1292 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1293 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1294 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1295 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1318912, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1327103, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1318912, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1327103, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1296 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1297 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1298 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1299 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1300 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1301 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1302 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1303 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1327104, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1335295, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1327104, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1335295, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1304 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1305 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1306 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1307 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1308 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1309 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1310 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1311 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1335296, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1343487, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1335296, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1343487, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1312 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1313 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1314 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1315 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1316 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1317 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1318 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1319 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1343488, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1351679, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1343488, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1351679, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1320 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1321 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1322 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1323 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1324 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1325 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1326 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1327 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1351680, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1359871, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1351680, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1359871, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1328 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1329 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1330 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1331 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1332 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1333 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1334 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1335 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1359872, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1368063, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1359872, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1368063, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1336 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1337 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1338 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1339 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1340 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1341 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1342 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1343 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1368064, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1376255, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1368064, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1376255, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1344 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1345 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1346 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1347 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1348 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1349 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1350 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1351 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1376256, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1384447, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1376256, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1384447, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1352 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1353 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1354 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1355 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1356 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1357 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1358 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1359 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1384448, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1392639, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1384448, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1392639, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1360 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1361 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1362 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1363 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1364 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1365 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1366 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1367 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1392640, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1400831, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1392640, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1400831, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1368 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1369 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1370 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1371 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1372 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1373 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1374 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1375 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1400832, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1409023, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1400832, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1409023, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1376 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1377 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1378 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1379 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1380 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1381 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1382 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1383 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1409024, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1417215, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1409024, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1417215, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1384 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1385 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1386 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1387 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1388 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1389 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1390 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1391 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1417216, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1425407, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1417216, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1425407, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1392 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1393 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1394 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1395 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1396 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1397 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1398 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1399 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1425408, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1433599, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1425408, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1433599, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1400 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1401 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1402 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1403 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1404 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1405 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1406 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1407 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1433600, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1441791, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1433600, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1441791, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1408 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1409 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1410 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1411 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1412 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1413 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1414 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1415 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1441792, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1449983, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1441792, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1449983, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1416 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1417 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1418 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1419 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1420 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1421 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1422 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1423 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1449984, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1458175, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1449984, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1458175, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1424 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1425 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1426 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1427 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1428 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1429 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1430 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1431 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1458176, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1466367, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1458176, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1466367, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1432 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1433 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1434 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1435 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1436 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1437 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1438 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1439 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1466368, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1474559, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1466368, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1474559, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1440 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1441 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1442 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1443 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1444 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1445 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1446 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1447 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1474560, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1482751, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1474560, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1482751, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1448 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1449 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1450 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1451 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1452 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1453 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1454 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1455 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1482752, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1490943, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1482752, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1490943, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1456 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1457 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1458 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1459 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1460 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1461 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1462 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1463 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1490944, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1499135, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1490944, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1499135, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1464 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1465 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1466 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1467 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1468 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1469 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1470 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1471 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1499136, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1507327, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1499136, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1507327, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1472 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1473 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1474 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1475 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1476 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1477 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1478 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1479 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1507328, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1515519, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1507328, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1515519, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1480 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1481 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1482 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1483 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1484 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1485 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1486 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1487 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1515520, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1523711, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1515520, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1523711, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1488 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1489 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1490 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1491 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1492 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1493 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1494 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1495 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1523712, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1531903, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1523712, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1531903, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1496 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1497 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1498 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1499 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1500 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1501 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1502 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1503 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1531904, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1540095, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1531904, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1540095, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1504 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1505 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1506 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1507 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1508 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1509 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1510 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1511 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1540096, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1548287, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1540096, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1548287, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1512 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1513 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1514 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1515 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1516 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1517 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1518 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1519 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1548288, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1556479, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1548288, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1556479, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1520 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1521 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1522 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1523 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1524 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1525 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1526 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1527 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1556480, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1564671, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1556480, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1564671, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1528 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1529 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1530 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1531 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1532 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1533 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1534 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1535 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1564672, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1572863, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1564672, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1572863, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1536 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1537 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1538 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1539 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1540 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1541 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1542 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1543 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1572864, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1581055, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1572864, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1581055, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1544 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1545 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1546 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1547 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1548 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1549 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1550 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1551 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1581056, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1589247, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1581056, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1589247, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1552 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1553 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1554 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1555 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1556 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1557 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1558 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1559 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1589248, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1597439, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1589248, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1597439, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1560 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1561 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1562 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1563 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1564 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1565 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1566 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1567 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1597440, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1605631, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1597440, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1605631, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1568 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1569 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1570 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1571 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1572 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1573 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1574 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1575 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1605632, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1613823, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1605632, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1613823, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1576 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1577 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1578 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1579 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1580 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1581 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1582 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1583 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1613824, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1622015, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1613824, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1622015, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1584 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1585 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1586 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1587 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1588 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1589 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1590 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1591 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1622016, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1630207, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1622016, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1630207, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1592 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1593 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1594 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1595 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1596 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1597 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1598 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1599 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1630208, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1638399, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1630208, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1638399, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1600 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1601 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1602 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1603 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1604 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1605 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1606 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1607 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1638400, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1646591, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1638400, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1646591, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1608 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1609 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1610 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1611 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1612 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1613 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1614 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1615 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1646592, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1654783, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1646592, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1654783, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1616 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1617 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1618 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1619 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1620 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1621 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1622 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1623 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1654784, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1662975, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1654784, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1662975, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1624 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1625 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1626 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1627 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1628 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1629 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1630 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1631 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1662976, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1671167, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1662976, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1671167, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1632 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1633 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1634 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1635 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1636 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1637 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1638 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1639 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1671168, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1679359, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1671168, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1679359, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1640 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1641 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1642 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1643 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1644 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1645 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1646 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1647 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1679360, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1687551, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1679360, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1687551, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1648 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1649 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1650 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1651 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1652 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1653 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1654 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1655 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1687552, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1695743, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1687552, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1695743, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1656 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1657 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1658 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1659 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1660 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1661 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1662 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1663 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1695744, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1703935, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1695744, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1703935, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1664 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1665 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1666 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1667 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1668 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1669 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1670 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1671 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1703936, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1712127, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1703936, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1712127, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1672 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1673 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1674 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1675 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1676 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1677 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1678 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1679 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1712128, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1720319, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1712128, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1720319, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1680 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1681 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1682 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1683 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1684 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1685 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1686 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1687 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1720320, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1728511, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1720320, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1728511, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1688 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1689 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1690 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1691 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1692 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1693 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1694 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1695 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1728512, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1736703, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1728512, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1736703, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1696 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1697 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1698 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1699 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1700 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1701 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1702 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1703 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1736704, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1744895, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1736704, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1744895, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1704 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1705 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1706 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1707 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1708 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1709 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1710 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1711 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1744896, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1753087, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1744896, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1753087, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1712 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1713 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1714 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1715 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1716 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1717 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1718 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1719 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1753088, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1761279, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1753088, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1761279, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1720 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1721 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1722 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1723 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1724 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1725 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1726 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1727 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1761280, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1769471, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1761280, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1769471, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1728 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1729 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1730 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1731 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1732 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1733 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1734 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1735 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1769472, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1777663, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1769472, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1777663, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1736 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1737 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1738 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1739 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1740 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1741 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1742 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1743 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1777664, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1785855, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1777664, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1785855, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1744 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1745 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1746 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1747 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1748 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1749 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1750 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1751 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1785856, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1794047, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1785856, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1794047, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1752 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1753 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1754 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1755 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1756 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1757 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1758 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1759 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1794048, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1802239, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1794048, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1802239, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1760 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1761 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1762 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1763 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1764 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1765 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1766 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1767 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1802240, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1810431, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1802240, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1810431, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1768 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1769 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1770 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1771 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1772 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1773 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1774 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1775 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1810432, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1818623, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1810432, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1818623, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1776 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1777 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1778 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1779 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1780 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1781 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1782 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1783 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1818624, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1826815, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1818624, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1826815, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1784 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1785 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1786 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1787 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1788 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1789 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1790 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1791 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1826816, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1835007, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1826816, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1835007, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1792 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1793 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1794 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1795 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1796 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1797 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1798 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1799 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1835008, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1843199, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1835008, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1843199, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1800 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1801 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1802 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1803 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1804 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1805 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1806 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1807 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1843200, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1851391, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1843200, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1851391, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1808 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1809 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1810 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1811 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1812 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1813 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1814 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1815 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1851392, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1859583, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1851392, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1859583, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1816 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1817 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1818 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1819 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1820 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1821 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1822 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1823 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1859584, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1867775, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1859584, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1867775, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1824 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1825 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1826 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1827 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1828 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1829 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1830 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1831 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1867776, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1875967, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1867776, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1875967, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1832 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1833 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1834 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1835 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1836 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1837 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1838 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1839 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1875968, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1884159, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1875968, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1884159, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1840 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1841 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1842 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1843 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1844 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1845 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1846 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1847 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1884160, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1892351, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1884160, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1892351, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1848 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1849 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1850 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1851 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1852 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1853 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1854 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1855 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1892352, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1900543, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1892352, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1900543, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1856 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1857 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1858 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1859 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1860 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1861 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1862 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1863 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1900544, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1908735, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1900544, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1908735, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1864 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1865 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1866 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1867 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1868 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1869 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1870 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1871 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1908736, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1916927, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1908736, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1916927, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1872 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1873 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1874 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1875 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1876 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1877 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1878 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1879 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1916928, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1925119, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1916928, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1925119, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1880 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1881 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1882 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1883 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1884 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1885 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1886 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1887 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1925120, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1933311, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1925120, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1933311, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1888 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1889 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1890 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1891 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1892 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1893 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1894 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1895 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1933312, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1941503, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1933312, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1941503, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1896 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1897 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1898 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1899 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1900 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1901 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1902 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1903 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1941504, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1949695, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1941504, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1949695, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1904 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1905 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1906 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1907 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1908 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1909 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1910 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1911 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1949696, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1957887, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1949696, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1957887, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1912 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1913 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1914 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1915 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1916 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1917 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1918 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1919 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1957888, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1966079, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1957888, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1966079, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1920 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1921 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1922 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1923 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1924 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1925 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1926 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1927 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1966080, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1974271, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1966080, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1974271, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1928 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1929 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1930 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1931 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1932 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1933 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1934 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1935 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1974272, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1982463, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1974272, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1982463, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1936 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1937 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1938 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1939 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1940 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1941 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1942 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1943 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1982464, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1990655, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1982464, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1990655, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1944 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1945 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1946 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1947 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1948 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1949 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1950 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1951 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1990656, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1998847, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1990656, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1998847, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1952 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1953 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1954 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1955 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1956 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1957 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1958 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1959 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 1998848, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2007039, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 1998848, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2007039, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1960 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1961 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1962 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1963 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1964 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1965 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1966 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1967 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2007040, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2015231, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2007040, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2015231, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1968 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1969 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1970 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1971 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1972 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1973 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1974 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1975 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2015232, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2023423, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2015232, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2023423, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1976 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1977 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1978 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1979 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1980 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1981 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1982 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1983 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2023424, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2031615, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2023424, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2031615, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1984 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1985 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1986 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1987 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1988 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1989 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1990 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1991 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2031616, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2039807, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2031616, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2039807, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1992 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1993 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1994 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1995 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1996 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1997 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1998 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1999 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2039808, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2047999, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2039808, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2047999, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2000 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2001 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2002 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2003 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2004 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2005 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2006 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2007 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2048000, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2056191, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2048000, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2056191, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2008 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2009 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2010 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2011 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2012 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2013 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2014 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2015 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2056192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2064383, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2056192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2064383, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2016 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2017 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2018 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2019 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2020 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2021 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2022 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2023 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2064384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2072575, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2064384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2072575, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2024 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2025 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2026 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2027 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2028 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2029 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2030 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2031 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2072576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2080767, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2072576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2080767, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2032 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2033 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2034 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2035 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2036 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2037 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2038 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2039 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2080768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2088959, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2080768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2088959, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2040 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2041 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2042 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2043 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2044 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2045 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2046 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2047 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 2088960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2097151, + PORT_A_LOGICAL_RAM_DEPTH = 2097152, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 2088960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2097151, + PORT_B_LOGICAL_RAM_DEPTH = 2097152, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[20..0] : WIRE; + address_b_sel[7..0] : WIRE; + address_b_wire[20..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[7..0] = address_a_wire[20..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[2047..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[2047..0].clk0 = clock0; + ram_block1a[2047..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[0..0]); + ram_block1a[41].portadatain[] = ( data_a[1..1]); + ram_block1a[42].portadatain[] = ( data_a[2..2]); + ram_block1a[43].portadatain[] = ( data_a[3..3]); + ram_block1a[44].portadatain[] = ( data_a[4..4]); + ram_block1a[45].portadatain[] = ( data_a[5..5]); + ram_block1a[46].portadatain[] = ( data_a[6..6]); + ram_block1a[47].portadatain[] = ( data_a[7..7]); + ram_block1a[48].portadatain[] = ( data_a[0..0]); + ram_block1a[49].portadatain[] = ( data_a[1..1]); + ram_block1a[50].portadatain[] = ( data_a[2..2]); + ram_block1a[51].portadatain[] = ( data_a[3..3]); + ram_block1a[52].portadatain[] = ( data_a[4..4]); + ram_block1a[53].portadatain[] = ( data_a[5..5]); + ram_block1a[54].portadatain[] = ( data_a[6..6]); + ram_block1a[55].portadatain[] = ( data_a[7..7]); + ram_block1a[56].portadatain[] = ( data_a[0..0]); + ram_block1a[57].portadatain[] = ( data_a[1..1]); + ram_block1a[58].portadatain[] = ( data_a[2..2]); + ram_block1a[59].portadatain[] = ( data_a[3..3]); + ram_block1a[60].portadatain[] = ( data_a[4..4]); + ram_block1a[61].portadatain[] = ( data_a[5..5]); + ram_block1a[62].portadatain[] = ( data_a[6..6]); + ram_block1a[63].portadatain[] = ( data_a[7..7]); + ram_block1a[64].portadatain[] = ( data_a[0..0]); + ram_block1a[65].portadatain[] = ( data_a[1..1]); + ram_block1a[66].portadatain[] = ( data_a[2..2]); + ram_block1a[67].portadatain[] = ( data_a[3..3]); + ram_block1a[68].portadatain[] = ( data_a[4..4]); + ram_block1a[69].portadatain[] = ( data_a[5..5]); + ram_block1a[70].portadatain[] = ( data_a[6..6]); + ram_block1a[71].portadatain[] = ( data_a[7..7]); + ram_block1a[72].portadatain[] = ( data_a[0..0]); + ram_block1a[73].portadatain[] = ( data_a[1..1]); + ram_block1a[74].portadatain[] = ( data_a[2..2]); + ram_block1a[75].portadatain[] = ( data_a[3..3]); + ram_block1a[76].portadatain[] = ( data_a[4..4]); + ram_block1a[77].portadatain[] = ( data_a[5..5]); + ram_block1a[78].portadatain[] = ( data_a[6..6]); + ram_block1a[79].portadatain[] = ( data_a[7..7]); + ram_block1a[80].portadatain[] = ( data_a[0..0]); + ram_block1a[81].portadatain[] = ( data_a[1..1]); + ram_block1a[82].portadatain[] = ( data_a[2..2]); + ram_block1a[83].portadatain[] = ( data_a[3..3]); + ram_block1a[84].portadatain[] = ( data_a[4..4]); + ram_block1a[85].portadatain[] = ( data_a[5..5]); + ram_block1a[86].portadatain[] = ( data_a[6..6]); + ram_block1a[87].portadatain[] = ( data_a[7..7]); + ram_block1a[88].portadatain[] = ( data_a[0..0]); + ram_block1a[89].portadatain[] = ( data_a[1..1]); + ram_block1a[90].portadatain[] = ( data_a[2..2]); + ram_block1a[91].portadatain[] = ( data_a[3..3]); + ram_block1a[92].portadatain[] = ( data_a[4..4]); + ram_block1a[93].portadatain[] = ( data_a[5..5]); + ram_block1a[94].portadatain[] = ( data_a[6..6]); + ram_block1a[95].portadatain[] = ( data_a[7..7]); + ram_block1a[96].portadatain[] = ( data_a[0..0]); + ram_block1a[97].portadatain[] = ( data_a[1..1]); + ram_block1a[98].portadatain[] = ( data_a[2..2]); + ram_block1a[99].portadatain[] = ( data_a[3..3]); + ram_block1a[100].portadatain[] = ( data_a[4..4]); + ram_block1a[101].portadatain[] = ( data_a[5..5]); + ram_block1a[102].portadatain[] = ( data_a[6..6]); + ram_block1a[103].portadatain[] = ( data_a[7..7]); + ram_block1a[104].portadatain[] = ( data_a[0..0]); + ram_block1a[105].portadatain[] = ( data_a[1..1]); + ram_block1a[106].portadatain[] = ( data_a[2..2]); + ram_block1a[107].portadatain[] = ( data_a[3..3]); + ram_block1a[108].portadatain[] = ( data_a[4..4]); + ram_block1a[109].portadatain[] = ( data_a[5..5]); + ram_block1a[110].portadatain[] = ( data_a[6..6]); + ram_block1a[111].portadatain[] = ( data_a[7..7]); + ram_block1a[112].portadatain[] = ( data_a[0..0]); + ram_block1a[113].portadatain[] = ( data_a[1..1]); + ram_block1a[114].portadatain[] = ( data_a[2..2]); + ram_block1a[115].portadatain[] = ( data_a[3..3]); + ram_block1a[116].portadatain[] = ( data_a[4..4]); + ram_block1a[117].portadatain[] = ( data_a[5..5]); + ram_block1a[118].portadatain[] = ( data_a[6..6]); + ram_block1a[119].portadatain[] = ( data_a[7..7]); + ram_block1a[120].portadatain[] = ( data_a[0..0]); + ram_block1a[121].portadatain[] = ( data_a[1..1]); + ram_block1a[122].portadatain[] = ( data_a[2..2]); + ram_block1a[123].portadatain[] = ( data_a[3..3]); + ram_block1a[124].portadatain[] = ( data_a[4..4]); + ram_block1a[125].portadatain[] = ( data_a[5..5]); + ram_block1a[126].portadatain[] = ( data_a[6..6]); + ram_block1a[127].portadatain[] = ( data_a[7..7]); + ram_block1a[128].portadatain[] = ( data_a[0..0]); + ram_block1a[129].portadatain[] = ( data_a[1..1]); + ram_block1a[130].portadatain[] = ( data_a[2..2]); + ram_block1a[131].portadatain[] = ( data_a[3..3]); + ram_block1a[132].portadatain[] = ( data_a[4..4]); + ram_block1a[133].portadatain[] = ( data_a[5..5]); + ram_block1a[134].portadatain[] = ( data_a[6..6]); + ram_block1a[135].portadatain[] = ( data_a[7..7]); + ram_block1a[136].portadatain[] = ( data_a[0..0]); + ram_block1a[137].portadatain[] = ( data_a[1..1]); + ram_block1a[138].portadatain[] = ( data_a[2..2]); + ram_block1a[139].portadatain[] = ( data_a[3..3]); + ram_block1a[140].portadatain[] = ( data_a[4..4]); + ram_block1a[141].portadatain[] = ( data_a[5..5]); + ram_block1a[142].portadatain[] = ( data_a[6..6]); + ram_block1a[143].portadatain[] = ( data_a[7..7]); + ram_block1a[144].portadatain[] = ( data_a[0..0]); + ram_block1a[145].portadatain[] = ( data_a[1..1]); + ram_block1a[146].portadatain[] = ( data_a[2..2]); + ram_block1a[147].portadatain[] = ( data_a[3..3]); + ram_block1a[148].portadatain[] = ( data_a[4..4]); + ram_block1a[149].portadatain[] = ( data_a[5..5]); + ram_block1a[150].portadatain[] = ( data_a[6..6]); + ram_block1a[151].portadatain[] = ( data_a[7..7]); + ram_block1a[152].portadatain[] = ( data_a[0..0]); + ram_block1a[153].portadatain[] = ( data_a[1..1]); + ram_block1a[154].portadatain[] = ( data_a[2..2]); + ram_block1a[155].portadatain[] = ( data_a[3..3]); + ram_block1a[156].portadatain[] = ( data_a[4..4]); + ram_block1a[157].portadatain[] = ( data_a[5..5]); + ram_block1a[158].portadatain[] = ( data_a[6..6]); + ram_block1a[159].portadatain[] = ( data_a[7..7]); + ram_block1a[160].portadatain[] = ( data_a[0..0]); + ram_block1a[161].portadatain[] = ( data_a[1..1]); + ram_block1a[162].portadatain[] = ( data_a[2..2]); + ram_block1a[163].portadatain[] = ( data_a[3..3]); + ram_block1a[164].portadatain[] = ( data_a[4..4]); + ram_block1a[165].portadatain[] = ( data_a[5..5]); + ram_block1a[166].portadatain[] = ( data_a[6..6]); + ram_block1a[167].portadatain[] = ( data_a[7..7]); + ram_block1a[168].portadatain[] = ( data_a[0..0]); + ram_block1a[169].portadatain[] = ( data_a[1..1]); + ram_block1a[170].portadatain[] = ( data_a[2..2]); + ram_block1a[171].portadatain[] = ( data_a[3..3]); + ram_block1a[172].portadatain[] = ( data_a[4..4]); + ram_block1a[173].portadatain[] = ( data_a[5..5]); + ram_block1a[174].portadatain[] = ( data_a[6..6]); + ram_block1a[175].portadatain[] = ( data_a[7..7]); + ram_block1a[176].portadatain[] = ( data_a[0..0]); + ram_block1a[177].portadatain[] = ( data_a[1..1]); + ram_block1a[178].portadatain[] = ( data_a[2..2]); + ram_block1a[179].portadatain[] = ( data_a[3..3]); + ram_block1a[180].portadatain[] = ( data_a[4..4]); + ram_block1a[181].portadatain[] = ( data_a[5..5]); + ram_block1a[182].portadatain[] = ( data_a[6..6]); + ram_block1a[183].portadatain[] = ( data_a[7..7]); + ram_block1a[184].portadatain[] = ( data_a[0..0]); + ram_block1a[185].portadatain[] = ( data_a[1..1]); + ram_block1a[186].portadatain[] = ( data_a[2..2]); + ram_block1a[187].portadatain[] = ( data_a[3..3]); + ram_block1a[188].portadatain[] = ( data_a[4..4]); + ram_block1a[189].portadatain[] = ( data_a[5..5]); + ram_block1a[190].portadatain[] = ( data_a[6..6]); + ram_block1a[191].portadatain[] = ( data_a[7..7]); + ram_block1a[192].portadatain[] = ( data_a[0..0]); + ram_block1a[193].portadatain[] = ( data_a[1..1]); + ram_block1a[194].portadatain[] = ( data_a[2..2]); + ram_block1a[195].portadatain[] = ( data_a[3..3]); + ram_block1a[196].portadatain[] = ( data_a[4..4]); + ram_block1a[197].portadatain[] = ( data_a[5..5]); + ram_block1a[198].portadatain[] = ( data_a[6..6]); + ram_block1a[199].portadatain[] = ( data_a[7..7]); + ram_block1a[200].portadatain[] = ( data_a[0..0]); + ram_block1a[201].portadatain[] = ( data_a[1..1]); + ram_block1a[202].portadatain[] = ( data_a[2..2]); + ram_block1a[203].portadatain[] = ( data_a[3..3]); + ram_block1a[204].portadatain[] = ( data_a[4..4]); + ram_block1a[205].portadatain[] = ( data_a[5..5]); + ram_block1a[206].portadatain[] = ( data_a[6..6]); + ram_block1a[207].portadatain[] = ( data_a[7..7]); + ram_block1a[208].portadatain[] = ( data_a[0..0]); + ram_block1a[209].portadatain[] = ( data_a[1..1]); + ram_block1a[210].portadatain[] = ( data_a[2..2]); + ram_block1a[211].portadatain[] = ( data_a[3..3]); + ram_block1a[212].portadatain[] = ( data_a[4..4]); + ram_block1a[213].portadatain[] = ( data_a[5..5]); + ram_block1a[214].portadatain[] = ( data_a[6..6]); + ram_block1a[215].portadatain[] = ( data_a[7..7]); + ram_block1a[216].portadatain[] = ( data_a[0..0]); + ram_block1a[217].portadatain[] = ( data_a[1..1]); + ram_block1a[218].portadatain[] = ( data_a[2..2]); + ram_block1a[219].portadatain[] = ( data_a[3..3]); + ram_block1a[220].portadatain[] = ( data_a[4..4]); + ram_block1a[221].portadatain[] = ( data_a[5..5]); + ram_block1a[222].portadatain[] = ( data_a[6..6]); + ram_block1a[223].portadatain[] = ( data_a[7..7]); + ram_block1a[224].portadatain[] = ( data_a[0..0]); + ram_block1a[225].portadatain[] = ( data_a[1..1]); + ram_block1a[226].portadatain[] = ( data_a[2..2]); + ram_block1a[227].portadatain[] = ( data_a[3..3]); + ram_block1a[228].portadatain[] = ( data_a[4..4]); + ram_block1a[229].portadatain[] = ( data_a[5..5]); + ram_block1a[230].portadatain[] = ( data_a[6..6]); + ram_block1a[231].portadatain[] = ( data_a[7..7]); + ram_block1a[232].portadatain[] = ( data_a[0..0]); + ram_block1a[233].portadatain[] = ( data_a[1..1]); + ram_block1a[234].portadatain[] = ( data_a[2..2]); + ram_block1a[235].portadatain[] = ( data_a[3..3]); + ram_block1a[236].portadatain[] = ( data_a[4..4]); + ram_block1a[237].portadatain[] = ( data_a[5..5]); + ram_block1a[238].portadatain[] = ( data_a[6..6]); + ram_block1a[239].portadatain[] = ( data_a[7..7]); + ram_block1a[240].portadatain[] = ( data_a[0..0]); + ram_block1a[241].portadatain[] = ( data_a[1..1]); + ram_block1a[242].portadatain[] = ( data_a[2..2]); + ram_block1a[243].portadatain[] = ( data_a[3..3]); + ram_block1a[244].portadatain[] = ( data_a[4..4]); + ram_block1a[245].portadatain[] = ( data_a[5..5]); + ram_block1a[246].portadatain[] = ( data_a[6..6]); + ram_block1a[247].portadatain[] = ( data_a[7..7]); + ram_block1a[248].portadatain[] = ( data_a[0..0]); + ram_block1a[249].portadatain[] = ( data_a[1..1]); + ram_block1a[250].portadatain[] = ( data_a[2..2]); + ram_block1a[251].portadatain[] = ( data_a[3..3]); + ram_block1a[252].portadatain[] = ( data_a[4..4]); + ram_block1a[253].portadatain[] = ( data_a[5..5]); + ram_block1a[254].portadatain[] = ( data_a[6..6]); + ram_block1a[255].portadatain[] = ( data_a[7..7]); + ram_block1a[256].portadatain[] = ( data_a[0..0]); + ram_block1a[257].portadatain[] = ( data_a[1..1]); + ram_block1a[258].portadatain[] = ( data_a[2..2]); + ram_block1a[259].portadatain[] = ( data_a[3..3]); + ram_block1a[260].portadatain[] = ( data_a[4..4]); + ram_block1a[261].portadatain[] = ( data_a[5..5]); + ram_block1a[262].portadatain[] = ( data_a[6..6]); + ram_block1a[263].portadatain[] = ( data_a[7..7]); + ram_block1a[264].portadatain[] = ( data_a[0..0]); + ram_block1a[265].portadatain[] = ( data_a[1..1]); + ram_block1a[266].portadatain[] = ( data_a[2..2]); + ram_block1a[267].portadatain[] = ( data_a[3..3]); + ram_block1a[268].portadatain[] = ( data_a[4..4]); + ram_block1a[269].portadatain[] = ( data_a[5..5]); + ram_block1a[270].portadatain[] = ( data_a[6..6]); + ram_block1a[271].portadatain[] = ( data_a[7..7]); + ram_block1a[272].portadatain[] = ( data_a[0..0]); + ram_block1a[273].portadatain[] = ( data_a[1..1]); + ram_block1a[274].portadatain[] = ( data_a[2..2]); + ram_block1a[275].portadatain[] = ( data_a[3..3]); + ram_block1a[276].portadatain[] = ( data_a[4..4]); + ram_block1a[277].portadatain[] = ( data_a[5..5]); + ram_block1a[278].portadatain[] = ( data_a[6..6]); + ram_block1a[279].portadatain[] = ( data_a[7..7]); + ram_block1a[280].portadatain[] = ( data_a[0..0]); + ram_block1a[281].portadatain[] = ( data_a[1..1]); + ram_block1a[282].portadatain[] = ( data_a[2..2]); + ram_block1a[283].portadatain[] = ( data_a[3..3]); + ram_block1a[284].portadatain[] = ( data_a[4..4]); + ram_block1a[285].portadatain[] = ( data_a[5..5]); + ram_block1a[286].portadatain[] = ( data_a[6..6]); + ram_block1a[287].portadatain[] = ( data_a[7..7]); + ram_block1a[288].portadatain[] = ( data_a[0..0]); + ram_block1a[289].portadatain[] = ( data_a[1..1]); + ram_block1a[290].portadatain[] = ( data_a[2..2]); + ram_block1a[291].portadatain[] = ( data_a[3..3]); + ram_block1a[292].portadatain[] = ( data_a[4..4]); + ram_block1a[293].portadatain[] = ( data_a[5..5]); + ram_block1a[294].portadatain[] = ( data_a[6..6]); + ram_block1a[295].portadatain[] = ( data_a[7..7]); + ram_block1a[296].portadatain[] = ( data_a[0..0]); + ram_block1a[297].portadatain[] = ( data_a[1..1]); + ram_block1a[298].portadatain[] = ( data_a[2..2]); + ram_block1a[299].portadatain[] = ( data_a[3..3]); + ram_block1a[300].portadatain[] = ( data_a[4..4]); + ram_block1a[301].portadatain[] = ( data_a[5..5]); + ram_block1a[302].portadatain[] = ( data_a[6..6]); + ram_block1a[303].portadatain[] = ( data_a[7..7]); + ram_block1a[304].portadatain[] = ( data_a[0..0]); + ram_block1a[305].portadatain[] = ( data_a[1..1]); + ram_block1a[306].portadatain[] = ( data_a[2..2]); + ram_block1a[307].portadatain[] = ( data_a[3..3]); + ram_block1a[308].portadatain[] = ( data_a[4..4]); + ram_block1a[309].portadatain[] = ( data_a[5..5]); + ram_block1a[310].portadatain[] = ( data_a[6..6]); + ram_block1a[311].portadatain[] = ( data_a[7..7]); + ram_block1a[312].portadatain[] = ( data_a[0..0]); + ram_block1a[313].portadatain[] = ( data_a[1..1]); + ram_block1a[314].portadatain[] = ( data_a[2..2]); + ram_block1a[315].portadatain[] = ( data_a[3..3]); + ram_block1a[316].portadatain[] = ( data_a[4..4]); + ram_block1a[317].portadatain[] = ( data_a[5..5]); + ram_block1a[318].portadatain[] = ( data_a[6..6]); + ram_block1a[319].portadatain[] = ( data_a[7..7]); + ram_block1a[320].portadatain[] = ( data_a[0..0]); + ram_block1a[321].portadatain[] = ( data_a[1..1]); + ram_block1a[322].portadatain[] = ( data_a[2..2]); + ram_block1a[323].portadatain[] = ( data_a[3..3]); + ram_block1a[324].portadatain[] = ( data_a[4..4]); + ram_block1a[325].portadatain[] = ( data_a[5..5]); + ram_block1a[326].portadatain[] = ( data_a[6..6]); + ram_block1a[327].portadatain[] = ( data_a[7..7]); + ram_block1a[328].portadatain[] = ( data_a[0..0]); + ram_block1a[329].portadatain[] = ( data_a[1..1]); + ram_block1a[330].portadatain[] = ( data_a[2..2]); + ram_block1a[331].portadatain[] = ( data_a[3..3]); + ram_block1a[332].portadatain[] = ( data_a[4..4]); + ram_block1a[333].portadatain[] = ( data_a[5..5]); + ram_block1a[334].portadatain[] = ( data_a[6..6]); + ram_block1a[335].portadatain[] = ( data_a[7..7]); + ram_block1a[336].portadatain[] = ( data_a[0..0]); + ram_block1a[337].portadatain[] = ( data_a[1..1]); + ram_block1a[338].portadatain[] = ( data_a[2..2]); + ram_block1a[339].portadatain[] = ( data_a[3..3]); + ram_block1a[340].portadatain[] = ( data_a[4..4]); + ram_block1a[341].portadatain[] = ( data_a[5..5]); + ram_block1a[342].portadatain[] = ( data_a[6..6]); + ram_block1a[343].portadatain[] = ( data_a[7..7]); + ram_block1a[344].portadatain[] = ( data_a[0..0]); + ram_block1a[345].portadatain[] = ( data_a[1..1]); + ram_block1a[346].portadatain[] = ( data_a[2..2]); + ram_block1a[347].portadatain[] = ( data_a[3..3]); + ram_block1a[348].portadatain[] = ( data_a[4..4]); + ram_block1a[349].portadatain[] = ( data_a[5..5]); + ram_block1a[350].portadatain[] = ( data_a[6..6]); + ram_block1a[351].portadatain[] = ( data_a[7..7]); + ram_block1a[352].portadatain[] = ( data_a[0..0]); + ram_block1a[353].portadatain[] = ( data_a[1..1]); + ram_block1a[354].portadatain[] = ( data_a[2..2]); + ram_block1a[355].portadatain[] = ( data_a[3..3]); + ram_block1a[356].portadatain[] = ( data_a[4..4]); + ram_block1a[357].portadatain[] = ( data_a[5..5]); + ram_block1a[358].portadatain[] = ( data_a[6..6]); + ram_block1a[359].portadatain[] = ( data_a[7..7]); + ram_block1a[360].portadatain[] = ( data_a[0..0]); + ram_block1a[361].portadatain[] = ( data_a[1..1]); + ram_block1a[362].portadatain[] = ( data_a[2..2]); + ram_block1a[363].portadatain[] = ( data_a[3..3]); + ram_block1a[364].portadatain[] = ( data_a[4..4]); + ram_block1a[365].portadatain[] = ( data_a[5..5]); + ram_block1a[366].portadatain[] = ( data_a[6..6]); + ram_block1a[367].portadatain[] = ( data_a[7..7]); + ram_block1a[368].portadatain[] = ( data_a[0..0]); + ram_block1a[369].portadatain[] = ( data_a[1..1]); + ram_block1a[370].portadatain[] = ( data_a[2..2]); + ram_block1a[371].portadatain[] = ( data_a[3..3]); + ram_block1a[372].portadatain[] = ( data_a[4..4]); + ram_block1a[373].portadatain[] = ( data_a[5..5]); + ram_block1a[374].portadatain[] = ( data_a[6..6]); + ram_block1a[375].portadatain[] = ( data_a[7..7]); + ram_block1a[376].portadatain[] = ( data_a[0..0]); + ram_block1a[377].portadatain[] = ( data_a[1..1]); + ram_block1a[378].portadatain[] = ( data_a[2..2]); + ram_block1a[379].portadatain[] = ( data_a[3..3]); + ram_block1a[380].portadatain[] = ( data_a[4..4]); + ram_block1a[381].portadatain[] = ( data_a[5..5]); + ram_block1a[382].portadatain[] = ( data_a[6..6]); + ram_block1a[383].portadatain[] = ( data_a[7..7]); + ram_block1a[384].portadatain[] = ( data_a[0..0]); + ram_block1a[385].portadatain[] = ( data_a[1..1]); + ram_block1a[386].portadatain[] = ( data_a[2..2]); + ram_block1a[387].portadatain[] = ( data_a[3..3]); + ram_block1a[388].portadatain[] = ( data_a[4..4]); + ram_block1a[389].portadatain[] = ( data_a[5..5]); + ram_block1a[390].portadatain[] = ( data_a[6..6]); + ram_block1a[391].portadatain[] = ( data_a[7..7]); + ram_block1a[392].portadatain[] = ( data_a[0..0]); + ram_block1a[393].portadatain[] = ( data_a[1..1]); + ram_block1a[394].portadatain[] = ( data_a[2..2]); + ram_block1a[395].portadatain[] = ( data_a[3..3]); + ram_block1a[396].portadatain[] = ( data_a[4..4]); + ram_block1a[397].portadatain[] = ( data_a[5..5]); + ram_block1a[398].portadatain[] = ( data_a[6..6]); + ram_block1a[399].portadatain[] = ( data_a[7..7]); + ram_block1a[400].portadatain[] = ( data_a[0..0]); + ram_block1a[401].portadatain[] = ( data_a[1..1]); + ram_block1a[402].portadatain[] = ( data_a[2..2]); + ram_block1a[403].portadatain[] = ( data_a[3..3]); + ram_block1a[404].portadatain[] = ( data_a[4..4]); + ram_block1a[405].portadatain[] = ( data_a[5..5]); + ram_block1a[406].portadatain[] = ( data_a[6..6]); + ram_block1a[407].portadatain[] = ( data_a[7..7]); + ram_block1a[408].portadatain[] = ( data_a[0..0]); + ram_block1a[409].portadatain[] = ( data_a[1..1]); + ram_block1a[410].portadatain[] = ( data_a[2..2]); + ram_block1a[411].portadatain[] = ( data_a[3..3]); + ram_block1a[412].portadatain[] = ( data_a[4..4]); + ram_block1a[413].portadatain[] = ( data_a[5..5]); + ram_block1a[414].portadatain[] = ( data_a[6..6]); + ram_block1a[415].portadatain[] = ( data_a[7..7]); + ram_block1a[416].portadatain[] = ( data_a[0..0]); + ram_block1a[417].portadatain[] = ( data_a[1..1]); + ram_block1a[418].portadatain[] = ( data_a[2..2]); + ram_block1a[419].portadatain[] = ( data_a[3..3]); + ram_block1a[420].portadatain[] = ( data_a[4..4]); + ram_block1a[421].portadatain[] = ( data_a[5..5]); + ram_block1a[422].portadatain[] = ( data_a[6..6]); + ram_block1a[423].portadatain[] = ( data_a[7..7]); + ram_block1a[424].portadatain[] = ( data_a[0..0]); + ram_block1a[425].portadatain[] = ( data_a[1..1]); + ram_block1a[426].portadatain[] = ( data_a[2..2]); + ram_block1a[427].portadatain[] = ( data_a[3..3]); + ram_block1a[428].portadatain[] = ( data_a[4..4]); + ram_block1a[429].portadatain[] = ( data_a[5..5]); + ram_block1a[430].portadatain[] = ( data_a[6..6]); + ram_block1a[431].portadatain[] = ( data_a[7..7]); + ram_block1a[432].portadatain[] = ( data_a[0..0]); + ram_block1a[433].portadatain[] = ( data_a[1..1]); + ram_block1a[434].portadatain[] = ( data_a[2..2]); + ram_block1a[435].portadatain[] = ( data_a[3..3]); + ram_block1a[436].portadatain[] = ( data_a[4..4]); + ram_block1a[437].portadatain[] = ( data_a[5..5]); + ram_block1a[438].portadatain[] = ( data_a[6..6]); + ram_block1a[439].portadatain[] = ( data_a[7..7]); + ram_block1a[440].portadatain[] = ( data_a[0..0]); + ram_block1a[441].portadatain[] = ( data_a[1..1]); + ram_block1a[442].portadatain[] = ( data_a[2..2]); + ram_block1a[443].portadatain[] = ( data_a[3..3]); + ram_block1a[444].portadatain[] = ( data_a[4..4]); + ram_block1a[445].portadatain[] = ( data_a[5..5]); + ram_block1a[446].portadatain[] = ( data_a[6..6]); + ram_block1a[447].portadatain[] = ( data_a[7..7]); + ram_block1a[448].portadatain[] = ( data_a[0..0]); + ram_block1a[449].portadatain[] = ( data_a[1..1]); + ram_block1a[450].portadatain[] = ( data_a[2..2]); + ram_block1a[451].portadatain[] = ( data_a[3..3]); + ram_block1a[452].portadatain[] = ( data_a[4..4]); + ram_block1a[453].portadatain[] = ( data_a[5..5]); + ram_block1a[454].portadatain[] = ( data_a[6..6]); + ram_block1a[455].portadatain[] = ( data_a[7..7]); + ram_block1a[456].portadatain[] = ( data_a[0..0]); + ram_block1a[457].portadatain[] = ( data_a[1..1]); + ram_block1a[458].portadatain[] = ( data_a[2..2]); + ram_block1a[459].portadatain[] = ( data_a[3..3]); + ram_block1a[460].portadatain[] = ( data_a[4..4]); + ram_block1a[461].portadatain[] = ( data_a[5..5]); + ram_block1a[462].portadatain[] = ( data_a[6..6]); + ram_block1a[463].portadatain[] = ( data_a[7..7]); + ram_block1a[464].portadatain[] = ( data_a[0..0]); + ram_block1a[465].portadatain[] = ( data_a[1..1]); + ram_block1a[466].portadatain[] = ( data_a[2..2]); + ram_block1a[467].portadatain[] = ( data_a[3..3]); + ram_block1a[468].portadatain[] = ( data_a[4..4]); + ram_block1a[469].portadatain[] = ( data_a[5..5]); + ram_block1a[470].portadatain[] = ( data_a[6..6]); + ram_block1a[471].portadatain[] = ( data_a[7..7]); + ram_block1a[472].portadatain[] = ( data_a[0..0]); + ram_block1a[473].portadatain[] = ( data_a[1..1]); + ram_block1a[474].portadatain[] = ( data_a[2..2]); + ram_block1a[475].portadatain[] = ( data_a[3..3]); + ram_block1a[476].portadatain[] = ( data_a[4..4]); + ram_block1a[477].portadatain[] = ( data_a[5..5]); + ram_block1a[478].portadatain[] = ( data_a[6..6]); + ram_block1a[479].portadatain[] = ( data_a[7..7]); + ram_block1a[480].portadatain[] = ( data_a[0..0]); + ram_block1a[481].portadatain[] = ( data_a[1..1]); + ram_block1a[482].portadatain[] = ( data_a[2..2]); + ram_block1a[483].portadatain[] = ( data_a[3..3]); + ram_block1a[484].portadatain[] = ( data_a[4..4]); + ram_block1a[485].portadatain[] = ( data_a[5..5]); + ram_block1a[486].portadatain[] = ( data_a[6..6]); + ram_block1a[487].portadatain[] = ( data_a[7..7]); + ram_block1a[488].portadatain[] = ( data_a[0..0]); + ram_block1a[489].portadatain[] = ( data_a[1..1]); + ram_block1a[490].portadatain[] = ( data_a[2..2]); + ram_block1a[491].portadatain[] = ( data_a[3..3]); + ram_block1a[492].portadatain[] = ( data_a[4..4]); + ram_block1a[493].portadatain[] = ( data_a[5..5]); + ram_block1a[494].portadatain[] = ( data_a[6..6]); + ram_block1a[495].portadatain[] = ( data_a[7..7]); + ram_block1a[496].portadatain[] = ( data_a[0..0]); + ram_block1a[497].portadatain[] = ( data_a[1..1]); + ram_block1a[498].portadatain[] = ( data_a[2..2]); + ram_block1a[499].portadatain[] = ( data_a[3..3]); + ram_block1a[500].portadatain[] = ( data_a[4..4]); + ram_block1a[501].portadatain[] = ( data_a[5..5]); + ram_block1a[502].portadatain[] = ( data_a[6..6]); + ram_block1a[503].portadatain[] = ( data_a[7..7]); + ram_block1a[504].portadatain[] = ( data_a[0..0]); + ram_block1a[505].portadatain[] = ( data_a[1..1]); + ram_block1a[506].portadatain[] = ( data_a[2..2]); + ram_block1a[507].portadatain[] = ( data_a[3..3]); + ram_block1a[508].portadatain[] = ( data_a[4..4]); + ram_block1a[509].portadatain[] = ( data_a[5..5]); + ram_block1a[510].portadatain[] = ( data_a[6..6]); + ram_block1a[511].portadatain[] = ( data_a[7..7]); + ram_block1a[512].portadatain[] = ( data_a[0..0]); + ram_block1a[513].portadatain[] = ( data_a[1..1]); + ram_block1a[514].portadatain[] = ( data_a[2..2]); + ram_block1a[515].portadatain[] = ( data_a[3..3]); + ram_block1a[516].portadatain[] = ( data_a[4..4]); + ram_block1a[517].portadatain[] = ( data_a[5..5]); + ram_block1a[518].portadatain[] = ( data_a[6..6]); + ram_block1a[519].portadatain[] = ( data_a[7..7]); + ram_block1a[520].portadatain[] = ( data_a[0..0]); + ram_block1a[521].portadatain[] = ( data_a[1..1]); + ram_block1a[522].portadatain[] = ( data_a[2..2]); + ram_block1a[523].portadatain[] = ( data_a[3..3]); + ram_block1a[524].portadatain[] = ( data_a[4..4]); + ram_block1a[525].portadatain[] = ( data_a[5..5]); + ram_block1a[526].portadatain[] = ( data_a[6..6]); + ram_block1a[527].portadatain[] = ( data_a[7..7]); + ram_block1a[528].portadatain[] = ( data_a[0..0]); + ram_block1a[529].portadatain[] = ( data_a[1..1]); + ram_block1a[530].portadatain[] = ( data_a[2..2]); + ram_block1a[531].portadatain[] = ( data_a[3..3]); + ram_block1a[532].portadatain[] = ( data_a[4..4]); + ram_block1a[533].portadatain[] = ( data_a[5..5]); + ram_block1a[534].portadatain[] = ( data_a[6..6]); + ram_block1a[535].portadatain[] = ( data_a[7..7]); + ram_block1a[536].portadatain[] = ( data_a[0..0]); + ram_block1a[537].portadatain[] = ( data_a[1..1]); + ram_block1a[538].portadatain[] = ( data_a[2..2]); + ram_block1a[539].portadatain[] = ( data_a[3..3]); + ram_block1a[540].portadatain[] = ( data_a[4..4]); + ram_block1a[541].portadatain[] = ( data_a[5..5]); + ram_block1a[542].portadatain[] = ( data_a[6..6]); + ram_block1a[543].portadatain[] = ( data_a[7..7]); + ram_block1a[544].portadatain[] = ( data_a[0..0]); + ram_block1a[545].portadatain[] = ( data_a[1..1]); + ram_block1a[546].portadatain[] = ( data_a[2..2]); + ram_block1a[547].portadatain[] = ( data_a[3..3]); + ram_block1a[548].portadatain[] = ( data_a[4..4]); + ram_block1a[549].portadatain[] = ( data_a[5..5]); + ram_block1a[550].portadatain[] = ( data_a[6..6]); + ram_block1a[551].portadatain[] = ( data_a[7..7]); + ram_block1a[552].portadatain[] = ( data_a[0..0]); + ram_block1a[553].portadatain[] = ( data_a[1..1]); + ram_block1a[554].portadatain[] = ( data_a[2..2]); + ram_block1a[555].portadatain[] = ( data_a[3..3]); + ram_block1a[556].portadatain[] = ( data_a[4..4]); + ram_block1a[557].portadatain[] = ( data_a[5..5]); + ram_block1a[558].portadatain[] = ( data_a[6..6]); + ram_block1a[559].portadatain[] = ( data_a[7..7]); + ram_block1a[560].portadatain[] = ( data_a[0..0]); + ram_block1a[561].portadatain[] = ( data_a[1..1]); + ram_block1a[562].portadatain[] = ( data_a[2..2]); + ram_block1a[563].portadatain[] = ( data_a[3..3]); + ram_block1a[564].portadatain[] = ( data_a[4..4]); + ram_block1a[565].portadatain[] = ( data_a[5..5]); + ram_block1a[566].portadatain[] = ( data_a[6..6]); + ram_block1a[567].portadatain[] = ( data_a[7..7]); + ram_block1a[568].portadatain[] = ( data_a[0..0]); + ram_block1a[569].portadatain[] = ( data_a[1..1]); + ram_block1a[570].portadatain[] = ( data_a[2..2]); + ram_block1a[571].portadatain[] = ( data_a[3..3]); + ram_block1a[572].portadatain[] = ( data_a[4..4]); + ram_block1a[573].portadatain[] = ( data_a[5..5]); + ram_block1a[574].portadatain[] = ( data_a[6..6]); + ram_block1a[575].portadatain[] = ( data_a[7..7]); + ram_block1a[576].portadatain[] = ( data_a[0..0]); + ram_block1a[577].portadatain[] = ( data_a[1..1]); + ram_block1a[578].portadatain[] = ( data_a[2..2]); + ram_block1a[579].portadatain[] = ( data_a[3..3]); + ram_block1a[580].portadatain[] = ( data_a[4..4]); + ram_block1a[581].portadatain[] = ( data_a[5..5]); + ram_block1a[582].portadatain[] = ( data_a[6..6]); + ram_block1a[583].portadatain[] = ( data_a[7..7]); + ram_block1a[584].portadatain[] = ( data_a[0..0]); + ram_block1a[585].portadatain[] = ( data_a[1..1]); + ram_block1a[586].portadatain[] = ( data_a[2..2]); + ram_block1a[587].portadatain[] = ( data_a[3..3]); + ram_block1a[588].portadatain[] = ( data_a[4..4]); + ram_block1a[589].portadatain[] = ( data_a[5..5]); + ram_block1a[590].portadatain[] = ( data_a[6..6]); + ram_block1a[591].portadatain[] = ( data_a[7..7]); + ram_block1a[592].portadatain[] = ( data_a[0..0]); + ram_block1a[593].portadatain[] = ( data_a[1..1]); + ram_block1a[594].portadatain[] = ( data_a[2..2]); + ram_block1a[595].portadatain[] = ( data_a[3..3]); + ram_block1a[596].portadatain[] = ( data_a[4..4]); + ram_block1a[597].portadatain[] = ( data_a[5..5]); + ram_block1a[598].portadatain[] = ( data_a[6..6]); + ram_block1a[599].portadatain[] = ( data_a[7..7]); + ram_block1a[600].portadatain[] = ( data_a[0..0]); + ram_block1a[601].portadatain[] = ( data_a[1..1]); + ram_block1a[602].portadatain[] = ( data_a[2..2]); + ram_block1a[603].portadatain[] = ( data_a[3..3]); + ram_block1a[604].portadatain[] = ( data_a[4..4]); + ram_block1a[605].portadatain[] = ( data_a[5..5]); + ram_block1a[606].portadatain[] = ( data_a[6..6]); + ram_block1a[607].portadatain[] = ( data_a[7..7]); + ram_block1a[608].portadatain[] = ( data_a[0..0]); + ram_block1a[609].portadatain[] = ( data_a[1..1]); + ram_block1a[610].portadatain[] = ( data_a[2..2]); + ram_block1a[611].portadatain[] = ( data_a[3..3]); + ram_block1a[612].portadatain[] = ( data_a[4..4]); + ram_block1a[613].portadatain[] = ( data_a[5..5]); + ram_block1a[614].portadatain[] = ( data_a[6..6]); + ram_block1a[615].portadatain[] = ( data_a[7..7]); + ram_block1a[616].portadatain[] = ( data_a[0..0]); + ram_block1a[617].portadatain[] = ( data_a[1..1]); + ram_block1a[618].portadatain[] = ( data_a[2..2]); + ram_block1a[619].portadatain[] = ( data_a[3..3]); + ram_block1a[620].portadatain[] = ( data_a[4..4]); + ram_block1a[621].portadatain[] = ( data_a[5..5]); + ram_block1a[622].portadatain[] = ( data_a[6..6]); + ram_block1a[623].portadatain[] = ( data_a[7..7]); + ram_block1a[624].portadatain[] = ( data_a[0..0]); + ram_block1a[625].portadatain[] = ( data_a[1..1]); + ram_block1a[626].portadatain[] = ( data_a[2..2]); + ram_block1a[627].portadatain[] = ( data_a[3..3]); + ram_block1a[628].portadatain[] = ( data_a[4..4]); + ram_block1a[629].portadatain[] = ( data_a[5..5]); + ram_block1a[630].portadatain[] = ( data_a[6..6]); + ram_block1a[631].portadatain[] = ( data_a[7..7]); + ram_block1a[632].portadatain[] = ( data_a[0..0]); + ram_block1a[633].portadatain[] = ( data_a[1..1]); + ram_block1a[634].portadatain[] = ( data_a[2..2]); + ram_block1a[635].portadatain[] = ( data_a[3..3]); + ram_block1a[636].portadatain[] = ( data_a[4..4]); + ram_block1a[637].portadatain[] = ( data_a[5..5]); + ram_block1a[638].portadatain[] = ( data_a[6..6]); + ram_block1a[639].portadatain[] = ( data_a[7..7]); + ram_block1a[640].portadatain[] = ( data_a[0..0]); + ram_block1a[641].portadatain[] = ( data_a[1..1]); + ram_block1a[642].portadatain[] = ( data_a[2..2]); + ram_block1a[643].portadatain[] = ( data_a[3..3]); + ram_block1a[644].portadatain[] = ( data_a[4..4]); + ram_block1a[645].portadatain[] = ( data_a[5..5]); + ram_block1a[646].portadatain[] = ( data_a[6..6]); + ram_block1a[647].portadatain[] = ( data_a[7..7]); + ram_block1a[648].portadatain[] = ( data_a[0..0]); + ram_block1a[649].portadatain[] = ( data_a[1..1]); + ram_block1a[650].portadatain[] = ( data_a[2..2]); + ram_block1a[651].portadatain[] = ( data_a[3..3]); + ram_block1a[652].portadatain[] = ( data_a[4..4]); + ram_block1a[653].portadatain[] = ( data_a[5..5]); + ram_block1a[654].portadatain[] = ( data_a[6..6]); + ram_block1a[655].portadatain[] = ( data_a[7..7]); + ram_block1a[656].portadatain[] = ( data_a[0..0]); + ram_block1a[657].portadatain[] = ( data_a[1..1]); + ram_block1a[658].portadatain[] = ( data_a[2..2]); + ram_block1a[659].portadatain[] = ( data_a[3..3]); + ram_block1a[660].portadatain[] = ( data_a[4..4]); + ram_block1a[661].portadatain[] = ( data_a[5..5]); + ram_block1a[662].portadatain[] = ( data_a[6..6]); + ram_block1a[663].portadatain[] = ( data_a[7..7]); + ram_block1a[664].portadatain[] = ( data_a[0..0]); + ram_block1a[665].portadatain[] = ( data_a[1..1]); + ram_block1a[666].portadatain[] = ( data_a[2..2]); + ram_block1a[667].portadatain[] = ( data_a[3..3]); + ram_block1a[668].portadatain[] = ( data_a[4..4]); + ram_block1a[669].portadatain[] = ( data_a[5..5]); + ram_block1a[670].portadatain[] = ( data_a[6..6]); + ram_block1a[671].portadatain[] = ( data_a[7..7]); + ram_block1a[672].portadatain[] = ( data_a[0..0]); + ram_block1a[673].portadatain[] = ( data_a[1..1]); + ram_block1a[674].portadatain[] = ( data_a[2..2]); + ram_block1a[675].portadatain[] = ( data_a[3..3]); + ram_block1a[676].portadatain[] = ( data_a[4..4]); + ram_block1a[677].portadatain[] = ( data_a[5..5]); + ram_block1a[678].portadatain[] = ( data_a[6..6]); + ram_block1a[679].portadatain[] = ( data_a[7..7]); + ram_block1a[680].portadatain[] = ( data_a[0..0]); + ram_block1a[681].portadatain[] = ( data_a[1..1]); + ram_block1a[682].portadatain[] = ( data_a[2..2]); + ram_block1a[683].portadatain[] = ( data_a[3..3]); + ram_block1a[684].portadatain[] = ( data_a[4..4]); + ram_block1a[685].portadatain[] = ( data_a[5..5]); + ram_block1a[686].portadatain[] = ( data_a[6..6]); + ram_block1a[687].portadatain[] = ( data_a[7..7]); + ram_block1a[688].portadatain[] = ( data_a[0..0]); + ram_block1a[689].portadatain[] = ( data_a[1..1]); + ram_block1a[690].portadatain[] = ( data_a[2..2]); + ram_block1a[691].portadatain[] = ( data_a[3..3]); + ram_block1a[692].portadatain[] = ( data_a[4..4]); + ram_block1a[693].portadatain[] = ( data_a[5..5]); + ram_block1a[694].portadatain[] = ( data_a[6..6]); + ram_block1a[695].portadatain[] = ( data_a[7..7]); + ram_block1a[696].portadatain[] = ( data_a[0..0]); + ram_block1a[697].portadatain[] = ( data_a[1..1]); + ram_block1a[698].portadatain[] = ( data_a[2..2]); + ram_block1a[699].portadatain[] = ( data_a[3..3]); + ram_block1a[700].portadatain[] = ( data_a[4..4]); + ram_block1a[701].portadatain[] = ( data_a[5..5]); + ram_block1a[702].portadatain[] = ( data_a[6..6]); + ram_block1a[703].portadatain[] = ( data_a[7..7]); + ram_block1a[704].portadatain[] = ( data_a[0..0]); + ram_block1a[705].portadatain[] = ( data_a[1..1]); + ram_block1a[706].portadatain[] = ( data_a[2..2]); + ram_block1a[707].portadatain[] = ( data_a[3..3]); + ram_block1a[708].portadatain[] = ( data_a[4..4]); + ram_block1a[709].portadatain[] = ( data_a[5..5]); + ram_block1a[710].portadatain[] = ( data_a[6..6]); + ram_block1a[711].portadatain[] = ( data_a[7..7]); + ram_block1a[712].portadatain[] = ( data_a[0..0]); + ram_block1a[713].portadatain[] = ( data_a[1..1]); + ram_block1a[714].portadatain[] = ( data_a[2..2]); + ram_block1a[715].portadatain[] = ( data_a[3..3]); + ram_block1a[716].portadatain[] = ( data_a[4..4]); + ram_block1a[717].portadatain[] = ( data_a[5..5]); + ram_block1a[718].portadatain[] = ( data_a[6..6]); + ram_block1a[719].portadatain[] = ( data_a[7..7]); + ram_block1a[720].portadatain[] = ( data_a[0..0]); + ram_block1a[721].portadatain[] = ( data_a[1..1]); + ram_block1a[722].portadatain[] = ( data_a[2..2]); + ram_block1a[723].portadatain[] = ( data_a[3..3]); + ram_block1a[724].portadatain[] = ( data_a[4..4]); + ram_block1a[725].portadatain[] = ( data_a[5..5]); + ram_block1a[726].portadatain[] = ( data_a[6..6]); + ram_block1a[727].portadatain[] = ( data_a[7..7]); + ram_block1a[728].portadatain[] = ( data_a[0..0]); + ram_block1a[729].portadatain[] = ( data_a[1..1]); + ram_block1a[730].portadatain[] = ( data_a[2..2]); + ram_block1a[731].portadatain[] = ( data_a[3..3]); + ram_block1a[732].portadatain[] = ( data_a[4..4]); + ram_block1a[733].portadatain[] = ( data_a[5..5]); + ram_block1a[734].portadatain[] = ( data_a[6..6]); + ram_block1a[735].portadatain[] = ( data_a[7..7]); + ram_block1a[736].portadatain[] = ( data_a[0..0]); + ram_block1a[737].portadatain[] = ( data_a[1..1]); + ram_block1a[738].portadatain[] = ( data_a[2..2]); + ram_block1a[739].portadatain[] = ( data_a[3..3]); + ram_block1a[740].portadatain[] = ( data_a[4..4]); + ram_block1a[741].portadatain[] = ( data_a[5..5]); + ram_block1a[742].portadatain[] = ( data_a[6..6]); + ram_block1a[743].portadatain[] = ( data_a[7..7]); + ram_block1a[744].portadatain[] = ( data_a[0..0]); + ram_block1a[745].portadatain[] = ( data_a[1..1]); + ram_block1a[746].portadatain[] = ( data_a[2..2]); + ram_block1a[747].portadatain[] = ( data_a[3..3]); + ram_block1a[748].portadatain[] = ( data_a[4..4]); + ram_block1a[749].portadatain[] = ( data_a[5..5]); + ram_block1a[750].portadatain[] = ( data_a[6..6]); + ram_block1a[751].portadatain[] = ( data_a[7..7]); + ram_block1a[752].portadatain[] = ( data_a[0..0]); + ram_block1a[753].portadatain[] = ( data_a[1..1]); + ram_block1a[754].portadatain[] = ( data_a[2..2]); + ram_block1a[755].portadatain[] = ( data_a[3..3]); + ram_block1a[756].portadatain[] = ( data_a[4..4]); + ram_block1a[757].portadatain[] = ( data_a[5..5]); + ram_block1a[758].portadatain[] = ( data_a[6..6]); + ram_block1a[759].portadatain[] = ( data_a[7..7]); + ram_block1a[760].portadatain[] = ( data_a[0..0]); + ram_block1a[761].portadatain[] = ( data_a[1..1]); + ram_block1a[762].portadatain[] = ( data_a[2..2]); + ram_block1a[763].portadatain[] = ( data_a[3..3]); + ram_block1a[764].portadatain[] = ( data_a[4..4]); + ram_block1a[765].portadatain[] = ( data_a[5..5]); + ram_block1a[766].portadatain[] = ( data_a[6..6]); + ram_block1a[767].portadatain[] = ( data_a[7..7]); + ram_block1a[768].portadatain[] = ( data_a[0..0]); + ram_block1a[769].portadatain[] = ( data_a[1..1]); + ram_block1a[770].portadatain[] = ( data_a[2..2]); + ram_block1a[771].portadatain[] = ( data_a[3..3]); + ram_block1a[772].portadatain[] = ( data_a[4..4]); + ram_block1a[773].portadatain[] = ( data_a[5..5]); + ram_block1a[774].portadatain[] = ( data_a[6..6]); + ram_block1a[775].portadatain[] = ( data_a[7..7]); + ram_block1a[776].portadatain[] = ( data_a[0..0]); + ram_block1a[777].portadatain[] = ( data_a[1..1]); + ram_block1a[778].portadatain[] = ( data_a[2..2]); + ram_block1a[779].portadatain[] = ( data_a[3..3]); + ram_block1a[780].portadatain[] = ( data_a[4..4]); + ram_block1a[781].portadatain[] = ( data_a[5..5]); + ram_block1a[782].portadatain[] = ( data_a[6..6]); + ram_block1a[783].portadatain[] = ( data_a[7..7]); + ram_block1a[784].portadatain[] = ( data_a[0..0]); + ram_block1a[785].portadatain[] = ( data_a[1..1]); + ram_block1a[786].portadatain[] = ( data_a[2..2]); + ram_block1a[787].portadatain[] = ( data_a[3..3]); + ram_block1a[788].portadatain[] = ( data_a[4..4]); + ram_block1a[789].portadatain[] = ( data_a[5..5]); + ram_block1a[790].portadatain[] = ( data_a[6..6]); + ram_block1a[791].portadatain[] = ( data_a[7..7]); + ram_block1a[792].portadatain[] = ( data_a[0..0]); + ram_block1a[793].portadatain[] = ( data_a[1..1]); + ram_block1a[794].portadatain[] = ( data_a[2..2]); + ram_block1a[795].portadatain[] = ( data_a[3..3]); + ram_block1a[796].portadatain[] = ( data_a[4..4]); + ram_block1a[797].portadatain[] = ( data_a[5..5]); + ram_block1a[798].portadatain[] = ( data_a[6..6]); + ram_block1a[799].portadatain[] = ( data_a[7..7]); + ram_block1a[800].portadatain[] = ( data_a[0..0]); + ram_block1a[801].portadatain[] = ( data_a[1..1]); + ram_block1a[802].portadatain[] = ( data_a[2..2]); + ram_block1a[803].portadatain[] = ( data_a[3..3]); + ram_block1a[804].portadatain[] = ( data_a[4..4]); + ram_block1a[805].portadatain[] = ( data_a[5..5]); + ram_block1a[806].portadatain[] = ( data_a[6..6]); + ram_block1a[807].portadatain[] = ( data_a[7..7]); + ram_block1a[808].portadatain[] = ( data_a[0..0]); + ram_block1a[809].portadatain[] = ( data_a[1..1]); + ram_block1a[810].portadatain[] = ( data_a[2..2]); + ram_block1a[811].portadatain[] = ( data_a[3..3]); + ram_block1a[812].portadatain[] = ( data_a[4..4]); + ram_block1a[813].portadatain[] = ( data_a[5..5]); + ram_block1a[814].portadatain[] = ( data_a[6..6]); + ram_block1a[815].portadatain[] = ( data_a[7..7]); + ram_block1a[816].portadatain[] = ( data_a[0..0]); + ram_block1a[817].portadatain[] = ( data_a[1..1]); + ram_block1a[818].portadatain[] = ( data_a[2..2]); + ram_block1a[819].portadatain[] = ( data_a[3..3]); + ram_block1a[820].portadatain[] = ( data_a[4..4]); + ram_block1a[821].portadatain[] = ( data_a[5..5]); + ram_block1a[822].portadatain[] = ( data_a[6..6]); + ram_block1a[823].portadatain[] = ( data_a[7..7]); + ram_block1a[824].portadatain[] = ( data_a[0..0]); + ram_block1a[825].portadatain[] = ( data_a[1..1]); + ram_block1a[826].portadatain[] = ( data_a[2..2]); + ram_block1a[827].portadatain[] = ( data_a[3..3]); + ram_block1a[828].portadatain[] = ( data_a[4..4]); + ram_block1a[829].portadatain[] = ( data_a[5..5]); + ram_block1a[830].portadatain[] = ( data_a[6..6]); + ram_block1a[831].portadatain[] = ( data_a[7..7]); + ram_block1a[832].portadatain[] = ( data_a[0..0]); + ram_block1a[833].portadatain[] = ( data_a[1..1]); + ram_block1a[834].portadatain[] = ( data_a[2..2]); + ram_block1a[835].portadatain[] = ( data_a[3..3]); + ram_block1a[836].portadatain[] = ( data_a[4..4]); + ram_block1a[837].portadatain[] = ( data_a[5..5]); + ram_block1a[838].portadatain[] = ( data_a[6..6]); + ram_block1a[839].portadatain[] = ( data_a[7..7]); + ram_block1a[840].portadatain[] = ( data_a[0..0]); + ram_block1a[841].portadatain[] = ( data_a[1..1]); + ram_block1a[842].portadatain[] = ( data_a[2..2]); + ram_block1a[843].portadatain[] = ( data_a[3..3]); + ram_block1a[844].portadatain[] = ( data_a[4..4]); + ram_block1a[845].portadatain[] = ( data_a[5..5]); + ram_block1a[846].portadatain[] = ( data_a[6..6]); + ram_block1a[847].portadatain[] = ( data_a[7..7]); + ram_block1a[848].portadatain[] = ( data_a[0..0]); + ram_block1a[849].portadatain[] = ( data_a[1..1]); + ram_block1a[850].portadatain[] = ( data_a[2..2]); + ram_block1a[851].portadatain[] = ( data_a[3..3]); + ram_block1a[852].portadatain[] = ( data_a[4..4]); + ram_block1a[853].portadatain[] = ( data_a[5..5]); + ram_block1a[854].portadatain[] = ( data_a[6..6]); + ram_block1a[855].portadatain[] = ( data_a[7..7]); + ram_block1a[856].portadatain[] = ( data_a[0..0]); + ram_block1a[857].portadatain[] = ( data_a[1..1]); + ram_block1a[858].portadatain[] = ( data_a[2..2]); + ram_block1a[859].portadatain[] = ( data_a[3..3]); + ram_block1a[860].portadatain[] = ( data_a[4..4]); + ram_block1a[861].portadatain[] = ( data_a[5..5]); + ram_block1a[862].portadatain[] = ( data_a[6..6]); + ram_block1a[863].portadatain[] = ( data_a[7..7]); + ram_block1a[864].portadatain[] = ( data_a[0..0]); + ram_block1a[865].portadatain[] = ( data_a[1..1]); + ram_block1a[866].portadatain[] = ( data_a[2..2]); + ram_block1a[867].portadatain[] = ( data_a[3..3]); + ram_block1a[868].portadatain[] = ( data_a[4..4]); + ram_block1a[869].portadatain[] = ( data_a[5..5]); + ram_block1a[870].portadatain[] = ( data_a[6..6]); + ram_block1a[871].portadatain[] = ( data_a[7..7]); + ram_block1a[872].portadatain[] = ( data_a[0..0]); + ram_block1a[873].portadatain[] = ( data_a[1..1]); + ram_block1a[874].portadatain[] = ( data_a[2..2]); + ram_block1a[875].portadatain[] = ( data_a[3..3]); + ram_block1a[876].portadatain[] = ( data_a[4..4]); + ram_block1a[877].portadatain[] = ( data_a[5..5]); + ram_block1a[878].portadatain[] = ( data_a[6..6]); + ram_block1a[879].portadatain[] = ( data_a[7..7]); + ram_block1a[880].portadatain[] = ( data_a[0..0]); + ram_block1a[881].portadatain[] = ( data_a[1..1]); + ram_block1a[882].portadatain[] = ( data_a[2..2]); + ram_block1a[883].portadatain[] = ( data_a[3..3]); + ram_block1a[884].portadatain[] = ( data_a[4..4]); + ram_block1a[885].portadatain[] = ( data_a[5..5]); + ram_block1a[886].portadatain[] = ( data_a[6..6]); + ram_block1a[887].portadatain[] = ( data_a[7..7]); + ram_block1a[888].portadatain[] = ( data_a[0..0]); + ram_block1a[889].portadatain[] = ( data_a[1..1]); + ram_block1a[890].portadatain[] = ( data_a[2..2]); + ram_block1a[891].portadatain[] = ( data_a[3..3]); + ram_block1a[892].portadatain[] = ( data_a[4..4]); + ram_block1a[893].portadatain[] = ( data_a[5..5]); + ram_block1a[894].portadatain[] = ( data_a[6..6]); + ram_block1a[895].portadatain[] = ( data_a[7..7]); + ram_block1a[896].portadatain[] = ( data_a[0..0]); + ram_block1a[897].portadatain[] = ( data_a[1..1]); + ram_block1a[898].portadatain[] = ( data_a[2..2]); + ram_block1a[899].portadatain[] = ( data_a[3..3]); + ram_block1a[900].portadatain[] = ( data_a[4..4]); + ram_block1a[901].portadatain[] = ( data_a[5..5]); + ram_block1a[902].portadatain[] = ( data_a[6..6]); + ram_block1a[903].portadatain[] = ( data_a[7..7]); + ram_block1a[904].portadatain[] = ( data_a[0..0]); + ram_block1a[905].portadatain[] = ( data_a[1..1]); + ram_block1a[906].portadatain[] = ( data_a[2..2]); + ram_block1a[907].portadatain[] = ( data_a[3..3]); + ram_block1a[908].portadatain[] = ( data_a[4..4]); + ram_block1a[909].portadatain[] = ( data_a[5..5]); + ram_block1a[910].portadatain[] = ( data_a[6..6]); + ram_block1a[911].portadatain[] = ( data_a[7..7]); + ram_block1a[912].portadatain[] = ( data_a[0..0]); + ram_block1a[913].portadatain[] = ( data_a[1..1]); + ram_block1a[914].portadatain[] = ( data_a[2..2]); + ram_block1a[915].portadatain[] = ( data_a[3..3]); + ram_block1a[916].portadatain[] = ( data_a[4..4]); + ram_block1a[917].portadatain[] = ( data_a[5..5]); + ram_block1a[918].portadatain[] = ( data_a[6..6]); + ram_block1a[919].portadatain[] = ( data_a[7..7]); + ram_block1a[920].portadatain[] = ( data_a[0..0]); + ram_block1a[921].portadatain[] = ( data_a[1..1]); + ram_block1a[922].portadatain[] = ( data_a[2..2]); + ram_block1a[923].portadatain[] = ( data_a[3..3]); + ram_block1a[924].portadatain[] = ( data_a[4..4]); + ram_block1a[925].portadatain[] = ( data_a[5..5]); + ram_block1a[926].portadatain[] = ( data_a[6..6]); + ram_block1a[927].portadatain[] = ( data_a[7..7]); + ram_block1a[928].portadatain[] = ( data_a[0..0]); + ram_block1a[929].portadatain[] = ( data_a[1..1]); + ram_block1a[930].portadatain[] = ( data_a[2..2]); + ram_block1a[931].portadatain[] = ( data_a[3..3]); + ram_block1a[932].portadatain[] = ( data_a[4..4]); + ram_block1a[933].portadatain[] = ( data_a[5..5]); + ram_block1a[934].portadatain[] = ( data_a[6..6]); + ram_block1a[935].portadatain[] = ( data_a[7..7]); + ram_block1a[936].portadatain[] = ( data_a[0..0]); + ram_block1a[937].portadatain[] = ( data_a[1..1]); + ram_block1a[938].portadatain[] = ( data_a[2..2]); + ram_block1a[939].portadatain[] = ( data_a[3..3]); + ram_block1a[940].portadatain[] = ( data_a[4..4]); + ram_block1a[941].portadatain[] = ( data_a[5..5]); + ram_block1a[942].portadatain[] = ( data_a[6..6]); + ram_block1a[943].portadatain[] = ( data_a[7..7]); + ram_block1a[944].portadatain[] = ( data_a[0..0]); + ram_block1a[945].portadatain[] = ( data_a[1..1]); + ram_block1a[946].portadatain[] = ( data_a[2..2]); + ram_block1a[947].portadatain[] = ( data_a[3..3]); + ram_block1a[948].portadatain[] = ( data_a[4..4]); + ram_block1a[949].portadatain[] = ( data_a[5..5]); + ram_block1a[950].portadatain[] = ( data_a[6..6]); + ram_block1a[951].portadatain[] = ( data_a[7..7]); + ram_block1a[952].portadatain[] = ( data_a[0..0]); + ram_block1a[953].portadatain[] = ( data_a[1..1]); + ram_block1a[954].portadatain[] = ( data_a[2..2]); + ram_block1a[955].portadatain[] = ( data_a[3..3]); + ram_block1a[956].portadatain[] = ( data_a[4..4]); + ram_block1a[957].portadatain[] = ( data_a[5..5]); + ram_block1a[958].portadatain[] = ( data_a[6..6]); + ram_block1a[959].portadatain[] = ( data_a[7..7]); + ram_block1a[960].portadatain[] = ( data_a[0..0]); + ram_block1a[961].portadatain[] = ( data_a[1..1]); + ram_block1a[962].portadatain[] = ( data_a[2..2]); + ram_block1a[963].portadatain[] = ( data_a[3..3]); + ram_block1a[964].portadatain[] = ( data_a[4..4]); + ram_block1a[965].portadatain[] = ( data_a[5..5]); + ram_block1a[966].portadatain[] = ( data_a[6..6]); + ram_block1a[967].portadatain[] = ( data_a[7..7]); + ram_block1a[968].portadatain[] = ( data_a[0..0]); + ram_block1a[969].portadatain[] = ( data_a[1..1]); + ram_block1a[970].portadatain[] = ( data_a[2..2]); + ram_block1a[971].portadatain[] = ( data_a[3..3]); + ram_block1a[972].portadatain[] = ( data_a[4..4]); + ram_block1a[973].portadatain[] = ( data_a[5..5]); + ram_block1a[974].portadatain[] = ( data_a[6..6]); + ram_block1a[975].portadatain[] = ( data_a[7..7]); + ram_block1a[976].portadatain[] = ( data_a[0..0]); + ram_block1a[977].portadatain[] = ( data_a[1..1]); + ram_block1a[978].portadatain[] = ( data_a[2..2]); + ram_block1a[979].portadatain[] = ( data_a[3..3]); + ram_block1a[980].portadatain[] = ( data_a[4..4]); + ram_block1a[981].portadatain[] = ( data_a[5..5]); + ram_block1a[982].portadatain[] = ( data_a[6..6]); + ram_block1a[983].portadatain[] = ( data_a[7..7]); + ram_block1a[984].portadatain[] = ( data_a[0..0]); + ram_block1a[985].portadatain[] = ( data_a[1..1]); + ram_block1a[986].portadatain[] = ( data_a[2..2]); + ram_block1a[987].portadatain[] = ( data_a[3..3]); + ram_block1a[988].portadatain[] = ( data_a[4..4]); + ram_block1a[989].portadatain[] = ( data_a[5..5]); + ram_block1a[990].portadatain[] = ( data_a[6..6]); + ram_block1a[991].portadatain[] = ( data_a[7..7]); + ram_block1a[992].portadatain[] = ( data_a[0..0]); + ram_block1a[993].portadatain[] = ( data_a[1..1]); + ram_block1a[994].portadatain[] = ( data_a[2..2]); + ram_block1a[995].portadatain[] = ( data_a[3..3]); + ram_block1a[996].portadatain[] = ( data_a[4..4]); + ram_block1a[997].portadatain[] = ( data_a[5..5]); + ram_block1a[998].portadatain[] = ( data_a[6..6]); + ram_block1a[999].portadatain[] = ( data_a[7..7]); + ram_block1a[1000].portadatain[] = ( data_a[0..0]); + ram_block1a[1001].portadatain[] = ( data_a[1..1]); + ram_block1a[1002].portadatain[] = ( data_a[2..2]); + ram_block1a[1003].portadatain[] = ( data_a[3..3]); + ram_block1a[1004].portadatain[] = ( data_a[4..4]); + ram_block1a[1005].portadatain[] = ( data_a[5..5]); + ram_block1a[1006].portadatain[] = ( data_a[6..6]); + ram_block1a[1007].portadatain[] = ( data_a[7..7]); + ram_block1a[1008].portadatain[] = ( data_a[0..0]); + ram_block1a[1009].portadatain[] = ( data_a[1..1]); + ram_block1a[1010].portadatain[] = ( data_a[2..2]); + ram_block1a[1011].portadatain[] = ( data_a[3..3]); + ram_block1a[1012].portadatain[] = ( data_a[4..4]); + ram_block1a[1013].portadatain[] = ( data_a[5..5]); + ram_block1a[1014].portadatain[] = ( data_a[6..6]); + ram_block1a[1015].portadatain[] = ( data_a[7..7]); + ram_block1a[1016].portadatain[] = ( data_a[0..0]); + ram_block1a[1017].portadatain[] = ( data_a[1..1]); + ram_block1a[1018].portadatain[] = ( data_a[2..2]); + ram_block1a[1019].portadatain[] = ( data_a[3..3]); + ram_block1a[1020].portadatain[] = ( data_a[4..4]); + ram_block1a[1021].portadatain[] = ( data_a[5..5]); + ram_block1a[1022].portadatain[] = ( data_a[6..6]); + ram_block1a[1023].portadatain[] = ( data_a[7..7]); + ram_block1a[1024].portadatain[] = ( data_a[0..0]); + ram_block1a[1025].portadatain[] = ( data_a[1..1]); + ram_block1a[1026].portadatain[] = ( data_a[2..2]); + ram_block1a[1027].portadatain[] = ( data_a[3..3]); + ram_block1a[1028].portadatain[] = ( data_a[4..4]); + ram_block1a[1029].portadatain[] = ( data_a[5..5]); + ram_block1a[1030].portadatain[] = ( data_a[6..6]); + ram_block1a[1031].portadatain[] = ( data_a[7..7]); + ram_block1a[1032].portadatain[] = ( data_a[0..0]); + ram_block1a[1033].portadatain[] = ( data_a[1..1]); + ram_block1a[1034].portadatain[] = ( data_a[2..2]); + ram_block1a[1035].portadatain[] = ( data_a[3..3]); + ram_block1a[1036].portadatain[] = ( data_a[4..4]); + ram_block1a[1037].portadatain[] = ( data_a[5..5]); + ram_block1a[1038].portadatain[] = ( data_a[6..6]); + ram_block1a[1039].portadatain[] = ( data_a[7..7]); + ram_block1a[1040].portadatain[] = ( data_a[0..0]); + ram_block1a[1041].portadatain[] = ( data_a[1..1]); + ram_block1a[1042].portadatain[] = ( data_a[2..2]); + ram_block1a[1043].portadatain[] = ( data_a[3..3]); + ram_block1a[1044].portadatain[] = ( data_a[4..4]); + ram_block1a[1045].portadatain[] = ( data_a[5..5]); + ram_block1a[1046].portadatain[] = ( data_a[6..6]); + ram_block1a[1047].portadatain[] = ( data_a[7..7]); + ram_block1a[1048].portadatain[] = ( data_a[0..0]); + ram_block1a[1049].portadatain[] = ( data_a[1..1]); + ram_block1a[1050].portadatain[] = ( data_a[2..2]); + ram_block1a[1051].portadatain[] = ( data_a[3..3]); + ram_block1a[1052].portadatain[] = ( data_a[4..4]); + ram_block1a[1053].portadatain[] = ( data_a[5..5]); + ram_block1a[1054].portadatain[] = ( data_a[6..6]); + ram_block1a[1055].portadatain[] = ( data_a[7..7]); + ram_block1a[1056].portadatain[] = ( data_a[0..0]); + ram_block1a[1057].portadatain[] = ( data_a[1..1]); + ram_block1a[1058].portadatain[] = ( data_a[2..2]); + ram_block1a[1059].portadatain[] = ( data_a[3..3]); + ram_block1a[1060].portadatain[] = ( data_a[4..4]); + ram_block1a[1061].portadatain[] = ( data_a[5..5]); + ram_block1a[1062].portadatain[] = ( data_a[6..6]); + ram_block1a[1063].portadatain[] = ( data_a[7..7]); + ram_block1a[1064].portadatain[] = ( data_a[0..0]); + ram_block1a[1065].portadatain[] = ( data_a[1..1]); + ram_block1a[1066].portadatain[] = ( data_a[2..2]); + ram_block1a[1067].portadatain[] = ( data_a[3..3]); + ram_block1a[1068].portadatain[] = ( data_a[4..4]); + ram_block1a[1069].portadatain[] = ( data_a[5..5]); + ram_block1a[1070].portadatain[] = ( data_a[6..6]); + ram_block1a[1071].portadatain[] = ( data_a[7..7]); + ram_block1a[1072].portadatain[] = ( data_a[0..0]); + ram_block1a[1073].portadatain[] = ( data_a[1..1]); + ram_block1a[1074].portadatain[] = ( data_a[2..2]); + ram_block1a[1075].portadatain[] = ( data_a[3..3]); + ram_block1a[1076].portadatain[] = ( data_a[4..4]); + ram_block1a[1077].portadatain[] = ( data_a[5..5]); + ram_block1a[1078].portadatain[] = ( data_a[6..6]); + ram_block1a[1079].portadatain[] = ( data_a[7..7]); + ram_block1a[1080].portadatain[] = ( data_a[0..0]); + ram_block1a[1081].portadatain[] = ( data_a[1..1]); + ram_block1a[1082].portadatain[] = ( data_a[2..2]); + ram_block1a[1083].portadatain[] = ( data_a[3..3]); + ram_block1a[1084].portadatain[] = ( data_a[4..4]); + ram_block1a[1085].portadatain[] = ( data_a[5..5]); + ram_block1a[1086].portadatain[] = ( data_a[6..6]); + ram_block1a[1087].portadatain[] = ( data_a[7..7]); + ram_block1a[1088].portadatain[] = ( data_a[0..0]); + ram_block1a[1089].portadatain[] = ( data_a[1..1]); + ram_block1a[1090].portadatain[] = ( data_a[2..2]); + ram_block1a[1091].portadatain[] = ( data_a[3..3]); + ram_block1a[1092].portadatain[] = ( data_a[4..4]); + ram_block1a[1093].portadatain[] = ( data_a[5..5]); + ram_block1a[1094].portadatain[] = ( data_a[6..6]); + ram_block1a[1095].portadatain[] = ( data_a[7..7]); + ram_block1a[1096].portadatain[] = ( data_a[0..0]); + ram_block1a[1097].portadatain[] = ( data_a[1..1]); + ram_block1a[1098].portadatain[] = ( data_a[2..2]); + ram_block1a[1099].portadatain[] = ( data_a[3..3]); + ram_block1a[1100].portadatain[] = ( data_a[4..4]); + ram_block1a[1101].portadatain[] = ( data_a[5..5]); + ram_block1a[1102].portadatain[] = ( data_a[6..6]); + ram_block1a[1103].portadatain[] = ( data_a[7..7]); + ram_block1a[1104].portadatain[] = ( data_a[0..0]); + ram_block1a[1105].portadatain[] = ( data_a[1..1]); + ram_block1a[1106].portadatain[] = ( data_a[2..2]); + ram_block1a[1107].portadatain[] = ( data_a[3..3]); + ram_block1a[1108].portadatain[] = ( data_a[4..4]); + ram_block1a[1109].portadatain[] = ( data_a[5..5]); + ram_block1a[1110].portadatain[] = ( data_a[6..6]); + ram_block1a[1111].portadatain[] = ( data_a[7..7]); + ram_block1a[1112].portadatain[] = ( data_a[0..0]); + ram_block1a[1113].portadatain[] = ( data_a[1..1]); + ram_block1a[1114].portadatain[] = ( data_a[2..2]); + ram_block1a[1115].portadatain[] = ( data_a[3..3]); + ram_block1a[1116].portadatain[] = ( data_a[4..4]); + ram_block1a[1117].portadatain[] = ( data_a[5..5]); + ram_block1a[1118].portadatain[] = ( data_a[6..6]); + ram_block1a[1119].portadatain[] = ( data_a[7..7]); + ram_block1a[1120].portadatain[] = ( data_a[0..0]); + ram_block1a[1121].portadatain[] = ( data_a[1..1]); + ram_block1a[1122].portadatain[] = ( data_a[2..2]); + ram_block1a[1123].portadatain[] = ( data_a[3..3]); + ram_block1a[1124].portadatain[] = ( data_a[4..4]); + ram_block1a[1125].portadatain[] = ( data_a[5..5]); + ram_block1a[1126].portadatain[] = ( data_a[6..6]); + ram_block1a[1127].portadatain[] = ( data_a[7..7]); + ram_block1a[1128].portadatain[] = ( data_a[0..0]); + ram_block1a[1129].portadatain[] = ( data_a[1..1]); + ram_block1a[1130].portadatain[] = ( data_a[2..2]); + ram_block1a[1131].portadatain[] = ( data_a[3..3]); + ram_block1a[1132].portadatain[] = ( data_a[4..4]); + ram_block1a[1133].portadatain[] = ( data_a[5..5]); + ram_block1a[1134].portadatain[] = ( data_a[6..6]); + ram_block1a[1135].portadatain[] = ( data_a[7..7]); + ram_block1a[1136].portadatain[] = ( data_a[0..0]); + ram_block1a[1137].portadatain[] = ( data_a[1..1]); + ram_block1a[1138].portadatain[] = ( data_a[2..2]); + ram_block1a[1139].portadatain[] = ( data_a[3..3]); + ram_block1a[1140].portadatain[] = ( data_a[4..4]); + ram_block1a[1141].portadatain[] = ( data_a[5..5]); + ram_block1a[1142].portadatain[] = ( data_a[6..6]); + ram_block1a[1143].portadatain[] = ( data_a[7..7]); + ram_block1a[1144].portadatain[] = ( data_a[0..0]); + ram_block1a[1145].portadatain[] = ( data_a[1..1]); + ram_block1a[1146].portadatain[] = ( data_a[2..2]); + ram_block1a[1147].portadatain[] = ( data_a[3..3]); + ram_block1a[1148].portadatain[] = ( data_a[4..4]); + ram_block1a[1149].portadatain[] = ( data_a[5..5]); + ram_block1a[1150].portadatain[] = ( data_a[6..6]); + ram_block1a[1151].portadatain[] = ( data_a[7..7]); + ram_block1a[1152].portadatain[] = ( data_a[0..0]); + ram_block1a[1153].portadatain[] = ( data_a[1..1]); + ram_block1a[1154].portadatain[] = ( data_a[2..2]); + ram_block1a[1155].portadatain[] = ( data_a[3..3]); + ram_block1a[1156].portadatain[] = ( data_a[4..4]); + ram_block1a[1157].portadatain[] = ( data_a[5..5]); + ram_block1a[1158].portadatain[] = ( data_a[6..6]); + ram_block1a[1159].portadatain[] = ( data_a[7..7]); + ram_block1a[1160].portadatain[] = ( data_a[0..0]); + ram_block1a[1161].portadatain[] = ( data_a[1..1]); + ram_block1a[1162].portadatain[] = ( data_a[2..2]); + ram_block1a[1163].portadatain[] = ( data_a[3..3]); + ram_block1a[1164].portadatain[] = ( data_a[4..4]); + ram_block1a[1165].portadatain[] = ( data_a[5..5]); + ram_block1a[1166].portadatain[] = ( data_a[6..6]); + ram_block1a[1167].portadatain[] = ( data_a[7..7]); + ram_block1a[1168].portadatain[] = ( data_a[0..0]); + ram_block1a[1169].portadatain[] = ( data_a[1..1]); + ram_block1a[1170].portadatain[] = ( data_a[2..2]); + ram_block1a[1171].portadatain[] = ( data_a[3..3]); + ram_block1a[1172].portadatain[] = ( data_a[4..4]); + ram_block1a[1173].portadatain[] = ( data_a[5..5]); + ram_block1a[1174].portadatain[] = ( data_a[6..6]); + ram_block1a[1175].portadatain[] = ( data_a[7..7]); + ram_block1a[1176].portadatain[] = ( data_a[0..0]); + ram_block1a[1177].portadatain[] = ( data_a[1..1]); + ram_block1a[1178].portadatain[] = ( data_a[2..2]); + ram_block1a[1179].portadatain[] = ( data_a[3..3]); + ram_block1a[1180].portadatain[] = ( data_a[4..4]); + ram_block1a[1181].portadatain[] = ( data_a[5..5]); + ram_block1a[1182].portadatain[] = ( data_a[6..6]); + ram_block1a[1183].portadatain[] = ( data_a[7..7]); + ram_block1a[1184].portadatain[] = ( data_a[0..0]); + ram_block1a[1185].portadatain[] = ( data_a[1..1]); + ram_block1a[1186].portadatain[] = ( data_a[2..2]); + ram_block1a[1187].portadatain[] = ( data_a[3..3]); + ram_block1a[1188].portadatain[] = ( data_a[4..4]); + ram_block1a[1189].portadatain[] = ( data_a[5..5]); + ram_block1a[1190].portadatain[] = ( data_a[6..6]); + ram_block1a[1191].portadatain[] = ( data_a[7..7]); + ram_block1a[1192].portadatain[] = ( data_a[0..0]); + ram_block1a[1193].portadatain[] = ( data_a[1..1]); + ram_block1a[1194].portadatain[] = ( data_a[2..2]); + ram_block1a[1195].portadatain[] = ( data_a[3..3]); + ram_block1a[1196].portadatain[] = ( data_a[4..4]); + ram_block1a[1197].portadatain[] = ( data_a[5..5]); + ram_block1a[1198].portadatain[] = ( data_a[6..6]); + ram_block1a[1199].portadatain[] = ( data_a[7..7]); + ram_block1a[1200].portadatain[] = ( data_a[0..0]); + ram_block1a[1201].portadatain[] = ( data_a[1..1]); + ram_block1a[1202].portadatain[] = ( data_a[2..2]); + ram_block1a[1203].portadatain[] = ( data_a[3..3]); + ram_block1a[1204].portadatain[] = ( data_a[4..4]); + ram_block1a[1205].portadatain[] = ( data_a[5..5]); + ram_block1a[1206].portadatain[] = ( data_a[6..6]); + ram_block1a[1207].portadatain[] = ( data_a[7..7]); + ram_block1a[1208].portadatain[] = ( data_a[0..0]); + ram_block1a[1209].portadatain[] = ( data_a[1..1]); + ram_block1a[1210].portadatain[] = ( data_a[2..2]); + ram_block1a[1211].portadatain[] = ( data_a[3..3]); + ram_block1a[1212].portadatain[] = ( data_a[4..4]); + ram_block1a[1213].portadatain[] = ( data_a[5..5]); + ram_block1a[1214].portadatain[] = ( data_a[6..6]); + ram_block1a[1215].portadatain[] = ( data_a[7..7]); + ram_block1a[1216].portadatain[] = ( data_a[0..0]); + ram_block1a[1217].portadatain[] = ( data_a[1..1]); + ram_block1a[1218].portadatain[] = ( data_a[2..2]); + ram_block1a[1219].portadatain[] = ( data_a[3..3]); + ram_block1a[1220].portadatain[] = ( data_a[4..4]); + ram_block1a[1221].portadatain[] = ( data_a[5..5]); + ram_block1a[1222].portadatain[] = ( data_a[6..6]); + ram_block1a[1223].portadatain[] = ( data_a[7..7]); + ram_block1a[1224].portadatain[] = ( data_a[0..0]); + ram_block1a[1225].portadatain[] = ( data_a[1..1]); + ram_block1a[1226].portadatain[] = ( data_a[2..2]); + ram_block1a[1227].portadatain[] = ( data_a[3..3]); + ram_block1a[1228].portadatain[] = ( data_a[4..4]); + ram_block1a[1229].portadatain[] = ( data_a[5..5]); + ram_block1a[1230].portadatain[] = ( data_a[6..6]); + ram_block1a[1231].portadatain[] = ( data_a[7..7]); + ram_block1a[1232].portadatain[] = ( data_a[0..0]); + ram_block1a[1233].portadatain[] = ( data_a[1..1]); + ram_block1a[1234].portadatain[] = ( data_a[2..2]); + ram_block1a[1235].portadatain[] = ( data_a[3..3]); + ram_block1a[1236].portadatain[] = ( data_a[4..4]); + ram_block1a[1237].portadatain[] = ( data_a[5..5]); + ram_block1a[1238].portadatain[] = ( data_a[6..6]); + ram_block1a[1239].portadatain[] = ( data_a[7..7]); + ram_block1a[1240].portadatain[] = ( data_a[0..0]); + ram_block1a[1241].portadatain[] = ( data_a[1..1]); + ram_block1a[1242].portadatain[] = ( data_a[2..2]); + ram_block1a[1243].portadatain[] = ( data_a[3..3]); + ram_block1a[1244].portadatain[] = ( data_a[4..4]); + ram_block1a[1245].portadatain[] = ( data_a[5..5]); + ram_block1a[1246].portadatain[] = ( data_a[6..6]); + ram_block1a[1247].portadatain[] = ( data_a[7..7]); + ram_block1a[1248].portadatain[] = ( data_a[0..0]); + ram_block1a[1249].portadatain[] = ( data_a[1..1]); + ram_block1a[1250].portadatain[] = ( data_a[2..2]); + ram_block1a[1251].portadatain[] = ( data_a[3..3]); + ram_block1a[1252].portadatain[] = ( data_a[4..4]); + ram_block1a[1253].portadatain[] = ( data_a[5..5]); + ram_block1a[1254].portadatain[] = ( data_a[6..6]); + ram_block1a[1255].portadatain[] = ( data_a[7..7]); + ram_block1a[1256].portadatain[] = ( data_a[0..0]); + ram_block1a[1257].portadatain[] = ( data_a[1..1]); + ram_block1a[1258].portadatain[] = ( data_a[2..2]); + ram_block1a[1259].portadatain[] = ( data_a[3..3]); + ram_block1a[1260].portadatain[] = ( data_a[4..4]); + ram_block1a[1261].portadatain[] = ( data_a[5..5]); + ram_block1a[1262].portadatain[] = ( data_a[6..6]); + ram_block1a[1263].portadatain[] = ( data_a[7..7]); + ram_block1a[1264].portadatain[] = ( data_a[0..0]); + ram_block1a[1265].portadatain[] = ( data_a[1..1]); + ram_block1a[1266].portadatain[] = ( data_a[2..2]); + ram_block1a[1267].portadatain[] = ( data_a[3..3]); + ram_block1a[1268].portadatain[] = ( data_a[4..4]); + ram_block1a[1269].portadatain[] = ( data_a[5..5]); + ram_block1a[1270].portadatain[] = ( data_a[6..6]); + ram_block1a[1271].portadatain[] = ( data_a[7..7]); + ram_block1a[1272].portadatain[] = ( data_a[0..0]); + ram_block1a[1273].portadatain[] = ( data_a[1..1]); + ram_block1a[1274].portadatain[] = ( data_a[2..2]); + ram_block1a[1275].portadatain[] = ( data_a[3..3]); + ram_block1a[1276].portadatain[] = ( data_a[4..4]); + ram_block1a[1277].portadatain[] = ( data_a[5..5]); + ram_block1a[1278].portadatain[] = ( data_a[6..6]); + ram_block1a[1279].portadatain[] = ( data_a[7..7]); + ram_block1a[1280].portadatain[] = ( data_a[0..0]); + ram_block1a[1281].portadatain[] = ( data_a[1..1]); + ram_block1a[1282].portadatain[] = ( data_a[2..2]); + ram_block1a[1283].portadatain[] = ( data_a[3..3]); + ram_block1a[1284].portadatain[] = ( data_a[4..4]); + ram_block1a[1285].portadatain[] = ( data_a[5..5]); + ram_block1a[1286].portadatain[] = ( data_a[6..6]); + ram_block1a[1287].portadatain[] = ( data_a[7..7]); + ram_block1a[1288].portadatain[] = ( data_a[0..0]); + ram_block1a[1289].portadatain[] = ( data_a[1..1]); + ram_block1a[1290].portadatain[] = ( data_a[2..2]); + ram_block1a[1291].portadatain[] = ( data_a[3..3]); + ram_block1a[1292].portadatain[] = ( data_a[4..4]); + ram_block1a[1293].portadatain[] = ( data_a[5..5]); + ram_block1a[1294].portadatain[] = ( data_a[6..6]); + ram_block1a[1295].portadatain[] = ( data_a[7..7]); + ram_block1a[1296].portadatain[] = ( data_a[0..0]); + ram_block1a[1297].portadatain[] = ( data_a[1..1]); + ram_block1a[1298].portadatain[] = ( data_a[2..2]); + ram_block1a[1299].portadatain[] = ( data_a[3..3]); + ram_block1a[1300].portadatain[] = ( data_a[4..4]); + ram_block1a[1301].portadatain[] = ( data_a[5..5]); + ram_block1a[1302].portadatain[] = ( data_a[6..6]); + ram_block1a[1303].portadatain[] = ( data_a[7..7]); + ram_block1a[1304].portadatain[] = ( data_a[0..0]); + ram_block1a[1305].portadatain[] = ( data_a[1..1]); + ram_block1a[1306].portadatain[] = ( data_a[2..2]); + ram_block1a[1307].portadatain[] = ( data_a[3..3]); + ram_block1a[1308].portadatain[] = ( data_a[4..4]); + ram_block1a[1309].portadatain[] = ( data_a[5..5]); + ram_block1a[1310].portadatain[] = ( data_a[6..6]); + ram_block1a[1311].portadatain[] = ( data_a[7..7]); + ram_block1a[1312].portadatain[] = ( data_a[0..0]); + ram_block1a[1313].portadatain[] = ( data_a[1..1]); + ram_block1a[1314].portadatain[] = ( data_a[2..2]); + ram_block1a[1315].portadatain[] = ( data_a[3..3]); + ram_block1a[1316].portadatain[] = ( data_a[4..4]); + ram_block1a[1317].portadatain[] = ( data_a[5..5]); + ram_block1a[1318].portadatain[] = ( data_a[6..6]); + ram_block1a[1319].portadatain[] = ( data_a[7..7]); + ram_block1a[1320].portadatain[] = ( data_a[0..0]); + ram_block1a[1321].portadatain[] = ( data_a[1..1]); + ram_block1a[1322].portadatain[] = ( data_a[2..2]); + ram_block1a[1323].portadatain[] = ( data_a[3..3]); + ram_block1a[1324].portadatain[] = ( data_a[4..4]); + ram_block1a[1325].portadatain[] = ( data_a[5..5]); + ram_block1a[1326].portadatain[] = ( data_a[6..6]); + ram_block1a[1327].portadatain[] = ( data_a[7..7]); + ram_block1a[1328].portadatain[] = ( data_a[0..0]); + ram_block1a[1329].portadatain[] = ( data_a[1..1]); + ram_block1a[1330].portadatain[] = ( data_a[2..2]); + ram_block1a[1331].portadatain[] = ( data_a[3..3]); + ram_block1a[1332].portadatain[] = ( data_a[4..4]); + ram_block1a[1333].portadatain[] = ( data_a[5..5]); + ram_block1a[1334].portadatain[] = ( data_a[6..6]); + ram_block1a[1335].portadatain[] = ( data_a[7..7]); + ram_block1a[1336].portadatain[] = ( data_a[0..0]); + ram_block1a[1337].portadatain[] = ( data_a[1..1]); + ram_block1a[1338].portadatain[] = ( data_a[2..2]); + ram_block1a[1339].portadatain[] = ( data_a[3..3]); + ram_block1a[1340].portadatain[] = ( data_a[4..4]); + ram_block1a[1341].portadatain[] = ( data_a[5..5]); + ram_block1a[1342].portadatain[] = ( data_a[6..6]); + ram_block1a[1343].portadatain[] = ( data_a[7..7]); + ram_block1a[1344].portadatain[] = ( data_a[0..0]); + ram_block1a[1345].portadatain[] = ( data_a[1..1]); + ram_block1a[1346].portadatain[] = ( data_a[2..2]); + ram_block1a[1347].portadatain[] = ( data_a[3..3]); + ram_block1a[1348].portadatain[] = ( data_a[4..4]); + ram_block1a[1349].portadatain[] = ( data_a[5..5]); + ram_block1a[1350].portadatain[] = ( data_a[6..6]); + ram_block1a[1351].portadatain[] = ( data_a[7..7]); + ram_block1a[1352].portadatain[] = ( data_a[0..0]); + ram_block1a[1353].portadatain[] = ( data_a[1..1]); + ram_block1a[1354].portadatain[] = ( data_a[2..2]); + ram_block1a[1355].portadatain[] = ( data_a[3..3]); + ram_block1a[1356].portadatain[] = ( data_a[4..4]); + ram_block1a[1357].portadatain[] = ( data_a[5..5]); + ram_block1a[1358].portadatain[] = ( data_a[6..6]); + ram_block1a[1359].portadatain[] = ( data_a[7..7]); + ram_block1a[1360].portadatain[] = ( data_a[0..0]); + ram_block1a[1361].portadatain[] = ( data_a[1..1]); + ram_block1a[1362].portadatain[] = ( data_a[2..2]); + ram_block1a[1363].portadatain[] = ( data_a[3..3]); + ram_block1a[1364].portadatain[] = ( data_a[4..4]); + ram_block1a[1365].portadatain[] = ( data_a[5..5]); + ram_block1a[1366].portadatain[] = ( data_a[6..6]); + ram_block1a[1367].portadatain[] = ( data_a[7..7]); + ram_block1a[1368].portadatain[] = ( data_a[0..0]); + ram_block1a[1369].portadatain[] = ( data_a[1..1]); + ram_block1a[1370].portadatain[] = ( data_a[2..2]); + ram_block1a[1371].portadatain[] = ( data_a[3..3]); + ram_block1a[1372].portadatain[] = ( data_a[4..4]); + ram_block1a[1373].portadatain[] = ( data_a[5..5]); + ram_block1a[1374].portadatain[] = ( data_a[6..6]); + ram_block1a[1375].portadatain[] = ( data_a[7..7]); + ram_block1a[1376].portadatain[] = ( data_a[0..0]); + ram_block1a[1377].portadatain[] = ( data_a[1..1]); + ram_block1a[1378].portadatain[] = ( data_a[2..2]); + ram_block1a[1379].portadatain[] = ( data_a[3..3]); + ram_block1a[1380].portadatain[] = ( data_a[4..4]); + ram_block1a[1381].portadatain[] = ( data_a[5..5]); + ram_block1a[1382].portadatain[] = ( data_a[6..6]); + ram_block1a[1383].portadatain[] = ( data_a[7..7]); + ram_block1a[1384].portadatain[] = ( data_a[0..0]); + ram_block1a[1385].portadatain[] = ( data_a[1..1]); + ram_block1a[1386].portadatain[] = ( data_a[2..2]); + ram_block1a[1387].portadatain[] = ( data_a[3..3]); + ram_block1a[1388].portadatain[] = ( data_a[4..4]); + ram_block1a[1389].portadatain[] = ( data_a[5..5]); + ram_block1a[1390].portadatain[] = ( data_a[6..6]); + ram_block1a[1391].portadatain[] = ( data_a[7..7]); + ram_block1a[1392].portadatain[] = ( data_a[0..0]); + ram_block1a[1393].portadatain[] = ( data_a[1..1]); + ram_block1a[1394].portadatain[] = ( data_a[2..2]); + ram_block1a[1395].portadatain[] = ( data_a[3..3]); + ram_block1a[1396].portadatain[] = ( data_a[4..4]); + ram_block1a[1397].portadatain[] = ( data_a[5..5]); + ram_block1a[1398].portadatain[] = ( data_a[6..6]); + ram_block1a[1399].portadatain[] = ( data_a[7..7]); + ram_block1a[1400].portadatain[] = ( data_a[0..0]); + ram_block1a[1401].portadatain[] = ( data_a[1..1]); + ram_block1a[1402].portadatain[] = ( data_a[2..2]); + ram_block1a[1403].portadatain[] = ( data_a[3..3]); + ram_block1a[1404].portadatain[] = ( data_a[4..4]); + ram_block1a[1405].portadatain[] = ( data_a[5..5]); + ram_block1a[1406].portadatain[] = ( data_a[6..6]); + ram_block1a[1407].portadatain[] = ( data_a[7..7]); + ram_block1a[1408].portadatain[] = ( data_a[0..0]); + ram_block1a[1409].portadatain[] = ( data_a[1..1]); + ram_block1a[1410].portadatain[] = ( data_a[2..2]); + ram_block1a[1411].portadatain[] = ( data_a[3..3]); + ram_block1a[1412].portadatain[] = ( data_a[4..4]); + ram_block1a[1413].portadatain[] = ( data_a[5..5]); + ram_block1a[1414].portadatain[] = ( data_a[6..6]); + ram_block1a[1415].portadatain[] = ( data_a[7..7]); + ram_block1a[1416].portadatain[] = ( data_a[0..0]); + ram_block1a[1417].portadatain[] = ( data_a[1..1]); + ram_block1a[1418].portadatain[] = ( data_a[2..2]); + ram_block1a[1419].portadatain[] = ( data_a[3..3]); + ram_block1a[1420].portadatain[] = ( data_a[4..4]); + ram_block1a[1421].portadatain[] = ( data_a[5..5]); + ram_block1a[1422].portadatain[] = ( data_a[6..6]); + ram_block1a[1423].portadatain[] = ( data_a[7..7]); + ram_block1a[1424].portadatain[] = ( data_a[0..0]); + ram_block1a[1425].portadatain[] = ( data_a[1..1]); + ram_block1a[1426].portadatain[] = ( data_a[2..2]); + ram_block1a[1427].portadatain[] = ( data_a[3..3]); + ram_block1a[1428].portadatain[] = ( data_a[4..4]); + ram_block1a[1429].portadatain[] = ( data_a[5..5]); + ram_block1a[1430].portadatain[] = ( data_a[6..6]); + ram_block1a[1431].portadatain[] = ( data_a[7..7]); + ram_block1a[1432].portadatain[] = ( data_a[0..0]); + ram_block1a[1433].portadatain[] = ( data_a[1..1]); + ram_block1a[1434].portadatain[] = ( data_a[2..2]); + ram_block1a[1435].portadatain[] = ( data_a[3..3]); + ram_block1a[1436].portadatain[] = ( data_a[4..4]); + ram_block1a[1437].portadatain[] = ( data_a[5..5]); + ram_block1a[1438].portadatain[] = ( data_a[6..6]); + ram_block1a[1439].portadatain[] = ( data_a[7..7]); + ram_block1a[1440].portadatain[] = ( data_a[0..0]); + ram_block1a[1441].portadatain[] = ( data_a[1..1]); + ram_block1a[1442].portadatain[] = ( data_a[2..2]); + ram_block1a[1443].portadatain[] = ( data_a[3..3]); + ram_block1a[1444].portadatain[] = ( data_a[4..4]); + ram_block1a[1445].portadatain[] = ( data_a[5..5]); + ram_block1a[1446].portadatain[] = ( data_a[6..6]); + ram_block1a[1447].portadatain[] = ( data_a[7..7]); + ram_block1a[1448].portadatain[] = ( data_a[0..0]); + ram_block1a[1449].portadatain[] = ( data_a[1..1]); + ram_block1a[1450].portadatain[] = ( data_a[2..2]); + ram_block1a[1451].portadatain[] = ( data_a[3..3]); + ram_block1a[1452].portadatain[] = ( data_a[4..4]); + ram_block1a[1453].portadatain[] = ( data_a[5..5]); + ram_block1a[1454].portadatain[] = ( data_a[6..6]); + ram_block1a[1455].portadatain[] = ( data_a[7..7]); + ram_block1a[1456].portadatain[] = ( data_a[0..0]); + ram_block1a[1457].portadatain[] = ( data_a[1..1]); + ram_block1a[1458].portadatain[] = ( data_a[2..2]); + ram_block1a[1459].portadatain[] = ( data_a[3..3]); + ram_block1a[1460].portadatain[] = ( data_a[4..4]); + ram_block1a[1461].portadatain[] = ( data_a[5..5]); + ram_block1a[1462].portadatain[] = ( data_a[6..6]); + ram_block1a[1463].portadatain[] = ( data_a[7..7]); + ram_block1a[1464].portadatain[] = ( data_a[0..0]); + ram_block1a[1465].portadatain[] = ( data_a[1..1]); + ram_block1a[1466].portadatain[] = ( data_a[2..2]); + ram_block1a[1467].portadatain[] = ( data_a[3..3]); + ram_block1a[1468].portadatain[] = ( data_a[4..4]); + ram_block1a[1469].portadatain[] = ( data_a[5..5]); + ram_block1a[1470].portadatain[] = ( data_a[6..6]); + ram_block1a[1471].portadatain[] = ( data_a[7..7]); + ram_block1a[1472].portadatain[] = ( data_a[0..0]); + ram_block1a[1473].portadatain[] = ( data_a[1..1]); + ram_block1a[1474].portadatain[] = ( data_a[2..2]); + ram_block1a[1475].portadatain[] = ( data_a[3..3]); + ram_block1a[1476].portadatain[] = ( data_a[4..4]); + ram_block1a[1477].portadatain[] = ( data_a[5..5]); + ram_block1a[1478].portadatain[] = ( data_a[6..6]); + ram_block1a[1479].portadatain[] = ( data_a[7..7]); + ram_block1a[1480].portadatain[] = ( data_a[0..0]); + ram_block1a[1481].portadatain[] = ( data_a[1..1]); + ram_block1a[1482].portadatain[] = ( data_a[2..2]); + ram_block1a[1483].portadatain[] = ( data_a[3..3]); + ram_block1a[1484].portadatain[] = ( data_a[4..4]); + ram_block1a[1485].portadatain[] = ( data_a[5..5]); + ram_block1a[1486].portadatain[] = ( data_a[6..6]); + ram_block1a[1487].portadatain[] = ( data_a[7..7]); + ram_block1a[1488].portadatain[] = ( data_a[0..0]); + ram_block1a[1489].portadatain[] = ( data_a[1..1]); + ram_block1a[1490].portadatain[] = ( data_a[2..2]); + ram_block1a[1491].portadatain[] = ( data_a[3..3]); + ram_block1a[1492].portadatain[] = ( data_a[4..4]); + ram_block1a[1493].portadatain[] = ( data_a[5..5]); + ram_block1a[1494].portadatain[] = ( data_a[6..6]); + ram_block1a[1495].portadatain[] = ( data_a[7..7]); + ram_block1a[1496].portadatain[] = ( data_a[0..0]); + ram_block1a[1497].portadatain[] = ( data_a[1..1]); + ram_block1a[1498].portadatain[] = ( data_a[2..2]); + ram_block1a[1499].portadatain[] = ( data_a[3..3]); + ram_block1a[1500].portadatain[] = ( data_a[4..4]); + ram_block1a[1501].portadatain[] = ( data_a[5..5]); + ram_block1a[1502].portadatain[] = ( data_a[6..6]); + ram_block1a[1503].portadatain[] = ( data_a[7..7]); + ram_block1a[1504].portadatain[] = ( data_a[0..0]); + ram_block1a[1505].portadatain[] = ( data_a[1..1]); + ram_block1a[1506].portadatain[] = ( data_a[2..2]); + ram_block1a[1507].portadatain[] = ( data_a[3..3]); + ram_block1a[1508].portadatain[] = ( data_a[4..4]); + ram_block1a[1509].portadatain[] = ( data_a[5..5]); + ram_block1a[1510].portadatain[] = ( data_a[6..6]); + ram_block1a[1511].portadatain[] = ( data_a[7..7]); + ram_block1a[1512].portadatain[] = ( data_a[0..0]); + ram_block1a[1513].portadatain[] = ( data_a[1..1]); + ram_block1a[1514].portadatain[] = ( data_a[2..2]); + ram_block1a[1515].portadatain[] = ( data_a[3..3]); + ram_block1a[1516].portadatain[] = ( data_a[4..4]); + ram_block1a[1517].portadatain[] = ( data_a[5..5]); + ram_block1a[1518].portadatain[] = ( data_a[6..6]); + ram_block1a[1519].portadatain[] = ( data_a[7..7]); + ram_block1a[1520].portadatain[] = ( data_a[0..0]); + ram_block1a[1521].portadatain[] = ( data_a[1..1]); + ram_block1a[1522].portadatain[] = ( data_a[2..2]); + ram_block1a[1523].portadatain[] = ( data_a[3..3]); + ram_block1a[1524].portadatain[] = ( data_a[4..4]); + ram_block1a[1525].portadatain[] = ( data_a[5..5]); + ram_block1a[1526].portadatain[] = ( data_a[6..6]); + ram_block1a[1527].portadatain[] = ( data_a[7..7]); + ram_block1a[1528].portadatain[] = ( data_a[0..0]); + ram_block1a[1529].portadatain[] = ( data_a[1..1]); + ram_block1a[1530].portadatain[] = ( data_a[2..2]); + ram_block1a[1531].portadatain[] = ( data_a[3..3]); + ram_block1a[1532].portadatain[] = ( data_a[4..4]); + ram_block1a[1533].portadatain[] = ( data_a[5..5]); + ram_block1a[1534].portadatain[] = ( data_a[6..6]); + ram_block1a[1535].portadatain[] = ( data_a[7..7]); + ram_block1a[1536].portadatain[] = ( data_a[0..0]); + ram_block1a[1537].portadatain[] = ( data_a[1..1]); + ram_block1a[1538].portadatain[] = ( data_a[2..2]); + ram_block1a[1539].portadatain[] = ( data_a[3..3]); + ram_block1a[1540].portadatain[] = ( data_a[4..4]); + ram_block1a[1541].portadatain[] = ( data_a[5..5]); + ram_block1a[1542].portadatain[] = ( data_a[6..6]); + ram_block1a[1543].portadatain[] = ( data_a[7..7]); + ram_block1a[1544].portadatain[] = ( data_a[0..0]); + ram_block1a[1545].portadatain[] = ( data_a[1..1]); + ram_block1a[1546].portadatain[] = ( data_a[2..2]); + ram_block1a[1547].portadatain[] = ( data_a[3..3]); + ram_block1a[1548].portadatain[] = ( data_a[4..4]); + ram_block1a[1549].portadatain[] = ( data_a[5..5]); + ram_block1a[1550].portadatain[] = ( data_a[6..6]); + ram_block1a[1551].portadatain[] = ( data_a[7..7]); + ram_block1a[1552].portadatain[] = ( data_a[0..0]); + ram_block1a[1553].portadatain[] = ( data_a[1..1]); + ram_block1a[1554].portadatain[] = ( data_a[2..2]); + ram_block1a[1555].portadatain[] = ( data_a[3..3]); + ram_block1a[1556].portadatain[] = ( data_a[4..4]); + ram_block1a[1557].portadatain[] = ( data_a[5..5]); + ram_block1a[1558].portadatain[] = ( data_a[6..6]); + ram_block1a[1559].portadatain[] = ( data_a[7..7]); + ram_block1a[1560].portadatain[] = ( data_a[0..0]); + ram_block1a[1561].portadatain[] = ( data_a[1..1]); + ram_block1a[1562].portadatain[] = ( data_a[2..2]); + ram_block1a[1563].portadatain[] = ( data_a[3..3]); + ram_block1a[1564].portadatain[] = ( data_a[4..4]); + ram_block1a[1565].portadatain[] = ( data_a[5..5]); + ram_block1a[1566].portadatain[] = ( data_a[6..6]); + ram_block1a[1567].portadatain[] = ( data_a[7..7]); + ram_block1a[1568].portadatain[] = ( data_a[0..0]); + ram_block1a[1569].portadatain[] = ( data_a[1..1]); + ram_block1a[1570].portadatain[] = ( data_a[2..2]); + ram_block1a[1571].portadatain[] = ( data_a[3..3]); + ram_block1a[1572].portadatain[] = ( data_a[4..4]); + ram_block1a[1573].portadatain[] = ( data_a[5..5]); + ram_block1a[1574].portadatain[] = ( data_a[6..6]); + ram_block1a[1575].portadatain[] = ( data_a[7..7]); + ram_block1a[1576].portadatain[] = ( data_a[0..0]); + ram_block1a[1577].portadatain[] = ( data_a[1..1]); + ram_block1a[1578].portadatain[] = ( data_a[2..2]); + ram_block1a[1579].portadatain[] = ( data_a[3..3]); + ram_block1a[1580].portadatain[] = ( data_a[4..4]); + ram_block1a[1581].portadatain[] = ( data_a[5..5]); + ram_block1a[1582].portadatain[] = ( data_a[6..6]); + ram_block1a[1583].portadatain[] = ( data_a[7..7]); + ram_block1a[1584].portadatain[] = ( data_a[0..0]); + ram_block1a[1585].portadatain[] = ( data_a[1..1]); + ram_block1a[1586].portadatain[] = ( data_a[2..2]); + ram_block1a[1587].portadatain[] = ( data_a[3..3]); + ram_block1a[1588].portadatain[] = ( data_a[4..4]); + ram_block1a[1589].portadatain[] = ( data_a[5..5]); + ram_block1a[1590].portadatain[] = ( data_a[6..6]); + ram_block1a[1591].portadatain[] = ( data_a[7..7]); + ram_block1a[1592].portadatain[] = ( data_a[0..0]); + ram_block1a[1593].portadatain[] = ( data_a[1..1]); + ram_block1a[1594].portadatain[] = ( data_a[2..2]); + ram_block1a[1595].portadatain[] = ( data_a[3..3]); + ram_block1a[1596].portadatain[] = ( data_a[4..4]); + ram_block1a[1597].portadatain[] = ( data_a[5..5]); + ram_block1a[1598].portadatain[] = ( data_a[6..6]); + ram_block1a[1599].portadatain[] = ( data_a[7..7]); + ram_block1a[1600].portadatain[] = ( data_a[0..0]); + ram_block1a[1601].portadatain[] = ( data_a[1..1]); + ram_block1a[1602].portadatain[] = ( data_a[2..2]); + ram_block1a[1603].portadatain[] = ( data_a[3..3]); + ram_block1a[1604].portadatain[] = ( data_a[4..4]); + ram_block1a[1605].portadatain[] = ( data_a[5..5]); + ram_block1a[1606].portadatain[] = ( data_a[6..6]); + ram_block1a[1607].portadatain[] = ( data_a[7..7]); + ram_block1a[1608].portadatain[] = ( data_a[0..0]); + ram_block1a[1609].portadatain[] = ( data_a[1..1]); + ram_block1a[1610].portadatain[] = ( data_a[2..2]); + ram_block1a[1611].portadatain[] = ( data_a[3..3]); + ram_block1a[1612].portadatain[] = ( data_a[4..4]); + ram_block1a[1613].portadatain[] = ( data_a[5..5]); + ram_block1a[1614].portadatain[] = ( data_a[6..6]); + ram_block1a[1615].portadatain[] = ( data_a[7..7]); + ram_block1a[1616].portadatain[] = ( data_a[0..0]); + ram_block1a[1617].portadatain[] = ( data_a[1..1]); + ram_block1a[1618].portadatain[] = ( data_a[2..2]); + ram_block1a[1619].portadatain[] = ( data_a[3..3]); + ram_block1a[1620].portadatain[] = ( data_a[4..4]); + ram_block1a[1621].portadatain[] = ( data_a[5..5]); + ram_block1a[1622].portadatain[] = ( data_a[6..6]); + ram_block1a[1623].portadatain[] = ( data_a[7..7]); + ram_block1a[1624].portadatain[] = ( data_a[0..0]); + ram_block1a[1625].portadatain[] = ( data_a[1..1]); + ram_block1a[1626].portadatain[] = ( data_a[2..2]); + ram_block1a[1627].portadatain[] = ( data_a[3..3]); + ram_block1a[1628].portadatain[] = ( data_a[4..4]); + ram_block1a[1629].portadatain[] = ( data_a[5..5]); + ram_block1a[1630].portadatain[] = ( data_a[6..6]); + ram_block1a[1631].portadatain[] = ( data_a[7..7]); + ram_block1a[1632].portadatain[] = ( data_a[0..0]); + ram_block1a[1633].portadatain[] = ( data_a[1..1]); + ram_block1a[1634].portadatain[] = ( data_a[2..2]); + ram_block1a[1635].portadatain[] = ( data_a[3..3]); + ram_block1a[1636].portadatain[] = ( data_a[4..4]); + ram_block1a[1637].portadatain[] = ( data_a[5..5]); + ram_block1a[1638].portadatain[] = ( data_a[6..6]); + ram_block1a[1639].portadatain[] = ( data_a[7..7]); + ram_block1a[1640].portadatain[] = ( data_a[0..0]); + ram_block1a[1641].portadatain[] = ( data_a[1..1]); + ram_block1a[1642].portadatain[] = ( data_a[2..2]); + ram_block1a[1643].portadatain[] = ( data_a[3..3]); + ram_block1a[1644].portadatain[] = ( data_a[4..4]); + ram_block1a[1645].portadatain[] = ( data_a[5..5]); + ram_block1a[1646].portadatain[] = ( data_a[6..6]); + ram_block1a[1647].portadatain[] = ( data_a[7..7]); + ram_block1a[1648].portadatain[] = ( data_a[0..0]); + ram_block1a[1649].portadatain[] = ( data_a[1..1]); + ram_block1a[1650].portadatain[] = ( data_a[2..2]); + ram_block1a[1651].portadatain[] = ( data_a[3..3]); + ram_block1a[1652].portadatain[] = ( data_a[4..4]); + ram_block1a[1653].portadatain[] = ( data_a[5..5]); + ram_block1a[1654].portadatain[] = ( data_a[6..6]); + ram_block1a[1655].portadatain[] = ( data_a[7..7]); + ram_block1a[1656].portadatain[] = ( data_a[0..0]); + ram_block1a[1657].portadatain[] = ( data_a[1..1]); + ram_block1a[1658].portadatain[] = ( data_a[2..2]); + ram_block1a[1659].portadatain[] = ( data_a[3..3]); + ram_block1a[1660].portadatain[] = ( data_a[4..4]); + ram_block1a[1661].portadatain[] = ( data_a[5..5]); + ram_block1a[1662].portadatain[] = ( data_a[6..6]); + ram_block1a[1663].portadatain[] = ( data_a[7..7]); + ram_block1a[1664].portadatain[] = ( data_a[0..0]); + ram_block1a[1665].portadatain[] = ( data_a[1..1]); + ram_block1a[1666].portadatain[] = ( data_a[2..2]); + ram_block1a[1667].portadatain[] = ( data_a[3..3]); + ram_block1a[1668].portadatain[] = ( data_a[4..4]); + ram_block1a[1669].portadatain[] = ( data_a[5..5]); + ram_block1a[1670].portadatain[] = ( data_a[6..6]); + ram_block1a[1671].portadatain[] = ( data_a[7..7]); + ram_block1a[1672].portadatain[] = ( data_a[0..0]); + ram_block1a[1673].portadatain[] = ( data_a[1..1]); + ram_block1a[1674].portadatain[] = ( data_a[2..2]); + ram_block1a[1675].portadatain[] = ( data_a[3..3]); + ram_block1a[1676].portadatain[] = ( data_a[4..4]); + ram_block1a[1677].portadatain[] = ( data_a[5..5]); + ram_block1a[1678].portadatain[] = ( data_a[6..6]); + ram_block1a[1679].portadatain[] = ( data_a[7..7]); + ram_block1a[1680].portadatain[] = ( data_a[0..0]); + ram_block1a[1681].portadatain[] = ( data_a[1..1]); + ram_block1a[1682].portadatain[] = ( data_a[2..2]); + ram_block1a[1683].portadatain[] = ( data_a[3..3]); + ram_block1a[1684].portadatain[] = ( data_a[4..4]); + ram_block1a[1685].portadatain[] = ( data_a[5..5]); + ram_block1a[1686].portadatain[] = ( data_a[6..6]); + ram_block1a[1687].portadatain[] = ( data_a[7..7]); + ram_block1a[1688].portadatain[] = ( data_a[0..0]); + ram_block1a[1689].portadatain[] = ( data_a[1..1]); + ram_block1a[1690].portadatain[] = ( data_a[2..2]); + ram_block1a[1691].portadatain[] = ( data_a[3..3]); + ram_block1a[1692].portadatain[] = ( data_a[4..4]); + ram_block1a[1693].portadatain[] = ( data_a[5..5]); + ram_block1a[1694].portadatain[] = ( data_a[6..6]); + ram_block1a[1695].portadatain[] = ( data_a[7..7]); + ram_block1a[1696].portadatain[] = ( data_a[0..0]); + ram_block1a[1697].portadatain[] = ( data_a[1..1]); + ram_block1a[1698].portadatain[] = ( data_a[2..2]); + ram_block1a[1699].portadatain[] = ( data_a[3..3]); + ram_block1a[1700].portadatain[] = ( data_a[4..4]); + ram_block1a[1701].portadatain[] = ( data_a[5..5]); + ram_block1a[1702].portadatain[] = ( data_a[6..6]); + ram_block1a[1703].portadatain[] = ( data_a[7..7]); + ram_block1a[1704].portadatain[] = ( data_a[0..0]); + ram_block1a[1705].portadatain[] = ( data_a[1..1]); + ram_block1a[1706].portadatain[] = ( data_a[2..2]); + ram_block1a[1707].portadatain[] = ( data_a[3..3]); + ram_block1a[1708].portadatain[] = ( data_a[4..4]); + ram_block1a[1709].portadatain[] = ( data_a[5..5]); + ram_block1a[1710].portadatain[] = ( data_a[6..6]); + ram_block1a[1711].portadatain[] = ( data_a[7..7]); + ram_block1a[1712].portadatain[] = ( data_a[0..0]); + ram_block1a[1713].portadatain[] = ( data_a[1..1]); + ram_block1a[1714].portadatain[] = ( data_a[2..2]); + ram_block1a[1715].portadatain[] = ( data_a[3..3]); + ram_block1a[1716].portadatain[] = ( data_a[4..4]); + ram_block1a[1717].portadatain[] = ( data_a[5..5]); + ram_block1a[1718].portadatain[] = ( data_a[6..6]); + ram_block1a[1719].portadatain[] = ( data_a[7..7]); + ram_block1a[1720].portadatain[] = ( data_a[0..0]); + ram_block1a[1721].portadatain[] = ( data_a[1..1]); + ram_block1a[1722].portadatain[] = ( data_a[2..2]); + ram_block1a[1723].portadatain[] = ( data_a[3..3]); + ram_block1a[1724].portadatain[] = ( data_a[4..4]); + ram_block1a[1725].portadatain[] = ( data_a[5..5]); + ram_block1a[1726].portadatain[] = ( data_a[6..6]); + ram_block1a[1727].portadatain[] = ( data_a[7..7]); + ram_block1a[1728].portadatain[] = ( data_a[0..0]); + ram_block1a[1729].portadatain[] = ( data_a[1..1]); + ram_block1a[1730].portadatain[] = ( data_a[2..2]); + ram_block1a[1731].portadatain[] = ( data_a[3..3]); + ram_block1a[1732].portadatain[] = ( data_a[4..4]); + ram_block1a[1733].portadatain[] = ( data_a[5..5]); + ram_block1a[1734].portadatain[] = ( data_a[6..6]); + ram_block1a[1735].portadatain[] = ( data_a[7..7]); + ram_block1a[1736].portadatain[] = ( data_a[0..0]); + ram_block1a[1737].portadatain[] = ( data_a[1..1]); + ram_block1a[1738].portadatain[] = ( data_a[2..2]); + ram_block1a[1739].portadatain[] = ( data_a[3..3]); + ram_block1a[1740].portadatain[] = ( data_a[4..4]); + ram_block1a[1741].portadatain[] = ( data_a[5..5]); + ram_block1a[1742].portadatain[] = ( data_a[6..6]); + ram_block1a[1743].portadatain[] = ( data_a[7..7]); + ram_block1a[1744].portadatain[] = ( data_a[0..0]); + ram_block1a[1745].portadatain[] = ( data_a[1..1]); + ram_block1a[1746].portadatain[] = ( data_a[2..2]); + ram_block1a[1747].portadatain[] = ( data_a[3..3]); + ram_block1a[1748].portadatain[] = ( data_a[4..4]); + ram_block1a[1749].portadatain[] = ( data_a[5..5]); + ram_block1a[1750].portadatain[] = ( data_a[6..6]); + ram_block1a[1751].portadatain[] = ( data_a[7..7]); + ram_block1a[1752].portadatain[] = ( data_a[0..0]); + ram_block1a[1753].portadatain[] = ( data_a[1..1]); + ram_block1a[1754].portadatain[] = ( data_a[2..2]); + ram_block1a[1755].portadatain[] = ( data_a[3..3]); + ram_block1a[1756].portadatain[] = ( data_a[4..4]); + ram_block1a[1757].portadatain[] = ( data_a[5..5]); + ram_block1a[1758].portadatain[] = ( data_a[6..6]); + ram_block1a[1759].portadatain[] = ( data_a[7..7]); + ram_block1a[1760].portadatain[] = ( data_a[0..0]); + ram_block1a[1761].portadatain[] = ( data_a[1..1]); + ram_block1a[1762].portadatain[] = ( data_a[2..2]); + ram_block1a[1763].portadatain[] = ( data_a[3..3]); + ram_block1a[1764].portadatain[] = ( data_a[4..4]); + ram_block1a[1765].portadatain[] = ( data_a[5..5]); + ram_block1a[1766].portadatain[] = ( data_a[6..6]); + ram_block1a[1767].portadatain[] = ( data_a[7..7]); + ram_block1a[1768].portadatain[] = ( data_a[0..0]); + ram_block1a[1769].portadatain[] = ( data_a[1..1]); + ram_block1a[1770].portadatain[] = ( data_a[2..2]); + ram_block1a[1771].portadatain[] = ( data_a[3..3]); + ram_block1a[1772].portadatain[] = ( data_a[4..4]); + ram_block1a[1773].portadatain[] = ( data_a[5..5]); + ram_block1a[1774].portadatain[] = ( data_a[6..6]); + ram_block1a[1775].portadatain[] = ( data_a[7..7]); + ram_block1a[1776].portadatain[] = ( data_a[0..0]); + ram_block1a[1777].portadatain[] = ( data_a[1..1]); + ram_block1a[1778].portadatain[] = ( data_a[2..2]); + ram_block1a[1779].portadatain[] = ( data_a[3..3]); + ram_block1a[1780].portadatain[] = ( data_a[4..4]); + ram_block1a[1781].portadatain[] = ( data_a[5..5]); + ram_block1a[1782].portadatain[] = ( data_a[6..6]); + ram_block1a[1783].portadatain[] = ( data_a[7..7]); + ram_block1a[1784].portadatain[] = ( data_a[0..0]); + ram_block1a[1785].portadatain[] = ( data_a[1..1]); + ram_block1a[1786].portadatain[] = ( data_a[2..2]); + ram_block1a[1787].portadatain[] = ( data_a[3..3]); + ram_block1a[1788].portadatain[] = ( data_a[4..4]); + ram_block1a[1789].portadatain[] = ( data_a[5..5]); + ram_block1a[1790].portadatain[] = ( data_a[6..6]); + ram_block1a[1791].portadatain[] = ( data_a[7..7]); + ram_block1a[1792].portadatain[] = ( data_a[0..0]); + ram_block1a[1793].portadatain[] = ( data_a[1..1]); + ram_block1a[1794].portadatain[] = ( data_a[2..2]); + ram_block1a[1795].portadatain[] = ( data_a[3..3]); + ram_block1a[1796].portadatain[] = ( data_a[4..4]); + ram_block1a[1797].portadatain[] = ( data_a[5..5]); + ram_block1a[1798].portadatain[] = ( data_a[6..6]); + ram_block1a[1799].portadatain[] = ( data_a[7..7]); + ram_block1a[1800].portadatain[] = ( data_a[0..0]); + ram_block1a[1801].portadatain[] = ( data_a[1..1]); + ram_block1a[1802].portadatain[] = ( data_a[2..2]); + ram_block1a[1803].portadatain[] = ( data_a[3..3]); + ram_block1a[1804].portadatain[] = ( data_a[4..4]); + ram_block1a[1805].portadatain[] = ( data_a[5..5]); + ram_block1a[1806].portadatain[] = ( data_a[6..6]); + ram_block1a[1807].portadatain[] = ( data_a[7..7]); + ram_block1a[1808].portadatain[] = ( data_a[0..0]); + ram_block1a[1809].portadatain[] = ( data_a[1..1]); + ram_block1a[1810].portadatain[] = ( data_a[2..2]); + ram_block1a[1811].portadatain[] = ( data_a[3..3]); + ram_block1a[1812].portadatain[] = ( data_a[4..4]); + ram_block1a[1813].portadatain[] = ( data_a[5..5]); + ram_block1a[1814].portadatain[] = ( data_a[6..6]); + ram_block1a[1815].portadatain[] = ( data_a[7..7]); + ram_block1a[1816].portadatain[] = ( data_a[0..0]); + ram_block1a[1817].portadatain[] = ( data_a[1..1]); + ram_block1a[1818].portadatain[] = ( data_a[2..2]); + ram_block1a[1819].portadatain[] = ( data_a[3..3]); + ram_block1a[1820].portadatain[] = ( data_a[4..4]); + ram_block1a[1821].portadatain[] = ( data_a[5..5]); + ram_block1a[1822].portadatain[] = ( data_a[6..6]); + ram_block1a[1823].portadatain[] = ( data_a[7..7]); + ram_block1a[1824].portadatain[] = ( data_a[0..0]); + ram_block1a[1825].portadatain[] = ( data_a[1..1]); + ram_block1a[1826].portadatain[] = ( data_a[2..2]); + ram_block1a[1827].portadatain[] = ( data_a[3..3]); + ram_block1a[1828].portadatain[] = ( data_a[4..4]); + ram_block1a[1829].portadatain[] = ( data_a[5..5]); + ram_block1a[1830].portadatain[] = ( data_a[6..6]); + ram_block1a[1831].portadatain[] = ( data_a[7..7]); + ram_block1a[1832].portadatain[] = ( data_a[0..0]); + ram_block1a[1833].portadatain[] = ( data_a[1..1]); + ram_block1a[1834].portadatain[] = ( data_a[2..2]); + ram_block1a[1835].portadatain[] = ( data_a[3..3]); + ram_block1a[1836].portadatain[] = ( data_a[4..4]); + ram_block1a[1837].portadatain[] = ( data_a[5..5]); + ram_block1a[1838].portadatain[] = ( data_a[6..6]); + ram_block1a[1839].portadatain[] = ( data_a[7..7]); + ram_block1a[1840].portadatain[] = ( data_a[0..0]); + ram_block1a[1841].portadatain[] = ( data_a[1..1]); + ram_block1a[1842].portadatain[] = ( data_a[2..2]); + ram_block1a[1843].portadatain[] = ( data_a[3..3]); + ram_block1a[1844].portadatain[] = ( data_a[4..4]); + ram_block1a[1845].portadatain[] = ( data_a[5..5]); + ram_block1a[1846].portadatain[] = ( data_a[6..6]); + ram_block1a[1847].portadatain[] = ( data_a[7..7]); + ram_block1a[1848].portadatain[] = ( data_a[0..0]); + ram_block1a[1849].portadatain[] = ( data_a[1..1]); + ram_block1a[1850].portadatain[] = ( data_a[2..2]); + ram_block1a[1851].portadatain[] = ( data_a[3..3]); + ram_block1a[1852].portadatain[] = ( data_a[4..4]); + ram_block1a[1853].portadatain[] = ( data_a[5..5]); + ram_block1a[1854].portadatain[] = ( data_a[6..6]); + ram_block1a[1855].portadatain[] = ( data_a[7..7]); + ram_block1a[1856].portadatain[] = ( data_a[0..0]); + ram_block1a[1857].portadatain[] = ( data_a[1..1]); + ram_block1a[1858].portadatain[] = ( data_a[2..2]); + ram_block1a[1859].portadatain[] = ( data_a[3..3]); + ram_block1a[1860].portadatain[] = ( data_a[4..4]); + ram_block1a[1861].portadatain[] = ( data_a[5..5]); + ram_block1a[1862].portadatain[] = ( data_a[6..6]); + ram_block1a[1863].portadatain[] = ( data_a[7..7]); + ram_block1a[1864].portadatain[] = ( data_a[0..0]); + ram_block1a[1865].portadatain[] = ( data_a[1..1]); + ram_block1a[1866].portadatain[] = ( data_a[2..2]); + ram_block1a[1867].portadatain[] = ( data_a[3..3]); + ram_block1a[1868].portadatain[] = ( data_a[4..4]); + ram_block1a[1869].portadatain[] = ( data_a[5..5]); + ram_block1a[1870].portadatain[] = ( data_a[6..6]); + ram_block1a[1871].portadatain[] = ( data_a[7..7]); + ram_block1a[1872].portadatain[] = ( data_a[0..0]); + ram_block1a[1873].portadatain[] = ( data_a[1..1]); + ram_block1a[1874].portadatain[] = ( data_a[2..2]); + ram_block1a[1875].portadatain[] = ( data_a[3..3]); + ram_block1a[1876].portadatain[] = ( data_a[4..4]); + ram_block1a[1877].portadatain[] = ( data_a[5..5]); + ram_block1a[1878].portadatain[] = ( data_a[6..6]); + ram_block1a[1879].portadatain[] = ( data_a[7..7]); + ram_block1a[1880].portadatain[] = ( data_a[0..0]); + ram_block1a[1881].portadatain[] = ( data_a[1..1]); + ram_block1a[1882].portadatain[] = ( data_a[2..2]); + ram_block1a[1883].portadatain[] = ( data_a[3..3]); + ram_block1a[1884].portadatain[] = ( data_a[4..4]); + ram_block1a[1885].portadatain[] = ( data_a[5..5]); + ram_block1a[1886].portadatain[] = ( data_a[6..6]); + ram_block1a[1887].portadatain[] = ( data_a[7..7]); + ram_block1a[1888].portadatain[] = ( data_a[0..0]); + ram_block1a[1889].portadatain[] = ( data_a[1..1]); + ram_block1a[1890].portadatain[] = ( data_a[2..2]); + ram_block1a[1891].portadatain[] = ( data_a[3..3]); + ram_block1a[1892].portadatain[] = ( data_a[4..4]); + ram_block1a[1893].portadatain[] = ( data_a[5..5]); + ram_block1a[1894].portadatain[] = ( data_a[6..6]); + ram_block1a[1895].portadatain[] = ( data_a[7..7]); + ram_block1a[1896].portadatain[] = ( data_a[0..0]); + ram_block1a[1897].portadatain[] = ( data_a[1..1]); + ram_block1a[1898].portadatain[] = ( data_a[2..2]); + ram_block1a[1899].portadatain[] = ( data_a[3..3]); + ram_block1a[1900].portadatain[] = ( data_a[4..4]); + ram_block1a[1901].portadatain[] = ( data_a[5..5]); + ram_block1a[1902].portadatain[] = ( data_a[6..6]); + ram_block1a[1903].portadatain[] = ( data_a[7..7]); + ram_block1a[1904].portadatain[] = ( data_a[0..0]); + ram_block1a[1905].portadatain[] = ( data_a[1..1]); + ram_block1a[1906].portadatain[] = ( data_a[2..2]); + ram_block1a[1907].portadatain[] = ( data_a[3..3]); + ram_block1a[1908].portadatain[] = ( data_a[4..4]); + ram_block1a[1909].portadatain[] = ( data_a[5..5]); + ram_block1a[1910].portadatain[] = ( data_a[6..6]); + ram_block1a[1911].portadatain[] = ( data_a[7..7]); + ram_block1a[1912].portadatain[] = ( data_a[0..0]); + ram_block1a[1913].portadatain[] = ( data_a[1..1]); + ram_block1a[1914].portadatain[] = ( data_a[2..2]); + ram_block1a[1915].portadatain[] = ( data_a[3..3]); + ram_block1a[1916].portadatain[] = ( data_a[4..4]); + ram_block1a[1917].portadatain[] = ( data_a[5..5]); + ram_block1a[1918].portadatain[] = ( data_a[6..6]); + ram_block1a[1919].portadatain[] = ( data_a[7..7]); + ram_block1a[1920].portadatain[] = ( data_a[0..0]); + ram_block1a[1921].portadatain[] = ( data_a[1..1]); + ram_block1a[1922].portadatain[] = ( data_a[2..2]); + ram_block1a[1923].portadatain[] = ( data_a[3..3]); + ram_block1a[1924].portadatain[] = ( data_a[4..4]); + ram_block1a[1925].portadatain[] = ( data_a[5..5]); + ram_block1a[1926].portadatain[] = ( data_a[6..6]); + ram_block1a[1927].portadatain[] = ( data_a[7..7]); + ram_block1a[1928].portadatain[] = ( data_a[0..0]); + ram_block1a[1929].portadatain[] = ( data_a[1..1]); + ram_block1a[1930].portadatain[] = ( data_a[2..2]); + ram_block1a[1931].portadatain[] = ( data_a[3..3]); + ram_block1a[1932].portadatain[] = ( data_a[4..4]); + ram_block1a[1933].portadatain[] = ( data_a[5..5]); + ram_block1a[1934].portadatain[] = ( data_a[6..6]); + ram_block1a[1935].portadatain[] = ( data_a[7..7]); + ram_block1a[1936].portadatain[] = ( data_a[0..0]); + ram_block1a[1937].portadatain[] = ( data_a[1..1]); + ram_block1a[1938].portadatain[] = ( data_a[2..2]); + ram_block1a[1939].portadatain[] = ( data_a[3..3]); + ram_block1a[1940].portadatain[] = ( data_a[4..4]); + ram_block1a[1941].portadatain[] = ( data_a[5..5]); + ram_block1a[1942].portadatain[] = ( data_a[6..6]); + ram_block1a[1943].portadatain[] = ( data_a[7..7]); + ram_block1a[1944].portadatain[] = ( data_a[0..0]); + ram_block1a[1945].portadatain[] = ( data_a[1..1]); + ram_block1a[1946].portadatain[] = ( data_a[2..2]); + ram_block1a[1947].portadatain[] = ( data_a[3..3]); + ram_block1a[1948].portadatain[] = ( data_a[4..4]); + ram_block1a[1949].portadatain[] = ( data_a[5..5]); + ram_block1a[1950].portadatain[] = ( data_a[6..6]); + ram_block1a[1951].portadatain[] = ( data_a[7..7]); + ram_block1a[1952].portadatain[] = ( data_a[0..0]); + ram_block1a[1953].portadatain[] = ( data_a[1..1]); + ram_block1a[1954].portadatain[] = ( data_a[2..2]); + ram_block1a[1955].portadatain[] = ( data_a[3..3]); + ram_block1a[1956].portadatain[] = ( data_a[4..4]); + ram_block1a[1957].portadatain[] = ( data_a[5..5]); + ram_block1a[1958].portadatain[] = ( data_a[6..6]); + ram_block1a[1959].portadatain[] = ( data_a[7..7]); + ram_block1a[1960].portadatain[] = ( data_a[0..0]); + ram_block1a[1961].portadatain[] = ( data_a[1..1]); + ram_block1a[1962].portadatain[] = ( data_a[2..2]); + ram_block1a[1963].portadatain[] = ( data_a[3..3]); + ram_block1a[1964].portadatain[] = ( data_a[4..4]); + ram_block1a[1965].portadatain[] = ( data_a[5..5]); + ram_block1a[1966].portadatain[] = ( data_a[6..6]); + ram_block1a[1967].portadatain[] = ( data_a[7..7]); + ram_block1a[1968].portadatain[] = ( data_a[0..0]); + ram_block1a[1969].portadatain[] = ( data_a[1..1]); + ram_block1a[1970].portadatain[] = ( data_a[2..2]); + ram_block1a[1971].portadatain[] = ( data_a[3..3]); + ram_block1a[1972].portadatain[] = ( data_a[4..4]); + ram_block1a[1973].portadatain[] = ( data_a[5..5]); + ram_block1a[1974].portadatain[] = ( data_a[6..6]); + ram_block1a[1975].portadatain[] = ( data_a[7..7]); + ram_block1a[1976].portadatain[] = ( data_a[0..0]); + ram_block1a[1977].portadatain[] = ( data_a[1..1]); + ram_block1a[1978].portadatain[] = ( data_a[2..2]); + ram_block1a[1979].portadatain[] = ( data_a[3..3]); + ram_block1a[1980].portadatain[] = ( data_a[4..4]); + ram_block1a[1981].portadatain[] = ( data_a[5..5]); + ram_block1a[1982].portadatain[] = ( data_a[6..6]); + ram_block1a[1983].portadatain[] = ( data_a[7..7]); + ram_block1a[1984].portadatain[] = ( data_a[0..0]); + ram_block1a[1985].portadatain[] = ( data_a[1..1]); + ram_block1a[1986].portadatain[] = ( data_a[2..2]); + ram_block1a[1987].portadatain[] = ( data_a[3..3]); + ram_block1a[1988].portadatain[] = ( data_a[4..4]); + ram_block1a[1989].portadatain[] = ( data_a[5..5]); + ram_block1a[1990].portadatain[] = ( data_a[6..6]); + ram_block1a[1991].portadatain[] = ( data_a[7..7]); + ram_block1a[1992].portadatain[] = ( data_a[0..0]); + ram_block1a[1993].portadatain[] = ( data_a[1..1]); + ram_block1a[1994].portadatain[] = ( data_a[2..2]); + ram_block1a[1995].portadatain[] = ( data_a[3..3]); + ram_block1a[1996].portadatain[] = ( data_a[4..4]); + ram_block1a[1997].portadatain[] = ( data_a[5..5]); + ram_block1a[1998].portadatain[] = ( data_a[6..6]); + ram_block1a[1999].portadatain[] = ( data_a[7..7]); + ram_block1a[2000].portadatain[] = ( data_a[0..0]); + ram_block1a[2001].portadatain[] = ( data_a[1..1]); + ram_block1a[2002].portadatain[] = ( data_a[2..2]); + ram_block1a[2003].portadatain[] = ( data_a[3..3]); + ram_block1a[2004].portadatain[] = ( data_a[4..4]); + ram_block1a[2005].portadatain[] = ( data_a[5..5]); + ram_block1a[2006].portadatain[] = ( data_a[6..6]); + ram_block1a[2007].portadatain[] = ( data_a[7..7]); + ram_block1a[2008].portadatain[] = ( data_a[0..0]); + ram_block1a[2009].portadatain[] = ( data_a[1..1]); + ram_block1a[2010].portadatain[] = ( data_a[2..2]); + ram_block1a[2011].portadatain[] = ( data_a[3..3]); + ram_block1a[2012].portadatain[] = ( data_a[4..4]); + ram_block1a[2013].portadatain[] = ( data_a[5..5]); + ram_block1a[2014].portadatain[] = ( data_a[6..6]); + ram_block1a[2015].portadatain[] = ( data_a[7..7]); + ram_block1a[2016].portadatain[] = ( data_a[0..0]); + ram_block1a[2017].portadatain[] = ( data_a[1..1]); + ram_block1a[2018].portadatain[] = ( data_a[2..2]); + ram_block1a[2019].portadatain[] = ( data_a[3..3]); + ram_block1a[2020].portadatain[] = ( data_a[4..4]); + ram_block1a[2021].portadatain[] = ( data_a[5..5]); + ram_block1a[2022].portadatain[] = ( data_a[6..6]); + ram_block1a[2023].portadatain[] = ( data_a[7..7]); + ram_block1a[2024].portadatain[] = ( data_a[0..0]); + ram_block1a[2025].portadatain[] = ( data_a[1..1]); + ram_block1a[2026].portadatain[] = ( data_a[2..2]); + ram_block1a[2027].portadatain[] = ( data_a[3..3]); + ram_block1a[2028].portadatain[] = ( data_a[4..4]); + ram_block1a[2029].portadatain[] = ( data_a[5..5]); + ram_block1a[2030].portadatain[] = ( data_a[6..6]); + ram_block1a[2031].portadatain[] = ( data_a[7..7]); + ram_block1a[2032].portadatain[] = ( data_a[0..0]); + ram_block1a[2033].portadatain[] = ( data_a[1..1]); + ram_block1a[2034].portadatain[] = ( data_a[2..2]); + ram_block1a[2035].portadatain[] = ( data_a[3..3]); + ram_block1a[2036].portadatain[] = ( data_a[4..4]); + ram_block1a[2037].portadatain[] = ( data_a[5..5]); + ram_block1a[2038].portadatain[] = ( data_a[6..6]); + ram_block1a[2039].portadatain[] = ( data_a[7..7]); + ram_block1a[2040].portadatain[] = ( data_a[0..0]); + ram_block1a[2041].portadatain[] = ( data_a[1..1]); + ram_block1a[2042].portadatain[] = ( data_a[2..2]); + ram_block1a[2043].portadatain[] = ( data_a[3..3]); + ram_block1a[2044].portadatain[] = ( data_a[4..4]); + ram_block1a[2045].portadatain[] = ( data_a[5..5]); + ram_block1a[2046].portadatain[] = ( data_a[6..6]); + ram_block1a[2047].portadatain[] = ( data_a[7..7]); + ram_block1a[2047..0].portawe = ( decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], 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decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..112], 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decode2.eq[100..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..78], decode2.eq[78..78], decode2.eq[78..78], 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decode2.eq[57..57], decode2.eq[57..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[2047..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[2047..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[7..0] = address_b[20..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/altsyncram_caq1.tdf b/proj_quartus/db/altsyncram_caq1.tdf new file mode 100644 index 000000000..5e62602d3 --- /dev/null +++ b/proj_quartus/db/altsyncram_caq1.tdf @@ -0,0 +1,996 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=32768 NUMWORDS_B=32768 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=15 WIDTHAD_B=15 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_8la (data[1..0], enable) +RETURNS ( eq[3..0]); +FUNCTION mux_ofb (data[31..0], sel[1..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 12 M10K 32 reg 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_caq1 +( + address_a[14..0] : input; + address_b[14..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[1..0] : dffe; + decode2 : decode_8la; + mux3 : mux_ofb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 32768, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 32768, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[14..0] : WIRE; + address_b_sel[1..0] : WIRE; + address_b_wire[14..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[1..0] = address_a_wire[14..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[31..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[31..0].portawe = ( decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[31..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[31..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[1..0] = address_b[14..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/altsyncram_daq1.tdf b/proj_quartus/db/altsyncram_daq1.tdf new file mode 100644 index 000000000..436c508ae --- /dev/null +++ b/proj_quartus/db/altsyncram_daq1.tdf @@ -0,0 +1,1924 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=65536 NUMWORDS_B=65536 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=16 WIDTHAD_B=16 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_dla (data[2..0], enable) +RETURNS ( eq[7..0]); +FUNCTION mux_tfb (data[63..0], sel[2..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 27 M10K 64 reg 3 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_daq1 +( + address_a[15..0] : input; + address_b[15..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[2..0] : dffe; + decode2 : decode_dla; + mux3 : mux_tfb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 65536, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 65536, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[15..0] : WIRE; + address_b_sel[2..0] : WIRE; + address_b_wire[15..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[2..0] = address_a_wire[15..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[63..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[63..0].clk0 = clock0; + ram_block1a[63..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[0..0]); + ram_block1a[41].portadatain[] = ( data_a[1..1]); + ram_block1a[42].portadatain[] = ( data_a[2..2]); + ram_block1a[43].portadatain[] = ( data_a[3..3]); + ram_block1a[44].portadatain[] = ( data_a[4..4]); + ram_block1a[45].portadatain[] = ( data_a[5..5]); + ram_block1a[46].portadatain[] = ( data_a[6..6]); + ram_block1a[47].portadatain[] = ( data_a[7..7]); + ram_block1a[48].portadatain[] = ( data_a[0..0]); + ram_block1a[49].portadatain[] = ( data_a[1..1]); + ram_block1a[50].portadatain[] = ( data_a[2..2]); + ram_block1a[51].portadatain[] = ( data_a[3..3]); + ram_block1a[52].portadatain[] = ( data_a[4..4]); + ram_block1a[53].portadatain[] = ( data_a[5..5]); + ram_block1a[54].portadatain[] = ( data_a[6..6]); + ram_block1a[55].portadatain[] = ( data_a[7..7]); + ram_block1a[56].portadatain[] = ( data_a[0..0]); + ram_block1a[57].portadatain[] = ( data_a[1..1]); + ram_block1a[58].portadatain[] = ( data_a[2..2]); + ram_block1a[59].portadatain[] = ( data_a[3..3]); + ram_block1a[60].portadatain[] = ( data_a[4..4]); + ram_block1a[61].portadatain[] = ( data_a[5..5]); + ram_block1a[62].portadatain[] = ( data_a[6..6]); + ram_block1a[63].portadatain[] = ( data_a[7..7]); + ram_block1a[63..0].portawe = ( decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[63..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[63..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[2..0] = address_b[15..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/altsyncram_ocq1.tdf b/proj_quartus/db/altsyncram_ocq1.tdf new file mode 100644 index 000000000..40cba4f13 --- /dev/null +++ b/proj_quartus/db/altsyncram_ocq1.tdf @@ -0,0 +1,3780 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=131072 NUMWORDS_B=131072 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=17 WIDTHAD_B=17 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_tma (data[3..0], enable) +RETURNS ( eq[15..0]); +FUNCTION mux_dhb (data[127..0], sel[3..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 58 M10K 128 reg 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_ocq1 +( + address_a[16..0] : input; + address_b[16..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[3..0] : dffe; + decode2 : decode_tma; + mux3 : mux_dhb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a64 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a65 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a66 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a67 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a68 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a69 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a70 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a71 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a72 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a73 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a74 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a75 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a76 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a77 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a78 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a79 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a80 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a81 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a82 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a83 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a84 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a85 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a86 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a87 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a88 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a89 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a90 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a91 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a92 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a93 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a94 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a95 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a96 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a97 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a98 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a99 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a100 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a101 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a102 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a103 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a104 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a105 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a106 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a107 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a108 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a109 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a110 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a111 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a112 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a113 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a114 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a115 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a116 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a117 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a118 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a119 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a120 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a121 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a122 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a123 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a124 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a125 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a126 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a127 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 131072, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 131072, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[16..0] : WIRE; + address_b_sel[3..0] : WIRE; + address_b_wire[16..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[3..0] = address_a_wire[16..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[127..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[127..0].clk0 = clock0; + ram_block1a[127..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[0..0]); + ram_block1a[41].portadatain[] = ( data_a[1..1]); + ram_block1a[42].portadatain[] = ( data_a[2..2]); + ram_block1a[43].portadatain[] = ( data_a[3..3]); + ram_block1a[44].portadatain[] = ( data_a[4..4]); + ram_block1a[45].portadatain[] = ( data_a[5..5]); + ram_block1a[46].portadatain[] = ( data_a[6..6]); + ram_block1a[47].portadatain[] = ( data_a[7..7]); + ram_block1a[48].portadatain[] = ( data_a[0..0]); + ram_block1a[49].portadatain[] = ( data_a[1..1]); + ram_block1a[50].portadatain[] = ( data_a[2..2]); + ram_block1a[51].portadatain[] = ( data_a[3..3]); + ram_block1a[52].portadatain[] = ( data_a[4..4]); + ram_block1a[53].portadatain[] = ( data_a[5..5]); + ram_block1a[54].portadatain[] = ( data_a[6..6]); + ram_block1a[55].portadatain[] = ( data_a[7..7]); + ram_block1a[56].portadatain[] = ( data_a[0..0]); + ram_block1a[57].portadatain[] = ( data_a[1..1]); + ram_block1a[58].portadatain[] = ( data_a[2..2]); + ram_block1a[59].portadatain[] = ( data_a[3..3]); + ram_block1a[60].portadatain[] = ( data_a[4..4]); + ram_block1a[61].portadatain[] = ( data_a[5..5]); + ram_block1a[62].portadatain[] = ( data_a[6..6]); + ram_block1a[63].portadatain[] = ( data_a[7..7]); + ram_block1a[64].portadatain[] = ( data_a[0..0]); + ram_block1a[65].portadatain[] = ( data_a[1..1]); + ram_block1a[66].portadatain[] = ( data_a[2..2]); + ram_block1a[67].portadatain[] = ( data_a[3..3]); + ram_block1a[68].portadatain[] = ( data_a[4..4]); + ram_block1a[69].portadatain[] = ( data_a[5..5]); + ram_block1a[70].portadatain[] = ( data_a[6..6]); + ram_block1a[71].portadatain[] = ( data_a[7..7]); + ram_block1a[72].portadatain[] = ( data_a[0..0]); + ram_block1a[73].portadatain[] = ( data_a[1..1]); + ram_block1a[74].portadatain[] = ( data_a[2..2]); + ram_block1a[75].portadatain[] = ( data_a[3..3]); + ram_block1a[76].portadatain[] = ( data_a[4..4]); + ram_block1a[77].portadatain[] = ( data_a[5..5]); + ram_block1a[78].portadatain[] = ( data_a[6..6]); + ram_block1a[79].portadatain[] = ( data_a[7..7]); + ram_block1a[80].portadatain[] = ( data_a[0..0]); + ram_block1a[81].portadatain[] = ( data_a[1..1]); + ram_block1a[82].portadatain[] = ( data_a[2..2]); + ram_block1a[83].portadatain[] = ( data_a[3..3]); + ram_block1a[84].portadatain[] = ( data_a[4..4]); + ram_block1a[85].portadatain[] = ( data_a[5..5]); + ram_block1a[86].portadatain[] = ( data_a[6..6]); + ram_block1a[87].portadatain[] = ( data_a[7..7]); + ram_block1a[88].portadatain[] = ( data_a[0..0]); + ram_block1a[89].portadatain[] = ( data_a[1..1]); + ram_block1a[90].portadatain[] = ( data_a[2..2]); + ram_block1a[91].portadatain[] = ( data_a[3..3]); + ram_block1a[92].portadatain[] = ( data_a[4..4]); + ram_block1a[93].portadatain[] = ( data_a[5..5]); + ram_block1a[94].portadatain[] = ( data_a[6..6]); + ram_block1a[95].portadatain[] = ( data_a[7..7]); + ram_block1a[96].portadatain[] = ( data_a[0..0]); + ram_block1a[97].portadatain[] = ( data_a[1..1]); + ram_block1a[98].portadatain[] = ( data_a[2..2]); + ram_block1a[99].portadatain[] = ( data_a[3..3]); + ram_block1a[100].portadatain[] = ( data_a[4..4]); + ram_block1a[101].portadatain[] = ( data_a[5..5]); + ram_block1a[102].portadatain[] = ( data_a[6..6]); + ram_block1a[103].portadatain[] = ( data_a[7..7]); + ram_block1a[104].portadatain[] = ( data_a[0..0]); + ram_block1a[105].portadatain[] = ( data_a[1..1]); + ram_block1a[106].portadatain[] = ( data_a[2..2]); + ram_block1a[107].portadatain[] = ( data_a[3..3]); + ram_block1a[108].portadatain[] = ( data_a[4..4]); + ram_block1a[109].portadatain[] = ( data_a[5..5]); + ram_block1a[110].portadatain[] = ( data_a[6..6]); + ram_block1a[111].portadatain[] = ( data_a[7..7]); + ram_block1a[112].portadatain[] = ( data_a[0..0]); + ram_block1a[113].portadatain[] = ( data_a[1..1]); + ram_block1a[114].portadatain[] = ( data_a[2..2]); + ram_block1a[115].portadatain[] = ( data_a[3..3]); + ram_block1a[116].portadatain[] = ( data_a[4..4]); + ram_block1a[117].portadatain[] = ( data_a[5..5]); + ram_block1a[118].portadatain[] = ( data_a[6..6]); + ram_block1a[119].portadatain[] = ( data_a[7..7]); + ram_block1a[120].portadatain[] = ( data_a[0..0]); + ram_block1a[121].portadatain[] = ( data_a[1..1]); + ram_block1a[122].portadatain[] = ( data_a[2..2]); + ram_block1a[123].portadatain[] = ( data_a[3..3]); + ram_block1a[124].portadatain[] = ( data_a[4..4]); + ram_block1a[125].portadatain[] = ( data_a[5..5]); + ram_block1a[126].portadatain[] = ( data_a[6..6]); + ram_block1a[127].portadatain[] = ( data_a[7..7]); + ram_block1a[127..0].portawe = ( decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[127..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[127..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[3..0] = address_b[16..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/altsyncram_qdq1.tdf b/proj_quartus/db/altsyncram_qdq1.tdf new file mode 100644 index 000000000..3a31e045c --- /dev/null +++ b/proj_quartus/db/altsyncram_qdq1.tdf @@ -0,0 +1,14916 @@ +--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=524288 NUMWORDS_B=524288 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=19 WIDTHAD_B=19 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + +FUNCTION decode_2na (data[5..0], enable) +RETURNS ( eq[63..0]); +FUNCTION mux_ihb (data[511..0], sel[5..0]) +RETURNS ( result[7..0]); +FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3) +RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 240 M10K 512 reg 6 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_qdq1 +( + address_a[18..0] : input; + address_b[18..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + address_reg_b[5..0] : dffe; + decode2 : decode_2na; + mux3 : mux_ihb; + ram_block1a0 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 8191, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 8192, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 16383, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 16384, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 24575, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 24576, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 32767, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 32768, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 40959, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 40960, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 49151, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 57343, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 49152, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 57343, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 57344, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 65535, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 57344, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 65535, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a64 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a65 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a66 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a67 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a68 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a69 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a70 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a71 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 65536, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 73727, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 65536, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 73727, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a72 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a73 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a74 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a75 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a76 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a77 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a78 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a79 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 73728, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 81919, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 73728, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 81919, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a80 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a81 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a82 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a83 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a84 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a85 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a86 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a87 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 81920, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 90111, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 81920, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 90111, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a88 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a89 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a90 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a91 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a92 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a93 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a94 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a95 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 90112, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 98303, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 90112, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 98303, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a96 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a97 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a98 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a99 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a100 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a101 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a102 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a103 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 98304, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 106495, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 98304, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 106495, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a104 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a105 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a106 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a107 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a108 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a109 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a110 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a111 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 106496, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 114687, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 106496, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 114687, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a112 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a113 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a114 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a115 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a116 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a117 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a118 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a119 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 114688, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 122879, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 114688, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 122879, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a120 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a121 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a122 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a123 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a124 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a125 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a126 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a127 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 122880, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 131071, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 122880, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 131071, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a128 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a129 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a130 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a131 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a132 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a133 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a134 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a135 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 131072, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 139263, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 131072, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 139263, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a136 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a137 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a138 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a139 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a140 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a141 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a142 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a143 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 139264, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 147455, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 139264, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 147455, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a144 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a145 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a146 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a147 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a148 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a149 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a150 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a151 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 147456, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 155647, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 147456, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 155647, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a152 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a153 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a154 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a155 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a156 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a157 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a158 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a159 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 155648, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 163839, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 155648, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 163839, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a160 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a161 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a162 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a163 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a164 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a165 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a166 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a167 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 163840, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 172031, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 163840, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 172031, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a168 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a169 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a170 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a171 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a172 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a173 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a174 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a175 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 172032, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 180223, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 172032, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 180223, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a176 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a177 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a178 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a179 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a180 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a181 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a182 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a183 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 180224, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 188415, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 180224, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 188415, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a184 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a185 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a186 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a187 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a188 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a189 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a190 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a191 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 188416, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 196607, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 188416, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 196607, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a192 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a193 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a194 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a195 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a196 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a197 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a198 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a199 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 196608, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 204799, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 196608, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 204799, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a200 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a201 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a202 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a203 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a204 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a205 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a206 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a207 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 204800, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 212991, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 204800, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 212991, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a208 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a209 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a210 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a211 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a212 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a213 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a214 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a215 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 212992, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 221183, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 212992, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 221183, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a216 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a217 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a218 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a219 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a220 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a221 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a222 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a223 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 221184, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 229375, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 221184, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 229375, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a224 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a225 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a226 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a227 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a228 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a229 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a230 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a231 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 229376, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 237567, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 229376, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 237567, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a232 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a233 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a234 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a235 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a236 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a237 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a238 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a239 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 237568, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 245759, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 237568, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 245759, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a240 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a241 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a242 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a243 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a244 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a245 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a246 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a247 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 245760, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 253951, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 245760, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 253951, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a248 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a249 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a250 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a251 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a252 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a253 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a254 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a255 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 253952, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 262143, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 253952, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 262143, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a256 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a257 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a258 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a259 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a260 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a261 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a262 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a263 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 262144, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 270335, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 262144, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 270335, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a264 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a265 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a266 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a267 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a268 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a269 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a270 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a271 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 270336, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 278527, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 270336, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 278527, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a272 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a273 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a274 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a275 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a276 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a277 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a278 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a279 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 278528, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 286719, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 278528, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 286719, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a280 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a281 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a282 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a283 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a284 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a285 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a286 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a287 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 286720, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 294911, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 286720, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 294911, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a288 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a289 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a290 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a291 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a292 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a293 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a294 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a295 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 294912, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 303103, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 294912, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 303103, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a296 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a297 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a298 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a299 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a300 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a301 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a302 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a303 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 303104, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 311295, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 303104, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 311295, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a304 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a305 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a306 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a307 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a308 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a309 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a310 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a311 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 311296, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 319487, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 311296, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 319487, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a312 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a313 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a314 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a315 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a316 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a317 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a318 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a319 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 319488, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 327679, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 319488, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 327679, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a320 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a321 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a322 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a323 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a324 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a325 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a326 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a327 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 327680, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 335871, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 327680, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 335871, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a328 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a329 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a330 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a331 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a332 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a333 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a334 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a335 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 335872, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 344063, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 335872, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 344063, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a336 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a337 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a338 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a339 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a340 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a341 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a342 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a343 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 344064, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 352255, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 344064, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 352255, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a344 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a345 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a346 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a347 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a348 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a349 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a350 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a351 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 352256, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 360447, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 352256, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 360447, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a352 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a353 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a354 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a355 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a356 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a357 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a358 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a359 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 360448, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 368639, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 360448, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 368639, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a360 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a361 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a362 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a363 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a364 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a365 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a366 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a367 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 368640, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 376831, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 368640, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 376831, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a368 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a369 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a370 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a371 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a372 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a373 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a374 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a375 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 376832, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 385023, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 376832, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 385023, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a376 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a377 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a378 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a379 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a380 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a381 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a382 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a383 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 385024, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 393215, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 385024, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 393215, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a384 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a385 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a386 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a387 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a388 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a389 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a390 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a391 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 393216, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 401407, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 393216, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 401407, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a392 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a393 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a394 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a395 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a396 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a397 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a398 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a399 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 401408, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 409599, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 401408, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 409599, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a400 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a401 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a402 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a403 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a404 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a405 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a406 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a407 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 409600, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 417791, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 409600, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 417791, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a408 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a409 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a410 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a411 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a412 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a413 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a414 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a415 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 417792, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 425983, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 417792, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 425983, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a416 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a417 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a418 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a419 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a420 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a421 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a422 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a423 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 425984, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 434175, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 425984, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 434175, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a424 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a425 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a426 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a427 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a428 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a429 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a430 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a431 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 434176, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 442367, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 434176, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 442367, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a432 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a433 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a434 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a435 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a436 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a437 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a438 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a439 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 442368, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 450559, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 442368, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 450559, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a440 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a441 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a442 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a443 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a444 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a445 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a446 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a447 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 450560, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 458751, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 450560, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 458751, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a448 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a449 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a450 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a451 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a452 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a453 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a454 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a455 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 458752, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 466943, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 458752, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 466943, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a456 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a457 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a458 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a459 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a460 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a461 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a462 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a463 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 466944, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 475135, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 466944, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 475135, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a464 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a465 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a466 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a467 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a468 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a469 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a470 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a471 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 475136, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 483327, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 475136, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 483327, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a472 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a473 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a474 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a475 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a476 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a477 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a478 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a479 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 483328, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 491519, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 483328, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 491519, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a480 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a481 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a482 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a483 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a484 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a485 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a486 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a487 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 491520, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 499711, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 491520, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 499711, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a488 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a489 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a490 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a491 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a492 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a493 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a494 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a495 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 499712, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 507903, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 499712, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 507903, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a496 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a497 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a498 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a499 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a500 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a501 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a502 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a503 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 507904, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 516095, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 507904, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 516095, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a504 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a505 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a506 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a507 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a508 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a509 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a510 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a511 : cyclonev_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 516096, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 524287, + PORT_A_LOGICAL_RAM_DEPTH = 524288, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 13, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 516096, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 524287, + PORT_B_LOGICAL_RAM_DEPTH = 524288, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[18..0] : WIRE; + address_b_sel[5..0] : WIRE; + address_b_wire[18..0] : WIRE; + +BEGIN + address_reg_b[].clk = clock0; + address_reg_b[].d = address_b_sel[]; + address_reg_b[].ena = rden_b; + decode2.data[5..0] = address_a_wire[18..13]; + decode2.enable = wren_a; + mux3.data[] = ( ram_block1a[511..0].portbdataout[0..0]); + mux3.sel[] = address_reg_b[].q; + ram_block1a[511..0].clk0 = clock0; + ram_block1a[511..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[0..0]); + ram_block1a[9].portadatain[] = ( data_a[1..1]); + ram_block1a[10].portadatain[] = ( data_a[2..2]); + ram_block1a[11].portadatain[] = ( data_a[3..3]); + ram_block1a[12].portadatain[] = ( data_a[4..4]); + ram_block1a[13].portadatain[] = ( data_a[5..5]); + ram_block1a[14].portadatain[] = ( data_a[6..6]); + ram_block1a[15].portadatain[] = ( data_a[7..7]); + ram_block1a[16].portadatain[] = ( data_a[0..0]); + ram_block1a[17].portadatain[] = ( data_a[1..1]); + ram_block1a[18].portadatain[] = ( data_a[2..2]); + ram_block1a[19].portadatain[] = ( data_a[3..3]); + ram_block1a[20].portadatain[] = ( data_a[4..4]); + ram_block1a[21].portadatain[] = ( data_a[5..5]); + ram_block1a[22].portadatain[] = ( data_a[6..6]); + ram_block1a[23].portadatain[] = ( data_a[7..7]); + ram_block1a[24].portadatain[] = ( data_a[0..0]); + ram_block1a[25].portadatain[] = ( data_a[1..1]); + ram_block1a[26].portadatain[] = ( data_a[2..2]); + ram_block1a[27].portadatain[] = ( data_a[3..3]); + ram_block1a[28].portadatain[] = ( data_a[4..4]); + ram_block1a[29].portadatain[] = ( data_a[5..5]); + ram_block1a[30].portadatain[] = ( data_a[6..6]); + ram_block1a[31].portadatain[] = ( data_a[7..7]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[0..0]); + ram_block1a[41].portadatain[] = ( data_a[1..1]); + ram_block1a[42].portadatain[] = ( data_a[2..2]); + ram_block1a[43].portadatain[] = ( data_a[3..3]); + ram_block1a[44].portadatain[] = ( data_a[4..4]); + ram_block1a[45].portadatain[] = ( data_a[5..5]); + ram_block1a[46].portadatain[] = ( data_a[6..6]); + ram_block1a[47].portadatain[] = ( data_a[7..7]); + ram_block1a[48].portadatain[] = ( data_a[0..0]); + ram_block1a[49].portadatain[] = ( data_a[1..1]); + ram_block1a[50].portadatain[] = ( data_a[2..2]); + ram_block1a[51].portadatain[] = ( data_a[3..3]); + ram_block1a[52].portadatain[] = ( data_a[4..4]); + ram_block1a[53].portadatain[] = ( data_a[5..5]); + ram_block1a[54].portadatain[] = ( data_a[6..6]); + ram_block1a[55].portadatain[] = ( data_a[7..7]); + ram_block1a[56].portadatain[] = ( data_a[0..0]); + ram_block1a[57].portadatain[] = ( data_a[1..1]); + ram_block1a[58].portadatain[] = ( data_a[2..2]); + ram_block1a[59].portadatain[] = ( data_a[3..3]); + ram_block1a[60].portadatain[] = ( data_a[4..4]); + ram_block1a[61].portadatain[] = ( data_a[5..5]); + ram_block1a[62].portadatain[] = ( data_a[6..6]); + ram_block1a[63].portadatain[] = ( data_a[7..7]); + ram_block1a[64].portadatain[] = ( data_a[0..0]); + ram_block1a[65].portadatain[] = ( data_a[1..1]); + ram_block1a[66].portadatain[] = ( data_a[2..2]); + ram_block1a[67].portadatain[] = ( data_a[3..3]); + ram_block1a[68].portadatain[] = ( data_a[4..4]); + ram_block1a[69].portadatain[] = ( data_a[5..5]); + ram_block1a[70].portadatain[] = ( data_a[6..6]); + ram_block1a[71].portadatain[] = ( data_a[7..7]); + ram_block1a[72].portadatain[] = ( data_a[0..0]); + ram_block1a[73].portadatain[] = ( data_a[1..1]); + ram_block1a[74].portadatain[] = ( data_a[2..2]); + ram_block1a[75].portadatain[] = ( data_a[3..3]); + ram_block1a[76].portadatain[] = ( data_a[4..4]); + ram_block1a[77].portadatain[] = ( data_a[5..5]); + ram_block1a[78].portadatain[] = ( data_a[6..6]); + ram_block1a[79].portadatain[] = ( data_a[7..7]); + ram_block1a[80].portadatain[] = ( data_a[0..0]); + ram_block1a[81].portadatain[] = ( data_a[1..1]); + ram_block1a[82].portadatain[] = ( data_a[2..2]); + ram_block1a[83].portadatain[] = ( data_a[3..3]); + ram_block1a[84].portadatain[] = ( data_a[4..4]); + ram_block1a[85].portadatain[] = ( data_a[5..5]); + ram_block1a[86].portadatain[] = ( data_a[6..6]); + ram_block1a[87].portadatain[] = ( data_a[7..7]); + ram_block1a[88].portadatain[] = ( data_a[0..0]); + ram_block1a[89].portadatain[] = ( data_a[1..1]); + ram_block1a[90].portadatain[] = ( data_a[2..2]); + ram_block1a[91].portadatain[] = ( data_a[3..3]); + ram_block1a[92].portadatain[] = ( data_a[4..4]); + ram_block1a[93].portadatain[] = ( data_a[5..5]); + ram_block1a[94].portadatain[] = ( data_a[6..6]); + ram_block1a[95].portadatain[] = ( data_a[7..7]); + ram_block1a[96].portadatain[] = ( data_a[0..0]); + ram_block1a[97].portadatain[] = ( data_a[1..1]); + ram_block1a[98].portadatain[] = ( data_a[2..2]); + ram_block1a[99].portadatain[] = ( data_a[3..3]); + ram_block1a[100].portadatain[] = ( data_a[4..4]); + ram_block1a[101].portadatain[] = ( data_a[5..5]); + ram_block1a[102].portadatain[] = ( data_a[6..6]); + ram_block1a[103].portadatain[] = ( data_a[7..7]); + ram_block1a[104].portadatain[] = ( data_a[0..0]); + ram_block1a[105].portadatain[] = ( data_a[1..1]); + ram_block1a[106].portadatain[] = ( data_a[2..2]); + ram_block1a[107].portadatain[] = ( data_a[3..3]); + ram_block1a[108].portadatain[] = ( data_a[4..4]); + ram_block1a[109].portadatain[] = ( data_a[5..5]); + ram_block1a[110].portadatain[] = ( data_a[6..6]); + ram_block1a[111].portadatain[] = ( data_a[7..7]); + ram_block1a[112].portadatain[] = ( data_a[0..0]); + ram_block1a[113].portadatain[] = ( data_a[1..1]); + ram_block1a[114].portadatain[] = ( data_a[2..2]); + ram_block1a[115].portadatain[] = ( data_a[3..3]); + ram_block1a[116].portadatain[] = ( data_a[4..4]); + ram_block1a[117].portadatain[] = ( data_a[5..5]); + ram_block1a[118].portadatain[] = ( data_a[6..6]); + ram_block1a[119].portadatain[] = ( data_a[7..7]); + ram_block1a[120].portadatain[] = ( data_a[0..0]); + ram_block1a[121].portadatain[] = ( data_a[1..1]); + ram_block1a[122].portadatain[] = ( data_a[2..2]); + ram_block1a[123].portadatain[] = ( data_a[3..3]); + ram_block1a[124].portadatain[] = ( data_a[4..4]); + ram_block1a[125].portadatain[] = ( data_a[5..5]); + ram_block1a[126].portadatain[] = ( data_a[6..6]); + ram_block1a[127].portadatain[] = ( data_a[7..7]); + ram_block1a[128].portadatain[] = ( data_a[0..0]); + ram_block1a[129].portadatain[] = ( data_a[1..1]); + ram_block1a[130].portadatain[] = ( data_a[2..2]); + ram_block1a[131].portadatain[] = ( data_a[3..3]); + ram_block1a[132].portadatain[] = ( data_a[4..4]); + ram_block1a[133].portadatain[] = ( data_a[5..5]); + ram_block1a[134].portadatain[] = ( data_a[6..6]); + ram_block1a[135].portadatain[] = ( data_a[7..7]); + ram_block1a[136].portadatain[] = ( data_a[0..0]); + ram_block1a[137].portadatain[] = ( data_a[1..1]); + ram_block1a[138].portadatain[] = ( data_a[2..2]); + ram_block1a[139].portadatain[] = ( data_a[3..3]); + ram_block1a[140].portadatain[] = ( data_a[4..4]); + ram_block1a[141].portadatain[] = ( data_a[5..5]); + ram_block1a[142].portadatain[] = ( data_a[6..6]); + ram_block1a[143].portadatain[] = ( data_a[7..7]); + ram_block1a[144].portadatain[] = ( data_a[0..0]); + ram_block1a[145].portadatain[] = ( data_a[1..1]); + ram_block1a[146].portadatain[] = ( data_a[2..2]); + ram_block1a[147].portadatain[] = ( data_a[3..3]); + ram_block1a[148].portadatain[] = ( data_a[4..4]); + ram_block1a[149].portadatain[] = ( data_a[5..5]); + ram_block1a[150].portadatain[] = ( data_a[6..6]); + ram_block1a[151].portadatain[] = ( data_a[7..7]); + ram_block1a[152].portadatain[] = ( data_a[0..0]); + ram_block1a[153].portadatain[] = ( data_a[1..1]); + ram_block1a[154].portadatain[] = ( data_a[2..2]); + ram_block1a[155].portadatain[] = ( data_a[3..3]); + ram_block1a[156].portadatain[] = ( data_a[4..4]); + ram_block1a[157].portadatain[] = ( data_a[5..5]); + ram_block1a[158].portadatain[] = ( data_a[6..6]); + ram_block1a[159].portadatain[] = ( data_a[7..7]); + ram_block1a[160].portadatain[] = ( data_a[0..0]); + ram_block1a[161].portadatain[] = ( data_a[1..1]); + ram_block1a[162].portadatain[] = ( data_a[2..2]); + ram_block1a[163].portadatain[] = ( data_a[3..3]); + ram_block1a[164].portadatain[] = ( data_a[4..4]); + ram_block1a[165].portadatain[] = ( data_a[5..5]); + ram_block1a[166].portadatain[] = ( data_a[6..6]); + ram_block1a[167].portadatain[] = ( data_a[7..7]); + ram_block1a[168].portadatain[] = ( data_a[0..0]); + ram_block1a[169].portadatain[] = ( data_a[1..1]); + ram_block1a[170].portadatain[] = ( data_a[2..2]); + ram_block1a[171].portadatain[] = ( data_a[3..3]); + ram_block1a[172].portadatain[] = ( data_a[4..4]); + ram_block1a[173].portadatain[] = ( data_a[5..5]); + ram_block1a[174].portadatain[] = ( data_a[6..6]); + ram_block1a[175].portadatain[] = ( data_a[7..7]); + ram_block1a[176].portadatain[] = ( data_a[0..0]); + ram_block1a[177].portadatain[] = ( data_a[1..1]); + ram_block1a[178].portadatain[] = ( data_a[2..2]); + ram_block1a[179].portadatain[] = ( data_a[3..3]); + ram_block1a[180].portadatain[] = ( data_a[4..4]); + ram_block1a[181].portadatain[] = ( data_a[5..5]); + ram_block1a[182].portadatain[] = ( data_a[6..6]); + ram_block1a[183].portadatain[] = ( data_a[7..7]); + ram_block1a[184].portadatain[] = ( data_a[0..0]); + ram_block1a[185].portadatain[] = ( data_a[1..1]); + ram_block1a[186].portadatain[] = ( data_a[2..2]); + ram_block1a[187].portadatain[] = ( data_a[3..3]); + ram_block1a[188].portadatain[] = ( data_a[4..4]); + ram_block1a[189].portadatain[] = ( data_a[5..5]); + ram_block1a[190].portadatain[] = ( data_a[6..6]); + ram_block1a[191].portadatain[] = ( data_a[7..7]); + ram_block1a[192].portadatain[] = ( data_a[0..0]); + ram_block1a[193].portadatain[] = ( data_a[1..1]); + ram_block1a[194].portadatain[] = ( data_a[2..2]); + ram_block1a[195].portadatain[] = ( data_a[3..3]); + ram_block1a[196].portadatain[] = ( data_a[4..4]); + ram_block1a[197].portadatain[] = ( data_a[5..5]); + ram_block1a[198].portadatain[] = ( data_a[6..6]); + ram_block1a[199].portadatain[] = ( data_a[7..7]); + ram_block1a[200].portadatain[] = ( data_a[0..0]); + ram_block1a[201].portadatain[] = ( data_a[1..1]); + ram_block1a[202].portadatain[] = ( data_a[2..2]); + ram_block1a[203].portadatain[] = ( data_a[3..3]); + ram_block1a[204].portadatain[] = ( data_a[4..4]); + ram_block1a[205].portadatain[] = ( data_a[5..5]); + ram_block1a[206].portadatain[] = ( data_a[6..6]); + ram_block1a[207].portadatain[] = ( data_a[7..7]); + ram_block1a[208].portadatain[] = ( data_a[0..0]); + ram_block1a[209].portadatain[] = ( data_a[1..1]); + ram_block1a[210].portadatain[] = ( data_a[2..2]); + ram_block1a[211].portadatain[] = ( data_a[3..3]); + ram_block1a[212].portadatain[] = ( data_a[4..4]); + ram_block1a[213].portadatain[] = ( data_a[5..5]); + ram_block1a[214].portadatain[] = ( data_a[6..6]); + ram_block1a[215].portadatain[] = ( data_a[7..7]); + ram_block1a[216].portadatain[] = ( data_a[0..0]); + ram_block1a[217].portadatain[] = ( data_a[1..1]); + ram_block1a[218].portadatain[] = ( data_a[2..2]); + ram_block1a[219].portadatain[] = ( data_a[3..3]); + ram_block1a[220].portadatain[] = ( data_a[4..4]); + ram_block1a[221].portadatain[] = ( data_a[5..5]); + ram_block1a[222].portadatain[] = ( data_a[6..6]); + ram_block1a[223].portadatain[] = ( data_a[7..7]); + ram_block1a[224].portadatain[] = ( data_a[0..0]); + ram_block1a[225].portadatain[] = ( data_a[1..1]); + ram_block1a[226].portadatain[] = ( data_a[2..2]); + ram_block1a[227].portadatain[] = ( data_a[3..3]); + ram_block1a[228].portadatain[] = ( data_a[4..4]); + ram_block1a[229].portadatain[] = ( data_a[5..5]); + ram_block1a[230].portadatain[] = ( data_a[6..6]); + ram_block1a[231].portadatain[] = ( data_a[7..7]); + ram_block1a[232].portadatain[] = ( data_a[0..0]); + ram_block1a[233].portadatain[] = ( data_a[1..1]); + ram_block1a[234].portadatain[] = ( data_a[2..2]); + ram_block1a[235].portadatain[] = ( data_a[3..3]); + ram_block1a[236].portadatain[] = ( data_a[4..4]); + ram_block1a[237].portadatain[] = ( data_a[5..5]); + ram_block1a[238].portadatain[] = ( data_a[6..6]); + ram_block1a[239].portadatain[] = ( data_a[7..7]); + ram_block1a[240].portadatain[] = ( data_a[0..0]); + ram_block1a[241].portadatain[] = ( data_a[1..1]); + ram_block1a[242].portadatain[] = ( data_a[2..2]); + ram_block1a[243].portadatain[] = ( data_a[3..3]); + ram_block1a[244].portadatain[] = ( data_a[4..4]); + ram_block1a[245].portadatain[] = ( data_a[5..5]); + ram_block1a[246].portadatain[] = ( data_a[6..6]); + ram_block1a[247].portadatain[] = ( data_a[7..7]); + ram_block1a[248].portadatain[] = ( data_a[0..0]); + ram_block1a[249].portadatain[] = ( data_a[1..1]); + ram_block1a[250].portadatain[] = ( data_a[2..2]); + ram_block1a[251].portadatain[] = ( data_a[3..3]); + ram_block1a[252].portadatain[] = ( data_a[4..4]); + ram_block1a[253].portadatain[] = ( data_a[5..5]); + ram_block1a[254].portadatain[] = ( data_a[6..6]); + ram_block1a[255].portadatain[] = ( data_a[7..7]); + ram_block1a[256].portadatain[] = ( data_a[0..0]); + ram_block1a[257].portadatain[] = ( data_a[1..1]); + ram_block1a[258].portadatain[] = ( data_a[2..2]); + ram_block1a[259].portadatain[] = ( data_a[3..3]); + ram_block1a[260].portadatain[] = ( data_a[4..4]); + ram_block1a[261].portadatain[] = ( data_a[5..5]); + ram_block1a[262].portadatain[] = ( data_a[6..6]); + ram_block1a[263].portadatain[] = ( data_a[7..7]); + ram_block1a[264].portadatain[] = ( data_a[0..0]); + ram_block1a[265].portadatain[] = ( data_a[1..1]); + ram_block1a[266].portadatain[] = ( data_a[2..2]); + ram_block1a[267].portadatain[] = ( data_a[3..3]); + ram_block1a[268].portadatain[] = ( data_a[4..4]); + ram_block1a[269].portadatain[] = ( data_a[5..5]); + ram_block1a[270].portadatain[] = ( data_a[6..6]); + ram_block1a[271].portadatain[] = ( data_a[7..7]); + ram_block1a[272].portadatain[] = ( data_a[0..0]); + ram_block1a[273].portadatain[] = ( data_a[1..1]); + ram_block1a[274].portadatain[] = ( data_a[2..2]); + ram_block1a[275].portadatain[] = ( data_a[3..3]); + ram_block1a[276].portadatain[] = ( data_a[4..4]); + ram_block1a[277].portadatain[] = ( data_a[5..5]); + ram_block1a[278].portadatain[] = ( data_a[6..6]); + ram_block1a[279].portadatain[] = ( data_a[7..7]); + ram_block1a[280].portadatain[] = ( data_a[0..0]); + ram_block1a[281].portadatain[] = ( data_a[1..1]); + ram_block1a[282].portadatain[] = ( data_a[2..2]); + ram_block1a[283].portadatain[] = ( data_a[3..3]); + ram_block1a[284].portadatain[] = ( data_a[4..4]); + ram_block1a[285].portadatain[] = ( data_a[5..5]); + ram_block1a[286].portadatain[] = ( data_a[6..6]); + ram_block1a[287].portadatain[] = ( data_a[7..7]); + ram_block1a[288].portadatain[] = ( data_a[0..0]); + ram_block1a[289].portadatain[] = ( data_a[1..1]); + ram_block1a[290].portadatain[] = ( data_a[2..2]); + ram_block1a[291].portadatain[] = ( data_a[3..3]); + ram_block1a[292].portadatain[] = ( data_a[4..4]); + ram_block1a[293].portadatain[] = ( data_a[5..5]); + ram_block1a[294].portadatain[] = ( data_a[6..6]); + ram_block1a[295].portadatain[] = ( data_a[7..7]); + ram_block1a[296].portadatain[] = ( data_a[0..0]); + ram_block1a[297].portadatain[] = ( data_a[1..1]); + ram_block1a[298].portadatain[] = ( data_a[2..2]); + ram_block1a[299].portadatain[] = ( data_a[3..3]); + ram_block1a[300].portadatain[] = ( data_a[4..4]); + ram_block1a[301].portadatain[] = ( data_a[5..5]); + ram_block1a[302].portadatain[] = ( data_a[6..6]); + ram_block1a[303].portadatain[] = ( data_a[7..7]); + ram_block1a[304].portadatain[] = ( data_a[0..0]); + ram_block1a[305].portadatain[] = ( data_a[1..1]); + ram_block1a[306].portadatain[] = ( data_a[2..2]); + ram_block1a[307].portadatain[] = ( data_a[3..3]); + ram_block1a[308].portadatain[] = ( data_a[4..4]); + ram_block1a[309].portadatain[] = ( data_a[5..5]); + ram_block1a[310].portadatain[] = ( data_a[6..6]); + ram_block1a[311].portadatain[] = ( data_a[7..7]); + ram_block1a[312].portadatain[] = ( data_a[0..0]); + ram_block1a[313].portadatain[] = ( data_a[1..1]); + ram_block1a[314].portadatain[] = ( data_a[2..2]); + ram_block1a[315].portadatain[] = ( data_a[3..3]); + ram_block1a[316].portadatain[] = ( data_a[4..4]); + ram_block1a[317].portadatain[] = ( data_a[5..5]); + ram_block1a[318].portadatain[] = ( data_a[6..6]); + ram_block1a[319].portadatain[] = ( data_a[7..7]); + ram_block1a[320].portadatain[] = ( data_a[0..0]); + ram_block1a[321].portadatain[] = ( data_a[1..1]); + ram_block1a[322].portadatain[] = ( data_a[2..2]); + ram_block1a[323].portadatain[] = ( data_a[3..3]); + ram_block1a[324].portadatain[] = ( data_a[4..4]); + ram_block1a[325].portadatain[] = ( data_a[5..5]); + ram_block1a[326].portadatain[] = ( data_a[6..6]); + ram_block1a[327].portadatain[] = ( data_a[7..7]); + ram_block1a[328].portadatain[] = ( data_a[0..0]); + ram_block1a[329].portadatain[] = ( data_a[1..1]); + ram_block1a[330].portadatain[] = ( data_a[2..2]); + ram_block1a[331].portadatain[] = ( data_a[3..3]); + ram_block1a[332].portadatain[] = ( data_a[4..4]); + ram_block1a[333].portadatain[] = ( data_a[5..5]); + ram_block1a[334].portadatain[] = ( data_a[6..6]); + ram_block1a[335].portadatain[] = ( data_a[7..7]); + ram_block1a[336].portadatain[] = ( data_a[0..0]); + ram_block1a[337].portadatain[] = ( data_a[1..1]); + ram_block1a[338].portadatain[] = ( data_a[2..2]); + ram_block1a[339].portadatain[] = ( data_a[3..3]); + ram_block1a[340].portadatain[] = ( data_a[4..4]); + ram_block1a[341].portadatain[] = ( data_a[5..5]); + ram_block1a[342].portadatain[] = ( data_a[6..6]); + ram_block1a[343].portadatain[] = ( data_a[7..7]); + ram_block1a[344].portadatain[] = ( data_a[0..0]); + ram_block1a[345].portadatain[] = ( data_a[1..1]); + ram_block1a[346].portadatain[] = ( data_a[2..2]); + ram_block1a[347].portadatain[] = ( data_a[3..3]); + ram_block1a[348].portadatain[] = ( data_a[4..4]); + ram_block1a[349].portadatain[] = ( data_a[5..5]); + ram_block1a[350].portadatain[] = ( data_a[6..6]); + ram_block1a[351].portadatain[] = ( data_a[7..7]); + ram_block1a[352].portadatain[] = ( data_a[0..0]); + ram_block1a[353].portadatain[] = ( data_a[1..1]); + ram_block1a[354].portadatain[] = ( data_a[2..2]); + ram_block1a[355].portadatain[] = ( data_a[3..3]); + ram_block1a[356].portadatain[] = ( data_a[4..4]); + ram_block1a[357].portadatain[] = ( data_a[5..5]); + ram_block1a[358].portadatain[] = ( data_a[6..6]); + ram_block1a[359].portadatain[] = ( data_a[7..7]); + ram_block1a[360].portadatain[] = ( data_a[0..0]); + ram_block1a[361].portadatain[] = ( data_a[1..1]); + ram_block1a[362].portadatain[] = ( data_a[2..2]); + ram_block1a[363].portadatain[] = ( data_a[3..3]); + ram_block1a[364].portadatain[] = ( data_a[4..4]); + ram_block1a[365].portadatain[] = ( data_a[5..5]); + ram_block1a[366].portadatain[] = ( data_a[6..6]); + ram_block1a[367].portadatain[] = ( data_a[7..7]); + ram_block1a[368].portadatain[] = ( data_a[0..0]); + ram_block1a[369].portadatain[] = ( data_a[1..1]); + ram_block1a[370].portadatain[] = ( data_a[2..2]); + ram_block1a[371].portadatain[] = ( data_a[3..3]); + ram_block1a[372].portadatain[] = ( data_a[4..4]); + ram_block1a[373].portadatain[] = ( data_a[5..5]); + ram_block1a[374].portadatain[] = ( data_a[6..6]); + ram_block1a[375].portadatain[] = ( data_a[7..7]); + ram_block1a[376].portadatain[] = ( data_a[0..0]); + ram_block1a[377].portadatain[] = ( data_a[1..1]); + ram_block1a[378].portadatain[] = ( data_a[2..2]); + ram_block1a[379].portadatain[] = ( data_a[3..3]); + ram_block1a[380].portadatain[] = ( data_a[4..4]); + ram_block1a[381].portadatain[] = ( data_a[5..5]); + ram_block1a[382].portadatain[] = ( data_a[6..6]); + ram_block1a[383].portadatain[] = ( data_a[7..7]); + ram_block1a[384].portadatain[] = ( data_a[0..0]); + ram_block1a[385].portadatain[] = ( data_a[1..1]); + ram_block1a[386].portadatain[] = ( data_a[2..2]); + ram_block1a[387].portadatain[] = ( data_a[3..3]); + ram_block1a[388].portadatain[] = ( data_a[4..4]); + ram_block1a[389].portadatain[] = ( data_a[5..5]); + ram_block1a[390].portadatain[] = ( data_a[6..6]); + ram_block1a[391].portadatain[] = ( data_a[7..7]); + ram_block1a[392].portadatain[] = ( data_a[0..0]); + ram_block1a[393].portadatain[] = ( data_a[1..1]); + ram_block1a[394].portadatain[] = ( data_a[2..2]); + ram_block1a[395].portadatain[] = ( data_a[3..3]); + ram_block1a[396].portadatain[] = ( data_a[4..4]); + ram_block1a[397].portadatain[] = ( data_a[5..5]); + ram_block1a[398].portadatain[] = ( data_a[6..6]); + ram_block1a[399].portadatain[] = ( data_a[7..7]); + ram_block1a[400].portadatain[] = ( data_a[0..0]); + ram_block1a[401].portadatain[] = ( data_a[1..1]); + ram_block1a[402].portadatain[] = ( data_a[2..2]); + ram_block1a[403].portadatain[] = ( data_a[3..3]); + ram_block1a[404].portadatain[] = ( data_a[4..4]); + ram_block1a[405].portadatain[] = ( data_a[5..5]); + ram_block1a[406].portadatain[] = ( data_a[6..6]); + ram_block1a[407].portadatain[] = ( data_a[7..7]); + ram_block1a[408].portadatain[] = ( data_a[0..0]); + ram_block1a[409].portadatain[] = ( data_a[1..1]); + ram_block1a[410].portadatain[] = ( data_a[2..2]); + ram_block1a[411].portadatain[] = ( data_a[3..3]); + ram_block1a[412].portadatain[] = ( data_a[4..4]); + ram_block1a[413].portadatain[] = ( data_a[5..5]); + ram_block1a[414].portadatain[] = ( data_a[6..6]); + ram_block1a[415].portadatain[] = ( data_a[7..7]); + ram_block1a[416].portadatain[] = ( data_a[0..0]); + ram_block1a[417].portadatain[] = ( data_a[1..1]); + ram_block1a[418].portadatain[] = ( data_a[2..2]); + ram_block1a[419].portadatain[] = ( data_a[3..3]); + ram_block1a[420].portadatain[] = ( data_a[4..4]); + ram_block1a[421].portadatain[] = ( data_a[5..5]); + ram_block1a[422].portadatain[] = ( data_a[6..6]); + ram_block1a[423].portadatain[] = ( data_a[7..7]); + ram_block1a[424].portadatain[] = ( data_a[0..0]); + ram_block1a[425].portadatain[] = ( data_a[1..1]); + ram_block1a[426].portadatain[] = ( data_a[2..2]); + ram_block1a[427].portadatain[] = ( data_a[3..3]); + ram_block1a[428].portadatain[] = ( data_a[4..4]); + ram_block1a[429].portadatain[] = ( data_a[5..5]); + ram_block1a[430].portadatain[] = ( data_a[6..6]); + ram_block1a[431].portadatain[] = ( data_a[7..7]); + ram_block1a[432].portadatain[] = ( data_a[0..0]); + ram_block1a[433].portadatain[] = ( data_a[1..1]); + ram_block1a[434].portadatain[] = ( data_a[2..2]); + ram_block1a[435].portadatain[] = ( data_a[3..3]); + ram_block1a[436].portadatain[] = ( data_a[4..4]); + ram_block1a[437].portadatain[] = ( data_a[5..5]); + ram_block1a[438].portadatain[] = ( data_a[6..6]); + ram_block1a[439].portadatain[] = ( data_a[7..7]); + ram_block1a[440].portadatain[] = ( data_a[0..0]); + ram_block1a[441].portadatain[] = ( data_a[1..1]); + ram_block1a[442].portadatain[] = ( data_a[2..2]); + ram_block1a[443].portadatain[] = ( data_a[3..3]); + ram_block1a[444].portadatain[] = ( data_a[4..4]); + ram_block1a[445].portadatain[] = ( data_a[5..5]); + ram_block1a[446].portadatain[] = ( data_a[6..6]); + ram_block1a[447].portadatain[] = ( data_a[7..7]); + ram_block1a[448].portadatain[] = ( data_a[0..0]); + ram_block1a[449].portadatain[] = ( data_a[1..1]); + ram_block1a[450].portadatain[] = ( data_a[2..2]); + ram_block1a[451].portadatain[] = ( data_a[3..3]); + ram_block1a[452].portadatain[] = ( data_a[4..4]); + ram_block1a[453].portadatain[] = ( data_a[5..5]); + ram_block1a[454].portadatain[] = ( data_a[6..6]); + ram_block1a[455].portadatain[] = ( data_a[7..7]); + ram_block1a[456].portadatain[] = ( data_a[0..0]); + ram_block1a[457].portadatain[] = ( data_a[1..1]); + ram_block1a[458].portadatain[] = ( data_a[2..2]); + ram_block1a[459].portadatain[] = ( data_a[3..3]); + ram_block1a[460].portadatain[] = ( data_a[4..4]); + ram_block1a[461].portadatain[] = ( data_a[5..5]); + ram_block1a[462].portadatain[] = ( data_a[6..6]); + ram_block1a[463].portadatain[] = ( data_a[7..7]); + ram_block1a[464].portadatain[] = ( data_a[0..0]); + ram_block1a[465].portadatain[] = ( data_a[1..1]); + ram_block1a[466].portadatain[] = ( data_a[2..2]); + ram_block1a[467].portadatain[] = ( data_a[3..3]); + ram_block1a[468].portadatain[] = ( data_a[4..4]); + ram_block1a[469].portadatain[] = ( data_a[5..5]); + ram_block1a[470].portadatain[] = ( data_a[6..6]); + ram_block1a[471].portadatain[] = ( data_a[7..7]); + ram_block1a[472].portadatain[] = ( data_a[0..0]); + ram_block1a[473].portadatain[] = ( data_a[1..1]); + ram_block1a[474].portadatain[] = ( data_a[2..2]); + ram_block1a[475].portadatain[] = ( data_a[3..3]); + ram_block1a[476].portadatain[] = ( data_a[4..4]); + ram_block1a[477].portadatain[] = ( data_a[5..5]); + ram_block1a[478].portadatain[] = ( data_a[6..6]); + ram_block1a[479].portadatain[] = ( data_a[7..7]); + ram_block1a[480].portadatain[] = ( data_a[0..0]); + ram_block1a[481].portadatain[] = ( data_a[1..1]); + ram_block1a[482].portadatain[] = ( data_a[2..2]); + ram_block1a[483].portadatain[] = ( data_a[3..3]); + ram_block1a[484].portadatain[] = ( data_a[4..4]); + ram_block1a[485].portadatain[] = ( data_a[5..5]); + ram_block1a[486].portadatain[] = ( data_a[6..6]); + ram_block1a[487].portadatain[] = ( data_a[7..7]); + ram_block1a[488].portadatain[] = ( data_a[0..0]); + ram_block1a[489].portadatain[] = ( data_a[1..1]); + ram_block1a[490].portadatain[] = ( data_a[2..2]); + ram_block1a[491].portadatain[] = ( data_a[3..3]); + ram_block1a[492].portadatain[] = ( data_a[4..4]); + ram_block1a[493].portadatain[] = ( data_a[5..5]); + ram_block1a[494].portadatain[] = ( data_a[6..6]); + ram_block1a[495].portadatain[] = ( data_a[7..7]); + ram_block1a[496].portadatain[] = ( data_a[0..0]); + ram_block1a[497].portadatain[] = ( data_a[1..1]); + ram_block1a[498].portadatain[] = ( data_a[2..2]); + ram_block1a[499].portadatain[] = ( data_a[3..3]); + ram_block1a[500].portadatain[] = ( data_a[4..4]); + ram_block1a[501].portadatain[] = ( data_a[5..5]); + ram_block1a[502].portadatain[] = ( data_a[6..6]); + ram_block1a[503].portadatain[] = ( data_a[7..7]); + ram_block1a[504].portadatain[] = ( data_a[0..0]); + ram_block1a[505].portadatain[] = ( data_a[1..1]); + ram_block1a[506].portadatain[] = ( data_a[2..2]); + ram_block1a[507].portadatain[] = ( data_a[3..3]); + ram_block1a[508].portadatain[] = ( data_a[4..4]); + ram_block1a[509].portadatain[] = ( data_a[5..5]); + ram_block1a[510].portadatain[] = ( data_a[6..6]); + ram_block1a[511].portadatain[] = ( data_a[7..7]); + ram_block1a[511..0].portawe = ( decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]); + ram_block1a[511..0].portbaddr[] = ( address_b_wire[12..0]); + ram_block1a[511..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_sel[5..0] = address_b[18..13]; + address_b_wire[] = address_b[]; + q_b[] = mux3.result[]; +END; +--VALID FILE diff --git a/proj_quartus/db/decode_2na.tdf b/proj_quartus/db/decode_2na.tdf new file mode 100644 index 000000000..535e9b722 --- /dev/null +++ b/proj_quartus/db/decode_2na.tdf @@ -0,0 +1,188 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=64 LPM_WIDTH=6 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 72 +SUBDESIGN decode_2na +( + data[5..0] : input; + enable : input; + eq[63..0] : output; +) +VARIABLE + data_wire[5..0] : WIRE; + enable_wire : WIRE; + eq_node[63..0] : WIRE; + eq_wire[63..0] : WIRE; + w_anode4241w[3..0] : WIRE; + w_anode4258w[3..0] : WIRE; + w_anode4275w[3..0] : WIRE; + w_anode4285w[3..0] : WIRE; + w_anode4295w[3..0] : WIRE; + w_anode4305w[3..0] : WIRE; + w_anode4315w[3..0] : WIRE; + w_anode4325w[3..0] : WIRE; + w_anode4335w[3..0] : WIRE; + w_anode4347w[3..0] : WIRE; + w_anode4358w[3..0] : WIRE; + w_anode4369w[3..0] : WIRE; + w_anode4379w[3..0] : WIRE; + w_anode4389w[3..0] : WIRE; + w_anode4399w[3..0] : WIRE; + w_anode4409w[3..0] : WIRE; + w_anode4419w[3..0] : WIRE; + w_anode4429w[3..0] : WIRE; + w_anode4440w[3..0] : WIRE; + w_anode4451w[3..0] : WIRE; + w_anode4462w[3..0] : WIRE; + w_anode4472w[3..0] : WIRE; + w_anode4482w[3..0] : WIRE; + w_anode4492w[3..0] : WIRE; + w_anode4502w[3..0] : WIRE; + w_anode4512w[3..0] : WIRE; + w_anode4522w[3..0] : WIRE; + w_anode4533w[3..0] : WIRE; + w_anode4544w[3..0] : WIRE; + w_anode4555w[3..0] : WIRE; + w_anode4565w[3..0] : WIRE; + w_anode4575w[3..0] : WIRE; + w_anode4585w[3..0] : WIRE; + w_anode4595w[3..0] : WIRE; + w_anode4605w[3..0] : WIRE; + w_anode4615w[3..0] : WIRE; + w_anode4626w[3..0] : WIRE; + w_anode4637w[3..0] : WIRE; + w_anode4648w[3..0] : WIRE; + w_anode4658w[3..0] : WIRE; + w_anode4668w[3..0] : WIRE; + w_anode4678w[3..0] : WIRE; + w_anode4688w[3..0] : WIRE; + w_anode4698w[3..0] : WIRE; + w_anode4708w[3..0] : WIRE; + w_anode4719w[3..0] : WIRE; + w_anode4730w[3..0] : WIRE; + w_anode4741w[3..0] : WIRE; + w_anode4751w[3..0] : WIRE; + w_anode4761w[3..0] : WIRE; + w_anode4771w[3..0] : WIRE; + w_anode4781w[3..0] : WIRE; + w_anode4791w[3..0] : WIRE; + w_anode4801w[3..0] : WIRE; + w_anode4812w[3..0] : WIRE; + w_anode4823w[3..0] : WIRE; + w_anode4834w[3..0] : WIRE; + w_anode4844w[3..0] : WIRE; + w_anode4854w[3..0] : WIRE; + w_anode4864w[3..0] : WIRE; + w_anode4874w[3..0] : WIRE; + w_anode4884w[3..0] : WIRE; + w_anode4894w[3..0] : WIRE; + w_anode4905w[3..0] : WIRE; + w_anode4916w[3..0] : WIRE; + w_anode4927w[3..0] : WIRE; + w_anode4937w[3..0] : WIRE; + w_anode4947w[3..0] : WIRE; + w_anode4957w[3..0] : WIRE; + w_anode4967w[3..0] : WIRE; + w_anode4977w[3..0] : WIRE; + w_anode4987w[3..0] : WIRE; + w_data4239w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[63..0] = eq_wire[63..0]; + eq_wire[] = ( ( w_anode4987w[3..3], w_anode4977w[3..3], w_anode4967w[3..3], w_anode4957w[3..3], w_anode4947w[3..3], w_anode4937w[3..3], w_anode4927w[3..3], w_anode4916w[3..3]), ( w_anode4894w[3..3], w_anode4884w[3..3], w_anode4874w[3..3], w_anode4864w[3..3], w_anode4854w[3..3], w_anode4844w[3..3], w_anode4834w[3..3], w_anode4823w[3..3]), ( w_anode4801w[3..3], w_anode4791w[3..3], w_anode4781w[3..3], w_anode4771w[3..3], w_anode4761w[3..3], w_anode4751w[3..3], w_anode4741w[3..3], w_anode4730w[3..3]), ( w_anode4708w[3..3], w_anode4698w[3..3], w_anode4688w[3..3], w_anode4678w[3..3], w_anode4668w[3..3], w_anode4658w[3..3], w_anode4648w[3..3], w_anode4637w[3..3]), ( w_anode4615w[3..3], w_anode4605w[3..3], w_anode4595w[3..3], w_anode4585w[3..3], w_anode4575w[3..3], w_anode4565w[3..3], w_anode4555w[3..3], w_anode4544w[3..3]), ( w_anode4522w[3..3], w_anode4512w[3..3], w_anode4502w[3..3], w_anode4492w[3..3], w_anode4482w[3..3], w_anode4472w[3..3], w_anode4462w[3..3], w_anode4451w[3..3]), ( w_anode4429w[3..3], w_anode4419w[3..3], w_anode4409w[3..3], w_anode4399w[3..3], w_anode4389w[3..3], w_anode4379w[3..3], w_anode4369w[3..3], w_anode4358w[3..3]), ( w_anode4335w[3..3], w_anode4325w[3..3], w_anode4315w[3..3], w_anode4305w[3..3], w_anode4295w[3..3], w_anode4285w[3..3], w_anode4275w[3..3], w_anode4258w[3..3])); + w_anode4241w[] = ( (w_anode4241w[2..2] & (! data_wire[5..5])), (w_anode4241w[1..1] & (! data_wire[4..4])), (w_anode4241w[0..0] & (! data_wire[3..3])), enable_wire); + w_anode4258w[] = ( (w_anode4258w[2..2] & (! w_data4239w[2..2])), (w_anode4258w[1..1] & (! w_data4239w[1..1])), (w_anode4258w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]); + w_anode4275w[] = ( (w_anode4275w[2..2] & (! w_data4239w[2..2])), (w_anode4275w[1..1] & (! w_data4239w[1..1])), (w_anode4275w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]); + w_anode4285w[] = ( (w_anode4285w[2..2] & (! w_data4239w[2..2])), (w_anode4285w[1..1] & w_data4239w[1..1]), (w_anode4285w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]); + w_anode4295w[] = ( (w_anode4295w[2..2] & (! w_data4239w[2..2])), (w_anode4295w[1..1] & w_data4239w[1..1]), (w_anode4295w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]); + w_anode4305w[] = ( (w_anode4305w[2..2] & w_data4239w[2..2]), (w_anode4305w[1..1] & (! w_data4239w[1..1])), (w_anode4305w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]); + w_anode4315w[] = ( (w_anode4315w[2..2] & w_data4239w[2..2]), (w_anode4315w[1..1] & (! w_data4239w[1..1])), (w_anode4315w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]); + w_anode4325w[] = ( (w_anode4325w[2..2] & w_data4239w[2..2]), (w_anode4325w[1..1] & w_data4239w[1..1]), (w_anode4325w[0..0] & (! w_data4239w[0..0])), w_anode4241w[3..3]); + w_anode4335w[] = ( (w_anode4335w[2..2] & w_data4239w[2..2]), (w_anode4335w[1..1] & w_data4239w[1..1]), (w_anode4335w[0..0] & w_data4239w[0..0]), w_anode4241w[3..3]); + w_anode4347w[] = ( (w_anode4347w[2..2] & (! data_wire[5..5])), (w_anode4347w[1..1] & (! data_wire[4..4])), (w_anode4347w[0..0] & data_wire[3..3]), enable_wire); + w_anode4358w[] = ( (w_anode4358w[2..2] & (! w_data4239w[2..2])), (w_anode4358w[1..1] & (! w_data4239w[1..1])), (w_anode4358w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]); + w_anode4369w[] = ( (w_anode4369w[2..2] & (! w_data4239w[2..2])), (w_anode4369w[1..1] & (! w_data4239w[1..1])), (w_anode4369w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]); + w_anode4379w[] = ( (w_anode4379w[2..2] & (! w_data4239w[2..2])), (w_anode4379w[1..1] & w_data4239w[1..1]), (w_anode4379w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]); + w_anode4389w[] = ( (w_anode4389w[2..2] & (! w_data4239w[2..2])), (w_anode4389w[1..1] & w_data4239w[1..1]), (w_anode4389w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]); + w_anode4399w[] = ( (w_anode4399w[2..2] & w_data4239w[2..2]), (w_anode4399w[1..1] & (! w_data4239w[1..1])), (w_anode4399w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]); + w_anode4409w[] = ( (w_anode4409w[2..2] & w_data4239w[2..2]), (w_anode4409w[1..1] & (! w_data4239w[1..1])), (w_anode4409w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]); + w_anode4419w[] = ( (w_anode4419w[2..2] & w_data4239w[2..2]), (w_anode4419w[1..1] & w_data4239w[1..1]), (w_anode4419w[0..0] & (! w_data4239w[0..0])), w_anode4347w[3..3]); + w_anode4429w[] = ( (w_anode4429w[2..2] & w_data4239w[2..2]), (w_anode4429w[1..1] & w_data4239w[1..1]), (w_anode4429w[0..0] & w_data4239w[0..0]), w_anode4347w[3..3]); + w_anode4440w[] = ( (w_anode4440w[2..2] & (! data_wire[5..5])), (w_anode4440w[1..1] & data_wire[4..4]), (w_anode4440w[0..0] & (! data_wire[3..3])), enable_wire); + w_anode4451w[] = ( (w_anode4451w[2..2] & (! w_data4239w[2..2])), (w_anode4451w[1..1] & (! w_data4239w[1..1])), (w_anode4451w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]); + w_anode4462w[] = ( (w_anode4462w[2..2] & (! w_data4239w[2..2])), (w_anode4462w[1..1] & (! w_data4239w[1..1])), (w_anode4462w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]); + w_anode4472w[] = ( (w_anode4472w[2..2] & (! w_data4239w[2..2])), (w_anode4472w[1..1] & w_data4239w[1..1]), (w_anode4472w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]); + w_anode4482w[] = ( (w_anode4482w[2..2] & (! w_data4239w[2..2])), (w_anode4482w[1..1] & w_data4239w[1..1]), (w_anode4482w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]); + w_anode4492w[] = ( (w_anode4492w[2..2] & w_data4239w[2..2]), (w_anode4492w[1..1] & (! w_data4239w[1..1])), (w_anode4492w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]); + w_anode4502w[] = ( (w_anode4502w[2..2] & w_data4239w[2..2]), (w_anode4502w[1..1] & (! w_data4239w[1..1])), (w_anode4502w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]); + w_anode4512w[] = ( (w_anode4512w[2..2] & w_data4239w[2..2]), (w_anode4512w[1..1] & w_data4239w[1..1]), (w_anode4512w[0..0] & (! w_data4239w[0..0])), w_anode4440w[3..3]); + w_anode4522w[] = ( (w_anode4522w[2..2] & w_data4239w[2..2]), (w_anode4522w[1..1] & w_data4239w[1..1]), (w_anode4522w[0..0] & w_data4239w[0..0]), w_anode4440w[3..3]); + w_anode4533w[] = ( (w_anode4533w[2..2] & (! data_wire[5..5])), (w_anode4533w[1..1] & data_wire[4..4]), (w_anode4533w[0..0] & data_wire[3..3]), enable_wire); + w_anode4544w[] = ( (w_anode4544w[2..2] & (! w_data4239w[2..2])), (w_anode4544w[1..1] & (! w_data4239w[1..1])), (w_anode4544w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]); + w_anode4555w[] = ( (w_anode4555w[2..2] & (! w_data4239w[2..2])), (w_anode4555w[1..1] & (! w_data4239w[1..1])), (w_anode4555w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]); + w_anode4565w[] = ( (w_anode4565w[2..2] & (! w_data4239w[2..2])), (w_anode4565w[1..1] & w_data4239w[1..1]), (w_anode4565w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]); + w_anode4575w[] = ( (w_anode4575w[2..2] & (! w_data4239w[2..2])), (w_anode4575w[1..1] & w_data4239w[1..1]), (w_anode4575w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]); + w_anode4585w[] = ( (w_anode4585w[2..2] & w_data4239w[2..2]), (w_anode4585w[1..1] & (! w_data4239w[1..1])), (w_anode4585w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]); + w_anode4595w[] = ( (w_anode4595w[2..2] & w_data4239w[2..2]), (w_anode4595w[1..1] & (! w_data4239w[1..1])), (w_anode4595w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]); + w_anode4605w[] = ( (w_anode4605w[2..2] & w_data4239w[2..2]), (w_anode4605w[1..1] & w_data4239w[1..1]), (w_anode4605w[0..0] & (! w_data4239w[0..0])), w_anode4533w[3..3]); + w_anode4615w[] = ( (w_anode4615w[2..2] & w_data4239w[2..2]), (w_anode4615w[1..1] & w_data4239w[1..1]), (w_anode4615w[0..0] & w_data4239w[0..0]), w_anode4533w[3..3]); + w_anode4626w[] = ( (w_anode4626w[2..2] & data_wire[5..5]), (w_anode4626w[1..1] & (! data_wire[4..4])), (w_anode4626w[0..0] & (! data_wire[3..3])), enable_wire); + w_anode4637w[] = ( (w_anode4637w[2..2] & (! w_data4239w[2..2])), (w_anode4637w[1..1] & (! w_data4239w[1..1])), (w_anode4637w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]); + w_anode4648w[] = ( (w_anode4648w[2..2] & (! w_data4239w[2..2])), (w_anode4648w[1..1] & (! w_data4239w[1..1])), (w_anode4648w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]); + w_anode4658w[] = ( (w_anode4658w[2..2] & (! w_data4239w[2..2])), (w_anode4658w[1..1] & w_data4239w[1..1]), (w_anode4658w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]); + w_anode4668w[] = ( (w_anode4668w[2..2] & (! w_data4239w[2..2])), (w_anode4668w[1..1] & w_data4239w[1..1]), (w_anode4668w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]); + w_anode4678w[] = ( (w_anode4678w[2..2] & w_data4239w[2..2]), (w_anode4678w[1..1] & (! w_data4239w[1..1])), (w_anode4678w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]); + w_anode4688w[] = ( (w_anode4688w[2..2] & w_data4239w[2..2]), (w_anode4688w[1..1] & (! w_data4239w[1..1])), (w_anode4688w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]); + w_anode4698w[] = ( (w_anode4698w[2..2] & w_data4239w[2..2]), (w_anode4698w[1..1] & w_data4239w[1..1]), (w_anode4698w[0..0] & (! w_data4239w[0..0])), w_anode4626w[3..3]); + w_anode4708w[] = ( (w_anode4708w[2..2] & w_data4239w[2..2]), (w_anode4708w[1..1] & w_data4239w[1..1]), (w_anode4708w[0..0] & w_data4239w[0..0]), w_anode4626w[3..3]); + w_anode4719w[] = ( (w_anode4719w[2..2] & data_wire[5..5]), (w_anode4719w[1..1] & (! data_wire[4..4])), (w_anode4719w[0..0] & data_wire[3..3]), enable_wire); + w_anode4730w[] = ( (w_anode4730w[2..2] & (! w_data4239w[2..2])), (w_anode4730w[1..1] & (! w_data4239w[1..1])), (w_anode4730w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]); + w_anode4741w[] = ( (w_anode4741w[2..2] & (! w_data4239w[2..2])), (w_anode4741w[1..1] & (! w_data4239w[1..1])), (w_anode4741w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]); + w_anode4751w[] = ( (w_anode4751w[2..2] & (! w_data4239w[2..2])), (w_anode4751w[1..1] & w_data4239w[1..1]), (w_anode4751w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]); + w_anode4761w[] = ( (w_anode4761w[2..2] & (! w_data4239w[2..2])), (w_anode4761w[1..1] & w_data4239w[1..1]), (w_anode4761w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]); + w_anode4771w[] = ( (w_anode4771w[2..2] & w_data4239w[2..2]), (w_anode4771w[1..1] & (! w_data4239w[1..1])), (w_anode4771w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]); + w_anode4781w[] = ( (w_anode4781w[2..2] & w_data4239w[2..2]), (w_anode4781w[1..1] & (! w_data4239w[1..1])), (w_anode4781w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]); + w_anode4791w[] = ( (w_anode4791w[2..2] & w_data4239w[2..2]), (w_anode4791w[1..1] & w_data4239w[1..1]), (w_anode4791w[0..0] & (! w_data4239w[0..0])), w_anode4719w[3..3]); + w_anode4801w[] = ( (w_anode4801w[2..2] & w_data4239w[2..2]), (w_anode4801w[1..1] & w_data4239w[1..1]), (w_anode4801w[0..0] & w_data4239w[0..0]), w_anode4719w[3..3]); + w_anode4812w[] = ( (w_anode4812w[2..2] & data_wire[5..5]), (w_anode4812w[1..1] & data_wire[4..4]), (w_anode4812w[0..0] & (! data_wire[3..3])), enable_wire); + w_anode4823w[] = ( (w_anode4823w[2..2] & (! w_data4239w[2..2])), (w_anode4823w[1..1] & (! w_data4239w[1..1])), (w_anode4823w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]); + w_anode4834w[] = ( (w_anode4834w[2..2] & (! w_data4239w[2..2])), (w_anode4834w[1..1] & (! w_data4239w[1..1])), (w_anode4834w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]); + w_anode4844w[] = ( (w_anode4844w[2..2] & (! w_data4239w[2..2])), (w_anode4844w[1..1] & w_data4239w[1..1]), (w_anode4844w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]); + w_anode4854w[] = ( (w_anode4854w[2..2] & (! w_data4239w[2..2])), (w_anode4854w[1..1] & w_data4239w[1..1]), (w_anode4854w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]); + w_anode4864w[] = ( (w_anode4864w[2..2] & w_data4239w[2..2]), (w_anode4864w[1..1] & (! w_data4239w[1..1])), (w_anode4864w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]); + w_anode4874w[] = ( (w_anode4874w[2..2] & w_data4239w[2..2]), (w_anode4874w[1..1] & (! w_data4239w[1..1])), (w_anode4874w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]); + w_anode4884w[] = ( (w_anode4884w[2..2] & w_data4239w[2..2]), (w_anode4884w[1..1] & w_data4239w[1..1]), (w_anode4884w[0..0] & (! w_data4239w[0..0])), w_anode4812w[3..3]); + w_anode4894w[] = ( (w_anode4894w[2..2] & w_data4239w[2..2]), (w_anode4894w[1..1] & w_data4239w[1..1]), (w_anode4894w[0..0] & w_data4239w[0..0]), w_anode4812w[3..3]); + w_anode4905w[] = ( (w_anode4905w[2..2] & data_wire[5..5]), (w_anode4905w[1..1] & data_wire[4..4]), (w_anode4905w[0..0] & data_wire[3..3]), enable_wire); + w_anode4916w[] = ( (w_anode4916w[2..2] & (! w_data4239w[2..2])), (w_anode4916w[1..1] & (! w_data4239w[1..1])), (w_anode4916w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]); + w_anode4927w[] = ( (w_anode4927w[2..2] & (! w_data4239w[2..2])), (w_anode4927w[1..1] & (! w_data4239w[1..1])), (w_anode4927w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]); + w_anode4937w[] = ( (w_anode4937w[2..2] & (! w_data4239w[2..2])), (w_anode4937w[1..1] & w_data4239w[1..1]), (w_anode4937w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]); + w_anode4947w[] = ( (w_anode4947w[2..2] & (! w_data4239w[2..2])), (w_anode4947w[1..1] & w_data4239w[1..1]), (w_anode4947w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]); + w_anode4957w[] = ( (w_anode4957w[2..2] & w_data4239w[2..2]), (w_anode4957w[1..1] & (! w_data4239w[1..1])), (w_anode4957w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]); + w_anode4967w[] = ( (w_anode4967w[2..2] & w_data4239w[2..2]), (w_anode4967w[1..1] & (! w_data4239w[1..1])), (w_anode4967w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]); + w_anode4977w[] = ( (w_anode4977w[2..2] & w_data4239w[2..2]), (w_anode4977w[1..1] & w_data4239w[1..1]), (w_anode4977w[0..0] & (! w_data4239w[0..0])), w_anode4905w[3..3]); + w_anode4987w[] = ( (w_anode4987w[2..2] & w_data4239w[2..2]), (w_anode4987w[1..1] & w_data4239w[1..1]), (w_anode4987w[0..0] & w_data4239w[0..0]), w_anode4905w[3..3]); + w_data4239w[2..0] = data_wire[2..0]; +END; +--VALID FILE diff --git a/proj_quartus/db/decode_5la.tdf b/proj_quartus/db/decode_5la.tdf new file mode 100644 index 000000000..8d212771b --- /dev/null +++ b/proj_quartus/db/decode_5la.tdf @@ -0,0 +1,36 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=2 LPM_WIDTH=1 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 1 +SUBDESIGN decode_5la +( + data[0..0] : input; + enable : input; + eq[1..0] : output; +) +VARIABLE + eq_node[1..0] : WIRE; + +BEGIN + eq[] = eq_node[]; + eq_node[] = ( (data[] & enable), ((! data[]) & enable)); +END; +--VALID FILE diff --git a/proj_quartus/db/decode_8la.tdf b/proj_quartus/db/decode_8la.tdf new file mode 100644 index 000000000..4b363ba81 --- /dev/null +++ b/proj_quartus/db/decode_8la.tdf @@ -0,0 +1,50 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=4 LPM_WIDTH=2 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 4 +SUBDESIGN decode_8la +( + data[1..0] : input; + enable : input; + eq[3..0] : output; +) +VARIABLE + data_wire[1..0] : WIRE; + enable_wire : WIRE; + eq_node[3..0] : WIRE; + eq_wire[3..0] : WIRE; + w_anode279w[2..0] : WIRE; + w_anode292w[2..0] : WIRE; + w_anode300w[2..0] : WIRE; + w_anode308w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[3..0] = eq_wire[3..0]; + eq_wire[] = ( w_anode308w[2..2], w_anode300w[2..2], w_anode292w[2..2], w_anode279w[2..2]); + w_anode279w[] = ( (w_anode279w[1..1] & (! data_wire[1..1])), (w_anode279w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode292w[] = ( (w_anode292w[1..1] & (! data_wire[1..1])), (w_anode292w[0..0] & data_wire[0..0]), enable_wire); + w_anode300w[] = ( (w_anode300w[1..1] & data_wire[1..1]), (w_anode300w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode308w[] = ( (w_anode308w[1..1] & data_wire[1..1]), (w_anode308w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/proj_quartus/db/decode_dla.tdf b/proj_quartus/db/decode_dla.tdf new file mode 100644 index 000000000..32da0d3fe --- /dev/null +++ b/proj_quartus/db/decode_dla.tdf @@ -0,0 +1,58 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=8 LPM_WIDTH=3 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 8 +SUBDESIGN decode_dla +( + data[2..0] : input; + enable : input; + eq[7..0] : output; +) +VARIABLE + data_wire[2..0] : WIRE; + enable_wire : WIRE; + eq_node[7..0] : WIRE; + eq_wire[7..0] : WIRE; + w_anode543w[3..0] : WIRE; + w_anode560w[3..0] : WIRE; + w_anode570w[3..0] : WIRE; + w_anode580w[3..0] : WIRE; + w_anode590w[3..0] : WIRE; + w_anode600w[3..0] : WIRE; + w_anode610w[3..0] : WIRE; + w_anode620w[3..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[7..0] = eq_wire[7..0]; + eq_wire[] = ( w_anode620w[3..3], w_anode610w[3..3], w_anode600w[3..3], w_anode590w[3..3], w_anode580w[3..3], w_anode570w[3..3], w_anode560w[3..3], w_anode543w[3..3]); + w_anode543w[] = ( (w_anode543w[2..2] & (! data_wire[2..2])), (w_anode543w[1..1] & (! data_wire[1..1])), (w_anode543w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode560w[] = ( (w_anode560w[2..2] & (! data_wire[2..2])), (w_anode560w[1..1] & (! data_wire[1..1])), (w_anode560w[0..0] & data_wire[0..0]), enable_wire); + w_anode570w[] = ( (w_anode570w[2..2] & (! data_wire[2..2])), (w_anode570w[1..1] & data_wire[1..1]), (w_anode570w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode580w[] = ( (w_anode580w[2..2] & (! data_wire[2..2])), (w_anode580w[1..1] & data_wire[1..1]), (w_anode580w[0..0] & data_wire[0..0]), enable_wire); + w_anode590w[] = ( (w_anode590w[2..2] & data_wire[2..2]), (w_anode590w[1..1] & (! data_wire[1..1])), (w_anode590w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode600w[] = ( (w_anode600w[2..2] & data_wire[2..2]), (w_anode600w[1..1] & (! data_wire[1..1])), (w_anode600w[0..0] & data_wire[0..0]), enable_wire); + w_anode610w[] = ( (w_anode610w[2..2] & data_wire[2..2]), (w_anode610w[1..1] & data_wire[1..1]), (w_anode610w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode620w[] = ( (w_anode620w[2..2] & data_wire[2..2]), (w_anode620w[1..1] & data_wire[1..1]), (w_anode620w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/proj_quartus/db/decode_noa.tdf b/proj_quartus/db/decode_noa.tdf new file mode 100644 index 000000000..b638ada48 --- /dev/null +++ b/proj_quartus/db/decode_noa.tdf @@ -0,0 +1,636 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=256 LPM_WIDTH=8 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 292 +SUBDESIGN decode_noa +( + data[7..0] : input; + enable : input; + eq[255..0] : output; +) +VARIABLE + data_wire[7..0] : WIRE; + enable_wire : WIRE; + eq_node[255..0] : WIRE; + eq_wire[255..0] : WIRE; + w_anode16913w[2..0] : WIRE; + w_anode16928w[3..0] : WIRE; + w_anode16945w[3..0] : WIRE; + w_anode16962w[3..0] : WIRE; + w_anode16972w[3..0] : WIRE; + w_anode16982w[3..0] : WIRE; + w_anode16992w[3..0] : WIRE; + w_anode17002w[3..0] : WIRE; + w_anode17012w[3..0] : WIRE; + w_anode17022w[3..0] : WIRE; + w_anode17034w[3..0] : WIRE; + w_anode17045w[3..0] : WIRE; + w_anode17056w[3..0] : WIRE; + w_anode17066w[3..0] : WIRE; + w_anode17076w[3..0] : WIRE; + w_anode17086w[3..0] : WIRE; + w_anode17096w[3..0] : WIRE; + w_anode17106w[3..0] : WIRE; + w_anode17116w[3..0] : WIRE; + w_anode17127w[3..0] : WIRE; + w_anode17138w[3..0] : WIRE; + w_anode17149w[3..0] : WIRE; + w_anode17159w[3..0] : WIRE; + w_anode17169w[3..0] : WIRE; + w_anode17179w[3..0] : WIRE; + w_anode17189w[3..0] : WIRE; + w_anode17199w[3..0] : WIRE; + w_anode17209w[3..0] : WIRE; + w_anode17220w[3..0] : WIRE; + w_anode17231w[3..0] : WIRE; + w_anode17242w[3..0] : WIRE; + w_anode17252w[3..0] : WIRE; + w_anode17262w[3..0] : WIRE; + w_anode17272w[3..0] : WIRE; + w_anode17282w[3..0] : WIRE; + w_anode17292w[3..0] : WIRE; + w_anode17302w[3..0] : WIRE; + w_anode17313w[3..0] : WIRE; + w_anode17324w[3..0] : WIRE; + w_anode17335w[3..0] : WIRE; + w_anode17345w[3..0] : WIRE; + w_anode17355w[3..0] : WIRE; + w_anode17365w[3..0] : WIRE; + w_anode17375w[3..0] : WIRE; + w_anode17385w[3..0] : WIRE; + w_anode17395w[3..0] : WIRE; + w_anode17406w[3..0] : WIRE; + w_anode17417w[3..0] : WIRE; + w_anode17428w[3..0] : WIRE; + w_anode17438w[3..0] : WIRE; + w_anode17448w[3..0] : WIRE; + w_anode17458w[3..0] : WIRE; + w_anode17468w[3..0] : WIRE; + w_anode17478w[3..0] : WIRE; + w_anode17488w[3..0] : WIRE; + w_anode17499w[3..0] : WIRE; + w_anode17510w[3..0] : WIRE; + w_anode17521w[3..0] : WIRE; + w_anode17531w[3..0] : WIRE; + w_anode17541w[3..0] : WIRE; + w_anode17551w[3..0] : WIRE; + w_anode17561w[3..0] : WIRE; + w_anode17571w[3..0] : WIRE; + w_anode17581w[3..0] : WIRE; + w_anode17592w[3..0] : WIRE; + w_anode17603w[3..0] : WIRE; + w_anode17614w[3..0] : WIRE; + w_anode17624w[3..0] : WIRE; + w_anode17634w[3..0] : WIRE; + w_anode17644w[3..0] : WIRE; + w_anode17654w[3..0] : WIRE; + w_anode17664w[3..0] : WIRE; + w_anode17674w[3..0] : WIRE; + w_anode17687w[2..0] : WIRE; + w_anode17697w[3..0] : WIRE; + w_anode17708w[3..0] : WIRE; + w_anode17725w[3..0] : WIRE; + w_anode17735w[3..0] : WIRE; + w_anode17745w[3..0] : WIRE; + w_anode17755w[3..0] : WIRE; + w_anode17765w[3..0] : WIRE; + w_anode17775w[3..0] : WIRE; + w_anode17785w[3..0] : WIRE; + w_anode17797w[3..0] : WIRE; + w_anode17808w[3..0] : WIRE; + w_anode17819w[3..0] : WIRE; + w_anode17829w[3..0] : WIRE; + w_anode17839w[3..0] : WIRE; + w_anode17849w[3..0] : WIRE; + w_anode17859w[3..0] : WIRE; + w_anode17869w[3..0] : WIRE; + w_anode17879w[3..0] : WIRE; + w_anode17890w[3..0] : WIRE; + w_anode17901w[3..0] : WIRE; + w_anode17912w[3..0] : WIRE; + w_anode17922w[3..0] : WIRE; + w_anode17932w[3..0] : WIRE; + w_anode17942w[3..0] : WIRE; + w_anode17952w[3..0] : WIRE; + w_anode17962w[3..0] : WIRE; + w_anode17972w[3..0] : WIRE; + w_anode17983w[3..0] : WIRE; + w_anode17994w[3..0] : WIRE; + w_anode18005w[3..0] : WIRE; + w_anode18015w[3..0] : WIRE; + w_anode18025w[3..0] : WIRE; + w_anode18035w[3..0] : WIRE; + w_anode18045w[3..0] : WIRE; + w_anode18055w[3..0] : WIRE; + w_anode18065w[3..0] : WIRE; + w_anode18076w[3..0] : WIRE; + w_anode18087w[3..0] : WIRE; + w_anode18098w[3..0] : WIRE; + w_anode18108w[3..0] : WIRE; + w_anode18118w[3..0] : WIRE; + w_anode18128w[3..0] : WIRE; + w_anode18138w[3..0] : WIRE; + w_anode18148w[3..0] : WIRE; + w_anode18158w[3..0] : WIRE; + w_anode18169w[3..0] : WIRE; + w_anode18180w[3..0] : WIRE; + w_anode18191w[3..0] : WIRE; + w_anode18201w[3..0] : WIRE; + w_anode18211w[3..0] : WIRE; + w_anode18221w[3..0] : WIRE; + w_anode18231w[3..0] : WIRE; + w_anode18241w[3..0] : WIRE; + w_anode18251w[3..0] : WIRE; + w_anode18262w[3..0] : WIRE; + w_anode18273w[3..0] : WIRE; + w_anode18284w[3..0] : WIRE; + w_anode18294w[3..0] : WIRE; + w_anode18304w[3..0] : WIRE; + w_anode18314w[3..0] : WIRE; + w_anode18324w[3..0] : WIRE; + w_anode18334w[3..0] : WIRE; + w_anode18344w[3..0] : WIRE; + w_anode18355w[3..0] : WIRE; + w_anode18366w[3..0] : WIRE; + w_anode18377w[3..0] : WIRE; + w_anode18387w[3..0] : WIRE; + w_anode18397w[3..0] : WIRE; + w_anode18407w[3..0] : WIRE; + w_anode18417w[3..0] : WIRE; + w_anode18427w[3..0] : WIRE; + w_anode18437w[3..0] : WIRE; + w_anode18449w[2..0] : WIRE; + w_anode18459w[3..0] : WIRE; + w_anode18470w[3..0] : WIRE; + w_anode18487w[3..0] : WIRE; + w_anode18497w[3..0] : WIRE; + w_anode18507w[3..0] : WIRE; + w_anode18517w[3..0] : WIRE; + w_anode18527w[3..0] : WIRE; + w_anode18537w[3..0] : WIRE; + w_anode18547w[3..0] : WIRE; + w_anode18559w[3..0] : WIRE; + w_anode18570w[3..0] : WIRE; + w_anode18581w[3..0] : WIRE; + w_anode18591w[3..0] : WIRE; + w_anode18601w[3..0] : WIRE; + w_anode18611w[3..0] : WIRE; + w_anode18621w[3..0] : WIRE; + w_anode18631w[3..0] : WIRE; + w_anode18641w[3..0] : WIRE; + w_anode18652w[3..0] : WIRE; + w_anode18663w[3..0] : WIRE; + w_anode18674w[3..0] : WIRE; + w_anode18684w[3..0] : WIRE; + w_anode18694w[3..0] : WIRE; + w_anode18704w[3..0] : WIRE; + w_anode18714w[3..0] : WIRE; + w_anode18724w[3..0] : WIRE; + w_anode18734w[3..0] : WIRE; + w_anode18745w[3..0] : WIRE; + w_anode18756w[3..0] : WIRE; + w_anode18767w[3..0] : WIRE; + w_anode18777w[3..0] : WIRE; + w_anode18787w[3..0] : WIRE; + w_anode18797w[3..0] : WIRE; + w_anode18807w[3..0] : WIRE; + w_anode18817w[3..0] : WIRE; + w_anode18827w[3..0] : WIRE; + w_anode18838w[3..0] : WIRE; + w_anode18849w[3..0] : WIRE; + w_anode18860w[3..0] : WIRE; + w_anode18870w[3..0] : WIRE; + w_anode18880w[3..0] : WIRE; + w_anode18890w[3..0] : WIRE; + w_anode18900w[3..0] : WIRE; + w_anode18910w[3..0] : WIRE; + w_anode18920w[3..0] : WIRE; + w_anode18931w[3..0] : WIRE; + w_anode18942w[3..0] : WIRE; + w_anode18953w[3..0] : WIRE; + w_anode18963w[3..0] : WIRE; + w_anode18973w[3..0] : WIRE; + w_anode18983w[3..0] : WIRE; + w_anode18993w[3..0] : WIRE; + w_anode19003w[3..0] : WIRE; + w_anode19013w[3..0] : WIRE; + w_anode19024w[3..0] : WIRE; + w_anode19035w[3..0] : WIRE; + w_anode19046w[3..0] : WIRE; + w_anode19056w[3..0] : WIRE; + w_anode19066w[3..0] : WIRE; + w_anode19076w[3..0] : WIRE; + w_anode19086w[3..0] : WIRE; + w_anode19096w[3..0] : WIRE; + w_anode19106w[3..0] : WIRE; + w_anode19117w[3..0] : WIRE; + w_anode19128w[3..0] : WIRE; + w_anode19139w[3..0] : WIRE; + w_anode19149w[3..0] : WIRE; + w_anode19159w[3..0] : WIRE; + w_anode19169w[3..0] : WIRE; + w_anode19179w[3..0] : WIRE; + w_anode19189w[3..0] : WIRE; + w_anode19199w[3..0] : WIRE; + w_anode19211w[2..0] : WIRE; + w_anode19221w[3..0] : WIRE; + w_anode19232w[3..0] : WIRE; + w_anode19249w[3..0] : WIRE; + w_anode19259w[3..0] : WIRE; + w_anode19269w[3..0] : WIRE; + w_anode19279w[3..0] : WIRE; + w_anode19289w[3..0] : WIRE; + w_anode19299w[3..0] : WIRE; + w_anode19309w[3..0] : WIRE; + w_anode19321w[3..0] : WIRE; + w_anode19332w[3..0] : WIRE; + w_anode19343w[3..0] : WIRE; + w_anode19353w[3..0] : WIRE; + w_anode19363w[3..0] : WIRE; + w_anode19373w[3..0] : WIRE; + w_anode19383w[3..0] : WIRE; + w_anode19393w[3..0] : WIRE; + w_anode19403w[3..0] : WIRE; + w_anode19414w[3..0] : WIRE; + w_anode19425w[3..0] : WIRE; + w_anode19436w[3..0] : WIRE; + w_anode19446w[3..0] : WIRE; + w_anode19456w[3..0] : WIRE; + w_anode19466w[3..0] : WIRE; + w_anode19476w[3..0] : WIRE; + w_anode19486w[3..0] : WIRE; + w_anode19496w[3..0] : WIRE; + w_anode19507w[3..0] : WIRE; + w_anode19518w[3..0] : WIRE; + w_anode19529w[3..0] : WIRE; + w_anode19539w[3..0] : WIRE; + w_anode19549w[3..0] : WIRE; + w_anode19559w[3..0] : WIRE; + w_anode19569w[3..0] : WIRE; + w_anode19579w[3..0] : WIRE; + w_anode19589w[3..0] : WIRE; + w_anode19600w[3..0] : WIRE; + w_anode19611w[3..0] : WIRE; + w_anode19622w[3..0] : WIRE; + w_anode19632w[3..0] : WIRE; + w_anode19642w[3..0] : WIRE; + w_anode19652w[3..0] : WIRE; + w_anode19662w[3..0] : WIRE; + w_anode19672w[3..0] : WIRE; + w_anode19682w[3..0] : WIRE; + w_anode19693w[3..0] : WIRE; + w_anode19704w[3..0] : WIRE; + w_anode19715w[3..0] : WIRE; + w_anode19725w[3..0] : WIRE; + w_anode19735w[3..0] : WIRE; + w_anode19745w[3..0] : WIRE; + w_anode19755w[3..0] : WIRE; + w_anode19765w[3..0] : WIRE; + w_anode19775w[3..0] : WIRE; + w_anode19786w[3..0] : WIRE; + w_anode19797w[3..0] : WIRE; + w_anode19808w[3..0] : WIRE; + w_anode19818w[3..0] : WIRE; + w_anode19828w[3..0] : WIRE; + w_anode19838w[3..0] : WIRE; + w_anode19848w[3..0] : WIRE; + w_anode19858w[3..0] : WIRE; + w_anode19868w[3..0] : WIRE; + w_anode19879w[3..0] : WIRE; + w_anode19890w[3..0] : WIRE; + w_anode19901w[3..0] : WIRE; + w_anode19911w[3..0] : WIRE; + w_anode19921w[3..0] : WIRE; + w_anode19931w[3..0] : WIRE; + w_anode19941w[3..0] : WIRE; + w_anode19951w[3..0] : WIRE; + w_anode19961w[3..0] : WIRE; + w_data16911w[5..0] : WIRE; + w_data16926w[2..0] : WIRE; + w_data17696w[2..0] : WIRE; + w_data18458w[2..0] : WIRE; + w_data19220w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[255..0] = eq_wire[255..0]; + eq_wire[] = ( ( ( w_anode19961w[3..3], w_anode19951w[3..3], w_anode19941w[3..3], w_anode19931w[3..3], w_anode19921w[3..3], w_anode19911w[3..3], w_anode19901w[3..3], w_anode19890w[3..3]), ( w_anode19868w[3..3], w_anode19858w[3..3], w_anode19848w[3..3], w_anode19838w[3..3], w_anode19828w[3..3], w_anode19818w[3..3], w_anode19808w[3..3], w_anode19797w[3..3]), ( w_anode19775w[3..3], w_anode19765w[3..3], w_anode19755w[3..3], w_anode19745w[3..3], w_anode19735w[3..3], w_anode19725w[3..3], w_anode19715w[3..3], w_anode19704w[3..3]), ( w_anode19682w[3..3], w_anode19672w[3..3], w_anode19662w[3..3], w_anode19652w[3..3], w_anode19642w[3..3], w_anode19632w[3..3], w_anode19622w[3..3], w_anode19611w[3..3]), ( w_anode19589w[3..3], w_anode19579w[3..3], w_anode19569w[3..3], w_anode19559w[3..3], w_anode19549w[3..3], w_anode19539w[3..3], w_anode19529w[3..3], w_anode19518w[3..3]), ( w_anode19496w[3..3], w_anode19486w[3..3], w_anode19476w[3..3], w_anode19466w[3..3], w_anode19456w[3..3], w_anode19446w[3..3], w_anode19436w[3..3], w_anode19425w[3..3]), ( w_anode19403w[3..3], w_anode19393w[3..3], w_anode19383w[3..3], w_anode19373w[3..3], w_anode19363w[3..3], w_anode19353w[3..3], w_anode19343w[3..3], w_anode19332w[3..3]), ( w_anode19309w[3..3], w_anode19299w[3..3], w_anode19289w[3..3], w_anode19279w[3..3], w_anode19269w[3..3], w_anode19259w[3..3], w_anode19249w[3..3], w_anode19232w[3..3])), ( ( w_anode19199w[3..3], w_anode19189w[3..3], w_anode19179w[3..3], w_anode19169w[3..3], w_anode19159w[3..3], w_anode19149w[3..3], w_anode19139w[3..3], w_anode19128w[3..3]), ( w_anode19106w[3..3], w_anode19096w[3..3], w_anode19086w[3..3], w_anode19076w[3..3], w_anode19066w[3..3], w_anode19056w[3..3], w_anode19046w[3..3], w_anode19035w[3..3]), ( w_anode19013w[3..3], w_anode19003w[3..3], w_anode18993w[3..3], w_anode18983w[3..3], w_anode18973w[3..3], w_anode18963w[3..3], w_anode18953w[3..3], w_anode18942w[3..3]), ( w_anode18920w[3..3], w_anode18910w[3..3], w_anode18900w[3..3], w_anode18890w[3..3], w_anode18880w[3..3], w_anode18870w[3..3], w_anode18860w[3..3], w_anode18849w[3..3]), ( w_anode18827w[3..3], w_anode18817w[3..3], w_anode18807w[3..3], w_anode18797w[3..3], w_anode18787w[3..3], w_anode18777w[3..3], w_anode18767w[3..3], w_anode18756w[3..3]), ( w_anode18734w[3..3], w_anode18724w[3..3], w_anode18714w[3..3], w_anode18704w[3..3], w_anode18694w[3..3], w_anode18684w[3..3], w_anode18674w[3..3], w_anode18663w[3..3]), ( w_anode18641w[3..3], w_anode18631w[3..3], w_anode18621w[3..3], w_anode18611w[3..3], w_anode18601w[3..3], w_anode18591w[3..3], w_anode18581w[3..3], w_anode18570w[3..3]), ( w_anode18547w[3..3], w_anode18537w[3..3], w_anode18527w[3..3], w_anode18517w[3..3], w_anode18507w[3..3], w_anode18497w[3..3], w_anode18487w[3..3], w_anode18470w[3..3])), ( ( w_anode18437w[3..3], w_anode18427w[3..3], w_anode18417w[3..3], w_anode18407w[3..3], w_anode18397w[3..3], w_anode18387w[3..3], w_anode18377w[3..3], w_anode18366w[3..3]), ( w_anode18344w[3..3], w_anode18334w[3..3], w_anode18324w[3..3], w_anode18314w[3..3], w_anode18304w[3..3], w_anode18294w[3..3], w_anode18284w[3..3], w_anode18273w[3..3]), ( w_anode18251w[3..3], w_anode18241w[3..3], w_anode18231w[3..3], w_anode18221w[3..3], w_anode18211w[3..3], w_anode18201w[3..3], w_anode18191w[3..3], w_anode18180w[3..3]), ( w_anode18158w[3..3], w_anode18148w[3..3], w_anode18138w[3..3], w_anode18128w[3..3], w_anode18118w[3..3], w_anode18108w[3..3], w_anode18098w[3..3], w_anode18087w[3..3]), ( w_anode18065w[3..3], w_anode18055w[3..3], w_anode18045w[3..3], w_anode18035w[3..3], w_anode18025w[3..3], w_anode18015w[3..3], w_anode18005w[3..3], w_anode17994w[3..3]), ( w_anode17972w[3..3], w_anode17962w[3..3], w_anode17952w[3..3], w_anode17942w[3..3], w_anode17932w[3..3], w_anode17922w[3..3], w_anode17912w[3..3], w_anode17901w[3..3]), ( w_anode17879w[3..3], w_anode17869w[3..3], w_anode17859w[3..3], w_anode17849w[3..3], w_anode17839w[3..3], w_anode17829w[3..3], w_anode17819w[3..3], w_anode17808w[3..3]), ( w_anode17785w[3..3], w_anode17775w[3..3], w_anode17765w[3..3], w_anode17755w[3..3], w_anode17745w[3..3], w_anode17735w[3..3], w_anode17725w[3..3], w_anode17708w[3..3])), ( ( w_anode17674w[3..3], w_anode17664w[3..3], w_anode17654w[3..3], w_anode17644w[3..3], w_anode17634w[3..3], w_anode17624w[3..3], w_anode17614w[3..3], w_anode17603w[3..3]), ( w_anode17581w[3..3], w_anode17571w[3..3], w_anode17561w[3..3], w_anode17551w[3..3], w_anode17541w[3..3], w_anode17531w[3..3], w_anode17521w[3..3], w_anode17510w[3..3]), ( w_anode17488w[3..3], w_anode17478w[3..3], w_anode17468w[3..3], w_anode17458w[3..3], w_anode17448w[3..3], w_anode17438w[3..3], w_anode17428w[3..3], w_anode17417w[3..3]), ( w_anode17395w[3..3], w_anode17385w[3..3], w_anode17375w[3..3], w_anode17365w[3..3], w_anode17355w[3..3], w_anode17345w[3..3], w_anode17335w[3..3], w_anode17324w[3..3]), ( w_anode17302w[3..3], w_anode17292w[3..3], w_anode17282w[3..3], w_anode17272w[3..3], w_anode17262w[3..3], w_anode17252w[3..3], w_anode17242w[3..3], w_anode17231w[3..3]), ( w_anode17209w[3..3], w_anode17199w[3..3], w_anode17189w[3..3], w_anode17179w[3..3], w_anode17169w[3..3], w_anode17159w[3..3], w_anode17149w[3..3], w_anode17138w[3..3]), ( w_anode17116w[3..3], w_anode17106w[3..3], w_anode17096w[3..3], w_anode17086w[3..3], w_anode17076w[3..3], w_anode17066w[3..3], w_anode17056w[3..3], w_anode17045w[3..3]), ( w_anode17022w[3..3], w_anode17012w[3..3], w_anode17002w[3..3], w_anode16992w[3..3], w_anode16982w[3..3], w_anode16972w[3..3], w_anode16962w[3..3], w_anode16945w[3..3]))); + w_anode16913w[] = ( (w_anode16913w[1..1] & (! data_wire[7..7])), (w_anode16913w[0..0] & (! data_wire[6..6])), enable_wire); + w_anode16928w[] = ( (w_anode16928w[2..2] & (! w_data16911w[5..5])), (w_anode16928w[1..1] & (! w_data16911w[4..4])), (w_anode16928w[0..0] & (! w_data16911w[3..3])), w_anode16913w[2..2]); + w_anode16945w[] = ( (w_anode16945w[2..2] & (! w_data16926w[2..2])), (w_anode16945w[1..1] & (! w_data16926w[1..1])), (w_anode16945w[0..0] & (! w_data16926w[0..0])), w_anode16928w[3..3]); + w_anode16962w[] = ( (w_anode16962w[2..2] & (! w_data16926w[2..2])), (w_anode16962w[1..1] & (! w_data16926w[1..1])), (w_anode16962w[0..0] & w_data16926w[0..0]), w_anode16928w[3..3]); + w_anode16972w[] = ( (w_anode16972w[2..2] & (! w_data16926w[2..2])), (w_anode16972w[1..1] & w_data16926w[1..1]), (w_anode16972w[0..0] & (! w_data16926w[0..0])), w_anode16928w[3..3]); + w_anode16982w[] = ( (w_anode16982w[2..2] & (! w_data16926w[2..2])), (w_anode16982w[1..1] & w_data16926w[1..1]), (w_anode16982w[0..0] & w_data16926w[0..0]), w_anode16928w[3..3]); + w_anode16992w[] = ( (w_anode16992w[2..2] & w_data16926w[2..2]), (w_anode16992w[1..1] & (! w_data16926w[1..1])), (w_anode16992w[0..0] & (! w_data16926w[0..0])), w_anode16928w[3..3]); + w_anode17002w[] = ( (w_anode17002w[2..2] & w_data16926w[2..2]), (w_anode17002w[1..1] & (! w_data16926w[1..1])), (w_anode17002w[0..0] & w_data16926w[0..0]), w_anode16928w[3..3]); + w_anode17012w[] = ( (w_anode17012w[2..2] & w_data16926w[2..2]), (w_anode17012w[1..1] & w_data16926w[1..1]), (w_anode17012w[0..0] & (! w_data16926w[0..0])), w_anode16928w[3..3]); + w_anode17022w[] = ( (w_anode17022w[2..2] & w_data16926w[2..2]), (w_anode17022w[1..1] & w_data16926w[1..1]), (w_anode17022w[0..0] & w_data16926w[0..0]), w_anode16928w[3..3]); + w_anode17034w[] = ( (w_anode17034w[2..2] & (! w_data16911w[5..5])), (w_anode17034w[1..1] & (! w_data16911w[4..4])), (w_anode17034w[0..0] & w_data16911w[3..3]), w_anode16913w[2..2]); + w_anode17045w[] = ( (w_anode17045w[2..2] & (! w_data16926w[2..2])), (w_anode17045w[1..1] & (! w_data16926w[1..1])), (w_anode17045w[0..0] & (! w_data16926w[0..0])), w_anode17034w[3..3]); + w_anode17056w[] = ( (w_anode17056w[2..2] & (! w_data16926w[2..2])), (w_anode17056w[1..1] & (! w_data16926w[1..1])), (w_anode17056w[0..0] & w_data16926w[0..0]), w_anode17034w[3..3]); + w_anode17066w[] = ( (w_anode17066w[2..2] & (! w_data16926w[2..2])), (w_anode17066w[1..1] & w_data16926w[1..1]), (w_anode17066w[0..0] & (! w_data16926w[0..0])), w_anode17034w[3..3]); + w_anode17076w[] = ( (w_anode17076w[2..2] & (! w_data16926w[2..2])), (w_anode17076w[1..1] & w_data16926w[1..1]), (w_anode17076w[0..0] & w_data16926w[0..0]), w_anode17034w[3..3]); + w_anode17086w[] = ( (w_anode17086w[2..2] & w_data16926w[2..2]), (w_anode17086w[1..1] & (! w_data16926w[1..1])), (w_anode17086w[0..0] & (! w_data16926w[0..0])), w_anode17034w[3..3]); + w_anode17096w[] = ( (w_anode17096w[2..2] & w_data16926w[2..2]), (w_anode17096w[1..1] & (! w_data16926w[1..1])), (w_anode17096w[0..0] & w_data16926w[0..0]), w_anode17034w[3..3]); + w_anode17106w[] = ( (w_anode17106w[2..2] & w_data16926w[2..2]), (w_anode17106w[1..1] & w_data16926w[1..1]), (w_anode17106w[0..0] & (! w_data16926w[0..0])), w_anode17034w[3..3]); + w_anode17116w[] = ( (w_anode17116w[2..2] & w_data16926w[2..2]), (w_anode17116w[1..1] & w_data16926w[1..1]), (w_anode17116w[0..0] & w_data16926w[0..0]), w_anode17034w[3..3]); + w_anode17127w[] = ( (w_anode17127w[2..2] & (! w_data16911w[5..5])), (w_anode17127w[1..1] & w_data16911w[4..4]), (w_anode17127w[0..0] & (! w_data16911w[3..3])), w_anode16913w[2..2]); + w_anode17138w[] = ( (w_anode17138w[2..2] & (! w_data16926w[2..2])), (w_anode17138w[1..1] & (! w_data16926w[1..1])), (w_anode17138w[0..0] & (! w_data16926w[0..0])), w_anode17127w[3..3]); + w_anode17149w[] = ( (w_anode17149w[2..2] & (! w_data16926w[2..2])), (w_anode17149w[1..1] & (! w_data16926w[1..1])), (w_anode17149w[0..0] & w_data16926w[0..0]), w_anode17127w[3..3]); + w_anode17159w[] = ( (w_anode17159w[2..2] & (! w_data16926w[2..2])), (w_anode17159w[1..1] & w_data16926w[1..1]), (w_anode17159w[0..0] & (! w_data16926w[0..0])), w_anode17127w[3..3]); + w_anode17169w[] = ( (w_anode17169w[2..2] & (! w_data16926w[2..2])), (w_anode17169w[1..1] & w_data16926w[1..1]), (w_anode17169w[0..0] & w_data16926w[0..0]), w_anode17127w[3..3]); + w_anode17179w[] = ( (w_anode17179w[2..2] & w_data16926w[2..2]), (w_anode17179w[1..1] & (! w_data16926w[1..1])), (w_anode17179w[0..0] & (! w_data16926w[0..0])), w_anode17127w[3..3]); + w_anode17189w[] = ( (w_anode17189w[2..2] & w_data16926w[2..2]), (w_anode17189w[1..1] & (! w_data16926w[1..1])), (w_anode17189w[0..0] & w_data16926w[0..0]), w_anode17127w[3..3]); + w_anode17199w[] = ( (w_anode17199w[2..2] & w_data16926w[2..2]), (w_anode17199w[1..1] & w_data16926w[1..1]), (w_anode17199w[0..0] & (! w_data16926w[0..0])), w_anode17127w[3..3]); + w_anode17209w[] = ( (w_anode17209w[2..2] & w_data16926w[2..2]), (w_anode17209w[1..1] & w_data16926w[1..1]), (w_anode17209w[0..0] & w_data16926w[0..0]), w_anode17127w[3..3]); + w_anode17220w[] = ( (w_anode17220w[2..2] & (! w_data16911w[5..5])), (w_anode17220w[1..1] & w_data16911w[4..4]), (w_anode17220w[0..0] & w_data16911w[3..3]), w_anode16913w[2..2]); + w_anode17231w[] = ( (w_anode17231w[2..2] & (! w_data16926w[2..2])), (w_anode17231w[1..1] & (! w_data16926w[1..1])), (w_anode17231w[0..0] & (! w_data16926w[0..0])), w_anode17220w[3..3]); + w_anode17242w[] = ( (w_anode17242w[2..2] & (! w_data16926w[2..2])), (w_anode17242w[1..1] & (! w_data16926w[1..1])), (w_anode17242w[0..0] & w_data16926w[0..0]), w_anode17220w[3..3]); + w_anode17252w[] = ( (w_anode17252w[2..2] & (! w_data16926w[2..2])), (w_anode17252w[1..1] & w_data16926w[1..1]), (w_anode17252w[0..0] & (! w_data16926w[0..0])), w_anode17220w[3..3]); + w_anode17262w[] = ( (w_anode17262w[2..2] & (! w_data16926w[2..2])), (w_anode17262w[1..1] & w_data16926w[1..1]), (w_anode17262w[0..0] & w_data16926w[0..0]), w_anode17220w[3..3]); + w_anode17272w[] = ( (w_anode17272w[2..2] & w_data16926w[2..2]), (w_anode17272w[1..1] & (! w_data16926w[1..1])), (w_anode17272w[0..0] & (! w_data16926w[0..0])), w_anode17220w[3..3]); + w_anode17282w[] = ( (w_anode17282w[2..2] & w_data16926w[2..2]), (w_anode17282w[1..1] & (! w_data16926w[1..1])), (w_anode17282w[0..0] & w_data16926w[0..0]), w_anode17220w[3..3]); + w_anode17292w[] = ( (w_anode17292w[2..2] & w_data16926w[2..2]), (w_anode17292w[1..1] & w_data16926w[1..1]), (w_anode17292w[0..0] & (! w_data16926w[0..0])), w_anode17220w[3..3]); + w_anode17302w[] = ( (w_anode17302w[2..2] & w_data16926w[2..2]), (w_anode17302w[1..1] & w_data16926w[1..1]), (w_anode17302w[0..0] & w_data16926w[0..0]), w_anode17220w[3..3]); + w_anode17313w[] = ( (w_anode17313w[2..2] & w_data16911w[5..5]), (w_anode17313w[1..1] & (! w_data16911w[4..4])), (w_anode17313w[0..0] & (! w_data16911w[3..3])), w_anode16913w[2..2]); + w_anode17324w[] = ( (w_anode17324w[2..2] & (! w_data16926w[2..2])), (w_anode17324w[1..1] & (! w_data16926w[1..1])), (w_anode17324w[0..0] & (! w_data16926w[0..0])), w_anode17313w[3..3]); + w_anode17335w[] = ( (w_anode17335w[2..2] & (! w_data16926w[2..2])), (w_anode17335w[1..1] & (! w_data16926w[1..1])), (w_anode17335w[0..0] & w_data16926w[0..0]), w_anode17313w[3..3]); + w_anode17345w[] = ( (w_anode17345w[2..2] & (! w_data16926w[2..2])), (w_anode17345w[1..1] & w_data16926w[1..1]), (w_anode17345w[0..0] & (! w_data16926w[0..0])), w_anode17313w[3..3]); + w_anode17355w[] = ( (w_anode17355w[2..2] & (! w_data16926w[2..2])), (w_anode17355w[1..1] & w_data16926w[1..1]), (w_anode17355w[0..0] & w_data16926w[0..0]), w_anode17313w[3..3]); + w_anode17365w[] = ( (w_anode17365w[2..2] & w_data16926w[2..2]), (w_anode17365w[1..1] & (! w_data16926w[1..1])), (w_anode17365w[0..0] & (! w_data16926w[0..0])), w_anode17313w[3..3]); + w_anode17375w[] = ( (w_anode17375w[2..2] & w_data16926w[2..2]), (w_anode17375w[1..1] & (! w_data16926w[1..1])), (w_anode17375w[0..0] & w_data16926w[0..0]), w_anode17313w[3..3]); + w_anode17385w[] = ( (w_anode17385w[2..2] & w_data16926w[2..2]), (w_anode17385w[1..1] & w_data16926w[1..1]), (w_anode17385w[0..0] & (! w_data16926w[0..0])), w_anode17313w[3..3]); + w_anode17395w[] = ( (w_anode17395w[2..2] & w_data16926w[2..2]), (w_anode17395w[1..1] & w_data16926w[1..1]), (w_anode17395w[0..0] & w_data16926w[0..0]), w_anode17313w[3..3]); + w_anode17406w[] = ( (w_anode17406w[2..2] & w_data16911w[5..5]), (w_anode17406w[1..1] & (! w_data16911w[4..4])), (w_anode17406w[0..0] & w_data16911w[3..3]), w_anode16913w[2..2]); + w_anode17417w[] = ( (w_anode17417w[2..2] & (! w_data16926w[2..2])), (w_anode17417w[1..1] & (! w_data16926w[1..1])), (w_anode17417w[0..0] & (! w_data16926w[0..0])), w_anode17406w[3..3]); + w_anode17428w[] = ( (w_anode17428w[2..2] & (! w_data16926w[2..2])), (w_anode17428w[1..1] & (! w_data16926w[1..1])), (w_anode17428w[0..0] & w_data16926w[0..0]), w_anode17406w[3..3]); + w_anode17438w[] = ( (w_anode17438w[2..2] & (! w_data16926w[2..2])), (w_anode17438w[1..1] & w_data16926w[1..1]), (w_anode17438w[0..0] & (! w_data16926w[0..0])), w_anode17406w[3..3]); + w_anode17448w[] = ( (w_anode17448w[2..2] & (! w_data16926w[2..2])), (w_anode17448w[1..1] & w_data16926w[1..1]), (w_anode17448w[0..0] & w_data16926w[0..0]), w_anode17406w[3..3]); + w_anode17458w[] = ( (w_anode17458w[2..2] & w_data16926w[2..2]), (w_anode17458w[1..1] & (! w_data16926w[1..1])), (w_anode17458w[0..0] & (! w_data16926w[0..0])), w_anode17406w[3..3]); + w_anode17468w[] = ( (w_anode17468w[2..2] & w_data16926w[2..2]), (w_anode17468w[1..1] & (! w_data16926w[1..1])), (w_anode17468w[0..0] & w_data16926w[0..0]), w_anode17406w[3..3]); + w_anode17478w[] = ( (w_anode17478w[2..2] & w_data16926w[2..2]), (w_anode17478w[1..1] & w_data16926w[1..1]), (w_anode17478w[0..0] & (! w_data16926w[0..0])), w_anode17406w[3..3]); + w_anode17488w[] = ( (w_anode17488w[2..2] & w_data16926w[2..2]), (w_anode17488w[1..1] & w_data16926w[1..1]), (w_anode17488w[0..0] & w_data16926w[0..0]), w_anode17406w[3..3]); + w_anode17499w[] = ( (w_anode17499w[2..2] & w_data16911w[5..5]), (w_anode17499w[1..1] & w_data16911w[4..4]), (w_anode17499w[0..0] & (! w_data16911w[3..3])), w_anode16913w[2..2]); + w_anode17510w[] = ( (w_anode17510w[2..2] & (! w_data16926w[2..2])), (w_anode17510w[1..1] & (! w_data16926w[1..1])), (w_anode17510w[0..0] & (! w_data16926w[0..0])), w_anode17499w[3..3]); + w_anode17521w[] = ( (w_anode17521w[2..2] & (! w_data16926w[2..2])), (w_anode17521w[1..1] & (! w_data16926w[1..1])), (w_anode17521w[0..0] & w_data16926w[0..0]), w_anode17499w[3..3]); + w_anode17531w[] = ( (w_anode17531w[2..2] & (! w_data16926w[2..2])), (w_anode17531w[1..1] & w_data16926w[1..1]), (w_anode17531w[0..0] & (! w_data16926w[0..0])), w_anode17499w[3..3]); + w_anode17541w[] = ( (w_anode17541w[2..2] & (! w_data16926w[2..2])), (w_anode17541w[1..1] & w_data16926w[1..1]), (w_anode17541w[0..0] & w_data16926w[0..0]), w_anode17499w[3..3]); + w_anode17551w[] = ( (w_anode17551w[2..2] & w_data16926w[2..2]), (w_anode17551w[1..1] & (! w_data16926w[1..1])), (w_anode17551w[0..0] & (! w_data16926w[0..0])), w_anode17499w[3..3]); + w_anode17561w[] = ( (w_anode17561w[2..2] & w_data16926w[2..2]), (w_anode17561w[1..1] & (! w_data16926w[1..1])), (w_anode17561w[0..0] & w_data16926w[0..0]), w_anode17499w[3..3]); + w_anode17571w[] = ( (w_anode17571w[2..2] & w_data16926w[2..2]), (w_anode17571w[1..1] & w_data16926w[1..1]), (w_anode17571w[0..0] & (! w_data16926w[0..0])), w_anode17499w[3..3]); + w_anode17581w[] = ( (w_anode17581w[2..2] & w_data16926w[2..2]), (w_anode17581w[1..1] & w_data16926w[1..1]), (w_anode17581w[0..0] & w_data16926w[0..0]), w_anode17499w[3..3]); + w_anode17592w[] = ( (w_anode17592w[2..2] & w_data16911w[5..5]), (w_anode17592w[1..1] & w_data16911w[4..4]), (w_anode17592w[0..0] & w_data16911w[3..3]), w_anode16913w[2..2]); + w_anode17603w[] = ( (w_anode17603w[2..2] & (! w_data16926w[2..2])), (w_anode17603w[1..1] & (! w_data16926w[1..1])), (w_anode17603w[0..0] & (! w_data16926w[0..0])), w_anode17592w[3..3]); + w_anode17614w[] = ( (w_anode17614w[2..2] & (! w_data16926w[2..2])), (w_anode17614w[1..1] & (! w_data16926w[1..1])), (w_anode17614w[0..0] & w_data16926w[0..0]), w_anode17592w[3..3]); + w_anode17624w[] = ( (w_anode17624w[2..2] & (! w_data16926w[2..2])), (w_anode17624w[1..1] & w_data16926w[1..1]), (w_anode17624w[0..0] & (! w_data16926w[0..0])), w_anode17592w[3..3]); + w_anode17634w[] = ( (w_anode17634w[2..2] & (! w_data16926w[2..2])), (w_anode17634w[1..1] & w_data16926w[1..1]), (w_anode17634w[0..0] & w_data16926w[0..0]), w_anode17592w[3..3]); + w_anode17644w[] = ( (w_anode17644w[2..2] & w_data16926w[2..2]), (w_anode17644w[1..1] & (! w_data16926w[1..1])), (w_anode17644w[0..0] & (! w_data16926w[0..0])), w_anode17592w[3..3]); + w_anode17654w[] = ( (w_anode17654w[2..2] & w_data16926w[2..2]), (w_anode17654w[1..1] & (! w_data16926w[1..1])), (w_anode17654w[0..0] & w_data16926w[0..0]), w_anode17592w[3..3]); + w_anode17664w[] = ( (w_anode17664w[2..2] & w_data16926w[2..2]), (w_anode17664w[1..1] & w_data16926w[1..1]), (w_anode17664w[0..0] & (! w_data16926w[0..0])), w_anode17592w[3..3]); + w_anode17674w[] = ( (w_anode17674w[2..2] & w_data16926w[2..2]), (w_anode17674w[1..1] & w_data16926w[1..1]), (w_anode17674w[0..0] & w_data16926w[0..0]), w_anode17592w[3..3]); + w_anode17687w[] = ( (w_anode17687w[1..1] & (! data_wire[7..7])), (w_anode17687w[0..0] & data_wire[6..6]), enable_wire); + w_anode17697w[] = ( (w_anode17697w[2..2] & (! w_data16911w[5..5])), (w_anode17697w[1..1] & (! w_data16911w[4..4])), (w_anode17697w[0..0] & (! w_data16911w[3..3])), w_anode17687w[2..2]); + w_anode17708w[] = ( (w_anode17708w[2..2] & (! w_data17696w[2..2])), (w_anode17708w[1..1] & (! w_data17696w[1..1])), (w_anode17708w[0..0] & (! w_data17696w[0..0])), w_anode17697w[3..3]); + w_anode17725w[] = ( (w_anode17725w[2..2] & (! w_data17696w[2..2])), (w_anode17725w[1..1] & (! w_data17696w[1..1])), (w_anode17725w[0..0] & w_data17696w[0..0]), w_anode17697w[3..3]); + w_anode17735w[] = ( (w_anode17735w[2..2] & (! w_data17696w[2..2])), (w_anode17735w[1..1] & w_data17696w[1..1]), (w_anode17735w[0..0] & (! w_data17696w[0..0])), w_anode17697w[3..3]); + w_anode17745w[] = ( (w_anode17745w[2..2] & (! w_data17696w[2..2])), (w_anode17745w[1..1] & w_data17696w[1..1]), (w_anode17745w[0..0] & w_data17696w[0..0]), w_anode17697w[3..3]); + w_anode17755w[] = ( (w_anode17755w[2..2] & w_data17696w[2..2]), (w_anode17755w[1..1] & (! w_data17696w[1..1])), (w_anode17755w[0..0] & (! w_data17696w[0..0])), w_anode17697w[3..3]); + w_anode17765w[] = ( (w_anode17765w[2..2] & w_data17696w[2..2]), (w_anode17765w[1..1] & (! w_data17696w[1..1])), (w_anode17765w[0..0] & w_data17696w[0..0]), w_anode17697w[3..3]); + w_anode17775w[] = ( (w_anode17775w[2..2] & w_data17696w[2..2]), (w_anode17775w[1..1] & w_data17696w[1..1]), (w_anode17775w[0..0] & (! w_data17696w[0..0])), w_anode17697w[3..3]); + w_anode17785w[] = ( (w_anode17785w[2..2] & w_data17696w[2..2]), (w_anode17785w[1..1] & w_data17696w[1..1]), (w_anode17785w[0..0] & w_data17696w[0..0]), w_anode17697w[3..3]); + w_anode17797w[] = ( (w_anode17797w[2..2] & (! w_data16911w[5..5])), (w_anode17797w[1..1] & (! w_data16911w[4..4])), (w_anode17797w[0..0] & w_data16911w[3..3]), w_anode17687w[2..2]); + w_anode17808w[] = ( (w_anode17808w[2..2] & (! w_data17696w[2..2])), (w_anode17808w[1..1] & (! w_data17696w[1..1])), (w_anode17808w[0..0] & (! w_data17696w[0..0])), w_anode17797w[3..3]); + w_anode17819w[] = ( (w_anode17819w[2..2] & (! w_data17696w[2..2])), (w_anode17819w[1..1] & (! w_data17696w[1..1])), (w_anode17819w[0..0] & w_data17696w[0..0]), w_anode17797w[3..3]); + w_anode17829w[] = ( (w_anode17829w[2..2] & (! w_data17696w[2..2])), (w_anode17829w[1..1] & w_data17696w[1..1]), (w_anode17829w[0..0] & (! w_data17696w[0..0])), w_anode17797w[3..3]); + w_anode17839w[] = ( (w_anode17839w[2..2] & (! w_data17696w[2..2])), (w_anode17839w[1..1] & w_data17696w[1..1]), (w_anode17839w[0..0] & w_data17696w[0..0]), w_anode17797w[3..3]); + w_anode17849w[] = ( (w_anode17849w[2..2] & w_data17696w[2..2]), (w_anode17849w[1..1] & (! w_data17696w[1..1])), (w_anode17849w[0..0] & (! w_data17696w[0..0])), w_anode17797w[3..3]); + w_anode17859w[] = ( (w_anode17859w[2..2] & w_data17696w[2..2]), (w_anode17859w[1..1] & (! w_data17696w[1..1])), (w_anode17859w[0..0] & w_data17696w[0..0]), w_anode17797w[3..3]); + w_anode17869w[] = ( (w_anode17869w[2..2] & w_data17696w[2..2]), (w_anode17869w[1..1] & w_data17696w[1..1]), (w_anode17869w[0..0] & (! w_data17696w[0..0])), w_anode17797w[3..3]); + w_anode17879w[] = ( (w_anode17879w[2..2] & w_data17696w[2..2]), (w_anode17879w[1..1] & w_data17696w[1..1]), (w_anode17879w[0..0] & w_data17696w[0..0]), w_anode17797w[3..3]); + w_anode17890w[] = ( (w_anode17890w[2..2] & (! w_data16911w[5..5])), (w_anode17890w[1..1] & w_data16911w[4..4]), (w_anode17890w[0..0] & (! w_data16911w[3..3])), w_anode17687w[2..2]); + w_anode17901w[] = ( (w_anode17901w[2..2] & (! w_data17696w[2..2])), (w_anode17901w[1..1] & (! w_data17696w[1..1])), (w_anode17901w[0..0] & (! w_data17696w[0..0])), w_anode17890w[3..3]); + w_anode17912w[] = ( (w_anode17912w[2..2] & (! w_data17696w[2..2])), (w_anode17912w[1..1] & (! w_data17696w[1..1])), (w_anode17912w[0..0] & w_data17696w[0..0]), w_anode17890w[3..3]); + w_anode17922w[] = ( (w_anode17922w[2..2] & (! w_data17696w[2..2])), (w_anode17922w[1..1] & w_data17696w[1..1]), (w_anode17922w[0..0] & (! w_data17696w[0..0])), w_anode17890w[3..3]); + w_anode17932w[] = ( (w_anode17932w[2..2] & (! w_data17696w[2..2])), (w_anode17932w[1..1] & w_data17696w[1..1]), (w_anode17932w[0..0] & w_data17696w[0..0]), w_anode17890w[3..3]); + w_anode17942w[] = ( (w_anode17942w[2..2] & w_data17696w[2..2]), (w_anode17942w[1..1] & (! w_data17696w[1..1])), (w_anode17942w[0..0] & (! w_data17696w[0..0])), w_anode17890w[3..3]); + w_anode17952w[] = ( (w_anode17952w[2..2] & w_data17696w[2..2]), (w_anode17952w[1..1] & (! w_data17696w[1..1])), (w_anode17952w[0..0] & w_data17696w[0..0]), w_anode17890w[3..3]); + w_anode17962w[] = ( (w_anode17962w[2..2] & w_data17696w[2..2]), (w_anode17962w[1..1] & w_data17696w[1..1]), (w_anode17962w[0..0] & (! w_data17696w[0..0])), w_anode17890w[3..3]); + w_anode17972w[] = ( (w_anode17972w[2..2] & w_data17696w[2..2]), (w_anode17972w[1..1] & w_data17696w[1..1]), (w_anode17972w[0..0] & w_data17696w[0..0]), w_anode17890w[3..3]); + w_anode17983w[] = ( (w_anode17983w[2..2] & (! w_data16911w[5..5])), (w_anode17983w[1..1] & w_data16911w[4..4]), (w_anode17983w[0..0] & w_data16911w[3..3]), w_anode17687w[2..2]); + w_anode17994w[] = ( (w_anode17994w[2..2] & (! w_data17696w[2..2])), (w_anode17994w[1..1] & (! w_data17696w[1..1])), (w_anode17994w[0..0] & (! w_data17696w[0..0])), w_anode17983w[3..3]); + w_anode18005w[] = ( (w_anode18005w[2..2] & (! w_data17696w[2..2])), (w_anode18005w[1..1] & (! w_data17696w[1..1])), (w_anode18005w[0..0] & w_data17696w[0..0]), w_anode17983w[3..3]); + w_anode18015w[] = ( (w_anode18015w[2..2] & (! w_data17696w[2..2])), (w_anode18015w[1..1] & w_data17696w[1..1]), (w_anode18015w[0..0] & (! w_data17696w[0..0])), w_anode17983w[3..3]); + w_anode18025w[] = ( (w_anode18025w[2..2] & (! w_data17696w[2..2])), (w_anode18025w[1..1] & w_data17696w[1..1]), (w_anode18025w[0..0] & w_data17696w[0..0]), w_anode17983w[3..3]); + w_anode18035w[] = ( (w_anode18035w[2..2] & w_data17696w[2..2]), (w_anode18035w[1..1] & (! w_data17696w[1..1])), (w_anode18035w[0..0] & (! w_data17696w[0..0])), w_anode17983w[3..3]); + w_anode18045w[] = ( (w_anode18045w[2..2] & w_data17696w[2..2]), (w_anode18045w[1..1] & (! w_data17696w[1..1])), (w_anode18045w[0..0] & w_data17696w[0..0]), w_anode17983w[3..3]); + w_anode18055w[] = ( (w_anode18055w[2..2] & w_data17696w[2..2]), (w_anode18055w[1..1] & w_data17696w[1..1]), (w_anode18055w[0..0] & (! w_data17696w[0..0])), w_anode17983w[3..3]); + w_anode18065w[] = ( (w_anode18065w[2..2] & w_data17696w[2..2]), (w_anode18065w[1..1] & w_data17696w[1..1]), (w_anode18065w[0..0] & w_data17696w[0..0]), w_anode17983w[3..3]); + w_anode18076w[] = ( (w_anode18076w[2..2] & w_data16911w[5..5]), (w_anode18076w[1..1] & (! w_data16911w[4..4])), (w_anode18076w[0..0] & (! w_data16911w[3..3])), w_anode17687w[2..2]); + w_anode18087w[] = ( (w_anode18087w[2..2] & (! w_data17696w[2..2])), (w_anode18087w[1..1] & (! w_data17696w[1..1])), (w_anode18087w[0..0] & (! w_data17696w[0..0])), w_anode18076w[3..3]); + w_anode18098w[] = ( (w_anode18098w[2..2] & (! w_data17696w[2..2])), (w_anode18098w[1..1] & (! w_data17696w[1..1])), (w_anode18098w[0..0] & w_data17696w[0..0]), w_anode18076w[3..3]); + w_anode18108w[] = ( (w_anode18108w[2..2] & (! w_data17696w[2..2])), (w_anode18108w[1..1] & w_data17696w[1..1]), (w_anode18108w[0..0] & (! w_data17696w[0..0])), w_anode18076w[3..3]); + w_anode18118w[] = ( (w_anode18118w[2..2] & (! w_data17696w[2..2])), (w_anode18118w[1..1] & w_data17696w[1..1]), (w_anode18118w[0..0] & w_data17696w[0..0]), w_anode18076w[3..3]); + w_anode18128w[] = ( (w_anode18128w[2..2] & w_data17696w[2..2]), (w_anode18128w[1..1] & (! w_data17696w[1..1])), (w_anode18128w[0..0] & (! w_data17696w[0..0])), w_anode18076w[3..3]); + w_anode18138w[] = ( (w_anode18138w[2..2] & w_data17696w[2..2]), (w_anode18138w[1..1] & (! w_data17696w[1..1])), (w_anode18138w[0..0] & w_data17696w[0..0]), w_anode18076w[3..3]); + w_anode18148w[] = ( (w_anode18148w[2..2] & w_data17696w[2..2]), (w_anode18148w[1..1] & w_data17696w[1..1]), (w_anode18148w[0..0] & (! w_data17696w[0..0])), w_anode18076w[3..3]); + w_anode18158w[] = ( (w_anode18158w[2..2] & w_data17696w[2..2]), (w_anode18158w[1..1] & w_data17696w[1..1]), (w_anode18158w[0..0] & w_data17696w[0..0]), w_anode18076w[3..3]); + w_anode18169w[] = ( (w_anode18169w[2..2] & w_data16911w[5..5]), (w_anode18169w[1..1] & (! w_data16911w[4..4])), (w_anode18169w[0..0] & w_data16911w[3..3]), w_anode17687w[2..2]); + w_anode18180w[] = ( (w_anode18180w[2..2] & (! w_data17696w[2..2])), (w_anode18180w[1..1] & (! w_data17696w[1..1])), (w_anode18180w[0..0] & (! w_data17696w[0..0])), w_anode18169w[3..3]); + w_anode18191w[] = ( (w_anode18191w[2..2] & (! w_data17696w[2..2])), (w_anode18191w[1..1] & (! w_data17696w[1..1])), (w_anode18191w[0..0] & w_data17696w[0..0]), w_anode18169w[3..3]); + w_anode18201w[] = ( (w_anode18201w[2..2] & (! w_data17696w[2..2])), (w_anode18201w[1..1] & w_data17696w[1..1]), (w_anode18201w[0..0] & (! w_data17696w[0..0])), w_anode18169w[3..3]); + w_anode18211w[] = ( (w_anode18211w[2..2] & (! w_data17696w[2..2])), (w_anode18211w[1..1] & w_data17696w[1..1]), (w_anode18211w[0..0] & w_data17696w[0..0]), w_anode18169w[3..3]); + w_anode18221w[] = ( (w_anode18221w[2..2] & w_data17696w[2..2]), (w_anode18221w[1..1] & (! w_data17696w[1..1])), (w_anode18221w[0..0] & (! w_data17696w[0..0])), w_anode18169w[3..3]); + w_anode18231w[] = ( (w_anode18231w[2..2] & w_data17696w[2..2]), (w_anode18231w[1..1] & (! w_data17696w[1..1])), (w_anode18231w[0..0] & w_data17696w[0..0]), w_anode18169w[3..3]); + w_anode18241w[] = ( (w_anode18241w[2..2] & w_data17696w[2..2]), (w_anode18241w[1..1] & w_data17696w[1..1]), (w_anode18241w[0..0] & (! w_data17696w[0..0])), w_anode18169w[3..3]); + w_anode18251w[] = ( (w_anode18251w[2..2] & w_data17696w[2..2]), (w_anode18251w[1..1] & w_data17696w[1..1]), (w_anode18251w[0..0] & w_data17696w[0..0]), w_anode18169w[3..3]); + w_anode18262w[] = ( (w_anode18262w[2..2] & w_data16911w[5..5]), (w_anode18262w[1..1] & w_data16911w[4..4]), (w_anode18262w[0..0] & (! w_data16911w[3..3])), w_anode17687w[2..2]); + w_anode18273w[] = ( (w_anode18273w[2..2] & (! w_data17696w[2..2])), (w_anode18273w[1..1] & (! w_data17696w[1..1])), (w_anode18273w[0..0] & (! w_data17696w[0..0])), w_anode18262w[3..3]); + w_anode18284w[] = ( (w_anode18284w[2..2] & (! w_data17696w[2..2])), (w_anode18284w[1..1] & (! w_data17696w[1..1])), (w_anode18284w[0..0] & w_data17696w[0..0]), w_anode18262w[3..3]); + w_anode18294w[] = ( (w_anode18294w[2..2] & (! w_data17696w[2..2])), (w_anode18294w[1..1] & w_data17696w[1..1]), (w_anode18294w[0..0] & (! w_data17696w[0..0])), w_anode18262w[3..3]); + w_anode18304w[] = ( (w_anode18304w[2..2] & (! w_data17696w[2..2])), (w_anode18304w[1..1] & w_data17696w[1..1]), (w_anode18304w[0..0] & w_data17696w[0..0]), w_anode18262w[3..3]); + w_anode18314w[] = ( (w_anode18314w[2..2] & w_data17696w[2..2]), (w_anode18314w[1..1] & (! w_data17696w[1..1])), (w_anode18314w[0..0] & (! w_data17696w[0..0])), w_anode18262w[3..3]); + w_anode18324w[] = ( (w_anode18324w[2..2] & w_data17696w[2..2]), (w_anode18324w[1..1] & (! w_data17696w[1..1])), (w_anode18324w[0..0] & w_data17696w[0..0]), w_anode18262w[3..3]); + w_anode18334w[] = ( (w_anode18334w[2..2] & w_data17696w[2..2]), (w_anode18334w[1..1] & w_data17696w[1..1]), (w_anode18334w[0..0] & (! w_data17696w[0..0])), w_anode18262w[3..3]); + w_anode18344w[] = ( (w_anode18344w[2..2] & w_data17696w[2..2]), (w_anode18344w[1..1] & w_data17696w[1..1]), (w_anode18344w[0..0] & w_data17696w[0..0]), w_anode18262w[3..3]); + w_anode18355w[] = ( (w_anode18355w[2..2] & w_data16911w[5..5]), (w_anode18355w[1..1] & w_data16911w[4..4]), (w_anode18355w[0..0] & w_data16911w[3..3]), w_anode17687w[2..2]); + w_anode18366w[] = ( (w_anode18366w[2..2] & (! w_data17696w[2..2])), (w_anode18366w[1..1] & (! w_data17696w[1..1])), (w_anode18366w[0..0] & (! w_data17696w[0..0])), w_anode18355w[3..3]); + w_anode18377w[] = ( (w_anode18377w[2..2] & (! w_data17696w[2..2])), (w_anode18377w[1..1] & (! w_data17696w[1..1])), (w_anode18377w[0..0] & w_data17696w[0..0]), w_anode18355w[3..3]); + w_anode18387w[] = ( (w_anode18387w[2..2] & (! w_data17696w[2..2])), (w_anode18387w[1..1] & w_data17696w[1..1]), (w_anode18387w[0..0] & (! w_data17696w[0..0])), w_anode18355w[3..3]); + w_anode18397w[] = ( (w_anode18397w[2..2] & (! w_data17696w[2..2])), (w_anode18397w[1..1] & w_data17696w[1..1]), (w_anode18397w[0..0] & w_data17696w[0..0]), w_anode18355w[3..3]); + w_anode18407w[] = ( (w_anode18407w[2..2] & w_data17696w[2..2]), (w_anode18407w[1..1] & (! w_data17696w[1..1])), (w_anode18407w[0..0] & (! w_data17696w[0..0])), w_anode18355w[3..3]); + w_anode18417w[] = ( (w_anode18417w[2..2] & w_data17696w[2..2]), (w_anode18417w[1..1] & (! w_data17696w[1..1])), (w_anode18417w[0..0] & w_data17696w[0..0]), w_anode18355w[3..3]); + w_anode18427w[] = ( (w_anode18427w[2..2] & w_data17696w[2..2]), (w_anode18427w[1..1] & w_data17696w[1..1]), (w_anode18427w[0..0] & (! w_data17696w[0..0])), w_anode18355w[3..3]); + w_anode18437w[] = ( (w_anode18437w[2..2] & w_data17696w[2..2]), (w_anode18437w[1..1] & w_data17696w[1..1]), (w_anode18437w[0..0] & w_data17696w[0..0]), w_anode18355w[3..3]); + w_anode18449w[] = ( (w_anode18449w[1..1] & data_wire[7..7]), (w_anode18449w[0..0] & (! data_wire[6..6])), enable_wire); + w_anode18459w[] = ( (w_anode18459w[2..2] & (! w_data16911w[5..5])), (w_anode18459w[1..1] & (! w_data16911w[4..4])), (w_anode18459w[0..0] & (! w_data16911w[3..3])), w_anode18449w[2..2]); + w_anode18470w[] = ( (w_anode18470w[2..2] & (! w_data18458w[2..2])), (w_anode18470w[1..1] & (! w_data18458w[1..1])), (w_anode18470w[0..0] & (! w_data18458w[0..0])), w_anode18459w[3..3]); + w_anode18487w[] = ( (w_anode18487w[2..2] & (! w_data18458w[2..2])), (w_anode18487w[1..1] & (! w_data18458w[1..1])), (w_anode18487w[0..0] & w_data18458w[0..0]), w_anode18459w[3..3]); + w_anode18497w[] = ( (w_anode18497w[2..2] & (! w_data18458w[2..2])), (w_anode18497w[1..1] & w_data18458w[1..1]), (w_anode18497w[0..0] & (! w_data18458w[0..0])), w_anode18459w[3..3]); + w_anode18507w[] = ( (w_anode18507w[2..2] & (! w_data18458w[2..2])), (w_anode18507w[1..1] & w_data18458w[1..1]), (w_anode18507w[0..0] & w_data18458w[0..0]), w_anode18459w[3..3]); + w_anode18517w[] = ( (w_anode18517w[2..2] & w_data18458w[2..2]), (w_anode18517w[1..1] & (! w_data18458w[1..1])), (w_anode18517w[0..0] & (! w_data18458w[0..0])), w_anode18459w[3..3]); + w_anode18527w[] = ( (w_anode18527w[2..2] & w_data18458w[2..2]), (w_anode18527w[1..1] & (! w_data18458w[1..1])), (w_anode18527w[0..0] & w_data18458w[0..0]), w_anode18459w[3..3]); + w_anode18537w[] = ( (w_anode18537w[2..2] & w_data18458w[2..2]), (w_anode18537w[1..1] & w_data18458w[1..1]), (w_anode18537w[0..0] & (! w_data18458w[0..0])), w_anode18459w[3..3]); + w_anode18547w[] = ( (w_anode18547w[2..2] & w_data18458w[2..2]), (w_anode18547w[1..1] & w_data18458w[1..1]), (w_anode18547w[0..0] & w_data18458w[0..0]), w_anode18459w[3..3]); + w_anode18559w[] = ( (w_anode18559w[2..2] & (! w_data16911w[5..5])), (w_anode18559w[1..1] & (! w_data16911w[4..4])), (w_anode18559w[0..0] & w_data16911w[3..3]), w_anode18449w[2..2]); + w_anode18570w[] = ( (w_anode18570w[2..2] & (! w_data18458w[2..2])), (w_anode18570w[1..1] & (! w_data18458w[1..1])), (w_anode18570w[0..0] & (! w_data18458w[0..0])), w_anode18559w[3..3]); + w_anode18581w[] = ( (w_anode18581w[2..2] & (! w_data18458w[2..2])), (w_anode18581w[1..1] & (! w_data18458w[1..1])), (w_anode18581w[0..0] & w_data18458w[0..0]), w_anode18559w[3..3]); + w_anode18591w[] = ( (w_anode18591w[2..2] & (! w_data18458w[2..2])), (w_anode18591w[1..1] & w_data18458w[1..1]), (w_anode18591w[0..0] & (! w_data18458w[0..0])), w_anode18559w[3..3]); + w_anode18601w[] = ( (w_anode18601w[2..2] & (! w_data18458w[2..2])), (w_anode18601w[1..1] & w_data18458w[1..1]), (w_anode18601w[0..0] & w_data18458w[0..0]), w_anode18559w[3..3]); + w_anode18611w[] = ( (w_anode18611w[2..2] & w_data18458w[2..2]), (w_anode18611w[1..1] & (! w_data18458w[1..1])), (w_anode18611w[0..0] & (! w_data18458w[0..0])), w_anode18559w[3..3]); + w_anode18621w[] = ( (w_anode18621w[2..2] & w_data18458w[2..2]), (w_anode18621w[1..1] & (! w_data18458w[1..1])), (w_anode18621w[0..0] & w_data18458w[0..0]), w_anode18559w[3..3]); + w_anode18631w[] = ( (w_anode18631w[2..2] & w_data18458w[2..2]), (w_anode18631w[1..1] & w_data18458w[1..1]), (w_anode18631w[0..0] & (! w_data18458w[0..0])), w_anode18559w[3..3]); + w_anode18641w[] = ( (w_anode18641w[2..2] & w_data18458w[2..2]), (w_anode18641w[1..1] & w_data18458w[1..1]), (w_anode18641w[0..0] & w_data18458w[0..0]), w_anode18559w[3..3]); + w_anode18652w[] = ( (w_anode18652w[2..2] & (! w_data16911w[5..5])), (w_anode18652w[1..1] & w_data16911w[4..4]), (w_anode18652w[0..0] & (! w_data16911w[3..3])), w_anode18449w[2..2]); + w_anode18663w[] = ( (w_anode18663w[2..2] & (! w_data18458w[2..2])), (w_anode18663w[1..1] & (! w_data18458w[1..1])), (w_anode18663w[0..0] & (! w_data18458w[0..0])), w_anode18652w[3..3]); + w_anode18674w[] = ( (w_anode18674w[2..2] & (! w_data18458w[2..2])), (w_anode18674w[1..1] & (! w_data18458w[1..1])), (w_anode18674w[0..0] & w_data18458w[0..0]), w_anode18652w[3..3]); + w_anode18684w[] = ( (w_anode18684w[2..2] & (! w_data18458w[2..2])), (w_anode18684w[1..1] & w_data18458w[1..1]), (w_anode18684w[0..0] & (! w_data18458w[0..0])), w_anode18652w[3..3]); + w_anode18694w[] = ( (w_anode18694w[2..2] & (! w_data18458w[2..2])), (w_anode18694w[1..1] & w_data18458w[1..1]), (w_anode18694w[0..0] & w_data18458w[0..0]), w_anode18652w[3..3]); + w_anode18704w[] = ( (w_anode18704w[2..2] & w_data18458w[2..2]), (w_anode18704w[1..1] & (! w_data18458w[1..1])), (w_anode18704w[0..0] & (! w_data18458w[0..0])), w_anode18652w[3..3]); + w_anode18714w[] = ( (w_anode18714w[2..2] & w_data18458w[2..2]), (w_anode18714w[1..1] & (! w_data18458w[1..1])), (w_anode18714w[0..0] & w_data18458w[0..0]), w_anode18652w[3..3]); + w_anode18724w[] = ( (w_anode18724w[2..2] & w_data18458w[2..2]), (w_anode18724w[1..1] & w_data18458w[1..1]), (w_anode18724w[0..0] & (! w_data18458w[0..0])), w_anode18652w[3..3]); + w_anode18734w[] = ( (w_anode18734w[2..2] & w_data18458w[2..2]), (w_anode18734w[1..1] & w_data18458w[1..1]), (w_anode18734w[0..0] & w_data18458w[0..0]), w_anode18652w[3..3]); + w_anode18745w[] = ( (w_anode18745w[2..2] & (! w_data16911w[5..5])), (w_anode18745w[1..1] & w_data16911w[4..4]), (w_anode18745w[0..0] & w_data16911w[3..3]), w_anode18449w[2..2]); + w_anode18756w[] = ( (w_anode18756w[2..2] & (! w_data18458w[2..2])), (w_anode18756w[1..1] & (! w_data18458w[1..1])), (w_anode18756w[0..0] & (! w_data18458w[0..0])), w_anode18745w[3..3]); + w_anode18767w[] = ( (w_anode18767w[2..2] & (! w_data18458w[2..2])), (w_anode18767w[1..1] & (! w_data18458w[1..1])), (w_anode18767w[0..0] & w_data18458w[0..0]), w_anode18745w[3..3]); + w_anode18777w[] = ( (w_anode18777w[2..2] & (! w_data18458w[2..2])), (w_anode18777w[1..1] & w_data18458w[1..1]), (w_anode18777w[0..0] & (! w_data18458w[0..0])), w_anode18745w[3..3]); + w_anode18787w[] = ( (w_anode18787w[2..2] & (! w_data18458w[2..2])), (w_anode18787w[1..1] & w_data18458w[1..1]), (w_anode18787w[0..0] & w_data18458w[0..0]), w_anode18745w[3..3]); + w_anode18797w[] = ( (w_anode18797w[2..2] & w_data18458w[2..2]), (w_anode18797w[1..1] & (! w_data18458w[1..1])), (w_anode18797w[0..0] & (! w_data18458w[0..0])), w_anode18745w[3..3]); + w_anode18807w[] = ( (w_anode18807w[2..2] & w_data18458w[2..2]), (w_anode18807w[1..1] & (! w_data18458w[1..1])), (w_anode18807w[0..0] & w_data18458w[0..0]), w_anode18745w[3..3]); + w_anode18817w[] = ( (w_anode18817w[2..2] & w_data18458w[2..2]), (w_anode18817w[1..1] & w_data18458w[1..1]), (w_anode18817w[0..0] & (! w_data18458w[0..0])), w_anode18745w[3..3]); + w_anode18827w[] = ( (w_anode18827w[2..2] & w_data18458w[2..2]), (w_anode18827w[1..1] & w_data18458w[1..1]), (w_anode18827w[0..0] & w_data18458w[0..0]), w_anode18745w[3..3]); + w_anode18838w[] = ( (w_anode18838w[2..2] & w_data16911w[5..5]), (w_anode18838w[1..1] & (! w_data16911w[4..4])), (w_anode18838w[0..0] & (! w_data16911w[3..3])), w_anode18449w[2..2]); + w_anode18849w[] = ( (w_anode18849w[2..2] & (! w_data18458w[2..2])), (w_anode18849w[1..1] & (! w_data18458w[1..1])), (w_anode18849w[0..0] & (! w_data18458w[0..0])), w_anode18838w[3..3]); + w_anode18860w[] = ( (w_anode18860w[2..2] & (! w_data18458w[2..2])), (w_anode18860w[1..1] & (! w_data18458w[1..1])), (w_anode18860w[0..0] & w_data18458w[0..0]), w_anode18838w[3..3]); + w_anode18870w[] = ( (w_anode18870w[2..2] & (! w_data18458w[2..2])), (w_anode18870w[1..1] & w_data18458w[1..1]), (w_anode18870w[0..0] & (! w_data18458w[0..0])), w_anode18838w[3..3]); + w_anode18880w[] = ( (w_anode18880w[2..2] & (! w_data18458w[2..2])), (w_anode18880w[1..1] & w_data18458w[1..1]), (w_anode18880w[0..0] & w_data18458w[0..0]), w_anode18838w[3..3]); + w_anode18890w[] = ( (w_anode18890w[2..2] & w_data18458w[2..2]), (w_anode18890w[1..1] & (! w_data18458w[1..1])), (w_anode18890w[0..0] & (! w_data18458w[0..0])), w_anode18838w[3..3]); + w_anode18900w[] = ( (w_anode18900w[2..2] & w_data18458w[2..2]), (w_anode18900w[1..1] & (! w_data18458w[1..1])), (w_anode18900w[0..0] & w_data18458w[0..0]), w_anode18838w[3..3]); + w_anode18910w[] = ( (w_anode18910w[2..2] & w_data18458w[2..2]), (w_anode18910w[1..1] & w_data18458w[1..1]), (w_anode18910w[0..0] & (! w_data18458w[0..0])), w_anode18838w[3..3]); + w_anode18920w[] = ( (w_anode18920w[2..2] & w_data18458w[2..2]), (w_anode18920w[1..1] & w_data18458w[1..1]), (w_anode18920w[0..0] & w_data18458w[0..0]), w_anode18838w[3..3]); + w_anode18931w[] = ( (w_anode18931w[2..2] & w_data16911w[5..5]), (w_anode18931w[1..1] & (! w_data16911w[4..4])), (w_anode18931w[0..0] & w_data16911w[3..3]), w_anode18449w[2..2]); + w_anode18942w[] = ( (w_anode18942w[2..2] & (! w_data18458w[2..2])), (w_anode18942w[1..1] & (! w_data18458w[1..1])), (w_anode18942w[0..0] & (! w_data18458w[0..0])), w_anode18931w[3..3]); + w_anode18953w[] = ( (w_anode18953w[2..2] & (! w_data18458w[2..2])), (w_anode18953w[1..1] & (! w_data18458w[1..1])), (w_anode18953w[0..0] & w_data18458w[0..0]), w_anode18931w[3..3]); + w_anode18963w[] = ( (w_anode18963w[2..2] & (! w_data18458w[2..2])), (w_anode18963w[1..1] & w_data18458w[1..1]), (w_anode18963w[0..0] & (! w_data18458w[0..0])), w_anode18931w[3..3]); + w_anode18973w[] = ( (w_anode18973w[2..2] & (! w_data18458w[2..2])), (w_anode18973w[1..1] & w_data18458w[1..1]), (w_anode18973w[0..0] & w_data18458w[0..0]), w_anode18931w[3..3]); + w_anode18983w[] = ( (w_anode18983w[2..2] & w_data18458w[2..2]), (w_anode18983w[1..1] & (! w_data18458w[1..1])), (w_anode18983w[0..0] & (! w_data18458w[0..0])), w_anode18931w[3..3]); + w_anode18993w[] = ( (w_anode18993w[2..2] & w_data18458w[2..2]), (w_anode18993w[1..1] & (! w_data18458w[1..1])), (w_anode18993w[0..0] & w_data18458w[0..0]), w_anode18931w[3..3]); + w_anode19003w[] = ( (w_anode19003w[2..2] & w_data18458w[2..2]), (w_anode19003w[1..1] & w_data18458w[1..1]), (w_anode19003w[0..0] & (! w_data18458w[0..0])), w_anode18931w[3..3]); + w_anode19013w[] = ( (w_anode19013w[2..2] & w_data18458w[2..2]), (w_anode19013w[1..1] & w_data18458w[1..1]), (w_anode19013w[0..0] & w_data18458w[0..0]), w_anode18931w[3..3]); + w_anode19024w[] = ( (w_anode19024w[2..2] & w_data16911w[5..5]), (w_anode19024w[1..1] & w_data16911w[4..4]), (w_anode19024w[0..0] & (! w_data16911w[3..3])), w_anode18449w[2..2]); + w_anode19035w[] = ( (w_anode19035w[2..2] & (! w_data18458w[2..2])), (w_anode19035w[1..1] & (! w_data18458w[1..1])), (w_anode19035w[0..0] & (! w_data18458w[0..0])), w_anode19024w[3..3]); + w_anode19046w[] = ( (w_anode19046w[2..2] & (! w_data18458w[2..2])), (w_anode19046w[1..1] & (! w_data18458w[1..1])), (w_anode19046w[0..0] & w_data18458w[0..0]), w_anode19024w[3..3]); + w_anode19056w[] = ( (w_anode19056w[2..2] & (! w_data18458w[2..2])), (w_anode19056w[1..1] & w_data18458w[1..1]), (w_anode19056w[0..0] & (! w_data18458w[0..0])), w_anode19024w[3..3]); + w_anode19066w[] = ( (w_anode19066w[2..2] & (! w_data18458w[2..2])), (w_anode19066w[1..1] & w_data18458w[1..1]), (w_anode19066w[0..0] & w_data18458w[0..0]), w_anode19024w[3..3]); + w_anode19076w[] = ( (w_anode19076w[2..2] & w_data18458w[2..2]), (w_anode19076w[1..1] & (! w_data18458w[1..1])), (w_anode19076w[0..0] & (! w_data18458w[0..0])), w_anode19024w[3..3]); + w_anode19086w[] = ( (w_anode19086w[2..2] & w_data18458w[2..2]), (w_anode19086w[1..1] & (! w_data18458w[1..1])), (w_anode19086w[0..0] & w_data18458w[0..0]), w_anode19024w[3..3]); + w_anode19096w[] = ( (w_anode19096w[2..2] & w_data18458w[2..2]), (w_anode19096w[1..1] & w_data18458w[1..1]), (w_anode19096w[0..0] & (! w_data18458w[0..0])), w_anode19024w[3..3]); + w_anode19106w[] = ( (w_anode19106w[2..2] & w_data18458w[2..2]), (w_anode19106w[1..1] & w_data18458w[1..1]), (w_anode19106w[0..0] & w_data18458w[0..0]), w_anode19024w[3..3]); + w_anode19117w[] = ( (w_anode19117w[2..2] & w_data16911w[5..5]), (w_anode19117w[1..1] & w_data16911w[4..4]), (w_anode19117w[0..0] & w_data16911w[3..3]), w_anode18449w[2..2]); + w_anode19128w[] = ( (w_anode19128w[2..2] & (! w_data18458w[2..2])), (w_anode19128w[1..1] & (! w_data18458w[1..1])), (w_anode19128w[0..0] & (! w_data18458w[0..0])), w_anode19117w[3..3]); + w_anode19139w[] = ( (w_anode19139w[2..2] & (! w_data18458w[2..2])), (w_anode19139w[1..1] & (! w_data18458w[1..1])), (w_anode19139w[0..0] & w_data18458w[0..0]), w_anode19117w[3..3]); + w_anode19149w[] = ( (w_anode19149w[2..2] & (! w_data18458w[2..2])), (w_anode19149w[1..1] & w_data18458w[1..1]), (w_anode19149w[0..0] & (! w_data18458w[0..0])), w_anode19117w[3..3]); + w_anode19159w[] = ( (w_anode19159w[2..2] & (! w_data18458w[2..2])), (w_anode19159w[1..1] & w_data18458w[1..1]), (w_anode19159w[0..0] & w_data18458w[0..0]), w_anode19117w[3..3]); + w_anode19169w[] = ( (w_anode19169w[2..2] & w_data18458w[2..2]), (w_anode19169w[1..1] & (! w_data18458w[1..1])), (w_anode19169w[0..0] & (! w_data18458w[0..0])), w_anode19117w[3..3]); + w_anode19179w[] = ( (w_anode19179w[2..2] & w_data18458w[2..2]), (w_anode19179w[1..1] & (! w_data18458w[1..1])), (w_anode19179w[0..0] & w_data18458w[0..0]), w_anode19117w[3..3]); + w_anode19189w[] = ( (w_anode19189w[2..2] & w_data18458w[2..2]), (w_anode19189w[1..1] & w_data18458w[1..1]), (w_anode19189w[0..0] & (! w_data18458w[0..0])), w_anode19117w[3..3]); + w_anode19199w[] = ( (w_anode19199w[2..2] & w_data18458w[2..2]), (w_anode19199w[1..1] & w_data18458w[1..1]), (w_anode19199w[0..0] & w_data18458w[0..0]), w_anode19117w[3..3]); + w_anode19211w[] = ( (w_anode19211w[1..1] & data_wire[7..7]), (w_anode19211w[0..0] & data_wire[6..6]), enable_wire); + w_anode19221w[] = ( (w_anode19221w[2..2] & (! w_data16911w[5..5])), (w_anode19221w[1..1] & (! w_data16911w[4..4])), (w_anode19221w[0..0] & (! w_data16911w[3..3])), w_anode19211w[2..2]); + w_anode19232w[] = ( (w_anode19232w[2..2] & (! w_data19220w[2..2])), (w_anode19232w[1..1] & (! w_data19220w[1..1])), (w_anode19232w[0..0] & (! w_data19220w[0..0])), w_anode19221w[3..3]); + w_anode19249w[] = ( (w_anode19249w[2..2] & (! w_data19220w[2..2])), (w_anode19249w[1..1] & (! w_data19220w[1..1])), (w_anode19249w[0..0] & w_data19220w[0..0]), w_anode19221w[3..3]); + w_anode19259w[] = ( (w_anode19259w[2..2] & (! w_data19220w[2..2])), (w_anode19259w[1..1] & w_data19220w[1..1]), (w_anode19259w[0..0] & (! w_data19220w[0..0])), w_anode19221w[3..3]); + w_anode19269w[] = ( (w_anode19269w[2..2] & (! w_data19220w[2..2])), (w_anode19269w[1..1] & w_data19220w[1..1]), (w_anode19269w[0..0] & w_data19220w[0..0]), w_anode19221w[3..3]); + w_anode19279w[] = ( (w_anode19279w[2..2] & w_data19220w[2..2]), (w_anode19279w[1..1] & (! w_data19220w[1..1])), (w_anode19279w[0..0] & (! w_data19220w[0..0])), w_anode19221w[3..3]); + w_anode19289w[] = ( (w_anode19289w[2..2] & w_data19220w[2..2]), (w_anode19289w[1..1] & (! w_data19220w[1..1])), (w_anode19289w[0..0] & w_data19220w[0..0]), w_anode19221w[3..3]); + w_anode19299w[] = ( (w_anode19299w[2..2] & w_data19220w[2..2]), (w_anode19299w[1..1] & w_data19220w[1..1]), (w_anode19299w[0..0] & (! w_data19220w[0..0])), w_anode19221w[3..3]); + w_anode19309w[] = ( (w_anode19309w[2..2] & w_data19220w[2..2]), (w_anode19309w[1..1] & w_data19220w[1..1]), (w_anode19309w[0..0] & w_data19220w[0..0]), w_anode19221w[3..3]); + w_anode19321w[] = ( (w_anode19321w[2..2] & (! w_data16911w[5..5])), (w_anode19321w[1..1] & (! w_data16911w[4..4])), (w_anode19321w[0..0] & w_data16911w[3..3]), w_anode19211w[2..2]); + w_anode19332w[] = ( (w_anode19332w[2..2] & (! w_data19220w[2..2])), (w_anode19332w[1..1] & (! w_data19220w[1..1])), (w_anode19332w[0..0] & (! w_data19220w[0..0])), w_anode19321w[3..3]); + w_anode19343w[] = ( (w_anode19343w[2..2] & (! w_data19220w[2..2])), (w_anode19343w[1..1] & (! w_data19220w[1..1])), (w_anode19343w[0..0] & w_data19220w[0..0]), w_anode19321w[3..3]); + w_anode19353w[] = ( (w_anode19353w[2..2] & (! w_data19220w[2..2])), (w_anode19353w[1..1] & w_data19220w[1..1]), (w_anode19353w[0..0] & (! w_data19220w[0..0])), w_anode19321w[3..3]); + w_anode19363w[] = ( (w_anode19363w[2..2] & (! w_data19220w[2..2])), (w_anode19363w[1..1] & w_data19220w[1..1]), (w_anode19363w[0..0] & w_data19220w[0..0]), w_anode19321w[3..3]); + w_anode19373w[] = ( (w_anode19373w[2..2] & w_data19220w[2..2]), (w_anode19373w[1..1] & (! w_data19220w[1..1])), (w_anode19373w[0..0] & (! w_data19220w[0..0])), w_anode19321w[3..3]); + w_anode19383w[] = ( (w_anode19383w[2..2] & w_data19220w[2..2]), (w_anode19383w[1..1] & (! w_data19220w[1..1])), (w_anode19383w[0..0] & w_data19220w[0..0]), w_anode19321w[3..3]); + w_anode19393w[] = ( (w_anode19393w[2..2] & w_data19220w[2..2]), (w_anode19393w[1..1] & w_data19220w[1..1]), (w_anode19393w[0..0] & (! w_data19220w[0..0])), w_anode19321w[3..3]); + w_anode19403w[] = ( (w_anode19403w[2..2] & w_data19220w[2..2]), (w_anode19403w[1..1] & w_data19220w[1..1]), (w_anode19403w[0..0] & w_data19220w[0..0]), w_anode19321w[3..3]); + w_anode19414w[] = ( (w_anode19414w[2..2] & (! w_data16911w[5..5])), (w_anode19414w[1..1] & w_data16911w[4..4]), (w_anode19414w[0..0] & (! w_data16911w[3..3])), w_anode19211w[2..2]); + w_anode19425w[] = ( (w_anode19425w[2..2] & (! w_data19220w[2..2])), (w_anode19425w[1..1] & (! w_data19220w[1..1])), (w_anode19425w[0..0] & (! w_data19220w[0..0])), w_anode19414w[3..3]); + w_anode19436w[] = ( (w_anode19436w[2..2] & (! w_data19220w[2..2])), (w_anode19436w[1..1] & (! w_data19220w[1..1])), (w_anode19436w[0..0] & w_data19220w[0..0]), w_anode19414w[3..3]); + w_anode19446w[] = ( (w_anode19446w[2..2] & (! w_data19220w[2..2])), (w_anode19446w[1..1] & w_data19220w[1..1]), (w_anode19446w[0..0] & (! w_data19220w[0..0])), w_anode19414w[3..3]); + w_anode19456w[] = ( (w_anode19456w[2..2] & (! w_data19220w[2..2])), (w_anode19456w[1..1] & w_data19220w[1..1]), (w_anode19456w[0..0] & w_data19220w[0..0]), w_anode19414w[3..3]); + w_anode19466w[] = ( (w_anode19466w[2..2] & w_data19220w[2..2]), (w_anode19466w[1..1] & (! w_data19220w[1..1])), (w_anode19466w[0..0] & (! w_data19220w[0..0])), w_anode19414w[3..3]); + w_anode19476w[] = ( (w_anode19476w[2..2] & w_data19220w[2..2]), (w_anode19476w[1..1] & (! w_data19220w[1..1])), (w_anode19476w[0..0] & w_data19220w[0..0]), w_anode19414w[3..3]); + w_anode19486w[] = ( (w_anode19486w[2..2] & w_data19220w[2..2]), (w_anode19486w[1..1] & w_data19220w[1..1]), (w_anode19486w[0..0] & (! w_data19220w[0..0])), w_anode19414w[3..3]); + w_anode19496w[] = ( (w_anode19496w[2..2] & w_data19220w[2..2]), (w_anode19496w[1..1] & w_data19220w[1..1]), (w_anode19496w[0..0] & w_data19220w[0..0]), w_anode19414w[3..3]); + w_anode19507w[] = ( (w_anode19507w[2..2] & (! w_data16911w[5..5])), (w_anode19507w[1..1] & w_data16911w[4..4]), (w_anode19507w[0..0] & w_data16911w[3..3]), w_anode19211w[2..2]); + w_anode19518w[] = ( (w_anode19518w[2..2] & (! w_data19220w[2..2])), (w_anode19518w[1..1] & (! w_data19220w[1..1])), (w_anode19518w[0..0] & (! w_data19220w[0..0])), w_anode19507w[3..3]); + w_anode19529w[] = ( (w_anode19529w[2..2] & (! w_data19220w[2..2])), (w_anode19529w[1..1] & (! w_data19220w[1..1])), (w_anode19529w[0..0] & w_data19220w[0..0]), w_anode19507w[3..3]); + w_anode19539w[] = ( (w_anode19539w[2..2] & (! w_data19220w[2..2])), (w_anode19539w[1..1] & w_data19220w[1..1]), (w_anode19539w[0..0] & (! w_data19220w[0..0])), w_anode19507w[3..3]); + w_anode19549w[] = ( (w_anode19549w[2..2] & (! w_data19220w[2..2])), (w_anode19549w[1..1] & w_data19220w[1..1]), (w_anode19549w[0..0] & w_data19220w[0..0]), w_anode19507w[3..3]); + w_anode19559w[] = ( (w_anode19559w[2..2] & w_data19220w[2..2]), (w_anode19559w[1..1] & (! w_data19220w[1..1])), (w_anode19559w[0..0] & (! w_data19220w[0..0])), w_anode19507w[3..3]); + w_anode19569w[] = ( (w_anode19569w[2..2] & w_data19220w[2..2]), (w_anode19569w[1..1] & (! w_data19220w[1..1])), (w_anode19569w[0..0] & w_data19220w[0..0]), w_anode19507w[3..3]); + w_anode19579w[] = ( (w_anode19579w[2..2] & w_data19220w[2..2]), (w_anode19579w[1..1] & w_data19220w[1..1]), (w_anode19579w[0..0] & (! w_data19220w[0..0])), w_anode19507w[3..3]); + w_anode19589w[] = ( (w_anode19589w[2..2] & w_data19220w[2..2]), (w_anode19589w[1..1] & w_data19220w[1..1]), (w_anode19589w[0..0] & w_data19220w[0..0]), w_anode19507w[3..3]); + w_anode19600w[] = ( (w_anode19600w[2..2] & w_data16911w[5..5]), (w_anode19600w[1..1] & (! w_data16911w[4..4])), (w_anode19600w[0..0] & (! w_data16911w[3..3])), w_anode19211w[2..2]); + w_anode19611w[] = ( (w_anode19611w[2..2] & (! w_data19220w[2..2])), (w_anode19611w[1..1] & (! w_data19220w[1..1])), (w_anode19611w[0..0] & (! w_data19220w[0..0])), w_anode19600w[3..3]); + w_anode19622w[] = ( (w_anode19622w[2..2] & (! w_data19220w[2..2])), (w_anode19622w[1..1] & (! w_data19220w[1..1])), (w_anode19622w[0..0] & w_data19220w[0..0]), w_anode19600w[3..3]); + w_anode19632w[] = ( (w_anode19632w[2..2] & (! w_data19220w[2..2])), (w_anode19632w[1..1] & w_data19220w[1..1]), (w_anode19632w[0..0] & (! w_data19220w[0..0])), w_anode19600w[3..3]); + w_anode19642w[] = ( (w_anode19642w[2..2] & (! w_data19220w[2..2])), (w_anode19642w[1..1] & w_data19220w[1..1]), (w_anode19642w[0..0] & w_data19220w[0..0]), w_anode19600w[3..3]); + w_anode19652w[] = ( (w_anode19652w[2..2] & w_data19220w[2..2]), (w_anode19652w[1..1] & (! w_data19220w[1..1])), (w_anode19652w[0..0] & (! w_data19220w[0..0])), w_anode19600w[3..3]); + w_anode19662w[] = ( (w_anode19662w[2..2] & w_data19220w[2..2]), (w_anode19662w[1..1] & (! w_data19220w[1..1])), (w_anode19662w[0..0] & w_data19220w[0..0]), w_anode19600w[3..3]); + w_anode19672w[] = ( (w_anode19672w[2..2] & w_data19220w[2..2]), (w_anode19672w[1..1] & w_data19220w[1..1]), (w_anode19672w[0..0] & (! w_data19220w[0..0])), w_anode19600w[3..3]); + w_anode19682w[] = ( (w_anode19682w[2..2] & w_data19220w[2..2]), (w_anode19682w[1..1] & w_data19220w[1..1]), (w_anode19682w[0..0] & w_data19220w[0..0]), w_anode19600w[3..3]); + w_anode19693w[] = ( (w_anode19693w[2..2] & w_data16911w[5..5]), (w_anode19693w[1..1] & (! w_data16911w[4..4])), (w_anode19693w[0..0] & w_data16911w[3..3]), w_anode19211w[2..2]); + w_anode19704w[] = ( (w_anode19704w[2..2] & (! w_data19220w[2..2])), (w_anode19704w[1..1] & (! w_data19220w[1..1])), (w_anode19704w[0..0] & (! w_data19220w[0..0])), w_anode19693w[3..3]); + w_anode19715w[] = ( (w_anode19715w[2..2] & (! w_data19220w[2..2])), (w_anode19715w[1..1] & (! w_data19220w[1..1])), (w_anode19715w[0..0] & w_data19220w[0..0]), w_anode19693w[3..3]); + w_anode19725w[] = ( (w_anode19725w[2..2] & (! w_data19220w[2..2])), (w_anode19725w[1..1] & w_data19220w[1..1]), (w_anode19725w[0..0] & (! w_data19220w[0..0])), w_anode19693w[3..3]); + w_anode19735w[] = ( (w_anode19735w[2..2] & (! w_data19220w[2..2])), (w_anode19735w[1..1] & w_data19220w[1..1]), (w_anode19735w[0..0] & w_data19220w[0..0]), w_anode19693w[3..3]); + w_anode19745w[] = ( (w_anode19745w[2..2] & w_data19220w[2..2]), (w_anode19745w[1..1] & (! w_data19220w[1..1])), (w_anode19745w[0..0] & (! w_data19220w[0..0])), w_anode19693w[3..3]); + w_anode19755w[] = ( (w_anode19755w[2..2] & w_data19220w[2..2]), (w_anode19755w[1..1] & (! w_data19220w[1..1])), (w_anode19755w[0..0] & w_data19220w[0..0]), w_anode19693w[3..3]); + w_anode19765w[] = ( (w_anode19765w[2..2] & w_data19220w[2..2]), (w_anode19765w[1..1] & w_data19220w[1..1]), (w_anode19765w[0..0] & (! w_data19220w[0..0])), w_anode19693w[3..3]); + w_anode19775w[] = ( (w_anode19775w[2..2] & w_data19220w[2..2]), (w_anode19775w[1..1] & w_data19220w[1..1]), (w_anode19775w[0..0] & w_data19220w[0..0]), w_anode19693w[3..3]); + w_anode19786w[] = ( (w_anode19786w[2..2] & w_data16911w[5..5]), (w_anode19786w[1..1] & w_data16911w[4..4]), (w_anode19786w[0..0] & (! w_data16911w[3..3])), w_anode19211w[2..2]); + w_anode19797w[] = ( (w_anode19797w[2..2] & (! w_data19220w[2..2])), (w_anode19797w[1..1] & (! w_data19220w[1..1])), (w_anode19797w[0..0] & (! w_data19220w[0..0])), w_anode19786w[3..3]); + w_anode19808w[] = ( (w_anode19808w[2..2] & (! w_data19220w[2..2])), (w_anode19808w[1..1] & (! w_data19220w[1..1])), (w_anode19808w[0..0] & w_data19220w[0..0]), w_anode19786w[3..3]); + w_anode19818w[] = ( (w_anode19818w[2..2] & (! w_data19220w[2..2])), (w_anode19818w[1..1] & w_data19220w[1..1]), (w_anode19818w[0..0] & (! w_data19220w[0..0])), w_anode19786w[3..3]); + w_anode19828w[] = ( (w_anode19828w[2..2] & (! w_data19220w[2..2])), (w_anode19828w[1..1] & w_data19220w[1..1]), (w_anode19828w[0..0] & w_data19220w[0..0]), w_anode19786w[3..3]); + w_anode19838w[] = ( (w_anode19838w[2..2] & w_data19220w[2..2]), (w_anode19838w[1..1] & (! w_data19220w[1..1])), (w_anode19838w[0..0] & (! w_data19220w[0..0])), w_anode19786w[3..3]); + w_anode19848w[] = ( (w_anode19848w[2..2] & w_data19220w[2..2]), (w_anode19848w[1..1] & (! w_data19220w[1..1])), (w_anode19848w[0..0] & w_data19220w[0..0]), w_anode19786w[3..3]); + w_anode19858w[] = ( (w_anode19858w[2..2] & w_data19220w[2..2]), (w_anode19858w[1..1] & w_data19220w[1..1]), (w_anode19858w[0..0] & (! w_data19220w[0..0])), w_anode19786w[3..3]); + w_anode19868w[] = ( (w_anode19868w[2..2] & w_data19220w[2..2]), (w_anode19868w[1..1] & w_data19220w[1..1]), (w_anode19868w[0..0] & w_data19220w[0..0]), w_anode19786w[3..3]); + w_anode19879w[] = ( (w_anode19879w[2..2] & w_data16911w[5..5]), (w_anode19879w[1..1] & w_data16911w[4..4]), (w_anode19879w[0..0] & w_data16911w[3..3]), w_anode19211w[2..2]); + w_anode19890w[] = ( (w_anode19890w[2..2] & (! w_data19220w[2..2])), (w_anode19890w[1..1] & (! w_data19220w[1..1])), (w_anode19890w[0..0] & (! w_data19220w[0..0])), w_anode19879w[3..3]); + w_anode19901w[] = ( (w_anode19901w[2..2] & (! w_data19220w[2..2])), (w_anode19901w[1..1] & (! w_data19220w[1..1])), (w_anode19901w[0..0] & w_data19220w[0..0]), w_anode19879w[3..3]); + w_anode19911w[] = ( (w_anode19911w[2..2] & (! w_data19220w[2..2])), (w_anode19911w[1..1] & w_data19220w[1..1]), (w_anode19911w[0..0] & (! w_data19220w[0..0])), w_anode19879w[3..3]); + w_anode19921w[] = ( (w_anode19921w[2..2] & (! w_data19220w[2..2])), (w_anode19921w[1..1] & w_data19220w[1..1]), (w_anode19921w[0..0] & w_data19220w[0..0]), w_anode19879w[3..3]); + w_anode19931w[] = ( (w_anode19931w[2..2] & w_data19220w[2..2]), (w_anode19931w[1..1] & (! w_data19220w[1..1])), (w_anode19931w[0..0] & (! w_data19220w[0..0])), w_anode19879w[3..3]); + w_anode19941w[] = ( (w_anode19941w[2..2] & w_data19220w[2..2]), (w_anode19941w[1..1] & (! w_data19220w[1..1])), (w_anode19941w[0..0] & w_data19220w[0..0]), w_anode19879w[3..3]); + w_anode19951w[] = ( (w_anode19951w[2..2] & w_data19220w[2..2]), (w_anode19951w[1..1] & w_data19220w[1..1]), (w_anode19951w[0..0] & (! w_data19220w[0..0])), w_anode19879w[3..3]); + w_anode19961w[] = ( (w_anode19961w[2..2] & w_data19220w[2..2]), (w_anode19961w[1..1] & w_data19220w[1..1]), (w_anode19961w[0..0] & w_data19220w[0..0]), w_anode19879w[3..3]); + w_data16911w[5..0] = data_wire[5..0]; + w_data16926w[2..0] = data_wire[2..0]; + w_data17696w[2..0] = data_wire[2..0]; + w_data18458w[2..0] = data_wire[2..0]; + w_data19220w[2..0] = data_wire[2..0]; +END; +--VALID FILE diff --git a/proj_quartus/db/decode_tma.tdf b/proj_quartus/db/decode_tma.tdf new file mode 100644 index 000000000..005c4a483 --- /dev/null +++ b/proj_quartus/db/decode_tma.tdf @@ -0,0 +1,80 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=16 LPM_WIDTH=4 data enable eq +--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 18 +SUBDESIGN decode_tma +( + data[3..0] : input; + enable : input; + eq[15..0] : output; +) +VARIABLE + data_wire[3..0] : WIRE; + enable_wire : WIRE; + eq_node[15..0] : WIRE; + eq_wire[15..0] : WIRE; + w_anode1073w[1..0] : WIRE; + w_anode1082w[3..0] : WIRE; + w_anode1099w[3..0] : WIRE; + w_anode1109w[3..0] : WIRE; + w_anode1119w[3..0] : WIRE; + w_anode1129w[3..0] : WIRE; + w_anode1139w[3..0] : WIRE; + w_anode1149w[3..0] : WIRE; + w_anode1159w[3..0] : WIRE; + w_anode1171w[1..0] : WIRE; + w_anode1178w[3..0] : WIRE; + w_anode1189w[3..0] : WIRE; + w_anode1199w[3..0] : WIRE; + w_anode1209w[3..0] : WIRE; + w_anode1219w[3..0] : WIRE; + w_anode1229w[3..0] : WIRE; + w_anode1239w[3..0] : WIRE; + w_anode1249w[3..0] : WIRE; + w_data1071w[2..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[15..0] = eq_wire[15..0]; + eq_wire[] = ( ( w_anode1249w[3..3], w_anode1239w[3..3], w_anode1229w[3..3], w_anode1219w[3..3], w_anode1209w[3..3], w_anode1199w[3..3], w_anode1189w[3..3], w_anode1178w[3..3]), ( w_anode1159w[3..3], w_anode1149w[3..3], w_anode1139w[3..3], w_anode1129w[3..3], w_anode1119w[3..3], w_anode1109w[3..3], w_anode1099w[3..3], w_anode1082w[3..3])); + w_anode1073w[] = ( (w_anode1073w[0..0] & (! data_wire[3..3])), enable_wire); + w_anode1082w[] = ( (w_anode1082w[2..2] & (! w_data1071w[2..2])), (w_anode1082w[1..1] & (! w_data1071w[1..1])), (w_anode1082w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); + w_anode1099w[] = ( (w_anode1099w[2..2] & (! w_data1071w[2..2])), (w_anode1099w[1..1] & (! w_data1071w[1..1])), (w_anode1099w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); + w_anode1109w[] = ( (w_anode1109w[2..2] & (! w_data1071w[2..2])), (w_anode1109w[1..1] & w_data1071w[1..1]), (w_anode1109w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); + w_anode1119w[] = ( (w_anode1119w[2..2] & (! w_data1071w[2..2])), (w_anode1119w[1..1] & w_data1071w[1..1]), (w_anode1119w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); + w_anode1129w[] = ( (w_anode1129w[2..2] & w_data1071w[2..2]), (w_anode1129w[1..1] & (! w_data1071w[1..1])), (w_anode1129w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); + w_anode1139w[] = ( (w_anode1139w[2..2] & w_data1071w[2..2]), (w_anode1139w[1..1] & (! w_data1071w[1..1])), (w_anode1139w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); + w_anode1149w[] = ( (w_anode1149w[2..2] & w_data1071w[2..2]), (w_anode1149w[1..1] & w_data1071w[1..1]), (w_anode1149w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]); + w_anode1159w[] = ( (w_anode1159w[2..2] & w_data1071w[2..2]), (w_anode1159w[1..1] & w_data1071w[1..1]), (w_anode1159w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]); + w_anode1171w[] = ( (w_anode1171w[0..0] & data_wire[3..3]), enable_wire); + w_anode1178w[] = ( (w_anode1178w[2..2] & (! w_data1071w[2..2])), (w_anode1178w[1..1] & (! w_data1071w[1..1])), (w_anode1178w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); + w_anode1189w[] = ( (w_anode1189w[2..2] & (! w_data1071w[2..2])), (w_anode1189w[1..1] & (! w_data1071w[1..1])), (w_anode1189w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); + w_anode1199w[] = ( (w_anode1199w[2..2] & (! w_data1071w[2..2])), (w_anode1199w[1..1] & w_data1071w[1..1]), (w_anode1199w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); + w_anode1209w[] = ( (w_anode1209w[2..2] & (! w_data1071w[2..2])), (w_anode1209w[1..1] & w_data1071w[1..1]), (w_anode1209w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); + w_anode1219w[] = ( (w_anode1219w[2..2] & w_data1071w[2..2]), (w_anode1219w[1..1] & (! w_data1071w[1..1])), (w_anode1219w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); + w_anode1229w[] = ( (w_anode1229w[2..2] & w_data1071w[2..2]), (w_anode1229w[1..1] & (! w_data1071w[1..1])), (w_anode1229w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); + w_anode1239w[] = ( (w_anode1239w[2..2] & w_data1071w[2..2]), (w_anode1239w[1..1] & w_data1071w[1..1]), (w_anode1239w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]); + w_anode1249w[] = ( (w_anode1249w[2..2] & w_data1071w[2..2]), (w_anode1249w[1..1] & w_data1071w[1..1]), (w_anode1249w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]); + w_data1071w[2..0] = data_wire[2..0]; +END; +--VALID FILE diff --git a/proj_quartus/db/mux_7jb.tdf b/proj_quartus/db/mux_7jb.tdf new file mode 100644 index 000000000..cf76d6886 --- /dev/null +++ b/proj_quartus/db/mux_7jb.tdf @@ -0,0 +1,4120 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=256 LPM_WIDTH=8 LPM_WIDTHS=8 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 680 +SUBDESIGN mux_7jb +( + data[2047..0] : input; + result[7..0] : output; + sel[7..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w0_n100_mux_dataout : WIRE; + l1_w0_n101_mux_dataout : WIRE; + l1_w0_n102_mux_dataout : WIRE; + l1_w0_n103_mux_dataout : WIRE; + l1_w0_n104_mux_dataout : WIRE; + l1_w0_n105_mux_dataout : WIRE; + l1_w0_n106_mux_dataout : WIRE; + l1_w0_n107_mux_dataout : WIRE; + l1_w0_n108_mux_dataout : WIRE; + l1_w0_n109_mux_dataout : WIRE; + l1_w0_n10_mux_dataout : WIRE; + l1_w0_n110_mux_dataout : WIRE; + l1_w0_n111_mux_dataout : WIRE; + l1_w0_n112_mux_dataout : WIRE; + l1_w0_n113_mux_dataout : WIRE; + l1_w0_n114_mux_dataout : WIRE; + l1_w0_n115_mux_dataout : WIRE; + l1_w0_n116_mux_dataout : WIRE; + l1_w0_n117_mux_dataout : WIRE; + l1_w0_n118_mux_dataout : WIRE; + l1_w0_n119_mux_dataout : WIRE; + l1_w0_n11_mux_dataout : WIRE; + l1_w0_n120_mux_dataout : WIRE; + l1_w0_n121_mux_dataout : WIRE; + l1_w0_n122_mux_dataout : WIRE; + l1_w0_n123_mux_dataout : WIRE; + l1_w0_n124_mux_dataout : WIRE; + l1_w0_n125_mux_dataout : WIRE; + l1_w0_n126_mux_dataout : WIRE; + l1_w0_n127_mux_dataout : WIRE; + l1_w0_n12_mux_dataout : WIRE; + l1_w0_n13_mux_dataout : WIRE; + l1_w0_n14_mux_dataout : WIRE; + l1_w0_n15_mux_dataout : WIRE; + l1_w0_n16_mux_dataout : WIRE; + l1_w0_n17_mux_dataout : WIRE; + l1_w0_n18_mux_dataout : WIRE; + l1_w0_n19_mux_dataout : WIRE; + l1_w0_n1_mux_dataout : WIRE; + l1_w0_n20_mux_dataout : WIRE; + l1_w0_n21_mux_dataout : WIRE; + l1_w0_n22_mux_dataout : WIRE; + l1_w0_n23_mux_dataout : WIRE; + l1_w0_n24_mux_dataout : WIRE; + l1_w0_n25_mux_dataout : WIRE; + l1_w0_n26_mux_dataout : WIRE; + l1_w0_n27_mux_dataout : WIRE; + l1_w0_n28_mux_dataout : WIRE; + l1_w0_n29_mux_dataout : WIRE; + l1_w0_n2_mux_dataout : WIRE; + l1_w0_n30_mux_dataout : WIRE; + l1_w0_n31_mux_dataout : WIRE; + l1_w0_n32_mux_dataout : WIRE; + l1_w0_n33_mux_dataout : WIRE; + l1_w0_n34_mux_dataout : WIRE; + l1_w0_n35_mux_dataout : WIRE; + l1_w0_n36_mux_dataout : WIRE; + l1_w0_n37_mux_dataout : WIRE; + l1_w0_n38_mux_dataout : WIRE; + l1_w0_n39_mux_dataout : WIRE; + l1_w0_n3_mux_dataout : WIRE; + l1_w0_n40_mux_dataout : WIRE; + l1_w0_n41_mux_dataout : WIRE; + l1_w0_n42_mux_dataout : WIRE; + l1_w0_n43_mux_dataout : WIRE; + l1_w0_n44_mux_dataout : WIRE; + l1_w0_n45_mux_dataout : WIRE; + l1_w0_n46_mux_dataout : WIRE; + l1_w0_n47_mux_dataout : WIRE; + l1_w0_n48_mux_dataout : WIRE; + l1_w0_n49_mux_dataout : WIRE; + l1_w0_n4_mux_dataout : WIRE; + l1_w0_n50_mux_dataout : WIRE; + l1_w0_n51_mux_dataout : WIRE; + l1_w0_n52_mux_dataout : WIRE; + l1_w0_n53_mux_dataout : WIRE; + l1_w0_n54_mux_dataout : WIRE; + l1_w0_n55_mux_dataout : WIRE; + l1_w0_n56_mux_dataout : WIRE; + l1_w0_n57_mux_dataout : WIRE; + l1_w0_n58_mux_dataout : WIRE; + l1_w0_n59_mux_dataout : WIRE; + l1_w0_n5_mux_dataout : WIRE; + l1_w0_n60_mux_dataout : WIRE; + l1_w0_n61_mux_dataout : WIRE; + l1_w0_n62_mux_dataout : WIRE; + l1_w0_n63_mux_dataout : WIRE; + l1_w0_n64_mux_dataout : WIRE; + l1_w0_n65_mux_dataout : WIRE; + l1_w0_n66_mux_dataout : WIRE; + l1_w0_n67_mux_dataout : WIRE; + l1_w0_n68_mux_dataout : WIRE; + l1_w0_n69_mux_dataout : WIRE; + l1_w0_n6_mux_dataout : WIRE; + l1_w0_n70_mux_dataout : WIRE; + l1_w0_n71_mux_dataout : WIRE; + l1_w0_n72_mux_dataout : WIRE; + l1_w0_n73_mux_dataout : WIRE; + l1_w0_n74_mux_dataout : WIRE; + l1_w0_n75_mux_dataout : WIRE; + l1_w0_n76_mux_dataout : WIRE; + l1_w0_n77_mux_dataout : WIRE; + l1_w0_n78_mux_dataout : WIRE; + l1_w0_n79_mux_dataout : WIRE; + l1_w0_n7_mux_dataout : WIRE; + l1_w0_n80_mux_dataout : WIRE; + l1_w0_n81_mux_dataout : WIRE; + l1_w0_n82_mux_dataout : WIRE; + l1_w0_n83_mux_dataout : WIRE; + l1_w0_n84_mux_dataout : WIRE; + l1_w0_n85_mux_dataout : WIRE; + l1_w0_n86_mux_dataout : WIRE; + l1_w0_n87_mux_dataout : WIRE; + l1_w0_n88_mux_dataout : WIRE; + l1_w0_n89_mux_dataout : WIRE; + l1_w0_n8_mux_dataout : WIRE; + l1_w0_n90_mux_dataout : WIRE; + l1_w0_n91_mux_dataout : WIRE; + l1_w0_n92_mux_dataout : WIRE; + l1_w0_n93_mux_dataout : WIRE; + l1_w0_n94_mux_dataout : WIRE; + l1_w0_n95_mux_dataout : WIRE; + l1_w0_n96_mux_dataout : WIRE; + l1_w0_n97_mux_dataout : WIRE; + l1_w0_n98_mux_dataout : WIRE; + l1_w0_n99_mux_dataout : WIRE; + l1_w0_n9_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w1_n100_mux_dataout : WIRE; + l1_w1_n101_mux_dataout : WIRE; + l1_w1_n102_mux_dataout : WIRE; + l1_w1_n103_mux_dataout : WIRE; + l1_w1_n104_mux_dataout : WIRE; + l1_w1_n105_mux_dataout : WIRE; + l1_w1_n106_mux_dataout : WIRE; + l1_w1_n107_mux_dataout : WIRE; + l1_w1_n108_mux_dataout : WIRE; + l1_w1_n109_mux_dataout : WIRE; + l1_w1_n10_mux_dataout : WIRE; + l1_w1_n110_mux_dataout : WIRE; + l1_w1_n111_mux_dataout : WIRE; + l1_w1_n112_mux_dataout : WIRE; + l1_w1_n113_mux_dataout : WIRE; + l1_w1_n114_mux_dataout : WIRE; + l1_w1_n115_mux_dataout : WIRE; + l1_w1_n116_mux_dataout : WIRE; + l1_w1_n117_mux_dataout : WIRE; + l1_w1_n118_mux_dataout : WIRE; + l1_w1_n119_mux_dataout : WIRE; + l1_w1_n11_mux_dataout : WIRE; + l1_w1_n120_mux_dataout : WIRE; + l1_w1_n121_mux_dataout : WIRE; + l1_w1_n122_mux_dataout : WIRE; + l1_w1_n123_mux_dataout : WIRE; + l1_w1_n124_mux_dataout : WIRE; + l1_w1_n125_mux_dataout : WIRE; + l1_w1_n126_mux_dataout : WIRE; + l1_w1_n127_mux_dataout : WIRE; + l1_w1_n12_mux_dataout : WIRE; + l1_w1_n13_mux_dataout : WIRE; + l1_w1_n14_mux_dataout : WIRE; + l1_w1_n15_mux_dataout : WIRE; + l1_w1_n16_mux_dataout : WIRE; + l1_w1_n17_mux_dataout : WIRE; + l1_w1_n18_mux_dataout : WIRE; + l1_w1_n19_mux_dataout : WIRE; + l1_w1_n1_mux_dataout : WIRE; + l1_w1_n20_mux_dataout : WIRE; + l1_w1_n21_mux_dataout : WIRE; + l1_w1_n22_mux_dataout : WIRE; + l1_w1_n23_mux_dataout : WIRE; + l1_w1_n24_mux_dataout : WIRE; + l1_w1_n25_mux_dataout : WIRE; + l1_w1_n26_mux_dataout : WIRE; + l1_w1_n27_mux_dataout : WIRE; + l1_w1_n28_mux_dataout : WIRE; + l1_w1_n29_mux_dataout : WIRE; + l1_w1_n2_mux_dataout : WIRE; + l1_w1_n30_mux_dataout : WIRE; + l1_w1_n31_mux_dataout : WIRE; + l1_w1_n32_mux_dataout : WIRE; + l1_w1_n33_mux_dataout : WIRE; + l1_w1_n34_mux_dataout : WIRE; + l1_w1_n35_mux_dataout : WIRE; + l1_w1_n36_mux_dataout : WIRE; + l1_w1_n37_mux_dataout : WIRE; + l1_w1_n38_mux_dataout : WIRE; + l1_w1_n39_mux_dataout : WIRE; + l1_w1_n3_mux_dataout : WIRE; + l1_w1_n40_mux_dataout : WIRE; + l1_w1_n41_mux_dataout : WIRE; + l1_w1_n42_mux_dataout : WIRE; + l1_w1_n43_mux_dataout : WIRE; + l1_w1_n44_mux_dataout : WIRE; + l1_w1_n45_mux_dataout : WIRE; + l1_w1_n46_mux_dataout : WIRE; + l1_w1_n47_mux_dataout : WIRE; + l1_w1_n48_mux_dataout : WIRE; + l1_w1_n49_mux_dataout : WIRE; + l1_w1_n4_mux_dataout : WIRE; + l1_w1_n50_mux_dataout : WIRE; + l1_w1_n51_mux_dataout : WIRE; + l1_w1_n52_mux_dataout : WIRE; + l1_w1_n53_mux_dataout : WIRE; + l1_w1_n54_mux_dataout : WIRE; + l1_w1_n55_mux_dataout : WIRE; + l1_w1_n56_mux_dataout : WIRE; + l1_w1_n57_mux_dataout : WIRE; + l1_w1_n58_mux_dataout : WIRE; + l1_w1_n59_mux_dataout : WIRE; + l1_w1_n5_mux_dataout : WIRE; + l1_w1_n60_mux_dataout : WIRE; + l1_w1_n61_mux_dataout : WIRE; + l1_w1_n62_mux_dataout : WIRE; + l1_w1_n63_mux_dataout : WIRE; + l1_w1_n64_mux_dataout : WIRE; + l1_w1_n65_mux_dataout : WIRE; + l1_w1_n66_mux_dataout : WIRE; + l1_w1_n67_mux_dataout : WIRE; + l1_w1_n68_mux_dataout : WIRE; + l1_w1_n69_mux_dataout : WIRE; + l1_w1_n6_mux_dataout : WIRE; + l1_w1_n70_mux_dataout : WIRE; + l1_w1_n71_mux_dataout : WIRE; + l1_w1_n72_mux_dataout : WIRE; + l1_w1_n73_mux_dataout : WIRE; + l1_w1_n74_mux_dataout : WIRE; + l1_w1_n75_mux_dataout : WIRE; + l1_w1_n76_mux_dataout : WIRE; + l1_w1_n77_mux_dataout : WIRE; + l1_w1_n78_mux_dataout : WIRE; + l1_w1_n79_mux_dataout : WIRE; + l1_w1_n7_mux_dataout : WIRE; + l1_w1_n80_mux_dataout : WIRE; + l1_w1_n81_mux_dataout : WIRE; + l1_w1_n82_mux_dataout : WIRE; + l1_w1_n83_mux_dataout : WIRE; + l1_w1_n84_mux_dataout : WIRE; + l1_w1_n85_mux_dataout : WIRE; + l1_w1_n86_mux_dataout : WIRE; + l1_w1_n87_mux_dataout : WIRE; + l1_w1_n88_mux_dataout : WIRE; + l1_w1_n89_mux_dataout : WIRE; + l1_w1_n8_mux_dataout : WIRE; + l1_w1_n90_mux_dataout : WIRE; + l1_w1_n91_mux_dataout : WIRE; + l1_w1_n92_mux_dataout : WIRE; + l1_w1_n93_mux_dataout : WIRE; + l1_w1_n94_mux_dataout : WIRE; + l1_w1_n95_mux_dataout : WIRE; + l1_w1_n96_mux_dataout : WIRE; + l1_w1_n97_mux_dataout : WIRE; + l1_w1_n98_mux_dataout : WIRE; + l1_w1_n99_mux_dataout : WIRE; + l1_w1_n9_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w2_n100_mux_dataout : WIRE; + l1_w2_n101_mux_dataout : WIRE; + l1_w2_n102_mux_dataout : WIRE; + l1_w2_n103_mux_dataout : WIRE; + l1_w2_n104_mux_dataout : WIRE; + l1_w2_n105_mux_dataout : WIRE; + l1_w2_n106_mux_dataout : WIRE; + l1_w2_n107_mux_dataout : WIRE; + l1_w2_n108_mux_dataout : WIRE; + l1_w2_n109_mux_dataout : WIRE; + l1_w2_n10_mux_dataout : WIRE; + l1_w2_n110_mux_dataout : WIRE; + l1_w2_n111_mux_dataout : WIRE; + l1_w2_n112_mux_dataout : WIRE; + l1_w2_n113_mux_dataout : WIRE; + l1_w2_n114_mux_dataout : WIRE; + l1_w2_n115_mux_dataout : WIRE; + l1_w2_n116_mux_dataout : WIRE; + l1_w2_n117_mux_dataout : WIRE; + l1_w2_n118_mux_dataout : WIRE; + l1_w2_n119_mux_dataout : WIRE; + l1_w2_n11_mux_dataout : WIRE; + l1_w2_n120_mux_dataout : WIRE; + l1_w2_n121_mux_dataout : WIRE; + l1_w2_n122_mux_dataout : WIRE; + l1_w2_n123_mux_dataout : WIRE; + l1_w2_n124_mux_dataout : WIRE; + l1_w2_n125_mux_dataout : WIRE; + l1_w2_n126_mux_dataout : WIRE; + l1_w2_n127_mux_dataout : WIRE; + l1_w2_n12_mux_dataout : WIRE; + l1_w2_n13_mux_dataout : WIRE; + l1_w2_n14_mux_dataout : WIRE; + l1_w2_n15_mux_dataout : WIRE; + l1_w2_n16_mux_dataout : WIRE; + l1_w2_n17_mux_dataout : WIRE; + l1_w2_n18_mux_dataout : WIRE; + l1_w2_n19_mux_dataout : WIRE; + l1_w2_n1_mux_dataout : WIRE; + l1_w2_n20_mux_dataout : WIRE; + l1_w2_n21_mux_dataout : WIRE; + l1_w2_n22_mux_dataout : WIRE; + l1_w2_n23_mux_dataout : WIRE; + l1_w2_n24_mux_dataout : WIRE; + l1_w2_n25_mux_dataout : WIRE; + l1_w2_n26_mux_dataout : WIRE; + l1_w2_n27_mux_dataout : WIRE; + l1_w2_n28_mux_dataout : WIRE; + l1_w2_n29_mux_dataout : WIRE; + l1_w2_n2_mux_dataout : WIRE; + l1_w2_n30_mux_dataout : WIRE; + l1_w2_n31_mux_dataout : WIRE; + l1_w2_n32_mux_dataout : WIRE; + l1_w2_n33_mux_dataout : WIRE; + l1_w2_n34_mux_dataout : WIRE; + l1_w2_n35_mux_dataout : WIRE; + l1_w2_n36_mux_dataout : WIRE; + l1_w2_n37_mux_dataout : WIRE; + l1_w2_n38_mux_dataout : WIRE; + l1_w2_n39_mux_dataout : WIRE; + l1_w2_n3_mux_dataout : WIRE; + l1_w2_n40_mux_dataout : WIRE; + l1_w2_n41_mux_dataout : WIRE; + l1_w2_n42_mux_dataout : WIRE; + l1_w2_n43_mux_dataout : WIRE; + l1_w2_n44_mux_dataout : WIRE; + l1_w2_n45_mux_dataout : WIRE; + l1_w2_n46_mux_dataout : WIRE; + l1_w2_n47_mux_dataout : WIRE; + l1_w2_n48_mux_dataout : WIRE; + l1_w2_n49_mux_dataout : WIRE; + l1_w2_n4_mux_dataout : WIRE; + l1_w2_n50_mux_dataout : WIRE; + l1_w2_n51_mux_dataout : WIRE; + l1_w2_n52_mux_dataout : WIRE; + l1_w2_n53_mux_dataout : WIRE; + l1_w2_n54_mux_dataout : WIRE; + l1_w2_n55_mux_dataout : WIRE; + l1_w2_n56_mux_dataout : WIRE; + l1_w2_n57_mux_dataout : WIRE; + l1_w2_n58_mux_dataout : WIRE; + l1_w2_n59_mux_dataout : WIRE; + l1_w2_n5_mux_dataout : WIRE; + l1_w2_n60_mux_dataout : WIRE; + l1_w2_n61_mux_dataout : WIRE; + l1_w2_n62_mux_dataout : WIRE; + l1_w2_n63_mux_dataout : WIRE; + l1_w2_n64_mux_dataout : WIRE; + l1_w2_n65_mux_dataout : WIRE; + l1_w2_n66_mux_dataout : WIRE; + l1_w2_n67_mux_dataout : WIRE; + l1_w2_n68_mux_dataout : WIRE; + l1_w2_n69_mux_dataout : WIRE; + l1_w2_n6_mux_dataout : WIRE; + l1_w2_n70_mux_dataout : WIRE; + l1_w2_n71_mux_dataout : WIRE; + l1_w2_n72_mux_dataout : WIRE; + l1_w2_n73_mux_dataout : WIRE; + l1_w2_n74_mux_dataout : WIRE; + l1_w2_n75_mux_dataout : WIRE; + l1_w2_n76_mux_dataout : WIRE; + l1_w2_n77_mux_dataout : WIRE; + l1_w2_n78_mux_dataout : WIRE; + l1_w2_n79_mux_dataout : WIRE; + l1_w2_n7_mux_dataout : WIRE; + l1_w2_n80_mux_dataout : WIRE; + l1_w2_n81_mux_dataout : WIRE; + l1_w2_n82_mux_dataout : WIRE; + l1_w2_n83_mux_dataout : WIRE; + l1_w2_n84_mux_dataout : WIRE; + l1_w2_n85_mux_dataout : WIRE; + l1_w2_n86_mux_dataout : WIRE; + l1_w2_n87_mux_dataout : WIRE; + l1_w2_n88_mux_dataout : WIRE; + l1_w2_n89_mux_dataout : WIRE; + l1_w2_n8_mux_dataout : WIRE; + l1_w2_n90_mux_dataout : WIRE; + l1_w2_n91_mux_dataout : WIRE; + l1_w2_n92_mux_dataout : WIRE; + l1_w2_n93_mux_dataout : WIRE; + l1_w2_n94_mux_dataout : WIRE; + l1_w2_n95_mux_dataout : WIRE; + l1_w2_n96_mux_dataout : WIRE; + l1_w2_n97_mux_dataout : WIRE; + l1_w2_n98_mux_dataout : WIRE; + l1_w2_n99_mux_dataout : WIRE; + l1_w2_n9_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w3_n100_mux_dataout : WIRE; + l1_w3_n101_mux_dataout : WIRE; + l1_w3_n102_mux_dataout : WIRE; + l1_w3_n103_mux_dataout : WIRE; + l1_w3_n104_mux_dataout : WIRE; + l1_w3_n105_mux_dataout : WIRE; + l1_w3_n106_mux_dataout : WIRE; + l1_w3_n107_mux_dataout : WIRE; + l1_w3_n108_mux_dataout : WIRE; + l1_w3_n109_mux_dataout : WIRE; + l1_w3_n10_mux_dataout : WIRE; + l1_w3_n110_mux_dataout : WIRE; + l1_w3_n111_mux_dataout : WIRE; + l1_w3_n112_mux_dataout : WIRE; + l1_w3_n113_mux_dataout : WIRE; + l1_w3_n114_mux_dataout : WIRE; + l1_w3_n115_mux_dataout : WIRE; + l1_w3_n116_mux_dataout : WIRE; + l1_w3_n117_mux_dataout : WIRE; + l1_w3_n118_mux_dataout : WIRE; + l1_w3_n119_mux_dataout : WIRE; + l1_w3_n11_mux_dataout : WIRE; + l1_w3_n120_mux_dataout : WIRE; + l1_w3_n121_mux_dataout : WIRE; + l1_w3_n122_mux_dataout : WIRE; + l1_w3_n123_mux_dataout : WIRE; + l1_w3_n124_mux_dataout : WIRE; + l1_w3_n125_mux_dataout : WIRE; + l1_w3_n126_mux_dataout : WIRE; + l1_w3_n127_mux_dataout : WIRE; + l1_w3_n12_mux_dataout : WIRE; + l1_w3_n13_mux_dataout : WIRE; + l1_w3_n14_mux_dataout : WIRE; + l1_w3_n15_mux_dataout : WIRE; + l1_w3_n16_mux_dataout : WIRE; + l1_w3_n17_mux_dataout : WIRE; + l1_w3_n18_mux_dataout : WIRE; + l1_w3_n19_mux_dataout : WIRE; + l1_w3_n1_mux_dataout : WIRE; + l1_w3_n20_mux_dataout : WIRE; + l1_w3_n21_mux_dataout : WIRE; + l1_w3_n22_mux_dataout : WIRE; + l1_w3_n23_mux_dataout : WIRE; + l1_w3_n24_mux_dataout : WIRE; + l1_w3_n25_mux_dataout : WIRE; + l1_w3_n26_mux_dataout : WIRE; + l1_w3_n27_mux_dataout : WIRE; + l1_w3_n28_mux_dataout : WIRE; + l1_w3_n29_mux_dataout : WIRE; + l1_w3_n2_mux_dataout : WIRE; + l1_w3_n30_mux_dataout : WIRE; + l1_w3_n31_mux_dataout : WIRE; + l1_w3_n32_mux_dataout : WIRE; + l1_w3_n33_mux_dataout : WIRE; + l1_w3_n34_mux_dataout : WIRE; + l1_w3_n35_mux_dataout : WIRE; + l1_w3_n36_mux_dataout : WIRE; + l1_w3_n37_mux_dataout : WIRE; + l1_w3_n38_mux_dataout : WIRE; + l1_w3_n39_mux_dataout : WIRE; + l1_w3_n3_mux_dataout : WIRE; + l1_w3_n40_mux_dataout : WIRE; + l1_w3_n41_mux_dataout : WIRE; + l1_w3_n42_mux_dataout : WIRE; + l1_w3_n43_mux_dataout : WIRE; + l1_w3_n44_mux_dataout : WIRE; + l1_w3_n45_mux_dataout : WIRE; + l1_w3_n46_mux_dataout : WIRE; + l1_w3_n47_mux_dataout : WIRE; + l1_w3_n48_mux_dataout : WIRE; + l1_w3_n49_mux_dataout : WIRE; + l1_w3_n4_mux_dataout : WIRE; + l1_w3_n50_mux_dataout : WIRE; + l1_w3_n51_mux_dataout : WIRE; + l1_w3_n52_mux_dataout : WIRE; + l1_w3_n53_mux_dataout : WIRE; + l1_w3_n54_mux_dataout : WIRE; + l1_w3_n55_mux_dataout : WIRE; + l1_w3_n56_mux_dataout : WIRE; + l1_w3_n57_mux_dataout : WIRE; + l1_w3_n58_mux_dataout : WIRE; + l1_w3_n59_mux_dataout : WIRE; + l1_w3_n5_mux_dataout : WIRE; + l1_w3_n60_mux_dataout : WIRE; + l1_w3_n61_mux_dataout : WIRE; + l1_w3_n62_mux_dataout : WIRE; + l1_w3_n63_mux_dataout : WIRE; + l1_w3_n64_mux_dataout : WIRE; + l1_w3_n65_mux_dataout : WIRE; + l1_w3_n66_mux_dataout : WIRE; + l1_w3_n67_mux_dataout : WIRE; + l1_w3_n68_mux_dataout : WIRE; + l1_w3_n69_mux_dataout : WIRE; + l1_w3_n6_mux_dataout : WIRE; + l1_w3_n70_mux_dataout : WIRE; + l1_w3_n71_mux_dataout : WIRE; + l1_w3_n72_mux_dataout : WIRE; + l1_w3_n73_mux_dataout : WIRE; + l1_w3_n74_mux_dataout : WIRE; + l1_w3_n75_mux_dataout : WIRE; + l1_w3_n76_mux_dataout : WIRE; + l1_w3_n77_mux_dataout : WIRE; + l1_w3_n78_mux_dataout : WIRE; + l1_w3_n79_mux_dataout : WIRE; + l1_w3_n7_mux_dataout : WIRE; + l1_w3_n80_mux_dataout : WIRE; + l1_w3_n81_mux_dataout : WIRE; + l1_w3_n82_mux_dataout : WIRE; + l1_w3_n83_mux_dataout : WIRE; + l1_w3_n84_mux_dataout : WIRE; + l1_w3_n85_mux_dataout : WIRE; + l1_w3_n86_mux_dataout : WIRE; + l1_w3_n87_mux_dataout : WIRE; + l1_w3_n88_mux_dataout : WIRE; + l1_w3_n89_mux_dataout : WIRE; + l1_w3_n8_mux_dataout : WIRE; + l1_w3_n90_mux_dataout : WIRE; + l1_w3_n91_mux_dataout : WIRE; + l1_w3_n92_mux_dataout : WIRE; + l1_w3_n93_mux_dataout : WIRE; + l1_w3_n94_mux_dataout : WIRE; + l1_w3_n95_mux_dataout : WIRE; + l1_w3_n96_mux_dataout : WIRE; + l1_w3_n97_mux_dataout : WIRE; + l1_w3_n98_mux_dataout : WIRE; + l1_w3_n99_mux_dataout : WIRE; + l1_w3_n9_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w4_n100_mux_dataout : WIRE; + l1_w4_n101_mux_dataout : WIRE; + l1_w4_n102_mux_dataout : WIRE; + l1_w4_n103_mux_dataout : WIRE; + l1_w4_n104_mux_dataout : WIRE; + l1_w4_n105_mux_dataout : WIRE; + l1_w4_n106_mux_dataout : WIRE; + l1_w4_n107_mux_dataout : WIRE; + l1_w4_n108_mux_dataout : WIRE; + l1_w4_n109_mux_dataout : WIRE; + l1_w4_n10_mux_dataout : WIRE; + l1_w4_n110_mux_dataout : WIRE; + l1_w4_n111_mux_dataout : WIRE; + l1_w4_n112_mux_dataout : WIRE; + l1_w4_n113_mux_dataout : WIRE; + l1_w4_n114_mux_dataout : WIRE; + l1_w4_n115_mux_dataout : WIRE; + l1_w4_n116_mux_dataout : WIRE; + l1_w4_n117_mux_dataout : WIRE; + l1_w4_n118_mux_dataout : WIRE; + l1_w4_n119_mux_dataout : WIRE; + l1_w4_n11_mux_dataout : WIRE; + l1_w4_n120_mux_dataout : WIRE; + l1_w4_n121_mux_dataout : WIRE; + l1_w4_n122_mux_dataout : WIRE; + l1_w4_n123_mux_dataout : WIRE; + l1_w4_n124_mux_dataout : WIRE; + l1_w4_n125_mux_dataout : WIRE; + l1_w4_n126_mux_dataout : WIRE; + l1_w4_n127_mux_dataout : WIRE; + l1_w4_n12_mux_dataout : WIRE; + l1_w4_n13_mux_dataout : WIRE; + l1_w4_n14_mux_dataout : WIRE; + l1_w4_n15_mux_dataout : WIRE; + l1_w4_n16_mux_dataout : WIRE; + l1_w4_n17_mux_dataout : WIRE; + l1_w4_n18_mux_dataout : WIRE; + l1_w4_n19_mux_dataout : WIRE; + l1_w4_n1_mux_dataout : WIRE; + l1_w4_n20_mux_dataout : WIRE; + l1_w4_n21_mux_dataout : WIRE; + l1_w4_n22_mux_dataout : WIRE; + l1_w4_n23_mux_dataout : WIRE; + l1_w4_n24_mux_dataout : WIRE; + l1_w4_n25_mux_dataout : WIRE; + l1_w4_n26_mux_dataout : WIRE; + l1_w4_n27_mux_dataout : WIRE; + l1_w4_n28_mux_dataout : WIRE; + l1_w4_n29_mux_dataout : WIRE; + l1_w4_n2_mux_dataout : WIRE; + l1_w4_n30_mux_dataout : WIRE; + l1_w4_n31_mux_dataout : WIRE; + l1_w4_n32_mux_dataout : WIRE; + l1_w4_n33_mux_dataout : WIRE; + l1_w4_n34_mux_dataout : WIRE; + l1_w4_n35_mux_dataout : WIRE; + l1_w4_n36_mux_dataout : WIRE; + l1_w4_n37_mux_dataout : WIRE; + l1_w4_n38_mux_dataout : WIRE; + l1_w4_n39_mux_dataout : WIRE; + l1_w4_n3_mux_dataout : WIRE; + l1_w4_n40_mux_dataout : WIRE; + l1_w4_n41_mux_dataout : WIRE; + l1_w4_n42_mux_dataout : WIRE; + l1_w4_n43_mux_dataout : WIRE; + l1_w4_n44_mux_dataout : WIRE; + l1_w4_n45_mux_dataout : WIRE; + l1_w4_n46_mux_dataout : WIRE; + l1_w4_n47_mux_dataout : WIRE; + l1_w4_n48_mux_dataout : WIRE; + l1_w4_n49_mux_dataout : WIRE; + l1_w4_n4_mux_dataout : WIRE; + l1_w4_n50_mux_dataout : WIRE; + l1_w4_n51_mux_dataout : WIRE; + l1_w4_n52_mux_dataout : WIRE; + l1_w4_n53_mux_dataout : WIRE; + l1_w4_n54_mux_dataout : WIRE; + l1_w4_n55_mux_dataout : WIRE; + l1_w4_n56_mux_dataout : WIRE; + l1_w4_n57_mux_dataout : WIRE; + l1_w4_n58_mux_dataout : WIRE; + l1_w4_n59_mux_dataout : WIRE; + l1_w4_n5_mux_dataout : WIRE; + l1_w4_n60_mux_dataout : WIRE; + l1_w4_n61_mux_dataout : WIRE; + l1_w4_n62_mux_dataout : WIRE; + l1_w4_n63_mux_dataout : WIRE; + l1_w4_n64_mux_dataout : WIRE; + l1_w4_n65_mux_dataout : WIRE; + l1_w4_n66_mux_dataout : WIRE; + l1_w4_n67_mux_dataout : WIRE; + l1_w4_n68_mux_dataout : WIRE; + l1_w4_n69_mux_dataout : WIRE; + l1_w4_n6_mux_dataout : WIRE; + l1_w4_n70_mux_dataout : WIRE; + l1_w4_n71_mux_dataout : WIRE; + l1_w4_n72_mux_dataout : WIRE; + l1_w4_n73_mux_dataout : WIRE; + l1_w4_n74_mux_dataout : WIRE; + l1_w4_n75_mux_dataout : WIRE; + l1_w4_n76_mux_dataout : WIRE; + l1_w4_n77_mux_dataout : WIRE; + l1_w4_n78_mux_dataout : WIRE; + l1_w4_n79_mux_dataout : WIRE; + l1_w4_n7_mux_dataout : WIRE; + l1_w4_n80_mux_dataout : WIRE; + l1_w4_n81_mux_dataout : WIRE; + l1_w4_n82_mux_dataout : WIRE; + l1_w4_n83_mux_dataout : WIRE; + l1_w4_n84_mux_dataout : WIRE; + l1_w4_n85_mux_dataout : WIRE; + l1_w4_n86_mux_dataout : WIRE; + l1_w4_n87_mux_dataout : WIRE; + l1_w4_n88_mux_dataout : WIRE; + l1_w4_n89_mux_dataout : WIRE; + l1_w4_n8_mux_dataout : WIRE; + l1_w4_n90_mux_dataout : WIRE; + l1_w4_n91_mux_dataout : WIRE; + l1_w4_n92_mux_dataout : WIRE; + l1_w4_n93_mux_dataout : WIRE; + l1_w4_n94_mux_dataout : WIRE; + l1_w4_n95_mux_dataout : WIRE; + l1_w4_n96_mux_dataout : WIRE; + l1_w4_n97_mux_dataout : WIRE; + l1_w4_n98_mux_dataout : WIRE; + l1_w4_n99_mux_dataout : WIRE; + l1_w4_n9_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w5_n100_mux_dataout : WIRE; + l1_w5_n101_mux_dataout : WIRE; + l1_w5_n102_mux_dataout : WIRE; + l1_w5_n103_mux_dataout : WIRE; + l1_w5_n104_mux_dataout : WIRE; + l1_w5_n105_mux_dataout : WIRE; + l1_w5_n106_mux_dataout : WIRE; + l1_w5_n107_mux_dataout : WIRE; + l1_w5_n108_mux_dataout : WIRE; + l1_w5_n109_mux_dataout : WIRE; + l1_w5_n10_mux_dataout : WIRE; + l1_w5_n110_mux_dataout : WIRE; + l1_w5_n111_mux_dataout : WIRE; + l1_w5_n112_mux_dataout : WIRE; + l1_w5_n113_mux_dataout : WIRE; + l1_w5_n114_mux_dataout : WIRE; + l1_w5_n115_mux_dataout : WIRE; + l1_w5_n116_mux_dataout : WIRE; + l1_w5_n117_mux_dataout : WIRE; + l1_w5_n118_mux_dataout : WIRE; + l1_w5_n119_mux_dataout : WIRE; + l1_w5_n11_mux_dataout : WIRE; + l1_w5_n120_mux_dataout : WIRE; + l1_w5_n121_mux_dataout : WIRE; + l1_w5_n122_mux_dataout : WIRE; + l1_w5_n123_mux_dataout : WIRE; + l1_w5_n124_mux_dataout : WIRE; + l1_w5_n125_mux_dataout : WIRE; + l1_w5_n126_mux_dataout : WIRE; + l1_w5_n127_mux_dataout : WIRE; + l1_w5_n12_mux_dataout : WIRE; + l1_w5_n13_mux_dataout : WIRE; + l1_w5_n14_mux_dataout : WIRE; + l1_w5_n15_mux_dataout : WIRE; + l1_w5_n16_mux_dataout : WIRE; + l1_w5_n17_mux_dataout : WIRE; + l1_w5_n18_mux_dataout : WIRE; + l1_w5_n19_mux_dataout : WIRE; + l1_w5_n1_mux_dataout : WIRE; + l1_w5_n20_mux_dataout : WIRE; + l1_w5_n21_mux_dataout : WIRE; + l1_w5_n22_mux_dataout : WIRE; + l1_w5_n23_mux_dataout : WIRE; + l1_w5_n24_mux_dataout : WIRE; + l1_w5_n25_mux_dataout : WIRE; + l1_w5_n26_mux_dataout : WIRE; + l1_w5_n27_mux_dataout : WIRE; + l1_w5_n28_mux_dataout : WIRE; + l1_w5_n29_mux_dataout : WIRE; + l1_w5_n2_mux_dataout : WIRE; + l1_w5_n30_mux_dataout : WIRE; + l1_w5_n31_mux_dataout : WIRE; + l1_w5_n32_mux_dataout : WIRE; + l1_w5_n33_mux_dataout : WIRE; + l1_w5_n34_mux_dataout : WIRE; + l1_w5_n35_mux_dataout : WIRE; + l1_w5_n36_mux_dataout : WIRE; + l1_w5_n37_mux_dataout : WIRE; + l1_w5_n38_mux_dataout : WIRE; + l1_w5_n39_mux_dataout : WIRE; + l1_w5_n3_mux_dataout : WIRE; + l1_w5_n40_mux_dataout : WIRE; + l1_w5_n41_mux_dataout : WIRE; + l1_w5_n42_mux_dataout : WIRE; + l1_w5_n43_mux_dataout : WIRE; + l1_w5_n44_mux_dataout : WIRE; + l1_w5_n45_mux_dataout : WIRE; + l1_w5_n46_mux_dataout : WIRE; + l1_w5_n47_mux_dataout : WIRE; + l1_w5_n48_mux_dataout : WIRE; + l1_w5_n49_mux_dataout : WIRE; + l1_w5_n4_mux_dataout : WIRE; + l1_w5_n50_mux_dataout : WIRE; + l1_w5_n51_mux_dataout : WIRE; + l1_w5_n52_mux_dataout : WIRE; + l1_w5_n53_mux_dataout : WIRE; + l1_w5_n54_mux_dataout : WIRE; + l1_w5_n55_mux_dataout : WIRE; + l1_w5_n56_mux_dataout : WIRE; + l1_w5_n57_mux_dataout : WIRE; + l1_w5_n58_mux_dataout : WIRE; + l1_w5_n59_mux_dataout : WIRE; + l1_w5_n5_mux_dataout : WIRE; + l1_w5_n60_mux_dataout : WIRE; + l1_w5_n61_mux_dataout : WIRE; + l1_w5_n62_mux_dataout : WIRE; + l1_w5_n63_mux_dataout : WIRE; + l1_w5_n64_mux_dataout : WIRE; + l1_w5_n65_mux_dataout : WIRE; + l1_w5_n66_mux_dataout : WIRE; + l1_w5_n67_mux_dataout : WIRE; + l1_w5_n68_mux_dataout : WIRE; + l1_w5_n69_mux_dataout : WIRE; + l1_w5_n6_mux_dataout : WIRE; + l1_w5_n70_mux_dataout : WIRE; + l1_w5_n71_mux_dataout : WIRE; + l1_w5_n72_mux_dataout : WIRE; + l1_w5_n73_mux_dataout : WIRE; + l1_w5_n74_mux_dataout : WIRE; + l1_w5_n75_mux_dataout : WIRE; + l1_w5_n76_mux_dataout : WIRE; + l1_w5_n77_mux_dataout : WIRE; + l1_w5_n78_mux_dataout : WIRE; + l1_w5_n79_mux_dataout : WIRE; + l1_w5_n7_mux_dataout : WIRE; + l1_w5_n80_mux_dataout : WIRE; + l1_w5_n81_mux_dataout : WIRE; + l1_w5_n82_mux_dataout : WIRE; + l1_w5_n83_mux_dataout : WIRE; + l1_w5_n84_mux_dataout : WIRE; + l1_w5_n85_mux_dataout : WIRE; + l1_w5_n86_mux_dataout : WIRE; + l1_w5_n87_mux_dataout : WIRE; + l1_w5_n88_mux_dataout : WIRE; + l1_w5_n89_mux_dataout : WIRE; + l1_w5_n8_mux_dataout : WIRE; + l1_w5_n90_mux_dataout : WIRE; + l1_w5_n91_mux_dataout : WIRE; + l1_w5_n92_mux_dataout : WIRE; + l1_w5_n93_mux_dataout : WIRE; + l1_w5_n94_mux_dataout : WIRE; + l1_w5_n95_mux_dataout : WIRE; + l1_w5_n96_mux_dataout : WIRE; + l1_w5_n97_mux_dataout : WIRE; + l1_w5_n98_mux_dataout : WIRE; + l1_w5_n99_mux_dataout : WIRE; + l1_w5_n9_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w6_n100_mux_dataout : WIRE; + l1_w6_n101_mux_dataout : WIRE; + l1_w6_n102_mux_dataout : WIRE; + l1_w6_n103_mux_dataout : WIRE; + l1_w6_n104_mux_dataout : WIRE; + l1_w6_n105_mux_dataout : WIRE; + l1_w6_n106_mux_dataout : WIRE; + l1_w6_n107_mux_dataout : WIRE; + l1_w6_n108_mux_dataout : WIRE; + l1_w6_n109_mux_dataout : WIRE; + l1_w6_n10_mux_dataout : WIRE; + l1_w6_n110_mux_dataout : WIRE; + l1_w6_n111_mux_dataout : WIRE; + l1_w6_n112_mux_dataout : WIRE; + l1_w6_n113_mux_dataout : WIRE; + l1_w6_n114_mux_dataout : WIRE; + l1_w6_n115_mux_dataout : WIRE; + l1_w6_n116_mux_dataout : WIRE; + l1_w6_n117_mux_dataout : WIRE; + l1_w6_n118_mux_dataout : WIRE; + l1_w6_n119_mux_dataout : WIRE; + l1_w6_n11_mux_dataout : WIRE; + l1_w6_n120_mux_dataout : WIRE; + l1_w6_n121_mux_dataout : WIRE; + l1_w6_n122_mux_dataout : WIRE; + l1_w6_n123_mux_dataout : WIRE; + l1_w6_n124_mux_dataout : WIRE; + l1_w6_n125_mux_dataout : WIRE; + l1_w6_n126_mux_dataout : WIRE; + l1_w6_n127_mux_dataout : WIRE; + l1_w6_n12_mux_dataout : WIRE; + l1_w6_n13_mux_dataout : WIRE; + l1_w6_n14_mux_dataout : WIRE; + l1_w6_n15_mux_dataout : WIRE; + l1_w6_n16_mux_dataout : WIRE; + l1_w6_n17_mux_dataout : WIRE; + l1_w6_n18_mux_dataout : WIRE; + l1_w6_n19_mux_dataout : WIRE; + l1_w6_n1_mux_dataout : WIRE; + l1_w6_n20_mux_dataout : WIRE; + l1_w6_n21_mux_dataout : WIRE; + l1_w6_n22_mux_dataout : WIRE; + l1_w6_n23_mux_dataout : WIRE; + l1_w6_n24_mux_dataout : WIRE; + l1_w6_n25_mux_dataout : WIRE; + l1_w6_n26_mux_dataout : WIRE; + l1_w6_n27_mux_dataout : WIRE; + l1_w6_n28_mux_dataout : WIRE; + l1_w6_n29_mux_dataout : WIRE; + l1_w6_n2_mux_dataout : WIRE; + l1_w6_n30_mux_dataout : WIRE; + l1_w6_n31_mux_dataout : WIRE; + l1_w6_n32_mux_dataout : WIRE; + l1_w6_n33_mux_dataout : WIRE; + l1_w6_n34_mux_dataout : WIRE; + l1_w6_n35_mux_dataout : WIRE; + l1_w6_n36_mux_dataout : WIRE; + l1_w6_n37_mux_dataout : WIRE; + l1_w6_n38_mux_dataout : WIRE; + l1_w6_n39_mux_dataout : WIRE; + l1_w6_n3_mux_dataout : WIRE; + l1_w6_n40_mux_dataout : WIRE; + l1_w6_n41_mux_dataout : WIRE; + l1_w6_n42_mux_dataout : WIRE; + l1_w6_n43_mux_dataout : WIRE; + l1_w6_n44_mux_dataout : WIRE; + l1_w6_n45_mux_dataout : WIRE; + l1_w6_n46_mux_dataout : WIRE; + l1_w6_n47_mux_dataout : WIRE; + l1_w6_n48_mux_dataout : WIRE; + l1_w6_n49_mux_dataout : WIRE; + l1_w6_n4_mux_dataout : WIRE; + l1_w6_n50_mux_dataout : WIRE; + l1_w6_n51_mux_dataout : WIRE; + l1_w6_n52_mux_dataout : WIRE; + l1_w6_n53_mux_dataout : WIRE; + l1_w6_n54_mux_dataout : WIRE; + l1_w6_n55_mux_dataout : WIRE; + l1_w6_n56_mux_dataout : WIRE; + l1_w6_n57_mux_dataout : WIRE; + l1_w6_n58_mux_dataout : WIRE; + l1_w6_n59_mux_dataout : WIRE; + l1_w6_n5_mux_dataout : WIRE; + l1_w6_n60_mux_dataout : WIRE; + l1_w6_n61_mux_dataout : WIRE; + l1_w6_n62_mux_dataout : WIRE; + l1_w6_n63_mux_dataout : WIRE; + l1_w6_n64_mux_dataout : WIRE; + l1_w6_n65_mux_dataout : WIRE; + l1_w6_n66_mux_dataout : WIRE; + l1_w6_n67_mux_dataout : WIRE; + l1_w6_n68_mux_dataout : WIRE; + l1_w6_n69_mux_dataout : WIRE; + l1_w6_n6_mux_dataout : WIRE; + l1_w6_n70_mux_dataout : WIRE; + l1_w6_n71_mux_dataout : WIRE; + l1_w6_n72_mux_dataout : WIRE; + l1_w6_n73_mux_dataout : WIRE; + l1_w6_n74_mux_dataout : WIRE; + l1_w6_n75_mux_dataout : WIRE; + l1_w6_n76_mux_dataout : WIRE; + l1_w6_n77_mux_dataout : WIRE; + l1_w6_n78_mux_dataout : WIRE; + l1_w6_n79_mux_dataout : WIRE; + l1_w6_n7_mux_dataout : WIRE; + l1_w6_n80_mux_dataout : WIRE; + l1_w6_n81_mux_dataout : WIRE; + l1_w6_n82_mux_dataout : WIRE; + l1_w6_n83_mux_dataout : WIRE; + l1_w6_n84_mux_dataout : WIRE; + l1_w6_n85_mux_dataout : WIRE; + l1_w6_n86_mux_dataout : WIRE; + l1_w6_n87_mux_dataout : WIRE; + l1_w6_n88_mux_dataout : WIRE; + l1_w6_n89_mux_dataout : WIRE; + l1_w6_n8_mux_dataout : WIRE; + l1_w6_n90_mux_dataout : WIRE; + l1_w6_n91_mux_dataout : WIRE; + l1_w6_n92_mux_dataout : WIRE; + l1_w6_n93_mux_dataout : WIRE; + l1_w6_n94_mux_dataout : WIRE; + l1_w6_n95_mux_dataout : WIRE; + l1_w6_n96_mux_dataout : WIRE; + l1_w6_n97_mux_dataout : WIRE; + l1_w6_n98_mux_dataout : WIRE; + l1_w6_n99_mux_dataout : WIRE; + l1_w6_n9_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + l1_w7_n100_mux_dataout : WIRE; + l1_w7_n101_mux_dataout : WIRE; + l1_w7_n102_mux_dataout : WIRE; + l1_w7_n103_mux_dataout : WIRE; + l1_w7_n104_mux_dataout : WIRE; + l1_w7_n105_mux_dataout : WIRE; + l1_w7_n106_mux_dataout : WIRE; + l1_w7_n107_mux_dataout : WIRE; + l1_w7_n108_mux_dataout : WIRE; + l1_w7_n109_mux_dataout : WIRE; + l1_w7_n10_mux_dataout : WIRE; + l1_w7_n110_mux_dataout : WIRE; + l1_w7_n111_mux_dataout : WIRE; + l1_w7_n112_mux_dataout : WIRE; + l1_w7_n113_mux_dataout : WIRE; + l1_w7_n114_mux_dataout : WIRE; + l1_w7_n115_mux_dataout : WIRE; + l1_w7_n116_mux_dataout : WIRE; + l1_w7_n117_mux_dataout : WIRE; + l1_w7_n118_mux_dataout : WIRE; + l1_w7_n119_mux_dataout : WIRE; + l1_w7_n11_mux_dataout : WIRE; + l1_w7_n120_mux_dataout : WIRE; + l1_w7_n121_mux_dataout : WIRE; + l1_w7_n122_mux_dataout : WIRE; + l1_w7_n123_mux_dataout : WIRE; + l1_w7_n124_mux_dataout : WIRE; + l1_w7_n125_mux_dataout : WIRE; + l1_w7_n126_mux_dataout : WIRE; + l1_w7_n127_mux_dataout : WIRE; + l1_w7_n12_mux_dataout : WIRE; + l1_w7_n13_mux_dataout : WIRE; + l1_w7_n14_mux_dataout : WIRE; + l1_w7_n15_mux_dataout : WIRE; + l1_w7_n16_mux_dataout : WIRE; + l1_w7_n17_mux_dataout : WIRE; + l1_w7_n18_mux_dataout : WIRE; + l1_w7_n19_mux_dataout : WIRE; + l1_w7_n1_mux_dataout : WIRE; + l1_w7_n20_mux_dataout : WIRE; + l1_w7_n21_mux_dataout : WIRE; + l1_w7_n22_mux_dataout : WIRE; + l1_w7_n23_mux_dataout : WIRE; + l1_w7_n24_mux_dataout : WIRE; + l1_w7_n25_mux_dataout : WIRE; + l1_w7_n26_mux_dataout : WIRE; + l1_w7_n27_mux_dataout : WIRE; + l1_w7_n28_mux_dataout : WIRE; + l1_w7_n29_mux_dataout : WIRE; + l1_w7_n2_mux_dataout : WIRE; + l1_w7_n30_mux_dataout : WIRE; + l1_w7_n31_mux_dataout : WIRE; + l1_w7_n32_mux_dataout : WIRE; + l1_w7_n33_mux_dataout : WIRE; + l1_w7_n34_mux_dataout : WIRE; + l1_w7_n35_mux_dataout : WIRE; + l1_w7_n36_mux_dataout : WIRE; + l1_w7_n37_mux_dataout : WIRE; + l1_w7_n38_mux_dataout : WIRE; + l1_w7_n39_mux_dataout : WIRE; + l1_w7_n3_mux_dataout : WIRE; + l1_w7_n40_mux_dataout : WIRE; + l1_w7_n41_mux_dataout : WIRE; + l1_w7_n42_mux_dataout : WIRE; + l1_w7_n43_mux_dataout : WIRE; + l1_w7_n44_mux_dataout : WIRE; + l1_w7_n45_mux_dataout : WIRE; + l1_w7_n46_mux_dataout : WIRE; + l1_w7_n47_mux_dataout : WIRE; + l1_w7_n48_mux_dataout : WIRE; + l1_w7_n49_mux_dataout : WIRE; + l1_w7_n4_mux_dataout : WIRE; + l1_w7_n50_mux_dataout : WIRE; + l1_w7_n51_mux_dataout : WIRE; + l1_w7_n52_mux_dataout : WIRE; + l1_w7_n53_mux_dataout : WIRE; + l1_w7_n54_mux_dataout : WIRE; + l1_w7_n55_mux_dataout : WIRE; + l1_w7_n56_mux_dataout : WIRE; + l1_w7_n57_mux_dataout : WIRE; + l1_w7_n58_mux_dataout : WIRE; + l1_w7_n59_mux_dataout : WIRE; + l1_w7_n5_mux_dataout : WIRE; + l1_w7_n60_mux_dataout : WIRE; + l1_w7_n61_mux_dataout : WIRE; + l1_w7_n62_mux_dataout : WIRE; + l1_w7_n63_mux_dataout : WIRE; + l1_w7_n64_mux_dataout : WIRE; + l1_w7_n65_mux_dataout : WIRE; + l1_w7_n66_mux_dataout : WIRE; + l1_w7_n67_mux_dataout : WIRE; + l1_w7_n68_mux_dataout : WIRE; + l1_w7_n69_mux_dataout : WIRE; + l1_w7_n6_mux_dataout : WIRE; + l1_w7_n70_mux_dataout : WIRE; + l1_w7_n71_mux_dataout : WIRE; + l1_w7_n72_mux_dataout : WIRE; + l1_w7_n73_mux_dataout : WIRE; + l1_w7_n74_mux_dataout : WIRE; + l1_w7_n75_mux_dataout : WIRE; + l1_w7_n76_mux_dataout : WIRE; + l1_w7_n77_mux_dataout : WIRE; + l1_w7_n78_mux_dataout : WIRE; + l1_w7_n79_mux_dataout : WIRE; + l1_w7_n7_mux_dataout : WIRE; + l1_w7_n80_mux_dataout : WIRE; + l1_w7_n81_mux_dataout : WIRE; + l1_w7_n82_mux_dataout : WIRE; + l1_w7_n83_mux_dataout : WIRE; + l1_w7_n84_mux_dataout : WIRE; + l1_w7_n85_mux_dataout : WIRE; + l1_w7_n86_mux_dataout : WIRE; + l1_w7_n87_mux_dataout : WIRE; + l1_w7_n88_mux_dataout : WIRE; + l1_w7_n89_mux_dataout : WIRE; + l1_w7_n8_mux_dataout : WIRE; + l1_w7_n90_mux_dataout : WIRE; + l1_w7_n91_mux_dataout : WIRE; + l1_w7_n92_mux_dataout : WIRE; + l1_w7_n93_mux_dataout : WIRE; + l1_w7_n94_mux_dataout : WIRE; + l1_w7_n95_mux_dataout : WIRE; + l1_w7_n96_mux_dataout : WIRE; + l1_w7_n97_mux_dataout : WIRE; + l1_w7_n98_mux_dataout : WIRE; + l1_w7_n99_mux_dataout : WIRE; + l1_w7_n9_mux_dataout : WIRE; + l2_w0_n0_mux_dataout : WIRE; + l2_w0_n10_mux_dataout : WIRE; + l2_w0_n11_mux_dataout : WIRE; + l2_w0_n12_mux_dataout : WIRE; + l2_w0_n13_mux_dataout : WIRE; + l2_w0_n14_mux_dataout : WIRE; + l2_w0_n15_mux_dataout : WIRE; + l2_w0_n16_mux_dataout : WIRE; + l2_w0_n17_mux_dataout : WIRE; + l2_w0_n18_mux_dataout : WIRE; + l2_w0_n19_mux_dataout : WIRE; + l2_w0_n1_mux_dataout : WIRE; + l2_w0_n20_mux_dataout : WIRE; + l2_w0_n21_mux_dataout : WIRE; + l2_w0_n22_mux_dataout : WIRE; + l2_w0_n23_mux_dataout : WIRE; + l2_w0_n24_mux_dataout : WIRE; + l2_w0_n25_mux_dataout : WIRE; + l2_w0_n26_mux_dataout : WIRE; + l2_w0_n27_mux_dataout : WIRE; + l2_w0_n28_mux_dataout : WIRE; + l2_w0_n29_mux_dataout : WIRE; + l2_w0_n2_mux_dataout : WIRE; + l2_w0_n30_mux_dataout : WIRE; + l2_w0_n31_mux_dataout : WIRE; + l2_w0_n32_mux_dataout : WIRE; + l2_w0_n33_mux_dataout : WIRE; + l2_w0_n34_mux_dataout : WIRE; + l2_w0_n35_mux_dataout : WIRE; + l2_w0_n36_mux_dataout : WIRE; + l2_w0_n37_mux_dataout : WIRE; + l2_w0_n38_mux_dataout : WIRE; + l2_w0_n39_mux_dataout : WIRE; + l2_w0_n3_mux_dataout : WIRE; + l2_w0_n40_mux_dataout : WIRE; + l2_w0_n41_mux_dataout : WIRE; + l2_w0_n42_mux_dataout : WIRE; + l2_w0_n43_mux_dataout : WIRE; + l2_w0_n44_mux_dataout : WIRE; + l2_w0_n45_mux_dataout : WIRE; + l2_w0_n46_mux_dataout : WIRE; + l2_w0_n47_mux_dataout : WIRE; + l2_w0_n48_mux_dataout : WIRE; + l2_w0_n49_mux_dataout : WIRE; + l2_w0_n4_mux_dataout : WIRE; + l2_w0_n50_mux_dataout : WIRE; + l2_w0_n51_mux_dataout : WIRE; + l2_w0_n52_mux_dataout : WIRE; + l2_w0_n53_mux_dataout : WIRE; + l2_w0_n54_mux_dataout : WIRE; + l2_w0_n55_mux_dataout : WIRE; + l2_w0_n56_mux_dataout : WIRE; + l2_w0_n57_mux_dataout : WIRE; + l2_w0_n58_mux_dataout : WIRE; + l2_w0_n59_mux_dataout : WIRE; + l2_w0_n5_mux_dataout : WIRE; + l2_w0_n60_mux_dataout : WIRE; + l2_w0_n61_mux_dataout : WIRE; + l2_w0_n62_mux_dataout : WIRE; + l2_w0_n63_mux_dataout : WIRE; + l2_w0_n6_mux_dataout : WIRE; + l2_w0_n7_mux_dataout : WIRE; + l2_w0_n8_mux_dataout : WIRE; + l2_w0_n9_mux_dataout : WIRE; + l2_w1_n0_mux_dataout : WIRE; + l2_w1_n10_mux_dataout : WIRE; + l2_w1_n11_mux_dataout : WIRE; + l2_w1_n12_mux_dataout : WIRE; + l2_w1_n13_mux_dataout : WIRE; + l2_w1_n14_mux_dataout : WIRE; + l2_w1_n15_mux_dataout : WIRE; + l2_w1_n16_mux_dataout : WIRE; + l2_w1_n17_mux_dataout : WIRE; + l2_w1_n18_mux_dataout : WIRE; + l2_w1_n19_mux_dataout : WIRE; + l2_w1_n1_mux_dataout : WIRE; + l2_w1_n20_mux_dataout : WIRE; + l2_w1_n21_mux_dataout : WIRE; + l2_w1_n22_mux_dataout : WIRE; + l2_w1_n23_mux_dataout : WIRE; + l2_w1_n24_mux_dataout : WIRE; + l2_w1_n25_mux_dataout : WIRE; + l2_w1_n26_mux_dataout : WIRE; + l2_w1_n27_mux_dataout : WIRE; + l2_w1_n28_mux_dataout : WIRE; + l2_w1_n29_mux_dataout : WIRE; + l2_w1_n2_mux_dataout : WIRE; + l2_w1_n30_mux_dataout : WIRE; + l2_w1_n31_mux_dataout : WIRE; + l2_w1_n32_mux_dataout : WIRE; + l2_w1_n33_mux_dataout : WIRE; + l2_w1_n34_mux_dataout : WIRE; + l2_w1_n35_mux_dataout : WIRE; + l2_w1_n36_mux_dataout : WIRE; + l2_w1_n37_mux_dataout : WIRE; + l2_w1_n38_mux_dataout : WIRE; + l2_w1_n39_mux_dataout : WIRE; + l2_w1_n3_mux_dataout : WIRE; + l2_w1_n40_mux_dataout : WIRE; + l2_w1_n41_mux_dataout : WIRE; + l2_w1_n42_mux_dataout : WIRE; + l2_w1_n43_mux_dataout : WIRE; + l2_w1_n44_mux_dataout : WIRE; + l2_w1_n45_mux_dataout : WIRE; + l2_w1_n46_mux_dataout : WIRE; + l2_w1_n47_mux_dataout : WIRE; + l2_w1_n48_mux_dataout : WIRE; + l2_w1_n49_mux_dataout : WIRE; + l2_w1_n4_mux_dataout : WIRE; + l2_w1_n50_mux_dataout : WIRE; + l2_w1_n51_mux_dataout : WIRE; + l2_w1_n52_mux_dataout : WIRE; + l2_w1_n53_mux_dataout : WIRE; + l2_w1_n54_mux_dataout : WIRE; + l2_w1_n55_mux_dataout : WIRE; + l2_w1_n56_mux_dataout : WIRE; + l2_w1_n57_mux_dataout : WIRE; + l2_w1_n58_mux_dataout : WIRE; + l2_w1_n59_mux_dataout : WIRE; + l2_w1_n5_mux_dataout : WIRE; + l2_w1_n60_mux_dataout : WIRE; + l2_w1_n61_mux_dataout : WIRE; + l2_w1_n62_mux_dataout : WIRE; + l2_w1_n63_mux_dataout : WIRE; + l2_w1_n6_mux_dataout : WIRE; + l2_w1_n7_mux_dataout : WIRE; + l2_w1_n8_mux_dataout : WIRE; + l2_w1_n9_mux_dataout : WIRE; + l2_w2_n0_mux_dataout : WIRE; + l2_w2_n10_mux_dataout : WIRE; + l2_w2_n11_mux_dataout : WIRE; + l2_w2_n12_mux_dataout : WIRE; + l2_w2_n13_mux_dataout : WIRE; + l2_w2_n14_mux_dataout : WIRE; + l2_w2_n15_mux_dataout : WIRE; + l2_w2_n16_mux_dataout : WIRE; + l2_w2_n17_mux_dataout : WIRE; + l2_w2_n18_mux_dataout : WIRE; + l2_w2_n19_mux_dataout : WIRE; + l2_w2_n1_mux_dataout : WIRE; + l2_w2_n20_mux_dataout : WIRE; + l2_w2_n21_mux_dataout : WIRE; + l2_w2_n22_mux_dataout : WIRE; + l2_w2_n23_mux_dataout : WIRE; + l2_w2_n24_mux_dataout : WIRE; + l2_w2_n25_mux_dataout : WIRE; + l2_w2_n26_mux_dataout : WIRE; + l2_w2_n27_mux_dataout : WIRE; + l2_w2_n28_mux_dataout : WIRE; + l2_w2_n29_mux_dataout : WIRE; + l2_w2_n2_mux_dataout : WIRE; + l2_w2_n30_mux_dataout : WIRE; + l2_w2_n31_mux_dataout : WIRE; + l2_w2_n32_mux_dataout : WIRE; + l2_w2_n33_mux_dataout : WIRE; + l2_w2_n34_mux_dataout : WIRE; + l2_w2_n35_mux_dataout : WIRE; + l2_w2_n36_mux_dataout : WIRE; + l2_w2_n37_mux_dataout : WIRE; + l2_w2_n38_mux_dataout : WIRE; + l2_w2_n39_mux_dataout : WIRE; + l2_w2_n3_mux_dataout : WIRE; + l2_w2_n40_mux_dataout : WIRE; + l2_w2_n41_mux_dataout : WIRE; + l2_w2_n42_mux_dataout : WIRE; + l2_w2_n43_mux_dataout : WIRE; + l2_w2_n44_mux_dataout : WIRE; + l2_w2_n45_mux_dataout : WIRE; + l2_w2_n46_mux_dataout : WIRE; + l2_w2_n47_mux_dataout : WIRE; + l2_w2_n48_mux_dataout : WIRE; + l2_w2_n49_mux_dataout : WIRE; + l2_w2_n4_mux_dataout : WIRE; + l2_w2_n50_mux_dataout : WIRE; + l2_w2_n51_mux_dataout : WIRE; + l2_w2_n52_mux_dataout : WIRE; + l2_w2_n53_mux_dataout : WIRE; + l2_w2_n54_mux_dataout : WIRE; + l2_w2_n55_mux_dataout : WIRE; + l2_w2_n56_mux_dataout : WIRE; + l2_w2_n57_mux_dataout : WIRE; + l2_w2_n58_mux_dataout : WIRE; + l2_w2_n59_mux_dataout : WIRE; + l2_w2_n5_mux_dataout : WIRE; + l2_w2_n60_mux_dataout : WIRE; + l2_w2_n61_mux_dataout : WIRE; + l2_w2_n62_mux_dataout : WIRE; + l2_w2_n63_mux_dataout : WIRE; + l2_w2_n6_mux_dataout : WIRE; + l2_w2_n7_mux_dataout : WIRE; + l2_w2_n8_mux_dataout : WIRE; + l2_w2_n9_mux_dataout : WIRE; + l2_w3_n0_mux_dataout : WIRE; + l2_w3_n10_mux_dataout : WIRE; + l2_w3_n11_mux_dataout : WIRE; + l2_w3_n12_mux_dataout : WIRE; + l2_w3_n13_mux_dataout : WIRE; + l2_w3_n14_mux_dataout : WIRE; + l2_w3_n15_mux_dataout : WIRE; + l2_w3_n16_mux_dataout : WIRE; + l2_w3_n17_mux_dataout : WIRE; + l2_w3_n18_mux_dataout : WIRE; + l2_w3_n19_mux_dataout : WIRE; + l2_w3_n1_mux_dataout : WIRE; + l2_w3_n20_mux_dataout : WIRE; + l2_w3_n21_mux_dataout : WIRE; + l2_w3_n22_mux_dataout : WIRE; + l2_w3_n23_mux_dataout : WIRE; + l2_w3_n24_mux_dataout : WIRE; + l2_w3_n25_mux_dataout : WIRE; + l2_w3_n26_mux_dataout : WIRE; + l2_w3_n27_mux_dataout : WIRE; + l2_w3_n28_mux_dataout : WIRE; + l2_w3_n29_mux_dataout : WIRE; + l2_w3_n2_mux_dataout : WIRE; + l2_w3_n30_mux_dataout : WIRE; + l2_w3_n31_mux_dataout : WIRE; + l2_w3_n32_mux_dataout : WIRE; + l2_w3_n33_mux_dataout : WIRE; + l2_w3_n34_mux_dataout : WIRE; + l2_w3_n35_mux_dataout : WIRE; + l2_w3_n36_mux_dataout : WIRE; + l2_w3_n37_mux_dataout : WIRE; + l2_w3_n38_mux_dataout : WIRE; + l2_w3_n39_mux_dataout : WIRE; + l2_w3_n3_mux_dataout : WIRE; + l2_w3_n40_mux_dataout : WIRE; + l2_w3_n41_mux_dataout : WIRE; + l2_w3_n42_mux_dataout : WIRE; + l2_w3_n43_mux_dataout : WIRE; + l2_w3_n44_mux_dataout : WIRE; + l2_w3_n45_mux_dataout : WIRE; + l2_w3_n46_mux_dataout : WIRE; + l2_w3_n47_mux_dataout : WIRE; + l2_w3_n48_mux_dataout : WIRE; + l2_w3_n49_mux_dataout : WIRE; + l2_w3_n4_mux_dataout : WIRE; + l2_w3_n50_mux_dataout : WIRE; + l2_w3_n51_mux_dataout : WIRE; + l2_w3_n52_mux_dataout : WIRE; + l2_w3_n53_mux_dataout : WIRE; + l2_w3_n54_mux_dataout : WIRE; + l2_w3_n55_mux_dataout : WIRE; + l2_w3_n56_mux_dataout : WIRE; + l2_w3_n57_mux_dataout : WIRE; + l2_w3_n58_mux_dataout : WIRE; + l2_w3_n59_mux_dataout : WIRE; + l2_w3_n5_mux_dataout : WIRE; + l2_w3_n60_mux_dataout : WIRE; + l2_w3_n61_mux_dataout : WIRE; + l2_w3_n62_mux_dataout : WIRE; + l2_w3_n63_mux_dataout : WIRE; + l2_w3_n6_mux_dataout : WIRE; + l2_w3_n7_mux_dataout : WIRE; + l2_w3_n8_mux_dataout : WIRE; + l2_w3_n9_mux_dataout : WIRE; + l2_w4_n0_mux_dataout : WIRE; + l2_w4_n10_mux_dataout : WIRE; + l2_w4_n11_mux_dataout : WIRE; + l2_w4_n12_mux_dataout : WIRE; + l2_w4_n13_mux_dataout : WIRE; + l2_w4_n14_mux_dataout : WIRE; + l2_w4_n15_mux_dataout : WIRE; + l2_w4_n16_mux_dataout : WIRE; + l2_w4_n17_mux_dataout : WIRE; + l2_w4_n18_mux_dataout : WIRE; + l2_w4_n19_mux_dataout : WIRE; + l2_w4_n1_mux_dataout : WIRE; + l2_w4_n20_mux_dataout : WIRE; + l2_w4_n21_mux_dataout : WIRE; + l2_w4_n22_mux_dataout : WIRE; + l2_w4_n23_mux_dataout : WIRE; + l2_w4_n24_mux_dataout : WIRE; + l2_w4_n25_mux_dataout : WIRE; + l2_w4_n26_mux_dataout : WIRE; + l2_w4_n27_mux_dataout : WIRE; + l2_w4_n28_mux_dataout : WIRE; + l2_w4_n29_mux_dataout : WIRE; + l2_w4_n2_mux_dataout : WIRE; + l2_w4_n30_mux_dataout : WIRE; + l2_w4_n31_mux_dataout : WIRE; + l2_w4_n32_mux_dataout : WIRE; + l2_w4_n33_mux_dataout : WIRE; + l2_w4_n34_mux_dataout : WIRE; + l2_w4_n35_mux_dataout : WIRE; + l2_w4_n36_mux_dataout : WIRE; + l2_w4_n37_mux_dataout : WIRE; + l2_w4_n38_mux_dataout : WIRE; + l2_w4_n39_mux_dataout : WIRE; + l2_w4_n3_mux_dataout : WIRE; + l2_w4_n40_mux_dataout : WIRE; + l2_w4_n41_mux_dataout : WIRE; + l2_w4_n42_mux_dataout : WIRE; + l2_w4_n43_mux_dataout : WIRE; + l2_w4_n44_mux_dataout : WIRE; + l2_w4_n45_mux_dataout : WIRE; + l2_w4_n46_mux_dataout : WIRE; + l2_w4_n47_mux_dataout : WIRE; + l2_w4_n48_mux_dataout : WIRE; + l2_w4_n49_mux_dataout : WIRE; + l2_w4_n4_mux_dataout : WIRE; + l2_w4_n50_mux_dataout : WIRE; + l2_w4_n51_mux_dataout : WIRE; + l2_w4_n52_mux_dataout : WIRE; + l2_w4_n53_mux_dataout : WIRE; + l2_w4_n54_mux_dataout : WIRE; + l2_w4_n55_mux_dataout : WIRE; + l2_w4_n56_mux_dataout : WIRE; + l2_w4_n57_mux_dataout : WIRE; + l2_w4_n58_mux_dataout : WIRE; + l2_w4_n59_mux_dataout : WIRE; + l2_w4_n5_mux_dataout : WIRE; + l2_w4_n60_mux_dataout : WIRE; + l2_w4_n61_mux_dataout : WIRE; + l2_w4_n62_mux_dataout : WIRE; + l2_w4_n63_mux_dataout : WIRE; + l2_w4_n6_mux_dataout : WIRE; + l2_w4_n7_mux_dataout : WIRE; + l2_w4_n8_mux_dataout : WIRE; + l2_w4_n9_mux_dataout : WIRE; + l2_w5_n0_mux_dataout : WIRE; + l2_w5_n10_mux_dataout : WIRE; + l2_w5_n11_mux_dataout : WIRE; + l2_w5_n12_mux_dataout : WIRE; + l2_w5_n13_mux_dataout : WIRE; + l2_w5_n14_mux_dataout : WIRE; + l2_w5_n15_mux_dataout : WIRE; + l2_w5_n16_mux_dataout : WIRE; + l2_w5_n17_mux_dataout : WIRE; + l2_w5_n18_mux_dataout : WIRE; + l2_w5_n19_mux_dataout : WIRE; + l2_w5_n1_mux_dataout : WIRE; + l2_w5_n20_mux_dataout : WIRE; + l2_w5_n21_mux_dataout : WIRE; + l2_w5_n22_mux_dataout : WIRE; + l2_w5_n23_mux_dataout : WIRE; + l2_w5_n24_mux_dataout : WIRE; + l2_w5_n25_mux_dataout : WIRE; + l2_w5_n26_mux_dataout : WIRE; + l2_w5_n27_mux_dataout : WIRE; + l2_w5_n28_mux_dataout : WIRE; + l2_w5_n29_mux_dataout : WIRE; + l2_w5_n2_mux_dataout : WIRE; + l2_w5_n30_mux_dataout : WIRE; + l2_w5_n31_mux_dataout : WIRE; + l2_w5_n32_mux_dataout : WIRE; + l2_w5_n33_mux_dataout : WIRE; + l2_w5_n34_mux_dataout : WIRE; + l2_w5_n35_mux_dataout : WIRE; + l2_w5_n36_mux_dataout : WIRE; + l2_w5_n37_mux_dataout : WIRE; + l2_w5_n38_mux_dataout : WIRE; + l2_w5_n39_mux_dataout : WIRE; + l2_w5_n3_mux_dataout : WIRE; + l2_w5_n40_mux_dataout : WIRE; + l2_w5_n41_mux_dataout : WIRE; + l2_w5_n42_mux_dataout : WIRE; + l2_w5_n43_mux_dataout : WIRE; + l2_w5_n44_mux_dataout : WIRE; + l2_w5_n45_mux_dataout : WIRE; + l2_w5_n46_mux_dataout : WIRE; + l2_w5_n47_mux_dataout : WIRE; + l2_w5_n48_mux_dataout : WIRE; + l2_w5_n49_mux_dataout : WIRE; + l2_w5_n4_mux_dataout : WIRE; + l2_w5_n50_mux_dataout : WIRE; + l2_w5_n51_mux_dataout : WIRE; + l2_w5_n52_mux_dataout : WIRE; + l2_w5_n53_mux_dataout : WIRE; + l2_w5_n54_mux_dataout : WIRE; + l2_w5_n55_mux_dataout : WIRE; + l2_w5_n56_mux_dataout : WIRE; + l2_w5_n57_mux_dataout : WIRE; + l2_w5_n58_mux_dataout : WIRE; + l2_w5_n59_mux_dataout : WIRE; + l2_w5_n5_mux_dataout : WIRE; + l2_w5_n60_mux_dataout : WIRE; + l2_w5_n61_mux_dataout : WIRE; + l2_w5_n62_mux_dataout : WIRE; + l2_w5_n63_mux_dataout : WIRE; + l2_w5_n6_mux_dataout : WIRE; + l2_w5_n7_mux_dataout : WIRE; + l2_w5_n8_mux_dataout : WIRE; + l2_w5_n9_mux_dataout : WIRE; + l2_w6_n0_mux_dataout : WIRE; + l2_w6_n10_mux_dataout : WIRE; + l2_w6_n11_mux_dataout : WIRE; + l2_w6_n12_mux_dataout : WIRE; + l2_w6_n13_mux_dataout : WIRE; + l2_w6_n14_mux_dataout : WIRE; + l2_w6_n15_mux_dataout : WIRE; + l2_w6_n16_mux_dataout : WIRE; + l2_w6_n17_mux_dataout : WIRE; + l2_w6_n18_mux_dataout : WIRE; + l2_w6_n19_mux_dataout : WIRE; + l2_w6_n1_mux_dataout : WIRE; + l2_w6_n20_mux_dataout : WIRE; + l2_w6_n21_mux_dataout : WIRE; + l2_w6_n22_mux_dataout : WIRE; + l2_w6_n23_mux_dataout : WIRE; + l2_w6_n24_mux_dataout : WIRE; + l2_w6_n25_mux_dataout : WIRE; + l2_w6_n26_mux_dataout : WIRE; + l2_w6_n27_mux_dataout : WIRE; + l2_w6_n28_mux_dataout : WIRE; + l2_w6_n29_mux_dataout : WIRE; + l2_w6_n2_mux_dataout : WIRE; + l2_w6_n30_mux_dataout : WIRE; + l2_w6_n31_mux_dataout : WIRE; + l2_w6_n32_mux_dataout : WIRE; + l2_w6_n33_mux_dataout : WIRE; + l2_w6_n34_mux_dataout : WIRE; + l2_w6_n35_mux_dataout : WIRE; + l2_w6_n36_mux_dataout : WIRE; + l2_w6_n37_mux_dataout : WIRE; + l2_w6_n38_mux_dataout : WIRE; + l2_w6_n39_mux_dataout : WIRE; + l2_w6_n3_mux_dataout : WIRE; + l2_w6_n40_mux_dataout : WIRE; + l2_w6_n41_mux_dataout : WIRE; + l2_w6_n42_mux_dataout : WIRE; + l2_w6_n43_mux_dataout : WIRE; + l2_w6_n44_mux_dataout : WIRE; + l2_w6_n45_mux_dataout : WIRE; + l2_w6_n46_mux_dataout : WIRE; + l2_w6_n47_mux_dataout : WIRE; + l2_w6_n48_mux_dataout : WIRE; + l2_w6_n49_mux_dataout : WIRE; + l2_w6_n4_mux_dataout : WIRE; + l2_w6_n50_mux_dataout : WIRE; + l2_w6_n51_mux_dataout : WIRE; + l2_w6_n52_mux_dataout : WIRE; + l2_w6_n53_mux_dataout : WIRE; + l2_w6_n54_mux_dataout : WIRE; + l2_w6_n55_mux_dataout : WIRE; + l2_w6_n56_mux_dataout : WIRE; + l2_w6_n57_mux_dataout : WIRE; + l2_w6_n58_mux_dataout : WIRE; + l2_w6_n59_mux_dataout : WIRE; + l2_w6_n5_mux_dataout : WIRE; + l2_w6_n60_mux_dataout : WIRE; + l2_w6_n61_mux_dataout : WIRE; + l2_w6_n62_mux_dataout : WIRE; + l2_w6_n63_mux_dataout : WIRE; + l2_w6_n6_mux_dataout : WIRE; + l2_w6_n7_mux_dataout : WIRE; + l2_w6_n8_mux_dataout : WIRE; + l2_w6_n9_mux_dataout : WIRE; + l2_w7_n0_mux_dataout : WIRE; + l2_w7_n10_mux_dataout : WIRE; + l2_w7_n11_mux_dataout : WIRE; + l2_w7_n12_mux_dataout : WIRE; + l2_w7_n13_mux_dataout : WIRE; + l2_w7_n14_mux_dataout : WIRE; + l2_w7_n15_mux_dataout : WIRE; + l2_w7_n16_mux_dataout : WIRE; + l2_w7_n17_mux_dataout : WIRE; + l2_w7_n18_mux_dataout : WIRE; + l2_w7_n19_mux_dataout : WIRE; + l2_w7_n1_mux_dataout : WIRE; + l2_w7_n20_mux_dataout : WIRE; + l2_w7_n21_mux_dataout : WIRE; + l2_w7_n22_mux_dataout : WIRE; + l2_w7_n23_mux_dataout : WIRE; + l2_w7_n24_mux_dataout : WIRE; + l2_w7_n25_mux_dataout : WIRE; + l2_w7_n26_mux_dataout : WIRE; + l2_w7_n27_mux_dataout : WIRE; + l2_w7_n28_mux_dataout : WIRE; + l2_w7_n29_mux_dataout : WIRE; + l2_w7_n2_mux_dataout : WIRE; + l2_w7_n30_mux_dataout : WIRE; + l2_w7_n31_mux_dataout : WIRE; + l2_w7_n32_mux_dataout : WIRE; + l2_w7_n33_mux_dataout : WIRE; + l2_w7_n34_mux_dataout : WIRE; + l2_w7_n35_mux_dataout : WIRE; + l2_w7_n36_mux_dataout : WIRE; + l2_w7_n37_mux_dataout : WIRE; + l2_w7_n38_mux_dataout : WIRE; + l2_w7_n39_mux_dataout : WIRE; + l2_w7_n3_mux_dataout : WIRE; + l2_w7_n40_mux_dataout : WIRE; + l2_w7_n41_mux_dataout : WIRE; + l2_w7_n42_mux_dataout : WIRE; + l2_w7_n43_mux_dataout : WIRE; + l2_w7_n44_mux_dataout : WIRE; + l2_w7_n45_mux_dataout : WIRE; + l2_w7_n46_mux_dataout : WIRE; + l2_w7_n47_mux_dataout : WIRE; + l2_w7_n48_mux_dataout : WIRE; + l2_w7_n49_mux_dataout : WIRE; + l2_w7_n4_mux_dataout : WIRE; + l2_w7_n50_mux_dataout : WIRE; + l2_w7_n51_mux_dataout : WIRE; + l2_w7_n52_mux_dataout : WIRE; + l2_w7_n53_mux_dataout : WIRE; + l2_w7_n54_mux_dataout : WIRE; + l2_w7_n55_mux_dataout : WIRE; + l2_w7_n56_mux_dataout : WIRE; + l2_w7_n57_mux_dataout : WIRE; + l2_w7_n58_mux_dataout : WIRE; + l2_w7_n59_mux_dataout : WIRE; + l2_w7_n5_mux_dataout : WIRE; + l2_w7_n60_mux_dataout : WIRE; + l2_w7_n61_mux_dataout : WIRE; + l2_w7_n62_mux_dataout : WIRE; + l2_w7_n63_mux_dataout : WIRE; + l2_w7_n6_mux_dataout : WIRE; + l2_w7_n7_mux_dataout : WIRE; + l2_w7_n8_mux_dataout : WIRE; + l2_w7_n9_mux_dataout : WIRE; + l3_w0_n0_mux_dataout : WIRE; + l3_w0_n10_mux_dataout : WIRE; + l3_w0_n11_mux_dataout : WIRE; + l3_w0_n12_mux_dataout : WIRE; + l3_w0_n13_mux_dataout : WIRE; + l3_w0_n14_mux_dataout : WIRE; + l3_w0_n15_mux_dataout : WIRE; + l3_w0_n16_mux_dataout : WIRE; + l3_w0_n17_mux_dataout : WIRE; + l3_w0_n18_mux_dataout : WIRE; + l3_w0_n19_mux_dataout : WIRE; + l3_w0_n1_mux_dataout : WIRE; + l3_w0_n20_mux_dataout : WIRE; + l3_w0_n21_mux_dataout : WIRE; + l3_w0_n22_mux_dataout : WIRE; + l3_w0_n23_mux_dataout : WIRE; + l3_w0_n24_mux_dataout : WIRE; + l3_w0_n25_mux_dataout : WIRE; + l3_w0_n26_mux_dataout : WIRE; + l3_w0_n27_mux_dataout : WIRE; + l3_w0_n28_mux_dataout : WIRE; + l3_w0_n29_mux_dataout : WIRE; + l3_w0_n2_mux_dataout : WIRE; + l3_w0_n30_mux_dataout : WIRE; + l3_w0_n31_mux_dataout : WIRE; + l3_w0_n3_mux_dataout : WIRE; + l3_w0_n4_mux_dataout : WIRE; + l3_w0_n5_mux_dataout : WIRE; + l3_w0_n6_mux_dataout : WIRE; + l3_w0_n7_mux_dataout : WIRE; + l3_w0_n8_mux_dataout : WIRE; + l3_w0_n9_mux_dataout : WIRE; + l3_w1_n0_mux_dataout : WIRE; + l3_w1_n10_mux_dataout : WIRE; + l3_w1_n11_mux_dataout : WIRE; + l3_w1_n12_mux_dataout : WIRE; + l3_w1_n13_mux_dataout : WIRE; + l3_w1_n14_mux_dataout : WIRE; + l3_w1_n15_mux_dataout : WIRE; + l3_w1_n16_mux_dataout : WIRE; + l3_w1_n17_mux_dataout : WIRE; + l3_w1_n18_mux_dataout : WIRE; + l3_w1_n19_mux_dataout : WIRE; + l3_w1_n1_mux_dataout : WIRE; + l3_w1_n20_mux_dataout : WIRE; + l3_w1_n21_mux_dataout : WIRE; + l3_w1_n22_mux_dataout : WIRE; + l3_w1_n23_mux_dataout : WIRE; + l3_w1_n24_mux_dataout : WIRE; + l3_w1_n25_mux_dataout : WIRE; + l3_w1_n26_mux_dataout : WIRE; + l3_w1_n27_mux_dataout : WIRE; + l3_w1_n28_mux_dataout : WIRE; + l3_w1_n29_mux_dataout : WIRE; + l3_w1_n2_mux_dataout : WIRE; + l3_w1_n30_mux_dataout : WIRE; + l3_w1_n31_mux_dataout : WIRE; + l3_w1_n3_mux_dataout : WIRE; + l3_w1_n4_mux_dataout : WIRE; + l3_w1_n5_mux_dataout : WIRE; + l3_w1_n6_mux_dataout : WIRE; + l3_w1_n7_mux_dataout : WIRE; + l3_w1_n8_mux_dataout : WIRE; + l3_w1_n9_mux_dataout : WIRE; + l3_w2_n0_mux_dataout : WIRE; + l3_w2_n10_mux_dataout : WIRE; + l3_w2_n11_mux_dataout : WIRE; + l3_w2_n12_mux_dataout : WIRE; + l3_w2_n13_mux_dataout : WIRE; + l3_w2_n14_mux_dataout : WIRE; + l3_w2_n15_mux_dataout : WIRE; + l3_w2_n16_mux_dataout : WIRE; + l3_w2_n17_mux_dataout : WIRE; + l3_w2_n18_mux_dataout : WIRE; + l3_w2_n19_mux_dataout : WIRE; + l3_w2_n1_mux_dataout : WIRE; + l3_w2_n20_mux_dataout : WIRE; + l3_w2_n21_mux_dataout : WIRE; + l3_w2_n22_mux_dataout : WIRE; + l3_w2_n23_mux_dataout : WIRE; + l3_w2_n24_mux_dataout : WIRE; + l3_w2_n25_mux_dataout : WIRE; + l3_w2_n26_mux_dataout : WIRE; + l3_w2_n27_mux_dataout : WIRE; + l3_w2_n28_mux_dataout : WIRE; + l3_w2_n29_mux_dataout : WIRE; + l3_w2_n2_mux_dataout : WIRE; + l3_w2_n30_mux_dataout : WIRE; + l3_w2_n31_mux_dataout : WIRE; + l3_w2_n3_mux_dataout : WIRE; + l3_w2_n4_mux_dataout : WIRE; + l3_w2_n5_mux_dataout : WIRE; + l3_w2_n6_mux_dataout : WIRE; + l3_w2_n7_mux_dataout : WIRE; + l3_w2_n8_mux_dataout : WIRE; + l3_w2_n9_mux_dataout : WIRE; + l3_w3_n0_mux_dataout : WIRE; + l3_w3_n10_mux_dataout : WIRE; + l3_w3_n11_mux_dataout : WIRE; + l3_w3_n12_mux_dataout : WIRE; + l3_w3_n13_mux_dataout : WIRE; + l3_w3_n14_mux_dataout : WIRE; + l3_w3_n15_mux_dataout : WIRE; + l3_w3_n16_mux_dataout : WIRE; + l3_w3_n17_mux_dataout : WIRE; + l3_w3_n18_mux_dataout : WIRE; + l3_w3_n19_mux_dataout : WIRE; + l3_w3_n1_mux_dataout : WIRE; + l3_w3_n20_mux_dataout : WIRE; + l3_w3_n21_mux_dataout : WIRE; + l3_w3_n22_mux_dataout : WIRE; + l3_w3_n23_mux_dataout : WIRE; + l3_w3_n24_mux_dataout : WIRE; + l3_w3_n25_mux_dataout : WIRE; + l3_w3_n26_mux_dataout : WIRE; + l3_w3_n27_mux_dataout : WIRE; + l3_w3_n28_mux_dataout : WIRE; + l3_w3_n29_mux_dataout : WIRE; + l3_w3_n2_mux_dataout : WIRE; + l3_w3_n30_mux_dataout : WIRE; + l3_w3_n31_mux_dataout : WIRE; + l3_w3_n3_mux_dataout : WIRE; + l3_w3_n4_mux_dataout : WIRE; + l3_w3_n5_mux_dataout : WIRE; + l3_w3_n6_mux_dataout : WIRE; + l3_w3_n7_mux_dataout : WIRE; + l3_w3_n8_mux_dataout : WIRE; + l3_w3_n9_mux_dataout : WIRE; + l3_w4_n0_mux_dataout : WIRE; + l3_w4_n10_mux_dataout : WIRE; + l3_w4_n11_mux_dataout : WIRE; + l3_w4_n12_mux_dataout : WIRE; + l3_w4_n13_mux_dataout : WIRE; + l3_w4_n14_mux_dataout : WIRE; + l3_w4_n15_mux_dataout : WIRE; + l3_w4_n16_mux_dataout : WIRE; + l3_w4_n17_mux_dataout : WIRE; + l3_w4_n18_mux_dataout : WIRE; + l3_w4_n19_mux_dataout : WIRE; + l3_w4_n1_mux_dataout : WIRE; + l3_w4_n20_mux_dataout : WIRE; + l3_w4_n21_mux_dataout : WIRE; + l3_w4_n22_mux_dataout : WIRE; + l3_w4_n23_mux_dataout : WIRE; + l3_w4_n24_mux_dataout : WIRE; + l3_w4_n25_mux_dataout : WIRE; + l3_w4_n26_mux_dataout : WIRE; + l3_w4_n27_mux_dataout : WIRE; + l3_w4_n28_mux_dataout : WIRE; + l3_w4_n29_mux_dataout : WIRE; + l3_w4_n2_mux_dataout : WIRE; + l3_w4_n30_mux_dataout : WIRE; + l3_w4_n31_mux_dataout : WIRE; + l3_w4_n3_mux_dataout : WIRE; + l3_w4_n4_mux_dataout : WIRE; + l3_w4_n5_mux_dataout : WIRE; + l3_w4_n6_mux_dataout : WIRE; + l3_w4_n7_mux_dataout : WIRE; + l3_w4_n8_mux_dataout : WIRE; + l3_w4_n9_mux_dataout : WIRE; + l3_w5_n0_mux_dataout : WIRE; + l3_w5_n10_mux_dataout : WIRE; + l3_w5_n11_mux_dataout : WIRE; + l3_w5_n12_mux_dataout : WIRE; + l3_w5_n13_mux_dataout : WIRE; + l3_w5_n14_mux_dataout : WIRE; + l3_w5_n15_mux_dataout : WIRE; + l3_w5_n16_mux_dataout : WIRE; + l3_w5_n17_mux_dataout : WIRE; + l3_w5_n18_mux_dataout : WIRE; + l3_w5_n19_mux_dataout : WIRE; + l3_w5_n1_mux_dataout : WIRE; + l3_w5_n20_mux_dataout : WIRE; + l3_w5_n21_mux_dataout : WIRE; + l3_w5_n22_mux_dataout : WIRE; + l3_w5_n23_mux_dataout : WIRE; + l3_w5_n24_mux_dataout : WIRE; + l3_w5_n25_mux_dataout : WIRE; + l3_w5_n26_mux_dataout : WIRE; + l3_w5_n27_mux_dataout : WIRE; + l3_w5_n28_mux_dataout : WIRE; + l3_w5_n29_mux_dataout : WIRE; + l3_w5_n2_mux_dataout : WIRE; + l3_w5_n30_mux_dataout : WIRE; + l3_w5_n31_mux_dataout : WIRE; + l3_w5_n3_mux_dataout : WIRE; + l3_w5_n4_mux_dataout : WIRE; + l3_w5_n5_mux_dataout : WIRE; + l3_w5_n6_mux_dataout : WIRE; + l3_w5_n7_mux_dataout : WIRE; + l3_w5_n8_mux_dataout : WIRE; + l3_w5_n9_mux_dataout : WIRE; + l3_w6_n0_mux_dataout : WIRE; + l3_w6_n10_mux_dataout : WIRE; + l3_w6_n11_mux_dataout : WIRE; + l3_w6_n12_mux_dataout : WIRE; + l3_w6_n13_mux_dataout : WIRE; + l3_w6_n14_mux_dataout : WIRE; + l3_w6_n15_mux_dataout : WIRE; + l3_w6_n16_mux_dataout : WIRE; + l3_w6_n17_mux_dataout : WIRE; + l3_w6_n18_mux_dataout : WIRE; + l3_w6_n19_mux_dataout : WIRE; + l3_w6_n1_mux_dataout : WIRE; + l3_w6_n20_mux_dataout : WIRE; + l3_w6_n21_mux_dataout : WIRE; + l3_w6_n22_mux_dataout : WIRE; + l3_w6_n23_mux_dataout : WIRE; + l3_w6_n24_mux_dataout : WIRE; + l3_w6_n25_mux_dataout : WIRE; + l3_w6_n26_mux_dataout : WIRE; + l3_w6_n27_mux_dataout : WIRE; + l3_w6_n28_mux_dataout : WIRE; + l3_w6_n29_mux_dataout : WIRE; + l3_w6_n2_mux_dataout : WIRE; + l3_w6_n30_mux_dataout : WIRE; + l3_w6_n31_mux_dataout : WIRE; + l3_w6_n3_mux_dataout : WIRE; + l3_w6_n4_mux_dataout : WIRE; + l3_w6_n5_mux_dataout : WIRE; + l3_w6_n6_mux_dataout : WIRE; + l3_w6_n7_mux_dataout : WIRE; + l3_w6_n8_mux_dataout : WIRE; + l3_w6_n9_mux_dataout : WIRE; + l3_w7_n0_mux_dataout : WIRE; + l3_w7_n10_mux_dataout : WIRE; + l3_w7_n11_mux_dataout : WIRE; + l3_w7_n12_mux_dataout : WIRE; + l3_w7_n13_mux_dataout : WIRE; + l3_w7_n14_mux_dataout : WIRE; + l3_w7_n15_mux_dataout : WIRE; + l3_w7_n16_mux_dataout : WIRE; + l3_w7_n17_mux_dataout : WIRE; + l3_w7_n18_mux_dataout : WIRE; + l3_w7_n19_mux_dataout : WIRE; + l3_w7_n1_mux_dataout : WIRE; + l3_w7_n20_mux_dataout : WIRE; + l3_w7_n21_mux_dataout : WIRE; + l3_w7_n22_mux_dataout : WIRE; + l3_w7_n23_mux_dataout : WIRE; + l3_w7_n24_mux_dataout : WIRE; + l3_w7_n25_mux_dataout : WIRE; + l3_w7_n26_mux_dataout : WIRE; + l3_w7_n27_mux_dataout : WIRE; + l3_w7_n28_mux_dataout : WIRE; + l3_w7_n29_mux_dataout : WIRE; + l3_w7_n2_mux_dataout : WIRE; + l3_w7_n30_mux_dataout : WIRE; + l3_w7_n31_mux_dataout : WIRE; + l3_w7_n3_mux_dataout : WIRE; + l3_w7_n4_mux_dataout : WIRE; + l3_w7_n5_mux_dataout : WIRE; + l3_w7_n6_mux_dataout : WIRE; + l3_w7_n7_mux_dataout : WIRE; + l3_w7_n8_mux_dataout : WIRE; + l3_w7_n9_mux_dataout : WIRE; + l4_w0_n0_mux_dataout : WIRE; + l4_w0_n10_mux_dataout : WIRE; + l4_w0_n11_mux_dataout : WIRE; + l4_w0_n12_mux_dataout : WIRE; + l4_w0_n13_mux_dataout : WIRE; + l4_w0_n14_mux_dataout : WIRE; + l4_w0_n15_mux_dataout : WIRE; + l4_w0_n1_mux_dataout : WIRE; + l4_w0_n2_mux_dataout : WIRE; + l4_w0_n3_mux_dataout : WIRE; + l4_w0_n4_mux_dataout : WIRE; + l4_w0_n5_mux_dataout : WIRE; + l4_w0_n6_mux_dataout : WIRE; + l4_w0_n7_mux_dataout : WIRE; + l4_w0_n8_mux_dataout : WIRE; + l4_w0_n9_mux_dataout : WIRE; + l4_w1_n0_mux_dataout : WIRE; + l4_w1_n10_mux_dataout : WIRE; + l4_w1_n11_mux_dataout : WIRE; + l4_w1_n12_mux_dataout : WIRE; + l4_w1_n13_mux_dataout : WIRE; + l4_w1_n14_mux_dataout : WIRE; + l4_w1_n15_mux_dataout : WIRE; + l4_w1_n1_mux_dataout : WIRE; + l4_w1_n2_mux_dataout : WIRE; + l4_w1_n3_mux_dataout : WIRE; + l4_w1_n4_mux_dataout : WIRE; + l4_w1_n5_mux_dataout : WIRE; + l4_w1_n6_mux_dataout : WIRE; + l4_w1_n7_mux_dataout : WIRE; + l4_w1_n8_mux_dataout : WIRE; + l4_w1_n9_mux_dataout : WIRE; + l4_w2_n0_mux_dataout : WIRE; + l4_w2_n10_mux_dataout : WIRE; + l4_w2_n11_mux_dataout : WIRE; + l4_w2_n12_mux_dataout : WIRE; + l4_w2_n13_mux_dataout : WIRE; + l4_w2_n14_mux_dataout : WIRE; + l4_w2_n15_mux_dataout : WIRE; + l4_w2_n1_mux_dataout : WIRE; + l4_w2_n2_mux_dataout : WIRE; + l4_w2_n3_mux_dataout : WIRE; + l4_w2_n4_mux_dataout : WIRE; + l4_w2_n5_mux_dataout : WIRE; + l4_w2_n6_mux_dataout : WIRE; + l4_w2_n7_mux_dataout : WIRE; + l4_w2_n8_mux_dataout : WIRE; + l4_w2_n9_mux_dataout : WIRE; + l4_w3_n0_mux_dataout : WIRE; + l4_w3_n10_mux_dataout : WIRE; + l4_w3_n11_mux_dataout : WIRE; + l4_w3_n12_mux_dataout : WIRE; + l4_w3_n13_mux_dataout : WIRE; + l4_w3_n14_mux_dataout : WIRE; + l4_w3_n15_mux_dataout : WIRE; + l4_w3_n1_mux_dataout : WIRE; + l4_w3_n2_mux_dataout : WIRE; + l4_w3_n3_mux_dataout : WIRE; + l4_w3_n4_mux_dataout : WIRE; + l4_w3_n5_mux_dataout : WIRE; + l4_w3_n6_mux_dataout : WIRE; + l4_w3_n7_mux_dataout : WIRE; + l4_w3_n8_mux_dataout : WIRE; + l4_w3_n9_mux_dataout : WIRE; + l4_w4_n0_mux_dataout : WIRE; + l4_w4_n10_mux_dataout : WIRE; + l4_w4_n11_mux_dataout : WIRE; + l4_w4_n12_mux_dataout : WIRE; + l4_w4_n13_mux_dataout : WIRE; + l4_w4_n14_mux_dataout : WIRE; + l4_w4_n15_mux_dataout : WIRE; + l4_w4_n1_mux_dataout : WIRE; + l4_w4_n2_mux_dataout : WIRE; + l4_w4_n3_mux_dataout : WIRE; + l4_w4_n4_mux_dataout : WIRE; + l4_w4_n5_mux_dataout : WIRE; + l4_w4_n6_mux_dataout : WIRE; + l4_w4_n7_mux_dataout : WIRE; + l4_w4_n8_mux_dataout : WIRE; + l4_w4_n9_mux_dataout : WIRE; + l4_w5_n0_mux_dataout : WIRE; + l4_w5_n10_mux_dataout : WIRE; + l4_w5_n11_mux_dataout : WIRE; + l4_w5_n12_mux_dataout : WIRE; + l4_w5_n13_mux_dataout : WIRE; + l4_w5_n14_mux_dataout : WIRE; + l4_w5_n15_mux_dataout : WIRE; + l4_w5_n1_mux_dataout : WIRE; + l4_w5_n2_mux_dataout : WIRE; + l4_w5_n3_mux_dataout : WIRE; + l4_w5_n4_mux_dataout : WIRE; + l4_w5_n5_mux_dataout : WIRE; + l4_w5_n6_mux_dataout : WIRE; + l4_w5_n7_mux_dataout : WIRE; + l4_w5_n8_mux_dataout : WIRE; + l4_w5_n9_mux_dataout : WIRE; + l4_w6_n0_mux_dataout : WIRE; + l4_w6_n10_mux_dataout : WIRE; + l4_w6_n11_mux_dataout : WIRE; + l4_w6_n12_mux_dataout : WIRE; + l4_w6_n13_mux_dataout : WIRE; + l4_w6_n14_mux_dataout : WIRE; + l4_w6_n15_mux_dataout : WIRE; + l4_w6_n1_mux_dataout : WIRE; + l4_w6_n2_mux_dataout : WIRE; + l4_w6_n3_mux_dataout : WIRE; + l4_w6_n4_mux_dataout : WIRE; + l4_w6_n5_mux_dataout : WIRE; + l4_w6_n6_mux_dataout : WIRE; + l4_w6_n7_mux_dataout : WIRE; + l4_w6_n8_mux_dataout : WIRE; + l4_w6_n9_mux_dataout : WIRE; + l4_w7_n0_mux_dataout : WIRE; + l4_w7_n10_mux_dataout : WIRE; + l4_w7_n11_mux_dataout : WIRE; + l4_w7_n12_mux_dataout : WIRE; + l4_w7_n13_mux_dataout : WIRE; + l4_w7_n14_mux_dataout : WIRE; + l4_w7_n15_mux_dataout : WIRE; + l4_w7_n1_mux_dataout : WIRE; + l4_w7_n2_mux_dataout : WIRE; + l4_w7_n3_mux_dataout : WIRE; + l4_w7_n4_mux_dataout : WIRE; + l4_w7_n5_mux_dataout : WIRE; + l4_w7_n6_mux_dataout : WIRE; + l4_w7_n7_mux_dataout : WIRE; + l4_w7_n8_mux_dataout : WIRE; + l4_w7_n9_mux_dataout : WIRE; + l5_w0_n0_mux_dataout : WIRE; + l5_w0_n1_mux_dataout : WIRE; + l5_w0_n2_mux_dataout : WIRE; + l5_w0_n3_mux_dataout : WIRE; + l5_w0_n4_mux_dataout : WIRE; + l5_w0_n5_mux_dataout : WIRE; + l5_w0_n6_mux_dataout : WIRE; + l5_w0_n7_mux_dataout : WIRE; + l5_w1_n0_mux_dataout : WIRE; + l5_w1_n1_mux_dataout : WIRE; + l5_w1_n2_mux_dataout : WIRE; + l5_w1_n3_mux_dataout : WIRE; + l5_w1_n4_mux_dataout : WIRE; + l5_w1_n5_mux_dataout : WIRE; + l5_w1_n6_mux_dataout : WIRE; + l5_w1_n7_mux_dataout : WIRE; + l5_w2_n0_mux_dataout : WIRE; + l5_w2_n1_mux_dataout : WIRE; + l5_w2_n2_mux_dataout : WIRE; + l5_w2_n3_mux_dataout : WIRE; + l5_w2_n4_mux_dataout : WIRE; + l5_w2_n5_mux_dataout : WIRE; + l5_w2_n6_mux_dataout : WIRE; + l5_w2_n7_mux_dataout : WIRE; + l5_w3_n0_mux_dataout : WIRE; + l5_w3_n1_mux_dataout : WIRE; + l5_w3_n2_mux_dataout : WIRE; + l5_w3_n3_mux_dataout : WIRE; + l5_w3_n4_mux_dataout : WIRE; + l5_w3_n5_mux_dataout : WIRE; + l5_w3_n6_mux_dataout : WIRE; + l5_w3_n7_mux_dataout : WIRE; + l5_w4_n0_mux_dataout : WIRE; + l5_w4_n1_mux_dataout : WIRE; + l5_w4_n2_mux_dataout : WIRE; + l5_w4_n3_mux_dataout : WIRE; + l5_w4_n4_mux_dataout : WIRE; + l5_w4_n5_mux_dataout : WIRE; + l5_w4_n6_mux_dataout : WIRE; + l5_w4_n7_mux_dataout : WIRE; + l5_w5_n0_mux_dataout : WIRE; + l5_w5_n1_mux_dataout : WIRE; + l5_w5_n2_mux_dataout : WIRE; + l5_w5_n3_mux_dataout : WIRE; + l5_w5_n4_mux_dataout : WIRE; + l5_w5_n5_mux_dataout : WIRE; + l5_w5_n6_mux_dataout : WIRE; + l5_w5_n7_mux_dataout : WIRE; + l5_w6_n0_mux_dataout : WIRE; + l5_w6_n1_mux_dataout : WIRE; + l5_w6_n2_mux_dataout : WIRE; + l5_w6_n3_mux_dataout : WIRE; + l5_w6_n4_mux_dataout : WIRE; + l5_w6_n5_mux_dataout : WIRE; + l5_w6_n6_mux_dataout : WIRE; + l5_w6_n7_mux_dataout : WIRE; + l5_w7_n0_mux_dataout : WIRE; + l5_w7_n1_mux_dataout : WIRE; + l5_w7_n2_mux_dataout : WIRE; + l5_w7_n3_mux_dataout : WIRE; + l5_w7_n4_mux_dataout : WIRE; + l5_w7_n5_mux_dataout : WIRE; + l5_w7_n6_mux_dataout : WIRE; + l5_w7_n7_mux_dataout : WIRE; + l6_w0_n0_mux_dataout : WIRE; + l6_w0_n1_mux_dataout : WIRE; + l6_w0_n2_mux_dataout : WIRE; + l6_w0_n3_mux_dataout : WIRE; + l6_w1_n0_mux_dataout : WIRE; + l6_w1_n1_mux_dataout : WIRE; + l6_w1_n2_mux_dataout : WIRE; + l6_w1_n3_mux_dataout : WIRE; + l6_w2_n0_mux_dataout : WIRE; + l6_w2_n1_mux_dataout : WIRE; + l6_w2_n2_mux_dataout : WIRE; + l6_w2_n3_mux_dataout : WIRE; + l6_w3_n0_mux_dataout : WIRE; + l6_w3_n1_mux_dataout : WIRE; + l6_w3_n2_mux_dataout : WIRE; + l6_w3_n3_mux_dataout : WIRE; + l6_w4_n0_mux_dataout : WIRE; + l6_w4_n1_mux_dataout : WIRE; + l6_w4_n2_mux_dataout : WIRE; + l6_w4_n3_mux_dataout : WIRE; + l6_w5_n0_mux_dataout : WIRE; + l6_w5_n1_mux_dataout : WIRE; + l6_w5_n2_mux_dataout : WIRE; + l6_w5_n3_mux_dataout : WIRE; + l6_w6_n0_mux_dataout : WIRE; + l6_w6_n1_mux_dataout : WIRE; + l6_w6_n2_mux_dataout : WIRE; + l6_w6_n3_mux_dataout : WIRE; + l6_w7_n0_mux_dataout : WIRE; + l6_w7_n1_mux_dataout : WIRE; + l6_w7_n2_mux_dataout : WIRE; + l6_w7_n3_mux_dataout : WIRE; + l7_w0_n0_mux_dataout : WIRE; + l7_w0_n1_mux_dataout : WIRE; + l7_w1_n0_mux_dataout : WIRE; + l7_w1_n1_mux_dataout : WIRE; + l7_w2_n0_mux_dataout : WIRE; + l7_w2_n1_mux_dataout : WIRE; + l7_w3_n0_mux_dataout : WIRE; + l7_w3_n1_mux_dataout : WIRE; + l7_w4_n0_mux_dataout : WIRE; + l7_w4_n1_mux_dataout : WIRE; + l7_w5_n0_mux_dataout : WIRE; + l7_w5_n1_mux_dataout : WIRE; + l7_w6_n0_mux_dataout : WIRE; + l7_w6_n1_mux_dataout : WIRE; + l7_w7_n0_mux_dataout : WIRE; + l7_w7_n1_mux_dataout : WIRE; + l8_w0_n0_mux_dataout : WIRE; + l8_w1_n0_mux_dataout : WIRE; + l8_w2_n0_mux_dataout : WIRE; + l8_w3_n0_mux_dataout : WIRE; + l8_w4_n0_mux_dataout : WIRE; + l8_w5_n0_mux_dataout : WIRE; + l8_w6_n0_mux_dataout : WIRE; + l8_w7_n0_mux_dataout : WIRE; + data_wire[4079..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[63..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w0_n100_mux_dataout = sel_wire[0..0] & data_wire[1608..1608] # !(sel_wire[0..0]) & data_wire[1600..1600]; + l1_w0_n101_mux_dataout = sel_wire[0..0] & data_wire[1624..1624] # !(sel_wire[0..0]) & data_wire[1616..1616]; + l1_w0_n102_mux_dataout = sel_wire[0..0] & data_wire[1640..1640] # !(sel_wire[0..0]) & data_wire[1632..1632]; + l1_w0_n103_mux_dataout = sel_wire[0..0] & data_wire[1656..1656] # !(sel_wire[0..0]) & data_wire[1648..1648]; + l1_w0_n104_mux_dataout = sel_wire[0..0] & data_wire[1672..1672] # !(sel_wire[0..0]) & data_wire[1664..1664]; + l1_w0_n105_mux_dataout = sel_wire[0..0] & data_wire[1688..1688] # !(sel_wire[0..0]) & data_wire[1680..1680]; + l1_w0_n106_mux_dataout = sel_wire[0..0] & data_wire[1704..1704] # !(sel_wire[0..0]) & data_wire[1696..1696]; + l1_w0_n107_mux_dataout = sel_wire[0..0] & data_wire[1720..1720] # !(sel_wire[0..0]) & data_wire[1712..1712]; + l1_w0_n108_mux_dataout = sel_wire[0..0] & data_wire[1736..1736] # !(sel_wire[0..0]) & data_wire[1728..1728]; + l1_w0_n109_mux_dataout = sel_wire[0..0] & data_wire[1752..1752] # !(sel_wire[0..0]) & data_wire[1744..1744]; + l1_w0_n10_mux_dataout = sel_wire[0..0] & data_wire[168..168] # !(sel_wire[0..0]) & data_wire[160..160]; + l1_w0_n110_mux_dataout = sel_wire[0..0] & data_wire[1768..1768] # !(sel_wire[0..0]) & data_wire[1760..1760]; + l1_w0_n111_mux_dataout = sel_wire[0..0] & data_wire[1784..1784] # !(sel_wire[0..0]) & data_wire[1776..1776]; + l1_w0_n112_mux_dataout = sel_wire[0..0] & data_wire[1800..1800] # !(sel_wire[0..0]) & data_wire[1792..1792]; + l1_w0_n113_mux_dataout = sel_wire[0..0] & data_wire[1816..1816] # !(sel_wire[0..0]) & data_wire[1808..1808]; + l1_w0_n114_mux_dataout = sel_wire[0..0] & data_wire[1832..1832] # !(sel_wire[0..0]) & data_wire[1824..1824]; + l1_w0_n115_mux_dataout = sel_wire[0..0] & data_wire[1848..1848] # !(sel_wire[0..0]) & data_wire[1840..1840]; + l1_w0_n116_mux_dataout = sel_wire[0..0] & data_wire[1864..1864] # !(sel_wire[0..0]) & data_wire[1856..1856]; + l1_w0_n117_mux_dataout = sel_wire[0..0] & data_wire[1880..1880] # !(sel_wire[0..0]) & data_wire[1872..1872]; + l1_w0_n118_mux_dataout = sel_wire[0..0] & data_wire[1896..1896] # !(sel_wire[0..0]) & data_wire[1888..1888]; + l1_w0_n119_mux_dataout = sel_wire[0..0] & data_wire[1912..1912] # !(sel_wire[0..0]) & data_wire[1904..1904]; + l1_w0_n11_mux_dataout = sel_wire[0..0] & data_wire[184..184] # !(sel_wire[0..0]) & data_wire[176..176]; + l1_w0_n120_mux_dataout = sel_wire[0..0] & data_wire[1928..1928] # !(sel_wire[0..0]) & data_wire[1920..1920]; + l1_w0_n121_mux_dataout = sel_wire[0..0] & data_wire[1944..1944] # !(sel_wire[0..0]) & data_wire[1936..1936]; + l1_w0_n122_mux_dataout = sel_wire[0..0] & data_wire[1960..1960] # !(sel_wire[0..0]) & data_wire[1952..1952]; + l1_w0_n123_mux_dataout = sel_wire[0..0] & data_wire[1976..1976] # !(sel_wire[0..0]) & data_wire[1968..1968]; + l1_w0_n124_mux_dataout = sel_wire[0..0] & data_wire[1992..1992] # !(sel_wire[0..0]) & data_wire[1984..1984]; + l1_w0_n125_mux_dataout = sel_wire[0..0] & data_wire[2008..2008] # !(sel_wire[0..0]) & data_wire[2000..2000]; + l1_w0_n126_mux_dataout = sel_wire[0..0] & data_wire[2024..2024] # !(sel_wire[0..0]) & data_wire[2016..2016]; + l1_w0_n127_mux_dataout = sel_wire[0..0] & data_wire[2040..2040] # !(sel_wire[0..0]) & data_wire[2032..2032]; + l1_w0_n12_mux_dataout = sel_wire[0..0] & data_wire[200..200] # !(sel_wire[0..0]) & data_wire[192..192]; + l1_w0_n13_mux_dataout = sel_wire[0..0] & data_wire[216..216] # !(sel_wire[0..0]) & data_wire[208..208]; + l1_w0_n14_mux_dataout = sel_wire[0..0] & data_wire[232..232] # !(sel_wire[0..0]) & data_wire[224..224]; + l1_w0_n15_mux_dataout = sel_wire[0..0] & data_wire[248..248] # !(sel_wire[0..0]) & data_wire[240..240]; + l1_w0_n16_mux_dataout = sel_wire[0..0] & data_wire[264..264] # !(sel_wire[0..0]) & data_wire[256..256]; + l1_w0_n17_mux_dataout = sel_wire[0..0] & data_wire[280..280] # !(sel_wire[0..0]) & data_wire[272..272]; + l1_w0_n18_mux_dataout = sel_wire[0..0] & data_wire[296..296] # !(sel_wire[0..0]) & data_wire[288..288]; + l1_w0_n19_mux_dataout = sel_wire[0..0] & data_wire[312..312] # !(sel_wire[0..0]) & data_wire[304..304]; + l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16]; + l1_w0_n20_mux_dataout = sel_wire[0..0] & data_wire[328..328] # !(sel_wire[0..0]) & data_wire[320..320]; + l1_w0_n21_mux_dataout = sel_wire[0..0] & data_wire[344..344] # !(sel_wire[0..0]) & data_wire[336..336]; + l1_w0_n22_mux_dataout = sel_wire[0..0] & data_wire[360..360] # !(sel_wire[0..0]) & data_wire[352..352]; + l1_w0_n23_mux_dataout = sel_wire[0..0] & data_wire[376..376] # !(sel_wire[0..0]) & data_wire[368..368]; + l1_w0_n24_mux_dataout = sel_wire[0..0] & data_wire[392..392] # !(sel_wire[0..0]) & data_wire[384..384]; + l1_w0_n25_mux_dataout = sel_wire[0..0] & data_wire[408..408] # !(sel_wire[0..0]) & data_wire[400..400]; + l1_w0_n26_mux_dataout = sel_wire[0..0] & data_wire[424..424] # !(sel_wire[0..0]) & data_wire[416..416]; + l1_w0_n27_mux_dataout = sel_wire[0..0] & data_wire[440..440] # !(sel_wire[0..0]) & data_wire[432..432]; + l1_w0_n28_mux_dataout = sel_wire[0..0] & data_wire[456..456] # !(sel_wire[0..0]) & data_wire[448..448]; + l1_w0_n29_mux_dataout = sel_wire[0..0] & data_wire[472..472] # !(sel_wire[0..0]) & data_wire[464..464]; + l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32]; + l1_w0_n30_mux_dataout = sel_wire[0..0] & data_wire[488..488] # !(sel_wire[0..0]) & data_wire[480..480]; + l1_w0_n31_mux_dataout = sel_wire[0..0] & data_wire[504..504] # !(sel_wire[0..0]) & data_wire[496..496]; + l1_w0_n32_mux_dataout = sel_wire[0..0] & data_wire[520..520] # !(sel_wire[0..0]) & data_wire[512..512]; + l1_w0_n33_mux_dataout = sel_wire[0..0] & data_wire[536..536] # !(sel_wire[0..0]) & data_wire[528..528]; + l1_w0_n34_mux_dataout = sel_wire[0..0] & data_wire[552..552] # !(sel_wire[0..0]) & data_wire[544..544]; + l1_w0_n35_mux_dataout = sel_wire[0..0] & data_wire[568..568] # !(sel_wire[0..0]) & data_wire[560..560]; + l1_w0_n36_mux_dataout = sel_wire[0..0] & data_wire[584..584] # !(sel_wire[0..0]) & data_wire[576..576]; + l1_w0_n37_mux_dataout = sel_wire[0..0] & data_wire[600..600] # !(sel_wire[0..0]) & data_wire[592..592]; + l1_w0_n38_mux_dataout = sel_wire[0..0] & data_wire[616..616] # !(sel_wire[0..0]) & data_wire[608..608]; + l1_w0_n39_mux_dataout = sel_wire[0..0] & data_wire[632..632] # !(sel_wire[0..0]) & data_wire[624..624]; + l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48]; + l1_w0_n40_mux_dataout = sel_wire[0..0] & data_wire[648..648] # !(sel_wire[0..0]) & data_wire[640..640]; + l1_w0_n41_mux_dataout = sel_wire[0..0] & data_wire[664..664] # !(sel_wire[0..0]) & data_wire[656..656]; + l1_w0_n42_mux_dataout = sel_wire[0..0] & data_wire[680..680] # !(sel_wire[0..0]) & data_wire[672..672]; + l1_w0_n43_mux_dataout = sel_wire[0..0] & data_wire[696..696] # !(sel_wire[0..0]) & data_wire[688..688]; + l1_w0_n44_mux_dataout = sel_wire[0..0] & data_wire[712..712] # !(sel_wire[0..0]) & data_wire[704..704]; + l1_w0_n45_mux_dataout = sel_wire[0..0] & data_wire[728..728] # !(sel_wire[0..0]) & data_wire[720..720]; + l1_w0_n46_mux_dataout = sel_wire[0..0] & data_wire[744..744] # !(sel_wire[0..0]) & data_wire[736..736]; + l1_w0_n47_mux_dataout = sel_wire[0..0] & data_wire[760..760] # !(sel_wire[0..0]) & data_wire[752..752]; + l1_w0_n48_mux_dataout = sel_wire[0..0] & data_wire[776..776] # !(sel_wire[0..0]) & data_wire[768..768]; + l1_w0_n49_mux_dataout = sel_wire[0..0] & data_wire[792..792] # !(sel_wire[0..0]) & data_wire[784..784]; + l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[72..72] # !(sel_wire[0..0]) & data_wire[64..64]; + l1_w0_n50_mux_dataout = sel_wire[0..0] & data_wire[808..808] # !(sel_wire[0..0]) & data_wire[800..800]; + l1_w0_n51_mux_dataout = sel_wire[0..0] & data_wire[824..824] # !(sel_wire[0..0]) & data_wire[816..816]; + l1_w0_n52_mux_dataout = sel_wire[0..0] & data_wire[840..840] # !(sel_wire[0..0]) & data_wire[832..832]; + l1_w0_n53_mux_dataout = sel_wire[0..0] & data_wire[856..856] # !(sel_wire[0..0]) & data_wire[848..848]; + l1_w0_n54_mux_dataout = sel_wire[0..0] & data_wire[872..872] # !(sel_wire[0..0]) & data_wire[864..864]; + l1_w0_n55_mux_dataout = sel_wire[0..0] & data_wire[888..888] # !(sel_wire[0..0]) & data_wire[880..880]; + l1_w0_n56_mux_dataout = sel_wire[0..0] & data_wire[904..904] # !(sel_wire[0..0]) & data_wire[896..896]; + l1_w0_n57_mux_dataout = sel_wire[0..0] & data_wire[920..920] # !(sel_wire[0..0]) & data_wire[912..912]; + l1_w0_n58_mux_dataout = sel_wire[0..0] & data_wire[936..936] # !(sel_wire[0..0]) & data_wire[928..928]; + l1_w0_n59_mux_dataout = sel_wire[0..0] & data_wire[952..952] # !(sel_wire[0..0]) & data_wire[944..944]; + l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[88..88] # !(sel_wire[0..0]) & data_wire[80..80]; + l1_w0_n60_mux_dataout = sel_wire[0..0] & data_wire[968..968] # !(sel_wire[0..0]) & data_wire[960..960]; + l1_w0_n61_mux_dataout = sel_wire[0..0] & data_wire[984..984] # !(sel_wire[0..0]) & data_wire[976..976]; + l1_w0_n62_mux_dataout = sel_wire[0..0] & data_wire[1000..1000] # !(sel_wire[0..0]) & data_wire[992..992]; + l1_w0_n63_mux_dataout = sel_wire[0..0] & data_wire[1016..1016] # !(sel_wire[0..0]) & data_wire[1008..1008]; + l1_w0_n64_mux_dataout = sel_wire[0..0] & data_wire[1032..1032] # !(sel_wire[0..0]) & data_wire[1024..1024]; + l1_w0_n65_mux_dataout = sel_wire[0..0] & data_wire[1048..1048] # !(sel_wire[0..0]) & data_wire[1040..1040]; + l1_w0_n66_mux_dataout = sel_wire[0..0] & data_wire[1064..1064] # !(sel_wire[0..0]) & data_wire[1056..1056]; + l1_w0_n67_mux_dataout = sel_wire[0..0] & data_wire[1080..1080] # !(sel_wire[0..0]) & data_wire[1072..1072]; + l1_w0_n68_mux_dataout = sel_wire[0..0] & data_wire[1096..1096] # !(sel_wire[0..0]) & data_wire[1088..1088]; + l1_w0_n69_mux_dataout = sel_wire[0..0] & data_wire[1112..1112] # !(sel_wire[0..0]) & data_wire[1104..1104]; + l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[104..104] # !(sel_wire[0..0]) & data_wire[96..96]; + l1_w0_n70_mux_dataout = sel_wire[0..0] & data_wire[1128..1128] # !(sel_wire[0..0]) & data_wire[1120..1120]; + l1_w0_n71_mux_dataout = sel_wire[0..0] & data_wire[1144..1144] # !(sel_wire[0..0]) & data_wire[1136..1136]; + l1_w0_n72_mux_dataout = sel_wire[0..0] & data_wire[1160..1160] # !(sel_wire[0..0]) & data_wire[1152..1152]; + l1_w0_n73_mux_dataout = sel_wire[0..0] & data_wire[1176..1176] # !(sel_wire[0..0]) & data_wire[1168..1168]; + l1_w0_n74_mux_dataout = sel_wire[0..0] & data_wire[1192..1192] # !(sel_wire[0..0]) & data_wire[1184..1184]; + l1_w0_n75_mux_dataout = sel_wire[0..0] & data_wire[1208..1208] # !(sel_wire[0..0]) & data_wire[1200..1200]; + l1_w0_n76_mux_dataout = sel_wire[0..0] & data_wire[1224..1224] # !(sel_wire[0..0]) & data_wire[1216..1216]; + l1_w0_n77_mux_dataout = sel_wire[0..0] & data_wire[1240..1240] # !(sel_wire[0..0]) & data_wire[1232..1232]; + l1_w0_n78_mux_dataout = sel_wire[0..0] & data_wire[1256..1256] # !(sel_wire[0..0]) & data_wire[1248..1248]; + l1_w0_n79_mux_dataout = sel_wire[0..0] & data_wire[1272..1272] # !(sel_wire[0..0]) & data_wire[1264..1264]; + l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[120..120] # !(sel_wire[0..0]) & data_wire[112..112]; + l1_w0_n80_mux_dataout = sel_wire[0..0] & data_wire[1288..1288] # !(sel_wire[0..0]) & data_wire[1280..1280]; + l1_w0_n81_mux_dataout = sel_wire[0..0] & data_wire[1304..1304] # !(sel_wire[0..0]) & data_wire[1296..1296]; + l1_w0_n82_mux_dataout = sel_wire[0..0] & data_wire[1320..1320] # !(sel_wire[0..0]) & data_wire[1312..1312]; + l1_w0_n83_mux_dataout = sel_wire[0..0] & data_wire[1336..1336] # !(sel_wire[0..0]) & data_wire[1328..1328]; + l1_w0_n84_mux_dataout = sel_wire[0..0] & data_wire[1352..1352] # !(sel_wire[0..0]) & data_wire[1344..1344]; + l1_w0_n85_mux_dataout = sel_wire[0..0] & data_wire[1368..1368] # !(sel_wire[0..0]) & data_wire[1360..1360]; + l1_w0_n86_mux_dataout = sel_wire[0..0] & data_wire[1384..1384] # !(sel_wire[0..0]) & data_wire[1376..1376]; + l1_w0_n87_mux_dataout = sel_wire[0..0] & data_wire[1400..1400] # !(sel_wire[0..0]) & data_wire[1392..1392]; + l1_w0_n88_mux_dataout = sel_wire[0..0] & data_wire[1416..1416] # !(sel_wire[0..0]) & data_wire[1408..1408]; + l1_w0_n89_mux_dataout = sel_wire[0..0] & data_wire[1432..1432] # !(sel_wire[0..0]) & data_wire[1424..1424]; + l1_w0_n8_mux_dataout = sel_wire[0..0] & data_wire[136..136] # !(sel_wire[0..0]) & data_wire[128..128]; + l1_w0_n90_mux_dataout = sel_wire[0..0] & data_wire[1448..1448] # !(sel_wire[0..0]) & data_wire[1440..1440]; + l1_w0_n91_mux_dataout = sel_wire[0..0] & data_wire[1464..1464] # !(sel_wire[0..0]) & data_wire[1456..1456]; + l1_w0_n92_mux_dataout = sel_wire[0..0] & data_wire[1480..1480] # !(sel_wire[0..0]) & data_wire[1472..1472]; + l1_w0_n93_mux_dataout = sel_wire[0..0] & data_wire[1496..1496] # !(sel_wire[0..0]) & data_wire[1488..1488]; + l1_w0_n94_mux_dataout = sel_wire[0..0] & data_wire[1512..1512] # !(sel_wire[0..0]) & data_wire[1504..1504]; + l1_w0_n95_mux_dataout = sel_wire[0..0] & data_wire[1528..1528] # !(sel_wire[0..0]) & data_wire[1520..1520]; + l1_w0_n96_mux_dataout = sel_wire[0..0] & data_wire[1544..1544] # !(sel_wire[0..0]) & data_wire[1536..1536]; + l1_w0_n97_mux_dataout = sel_wire[0..0] & data_wire[1560..1560] # !(sel_wire[0..0]) & data_wire[1552..1552]; + l1_w0_n98_mux_dataout = sel_wire[0..0] & data_wire[1576..1576] # !(sel_wire[0..0]) & data_wire[1568..1568]; + l1_w0_n99_mux_dataout = sel_wire[0..0] & data_wire[1592..1592] # !(sel_wire[0..0]) & data_wire[1584..1584]; + l1_w0_n9_mux_dataout = sel_wire[0..0] & data_wire[152..152] # !(sel_wire[0..0]) & data_wire[144..144]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w1_n100_mux_dataout = sel_wire[0..0] & data_wire[1609..1609] # !(sel_wire[0..0]) & data_wire[1601..1601]; + l1_w1_n101_mux_dataout = sel_wire[0..0] & data_wire[1625..1625] # !(sel_wire[0..0]) & data_wire[1617..1617]; + l1_w1_n102_mux_dataout = sel_wire[0..0] & data_wire[1641..1641] # !(sel_wire[0..0]) & data_wire[1633..1633]; + l1_w1_n103_mux_dataout = sel_wire[0..0] & data_wire[1657..1657] # !(sel_wire[0..0]) & data_wire[1649..1649]; + l1_w1_n104_mux_dataout = sel_wire[0..0] & data_wire[1673..1673] # !(sel_wire[0..0]) & data_wire[1665..1665]; + l1_w1_n105_mux_dataout = sel_wire[0..0] & data_wire[1689..1689] # !(sel_wire[0..0]) & data_wire[1681..1681]; + l1_w1_n106_mux_dataout = sel_wire[0..0] & data_wire[1705..1705] # !(sel_wire[0..0]) & data_wire[1697..1697]; + l1_w1_n107_mux_dataout = sel_wire[0..0] & data_wire[1721..1721] # !(sel_wire[0..0]) & data_wire[1713..1713]; + l1_w1_n108_mux_dataout = sel_wire[0..0] & data_wire[1737..1737] # !(sel_wire[0..0]) & data_wire[1729..1729]; + l1_w1_n109_mux_dataout = sel_wire[0..0] & data_wire[1753..1753] # !(sel_wire[0..0]) & data_wire[1745..1745]; + l1_w1_n10_mux_dataout = sel_wire[0..0] & data_wire[169..169] # !(sel_wire[0..0]) & data_wire[161..161]; + l1_w1_n110_mux_dataout = sel_wire[0..0] & data_wire[1769..1769] # !(sel_wire[0..0]) & data_wire[1761..1761]; + l1_w1_n111_mux_dataout = sel_wire[0..0] & data_wire[1785..1785] # !(sel_wire[0..0]) & data_wire[1777..1777]; + l1_w1_n112_mux_dataout = sel_wire[0..0] & data_wire[1801..1801] # !(sel_wire[0..0]) & data_wire[1793..1793]; + l1_w1_n113_mux_dataout = sel_wire[0..0] & data_wire[1817..1817] # !(sel_wire[0..0]) & data_wire[1809..1809]; + l1_w1_n114_mux_dataout = sel_wire[0..0] & data_wire[1833..1833] # !(sel_wire[0..0]) & data_wire[1825..1825]; + l1_w1_n115_mux_dataout = sel_wire[0..0] & data_wire[1849..1849] # !(sel_wire[0..0]) & data_wire[1841..1841]; + l1_w1_n116_mux_dataout = sel_wire[0..0] & data_wire[1865..1865] # !(sel_wire[0..0]) & data_wire[1857..1857]; + l1_w1_n117_mux_dataout = sel_wire[0..0] & data_wire[1881..1881] # !(sel_wire[0..0]) & data_wire[1873..1873]; + l1_w1_n118_mux_dataout = sel_wire[0..0] & data_wire[1897..1897] # !(sel_wire[0..0]) & data_wire[1889..1889]; + l1_w1_n119_mux_dataout = sel_wire[0..0] & data_wire[1913..1913] # !(sel_wire[0..0]) & data_wire[1905..1905]; + l1_w1_n11_mux_dataout = sel_wire[0..0] & data_wire[185..185] # !(sel_wire[0..0]) & data_wire[177..177]; + l1_w1_n120_mux_dataout = sel_wire[0..0] & data_wire[1929..1929] # !(sel_wire[0..0]) & data_wire[1921..1921]; + l1_w1_n121_mux_dataout = sel_wire[0..0] & data_wire[1945..1945] # !(sel_wire[0..0]) & data_wire[1937..1937]; + l1_w1_n122_mux_dataout = sel_wire[0..0] & data_wire[1961..1961] # !(sel_wire[0..0]) & data_wire[1953..1953]; + l1_w1_n123_mux_dataout = sel_wire[0..0] & data_wire[1977..1977] # !(sel_wire[0..0]) & data_wire[1969..1969]; + l1_w1_n124_mux_dataout = sel_wire[0..0] & data_wire[1993..1993] # !(sel_wire[0..0]) & data_wire[1985..1985]; + l1_w1_n125_mux_dataout = sel_wire[0..0] & data_wire[2009..2009] # !(sel_wire[0..0]) & data_wire[2001..2001]; + l1_w1_n126_mux_dataout = sel_wire[0..0] & data_wire[2025..2025] # !(sel_wire[0..0]) & data_wire[2017..2017]; + l1_w1_n127_mux_dataout = sel_wire[0..0] & data_wire[2041..2041] # !(sel_wire[0..0]) & data_wire[2033..2033]; + l1_w1_n12_mux_dataout = sel_wire[0..0] & data_wire[201..201] # !(sel_wire[0..0]) & data_wire[193..193]; + l1_w1_n13_mux_dataout = sel_wire[0..0] & data_wire[217..217] # !(sel_wire[0..0]) & data_wire[209..209]; + l1_w1_n14_mux_dataout = sel_wire[0..0] & data_wire[233..233] # !(sel_wire[0..0]) & data_wire[225..225]; + l1_w1_n15_mux_dataout = sel_wire[0..0] & data_wire[249..249] # !(sel_wire[0..0]) & data_wire[241..241]; + l1_w1_n16_mux_dataout = sel_wire[0..0] & data_wire[265..265] # !(sel_wire[0..0]) & data_wire[257..257]; + l1_w1_n17_mux_dataout = sel_wire[0..0] & data_wire[281..281] # !(sel_wire[0..0]) & data_wire[273..273]; + l1_w1_n18_mux_dataout = sel_wire[0..0] & data_wire[297..297] # !(sel_wire[0..0]) & data_wire[289..289]; + l1_w1_n19_mux_dataout = sel_wire[0..0] & data_wire[313..313] # !(sel_wire[0..0]) & data_wire[305..305]; + l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17]; + l1_w1_n20_mux_dataout = sel_wire[0..0] & data_wire[329..329] # !(sel_wire[0..0]) & data_wire[321..321]; + l1_w1_n21_mux_dataout = sel_wire[0..0] & data_wire[345..345] # !(sel_wire[0..0]) & data_wire[337..337]; + l1_w1_n22_mux_dataout = sel_wire[0..0] & data_wire[361..361] # !(sel_wire[0..0]) & data_wire[353..353]; + l1_w1_n23_mux_dataout = sel_wire[0..0] & data_wire[377..377] # !(sel_wire[0..0]) & data_wire[369..369]; + l1_w1_n24_mux_dataout = sel_wire[0..0] & data_wire[393..393] # !(sel_wire[0..0]) & data_wire[385..385]; + l1_w1_n25_mux_dataout = sel_wire[0..0] & data_wire[409..409] # !(sel_wire[0..0]) & data_wire[401..401]; + l1_w1_n26_mux_dataout = sel_wire[0..0] & data_wire[425..425] # !(sel_wire[0..0]) & data_wire[417..417]; + l1_w1_n27_mux_dataout = sel_wire[0..0] & data_wire[441..441] # !(sel_wire[0..0]) & data_wire[433..433]; + l1_w1_n28_mux_dataout = sel_wire[0..0] & data_wire[457..457] # !(sel_wire[0..0]) & data_wire[449..449]; + l1_w1_n29_mux_dataout = sel_wire[0..0] & data_wire[473..473] # !(sel_wire[0..0]) & data_wire[465..465]; + l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33]; + l1_w1_n30_mux_dataout = sel_wire[0..0] & data_wire[489..489] # !(sel_wire[0..0]) & data_wire[481..481]; + l1_w1_n31_mux_dataout = sel_wire[0..0] & data_wire[505..505] # !(sel_wire[0..0]) & data_wire[497..497]; + l1_w1_n32_mux_dataout = sel_wire[0..0] & data_wire[521..521] # !(sel_wire[0..0]) & data_wire[513..513]; + l1_w1_n33_mux_dataout = sel_wire[0..0] & data_wire[537..537] # !(sel_wire[0..0]) & data_wire[529..529]; + l1_w1_n34_mux_dataout = sel_wire[0..0] & data_wire[553..553] # !(sel_wire[0..0]) & data_wire[545..545]; + l1_w1_n35_mux_dataout = sel_wire[0..0] & data_wire[569..569] # !(sel_wire[0..0]) & data_wire[561..561]; + l1_w1_n36_mux_dataout = sel_wire[0..0] & data_wire[585..585] # !(sel_wire[0..0]) & data_wire[577..577]; + l1_w1_n37_mux_dataout = sel_wire[0..0] & data_wire[601..601] # !(sel_wire[0..0]) & data_wire[593..593]; + l1_w1_n38_mux_dataout = sel_wire[0..0] & data_wire[617..617] # !(sel_wire[0..0]) & data_wire[609..609]; + l1_w1_n39_mux_dataout = sel_wire[0..0] & data_wire[633..633] # !(sel_wire[0..0]) & data_wire[625..625]; + l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49]; + l1_w1_n40_mux_dataout = sel_wire[0..0] & data_wire[649..649] # !(sel_wire[0..0]) & data_wire[641..641]; + l1_w1_n41_mux_dataout = sel_wire[0..0] & data_wire[665..665] # !(sel_wire[0..0]) & data_wire[657..657]; + l1_w1_n42_mux_dataout = sel_wire[0..0] & data_wire[681..681] # !(sel_wire[0..0]) & data_wire[673..673]; + l1_w1_n43_mux_dataout = sel_wire[0..0] & data_wire[697..697] # !(sel_wire[0..0]) & data_wire[689..689]; + l1_w1_n44_mux_dataout = sel_wire[0..0] & data_wire[713..713] # !(sel_wire[0..0]) & data_wire[705..705]; + l1_w1_n45_mux_dataout = sel_wire[0..0] & data_wire[729..729] # !(sel_wire[0..0]) & data_wire[721..721]; + l1_w1_n46_mux_dataout = sel_wire[0..0] & data_wire[745..745] # !(sel_wire[0..0]) & data_wire[737..737]; + l1_w1_n47_mux_dataout = sel_wire[0..0] & data_wire[761..761] # !(sel_wire[0..0]) & data_wire[753..753]; + l1_w1_n48_mux_dataout = sel_wire[0..0] & data_wire[777..777] # !(sel_wire[0..0]) & data_wire[769..769]; + l1_w1_n49_mux_dataout = sel_wire[0..0] & data_wire[793..793] # !(sel_wire[0..0]) & data_wire[785..785]; + l1_w1_n4_mux_dataout = sel_wire[0..0] & data_wire[73..73] # !(sel_wire[0..0]) & data_wire[65..65]; + l1_w1_n50_mux_dataout = sel_wire[0..0] & data_wire[809..809] # !(sel_wire[0..0]) & data_wire[801..801]; + l1_w1_n51_mux_dataout = sel_wire[0..0] & data_wire[825..825] # !(sel_wire[0..0]) & data_wire[817..817]; + l1_w1_n52_mux_dataout = sel_wire[0..0] & data_wire[841..841] # !(sel_wire[0..0]) & data_wire[833..833]; + l1_w1_n53_mux_dataout = sel_wire[0..0] & data_wire[857..857] # !(sel_wire[0..0]) & data_wire[849..849]; + l1_w1_n54_mux_dataout = sel_wire[0..0] & data_wire[873..873] # !(sel_wire[0..0]) & data_wire[865..865]; + l1_w1_n55_mux_dataout = sel_wire[0..0] & data_wire[889..889] # !(sel_wire[0..0]) & data_wire[881..881]; + l1_w1_n56_mux_dataout = sel_wire[0..0] & data_wire[905..905] # !(sel_wire[0..0]) & data_wire[897..897]; + l1_w1_n57_mux_dataout = sel_wire[0..0] & data_wire[921..921] # !(sel_wire[0..0]) & data_wire[913..913]; + l1_w1_n58_mux_dataout = sel_wire[0..0] & data_wire[937..937] # !(sel_wire[0..0]) & data_wire[929..929]; + l1_w1_n59_mux_dataout = sel_wire[0..0] & data_wire[953..953] # !(sel_wire[0..0]) & data_wire[945..945]; + l1_w1_n5_mux_dataout = sel_wire[0..0] & data_wire[89..89] # !(sel_wire[0..0]) & data_wire[81..81]; + l1_w1_n60_mux_dataout = sel_wire[0..0] & data_wire[969..969] # !(sel_wire[0..0]) & data_wire[961..961]; + l1_w1_n61_mux_dataout = sel_wire[0..0] & data_wire[985..985] # !(sel_wire[0..0]) & data_wire[977..977]; + l1_w1_n62_mux_dataout = sel_wire[0..0] & data_wire[1001..1001] # !(sel_wire[0..0]) & data_wire[993..993]; + l1_w1_n63_mux_dataout = sel_wire[0..0] & data_wire[1017..1017] # !(sel_wire[0..0]) & data_wire[1009..1009]; + l1_w1_n64_mux_dataout = sel_wire[0..0] & data_wire[1033..1033] # !(sel_wire[0..0]) & data_wire[1025..1025]; + l1_w1_n65_mux_dataout = sel_wire[0..0] & data_wire[1049..1049] # !(sel_wire[0..0]) & data_wire[1041..1041]; + l1_w1_n66_mux_dataout = sel_wire[0..0] & data_wire[1065..1065] # !(sel_wire[0..0]) & data_wire[1057..1057]; + l1_w1_n67_mux_dataout = sel_wire[0..0] & data_wire[1081..1081] # !(sel_wire[0..0]) & data_wire[1073..1073]; + l1_w1_n68_mux_dataout = sel_wire[0..0] & data_wire[1097..1097] # !(sel_wire[0..0]) & data_wire[1089..1089]; + l1_w1_n69_mux_dataout = sel_wire[0..0] & data_wire[1113..1113] # !(sel_wire[0..0]) & data_wire[1105..1105]; + l1_w1_n6_mux_dataout = sel_wire[0..0] & data_wire[105..105] # !(sel_wire[0..0]) & data_wire[97..97]; + l1_w1_n70_mux_dataout = sel_wire[0..0] & data_wire[1129..1129] # !(sel_wire[0..0]) & data_wire[1121..1121]; + l1_w1_n71_mux_dataout = sel_wire[0..0] & data_wire[1145..1145] # !(sel_wire[0..0]) & data_wire[1137..1137]; + l1_w1_n72_mux_dataout = sel_wire[0..0] & data_wire[1161..1161] # !(sel_wire[0..0]) & data_wire[1153..1153]; + l1_w1_n73_mux_dataout = sel_wire[0..0] & data_wire[1177..1177] # !(sel_wire[0..0]) & data_wire[1169..1169]; + l1_w1_n74_mux_dataout = sel_wire[0..0] & data_wire[1193..1193] # !(sel_wire[0..0]) & data_wire[1185..1185]; + l1_w1_n75_mux_dataout = sel_wire[0..0] & data_wire[1209..1209] # !(sel_wire[0..0]) & data_wire[1201..1201]; + l1_w1_n76_mux_dataout = sel_wire[0..0] & data_wire[1225..1225] # !(sel_wire[0..0]) & data_wire[1217..1217]; + l1_w1_n77_mux_dataout = sel_wire[0..0] & data_wire[1241..1241] # !(sel_wire[0..0]) & data_wire[1233..1233]; + l1_w1_n78_mux_dataout = sel_wire[0..0] & data_wire[1257..1257] # !(sel_wire[0..0]) & data_wire[1249..1249]; + l1_w1_n79_mux_dataout = sel_wire[0..0] & data_wire[1273..1273] # !(sel_wire[0..0]) & data_wire[1265..1265]; + l1_w1_n7_mux_dataout = sel_wire[0..0] & data_wire[121..121] # !(sel_wire[0..0]) & data_wire[113..113]; + l1_w1_n80_mux_dataout = sel_wire[0..0] & data_wire[1289..1289] # !(sel_wire[0..0]) & data_wire[1281..1281]; + l1_w1_n81_mux_dataout = sel_wire[0..0] & data_wire[1305..1305] # !(sel_wire[0..0]) & data_wire[1297..1297]; + l1_w1_n82_mux_dataout = sel_wire[0..0] & data_wire[1321..1321] # !(sel_wire[0..0]) & data_wire[1313..1313]; + l1_w1_n83_mux_dataout = sel_wire[0..0] & data_wire[1337..1337] # !(sel_wire[0..0]) & data_wire[1329..1329]; + l1_w1_n84_mux_dataout = sel_wire[0..0] & data_wire[1353..1353] # !(sel_wire[0..0]) & data_wire[1345..1345]; + l1_w1_n85_mux_dataout = sel_wire[0..0] & data_wire[1369..1369] # !(sel_wire[0..0]) & data_wire[1361..1361]; + l1_w1_n86_mux_dataout = sel_wire[0..0] & data_wire[1385..1385] # !(sel_wire[0..0]) & data_wire[1377..1377]; + l1_w1_n87_mux_dataout = sel_wire[0..0] & data_wire[1401..1401] # !(sel_wire[0..0]) & data_wire[1393..1393]; + l1_w1_n88_mux_dataout = sel_wire[0..0] & data_wire[1417..1417] # !(sel_wire[0..0]) & data_wire[1409..1409]; + l1_w1_n89_mux_dataout = sel_wire[0..0] & data_wire[1433..1433] # !(sel_wire[0..0]) & data_wire[1425..1425]; + l1_w1_n8_mux_dataout = sel_wire[0..0] & data_wire[137..137] # !(sel_wire[0..0]) & data_wire[129..129]; + l1_w1_n90_mux_dataout = sel_wire[0..0] & data_wire[1449..1449] # !(sel_wire[0..0]) & data_wire[1441..1441]; + l1_w1_n91_mux_dataout = sel_wire[0..0] & data_wire[1465..1465] # !(sel_wire[0..0]) & data_wire[1457..1457]; + l1_w1_n92_mux_dataout = sel_wire[0..0] & data_wire[1481..1481] # !(sel_wire[0..0]) & data_wire[1473..1473]; + l1_w1_n93_mux_dataout = sel_wire[0..0] & data_wire[1497..1497] # !(sel_wire[0..0]) & data_wire[1489..1489]; + l1_w1_n94_mux_dataout = sel_wire[0..0] & data_wire[1513..1513] # !(sel_wire[0..0]) & data_wire[1505..1505]; + l1_w1_n95_mux_dataout = sel_wire[0..0] & data_wire[1529..1529] # !(sel_wire[0..0]) & data_wire[1521..1521]; + l1_w1_n96_mux_dataout = sel_wire[0..0] & data_wire[1545..1545] # !(sel_wire[0..0]) & data_wire[1537..1537]; + l1_w1_n97_mux_dataout = sel_wire[0..0] & data_wire[1561..1561] # !(sel_wire[0..0]) & data_wire[1553..1553]; + l1_w1_n98_mux_dataout = sel_wire[0..0] & data_wire[1577..1577] # !(sel_wire[0..0]) & data_wire[1569..1569]; + l1_w1_n99_mux_dataout = sel_wire[0..0] & data_wire[1593..1593] # !(sel_wire[0..0]) & data_wire[1585..1585]; + l1_w1_n9_mux_dataout = sel_wire[0..0] & data_wire[153..153] # !(sel_wire[0..0]) & data_wire[145..145]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w2_n100_mux_dataout = sel_wire[0..0] & data_wire[1610..1610] # !(sel_wire[0..0]) & data_wire[1602..1602]; + l1_w2_n101_mux_dataout = sel_wire[0..0] & data_wire[1626..1626] # !(sel_wire[0..0]) & data_wire[1618..1618]; + l1_w2_n102_mux_dataout = sel_wire[0..0] & data_wire[1642..1642] # !(sel_wire[0..0]) & data_wire[1634..1634]; + l1_w2_n103_mux_dataout = sel_wire[0..0] & data_wire[1658..1658] # !(sel_wire[0..0]) & data_wire[1650..1650]; + l1_w2_n104_mux_dataout = sel_wire[0..0] & data_wire[1674..1674] # !(sel_wire[0..0]) & data_wire[1666..1666]; + l1_w2_n105_mux_dataout = sel_wire[0..0] & data_wire[1690..1690] # !(sel_wire[0..0]) & data_wire[1682..1682]; + l1_w2_n106_mux_dataout = sel_wire[0..0] & data_wire[1706..1706] # !(sel_wire[0..0]) & data_wire[1698..1698]; + l1_w2_n107_mux_dataout = sel_wire[0..0] & data_wire[1722..1722] # !(sel_wire[0..0]) & data_wire[1714..1714]; + l1_w2_n108_mux_dataout = sel_wire[0..0] & data_wire[1738..1738] # !(sel_wire[0..0]) & data_wire[1730..1730]; + l1_w2_n109_mux_dataout = sel_wire[0..0] & data_wire[1754..1754] # !(sel_wire[0..0]) & data_wire[1746..1746]; + l1_w2_n10_mux_dataout = sel_wire[0..0] & data_wire[170..170] # !(sel_wire[0..0]) & data_wire[162..162]; + l1_w2_n110_mux_dataout = sel_wire[0..0] & data_wire[1770..1770] # !(sel_wire[0..0]) & data_wire[1762..1762]; + l1_w2_n111_mux_dataout = sel_wire[0..0] & data_wire[1786..1786] # !(sel_wire[0..0]) & data_wire[1778..1778]; + l1_w2_n112_mux_dataout = sel_wire[0..0] & data_wire[1802..1802] # !(sel_wire[0..0]) & data_wire[1794..1794]; + l1_w2_n113_mux_dataout = sel_wire[0..0] & data_wire[1818..1818] # !(sel_wire[0..0]) & data_wire[1810..1810]; + l1_w2_n114_mux_dataout = sel_wire[0..0] & data_wire[1834..1834] # !(sel_wire[0..0]) & data_wire[1826..1826]; + l1_w2_n115_mux_dataout = sel_wire[0..0] & data_wire[1850..1850] # !(sel_wire[0..0]) & data_wire[1842..1842]; + l1_w2_n116_mux_dataout = sel_wire[0..0] & data_wire[1866..1866] # !(sel_wire[0..0]) & data_wire[1858..1858]; + l1_w2_n117_mux_dataout = sel_wire[0..0] & data_wire[1882..1882] # !(sel_wire[0..0]) & data_wire[1874..1874]; + l1_w2_n118_mux_dataout = sel_wire[0..0] & data_wire[1898..1898] # !(sel_wire[0..0]) & data_wire[1890..1890]; + l1_w2_n119_mux_dataout = sel_wire[0..0] & data_wire[1914..1914] # !(sel_wire[0..0]) & data_wire[1906..1906]; + l1_w2_n11_mux_dataout = sel_wire[0..0] & data_wire[186..186] # !(sel_wire[0..0]) & data_wire[178..178]; + l1_w2_n120_mux_dataout = sel_wire[0..0] & data_wire[1930..1930] # !(sel_wire[0..0]) & data_wire[1922..1922]; + l1_w2_n121_mux_dataout = sel_wire[0..0] & data_wire[1946..1946] # !(sel_wire[0..0]) & data_wire[1938..1938]; + l1_w2_n122_mux_dataout = sel_wire[0..0] & data_wire[1962..1962] # !(sel_wire[0..0]) & data_wire[1954..1954]; + l1_w2_n123_mux_dataout = sel_wire[0..0] & data_wire[1978..1978] # !(sel_wire[0..0]) & data_wire[1970..1970]; + l1_w2_n124_mux_dataout = sel_wire[0..0] & data_wire[1994..1994] # !(sel_wire[0..0]) & data_wire[1986..1986]; + l1_w2_n125_mux_dataout = sel_wire[0..0] & data_wire[2010..2010] # !(sel_wire[0..0]) & data_wire[2002..2002]; + l1_w2_n126_mux_dataout = sel_wire[0..0] & data_wire[2026..2026] # !(sel_wire[0..0]) & data_wire[2018..2018]; + l1_w2_n127_mux_dataout = sel_wire[0..0] & data_wire[2042..2042] # !(sel_wire[0..0]) & data_wire[2034..2034]; + l1_w2_n12_mux_dataout = sel_wire[0..0] & data_wire[202..202] # !(sel_wire[0..0]) & data_wire[194..194]; + l1_w2_n13_mux_dataout = sel_wire[0..0] & data_wire[218..218] # !(sel_wire[0..0]) & data_wire[210..210]; + l1_w2_n14_mux_dataout = sel_wire[0..0] & data_wire[234..234] # !(sel_wire[0..0]) & data_wire[226..226]; + l1_w2_n15_mux_dataout = sel_wire[0..0] & data_wire[250..250] # !(sel_wire[0..0]) & data_wire[242..242]; + l1_w2_n16_mux_dataout = sel_wire[0..0] & data_wire[266..266] # !(sel_wire[0..0]) & data_wire[258..258]; + l1_w2_n17_mux_dataout = sel_wire[0..0] & data_wire[282..282] # !(sel_wire[0..0]) & data_wire[274..274]; + l1_w2_n18_mux_dataout = sel_wire[0..0] & data_wire[298..298] # !(sel_wire[0..0]) & data_wire[290..290]; + l1_w2_n19_mux_dataout = sel_wire[0..0] & data_wire[314..314] # !(sel_wire[0..0]) & data_wire[306..306]; + l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18]; + l1_w2_n20_mux_dataout = sel_wire[0..0] & data_wire[330..330] # !(sel_wire[0..0]) & data_wire[322..322]; + l1_w2_n21_mux_dataout = sel_wire[0..0] & data_wire[346..346] # !(sel_wire[0..0]) & data_wire[338..338]; + l1_w2_n22_mux_dataout = sel_wire[0..0] & data_wire[362..362] # !(sel_wire[0..0]) & data_wire[354..354]; + l1_w2_n23_mux_dataout = sel_wire[0..0] & data_wire[378..378] # !(sel_wire[0..0]) & data_wire[370..370]; + l1_w2_n24_mux_dataout = sel_wire[0..0] & data_wire[394..394] # !(sel_wire[0..0]) & data_wire[386..386]; + l1_w2_n25_mux_dataout = sel_wire[0..0] & data_wire[410..410] # !(sel_wire[0..0]) & data_wire[402..402]; + l1_w2_n26_mux_dataout = sel_wire[0..0] & data_wire[426..426] # !(sel_wire[0..0]) & data_wire[418..418]; + l1_w2_n27_mux_dataout = sel_wire[0..0] & data_wire[442..442] # !(sel_wire[0..0]) & data_wire[434..434]; + l1_w2_n28_mux_dataout = sel_wire[0..0] & data_wire[458..458] # !(sel_wire[0..0]) & data_wire[450..450]; + l1_w2_n29_mux_dataout = sel_wire[0..0] & data_wire[474..474] # !(sel_wire[0..0]) & data_wire[466..466]; + l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34]; + l1_w2_n30_mux_dataout = sel_wire[0..0] & data_wire[490..490] # !(sel_wire[0..0]) & data_wire[482..482]; + l1_w2_n31_mux_dataout = sel_wire[0..0] & data_wire[506..506] # !(sel_wire[0..0]) & data_wire[498..498]; + l1_w2_n32_mux_dataout = sel_wire[0..0] & data_wire[522..522] # !(sel_wire[0..0]) & data_wire[514..514]; + l1_w2_n33_mux_dataout = sel_wire[0..0] & data_wire[538..538] # !(sel_wire[0..0]) & data_wire[530..530]; + l1_w2_n34_mux_dataout = sel_wire[0..0] & data_wire[554..554] # !(sel_wire[0..0]) & data_wire[546..546]; + l1_w2_n35_mux_dataout = sel_wire[0..0] & data_wire[570..570] # !(sel_wire[0..0]) & data_wire[562..562]; + l1_w2_n36_mux_dataout = sel_wire[0..0] & data_wire[586..586] # !(sel_wire[0..0]) & data_wire[578..578]; + l1_w2_n37_mux_dataout = sel_wire[0..0] & data_wire[602..602] # !(sel_wire[0..0]) & data_wire[594..594]; + l1_w2_n38_mux_dataout = sel_wire[0..0] & data_wire[618..618] # !(sel_wire[0..0]) & data_wire[610..610]; + l1_w2_n39_mux_dataout = sel_wire[0..0] & data_wire[634..634] # !(sel_wire[0..0]) & data_wire[626..626]; + l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50]; + l1_w2_n40_mux_dataout = sel_wire[0..0] & data_wire[650..650] # !(sel_wire[0..0]) & data_wire[642..642]; + l1_w2_n41_mux_dataout = sel_wire[0..0] & data_wire[666..666] # !(sel_wire[0..0]) & data_wire[658..658]; + l1_w2_n42_mux_dataout = sel_wire[0..0] & data_wire[682..682] # !(sel_wire[0..0]) & data_wire[674..674]; + l1_w2_n43_mux_dataout = sel_wire[0..0] & data_wire[698..698] # !(sel_wire[0..0]) & data_wire[690..690]; + l1_w2_n44_mux_dataout = sel_wire[0..0] & data_wire[714..714] # !(sel_wire[0..0]) & data_wire[706..706]; + l1_w2_n45_mux_dataout = sel_wire[0..0] & data_wire[730..730] # !(sel_wire[0..0]) & data_wire[722..722]; + l1_w2_n46_mux_dataout = sel_wire[0..0] & data_wire[746..746] # !(sel_wire[0..0]) & data_wire[738..738]; + l1_w2_n47_mux_dataout = sel_wire[0..0] & data_wire[762..762] # !(sel_wire[0..0]) & data_wire[754..754]; + l1_w2_n48_mux_dataout = sel_wire[0..0] & data_wire[778..778] # !(sel_wire[0..0]) & data_wire[770..770]; + l1_w2_n49_mux_dataout = sel_wire[0..0] & data_wire[794..794] # !(sel_wire[0..0]) & data_wire[786..786]; + l1_w2_n4_mux_dataout = sel_wire[0..0] & data_wire[74..74] # !(sel_wire[0..0]) & data_wire[66..66]; + l1_w2_n50_mux_dataout = sel_wire[0..0] & data_wire[810..810] # !(sel_wire[0..0]) & data_wire[802..802]; + l1_w2_n51_mux_dataout = sel_wire[0..0] & data_wire[826..826] # !(sel_wire[0..0]) & data_wire[818..818]; + l1_w2_n52_mux_dataout = sel_wire[0..0] & data_wire[842..842] # !(sel_wire[0..0]) & data_wire[834..834]; + l1_w2_n53_mux_dataout = sel_wire[0..0] & data_wire[858..858] # !(sel_wire[0..0]) & data_wire[850..850]; + l1_w2_n54_mux_dataout = sel_wire[0..0] & data_wire[874..874] # !(sel_wire[0..0]) & data_wire[866..866]; + l1_w2_n55_mux_dataout = sel_wire[0..0] & data_wire[890..890] # !(sel_wire[0..0]) & data_wire[882..882]; + l1_w2_n56_mux_dataout = sel_wire[0..0] & data_wire[906..906] # !(sel_wire[0..0]) & data_wire[898..898]; + l1_w2_n57_mux_dataout = sel_wire[0..0] & data_wire[922..922] # !(sel_wire[0..0]) & data_wire[914..914]; + l1_w2_n58_mux_dataout = sel_wire[0..0] & data_wire[938..938] # !(sel_wire[0..0]) & data_wire[930..930]; + l1_w2_n59_mux_dataout = sel_wire[0..0] & data_wire[954..954] # !(sel_wire[0..0]) & data_wire[946..946]; + l1_w2_n5_mux_dataout = sel_wire[0..0] & data_wire[90..90] # !(sel_wire[0..0]) & data_wire[82..82]; + l1_w2_n60_mux_dataout = sel_wire[0..0] & data_wire[970..970] # !(sel_wire[0..0]) & data_wire[962..962]; + l1_w2_n61_mux_dataout = sel_wire[0..0] & data_wire[986..986] # !(sel_wire[0..0]) & data_wire[978..978]; + l1_w2_n62_mux_dataout = sel_wire[0..0] & data_wire[1002..1002] # !(sel_wire[0..0]) & data_wire[994..994]; + l1_w2_n63_mux_dataout = sel_wire[0..0] & data_wire[1018..1018] # !(sel_wire[0..0]) & data_wire[1010..1010]; + l1_w2_n64_mux_dataout = sel_wire[0..0] & data_wire[1034..1034] # !(sel_wire[0..0]) & data_wire[1026..1026]; + l1_w2_n65_mux_dataout = sel_wire[0..0] & data_wire[1050..1050] # !(sel_wire[0..0]) & data_wire[1042..1042]; + l1_w2_n66_mux_dataout = sel_wire[0..0] & data_wire[1066..1066] # !(sel_wire[0..0]) & data_wire[1058..1058]; + l1_w2_n67_mux_dataout = sel_wire[0..0] & data_wire[1082..1082] # !(sel_wire[0..0]) & data_wire[1074..1074]; + l1_w2_n68_mux_dataout = sel_wire[0..0] & data_wire[1098..1098] # !(sel_wire[0..0]) & data_wire[1090..1090]; + l1_w2_n69_mux_dataout = sel_wire[0..0] & data_wire[1114..1114] # !(sel_wire[0..0]) & data_wire[1106..1106]; + l1_w2_n6_mux_dataout = sel_wire[0..0] & data_wire[106..106] # !(sel_wire[0..0]) & data_wire[98..98]; + l1_w2_n70_mux_dataout = sel_wire[0..0] & data_wire[1130..1130] # !(sel_wire[0..0]) & data_wire[1122..1122]; + l1_w2_n71_mux_dataout = sel_wire[0..0] & data_wire[1146..1146] # !(sel_wire[0..0]) & data_wire[1138..1138]; + l1_w2_n72_mux_dataout = sel_wire[0..0] & data_wire[1162..1162] # !(sel_wire[0..0]) & data_wire[1154..1154]; + l1_w2_n73_mux_dataout = sel_wire[0..0] & data_wire[1178..1178] # !(sel_wire[0..0]) & data_wire[1170..1170]; + l1_w2_n74_mux_dataout = sel_wire[0..0] & data_wire[1194..1194] # !(sel_wire[0..0]) & data_wire[1186..1186]; + l1_w2_n75_mux_dataout = sel_wire[0..0] & data_wire[1210..1210] # !(sel_wire[0..0]) & data_wire[1202..1202]; + l1_w2_n76_mux_dataout = sel_wire[0..0] & data_wire[1226..1226] # !(sel_wire[0..0]) & data_wire[1218..1218]; + l1_w2_n77_mux_dataout = sel_wire[0..0] & data_wire[1242..1242] # !(sel_wire[0..0]) & data_wire[1234..1234]; + l1_w2_n78_mux_dataout = sel_wire[0..0] & data_wire[1258..1258] # !(sel_wire[0..0]) & data_wire[1250..1250]; + l1_w2_n79_mux_dataout = sel_wire[0..0] & data_wire[1274..1274] # !(sel_wire[0..0]) & data_wire[1266..1266]; + l1_w2_n7_mux_dataout = sel_wire[0..0] & data_wire[122..122] # !(sel_wire[0..0]) & data_wire[114..114]; + l1_w2_n80_mux_dataout = sel_wire[0..0] & data_wire[1290..1290] # !(sel_wire[0..0]) & data_wire[1282..1282]; + l1_w2_n81_mux_dataout = sel_wire[0..0] & data_wire[1306..1306] # !(sel_wire[0..0]) & data_wire[1298..1298]; + l1_w2_n82_mux_dataout = sel_wire[0..0] & data_wire[1322..1322] # !(sel_wire[0..0]) & data_wire[1314..1314]; + l1_w2_n83_mux_dataout = sel_wire[0..0] & data_wire[1338..1338] # !(sel_wire[0..0]) & data_wire[1330..1330]; + l1_w2_n84_mux_dataout = sel_wire[0..0] & data_wire[1354..1354] # !(sel_wire[0..0]) & data_wire[1346..1346]; + l1_w2_n85_mux_dataout = sel_wire[0..0] & data_wire[1370..1370] # !(sel_wire[0..0]) & data_wire[1362..1362]; + l1_w2_n86_mux_dataout = sel_wire[0..0] & data_wire[1386..1386] # !(sel_wire[0..0]) & data_wire[1378..1378]; + l1_w2_n87_mux_dataout = sel_wire[0..0] & data_wire[1402..1402] # !(sel_wire[0..0]) & data_wire[1394..1394]; + l1_w2_n88_mux_dataout = sel_wire[0..0] & data_wire[1418..1418] # !(sel_wire[0..0]) & data_wire[1410..1410]; + l1_w2_n89_mux_dataout = sel_wire[0..0] & data_wire[1434..1434] # !(sel_wire[0..0]) & data_wire[1426..1426]; + l1_w2_n8_mux_dataout = sel_wire[0..0] & data_wire[138..138] # !(sel_wire[0..0]) & data_wire[130..130]; + l1_w2_n90_mux_dataout = sel_wire[0..0] & data_wire[1450..1450] # !(sel_wire[0..0]) & data_wire[1442..1442]; + l1_w2_n91_mux_dataout = sel_wire[0..0] & data_wire[1466..1466] # !(sel_wire[0..0]) & data_wire[1458..1458]; + l1_w2_n92_mux_dataout = sel_wire[0..0] & data_wire[1482..1482] # !(sel_wire[0..0]) & data_wire[1474..1474]; + l1_w2_n93_mux_dataout = sel_wire[0..0] & data_wire[1498..1498] # !(sel_wire[0..0]) & data_wire[1490..1490]; + l1_w2_n94_mux_dataout = sel_wire[0..0] & data_wire[1514..1514] # !(sel_wire[0..0]) & data_wire[1506..1506]; + l1_w2_n95_mux_dataout = sel_wire[0..0] & data_wire[1530..1530] # !(sel_wire[0..0]) & data_wire[1522..1522]; + l1_w2_n96_mux_dataout = sel_wire[0..0] & data_wire[1546..1546] # !(sel_wire[0..0]) & data_wire[1538..1538]; + l1_w2_n97_mux_dataout = sel_wire[0..0] & data_wire[1562..1562] # !(sel_wire[0..0]) & data_wire[1554..1554]; + l1_w2_n98_mux_dataout = sel_wire[0..0] & data_wire[1578..1578] # !(sel_wire[0..0]) & data_wire[1570..1570]; + l1_w2_n99_mux_dataout = sel_wire[0..0] & data_wire[1594..1594] # !(sel_wire[0..0]) & data_wire[1586..1586]; + l1_w2_n9_mux_dataout = sel_wire[0..0] & data_wire[154..154] # !(sel_wire[0..0]) & data_wire[146..146]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w3_n100_mux_dataout = sel_wire[0..0] & data_wire[1611..1611] # !(sel_wire[0..0]) & data_wire[1603..1603]; + l1_w3_n101_mux_dataout = sel_wire[0..0] & data_wire[1627..1627] # !(sel_wire[0..0]) & data_wire[1619..1619]; + l1_w3_n102_mux_dataout = sel_wire[0..0] & data_wire[1643..1643] # !(sel_wire[0..0]) & data_wire[1635..1635]; + l1_w3_n103_mux_dataout = sel_wire[0..0] & data_wire[1659..1659] # !(sel_wire[0..0]) & data_wire[1651..1651]; + l1_w3_n104_mux_dataout = sel_wire[0..0] & data_wire[1675..1675] # !(sel_wire[0..0]) & data_wire[1667..1667]; + l1_w3_n105_mux_dataout = sel_wire[0..0] & data_wire[1691..1691] # !(sel_wire[0..0]) & data_wire[1683..1683]; + l1_w3_n106_mux_dataout = sel_wire[0..0] & data_wire[1707..1707] # !(sel_wire[0..0]) & data_wire[1699..1699]; + l1_w3_n107_mux_dataout = sel_wire[0..0] & data_wire[1723..1723] # !(sel_wire[0..0]) & data_wire[1715..1715]; + l1_w3_n108_mux_dataout = sel_wire[0..0] & data_wire[1739..1739] # !(sel_wire[0..0]) & data_wire[1731..1731]; + l1_w3_n109_mux_dataout = sel_wire[0..0] & data_wire[1755..1755] # !(sel_wire[0..0]) & data_wire[1747..1747]; + l1_w3_n10_mux_dataout = sel_wire[0..0] & data_wire[171..171] # !(sel_wire[0..0]) & data_wire[163..163]; + l1_w3_n110_mux_dataout = sel_wire[0..0] & data_wire[1771..1771] # !(sel_wire[0..0]) & data_wire[1763..1763]; + l1_w3_n111_mux_dataout = sel_wire[0..0] & data_wire[1787..1787] # !(sel_wire[0..0]) & data_wire[1779..1779]; + l1_w3_n112_mux_dataout = sel_wire[0..0] & data_wire[1803..1803] # !(sel_wire[0..0]) & data_wire[1795..1795]; + l1_w3_n113_mux_dataout = sel_wire[0..0] & data_wire[1819..1819] # !(sel_wire[0..0]) & data_wire[1811..1811]; + l1_w3_n114_mux_dataout = sel_wire[0..0] & data_wire[1835..1835] # !(sel_wire[0..0]) & data_wire[1827..1827]; + l1_w3_n115_mux_dataout = sel_wire[0..0] & data_wire[1851..1851] # !(sel_wire[0..0]) & data_wire[1843..1843]; + l1_w3_n116_mux_dataout = sel_wire[0..0] & data_wire[1867..1867] # !(sel_wire[0..0]) & data_wire[1859..1859]; + l1_w3_n117_mux_dataout = sel_wire[0..0] & data_wire[1883..1883] # !(sel_wire[0..0]) & data_wire[1875..1875]; + l1_w3_n118_mux_dataout = sel_wire[0..0] & data_wire[1899..1899] # !(sel_wire[0..0]) & data_wire[1891..1891]; + l1_w3_n119_mux_dataout = sel_wire[0..0] & data_wire[1915..1915] # !(sel_wire[0..0]) & data_wire[1907..1907]; + l1_w3_n11_mux_dataout = sel_wire[0..0] & data_wire[187..187] # !(sel_wire[0..0]) & data_wire[179..179]; + l1_w3_n120_mux_dataout = sel_wire[0..0] & data_wire[1931..1931] # !(sel_wire[0..0]) & data_wire[1923..1923]; + l1_w3_n121_mux_dataout = sel_wire[0..0] & data_wire[1947..1947] # !(sel_wire[0..0]) & data_wire[1939..1939]; + l1_w3_n122_mux_dataout = sel_wire[0..0] & data_wire[1963..1963] # !(sel_wire[0..0]) & data_wire[1955..1955]; + l1_w3_n123_mux_dataout = sel_wire[0..0] & data_wire[1979..1979] # !(sel_wire[0..0]) & data_wire[1971..1971]; + l1_w3_n124_mux_dataout = sel_wire[0..0] & data_wire[1995..1995] # !(sel_wire[0..0]) & data_wire[1987..1987]; + l1_w3_n125_mux_dataout = sel_wire[0..0] & data_wire[2011..2011] # !(sel_wire[0..0]) & data_wire[2003..2003]; + l1_w3_n126_mux_dataout = sel_wire[0..0] & data_wire[2027..2027] # !(sel_wire[0..0]) & data_wire[2019..2019]; + l1_w3_n127_mux_dataout = sel_wire[0..0] & data_wire[2043..2043] # !(sel_wire[0..0]) & data_wire[2035..2035]; + l1_w3_n12_mux_dataout = sel_wire[0..0] & data_wire[203..203] # !(sel_wire[0..0]) & data_wire[195..195]; + l1_w3_n13_mux_dataout = sel_wire[0..0] & data_wire[219..219] # !(sel_wire[0..0]) & data_wire[211..211]; + l1_w3_n14_mux_dataout = sel_wire[0..0] & data_wire[235..235] # !(sel_wire[0..0]) & data_wire[227..227]; + l1_w3_n15_mux_dataout = sel_wire[0..0] & data_wire[251..251] # !(sel_wire[0..0]) & data_wire[243..243]; + l1_w3_n16_mux_dataout = sel_wire[0..0] & data_wire[267..267] # !(sel_wire[0..0]) & data_wire[259..259]; + l1_w3_n17_mux_dataout = sel_wire[0..0] & data_wire[283..283] # !(sel_wire[0..0]) & data_wire[275..275]; + l1_w3_n18_mux_dataout = sel_wire[0..0] & data_wire[299..299] # !(sel_wire[0..0]) & data_wire[291..291]; + l1_w3_n19_mux_dataout = sel_wire[0..0] & data_wire[315..315] # !(sel_wire[0..0]) & data_wire[307..307]; + l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19]; + l1_w3_n20_mux_dataout = sel_wire[0..0] & data_wire[331..331] # !(sel_wire[0..0]) & data_wire[323..323]; + l1_w3_n21_mux_dataout = sel_wire[0..0] & data_wire[347..347] # !(sel_wire[0..0]) & data_wire[339..339]; + l1_w3_n22_mux_dataout = sel_wire[0..0] & data_wire[363..363] # !(sel_wire[0..0]) & data_wire[355..355]; + l1_w3_n23_mux_dataout = sel_wire[0..0] & data_wire[379..379] # !(sel_wire[0..0]) & data_wire[371..371]; + l1_w3_n24_mux_dataout = sel_wire[0..0] & data_wire[395..395] # !(sel_wire[0..0]) & data_wire[387..387]; + l1_w3_n25_mux_dataout = sel_wire[0..0] & data_wire[411..411] # !(sel_wire[0..0]) & data_wire[403..403]; + l1_w3_n26_mux_dataout = sel_wire[0..0] & data_wire[427..427] # !(sel_wire[0..0]) & data_wire[419..419]; + l1_w3_n27_mux_dataout = sel_wire[0..0] & data_wire[443..443] # !(sel_wire[0..0]) & data_wire[435..435]; + l1_w3_n28_mux_dataout = sel_wire[0..0] & data_wire[459..459] # !(sel_wire[0..0]) & data_wire[451..451]; + l1_w3_n29_mux_dataout = sel_wire[0..0] & data_wire[475..475] # !(sel_wire[0..0]) & data_wire[467..467]; + l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35]; + l1_w3_n30_mux_dataout = sel_wire[0..0] & data_wire[491..491] # !(sel_wire[0..0]) & data_wire[483..483]; + l1_w3_n31_mux_dataout = sel_wire[0..0] & data_wire[507..507] # !(sel_wire[0..0]) & data_wire[499..499]; + l1_w3_n32_mux_dataout = sel_wire[0..0] & data_wire[523..523] # !(sel_wire[0..0]) & data_wire[515..515]; + l1_w3_n33_mux_dataout = sel_wire[0..0] & data_wire[539..539] # !(sel_wire[0..0]) & data_wire[531..531]; + l1_w3_n34_mux_dataout = sel_wire[0..0] & data_wire[555..555] # !(sel_wire[0..0]) & data_wire[547..547]; + l1_w3_n35_mux_dataout = sel_wire[0..0] & data_wire[571..571] # !(sel_wire[0..0]) & data_wire[563..563]; + l1_w3_n36_mux_dataout = sel_wire[0..0] & data_wire[587..587] # !(sel_wire[0..0]) & data_wire[579..579]; + l1_w3_n37_mux_dataout = sel_wire[0..0] & data_wire[603..603] # !(sel_wire[0..0]) & data_wire[595..595]; + l1_w3_n38_mux_dataout = sel_wire[0..0] & data_wire[619..619] # !(sel_wire[0..0]) & data_wire[611..611]; + l1_w3_n39_mux_dataout = sel_wire[0..0] & data_wire[635..635] # !(sel_wire[0..0]) & data_wire[627..627]; + l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51]; + l1_w3_n40_mux_dataout = sel_wire[0..0] & data_wire[651..651] # !(sel_wire[0..0]) & data_wire[643..643]; + l1_w3_n41_mux_dataout = sel_wire[0..0] & data_wire[667..667] # !(sel_wire[0..0]) & data_wire[659..659]; + l1_w3_n42_mux_dataout = sel_wire[0..0] & data_wire[683..683] # !(sel_wire[0..0]) & data_wire[675..675]; + l1_w3_n43_mux_dataout = sel_wire[0..0] & data_wire[699..699] # !(sel_wire[0..0]) & data_wire[691..691]; + l1_w3_n44_mux_dataout = sel_wire[0..0] & data_wire[715..715] # !(sel_wire[0..0]) & data_wire[707..707]; + l1_w3_n45_mux_dataout = sel_wire[0..0] & data_wire[731..731] # !(sel_wire[0..0]) & data_wire[723..723]; + l1_w3_n46_mux_dataout = sel_wire[0..0] & data_wire[747..747] # !(sel_wire[0..0]) & data_wire[739..739]; + l1_w3_n47_mux_dataout = sel_wire[0..0] & data_wire[763..763] # !(sel_wire[0..0]) & data_wire[755..755]; + l1_w3_n48_mux_dataout = sel_wire[0..0] & data_wire[779..779] # !(sel_wire[0..0]) & data_wire[771..771]; + l1_w3_n49_mux_dataout = sel_wire[0..0] & data_wire[795..795] # !(sel_wire[0..0]) & data_wire[787..787]; + l1_w3_n4_mux_dataout = sel_wire[0..0] & data_wire[75..75] # !(sel_wire[0..0]) & data_wire[67..67]; + l1_w3_n50_mux_dataout = sel_wire[0..0] & data_wire[811..811] # !(sel_wire[0..0]) & data_wire[803..803]; + l1_w3_n51_mux_dataout = sel_wire[0..0] & data_wire[827..827] # !(sel_wire[0..0]) & data_wire[819..819]; + l1_w3_n52_mux_dataout = sel_wire[0..0] & data_wire[843..843] # !(sel_wire[0..0]) & data_wire[835..835]; + l1_w3_n53_mux_dataout = sel_wire[0..0] & data_wire[859..859] # !(sel_wire[0..0]) & data_wire[851..851]; + l1_w3_n54_mux_dataout = sel_wire[0..0] & data_wire[875..875] # !(sel_wire[0..0]) & data_wire[867..867]; + l1_w3_n55_mux_dataout = sel_wire[0..0] & data_wire[891..891] # !(sel_wire[0..0]) & data_wire[883..883]; + l1_w3_n56_mux_dataout = sel_wire[0..0] & data_wire[907..907] # !(sel_wire[0..0]) & data_wire[899..899]; + l1_w3_n57_mux_dataout = sel_wire[0..0] & data_wire[923..923] # !(sel_wire[0..0]) & data_wire[915..915]; + l1_w3_n58_mux_dataout = sel_wire[0..0] & data_wire[939..939] # !(sel_wire[0..0]) & data_wire[931..931]; + l1_w3_n59_mux_dataout = sel_wire[0..0] & data_wire[955..955] # !(sel_wire[0..0]) & data_wire[947..947]; + l1_w3_n5_mux_dataout = sel_wire[0..0] & data_wire[91..91] # !(sel_wire[0..0]) & data_wire[83..83]; + l1_w3_n60_mux_dataout = sel_wire[0..0] & data_wire[971..971] # !(sel_wire[0..0]) & data_wire[963..963]; + l1_w3_n61_mux_dataout = sel_wire[0..0] & data_wire[987..987] # !(sel_wire[0..0]) & data_wire[979..979]; + l1_w3_n62_mux_dataout = sel_wire[0..0] & data_wire[1003..1003] # !(sel_wire[0..0]) & data_wire[995..995]; + l1_w3_n63_mux_dataout = sel_wire[0..0] & data_wire[1019..1019] # !(sel_wire[0..0]) & data_wire[1011..1011]; + l1_w3_n64_mux_dataout = sel_wire[0..0] & data_wire[1035..1035] # !(sel_wire[0..0]) & data_wire[1027..1027]; + l1_w3_n65_mux_dataout = sel_wire[0..0] & data_wire[1051..1051] # !(sel_wire[0..0]) & data_wire[1043..1043]; + l1_w3_n66_mux_dataout = sel_wire[0..0] & data_wire[1067..1067] # !(sel_wire[0..0]) & data_wire[1059..1059]; + l1_w3_n67_mux_dataout = sel_wire[0..0] & data_wire[1083..1083] # !(sel_wire[0..0]) & data_wire[1075..1075]; + l1_w3_n68_mux_dataout = sel_wire[0..0] & data_wire[1099..1099] # !(sel_wire[0..0]) & data_wire[1091..1091]; + l1_w3_n69_mux_dataout = sel_wire[0..0] & data_wire[1115..1115] # !(sel_wire[0..0]) & data_wire[1107..1107]; + l1_w3_n6_mux_dataout = sel_wire[0..0] & data_wire[107..107] # !(sel_wire[0..0]) & data_wire[99..99]; + l1_w3_n70_mux_dataout = sel_wire[0..0] & data_wire[1131..1131] # !(sel_wire[0..0]) & data_wire[1123..1123]; + l1_w3_n71_mux_dataout = sel_wire[0..0] & data_wire[1147..1147] # !(sel_wire[0..0]) & data_wire[1139..1139]; + l1_w3_n72_mux_dataout = sel_wire[0..0] & data_wire[1163..1163] # !(sel_wire[0..0]) & data_wire[1155..1155]; + l1_w3_n73_mux_dataout = sel_wire[0..0] & data_wire[1179..1179] # !(sel_wire[0..0]) & data_wire[1171..1171]; + l1_w3_n74_mux_dataout = sel_wire[0..0] & data_wire[1195..1195] # !(sel_wire[0..0]) & data_wire[1187..1187]; + l1_w3_n75_mux_dataout = sel_wire[0..0] & data_wire[1211..1211] # !(sel_wire[0..0]) & data_wire[1203..1203]; + l1_w3_n76_mux_dataout = sel_wire[0..0] & data_wire[1227..1227] # !(sel_wire[0..0]) & data_wire[1219..1219]; + l1_w3_n77_mux_dataout = sel_wire[0..0] & data_wire[1243..1243] # !(sel_wire[0..0]) & data_wire[1235..1235]; + l1_w3_n78_mux_dataout = sel_wire[0..0] & data_wire[1259..1259] # !(sel_wire[0..0]) & data_wire[1251..1251]; + l1_w3_n79_mux_dataout = sel_wire[0..0] & data_wire[1275..1275] # !(sel_wire[0..0]) & data_wire[1267..1267]; + l1_w3_n7_mux_dataout = sel_wire[0..0] & data_wire[123..123] # !(sel_wire[0..0]) & data_wire[115..115]; + l1_w3_n80_mux_dataout = sel_wire[0..0] & data_wire[1291..1291] # !(sel_wire[0..0]) & data_wire[1283..1283]; + l1_w3_n81_mux_dataout = sel_wire[0..0] & data_wire[1307..1307] # !(sel_wire[0..0]) & data_wire[1299..1299]; + l1_w3_n82_mux_dataout = sel_wire[0..0] & data_wire[1323..1323] # !(sel_wire[0..0]) & data_wire[1315..1315]; + l1_w3_n83_mux_dataout = sel_wire[0..0] & data_wire[1339..1339] # !(sel_wire[0..0]) & data_wire[1331..1331]; + l1_w3_n84_mux_dataout = sel_wire[0..0] & data_wire[1355..1355] # !(sel_wire[0..0]) & data_wire[1347..1347]; + l1_w3_n85_mux_dataout = sel_wire[0..0] & data_wire[1371..1371] # !(sel_wire[0..0]) & data_wire[1363..1363]; + l1_w3_n86_mux_dataout = sel_wire[0..0] & data_wire[1387..1387] # !(sel_wire[0..0]) & data_wire[1379..1379]; + l1_w3_n87_mux_dataout = sel_wire[0..0] & data_wire[1403..1403] # !(sel_wire[0..0]) & data_wire[1395..1395]; + l1_w3_n88_mux_dataout = sel_wire[0..0] & data_wire[1419..1419] # !(sel_wire[0..0]) & data_wire[1411..1411]; + l1_w3_n89_mux_dataout = sel_wire[0..0] & data_wire[1435..1435] # !(sel_wire[0..0]) & data_wire[1427..1427]; + l1_w3_n8_mux_dataout = sel_wire[0..0] & data_wire[139..139] # !(sel_wire[0..0]) & data_wire[131..131]; + l1_w3_n90_mux_dataout = sel_wire[0..0] & data_wire[1451..1451] # !(sel_wire[0..0]) & data_wire[1443..1443]; + l1_w3_n91_mux_dataout = sel_wire[0..0] & data_wire[1467..1467] # !(sel_wire[0..0]) & data_wire[1459..1459]; + l1_w3_n92_mux_dataout = sel_wire[0..0] & data_wire[1483..1483] # !(sel_wire[0..0]) & data_wire[1475..1475]; + l1_w3_n93_mux_dataout = sel_wire[0..0] & data_wire[1499..1499] # !(sel_wire[0..0]) & data_wire[1491..1491]; + l1_w3_n94_mux_dataout = sel_wire[0..0] & data_wire[1515..1515] # !(sel_wire[0..0]) & data_wire[1507..1507]; + l1_w3_n95_mux_dataout = sel_wire[0..0] & data_wire[1531..1531] # !(sel_wire[0..0]) & data_wire[1523..1523]; + l1_w3_n96_mux_dataout = sel_wire[0..0] & data_wire[1547..1547] # !(sel_wire[0..0]) & data_wire[1539..1539]; + l1_w3_n97_mux_dataout = sel_wire[0..0] & data_wire[1563..1563] # !(sel_wire[0..0]) & data_wire[1555..1555]; + l1_w3_n98_mux_dataout = sel_wire[0..0] & data_wire[1579..1579] # !(sel_wire[0..0]) & data_wire[1571..1571]; + l1_w3_n99_mux_dataout = sel_wire[0..0] & data_wire[1595..1595] # !(sel_wire[0..0]) & data_wire[1587..1587]; + l1_w3_n9_mux_dataout = sel_wire[0..0] & data_wire[155..155] # !(sel_wire[0..0]) & data_wire[147..147]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w4_n100_mux_dataout = sel_wire[0..0] & data_wire[1612..1612] # !(sel_wire[0..0]) & data_wire[1604..1604]; + l1_w4_n101_mux_dataout = sel_wire[0..0] & data_wire[1628..1628] # !(sel_wire[0..0]) & data_wire[1620..1620]; + l1_w4_n102_mux_dataout = sel_wire[0..0] & data_wire[1644..1644] # !(sel_wire[0..0]) & data_wire[1636..1636]; + l1_w4_n103_mux_dataout = sel_wire[0..0] & data_wire[1660..1660] # !(sel_wire[0..0]) & data_wire[1652..1652]; + l1_w4_n104_mux_dataout = sel_wire[0..0] & data_wire[1676..1676] # !(sel_wire[0..0]) & data_wire[1668..1668]; + l1_w4_n105_mux_dataout = sel_wire[0..0] & data_wire[1692..1692] # !(sel_wire[0..0]) & data_wire[1684..1684]; + l1_w4_n106_mux_dataout = sel_wire[0..0] & data_wire[1708..1708] # !(sel_wire[0..0]) & data_wire[1700..1700]; + l1_w4_n107_mux_dataout = sel_wire[0..0] & data_wire[1724..1724] # !(sel_wire[0..0]) & data_wire[1716..1716]; + l1_w4_n108_mux_dataout = sel_wire[0..0] & data_wire[1740..1740] # !(sel_wire[0..0]) & data_wire[1732..1732]; + l1_w4_n109_mux_dataout = sel_wire[0..0] & data_wire[1756..1756] # !(sel_wire[0..0]) & data_wire[1748..1748]; + l1_w4_n10_mux_dataout = sel_wire[0..0] & data_wire[172..172] # !(sel_wire[0..0]) & data_wire[164..164]; + l1_w4_n110_mux_dataout = sel_wire[0..0] & data_wire[1772..1772] # !(sel_wire[0..0]) & data_wire[1764..1764]; + l1_w4_n111_mux_dataout = sel_wire[0..0] & data_wire[1788..1788] # !(sel_wire[0..0]) & data_wire[1780..1780]; + l1_w4_n112_mux_dataout = sel_wire[0..0] & data_wire[1804..1804] # !(sel_wire[0..0]) & data_wire[1796..1796]; + l1_w4_n113_mux_dataout = sel_wire[0..0] & data_wire[1820..1820] # !(sel_wire[0..0]) & data_wire[1812..1812]; + l1_w4_n114_mux_dataout = sel_wire[0..0] & data_wire[1836..1836] # !(sel_wire[0..0]) & data_wire[1828..1828]; + l1_w4_n115_mux_dataout = sel_wire[0..0] & data_wire[1852..1852] # !(sel_wire[0..0]) & data_wire[1844..1844]; + l1_w4_n116_mux_dataout = sel_wire[0..0] & data_wire[1868..1868] # !(sel_wire[0..0]) & data_wire[1860..1860]; + l1_w4_n117_mux_dataout = sel_wire[0..0] & data_wire[1884..1884] # !(sel_wire[0..0]) & data_wire[1876..1876]; + l1_w4_n118_mux_dataout = sel_wire[0..0] & data_wire[1900..1900] # !(sel_wire[0..0]) & data_wire[1892..1892]; + l1_w4_n119_mux_dataout = sel_wire[0..0] & data_wire[1916..1916] # !(sel_wire[0..0]) & data_wire[1908..1908]; + l1_w4_n11_mux_dataout = sel_wire[0..0] & data_wire[188..188] # !(sel_wire[0..0]) & data_wire[180..180]; + l1_w4_n120_mux_dataout = sel_wire[0..0] & data_wire[1932..1932] # !(sel_wire[0..0]) & data_wire[1924..1924]; + l1_w4_n121_mux_dataout = sel_wire[0..0] & data_wire[1948..1948] # !(sel_wire[0..0]) & data_wire[1940..1940]; + l1_w4_n122_mux_dataout = sel_wire[0..0] & data_wire[1964..1964] # !(sel_wire[0..0]) & data_wire[1956..1956]; + l1_w4_n123_mux_dataout = sel_wire[0..0] & data_wire[1980..1980] # !(sel_wire[0..0]) & data_wire[1972..1972]; + l1_w4_n124_mux_dataout = sel_wire[0..0] & data_wire[1996..1996] # !(sel_wire[0..0]) & data_wire[1988..1988]; + l1_w4_n125_mux_dataout = sel_wire[0..0] & data_wire[2012..2012] # !(sel_wire[0..0]) & data_wire[2004..2004]; + l1_w4_n126_mux_dataout = sel_wire[0..0] & data_wire[2028..2028] # !(sel_wire[0..0]) & data_wire[2020..2020]; + l1_w4_n127_mux_dataout = sel_wire[0..0] & data_wire[2044..2044] # !(sel_wire[0..0]) & data_wire[2036..2036]; + l1_w4_n12_mux_dataout = sel_wire[0..0] & data_wire[204..204] # !(sel_wire[0..0]) & data_wire[196..196]; + l1_w4_n13_mux_dataout = sel_wire[0..0] & data_wire[220..220] # !(sel_wire[0..0]) & data_wire[212..212]; + l1_w4_n14_mux_dataout = sel_wire[0..0] & data_wire[236..236] # !(sel_wire[0..0]) & data_wire[228..228]; + l1_w4_n15_mux_dataout = sel_wire[0..0] & data_wire[252..252] # !(sel_wire[0..0]) & data_wire[244..244]; + l1_w4_n16_mux_dataout = sel_wire[0..0] & data_wire[268..268] # !(sel_wire[0..0]) & data_wire[260..260]; + l1_w4_n17_mux_dataout = sel_wire[0..0] & data_wire[284..284] # !(sel_wire[0..0]) & data_wire[276..276]; + l1_w4_n18_mux_dataout = sel_wire[0..0] & data_wire[300..300] # !(sel_wire[0..0]) & data_wire[292..292]; + l1_w4_n19_mux_dataout = sel_wire[0..0] & data_wire[316..316] # !(sel_wire[0..0]) & data_wire[308..308]; + l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20]; + l1_w4_n20_mux_dataout = sel_wire[0..0] & data_wire[332..332] # !(sel_wire[0..0]) & data_wire[324..324]; + l1_w4_n21_mux_dataout = sel_wire[0..0] & data_wire[348..348] # !(sel_wire[0..0]) & data_wire[340..340]; + l1_w4_n22_mux_dataout = sel_wire[0..0] & data_wire[364..364] # !(sel_wire[0..0]) & data_wire[356..356]; + l1_w4_n23_mux_dataout = sel_wire[0..0] & data_wire[380..380] # !(sel_wire[0..0]) & data_wire[372..372]; + l1_w4_n24_mux_dataout = sel_wire[0..0] & data_wire[396..396] # !(sel_wire[0..0]) & data_wire[388..388]; + l1_w4_n25_mux_dataout = sel_wire[0..0] & data_wire[412..412] # !(sel_wire[0..0]) & data_wire[404..404]; + l1_w4_n26_mux_dataout = sel_wire[0..0] & data_wire[428..428] # !(sel_wire[0..0]) & data_wire[420..420]; + l1_w4_n27_mux_dataout = sel_wire[0..0] & data_wire[444..444] # !(sel_wire[0..0]) & data_wire[436..436]; + l1_w4_n28_mux_dataout = sel_wire[0..0] & data_wire[460..460] # !(sel_wire[0..0]) & data_wire[452..452]; + l1_w4_n29_mux_dataout = sel_wire[0..0] & data_wire[476..476] # !(sel_wire[0..0]) & data_wire[468..468]; + l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36]; + l1_w4_n30_mux_dataout = sel_wire[0..0] & data_wire[492..492] # !(sel_wire[0..0]) & data_wire[484..484]; + l1_w4_n31_mux_dataout = sel_wire[0..0] & data_wire[508..508] # !(sel_wire[0..0]) & data_wire[500..500]; + l1_w4_n32_mux_dataout = sel_wire[0..0] & data_wire[524..524] # !(sel_wire[0..0]) & data_wire[516..516]; + l1_w4_n33_mux_dataout = sel_wire[0..0] & data_wire[540..540] # !(sel_wire[0..0]) & data_wire[532..532]; + l1_w4_n34_mux_dataout = sel_wire[0..0] & data_wire[556..556] # !(sel_wire[0..0]) & data_wire[548..548]; + l1_w4_n35_mux_dataout = sel_wire[0..0] & data_wire[572..572] # !(sel_wire[0..0]) & data_wire[564..564]; + l1_w4_n36_mux_dataout = sel_wire[0..0] & data_wire[588..588] # !(sel_wire[0..0]) & data_wire[580..580]; + l1_w4_n37_mux_dataout = sel_wire[0..0] & data_wire[604..604] # !(sel_wire[0..0]) & data_wire[596..596]; + l1_w4_n38_mux_dataout = sel_wire[0..0] & data_wire[620..620] # !(sel_wire[0..0]) & data_wire[612..612]; + l1_w4_n39_mux_dataout = sel_wire[0..0] & data_wire[636..636] # !(sel_wire[0..0]) & data_wire[628..628]; + l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52]; + l1_w4_n40_mux_dataout = sel_wire[0..0] & data_wire[652..652] # !(sel_wire[0..0]) & data_wire[644..644]; + l1_w4_n41_mux_dataout = sel_wire[0..0] & data_wire[668..668] # !(sel_wire[0..0]) & data_wire[660..660]; + l1_w4_n42_mux_dataout = sel_wire[0..0] & data_wire[684..684] # !(sel_wire[0..0]) & data_wire[676..676]; + l1_w4_n43_mux_dataout = sel_wire[0..0] & data_wire[700..700] # !(sel_wire[0..0]) & data_wire[692..692]; + l1_w4_n44_mux_dataout = sel_wire[0..0] & data_wire[716..716] # !(sel_wire[0..0]) & data_wire[708..708]; + l1_w4_n45_mux_dataout = sel_wire[0..0] & data_wire[732..732] # !(sel_wire[0..0]) & data_wire[724..724]; + l1_w4_n46_mux_dataout = sel_wire[0..0] & data_wire[748..748] # !(sel_wire[0..0]) & data_wire[740..740]; + l1_w4_n47_mux_dataout = sel_wire[0..0] & data_wire[764..764] # !(sel_wire[0..0]) & data_wire[756..756]; + l1_w4_n48_mux_dataout = sel_wire[0..0] & data_wire[780..780] # !(sel_wire[0..0]) & data_wire[772..772]; + l1_w4_n49_mux_dataout = sel_wire[0..0] & data_wire[796..796] # !(sel_wire[0..0]) & data_wire[788..788]; + l1_w4_n4_mux_dataout = sel_wire[0..0] & data_wire[76..76] # !(sel_wire[0..0]) & data_wire[68..68]; + l1_w4_n50_mux_dataout = sel_wire[0..0] & data_wire[812..812] # !(sel_wire[0..0]) & data_wire[804..804]; + l1_w4_n51_mux_dataout = sel_wire[0..0] & data_wire[828..828] # !(sel_wire[0..0]) & data_wire[820..820]; + l1_w4_n52_mux_dataout = sel_wire[0..0] & data_wire[844..844] # !(sel_wire[0..0]) & data_wire[836..836]; + l1_w4_n53_mux_dataout = sel_wire[0..0] & data_wire[860..860] # !(sel_wire[0..0]) & data_wire[852..852]; + l1_w4_n54_mux_dataout = sel_wire[0..0] & data_wire[876..876] # !(sel_wire[0..0]) & data_wire[868..868]; + l1_w4_n55_mux_dataout = sel_wire[0..0] & data_wire[892..892] # !(sel_wire[0..0]) & data_wire[884..884]; + l1_w4_n56_mux_dataout = sel_wire[0..0] & data_wire[908..908] # !(sel_wire[0..0]) & data_wire[900..900]; + l1_w4_n57_mux_dataout = sel_wire[0..0] & data_wire[924..924] # !(sel_wire[0..0]) & data_wire[916..916]; + l1_w4_n58_mux_dataout = sel_wire[0..0] & data_wire[940..940] # !(sel_wire[0..0]) & data_wire[932..932]; + l1_w4_n59_mux_dataout = sel_wire[0..0] & data_wire[956..956] # !(sel_wire[0..0]) & data_wire[948..948]; + l1_w4_n5_mux_dataout = sel_wire[0..0] & data_wire[92..92] # !(sel_wire[0..0]) & data_wire[84..84]; + l1_w4_n60_mux_dataout = sel_wire[0..0] & data_wire[972..972] # !(sel_wire[0..0]) & data_wire[964..964]; + l1_w4_n61_mux_dataout = sel_wire[0..0] & data_wire[988..988] # !(sel_wire[0..0]) & data_wire[980..980]; + l1_w4_n62_mux_dataout = sel_wire[0..0] & data_wire[1004..1004] # !(sel_wire[0..0]) & data_wire[996..996]; + l1_w4_n63_mux_dataout = sel_wire[0..0] & data_wire[1020..1020] # !(sel_wire[0..0]) & data_wire[1012..1012]; + l1_w4_n64_mux_dataout = sel_wire[0..0] & data_wire[1036..1036] # !(sel_wire[0..0]) & data_wire[1028..1028]; + l1_w4_n65_mux_dataout = sel_wire[0..0] & data_wire[1052..1052] # !(sel_wire[0..0]) & data_wire[1044..1044]; + l1_w4_n66_mux_dataout = sel_wire[0..0] & data_wire[1068..1068] # !(sel_wire[0..0]) & data_wire[1060..1060]; + l1_w4_n67_mux_dataout = sel_wire[0..0] & data_wire[1084..1084] # !(sel_wire[0..0]) & data_wire[1076..1076]; + l1_w4_n68_mux_dataout = sel_wire[0..0] & data_wire[1100..1100] # !(sel_wire[0..0]) & data_wire[1092..1092]; + l1_w4_n69_mux_dataout = sel_wire[0..0] & data_wire[1116..1116] # !(sel_wire[0..0]) & data_wire[1108..1108]; + l1_w4_n6_mux_dataout = sel_wire[0..0] & data_wire[108..108] # !(sel_wire[0..0]) & data_wire[100..100]; + l1_w4_n70_mux_dataout = sel_wire[0..0] & data_wire[1132..1132] # !(sel_wire[0..0]) & data_wire[1124..1124]; + l1_w4_n71_mux_dataout = sel_wire[0..0] & data_wire[1148..1148] # !(sel_wire[0..0]) & data_wire[1140..1140]; + l1_w4_n72_mux_dataout = sel_wire[0..0] & data_wire[1164..1164] # !(sel_wire[0..0]) & data_wire[1156..1156]; + l1_w4_n73_mux_dataout = sel_wire[0..0] & data_wire[1180..1180] # !(sel_wire[0..0]) & data_wire[1172..1172]; + l1_w4_n74_mux_dataout = sel_wire[0..0] & data_wire[1196..1196] # !(sel_wire[0..0]) & data_wire[1188..1188]; + l1_w4_n75_mux_dataout = sel_wire[0..0] & data_wire[1212..1212] # !(sel_wire[0..0]) & data_wire[1204..1204]; + l1_w4_n76_mux_dataout = sel_wire[0..0] & data_wire[1228..1228] # !(sel_wire[0..0]) & data_wire[1220..1220]; + l1_w4_n77_mux_dataout = sel_wire[0..0] & data_wire[1244..1244] # !(sel_wire[0..0]) & data_wire[1236..1236]; + l1_w4_n78_mux_dataout = sel_wire[0..0] & data_wire[1260..1260] # !(sel_wire[0..0]) & data_wire[1252..1252]; + l1_w4_n79_mux_dataout = sel_wire[0..0] & data_wire[1276..1276] # !(sel_wire[0..0]) & data_wire[1268..1268]; + l1_w4_n7_mux_dataout = sel_wire[0..0] & data_wire[124..124] # !(sel_wire[0..0]) & data_wire[116..116]; + l1_w4_n80_mux_dataout = sel_wire[0..0] & data_wire[1292..1292] # !(sel_wire[0..0]) & data_wire[1284..1284]; + l1_w4_n81_mux_dataout = sel_wire[0..0] & data_wire[1308..1308] # !(sel_wire[0..0]) & data_wire[1300..1300]; + l1_w4_n82_mux_dataout = sel_wire[0..0] & data_wire[1324..1324] # !(sel_wire[0..0]) & data_wire[1316..1316]; + l1_w4_n83_mux_dataout = sel_wire[0..0] & data_wire[1340..1340] # !(sel_wire[0..0]) & data_wire[1332..1332]; + l1_w4_n84_mux_dataout = sel_wire[0..0] & data_wire[1356..1356] # !(sel_wire[0..0]) & data_wire[1348..1348]; + l1_w4_n85_mux_dataout = sel_wire[0..0] & data_wire[1372..1372] # !(sel_wire[0..0]) & data_wire[1364..1364]; + l1_w4_n86_mux_dataout = sel_wire[0..0] & data_wire[1388..1388] # !(sel_wire[0..0]) & data_wire[1380..1380]; + l1_w4_n87_mux_dataout = sel_wire[0..0] & data_wire[1404..1404] # !(sel_wire[0..0]) & data_wire[1396..1396]; + l1_w4_n88_mux_dataout = sel_wire[0..0] & data_wire[1420..1420] # !(sel_wire[0..0]) & data_wire[1412..1412]; + l1_w4_n89_mux_dataout = sel_wire[0..0] & data_wire[1436..1436] # !(sel_wire[0..0]) & data_wire[1428..1428]; + l1_w4_n8_mux_dataout = sel_wire[0..0] & data_wire[140..140] # !(sel_wire[0..0]) & data_wire[132..132]; + l1_w4_n90_mux_dataout = sel_wire[0..0] & data_wire[1452..1452] # !(sel_wire[0..0]) & data_wire[1444..1444]; + l1_w4_n91_mux_dataout = sel_wire[0..0] & data_wire[1468..1468] # !(sel_wire[0..0]) & data_wire[1460..1460]; + l1_w4_n92_mux_dataout = sel_wire[0..0] & data_wire[1484..1484] # !(sel_wire[0..0]) & data_wire[1476..1476]; + l1_w4_n93_mux_dataout = sel_wire[0..0] & data_wire[1500..1500] # !(sel_wire[0..0]) & data_wire[1492..1492]; + l1_w4_n94_mux_dataout = sel_wire[0..0] & data_wire[1516..1516] # !(sel_wire[0..0]) & data_wire[1508..1508]; + l1_w4_n95_mux_dataout = sel_wire[0..0] & data_wire[1532..1532] # !(sel_wire[0..0]) & data_wire[1524..1524]; + l1_w4_n96_mux_dataout = sel_wire[0..0] & data_wire[1548..1548] # !(sel_wire[0..0]) & data_wire[1540..1540]; + l1_w4_n97_mux_dataout = sel_wire[0..0] & data_wire[1564..1564] # !(sel_wire[0..0]) & data_wire[1556..1556]; + l1_w4_n98_mux_dataout = sel_wire[0..0] & data_wire[1580..1580] # !(sel_wire[0..0]) & data_wire[1572..1572]; + l1_w4_n99_mux_dataout = sel_wire[0..0] & data_wire[1596..1596] # !(sel_wire[0..0]) & data_wire[1588..1588]; + l1_w4_n9_mux_dataout = sel_wire[0..0] & data_wire[156..156] # !(sel_wire[0..0]) & data_wire[148..148]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w5_n100_mux_dataout = sel_wire[0..0] & data_wire[1613..1613] # !(sel_wire[0..0]) & data_wire[1605..1605]; + l1_w5_n101_mux_dataout = sel_wire[0..0] & data_wire[1629..1629] # !(sel_wire[0..0]) & data_wire[1621..1621]; + l1_w5_n102_mux_dataout = sel_wire[0..0] & data_wire[1645..1645] # !(sel_wire[0..0]) & data_wire[1637..1637]; + l1_w5_n103_mux_dataout = sel_wire[0..0] & data_wire[1661..1661] # !(sel_wire[0..0]) & data_wire[1653..1653]; + l1_w5_n104_mux_dataout = sel_wire[0..0] & data_wire[1677..1677] # !(sel_wire[0..0]) & data_wire[1669..1669]; + l1_w5_n105_mux_dataout = sel_wire[0..0] & data_wire[1693..1693] # !(sel_wire[0..0]) & data_wire[1685..1685]; + l1_w5_n106_mux_dataout = sel_wire[0..0] & data_wire[1709..1709] # !(sel_wire[0..0]) & data_wire[1701..1701]; + l1_w5_n107_mux_dataout = sel_wire[0..0] & data_wire[1725..1725] # !(sel_wire[0..0]) & data_wire[1717..1717]; + l1_w5_n108_mux_dataout = sel_wire[0..0] & data_wire[1741..1741] # !(sel_wire[0..0]) & data_wire[1733..1733]; + l1_w5_n109_mux_dataout = sel_wire[0..0] & data_wire[1757..1757] # !(sel_wire[0..0]) & data_wire[1749..1749]; + l1_w5_n10_mux_dataout = sel_wire[0..0] & data_wire[173..173] # !(sel_wire[0..0]) & data_wire[165..165]; + l1_w5_n110_mux_dataout = sel_wire[0..0] & data_wire[1773..1773] # !(sel_wire[0..0]) & data_wire[1765..1765]; + l1_w5_n111_mux_dataout = sel_wire[0..0] & data_wire[1789..1789] # !(sel_wire[0..0]) & data_wire[1781..1781]; + l1_w5_n112_mux_dataout = sel_wire[0..0] & data_wire[1805..1805] # !(sel_wire[0..0]) & data_wire[1797..1797]; + l1_w5_n113_mux_dataout = sel_wire[0..0] & data_wire[1821..1821] # !(sel_wire[0..0]) & data_wire[1813..1813]; + l1_w5_n114_mux_dataout = sel_wire[0..0] & data_wire[1837..1837] # !(sel_wire[0..0]) & data_wire[1829..1829]; + l1_w5_n115_mux_dataout = sel_wire[0..0] & data_wire[1853..1853] # !(sel_wire[0..0]) & data_wire[1845..1845]; + l1_w5_n116_mux_dataout = sel_wire[0..0] & data_wire[1869..1869] # !(sel_wire[0..0]) & data_wire[1861..1861]; + l1_w5_n117_mux_dataout = sel_wire[0..0] & data_wire[1885..1885] # !(sel_wire[0..0]) & data_wire[1877..1877]; + l1_w5_n118_mux_dataout = sel_wire[0..0] & data_wire[1901..1901] # !(sel_wire[0..0]) & data_wire[1893..1893]; + l1_w5_n119_mux_dataout = sel_wire[0..0] & data_wire[1917..1917] # !(sel_wire[0..0]) & data_wire[1909..1909]; + l1_w5_n11_mux_dataout = sel_wire[0..0] & data_wire[189..189] # !(sel_wire[0..0]) & data_wire[181..181]; + l1_w5_n120_mux_dataout = sel_wire[0..0] & data_wire[1933..1933] # !(sel_wire[0..0]) & data_wire[1925..1925]; + l1_w5_n121_mux_dataout = sel_wire[0..0] & data_wire[1949..1949] # !(sel_wire[0..0]) & data_wire[1941..1941]; + l1_w5_n122_mux_dataout = sel_wire[0..0] & data_wire[1965..1965] # !(sel_wire[0..0]) & data_wire[1957..1957]; + l1_w5_n123_mux_dataout = sel_wire[0..0] & data_wire[1981..1981] # !(sel_wire[0..0]) & data_wire[1973..1973]; + l1_w5_n124_mux_dataout = sel_wire[0..0] & data_wire[1997..1997] # !(sel_wire[0..0]) & data_wire[1989..1989]; + l1_w5_n125_mux_dataout = sel_wire[0..0] & data_wire[2013..2013] # !(sel_wire[0..0]) & data_wire[2005..2005]; + l1_w5_n126_mux_dataout = sel_wire[0..0] & data_wire[2029..2029] # !(sel_wire[0..0]) & data_wire[2021..2021]; + l1_w5_n127_mux_dataout = sel_wire[0..0] & data_wire[2045..2045] # !(sel_wire[0..0]) & data_wire[2037..2037]; + l1_w5_n12_mux_dataout = sel_wire[0..0] & data_wire[205..205] # !(sel_wire[0..0]) & data_wire[197..197]; + l1_w5_n13_mux_dataout = sel_wire[0..0] & data_wire[221..221] # !(sel_wire[0..0]) & data_wire[213..213]; + l1_w5_n14_mux_dataout = sel_wire[0..0] & data_wire[237..237] # !(sel_wire[0..0]) & data_wire[229..229]; + l1_w5_n15_mux_dataout = sel_wire[0..0] & data_wire[253..253] # !(sel_wire[0..0]) & data_wire[245..245]; + l1_w5_n16_mux_dataout = sel_wire[0..0] & data_wire[269..269] # !(sel_wire[0..0]) & data_wire[261..261]; + l1_w5_n17_mux_dataout = sel_wire[0..0] & data_wire[285..285] # !(sel_wire[0..0]) & data_wire[277..277]; + l1_w5_n18_mux_dataout = sel_wire[0..0] & data_wire[301..301] # !(sel_wire[0..0]) & data_wire[293..293]; + l1_w5_n19_mux_dataout = sel_wire[0..0] & data_wire[317..317] # !(sel_wire[0..0]) & data_wire[309..309]; + l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21]; + l1_w5_n20_mux_dataout = sel_wire[0..0] & data_wire[333..333] # !(sel_wire[0..0]) & data_wire[325..325]; + l1_w5_n21_mux_dataout = sel_wire[0..0] & data_wire[349..349] # !(sel_wire[0..0]) & data_wire[341..341]; + l1_w5_n22_mux_dataout = sel_wire[0..0] & data_wire[365..365] # !(sel_wire[0..0]) & data_wire[357..357]; + l1_w5_n23_mux_dataout = sel_wire[0..0] & data_wire[381..381] # !(sel_wire[0..0]) & data_wire[373..373]; + l1_w5_n24_mux_dataout = sel_wire[0..0] & data_wire[397..397] # !(sel_wire[0..0]) & data_wire[389..389]; + l1_w5_n25_mux_dataout = sel_wire[0..0] & data_wire[413..413] # !(sel_wire[0..0]) & data_wire[405..405]; + l1_w5_n26_mux_dataout = sel_wire[0..0] & data_wire[429..429] # !(sel_wire[0..0]) & data_wire[421..421]; + l1_w5_n27_mux_dataout = sel_wire[0..0] & data_wire[445..445] # !(sel_wire[0..0]) & data_wire[437..437]; + l1_w5_n28_mux_dataout = sel_wire[0..0] & data_wire[461..461] # !(sel_wire[0..0]) & data_wire[453..453]; + l1_w5_n29_mux_dataout = sel_wire[0..0] & data_wire[477..477] # !(sel_wire[0..0]) & data_wire[469..469]; + l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37]; + l1_w5_n30_mux_dataout = sel_wire[0..0] & data_wire[493..493] # !(sel_wire[0..0]) & data_wire[485..485]; + l1_w5_n31_mux_dataout = sel_wire[0..0] & data_wire[509..509] # !(sel_wire[0..0]) & data_wire[501..501]; + l1_w5_n32_mux_dataout = sel_wire[0..0] & data_wire[525..525] # !(sel_wire[0..0]) & data_wire[517..517]; + l1_w5_n33_mux_dataout = sel_wire[0..0] & data_wire[541..541] # !(sel_wire[0..0]) & data_wire[533..533]; + l1_w5_n34_mux_dataout = sel_wire[0..0] & data_wire[557..557] # !(sel_wire[0..0]) & data_wire[549..549]; + l1_w5_n35_mux_dataout = sel_wire[0..0] & data_wire[573..573] # !(sel_wire[0..0]) & data_wire[565..565]; + l1_w5_n36_mux_dataout = sel_wire[0..0] & data_wire[589..589] # !(sel_wire[0..0]) & data_wire[581..581]; + l1_w5_n37_mux_dataout = sel_wire[0..0] & data_wire[605..605] # !(sel_wire[0..0]) & data_wire[597..597]; + l1_w5_n38_mux_dataout = sel_wire[0..0] & data_wire[621..621] # !(sel_wire[0..0]) & data_wire[613..613]; + l1_w5_n39_mux_dataout = sel_wire[0..0] & data_wire[637..637] # !(sel_wire[0..0]) & data_wire[629..629]; + l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53]; + l1_w5_n40_mux_dataout = sel_wire[0..0] & data_wire[653..653] # !(sel_wire[0..0]) & data_wire[645..645]; + l1_w5_n41_mux_dataout = sel_wire[0..0] & data_wire[669..669] # !(sel_wire[0..0]) & data_wire[661..661]; + l1_w5_n42_mux_dataout = sel_wire[0..0] & data_wire[685..685] # !(sel_wire[0..0]) & data_wire[677..677]; + l1_w5_n43_mux_dataout = sel_wire[0..0] & data_wire[701..701] # !(sel_wire[0..0]) & data_wire[693..693]; + l1_w5_n44_mux_dataout = sel_wire[0..0] & data_wire[717..717] # !(sel_wire[0..0]) & data_wire[709..709]; + l1_w5_n45_mux_dataout = sel_wire[0..0] & data_wire[733..733] # !(sel_wire[0..0]) & data_wire[725..725]; + l1_w5_n46_mux_dataout = sel_wire[0..0] & data_wire[749..749] # !(sel_wire[0..0]) & data_wire[741..741]; + l1_w5_n47_mux_dataout = sel_wire[0..0] & data_wire[765..765] # !(sel_wire[0..0]) & data_wire[757..757]; + l1_w5_n48_mux_dataout = sel_wire[0..0] & data_wire[781..781] # !(sel_wire[0..0]) & data_wire[773..773]; + l1_w5_n49_mux_dataout = sel_wire[0..0] & data_wire[797..797] # !(sel_wire[0..0]) & data_wire[789..789]; + l1_w5_n4_mux_dataout = sel_wire[0..0] & data_wire[77..77] # !(sel_wire[0..0]) & data_wire[69..69]; + l1_w5_n50_mux_dataout = sel_wire[0..0] & data_wire[813..813] # !(sel_wire[0..0]) & data_wire[805..805]; + l1_w5_n51_mux_dataout = sel_wire[0..0] & data_wire[829..829] # !(sel_wire[0..0]) & data_wire[821..821]; + l1_w5_n52_mux_dataout = sel_wire[0..0] & data_wire[845..845] # !(sel_wire[0..0]) & data_wire[837..837]; + l1_w5_n53_mux_dataout = sel_wire[0..0] & data_wire[861..861] # !(sel_wire[0..0]) & data_wire[853..853]; + l1_w5_n54_mux_dataout = sel_wire[0..0] & data_wire[877..877] # !(sel_wire[0..0]) & data_wire[869..869]; + l1_w5_n55_mux_dataout = sel_wire[0..0] & data_wire[893..893] # !(sel_wire[0..0]) & data_wire[885..885]; + l1_w5_n56_mux_dataout = sel_wire[0..0] & data_wire[909..909] # !(sel_wire[0..0]) & data_wire[901..901]; + l1_w5_n57_mux_dataout = sel_wire[0..0] & data_wire[925..925] # !(sel_wire[0..0]) & data_wire[917..917]; + l1_w5_n58_mux_dataout = sel_wire[0..0] & data_wire[941..941] # !(sel_wire[0..0]) & data_wire[933..933]; + l1_w5_n59_mux_dataout = sel_wire[0..0] & data_wire[957..957] # !(sel_wire[0..0]) & data_wire[949..949]; + l1_w5_n5_mux_dataout = sel_wire[0..0] & data_wire[93..93] # !(sel_wire[0..0]) & data_wire[85..85]; + l1_w5_n60_mux_dataout = sel_wire[0..0] & data_wire[973..973] # !(sel_wire[0..0]) & data_wire[965..965]; + l1_w5_n61_mux_dataout = sel_wire[0..0] & data_wire[989..989] # !(sel_wire[0..0]) & data_wire[981..981]; + l1_w5_n62_mux_dataout = sel_wire[0..0] & data_wire[1005..1005] # !(sel_wire[0..0]) & data_wire[997..997]; + l1_w5_n63_mux_dataout = sel_wire[0..0] & data_wire[1021..1021] # !(sel_wire[0..0]) & data_wire[1013..1013]; + l1_w5_n64_mux_dataout = sel_wire[0..0] & data_wire[1037..1037] # !(sel_wire[0..0]) & data_wire[1029..1029]; + l1_w5_n65_mux_dataout = sel_wire[0..0] & data_wire[1053..1053] # !(sel_wire[0..0]) & data_wire[1045..1045]; + l1_w5_n66_mux_dataout = sel_wire[0..0] & data_wire[1069..1069] # !(sel_wire[0..0]) & data_wire[1061..1061]; + l1_w5_n67_mux_dataout = sel_wire[0..0] & data_wire[1085..1085] # !(sel_wire[0..0]) & data_wire[1077..1077]; + l1_w5_n68_mux_dataout = sel_wire[0..0] & data_wire[1101..1101] # !(sel_wire[0..0]) & data_wire[1093..1093]; + l1_w5_n69_mux_dataout = sel_wire[0..0] & data_wire[1117..1117] # !(sel_wire[0..0]) & data_wire[1109..1109]; + l1_w5_n6_mux_dataout = sel_wire[0..0] & data_wire[109..109] # !(sel_wire[0..0]) & data_wire[101..101]; + l1_w5_n70_mux_dataout = sel_wire[0..0] & data_wire[1133..1133] # !(sel_wire[0..0]) & data_wire[1125..1125]; + l1_w5_n71_mux_dataout = sel_wire[0..0] & data_wire[1149..1149] # !(sel_wire[0..0]) & data_wire[1141..1141]; + l1_w5_n72_mux_dataout = sel_wire[0..0] & data_wire[1165..1165] # !(sel_wire[0..0]) & data_wire[1157..1157]; + l1_w5_n73_mux_dataout = sel_wire[0..0] & data_wire[1181..1181] # !(sel_wire[0..0]) & data_wire[1173..1173]; + l1_w5_n74_mux_dataout = sel_wire[0..0] & data_wire[1197..1197] # !(sel_wire[0..0]) & data_wire[1189..1189]; + l1_w5_n75_mux_dataout = sel_wire[0..0] & data_wire[1213..1213] # !(sel_wire[0..0]) & data_wire[1205..1205]; + l1_w5_n76_mux_dataout = sel_wire[0..0] & data_wire[1229..1229] # !(sel_wire[0..0]) & data_wire[1221..1221]; + l1_w5_n77_mux_dataout = sel_wire[0..0] & data_wire[1245..1245] # !(sel_wire[0..0]) & data_wire[1237..1237]; + l1_w5_n78_mux_dataout = sel_wire[0..0] & data_wire[1261..1261] # !(sel_wire[0..0]) & data_wire[1253..1253]; + l1_w5_n79_mux_dataout = sel_wire[0..0] & data_wire[1277..1277] # !(sel_wire[0..0]) & data_wire[1269..1269]; + l1_w5_n7_mux_dataout = sel_wire[0..0] & data_wire[125..125] # !(sel_wire[0..0]) & data_wire[117..117]; + l1_w5_n80_mux_dataout = sel_wire[0..0] & data_wire[1293..1293] # !(sel_wire[0..0]) & data_wire[1285..1285]; + l1_w5_n81_mux_dataout = sel_wire[0..0] & data_wire[1309..1309] # !(sel_wire[0..0]) & data_wire[1301..1301]; + l1_w5_n82_mux_dataout = sel_wire[0..0] & data_wire[1325..1325] # !(sel_wire[0..0]) & data_wire[1317..1317]; + l1_w5_n83_mux_dataout = sel_wire[0..0] & data_wire[1341..1341] # !(sel_wire[0..0]) & data_wire[1333..1333]; + l1_w5_n84_mux_dataout = sel_wire[0..0] & data_wire[1357..1357] # !(sel_wire[0..0]) & data_wire[1349..1349]; + l1_w5_n85_mux_dataout = sel_wire[0..0] & data_wire[1373..1373] # !(sel_wire[0..0]) & data_wire[1365..1365]; + l1_w5_n86_mux_dataout = sel_wire[0..0] & data_wire[1389..1389] # !(sel_wire[0..0]) & data_wire[1381..1381]; + l1_w5_n87_mux_dataout = sel_wire[0..0] & data_wire[1405..1405] # !(sel_wire[0..0]) & data_wire[1397..1397]; + l1_w5_n88_mux_dataout = sel_wire[0..0] & data_wire[1421..1421] # !(sel_wire[0..0]) & data_wire[1413..1413]; + l1_w5_n89_mux_dataout = sel_wire[0..0] & data_wire[1437..1437] # !(sel_wire[0..0]) & data_wire[1429..1429]; + l1_w5_n8_mux_dataout = sel_wire[0..0] & data_wire[141..141] # !(sel_wire[0..0]) & data_wire[133..133]; + l1_w5_n90_mux_dataout = sel_wire[0..0] & data_wire[1453..1453] # !(sel_wire[0..0]) & data_wire[1445..1445]; + l1_w5_n91_mux_dataout = sel_wire[0..0] & data_wire[1469..1469] # !(sel_wire[0..0]) & data_wire[1461..1461]; + l1_w5_n92_mux_dataout = sel_wire[0..0] & data_wire[1485..1485] # !(sel_wire[0..0]) & data_wire[1477..1477]; + l1_w5_n93_mux_dataout = sel_wire[0..0] & data_wire[1501..1501] # !(sel_wire[0..0]) & data_wire[1493..1493]; + l1_w5_n94_mux_dataout = sel_wire[0..0] & data_wire[1517..1517] # !(sel_wire[0..0]) & data_wire[1509..1509]; + l1_w5_n95_mux_dataout = sel_wire[0..0] & data_wire[1533..1533] # !(sel_wire[0..0]) & data_wire[1525..1525]; + l1_w5_n96_mux_dataout = sel_wire[0..0] & data_wire[1549..1549] # !(sel_wire[0..0]) & data_wire[1541..1541]; + l1_w5_n97_mux_dataout = sel_wire[0..0] & data_wire[1565..1565] # !(sel_wire[0..0]) & data_wire[1557..1557]; + l1_w5_n98_mux_dataout = sel_wire[0..0] & data_wire[1581..1581] # !(sel_wire[0..0]) & data_wire[1573..1573]; + l1_w5_n99_mux_dataout = sel_wire[0..0] & data_wire[1597..1597] # !(sel_wire[0..0]) & data_wire[1589..1589]; + l1_w5_n9_mux_dataout = sel_wire[0..0] & data_wire[157..157] # !(sel_wire[0..0]) & data_wire[149..149]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w6_n100_mux_dataout = sel_wire[0..0] & data_wire[1614..1614] # !(sel_wire[0..0]) & data_wire[1606..1606]; + l1_w6_n101_mux_dataout = sel_wire[0..0] & data_wire[1630..1630] # !(sel_wire[0..0]) & data_wire[1622..1622]; + l1_w6_n102_mux_dataout = sel_wire[0..0] & data_wire[1646..1646] # !(sel_wire[0..0]) & data_wire[1638..1638]; + l1_w6_n103_mux_dataout = sel_wire[0..0] & data_wire[1662..1662] # !(sel_wire[0..0]) & data_wire[1654..1654]; + l1_w6_n104_mux_dataout = sel_wire[0..0] & data_wire[1678..1678] # !(sel_wire[0..0]) & data_wire[1670..1670]; + l1_w6_n105_mux_dataout = sel_wire[0..0] & data_wire[1694..1694] # !(sel_wire[0..0]) & data_wire[1686..1686]; + l1_w6_n106_mux_dataout = sel_wire[0..0] & data_wire[1710..1710] # !(sel_wire[0..0]) & data_wire[1702..1702]; + l1_w6_n107_mux_dataout = sel_wire[0..0] & data_wire[1726..1726] # !(sel_wire[0..0]) & data_wire[1718..1718]; + l1_w6_n108_mux_dataout = sel_wire[0..0] & data_wire[1742..1742] # !(sel_wire[0..0]) & data_wire[1734..1734]; + l1_w6_n109_mux_dataout = sel_wire[0..0] & data_wire[1758..1758] # !(sel_wire[0..0]) & data_wire[1750..1750]; + l1_w6_n10_mux_dataout = sel_wire[0..0] & data_wire[174..174] # !(sel_wire[0..0]) & data_wire[166..166]; + l1_w6_n110_mux_dataout = sel_wire[0..0] & data_wire[1774..1774] # !(sel_wire[0..0]) & data_wire[1766..1766]; + l1_w6_n111_mux_dataout = sel_wire[0..0] & data_wire[1790..1790] # !(sel_wire[0..0]) & data_wire[1782..1782]; + l1_w6_n112_mux_dataout = sel_wire[0..0] & data_wire[1806..1806] # !(sel_wire[0..0]) & data_wire[1798..1798]; + l1_w6_n113_mux_dataout = sel_wire[0..0] & data_wire[1822..1822] # !(sel_wire[0..0]) & data_wire[1814..1814]; + l1_w6_n114_mux_dataout = sel_wire[0..0] & data_wire[1838..1838] # !(sel_wire[0..0]) & data_wire[1830..1830]; + l1_w6_n115_mux_dataout = sel_wire[0..0] & data_wire[1854..1854] # !(sel_wire[0..0]) & data_wire[1846..1846]; + l1_w6_n116_mux_dataout = sel_wire[0..0] & data_wire[1870..1870] # !(sel_wire[0..0]) & data_wire[1862..1862]; + l1_w6_n117_mux_dataout = sel_wire[0..0] & data_wire[1886..1886] # !(sel_wire[0..0]) & data_wire[1878..1878]; + l1_w6_n118_mux_dataout = sel_wire[0..0] & data_wire[1902..1902] # !(sel_wire[0..0]) & data_wire[1894..1894]; + l1_w6_n119_mux_dataout = sel_wire[0..0] & data_wire[1918..1918] # !(sel_wire[0..0]) & data_wire[1910..1910]; + l1_w6_n11_mux_dataout = sel_wire[0..0] & data_wire[190..190] # !(sel_wire[0..0]) & data_wire[182..182]; + l1_w6_n120_mux_dataout = sel_wire[0..0] & data_wire[1934..1934] # !(sel_wire[0..0]) & data_wire[1926..1926]; + l1_w6_n121_mux_dataout = sel_wire[0..0] & data_wire[1950..1950] # !(sel_wire[0..0]) & data_wire[1942..1942]; + l1_w6_n122_mux_dataout = sel_wire[0..0] & data_wire[1966..1966] # !(sel_wire[0..0]) & data_wire[1958..1958]; + l1_w6_n123_mux_dataout = sel_wire[0..0] & data_wire[1982..1982] # !(sel_wire[0..0]) & data_wire[1974..1974]; + l1_w6_n124_mux_dataout = sel_wire[0..0] & data_wire[1998..1998] # !(sel_wire[0..0]) & data_wire[1990..1990]; + l1_w6_n125_mux_dataout = sel_wire[0..0] & data_wire[2014..2014] # !(sel_wire[0..0]) & data_wire[2006..2006]; + l1_w6_n126_mux_dataout = sel_wire[0..0] & data_wire[2030..2030] # !(sel_wire[0..0]) & data_wire[2022..2022]; + l1_w6_n127_mux_dataout = sel_wire[0..0] & data_wire[2046..2046] # !(sel_wire[0..0]) & data_wire[2038..2038]; + l1_w6_n12_mux_dataout = sel_wire[0..0] & data_wire[206..206] # !(sel_wire[0..0]) & data_wire[198..198]; + l1_w6_n13_mux_dataout = sel_wire[0..0] & data_wire[222..222] # !(sel_wire[0..0]) & data_wire[214..214]; + l1_w6_n14_mux_dataout = sel_wire[0..0] & data_wire[238..238] # !(sel_wire[0..0]) & data_wire[230..230]; + l1_w6_n15_mux_dataout = sel_wire[0..0] & data_wire[254..254] # !(sel_wire[0..0]) & data_wire[246..246]; + l1_w6_n16_mux_dataout = sel_wire[0..0] & data_wire[270..270] # !(sel_wire[0..0]) & data_wire[262..262]; + l1_w6_n17_mux_dataout = sel_wire[0..0] & data_wire[286..286] # !(sel_wire[0..0]) & data_wire[278..278]; + l1_w6_n18_mux_dataout = sel_wire[0..0] & data_wire[302..302] # !(sel_wire[0..0]) & data_wire[294..294]; + l1_w6_n19_mux_dataout = sel_wire[0..0] & data_wire[318..318] # !(sel_wire[0..0]) & data_wire[310..310]; + l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22]; + l1_w6_n20_mux_dataout = sel_wire[0..0] & data_wire[334..334] # !(sel_wire[0..0]) & data_wire[326..326]; + l1_w6_n21_mux_dataout = sel_wire[0..0] & data_wire[350..350] # !(sel_wire[0..0]) & data_wire[342..342]; + l1_w6_n22_mux_dataout = sel_wire[0..0] & data_wire[366..366] # !(sel_wire[0..0]) & data_wire[358..358]; + l1_w6_n23_mux_dataout = sel_wire[0..0] & data_wire[382..382] # !(sel_wire[0..0]) & data_wire[374..374]; + l1_w6_n24_mux_dataout = sel_wire[0..0] & data_wire[398..398] # !(sel_wire[0..0]) & data_wire[390..390]; + l1_w6_n25_mux_dataout = sel_wire[0..0] & data_wire[414..414] # !(sel_wire[0..0]) & data_wire[406..406]; + l1_w6_n26_mux_dataout = sel_wire[0..0] & data_wire[430..430] # !(sel_wire[0..0]) & data_wire[422..422]; + l1_w6_n27_mux_dataout = sel_wire[0..0] & data_wire[446..446] # !(sel_wire[0..0]) & data_wire[438..438]; + l1_w6_n28_mux_dataout = sel_wire[0..0] & data_wire[462..462] # !(sel_wire[0..0]) & data_wire[454..454]; + l1_w6_n29_mux_dataout = sel_wire[0..0] & data_wire[478..478] # !(sel_wire[0..0]) & data_wire[470..470]; + l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38]; + l1_w6_n30_mux_dataout = sel_wire[0..0] & data_wire[494..494] # !(sel_wire[0..0]) & data_wire[486..486]; + l1_w6_n31_mux_dataout = sel_wire[0..0] & data_wire[510..510] # !(sel_wire[0..0]) & data_wire[502..502]; + l1_w6_n32_mux_dataout = sel_wire[0..0] & data_wire[526..526] # !(sel_wire[0..0]) & data_wire[518..518]; + l1_w6_n33_mux_dataout = sel_wire[0..0] & data_wire[542..542] # !(sel_wire[0..0]) & data_wire[534..534]; + l1_w6_n34_mux_dataout = sel_wire[0..0] & data_wire[558..558] # !(sel_wire[0..0]) & data_wire[550..550]; + l1_w6_n35_mux_dataout = sel_wire[0..0] & data_wire[574..574] # !(sel_wire[0..0]) & data_wire[566..566]; + l1_w6_n36_mux_dataout = sel_wire[0..0] & data_wire[590..590] # !(sel_wire[0..0]) & data_wire[582..582]; + l1_w6_n37_mux_dataout = sel_wire[0..0] & data_wire[606..606] # !(sel_wire[0..0]) & data_wire[598..598]; + l1_w6_n38_mux_dataout = sel_wire[0..0] & data_wire[622..622] # !(sel_wire[0..0]) & data_wire[614..614]; + l1_w6_n39_mux_dataout = sel_wire[0..0] & data_wire[638..638] # !(sel_wire[0..0]) & data_wire[630..630]; + l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54]; + l1_w6_n40_mux_dataout = sel_wire[0..0] & data_wire[654..654] # !(sel_wire[0..0]) & data_wire[646..646]; + l1_w6_n41_mux_dataout = sel_wire[0..0] & data_wire[670..670] # !(sel_wire[0..0]) & data_wire[662..662]; + l1_w6_n42_mux_dataout = sel_wire[0..0] & data_wire[686..686] # !(sel_wire[0..0]) & data_wire[678..678]; + l1_w6_n43_mux_dataout = sel_wire[0..0] & data_wire[702..702] # !(sel_wire[0..0]) & data_wire[694..694]; + l1_w6_n44_mux_dataout = sel_wire[0..0] & data_wire[718..718] # !(sel_wire[0..0]) & data_wire[710..710]; + l1_w6_n45_mux_dataout = sel_wire[0..0] & data_wire[734..734] # !(sel_wire[0..0]) & data_wire[726..726]; + l1_w6_n46_mux_dataout = sel_wire[0..0] & data_wire[750..750] # !(sel_wire[0..0]) & data_wire[742..742]; + l1_w6_n47_mux_dataout = sel_wire[0..0] & data_wire[766..766] # !(sel_wire[0..0]) & data_wire[758..758]; + l1_w6_n48_mux_dataout = sel_wire[0..0] & data_wire[782..782] # !(sel_wire[0..0]) & data_wire[774..774]; + l1_w6_n49_mux_dataout = sel_wire[0..0] & data_wire[798..798] # !(sel_wire[0..0]) & data_wire[790..790]; + l1_w6_n4_mux_dataout = sel_wire[0..0] & data_wire[78..78] # !(sel_wire[0..0]) & data_wire[70..70]; + l1_w6_n50_mux_dataout = sel_wire[0..0] & data_wire[814..814] # !(sel_wire[0..0]) & data_wire[806..806]; + l1_w6_n51_mux_dataout = sel_wire[0..0] & data_wire[830..830] # !(sel_wire[0..0]) & data_wire[822..822]; + l1_w6_n52_mux_dataout = sel_wire[0..0] & data_wire[846..846] # !(sel_wire[0..0]) & data_wire[838..838]; + l1_w6_n53_mux_dataout = sel_wire[0..0] & data_wire[862..862] # !(sel_wire[0..0]) & data_wire[854..854]; + l1_w6_n54_mux_dataout = sel_wire[0..0] & data_wire[878..878] # !(sel_wire[0..0]) & data_wire[870..870]; + l1_w6_n55_mux_dataout = sel_wire[0..0] & data_wire[894..894] # !(sel_wire[0..0]) & data_wire[886..886]; + l1_w6_n56_mux_dataout = sel_wire[0..0] & data_wire[910..910] # !(sel_wire[0..0]) & data_wire[902..902]; + l1_w6_n57_mux_dataout = sel_wire[0..0] & data_wire[926..926] # !(sel_wire[0..0]) & data_wire[918..918]; + l1_w6_n58_mux_dataout = sel_wire[0..0] & data_wire[942..942] # !(sel_wire[0..0]) & data_wire[934..934]; + l1_w6_n59_mux_dataout = sel_wire[0..0] & data_wire[958..958] # !(sel_wire[0..0]) & data_wire[950..950]; + l1_w6_n5_mux_dataout = sel_wire[0..0] & data_wire[94..94] # !(sel_wire[0..0]) & data_wire[86..86]; + l1_w6_n60_mux_dataout = sel_wire[0..0] & data_wire[974..974] # !(sel_wire[0..0]) & data_wire[966..966]; + l1_w6_n61_mux_dataout = sel_wire[0..0] & data_wire[990..990] # !(sel_wire[0..0]) & data_wire[982..982]; + l1_w6_n62_mux_dataout = sel_wire[0..0] & data_wire[1006..1006] # !(sel_wire[0..0]) & data_wire[998..998]; + l1_w6_n63_mux_dataout = sel_wire[0..0] & data_wire[1022..1022] # !(sel_wire[0..0]) & data_wire[1014..1014]; + l1_w6_n64_mux_dataout = sel_wire[0..0] & data_wire[1038..1038] # !(sel_wire[0..0]) & data_wire[1030..1030]; + l1_w6_n65_mux_dataout = sel_wire[0..0] & data_wire[1054..1054] # !(sel_wire[0..0]) & data_wire[1046..1046]; + l1_w6_n66_mux_dataout = sel_wire[0..0] & data_wire[1070..1070] # !(sel_wire[0..0]) & data_wire[1062..1062]; + l1_w6_n67_mux_dataout = sel_wire[0..0] & data_wire[1086..1086] # !(sel_wire[0..0]) & data_wire[1078..1078]; + l1_w6_n68_mux_dataout = sel_wire[0..0] & data_wire[1102..1102] # !(sel_wire[0..0]) & data_wire[1094..1094]; + l1_w6_n69_mux_dataout = sel_wire[0..0] & data_wire[1118..1118] # !(sel_wire[0..0]) & data_wire[1110..1110]; + l1_w6_n6_mux_dataout = sel_wire[0..0] & data_wire[110..110] # !(sel_wire[0..0]) & data_wire[102..102]; + l1_w6_n70_mux_dataout = sel_wire[0..0] & data_wire[1134..1134] # !(sel_wire[0..0]) & data_wire[1126..1126]; + l1_w6_n71_mux_dataout = sel_wire[0..0] & data_wire[1150..1150] # !(sel_wire[0..0]) & data_wire[1142..1142]; + l1_w6_n72_mux_dataout = sel_wire[0..0] & data_wire[1166..1166] # !(sel_wire[0..0]) & data_wire[1158..1158]; + l1_w6_n73_mux_dataout = sel_wire[0..0] & data_wire[1182..1182] # !(sel_wire[0..0]) & data_wire[1174..1174]; + l1_w6_n74_mux_dataout = sel_wire[0..0] & data_wire[1198..1198] # !(sel_wire[0..0]) & data_wire[1190..1190]; + l1_w6_n75_mux_dataout = sel_wire[0..0] & data_wire[1214..1214] # !(sel_wire[0..0]) & data_wire[1206..1206]; + l1_w6_n76_mux_dataout = sel_wire[0..0] & data_wire[1230..1230] # !(sel_wire[0..0]) & data_wire[1222..1222]; + l1_w6_n77_mux_dataout = sel_wire[0..0] & data_wire[1246..1246] # !(sel_wire[0..0]) & data_wire[1238..1238]; + l1_w6_n78_mux_dataout = sel_wire[0..0] & data_wire[1262..1262] # !(sel_wire[0..0]) & data_wire[1254..1254]; + l1_w6_n79_mux_dataout = sel_wire[0..0] & data_wire[1278..1278] # !(sel_wire[0..0]) & data_wire[1270..1270]; + l1_w6_n7_mux_dataout = sel_wire[0..0] & data_wire[126..126] # !(sel_wire[0..0]) & data_wire[118..118]; + l1_w6_n80_mux_dataout = sel_wire[0..0] & data_wire[1294..1294] # !(sel_wire[0..0]) & data_wire[1286..1286]; + l1_w6_n81_mux_dataout = sel_wire[0..0] & data_wire[1310..1310] # !(sel_wire[0..0]) & data_wire[1302..1302]; + l1_w6_n82_mux_dataout = sel_wire[0..0] & data_wire[1326..1326] # !(sel_wire[0..0]) & data_wire[1318..1318]; + l1_w6_n83_mux_dataout = sel_wire[0..0] & data_wire[1342..1342] # !(sel_wire[0..0]) & data_wire[1334..1334]; + l1_w6_n84_mux_dataout = sel_wire[0..0] & data_wire[1358..1358] # !(sel_wire[0..0]) & data_wire[1350..1350]; + l1_w6_n85_mux_dataout = sel_wire[0..0] & data_wire[1374..1374] # !(sel_wire[0..0]) & data_wire[1366..1366]; + l1_w6_n86_mux_dataout = sel_wire[0..0] & data_wire[1390..1390] # !(sel_wire[0..0]) & data_wire[1382..1382]; + l1_w6_n87_mux_dataout = sel_wire[0..0] & data_wire[1406..1406] # !(sel_wire[0..0]) & data_wire[1398..1398]; + l1_w6_n88_mux_dataout = sel_wire[0..0] & data_wire[1422..1422] # !(sel_wire[0..0]) & data_wire[1414..1414]; + l1_w6_n89_mux_dataout = sel_wire[0..0] & data_wire[1438..1438] # !(sel_wire[0..0]) & data_wire[1430..1430]; + l1_w6_n8_mux_dataout = sel_wire[0..0] & data_wire[142..142] # !(sel_wire[0..0]) & data_wire[134..134]; + l1_w6_n90_mux_dataout = sel_wire[0..0] & data_wire[1454..1454] # !(sel_wire[0..0]) & data_wire[1446..1446]; + l1_w6_n91_mux_dataout = sel_wire[0..0] & data_wire[1470..1470] # !(sel_wire[0..0]) & data_wire[1462..1462]; + l1_w6_n92_mux_dataout = sel_wire[0..0] & data_wire[1486..1486] # !(sel_wire[0..0]) & data_wire[1478..1478]; + l1_w6_n93_mux_dataout = sel_wire[0..0] & data_wire[1502..1502] # !(sel_wire[0..0]) & data_wire[1494..1494]; + l1_w6_n94_mux_dataout = sel_wire[0..0] & data_wire[1518..1518] # !(sel_wire[0..0]) & data_wire[1510..1510]; + l1_w6_n95_mux_dataout = sel_wire[0..0] & data_wire[1534..1534] # !(sel_wire[0..0]) & data_wire[1526..1526]; + l1_w6_n96_mux_dataout = sel_wire[0..0] & data_wire[1550..1550] # !(sel_wire[0..0]) & data_wire[1542..1542]; + l1_w6_n97_mux_dataout = sel_wire[0..0] & data_wire[1566..1566] # !(sel_wire[0..0]) & data_wire[1558..1558]; + l1_w6_n98_mux_dataout = sel_wire[0..0] & data_wire[1582..1582] # !(sel_wire[0..0]) & data_wire[1574..1574]; + l1_w6_n99_mux_dataout = sel_wire[0..0] & data_wire[1598..1598] # !(sel_wire[0..0]) & data_wire[1590..1590]; + l1_w6_n9_mux_dataout = sel_wire[0..0] & data_wire[158..158] # !(sel_wire[0..0]) & data_wire[150..150]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + l1_w7_n100_mux_dataout = sel_wire[0..0] & data_wire[1615..1615] # !(sel_wire[0..0]) & data_wire[1607..1607]; + l1_w7_n101_mux_dataout = sel_wire[0..0] & data_wire[1631..1631] # !(sel_wire[0..0]) & data_wire[1623..1623]; + l1_w7_n102_mux_dataout = sel_wire[0..0] & data_wire[1647..1647] # !(sel_wire[0..0]) & data_wire[1639..1639]; + l1_w7_n103_mux_dataout = sel_wire[0..0] & data_wire[1663..1663] # !(sel_wire[0..0]) & data_wire[1655..1655]; + l1_w7_n104_mux_dataout = sel_wire[0..0] & data_wire[1679..1679] # !(sel_wire[0..0]) & data_wire[1671..1671]; + l1_w7_n105_mux_dataout = sel_wire[0..0] & data_wire[1695..1695] # !(sel_wire[0..0]) & data_wire[1687..1687]; + l1_w7_n106_mux_dataout = sel_wire[0..0] & data_wire[1711..1711] # !(sel_wire[0..0]) & data_wire[1703..1703]; + l1_w7_n107_mux_dataout = sel_wire[0..0] & data_wire[1727..1727] # !(sel_wire[0..0]) & data_wire[1719..1719]; + l1_w7_n108_mux_dataout = sel_wire[0..0] & data_wire[1743..1743] # !(sel_wire[0..0]) & data_wire[1735..1735]; + l1_w7_n109_mux_dataout = sel_wire[0..0] & data_wire[1759..1759] # !(sel_wire[0..0]) & data_wire[1751..1751]; + l1_w7_n10_mux_dataout = sel_wire[0..0] & data_wire[175..175] # !(sel_wire[0..0]) & data_wire[167..167]; + l1_w7_n110_mux_dataout = sel_wire[0..0] & data_wire[1775..1775] # !(sel_wire[0..0]) & data_wire[1767..1767]; + l1_w7_n111_mux_dataout = sel_wire[0..0] & data_wire[1791..1791] # !(sel_wire[0..0]) & data_wire[1783..1783]; + l1_w7_n112_mux_dataout = sel_wire[0..0] & data_wire[1807..1807] # !(sel_wire[0..0]) & data_wire[1799..1799]; + l1_w7_n113_mux_dataout = sel_wire[0..0] & data_wire[1823..1823] # !(sel_wire[0..0]) & data_wire[1815..1815]; + l1_w7_n114_mux_dataout = sel_wire[0..0] & data_wire[1839..1839] # !(sel_wire[0..0]) & data_wire[1831..1831]; + l1_w7_n115_mux_dataout = sel_wire[0..0] & data_wire[1855..1855] # !(sel_wire[0..0]) & data_wire[1847..1847]; + l1_w7_n116_mux_dataout = sel_wire[0..0] & data_wire[1871..1871] # !(sel_wire[0..0]) & data_wire[1863..1863]; + l1_w7_n117_mux_dataout = sel_wire[0..0] & data_wire[1887..1887] # !(sel_wire[0..0]) & data_wire[1879..1879]; + l1_w7_n118_mux_dataout = sel_wire[0..0] & data_wire[1903..1903] # !(sel_wire[0..0]) & data_wire[1895..1895]; + l1_w7_n119_mux_dataout = sel_wire[0..0] & data_wire[1919..1919] # !(sel_wire[0..0]) & data_wire[1911..1911]; + l1_w7_n11_mux_dataout = sel_wire[0..0] & data_wire[191..191] # !(sel_wire[0..0]) & data_wire[183..183]; + l1_w7_n120_mux_dataout = sel_wire[0..0] & data_wire[1935..1935] # !(sel_wire[0..0]) & data_wire[1927..1927]; + l1_w7_n121_mux_dataout = sel_wire[0..0] & data_wire[1951..1951] # !(sel_wire[0..0]) & data_wire[1943..1943]; + l1_w7_n122_mux_dataout = sel_wire[0..0] & data_wire[1967..1967] # !(sel_wire[0..0]) & data_wire[1959..1959]; + l1_w7_n123_mux_dataout = sel_wire[0..0] & data_wire[1983..1983] # !(sel_wire[0..0]) & data_wire[1975..1975]; + l1_w7_n124_mux_dataout = sel_wire[0..0] & data_wire[1999..1999] # !(sel_wire[0..0]) & data_wire[1991..1991]; + l1_w7_n125_mux_dataout = sel_wire[0..0] & data_wire[2015..2015] # !(sel_wire[0..0]) & data_wire[2007..2007]; + l1_w7_n126_mux_dataout = sel_wire[0..0] & data_wire[2031..2031] # !(sel_wire[0..0]) & data_wire[2023..2023]; + l1_w7_n127_mux_dataout = sel_wire[0..0] & data_wire[2047..2047] # !(sel_wire[0..0]) & data_wire[2039..2039]; + l1_w7_n12_mux_dataout = sel_wire[0..0] & data_wire[207..207] # !(sel_wire[0..0]) & data_wire[199..199]; + l1_w7_n13_mux_dataout = sel_wire[0..0] & data_wire[223..223] # !(sel_wire[0..0]) & data_wire[215..215]; + l1_w7_n14_mux_dataout = sel_wire[0..0] & data_wire[239..239] # !(sel_wire[0..0]) & data_wire[231..231]; + l1_w7_n15_mux_dataout = sel_wire[0..0] & data_wire[255..255] # !(sel_wire[0..0]) & data_wire[247..247]; + l1_w7_n16_mux_dataout = sel_wire[0..0] & data_wire[271..271] # !(sel_wire[0..0]) & data_wire[263..263]; + l1_w7_n17_mux_dataout = sel_wire[0..0] & data_wire[287..287] # !(sel_wire[0..0]) & data_wire[279..279]; + l1_w7_n18_mux_dataout = sel_wire[0..0] & data_wire[303..303] # !(sel_wire[0..0]) & data_wire[295..295]; + l1_w7_n19_mux_dataout = sel_wire[0..0] & data_wire[319..319] # !(sel_wire[0..0]) & data_wire[311..311]; + l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23]; + l1_w7_n20_mux_dataout = sel_wire[0..0] & data_wire[335..335] # !(sel_wire[0..0]) & data_wire[327..327]; + l1_w7_n21_mux_dataout = sel_wire[0..0] & data_wire[351..351] # !(sel_wire[0..0]) & data_wire[343..343]; + l1_w7_n22_mux_dataout = sel_wire[0..0] & data_wire[367..367] # !(sel_wire[0..0]) & data_wire[359..359]; + l1_w7_n23_mux_dataout = sel_wire[0..0] & data_wire[383..383] # !(sel_wire[0..0]) & data_wire[375..375]; + l1_w7_n24_mux_dataout = sel_wire[0..0] & data_wire[399..399] # !(sel_wire[0..0]) & data_wire[391..391]; + l1_w7_n25_mux_dataout = sel_wire[0..0] & data_wire[415..415] # !(sel_wire[0..0]) & data_wire[407..407]; + l1_w7_n26_mux_dataout = sel_wire[0..0] & data_wire[431..431] # !(sel_wire[0..0]) & data_wire[423..423]; + l1_w7_n27_mux_dataout = sel_wire[0..0] & data_wire[447..447] # !(sel_wire[0..0]) & data_wire[439..439]; + l1_w7_n28_mux_dataout = sel_wire[0..0] & data_wire[463..463] # !(sel_wire[0..0]) & data_wire[455..455]; + l1_w7_n29_mux_dataout = sel_wire[0..0] & data_wire[479..479] # !(sel_wire[0..0]) & data_wire[471..471]; + l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39]; + l1_w7_n30_mux_dataout = sel_wire[0..0] & data_wire[495..495] # !(sel_wire[0..0]) & data_wire[487..487]; + l1_w7_n31_mux_dataout = sel_wire[0..0] & data_wire[511..511] # !(sel_wire[0..0]) & data_wire[503..503]; + l1_w7_n32_mux_dataout = sel_wire[0..0] & data_wire[527..527] # !(sel_wire[0..0]) & data_wire[519..519]; + l1_w7_n33_mux_dataout = sel_wire[0..0] & data_wire[543..543] # !(sel_wire[0..0]) & data_wire[535..535]; + l1_w7_n34_mux_dataout = sel_wire[0..0] & data_wire[559..559] # !(sel_wire[0..0]) & data_wire[551..551]; + l1_w7_n35_mux_dataout = sel_wire[0..0] & data_wire[575..575] # !(sel_wire[0..0]) & data_wire[567..567]; + l1_w7_n36_mux_dataout = sel_wire[0..0] & data_wire[591..591] # !(sel_wire[0..0]) & data_wire[583..583]; + l1_w7_n37_mux_dataout = sel_wire[0..0] & data_wire[607..607] # !(sel_wire[0..0]) & data_wire[599..599]; + l1_w7_n38_mux_dataout = sel_wire[0..0] & data_wire[623..623] # !(sel_wire[0..0]) & data_wire[615..615]; + l1_w7_n39_mux_dataout = sel_wire[0..0] & data_wire[639..639] # !(sel_wire[0..0]) & data_wire[631..631]; + l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55]; + l1_w7_n40_mux_dataout = sel_wire[0..0] & data_wire[655..655] # !(sel_wire[0..0]) & data_wire[647..647]; + l1_w7_n41_mux_dataout = sel_wire[0..0] & data_wire[671..671] # !(sel_wire[0..0]) & data_wire[663..663]; + l1_w7_n42_mux_dataout = sel_wire[0..0] & data_wire[687..687] # !(sel_wire[0..0]) & data_wire[679..679]; + l1_w7_n43_mux_dataout = sel_wire[0..0] & data_wire[703..703] # !(sel_wire[0..0]) & data_wire[695..695]; + l1_w7_n44_mux_dataout = sel_wire[0..0] & data_wire[719..719] # !(sel_wire[0..0]) & data_wire[711..711]; + l1_w7_n45_mux_dataout = sel_wire[0..0] & data_wire[735..735] # !(sel_wire[0..0]) & data_wire[727..727]; + l1_w7_n46_mux_dataout = sel_wire[0..0] & data_wire[751..751] # !(sel_wire[0..0]) & data_wire[743..743]; + l1_w7_n47_mux_dataout = sel_wire[0..0] & data_wire[767..767] # !(sel_wire[0..0]) & data_wire[759..759]; + l1_w7_n48_mux_dataout = sel_wire[0..0] & data_wire[783..783] # !(sel_wire[0..0]) & data_wire[775..775]; + l1_w7_n49_mux_dataout = sel_wire[0..0] & data_wire[799..799] # !(sel_wire[0..0]) & data_wire[791..791]; + l1_w7_n4_mux_dataout = sel_wire[0..0] & data_wire[79..79] # !(sel_wire[0..0]) & data_wire[71..71]; + l1_w7_n50_mux_dataout = sel_wire[0..0] & data_wire[815..815] # !(sel_wire[0..0]) & data_wire[807..807]; + l1_w7_n51_mux_dataout = sel_wire[0..0] & data_wire[831..831] # !(sel_wire[0..0]) & data_wire[823..823]; + l1_w7_n52_mux_dataout = sel_wire[0..0] & data_wire[847..847] # !(sel_wire[0..0]) & data_wire[839..839]; + l1_w7_n53_mux_dataout = sel_wire[0..0] & data_wire[863..863] # !(sel_wire[0..0]) & data_wire[855..855]; + l1_w7_n54_mux_dataout = sel_wire[0..0] & data_wire[879..879] # !(sel_wire[0..0]) & data_wire[871..871]; + l1_w7_n55_mux_dataout = sel_wire[0..0] & data_wire[895..895] # !(sel_wire[0..0]) & data_wire[887..887]; + l1_w7_n56_mux_dataout = sel_wire[0..0] & data_wire[911..911] # !(sel_wire[0..0]) & data_wire[903..903]; + l1_w7_n57_mux_dataout = sel_wire[0..0] & data_wire[927..927] # !(sel_wire[0..0]) & data_wire[919..919]; + l1_w7_n58_mux_dataout = sel_wire[0..0] & data_wire[943..943] # !(sel_wire[0..0]) & data_wire[935..935]; + l1_w7_n59_mux_dataout = sel_wire[0..0] & data_wire[959..959] # !(sel_wire[0..0]) & data_wire[951..951]; + l1_w7_n5_mux_dataout = sel_wire[0..0] & data_wire[95..95] # !(sel_wire[0..0]) & data_wire[87..87]; + l1_w7_n60_mux_dataout = sel_wire[0..0] & data_wire[975..975] # !(sel_wire[0..0]) & data_wire[967..967]; + l1_w7_n61_mux_dataout = sel_wire[0..0] & data_wire[991..991] # !(sel_wire[0..0]) & data_wire[983..983]; + l1_w7_n62_mux_dataout = sel_wire[0..0] & data_wire[1007..1007] # !(sel_wire[0..0]) & data_wire[999..999]; + l1_w7_n63_mux_dataout = sel_wire[0..0] & data_wire[1023..1023] # !(sel_wire[0..0]) & data_wire[1015..1015]; + l1_w7_n64_mux_dataout = sel_wire[0..0] & data_wire[1039..1039] # !(sel_wire[0..0]) & data_wire[1031..1031]; + l1_w7_n65_mux_dataout = sel_wire[0..0] & data_wire[1055..1055] # !(sel_wire[0..0]) & data_wire[1047..1047]; + l1_w7_n66_mux_dataout = sel_wire[0..0] & data_wire[1071..1071] # !(sel_wire[0..0]) & data_wire[1063..1063]; + l1_w7_n67_mux_dataout = sel_wire[0..0] & data_wire[1087..1087] # !(sel_wire[0..0]) & data_wire[1079..1079]; + l1_w7_n68_mux_dataout = sel_wire[0..0] & data_wire[1103..1103] # !(sel_wire[0..0]) & data_wire[1095..1095]; + l1_w7_n69_mux_dataout = sel_wire[0..0] & data_wire[1119..1119] # !(sel_wire[0..0]) & data_wire[1111..1111]; + l1_w7_n6_mux_dataout = sel_wire[0..0] & data_wire[111..111] # !(sel_wire[0..0]) & data_wire[103..103]; + l1_w7_n70_mux_dataout = sel_wire[0..0] & data_wire[1135..1135] # !(sel_wire[0..0]) & data_wire[1127..1127]; + l1_w7_n71_mux_dataout = sel_wire[0..0] & data_wire[1151..1151] # !(sel_wire[0..0]) & data_wire[1143..1143]; + l1_w7_n72_mux_dataout = sel_wire[0..0] & data_wire[1167..1167] # !(sel_wire[0..0]) & data_wire[1159..1159]; + l1_w7_n73_mux_dataout = sel_wire[0..0] & data_wire[1183..1183] # !(sel_wire[0..0]) & data_wire[1175..1175]; + l1_w7_n74_mux_dataout = sel_wire[0..0] & data_wire[1199..1199] # !(sel_wire[0..0]) & data_wire[1191..1191]; + l1_w7_n75_mux_dataout = sel_wire[0..0] & data_wire[1215..1215] # !(sel_wire[0..0]) & data_wire[1207..1207]; + l1_w7_n76_mux_dataout = sel_wire[0..0] & data_wire[1231..1231] # !(sel_wire[0..0]) & data_wire[1223..1223]; + l1_w7_n77_mux_dataout = sel_wire[0..0] & data_wire[1247..1247] # !(sel_wire[0..0]) & data_wire[1239..1239]; + l1_w7_n78_mux_dataout = sel_wire[0..0] & data_wire[1263..1263] # !(sel_wire[0..0]) & data_wire[1255..1255]; + l1_w7_n79_mux_dataout = sel_wire[0..0] & data_wire[1279..1279] # !(sel_wire[0..0]) & data_wire[1271..1271]; + l1_w7_n7_mux_dataout = sel_wire[0..0] & data_wire[127..127] # !(sel_wire[0..0]) & data_wire[119..119]; + l1_w7_n80_mux_dataout = sel_wire[0..0] & data_wire[1295..1295] # !(sel_wire[0..0]) & data_wire[1287..1287]; + l1_w7_n81_mux_dataout = sel_wire[0..0] & data_wire[1311..1311] # !(sel_wire[0..0]) & data_wire[1303..1303]; + l1_w7_n82_mux_dataout = sel_wire[0..0] & data_wire[1327..1327] # !(sel_wire[0..0]) & data_wire[1319..1319]; + l1_w7_n83_mux_dataout = sel_wire[0..0] & data_wire[1343..1343] # !(sel_wire[0..0]) & data_wire[1335..1335]; + l1_w7_n84_mux_dataout = sel_wire[0..0] & data_wire[1359..1359] # !(sel_wire[0..0]) & data_wire[1351..1351]; + l1_w7_n85_mux_dataout = sel_wire[0..0] & data_wire[1375..1375] # !(sel_wire[0..0]) & data_wire[1367..1367]; + l1_w7_n86_mux_dataout = sel_wire[0..0] & data_wire[1391..1391] # !(sel_wire[0..0]) & data_wire[1383..1383]; + l1_w7_n87_mux_dataout = sel_wire[0..0] & data_wire[1407..1407] # !(sel_wire[0..0]) & data_wire[1399..1399]; + l1_w7_n88_mux_dataout = sel_wire[0..0] & data_wire[1423..1423] # !(sel_wire[0..0]) & data_wire[1415..1415]; + l1_w7_n89_mux_dataout = sel_wire[0..0] & data_wire[1439..1439] # !(sel_wire[0..0]) & data_wire[1431..1431]; + l1_w7_n8_mux_dataout = sel_wire[0..0] & data_wire[143..143] # !(sel_wire[0..0]) & data_wire[135..135]; + l1_w7_n90_mux_dataout = sel_wire[0..0] & data_wire[1455..1455] # !(sel_wire[0..0]) & data_wire[1447..1447]; + l1_w7_n91_mux_dataout = sel_wire[0..0] & data_wire[1471..1471] # !(sel_wire[0..0]) & data_wire[1463..1463]; + l1_w7_n92_mux_dataout = sel_wire[0..0] & data_wire[1487..1487] # !(sel_wire[0..0]) & data_wire[1479..1479]; + l1_w7_n93_mux_dataout = sel_wire[0..0] & data_wire[1503..1503] # !(sel_wire[0..0]) & data_wire[1495..1495]; + l1_w7_n94_mux_dataout = sel_wire[0..0] & data_wire[1519..1519] # !(sel_wire[0..0]) & data_wire[1511..1511]; + l1_w7_n95_mux_dataout = sel_wire[0..0] & data_wire[1535..1535] # !(sel_wire[0..0]) & data_wire[1527..1527]; + l1_w7_n96_mux_dataout = sel_wire[0..0] & data_wire[1551..1551] # !(sel_wire[0..0]) & data_wire[1543..1543]; + l1_w7_n97_mux_dataout = sel_wire[0..0] & data_wire[1567..1567] # !(sel_wire[0..0]) & data_wire[1559..1559]; + l1_w7_n98_mux_dataout = sel_wire[0..0] & data_wire[1583..1583] # !(sel_wire[0..0]) & data_wire[1575..1575]; + l1_w7_n99_mux_dataout = sel_wire[0..0] & data_wire[1599..1599] # !(sel_wire[0..0]) & data_wire[1591..1591]; + l1_w7_n9_mux_dataout = sel_wire[0..0] & data_wire[159..159] # !(sel_wire[0..0]) & data_wire[151..151]; + l2_w0_n0_mux_dataout = sel_wire[9..9] & data_wire[2049..2049] # !(sel_wire[9..9]) & data_wire[2048..2048]; + l2_w0_n10_mux_dataout = sel_wire[9..9] & data_wire[2069..2069] # !(sel_wire[9..9]) & data_wire[2068..2068]; + l2_w0_n11_mux_dataout = sel_wire[9..9] & data_wire[2071..2071] # !(sel_wire[9..9]) & data_wire[2070..2070]; + l2_w0_n12_mux_dataout = sel_wire[9..9] & data_wire[2073..2073] # !(sel_wire[9..9]) & data_wire[2072..2072]; + l2_w0_n13_mux_dataout = sel_wire[9..9] & data_wire[2075..2075] # !(sel_wire[9..9]) & data_wire[2074..2074]; + l2_w0_n14_mux_dataout = sel_wire[9..9] & data_wire[2077..2077] # !(sel_wire[9..9]) & data_wire[2076..2076]; + l2_w0_n15_mux_dataout = sel_wire[9..9] & data_wire[2079..2079] # !(sel_wire[9..9]) & data_wire[2078..2078]; + l2_w0_n16_mux_dataout = sel_wire[9..9] & data_wire[2081..2081] # !(sel_wire[9..9]) & data_wire[2080..2080]; + l2_w0_n17_mux_dataout = sel_wire[9..9] & data_wire[2083..2083] # !(sel_wire[9..9]) & data_wire[2082..2082]; + l2_w0_n18_mux_dataout = sel_wire[9..9] & data_wire[2085..2085] # !(sel_wire[9..9]) & data_wire[2084..2084]; + l2_w0_n19_mux_dataout = sel_wire[9..9] & data_wire[2087..2087] # !(sel_wire[9..9]) & data_wire[2086..2086]; + l2_w0_n1_mux_dataout = sel_wire[9..9] & data_wire[2051..2051] # !(sel_wire[9..9]) & data_wire[2050..2050]; + l2_w0_n20_mux_dataout = sel_wire[9..9] & data_wire[2089..2089] # !(sel_wire[9..9]) & data_wire[2088..2088]; + l2_w0_n21_mux_dataout = sel_wire[9..9] & data_wire[2091..2091] # !(sel_wire[9..9]) & data_wire[2090..2090]; + l2_w0_n22_mux_dataout = sel_wire[9..9] & data_wire[2093..2093] # !(sel_wire[9..9]) & data_wire[2092..2092]; + l2_w0_n23_mux_dataout = sel_wire[9..9] & data_wire[2095..2095] # !(sel_wire[9..9]) & data_wire[2094..2094]; + l2_w0_n24_mux_dataout = sel_wire[9..9] & data_wire[2097..2097] # !(sel_wire[9..9]) & data_wire[2096..2096]; + l2_w0_n25_mux_dataout = sel_wire[9..9] & data_wire[2099..2099] # !(sel_wire[9..9]) & data_wire[2098..2098]; + l2_w0_n26_mux_dataout = sel_wire[9..9] & data_wire[2101..2101] # !(sel_wire[9..9]) & data_wire[2100..2100]; + l2_w0_n27_mux_dataout = sel_wire[9..9] & data_wire[2103..2103] # !(sel_wire[9..9]) & data_wire[2102..2102]; + l2_w0_n28_mux_dataout = sel_wire[9..9] & data_wire[2105..2105] # !(sel_wire[9..9]) & data_wire[2104..2104]; + l2_w0_n29_mux_dataout = sel_wire[9..9] & data_wire[2107..2107] # !(sel_wire[9..9]) & data_wire[2106..2106]; + l2_w0_n2_mux_dataout = sel_wire[9..9] & data_wire[2053..2053] # !(sel_wire[9..9]) & data_wire[2052..2052]; + l2_w0_n30_mux_dataout = sel_wire[9..9] & data_wire[2109..2109] # !(sel_wire[9..9]) & data_wire[2108..2108]; + l2_w0_n31_mux_dataout = sel_wire[9..9] & data_wire[2111..2111] # !(sel_wire[9..9]) & data_wire[2110..2110]; + l2_w0_n32_mux_dataout = sel_wire[9..9] & data_wire[2113..2113] # !(sel_wire[9..9]) & data_wire[2112..2112]; + l2_w0_n33_mux_dataout = sel_wire[9..9] & data_wire[2115..2115] # !(sel_wire[9..9]) & data_wire[2114..2114]; + l2_w0_n34_mux_dataout = sel_wire[9..9] & data_wire[2117..2117] # !(sel_wire[9..9]) & data_wire[2116..2116]; + l2_w0_n35_mux_dataout = sel_wire[9..9] & data_wire[2119..2119] # !(sel_wire[9..9]) & data_wire[2118..2118]; + l2_w0_n36_mux_dataout = sel_wire[9..9] & data_wire[2121..2121] # !(sel_wire[9..9]) & data_wire[2120..2120]; + l2_w0_n37_mux_dataout = sel_wire[9..9] & data_wire[2123..2123] # !(sel_wire[9..9]) & data_wire[2122..2122]; + l2_w0_n38_mux_dataout = sel_wire[9..9] & data_wire[2125..2125] # !(sel_wire[9..9]) & data_wire[2124..2124]; + l2_w0_n39_mux_dataout = sel_wire[9..9] & data_wire[2127..2127] # !(sel_wire[9..9]) & data_wire[2126..2126]; + l2_w0_n3_mux_dataout = sel_wire[9..9] & data_wire[2055..2055] # !(sel_wire[9..9]) & data_wire[2054..2054]; + l2_w0_n40_mux_dataout = sel_wire[9..9] & data_wire[2129..2129] # !(sel_wire[9..9]) & data_wire[2128..2128]; + l2_w0_n41_mux_dataout = sel_wire[9..9] & data_wire[2131..2131] # !(sel_wire[9..9]) & data_wire[2130..2130]; + l2_w0_n42_mux_dataout = sel_wire[9..9] & data_wire[2133..2133] # !(sel_wire[9..9]) & data_wire[2132..2132]; + l2_w0_n43_mux_dataout = sel_wire[9..9] & data_wire[2135..2135] # !(sel_wire[9..9]) & data_wire[2134..2134]; + l2_w0_n44_mux_dataout = sel_wire[9..9] & data_wire[2137..2137] # !(sel_wire[9..9]) & data_wire[2136..2136]; + l2_w0_n45_mux_dataout = sel_wire[9..9] & data_wire[2139..2139] # !(sel_wire[9..9]) & data_wire[2138..2138]; + l2_w0_n46_mux_dataout = sel_wire[9..9] & data_wire[2141..2141] # !(sel_wire[9..9]) & data_wire[2140..2140]; + l2_w0_n47_mux_dataout = sel_wire[9..9] & data_wire[2143..2143] # !(sel_wire[9..9]) & data_wire[2142..2142]; + l2_w0_n48_mux_dataout = sel_wire[9..9] & data_wire[2145..2145] # !(sel_wire[9..9]) & data_wire[2144..2144]; + l2_w0_n49_mux_dataout = sel_wire[9..9] & data_wire[2147..2147] # !(sel_wire[9..9]) & data_wire[2146..2146]; + l2_w0_n4_mux_dataout = sel_wire[9..9] & data_wire[2057..2057] # !(sel_wire[9..9]) & data_wire[2056..2056]; + l2_w0_n50_mux_dataout = sel_wire[9..9] & data_wire[2149..2149] # !(sel_wire[9..9]) & data_wire[2148..2148]; + l2_w0_n51_mux_dataout = sel_wire[9..9] & data_wire[2151..2151] # !(sel_wire[9..9]) & data_wire[2150..2150]; + l2_w0_n52_mux_dataout = sel_wire[9..9] & data_wire[2153..2153] # !(sel_wire[9..9]) & data_wire[2152..2152]; + l2_w0_n53_mux_dataout = sel_wire[9..9] & data_wire[2155..2155] # !(sel_wire[9..9]) & data_wire[2154..2154]; + l2_w0_n54_mux_dataout = sel_wire[9..9] & data_wire[2157..2157] # !(sel_wire[9..9]) & data_wire[2156..2156]; + l2_w0_n55_mux_dataout = sel_wire[9..9] & data_wire[2159..2159] # !(sel_wire[9..9]) & data_wire[2158..2158]; + l2_w0_n56_mux_dataout = sel_wire[9..9] & data_wire[2161..2161] # !(sel_wire[9..9]) & data_wire[2160..2160]; + l2_w0_n57_mux_dataout = sel_wire[9..9] & data_wire[2163..2163] # !(sel_wire[9..9]) & data_wire[2162..2162]; + l2_w0_n58_mux_dataout = sel_wire[9..9] & data_wire[2165..2165] # !(sel_wire[9..9]) & data_wire[2164..2164]; + l2_w0_n59_mux_dataout = sel_wire[9..9] & data_wire[2167..2167] # !(sel_wire[9..9]) & data_wire[2166..2166]; + l2_w0_n5_mux_dataout = sel_wire[9..9] & data_wire[2059..2059] # !(sel_wire[9..9]) & data_wire[2058..2058]; + l2_w0_n60_mux_dataout = sel_wire[9..9] & data_wire[2169..2169] # !(sel_wire[9..9]) & data_wire[2168..2168]; + l2_w0_n61_mux_dataout = sel_wire[9..9] & data_wire[2171..2171] # !(sel_wire[9..9]) & data_wire[2170..2170]; + l2_w0_n62_mux_dataout = sel_wire[9..9] & data_wire[2173..2173] # !(sel_wire[9..9]) & data_wire[2172..2172]; + l2_w0_n63_mux_dataout = sel_wire[9..9] & data_wire[2175..2175] # !(sel_wire[9..9]) & data_wire[2174..2174]; + l2_w0_n6_mux_dataout = sel_wire[9..9] & data_wire[2061..2061] # !(sel_wire[9..9]) & data_wire[2060..2060]; + l2_w0_n7_mux_dataout = sel_wire[9..9] & data_wire[2063..2063] # !(sel_wire[9..9]) & data_wire[2062..2062]; + l2_w0_n8_mux_dataout = sel_wire[9..9] & data_wire[2065..2065] # !(sel_wire[9..9]) & data_wire[2064..2064]; + l2_w0_n9_mux_dataout = sel_wire[9..9] & data_wire[2067..2067] # !(sel_wire[9..9]) & data_wire[2066..2066]; + l2_w1_n0_mux_dataout = sel_wire[9..9] & data_wire[2177..2177] # !(sel_wire[9..9]) & data_wire[2176..2176]; + l2_w1_n10_mux_dataout = sel_wire[9..9] & data_wire[2197..2197] # !(sel_wire[9..9]) & data_wire[2196..2196]; + l2_w1_n11_mux_dataout = sel_wire[9..9] & data_wire[2199..2199] # !(sel_wire[9..9]) & data_wire[2198..2198]; + l2_w1_n12_mux_dataout = sel_wire[9..9] & data_wire[2201..2201] # !(sel_wire[9..9]) & data_wire[2200..2200]; + l2_w1_n13_mux_dataout = sel_wire[9..9] & data_wire[2203..2203] # !(sel_wire[9..9]) & data_wire[2202..2202]; + l2_w1_n14_mux_dataout = sel_wire[9..9] & data_wire[2205..2205] # !(sel_wire[9..9]) & data_wire[2204..2204]; + l2_w1_n15_mux_dataout = sel_wire[9..9] & data_wire[2207..2207] # !(sel_wire[9..9]) & data_wire[2206..2206]; + l2_w1_n16_mux_dataout = sel_wire[9..9] & data_wire[2209..2209] # !(sel_wire[9..9]) & data_wire[2208..2208]; + l2_w1_n17_mux_dataout = sel_wire[9..9] & data_wire[2211..2211] # !(sel_wire[9..9]) & data_wire[2210..2210]; + l2_w1_n18_mux_dataout = sel_wire[9..9] & data_wire[2213..2213] # !(sel_wire[9..9]) & data_wire[2212..2212]; + l2_w1_n19_mux_dataout = sel_wire[9..9] & data_wire[2215..2215] # !(sel_wire[9..9]) & data_wire[2214..2214]; + l2_w1_n1_mux_dataout = sel_wire[9..9] & data_wire[2179..2179] # !(sel_wire[9..9]) & data_wire[2178..2178]; + l2_w1_n20_mux_dataout = sel_wire[9..9] & data_wire[2217..2217] # !(sel_wire[9..9]) & data_wire[2216..2216]; + l2_w1_n21_mux_dataout = sel_wire[9..9] & data_wire[2219..2219] # !(sel_wire[9..9]) & data_wire[2218..2218]; + l2_w1_n22_mux_dataout = sel_wire[9..9] & data_wire[2221..2221] # !(sel_wire[9..9]) & data_wire[2220..2220]; + l2_w1_n23_mux_dataout = sel_wire[9..9] & data_wire[2223..2223] # !(sel_wire[9..9]) & data_wire[2222..2222]; + l2_w1_n24_mux_dataout = sel_wire[9..9] & data_wire[2225..2225] # !(sel_wire[9..9]) & data_wire[2224..2224]; + l2_w1_n25_mux_dataout = sel_wire[9..9] & data_wire[2227..2227] # !(sel_wire[9..9]) & data_wire[2226..2226]; + l2_w1_n26_mux_dataout = sel_wire[9..9] & data_wire[2229..2229] # !(sel_wire[9..9]) & data_wire[2228..2228]; + l2_w1_n27_mux_dataout = sel_wire[9..9] & data_wire[2231..2231] # !(sel_wire[9..9]) & data_wire[2230..2230]; + l2_w1_n28_mux_dataout = sel_wire[9..9] & data_wire[2233..2233] # !(sel_wire[9..9]) & data_wire[2232..2232]; + l2_w1_n29_mux_dataout = sel_wire[9..9] & data_wire[2235..2235] # !(sel_wire[9..9]) & data_wire[2234..2234]; + l2_w1_n2_mux_dataout = sel_wire[9..9] & data_wire[2181..2181] # !(sel_wire[9..9]) & data_wire[2180..2180]; + l2_w1_n30_mux_dataout = sel_wire[9..9] & data_wire[2237..2237] # !(sel_wire[9..9]) & data_wire[2236..2236]; + l2_w1_n31_mux_dataout = sel_wire[9..9] & data_wire[2239..2239] # !(sel_wire[9..9]) & data_wire[2238..2238]; + l2_w1_n32_mux_dataout = sel_wire[9..9] & data_wire[2241..2241] # !(sel_wire[9..9]) & data_wire[2240..2240]; + l2_w1_n33_mux_dataout = sel_wire[9..9] & data_wire[2243..2243] # !(sel_wire[9..9]) & data_wire[2242..2242]; + l2_w1_n34_mux_dataout = sel_wire[9..9] & data_wire[2245..2245] # !(sel_wire[9..9]) & data_wire[2244..2244]; + l2_w1_n35_mux_dataout = sel_wire[9..9] & data_wire[2247..2247] # !(sel_wire[9..9]) & data_wire[2246..2246]; + l2_w1_n36_mux_dataout = sel_wire[9..9] & data_wire[2249..2249] # !(sel_wire[9..9]) & data_wire[2248..2248]; + l2_w1_n37_mux_dataout = sel_wire[9..9] & data_wire[2251..2251] # !(sel_wire[9..9]) & data_wire[2250..2250]; + l2_w1_n38_mux_dataout = sel_wire[9..9] & data_wire[2253..2253] # !(sel_wire[9..9]) & data_wire[2252..2252]; + l2_w1_n39_mux_dataout = sel_wire[9..9] & data_wire[2255..2255] # !(sel_wire[9..9]) & data_wire[2254..2254]; + l2_w1_n3_mux_dataout = sel_wire[9..9] & data_wire[2183..2183] # !(sel_wire[9..9]) & data_wire[2182..2182]; + l2_w1_n40_mux_dataout = sel_wire[9..9] & data_wire[2257..2257] # !(sel_wire[9..9]) & data_wire[2256..2256]; + l2_w1_n41_mux_dataout = sel_wire[9..9] & data_wire[2259..2259] # !(sel_wire[9..9]) & data_wire[2258..2258]; + l2_w1_n42_mux_dataout = sel_wire[9..9] & data_wire[2261..2261] # !(sel_wire[9..9]) & data_wire[2260..2260]; + l2_w1_n43_mux_dataout = sel_wire[9..9] & data_wire[2263..2263] # !(sel_wire[9..9]) & data_wire[2262..2262]; + l2_w1_n44_mux_dataout = sel_wire[9..9] & data_wire[2265..2265] # !(sel_wire[9..9]) & data_wire[2264..2264]; + l2_w1_n45_mux_dataout = sel_wire[9..9] & data_wire[2267..2267] # !(sel_wire[9..9]) & data_wire[2266..2266]; + l2_w1_n46_mux_dataout = sel_wire[9..9] & data_wire[2269..2269] # !(sel_wire[9..9]) & data_wire[2268..2268]; + l2_w1_n47_mux_dataout = sel_wire[9..9] & data_wire[2271..2271] # !(sel_wire[9..9]) & data_wire[2270..2270]; + l2_w1_n48_mux_dataout = sel_wire[9..9] & data_wire[2273..2273] # !(sel_wire[9..9]) & data_wire[2272..2272]; + l2_w1_n49_mux_dataout = sel_wire[9..9] & data_wire[2275..2275] # !(sel_wire[9..9]) & data_wire[2274..2274]; + l2_w1_n4_mux_dataout = sel_wire[9..9] & data_wire[2185..2185] # !(sel_wire[9..9]) & data_wire[2184..2184]; + l2_w1_n50_mux_dataout = sel_wire[9..9] & data_wire[2277..2277] # !(sel_wire[9..9]) & data_wire[2276..2276]; + l2_w1_n51_mux_dataout = sel_wire[9..9] & data_wire[2279..2279] # !(sel_wire[9..9]) & data_wire[2278..2278]; + l2_w1_n52_mux_dataout = sel_wire[9..9] & data_wire[2281..2281] # !(sel_wire[9..9]) & data_wire[2280..2280]; + l2_w1_n53_mux_dataout = sel_wire[9..9] & data_wire[2283..2283] # !(sel_wire[9..9]) & data_wire[2282..2282]; + l2_w1_n54_mux_dataout = sel_wire[9..9] & data_wire[2285..2285] # !(sel_wire[9..9]) & data_wire[2284..2284]; + l2_w1_n55_mux_dataout = sel_wire[9..9] & data_wire[2287..2287] # !(sel_wire[9..9]) & data_wire[2286..2286]; + l2_w1_n56_mux_dataout = sel_wire[9..9] & data_wire[2289..2289] # !(sel_wire[9..9]) & data_wire[2288..2288]; + l2_w1_n57_mux_dataout = sel_wire[9..9] & data_wire[2291..2291] # !(sel_wire[9..9]) & data_wire[2290..2290]; + l2_w1_n58_mux_dataout = sel_wire[9..9] & data_wire[2293..2293] # !(sel_wire[9..9]) & data_wire[2292..2292]; + l2_w1_n59_mux_dataout = sel_wire[9..9] & data_wire[2295..2295] # !(sel_wire[9..9]) & data_wire[2294..2294]; + l2_w1_n5_mux_dataout = sel_wire[9..9] & data_wire[2187..2187] # !(sel_wire[9..9]) & data_wire[2186..2186]; + l2_w1_n60_mux_dataout = sel_wire[9..9] & data_wire[2297..2297] # !(sel_wire[9..9]) & data_wire[2296..2296]; + l2_w1_n61_mux_dataout = sel_wire[9..9] & data_wire[2299..2299] # !(sel_wire[9..9]) & data_wire[2298..2298]; + l2_w1_n62_mux_dataout = sel_wire[9..9] & data_wire[2301..2301] # !(sel_wire[9..9]) & data_wire[2300..2300]; + l2_w1_n63_mux_dataout = sel_wire[9..9] & data_wire[2303..2303] # !(sel_wire[9..9]) & data_wire[2302..2302]; + l2_w1_n6_mux_dataout = sel_wire[9..9] & data_wire[2189..2189] # !(sel_wire[9..9]) & data_wire[2188..2188]; + l2_w1_n7_mux_dataout = sel_wire[9..9] & data_wire[2191..2191] # !(sel_wire[9..9]) & data_wire[2190..2190]; + l2_w1_n8_mux_dataout = sel_wire[9..9] & data_wire[2193..2193] # !(sel_wire[9..9]) & data_wire[2192..2192]; + l2_w1_n9_mux_dataout = sel_wire[9..9] & data_wire[2195..2195] # !(sel_wire[9..9]) & data_wire[2194..2194]; + l2_w2_n0_mux_dataout = sel_wire[9..9] & data_wire[2305..2305] # !(sel_wire[9..9]) & data_wire[2304..2304]; + l2_w2_n10_mux_dataout = sel_wire[9..9] & data_wire[2325..2325] # !(sel_wire[9..9]) & data_wire[2324..2324]; + l2_w2_n11_mux_dataout = sel_wire[9..9] & data_wire[2327..2327] # !(sel_wire[9..9]) & data_wire[2326..2326]; + l2_w2_n12_mux_dataout = sel_wire[9..9] & data_wire[2329..2329] # !(sel_wire[9..9]) & data_wire[2328..2328]; + l2_w2_n13_mux_dataout = sel_wire[9..9] & data_wire[2331..2331] # !(sel_wire[9..9]) & data_wire[2330..2330]; + l2_w2_n14_mux_dataout = sel_wire[9..9] & data_wire[2333..2333] # !(sel_wire[9..9]) & data_wire[2332..2332]; + l2_w2_n15_mux_dataout = sel_wire[9..9] & data_wire[2335..2335] # !(sel_wire[9..9]) & data_wire[2334..2334]; + l2_w2_n16_mux_dataout = sel_wire[9..9] & data_wire[2337..2337] # !(sel_wire[9..9]) & data_wire[2336..2336]; + l2_w2_n17_mux_dataout = sel_wire[9..9] & data_wire[2339..2339] # !(sel_wire[9..9]) & data_wire[2338..2338]; + l2_w2_n18_mux_dataout = sel_wire[9..9] & data_wire[2341..2341] # !(sel_wire[9..9]) & data_wire[2340..2340]; + l2_w2_n19_mux_dataout = sel_wire[9..9] & data_wire[2343..2343] # !(sel_wire[9..9]) & data_wire[2342..2342]; + l2_w2_n1_mux_dataout = sel_wire[9..9] & data_wire[2307..2307] # !(sel_wire[9..9]) & data_wire[2306..2306]; + l2_w2_n20_mux_dataout = sel_wire[9..9] & data_wire[2345..2345] # !(sel_wire[9..9]) & data_wire[2344..2344]; + l2_w2_n21_mux_dataout = sel_wire[9..9] & data_wire[2347..2347] # !(sel_wire[9..9]) & data_wire[2346..2346]; + l2_w2_n22_mux_dataout = sel_wire[9..9] & data_wire[2349..2349] # !(sel_wire[9..9]) & data_wire[2348..2348]; + l2_w2_n23_mux_dataout = sel_wire[9..9] & data_wire[2351..2351] # !(sel_wire[9..9]) & data_wire[2350..2350]; + l2_w2_n24_mux_dataout = sel_wire[9..9] & data_wire[2353..2353] # !(sel_wire[9..9]) & data_wire[2352..2352]; + l2_w2_n25_mux_dataout = sel_wire[9..9] & data_wire[2355..2355] # !(sel_wire[9..9]) & data_wire[2354..2354]; + l2_w2_n26_mux_dataout = sel_wire[9..9] & data_wire[2357..2357] # !(sel_wire[9..9]) & data_wire[2356..2356]; + l2_w2_n27_mux_dataout = sel_wire[9..9] & data_wire[2359..2359] # !(sel_wire[9..9]) & data_wire[2358..2358]; + l2_w2_n28_mux_dataout = sel_wire[9..9] & data_wire[2361..2361] # !(sel_wire[9..9]) & data_wire[2360..2360]; + l2_w2_n29_mux_dataout = sel_wire[9..9] & data_wire[2363..2363] # !(sel_wire[9..9]) & data_wire[2362..2362]; + l2_w2_n2_mux_dataout = sel_wire[9..9] & data_wire[2309..2309] # !(sel_wire[9..9]) & data_wire[2308..2308]; + l2_w2_n30_mux_dataout = sel_wire[9..9] & data_wire[2365..2365] # !(sel_wire[9..9]) & data_wire[2364..2364]; + l2_w2_n31_mux_dataout = sel_wire[9..9] & data_wire[2367..2367] # !(sel_wire[9..9]) & data_wire[2366..2366]; + l2_w2_n32_mux_dataout = sel_wire[9..9] & data_wire[2369..2369] # !(sel_wire[9..9]) & data_wire[2368..2368]; + l2_w2_n33_mux_dataout = sel_wire[9..9] & data_wire[2371..2371] # !(sel_wire[9..9]) & data_wire[2370..2370]; + l2_w2_n34_mux_dataout = sel_wire[9..9] & data_wire[2373..2373] # !(sel_wire[9..9]) & data_wire[2372..2372]; + l2_w2_n35_mux_dataout = sel_wire[9..9] & data_wire[2375..2375] # !(sel_wire[9..9]) & data_wire[2374..2374]; + l2_w2_n36_mux_dataout = sel_wire[9..9] & data_wire[2377..2377] # !(sel_wire[9..9]) & data_wire[2376..2376]; + l2_w2_n37_mux_dataout = sel_wire[9..9] & data_wire[2379..2379] # !(sel_wire[9..9]) & data_wire[2378..2378]; + l2_w2_n38_mux_dataout = sel_wire[9..9] & data_wire[2381..2381] # !(sel_wire[9..9]) & data_wire[2380..2380]; + l2_w2_n39_mux_dataout = sel_wire[9..9] & data_wire[2383..2383] # !(sel_wire[9..9]) & data_wire[2382..2382]; + l2_w2_n3_mux_dataout = sel_wire[9..9] & data_wire[2311..2311] # !(sel_wire[9..9]) & data_wire[2310..2310]; + l2_w2_n40_mux_dataout = sel_wire[9..9] & data_wire[2385..2385] # !(sel_wire[9..9]) & data_wire[2384..2384]; + l2_w2_n41_mux_dataout = sel_wire[9..9] & data_wire[2387..2387] # !(sel_wire[9..9]) & data_wire[2386..2386]; + l2_w2_n42_mux_dataout = sel_wire[9..9] & data_wire[2389..2389] # !(sel_wire[9..9]) & data_wire[2388..2388]; + l2_w2_n43_mux_dataout = sel_wire[9..9] & data_wire[2391..2391] # !(sel_wire[9..9]) & data_wire[2390..2390]; + l2_w2_n44_mux_dataout = sel_wire[9..9] & data_wire[2393..2393] # !(sel_wire[9..9]) & data_wire[2392..2392]; + l2_w2_n45_mux_dataout = sel_wire[9..9] & data_wire[2395..2395] # !(sel_wire[9..9]) & data_wire[2394..2394]; + l2_w2_n46_mux_dataout = sel_wire[9..9] & data_wire[2397..2397] # !(sel_wire[9..9]) & data_wire[2396..2396]; + l2_w2_n47_mux_dataout = sel_wire[9..9] & data_wire[2399..2399] # !(sel_wire[9..9]) & data_wire[2398..2398]; + l2_w2_n48_mux_dataout = sel_wire[9..9] & data_wire[2401..2401] # !(sel_wire[9..9]) & data_wire[2400..2400]; + l2_w2_n49_mux_dataout = sel_wire[9..9] & data_wire[2403..2403] # !(sel_wire[9..9]) & data_wire[2402..2402]; + l2_w2_n4_mux_dataout = sel_wire[9..9] & data_wire[2313..2313] # !(sel_wire[9..9]) & data_wire[2312..2312]; + l2_w2_n50_mux_dataout = sel_wire[9..9] & data_wire[2405..2405] # !(sel_wire[9..9]) & data_wire[2404..2404]; + l2_w2_n51_mux_dataout = sel_wire[9..9] & data_wire[2407..2407] # !(sel_wire[9..9]) & data_wire[2406..2406]; + l2_w2_n52_mux_dataout = sel_wire[9..9] & data_wire[2409..2409] # !(sel_wire[9..9]) & data_wire[2408..2408]; + l2_w2_n53_mux_dataout = sel_wire[9..9] & data_wire[2411..2411] # !(sel_wire[9..9]) & data_wire[2410..2410]; + l2_w2_n54_mux_dataout = sel_wire[9..9] & data_wire[2413..2413] # !(sel_wire[9..9]) & data_wire[2412..2412]; + l2_w2_n55_mux_dataout = sel_wire[9..9] & data_wire[2415..2415] # !(sel_wire[9..9]) & data_wire[2414..2414]; + l2_w2_n56_mux_dataout = sel_wire[9..9] & data_wire[2417..2417] # !(sel_wire[9..9]) & data_wire[2416..2416]; + l2_w2_n57_mux_dataout = sel_wire[9..9] & data_wire[2419..2419] # !(sel_wire[9..9]) & data_wire[2418..2418]; + l2_w2_n58_mux_dataout = sel_wire[9..9] & data_wire[2421..2421] # !(sel_wire[9..9]) & data_wire[2420..2420]; + l2_w2_n59_mux_dataout = sel_wire[9..9] & data_wire[2423..2423] # !(sel_wire[9..9]) & data_wire[2422..2422]; + l2_w2_n5_mux_dataout = sel_wire[9..9] & data_wire[2315..2315] # !(sel_wire[9..9]) & data_wire[2314..2314]; + l2_w2_n60_mux_dataout = sel_wire[9..9] & data_wire[2425..2425] # !(sel_wire[9..9]) & data_wire[2424..2424]; + l2_w2_n61_mux_dataout = sel_wire[9..9] & data_wire[2427..2427] # !(sel_wire[9..9]) & data_wire[2426..2426]; + l2_w2_n62_mux_dataout = sel_wire[9..9] & data_wire[2429..2429] # !(sel_wire[9..9]) & data_wire[2428..2428]; + l2_w2_n63_mux_dataout = sel_wire[9..9] & data_wire[2431..2431] # !(sel_wire[9..9]) & data_wire[2430..2430]; + l2_w2_n6_mux_dataout = sel_wire[9..9] & data_wire[2317..2317] # !(sel_wire[9..9]) & data_wire[2316..2316]; + l2_w2_n7_mux_dataout = sel_wire[9..9] & data_wire[2319..2319] # !(sel_wire[9..9]) & data_wire[2318..2318]; + l2_w2_n8_mux_dataout = sel_wire[9..9] & data_wire[2321..2321] # !(sel_wire[9..9]) & data_wire[2320..2320]; + l2_w2_n9_mux_dataout = sel_wire[9..9] & data_wire[2323..2323] # !(sel_wire[9..9]) & data_wire[2322..2322]; + l2_w3_n0_mux_dataout = sel_wire[9..9] & data_wire[2433..2433] # !(sel_wire[9..9]) & data_wire[2432..2432]; + l2_w3_n10_mux_dataout = sel_wire[9..9] & data_wire[2453..2453] # !(sel_wire[9..9]) & data_wire[2452..2452]; + l2_w3_n11_mux_dataout = sel_wire[9..9] & data_wire[2455..2455] # !(sel_wire[9..9]) & data_wire[2454..2454]; + l2_w3_n12_mux_dataout = sel_wire[9..9] & data_wire[2457..2457] # !(sel_wire[9..9]) & data_wire[2456..2456]; + l2_w3_n13_mux_dataout = sel_wire[9..9] & data_wire[2459..2459] # !(sel_wire[9..9]) & data_wire[2458..2458]; + l2_w3_n14_mux_dataout = sel_wire[9..9] & data_wire[2461..2461] # !(sel_wire[9..9]) & data_wire[2460..2460]; + l2_w3_n15_mux_dataout = sel_wire[9..9] & data_wire[2463..2463] # !(sel_wire[9..9]) & data_wire[2462..2462]; + l2_w3_n16_mux_dataout = sel_wire[9..9] & data_wire[2465..2465] # !(sel_wire[9..9]) & data_wire[2464..2464]; + l2_w3_n17_mux_dataout = sel_wire[9..9] & data_wire[2467..2467] # !(sel_wire[9..9]) & data_wire[2466..2466]; + l2_w3_n18_mux_dataout = sel_wire[9..9] & data_wire[2469..2469] # !(sel_wire[9..9]) & data_wire[2468..2468]; + l2_w3_n19_mux_dataout = sel_wire[9..9] & data_wire[2471..2471] # !(sel_wire[9..9]) & data_wire[2470..2470]; + l2_w3_n1_mux_dataout = sel_wire[9..9] & data_wire[2435..2435] # !(sel_wire[9..9]) & data_wire[2434..2434]; + l2_w3_n20_mux_dataout = sel_wire[9..9] & data_wire[2473..2473] # !(sel_wire[9..9]) & data_wire[2472..2472]; + l2_w3_n21_mux_dataout = sel_wire[9..9] & data_wire[2475..2475] # !(sel_wire[9..9]) & data_wire[2474..2474]; + l2_w3_n22_mux_dataout = sel_wire[9..9] & data_wire[2477..2477] # !(sel_wire[9..9]) & data_wire[2476..2476]; + l2_w3_n23_mux_dataout = sel_wire[9..9] & data_wire[2479..2479] # !(sel_wire[9..9]) & data_wire[2478..2478]; + l2_w3_n24_mux_dataout = sel_wire[9..9] & data_wire[2481..2481] # !(sel_wire[9..9]) & data_wire[2480..2480]; + l2_w3_n25_mux_dataout = sel_wire[9..9] & data_wire[2483..2483] # !(sel_wire[9..9]) & data_wire[2482..2482]; + l2_w3_n26_mux_dataout = sel_wire[9..9] & data_wire[2485..2485] # !(sel_wire[9..9]) & data_wire[2484..2484]; + l2_w3_n27_mux_dataout = sel_wire[9..9] & data_wire[2487..2487] # !(sel_wire[9..9]) & data_wire[2486..2486]; + l2_w3_n28_mux_dataout = sel_wire[9..9] & data_wire[2489..2489] # !(sel_wire[9..9]) & data_wire[2488..2488]; + l2_w3_n29_mux_dataout = sel_wire[9..9] & data_wire[2491..2491] # !(sel_wire[9..9]) & data_wire[2490..2490]; + l2_w3_n2_mux_dataout = sel_wire[9..9] & data_wire[2437..2437] # !(sel_wire[9..9]) & data_wire[2436..2436]; + l2_w3_n30_mux_dataout = sel_wire[9..9] & data_wire[2493..2493] # !(sel_wire[9..9]) & data_wire[2492..2492]; + l2_w3_n31_mux_dataout = sel_wire[9..9] & data_wire[2495..2495] # !(sel_wire[9..9]) & data_wire[2494..2494]; + l2_w3_n32_mux_dataout = sel_wire[9..9] & data_wire[2497..2497] # !(sel_wire[9..9]) & data_wire[2496..2496]; + l2_w3_n33_mux_dataout = sel_wire[9..9] & data_wire[2499..2499] # !(sel_wire[9..9]) & data_wire[2498..2498]; + l2_w3_n34_mux_dataout = sel_wire[9..9] & data_wire[2501..2501] # !(sel_wire[9..9]) & data_wire[2500..2500]; + l2_w3_n35_mux_dataout = sel_wire[9..9] & data_wire[2503..2503] # !(sel_wire[9..9]) & data_wire[2502..2502]; + l2_w3_n36_mux_dataout = sel_wire[9..9] & data_wire[2505..2505] # !(sel_wire[9..9]) & data_wire[2504..2504]; + l2_w3_n37_mux_dataout = sel_wire[9..9] & data_wire[2507..2507] # !(sel_wire[9..9]) & data_wire[2506..2506]; + l2_w3_n38_mux_dataout = sel_wire[9..9] & data_wire[2509..2509] # !(sel_wire[9..9]) & data_wire[2508..2508]; + l2_w3_n39_mux_dataout = sel_wire[9..9] & data_wire[2511..2511] # !(sel_wire[9..9]) & data_wire[2510..2510]; + l2_w3_n3_mux_dataout = sel_wire[9..9] & data_wire[2439..2439] # !(sel_wire[9..9]) & data_wire[2438..2438]; + l2_w3_n40_mux_dataout = sel_wire[9..9] & data_wire[2513..2513] # !(sel_wire[9..9]) & data_wire[2512..2512]; + l2_w3_n41_mux_dataout = sel_wire[9..9] & data_wire[2515..2515] # !(sel_wire[9..9]) & data_wire[2514..2514]; + l2_w3_n42_mux_dataout = sel_wire[9..9] & data_wire[2517..2517] # !(sel_wire[9..9]) & data_wire[2516..2516]; + l2_w3_n43_mux_dataout = sel_wire[9..9] & data_wire[2519..2519] # !(sel_wire[9..9]) & data_wire[2518..2518]; + l2_w3_n44_mux_dataout = sel_wire[9..9] & data_wire[2521..2521] # !(sel_wire[9..9]) & data_wire[2520..2520]; + l2_w3_n45_mux_dataout = sel_wire[9..9] & data_wire[2523..2523] # !(sel_wire[9..9]) & data_wire[2522..2522]; + l2_w3_n46_mux_dataout = sel_wire[9..9] & data_wire[2525..2525] # !(sel_wire[9..9]) & data_wire[2524..2524]; + l2_w3_n47_mux_dataout = sel_wire[9..9] & data_wire[2527..2527] # !(sel_wire[9..9]) & data_wire[2526..2526]; + l2_w3_n48_mux_dataout = sel_wire[9..9] & data_wire[2529..2529] # !(sel_wire[9..9]) & data_wire[2528..2528]; + l2_w3_n49_mux_dataout = sel_wire[9..9] & data_wire[2531..2531] # !(sel_wire[9..9]) & data_wire[2530..2530]; + l2_w3_n4_mux_dataout = sel_wire[9..9] & data_wire[2441..2441] # !(sel_wire[9..9]) & data_wire[2440..2440]; + l2_w3_n50_mux_dataout = sel_wire[9..9] & data_wire[2533..2533] # !(sel_wire[9..9]) & data_wire[2532..2532]; + l2_w3_n51_mux_dataout = sel_wire[9..9] & data_wire[2535..2535] # !(sel_wire[9..9]) & data_wire[2534..2534]; + l2_w3_n52_mux_dataout = sel_wire[9..9] & data_wire[2537..2537] # !(sel_wire[9..9]) & data_wire[2536..2536]; + l2_w3_n53_mux_dataout = sel_wire[9..9] & data_wire[2539..2539] # !(sel_wire[9..9]) & data_wire[2538..2538]; + l2_w3_n54_mux_dataout = sel_wire[9..9] & data_wire[2541..2541] # !(sel_wire[9..9]) & data_wire[2540..2540]; + l2_w3_n55_mux_dataout = sel_wire[9..9] & data_wire[2543..2543] # !(sel_wire[9..9]) & data_wire[2542..2542]; + l2_w3_n56_mux_dataout = sel_wire[9..9] & data_wire[2545..2545] # !(sel_wire[9..9]) & data_wire[2544..2544]; + l2_w3_n57_mux_dataout = sel_wire[9..9] & data_wire[2547..2547] # !(sel_wire[9..9]) & data_wire[2546..2546]; + l2_w3_n58_mux_dataout = sel_wire[9..9] & data_wire[2549..2549] # !(sel_wire[9..9]) & data_wire[2548..2548]; + l2_w3_n59_mux_dataout = sel_wire[9..9] & data_wire[2551..2551] # !(sel_wire[9..9]) & data_wire[2550..2550]; + l2_w3_n5_mux_dataout = sel_wire[9..9] & data_wire[2443..2443] # !(sel_wire[9..9]) & data_wire[2442..2442]; + l2_w3_n60_mux_dataout = sel_wire[9..9] & data_wire[2553..2553] # !(sel_wire[9..9]) & data_wire[2552..2552]; + l2_w3_n61_mux_dataout = sel_wire[9..9] & data_wire[2555..2555] # !(sel_wire[9..9]) & data_wire[2554..2554]; + l2_w3_n62_mux_dataout = sel_wire[9..9] & data_wire[2557..2557] # !(sel_wire[9..9]) & data_wire[2556..2556]; + l2_w3_n63_mux_dataout = sel_wire[9..9] & data_wire[2559..2559] # !(sel_wire[9..9]) & data_wire[2558..2558]; + l2_w3_n6_mux_dataout = sel_wire[9..9] & data_wire[2445..2445] # !(sel_wire[9..9]) & data_wire[2444..2444]; + l2_w3_n7_mux_dataout = sel_wire[9..9] & data_wire[2447..2447] # !(sel_wire[9..9]) & data_wire[2446..2446]; + l2_w3_n8_mux_dataout = sel_wire[9..9] & data_wire[2449..2449] # !(sel_wire[9..9]) & data_wire[2448..2448]; + l2_w3_n9_mux_dataout = sel_wire[9..9] & data_wire[2451..2451] # !(sel_wire[9..9]) & data_wire[2450..2450]; + l2_w4_n0_mux_dataout = sel_wire[9..9] & data_wire[2561..2561] # !(sel_wire[9..9]) & data_wire[2560..2560]; + l2_w4_n10_mux_dataout = sel_wire[9..9] & data_wire[2581..2581] # !(sel_wire[9..9]) & data_wire[2580..2580]; + l2_w4_n11_mux_dataout = sel_wire[9..9] & data_wire[2583..2583] # !(sel_wire[9..9]) & data_wire[2582..2582]; + l2_w4_n12_mux_dataout = sel_wire[9..9] & data_wire[2585..2585] # !(sel_wire[9..9]) & data_wire[2584..2584]; + l2_w4_n13_mux_dataout = sel_wire[9..9] & data_wire[2587..2587] # !(sel_wire[9..9]) & data_wire[2586..2586]; + l2_w4_n14_mux_dataout = sel_wire[9..9] & data_wire[2589..2589] # !(sel_wire[9..9]) & data_wire[2588..2588]; + l2_w4_n15_mux_dataout = sel_wire[9..9] & data_wire[2591..2591] # !(sel_wire[9..9]) & data_wire[2590..2590]; + l2_w4_n16_mux_dataout = sel_wire[9..9] & data_wire[2593..2593] # !(sel_wire[9..9]) & data_wire[2592..2592]; + l2_w4_n17_mux_dataout = sel_wire[9..9] & data_wire[2595..2595] # !(sel_wire[9..9]) & data_wire[2594..2594]; + l2_w4_n18_mux_dataout = sel_wire[9..9] & data_wire[2597..2597] # !(sel_wire[9..9]) & data_wire[2596..2596]; + l2_w4_n19_mux_dataout = sel_wire[9..9] & data_wire[2599..2599] # !(sel_wire[9..9]) & data_wire[2598..2598]; + l2_w4_n1_mux_dataout = sel_wire[9..9] & data_wire[2563..2563] # !(sel_wire[9..9]) & data_wire[2562..2562]; + l2_w4_n20_mux_dataout = sel_wire[9..9] & data_wire[2601..2601] # !(sel_wire[9..9]) & data_wire[2600..2600]; + l2_w4_n21_mux_dataout = sel_wire[9..9] & data_wire[2603..2603] # !(sel_wire[9..9]) & data_wire[2602..2602]; + l2_w4_n22_mux_dataout = sel_wire[9..9] & data_wire[2605..2605] # !(sel_wire[9..9]) & data_wire[2604..2604]; + l2_w4_n23_mux_dataout = sel_wire[9..9] & data_wire[2607..2607] # !(sel_wire[9..9]) & data_wire[2606..2606]; + l2_w4_n24_mux_dataout = sel_wire[9..9] & data_wire[2609..2609] # !(sel_wire[9..9]) & data_wire[2608..2608]; + l2_w4_n25_mux_dataout = sel_wire[9..9] & data_wire[2611..2611] # !(sel_wire[9..9]) & data_wire[2610..2610]; + l2_w4_n26_mux_dataout = sel_wire[9..9] & data_wire[2613..2613] # !(sel_wire[9..9]) & data_wire[2612..2612]; + l2_w4_n27_mux_dataout = sel_wire[9..9] & data_wire[2615..2615] # !(sel_wire[9..9]) & data_wire[2614..2614]; + l2_w4_n28_mux_dataout = sel_wire[9..9] & data_wire[2617..2617] # !(sel_wire[9..9]) & data_wire[2616..2616]; + l2_w4_n29_mux_dataout = sel_wire[9..9] & data_wire[2619..2619] # !(sel_wire[9..9]) & data_wire[2618..2618]; + l2_w4_n2_mux_dataout = sel_wire[9..9] & data_wire[2565..2565] # !(sel_wire[9..9]) & data_wire[2564..2564]; + l2_w4_n30_mux_dataout = sel_wire[9..9] & data_wire[2621..2621] # !(sel_wire[9..9]) & data_wire[2620..2620]; + l2_w4_n31_mux_dataout = sel_wire[9..9] & data_wire[2623..2623] # !(sel_wire[9..9]) & data_wire[2622..2622]; + l2_w4_n32_mux_dataout = sel_wire[9..9] & data_wire[2625..2625] # !(sel_wire[9..9]) & data_wire[2624..2624]; + l2_w4_n33_mux_dataout = sel_wire[9..9] & data_wire[2627..2627] # !(sel_wire[9..9]) & data_wire[2626..2626]; + l2_w4_n34_mux_dataout = sel_wire[9..9] & data_wire[2629..2629] # !(sel_wire[9..9]) & data_wire[2628..2628]; + l2_w4_n35_mux_dataout = sel_wire[9..9] & data_wire[2631..2631] # !(sel_wire[9..9]) & data_wire[2630..2630]; + l2_w4_n36_mux_dataout = sel_wire[9..9] & data_wire[2633..2633] # !(sel_wire[9..9]) & data_wire[2632..2632]; + l2_w4_n37_mux_dataout = sel_wire[9..9] & data_wire[2635..2635] # !(sel_wire[9..9]) & data_wire[2634..2634]; + l2_w4_n38_mux_dataout = sel_wire[9..9] & data_wire[2637..2637] # !(sel_wire[9..9]) & data_wire[2636..2636]; + l2_w4_n39_mux_dataout = sel_wire[9..9] & data_wire[2639..2639] # !(sel_wire[9..9]) & data_wire[2638..2638]; + l2_w4_n3_mux_dataout = sel_wire[9..9] & data_wire[2567..2567] # !(sel_wire[9..9]) & data_wire[2566..2566]; + l2_w4_n40_mux_dataout = sel_wire[9..9] & data_wire[2641..2641] # !(sel_wire[9..9]) & data_wire[2640..2640]; + l2_w4_n41_mux_dataout = sel_wire[9..9] & data_wire[2643..2643] # !(sel_wire[9..9]) & data_wire[2642..2642]; + l2_w4_n42_mux_dataout = sel_wire[9..9] & data_wire[2645..2645] # !(sel_wire[9..9]) & data_wire[2644..2644]; + l2_w4_n43_mux_dataout = sel_wire[9..9] & data_wire[2647..2647] # !(sel_wire[9..9]) & data_wire[2646..2646]; + l2_w4_n44_mux_dataout = sel_wire[9..9] & data_wire[2649..2649] # !(sel_wire[9..9]) & data_wire[2648..2648]; + l2_w4_n45_mux_dataout = sel_wire[9..9] & data_wire[2651..2651] # !(sel_wire[9..9]) & data_wire[2650..2650]; + l2_w4_n46_mux_dataout = sel_wire[9..9] & data_wire[2653..2653] # !(sel_wire[9..9]) & data_wire[2652..2652]; + l2_w4_n47_mux_dataout = sel_wire[9..9] & data_wire[2655..2655] # !(sel_wire[9..9]) & data_wire[2654..2654]; + l2_w4_n48_mux_dataout = sel_wire[9..9] & data_wire[2657..2657] # !(sel_wire[9..9]) & data_wire[2656..2656]; + l2_w4_n49_mux_dataout = sel_wire[9..9] & data_wire[2659..2659] # !(sel_wire[9..9]) & data_wire[2658..2658]; + l2_w4_n4_mux_dataout = sel_wire[9..9] & data_wire[2569..2569] # !(sel_wire[9..9]) & data_wire[2568..2568]; + l2_w4_n50_mux_dataout = sel_wire[9..9] & data_wire[2661..2661] # !(sel_wire[9..9]) & data_wire[2660..2660]; + l2_w4_n51_mux_dataout = sel_wire[9..9] & data_wire[2663..2663] # !(sel_wire[9..9]) & data_wire[2662..2662]; + l2_w4_n52_mux_dataout = sel_wire[9..9] & data_wire[2665..2665] # !(sel_wire[9..9]) & data_wire[2664..2664]; + l2_w4_n53_mux_dataout = sel_wire[9..9] & data_wire[2667..2667] # !(sel_wire[9..9]) & data_wire[2666..2666]; + l2_w4_n54_mux_dataout = sel_wire[9..9] & data_wire[2669..2669] # !(sel_wire[9..9]) & data_wire[2668..2668]; + l2_w4_n55_mux_dataout = sel_wire[9..9] & data_wire[2671..2671] # !(sel_wire[9..9]) & data_wire[2670..2670]; + l2_w4_n56_mux_dataout = sel_wire[9..9] & data_wire[2673..2673] # !(sel_wire[9..9]) & data_wire[2672..2672]; + l2_w4_n57_mux_dataout = sel_wire[9..9] & data_wire[2675..2675] # !(sel_wire[9..9]) & data_wire[2674..2674]; + l2_w4_n58_mux_dataout = sel_wire[9..9] & data_wire[2677..2677] # !(sel_wire[9..9]) & data_wire[2676..2676]; + l2_w4_n59_mux_dataout = sel_wire[9..9] & data_wire[2679..2679] # !(sel_wire[9..9]) & data_wire[2678..2678]; + l2_w4_n5_mux_dataout = sel_wire[9..9] & data_wire[2571..2571] # !(sel_wire[9..9]) & data_wire[2570..2570]; + l2_w4_n60_mux_dataout = sel_wire[9..9] & data_wire[2681..2681] # !(sel_wire[9..9]) & data_wire[2680..2680]; + l2_w4_n61_mux_dataout = sel_wire[9..9] & data_wire[2683..2683] # !(sel_wire[9..9]) & data_wire[2682..2682]; + l2_w4_n62_mux_dataout = sel_wire[9..9] & data_wire[2685..2685] # !(sel_wire[9..9]) & data_wire[2684..2684]; + l2_w4_n63_mux_dataout = sel_wire[9..9] & data_wire[2687..2687] # !(sel_wire[9..9]) & data_wire[2686..2686]; + l2_w4_n6_mux_dataout = sel_wire[9..9] & data_wire[2573..2573] # !(sel_wire[9..9]) & data_wire[2572..2572]; + l2_w4_n7_mux_dataout = sel_wire[9..9] & data_wire[2575..2575] # !(sel_wire[9..9]) & data_wire[2574..2574]; + l2_w4_n8_mux_dataout = sel_wire[9..9] & data_wire[2577..2577] # !(sel_wire[9..9]) & data_wire[2576..2576]; + l2_w4_n9_mux_dataout = sel_wire[9..9] & data_wire[2579..2579] # !(sel_wire[9..9]) & data_wire[2578..2578]; + l2_w5_n0_mux_dataout = sel_wire[9..9] & data_wire[2689..2689] # !(sel_wire[9..9]) & data_wire[2688..2688]; + l2_w5_n10_mux_dataout = sel_wire[9..9] & data_wire[2709..2709] # !(sel_wire[9..9]) & data_wire[2708..2708]; + l2_w5_n11_mux_dataout = sel_wire[9..9] & data_wire[2711..2711] # !(sel_wire[9..9]) & data_wire[2710..2710]; + l2_w5_n12_mux_dataout = sel_wire[9..9] & data_wire[2713..2713] # !(sel_wire[9..9]) & data_wire[2712..2712]; + l2_w5_n13_mux_dataout = sel_wire[9..9] & data_wire[2715..2715] # !(sel_wire[9..9]) & data_wire[2714..2714]; + l2_w5_n14_mux_dataout = sel_wire[9..9] & data_wire[2717..2717] # !(sel_wire[9..9]) & data_wire[2716..2716]; + l2_w5_n15_mux_dataout = sel_wire[9..9] & data_wire[2719..2719] # !(sel_wire[9..9]) & data_wire[2718..2718]; + l2_w5_n16_mux_dataout = sel_wire[9..9] & data_wire[2721..2721] # !(sel_wire[9..9]) & data_wire[2720..2720]; + l2_w5_n17_mux_dataout = sel_wire[9..9] & data_wire[2723..2723] # !(sel_wire[9..9]) & data_wire[2722..2722]; + l2_w5_n18_mux_dataout = sel_wire[9..9] & data_wire[2725..2725] # !(sel_wire[9..9]) & data_wire[2724..2724]; + l2_w5_n19_mux_dataout = sel_wire[9..9] & data_wire[2727..2727] # !(sel_wire[9..9]) & data_wire[2726..2726]; + l2_w5_n1_mux_dataout = sel_wire[9..9] & data_wire[2691..2691] # !(sel_wire[9..9]) & data_wire[2690..2690]; + l2_w5_n20_mux_dataout = sel_wire[9..9] & data_wire[2729..2729] # !(sel_wire[9..9]) & data_wire[2728..2728]; + l2_w5_n21_mux_dataout = sel_wire[9..9] & data_wire[2731..2731] # !(sel_wire[9..9]) & data_wire[2730..2730]; + l2_w5_n22_mux_dataout = sel_wire[9..9] & data_wire[2733..2733] # !(sel_wire[9..9]) & data_wire[2732..2732]; + l2_w5_n23_mux_dataout = sel_wire[9..9] & data_wire[2735..2735] # !(sel_wire[9..9]) & data_wire[2734..2734]; + l2_w5_n24_mux_dataout = sel_wire[9..9] & data_wire[2737..2737] # !(sel_wire[9..9]) & data_wire[2736..2736]; + l2_w5_n25_mux_dataout = sel_wire[9..9] & data_wire[2739..2739] # !(sel_wire[9..9]) & data_wire[2738..2738]; + l2_w5_n26_mux_dataout = sel_wire[9..9] & data_wire[2741..2741] # !(sel_wire[9..9]) & data_wire[2740..2740]; + l2_w5_n27_mux_dataout = sel_wire[9..9] & data_wire[2743..2743] # !(sel_wire[9..9]) & data_wire[2742..2742]; + l2_w5_n28_mux_dataout = sel_wire[9..9] & data_wire[2745..2745] # !(sel_wire[9..9]) & data_wire[2744..2744]; + l2_w5_n29_mux_dataout = sel_wire[9..9] & data_wire[2747..2747] # !(sel_wire[9..9]) & data_wire[2746..2746]; + l2_w5_n2_mux_dataout = sel_wire[9..9] & data_wire[2693..2693] # !(sel_wire[9..9]) & data_wire[2692..2692]; + l2_w5_n30_mux_dataout = sel_wire[9..9] & data_wire[2749..2749] # !(sel_wire[9..9]) & data_wire[2748..2748]; + l2_w5_n31_mux_dataout = sel_wire[9..9] & data_wire[2751..2751] # !(sel_wire[9..9]) & data_wire[2750..2750]; + l2_w5_n32_mux_dataout = sel_wire[9..9] & data_wire[2753..2753] # !(sel_wire[9..9]) & data_wire[2752..2752]; + l2_w5_n33_mux_dataout = sel_wire[9..9] & data_wire[2755..2755] # !(sel_wire[9..9]) & data_wire[2754..2754]; + l2_w5_n34_mux_dataout = sel_wire[9..9] & data_wire[2757..2757] # !(sel_wire[9..9]) & data_wire[2756..2756]; + l2_w5_n35_mux_dataout = sel_wire[9..9] & data_wire[2759..2759] # !(sel_wire[9..9]) & data_wire[2758..2758]; + l2_w5_n36_mux_dataout = sel_wire[9..9] & data_wire[2761..2761] # !(sel_wire[9..9]) & data_wire[2760..2760]; + l2_w5_n37_mux_dataout = sel_wire[9..9] & data_wire[2763..2763] # !(sel_wire[9..9]) & data_wire[2762..2762]; + l2_w5_n38_mux_dataout = sel_wire[9..9] & data_wire[2765..2765] # !(sel_wire[9..9]) & data_wire[2764..2764]; + l2_w5_n39_mux_dataout = sel_wire[9..9] & data_wire[2767..2767] # !(sel_wire[9..9]) & data_wire[2766..2766]; + l2_w5_n3_mux_dataout = sel_wire[9..9] & data_wire[2695..2695] # !(sel_wire[9..9]) & data_wire[2694..2694]; + l2_w5_n40_mux_dataout = sel_wire[9..9] & data_wire[2769..2769] # !(sel_wire[9..9]) & data_wire[2768..2768]; + l2_w5_n41_mux_dataout = sel_wire[9..9] & data_wire[2771..2771] # !(sel_wire[9..9]) & data_wire[2770..2770]; + l2_w5_n42_mux_dataout = sel_wire[9..9] & data_wire[2773..2773] # !(sel_wire[9..9]) & data_wire[2772..2772]; + l2_w5_n43_mux_dataout = sel_wire[9..9] & data_wire[2775..2775] # !(sel_wire[9..9]) & data_wire[2774..2774]; + l2_w5_n44_mux_dataout = sel_wire[9..9] & data_wire[2777..2777] # !(sel_wire[9..9]) & data_wire[2776..2776]; + l2_w5_n45_mux_dataout = sel_wire[9..9] & data_wire[2779..2779] # !(sel_wire[9..9]) & data_wire[2778..2778]; + l2_w5_n46_mux_dataout = sel_wire[9..9] & data_wire[2781..2781] # !(sel_wire[9..9]) & data_wire[2780..2780]; + l2_w5_n47_mux_dataout = sel_wire[9..9] & data_wire[2783..2783] # !(sel_wire[9..9]) & data_wire[2782..2782]; + l2_w5_n48_mux_dataout = sel_wire[9..9] & data_wire[2785..2785] # !(sel_wire[9..9]) & data_wire[2784..2784]; + l2_w5_n49_mux_dataout = sel_wire[9..9] & data_wire[2787..2787] # !(sel_wire[9..9]) & data_wire[2786..2786]; + l2_w5_n4_mux_dataout = sel_wire[9..9] & data_wire[2697..2697] # !(sel_wire[9..9]) & data_wire[2696..2696]; + l2_w5_n50_mux_dataout = sel_wire[9..9] & data_wire[2789..2789] # !(sel_wire[9..9]) & data_wire[2788..2788]; + l2_w5_n51_mux_dataout = sel_wire[9..9] & data_wire[2791..2791] # !(sel_wire[9..9]) & data_wire[2790..2790]; + l2_w5_n52_mux_dataout = sel_wire[9..9] & data_wire[2793..2793] # !(sel_wire[9..9]) & data_wire[2792..2792]; + l2_w5_n53_mux_dataout = sel_wire[9..9] & data_wire[2795..2795] # !(sel_wire[9..9]) & data_wire[2794..2794]; + l2_w5_n54_mux_dataout = sel_wire[9..9] & data_wire[2797..2797] # !(sel_wire[9..9]) & data_wire[2796..2796]; + l2_w5_n55_mux_dataout = sel_wire[9..9] & data_wire[2799..2799] # !(sel_wire[9..9]) & data_wire[2798..2798]; + l2_w5_n56_mux_dataout = sel_wire[9..9] & data_wire[2801..2801] # !(sel_wire[9..9]) & data_wire[2800..2800]; + l2_w5_n57_mux_dataout = sel_wire[9..9] & data_wire[2803..2803] # !(sel_wire[9..9]) & data_wire[2802..2802]; + l2_w5_n58_mux_dataout = sel_wire[9..9] & data_wire[2805..2805] # !(sel_wire[9..9]) & data_wire[2804..2804]; + l2_w5_n59_mux_dataout = sel_wire[9..9] & data_wire[2807..2807] # !(sel_wire[9..9]) & data_wire[2806..2806]; + l2_w5_n5_mux_dataout = sel_wire[9..9] & data_wire[2699..2699] # !(sel_wire[9..9]) & data_wire[2698..2698]; + l2_w5_n60_mux_dataout = sel_wire[9..9] & data_wire[2809..2809] # !(sel_wire[9..9]) & data_wire[2808..2808]; + l2_w5_n61_mux_dataout = sel_wire[9..9] & data_wire[2811..2811] # !(sel_wire[9..9]) & data_wire[2810..2810]; + l2_w5_n62_mux_dataout = sel_wire[9..9] & data_wire[2813..2813] # !(sel_wire[9..9]) & data_wire[2812..2812]; + l2_w5_n63_mux_dataout = sel_wire[9..9] & data_wire[2815..2815] # !(sel_wire[9..9]) & data_wire[2814..2814]; + l2_w5_n6_mux_dataout = sel_wire[9..9] & data_wire[2701..2701] # !(sel_wire[9..9]) & data_wire[2700..2700]; + l2_w5_n7_mux_dataout = sel_wire[9..9] & data_wire[2703..2703] # !(sel_wire[9..9]) & data_wire[2702..2702]; + l2_w5_n8_mux_dataout = sel_wire[9..9] & data_wire[2705..2705] # !(sel_wire[9..9]) & data_wire[2704..2704]; + l2_w5_n9_mux_dataout = sel_wire[9..9] & data_wire[2707..2707] # !(sel_wire[9..9]) & data_wire[2706..2706]; + l2_w6_n0_mux_dataout = sel_wire[9..9] & data_wire[2817..2817] # !(sel_wire[9..9]) & data_wire[2816..2816]; + l2_w6_n10_mux_dataout = sel_wire[9..9] & data_wire[2837..2837] # !(sel_wire[9..9]) & data_wire[2836..2836]; + l2_w6_n11_mux_dataout = sel_wire[9..9] & data_wire[2839..2839] # !(sel_wire[9..9]) & data_wire[2838..2838]; + l2_w6_n12_mux_dataout = sel_wire[9..9] & data_wire[2841..2841] # !(sel_wire[9..9]) & data_wire[2840..2840]; + l2_w6_n13_mux_dataout = sel_wire[9..9] & data_wire[2843..2843] # !(sel_wire[9..9]) & data_wire[2842..2842]; + l2_w6_n14_mux_dataout = sel_wire[9..9] & data_wire[2845..2845] # !(sel_wire[9..9]) & data_wire[2844..2844]; + l2_w6_n15_mux_dataout = sel_wire[9..9] & data_wire[2847..2847] # !(sel_wire[9..9]) & data_wire[2846..2846]; + l2_w6_n16_mux_dataout = sel_wire[9..9] & data_wire[2849..2849] # !(sel_wire[9..9]) & data_wire[2848..2848]; + l2_w6_n17_mux_dataout = sel_wire[9..9] & data_wire[2851..2851] # !(sel_wire[9..9]) & data_wire[2850..2850]; + l2_w6_n18_mux_dataout = sel_wire[9..9] & data_wire[2853..2853] # !(sel_wire[9..9]) & data_wire[2852..2852]; + l2_w6_n19_mux_dataout = sel_wire[9..9] & data_wire[2855..2855] # !(sel_wire[9..9]) & data_wire[2854..2854]; + l2_w6_n1_mux_dataout = sel_wire[9..9] & data_wire[2819..2819] # !(sel_wire[9..9]) & data_wire[2818..2818]; + l2_w6_n20_mux_dataout = sel_wire[9..9] & data_wire[2857..2857] # !(sel_wire[9..9]) & data_wire[2856..2856]; + l2_w6_n21_mux_dataout = sel_wire[9..9] & data_wire[2859..2859] # !(sel_wire[9..9]) & data_wire[2858..2858]; + l2_w6_n22_mux_dataout = sel_wire[9..9] & data_wire[2861..2861] # !(sel_wire[9..9]) & data_wire[2860..2860]; + l2_w6_n23_mux_dataout = sel_wire[9..9] & data_wire[2863..2863] # !(sel_wire[9..9]) & data_wire[2862..2862]; + l2_w6_n24_mux_dataout = sel_wire[9..9] & data_wire[2865..2865] # !(sel_wire[9..9]) & data_wire[2864..2864]; + l2_w6_n25_mux_dataout = sel_wire[9..9] & data_wire[2867..2867] # !(sel_wire[9..9]) & data_wire[2866..2866]; + l2_w6_n26_mux_dataout = sel_wire[9..9] & data_wire[2869..2869] # !(sel_wire[9..9]) & data_wire[2868..2868]; + l2_w6_n27_mux_dataout = sel_wire[9..9] & data_wire[2871..2871] # !(sel_wire[9..9]) & data_wire[2870..2870]; + l2_w6_n28_mux_dataout = sel_wire[9..9] & data_wire[2873..2873] # !(sel_wire[9..9]) & data_wire[2872..2872]; + l2_w6_n29_mux_dataout = sel_wire[9..9] & data_wire[2875..2875] # !(sel_wire[9..9]) & data_wire[2874..2874]; + l2_w6_n2_mux_dataout = sel_wire[9..9] & data_wire[2821..2821] # !(sel_wire[9..9]) & data_wire[2820..2820]; + l2_w6_n30_mux_dataout = sel_wire[9..9] & data_wire[2877..2877] # !(sel_wire[9..9]) & data_wire[2876..2876]; + l2_w6_n31_mux_dataout = sel_wire[9..9] & data_wire[2879..2879] # !(sel_wire[9..9]) & data_wire[2878..2878]; + l2_w6_n32_mux_dataout = sel_wire[9..9] & data_wire[2881..2881] # !(sel_wire[9..9]) & data_wire[2880..2880]; + l2_w6_n33_mux_dataout = sel_wire[9..9] & data_wire[2883..2883] # !(sel_wire[9..9]) & data_wire[2882..2882]; + l2_w6_n34_mux_dataout = sel_wire[9..9] & data_wire[2885..2885] # !(sel_wire[9..9]) & data_wire[2884..2884]; + l2_w6_n35_mux_dataout = sel_wire[9..9] & data_wire[2887..2887] # !(sel_wire[9..9]) & data_wire[2886..2886]; + l2_w6_n36_mux_dataout = sel_wire[9..9] & data_wire[2889..2889] # !(sel_wire[9..9]) & data_wire[2888..2888]; + l2_w6_n37_mux_dataout = sel_wire[9..9] & data_wire[2891..2891] # !(sel_wire[9..9]) & data_wire[2890..2890]; + l2_w6_n38_mux_dataout = sel_wire[9..9] & data_wire[2893..2893] # !(sel_wire[9..9]) & data_wire[2892..2892]; + l2_w6_n39_mux_dataout = sel_wire[9..9] & data_wire[2895..2895] # !(sel_wire[9..9]) & data_wire[2894..2894]; + l2_w6_n3_mux_dataout = sel_wire[9..9] & data_wire[2823..2823] # !(sel_wire[9..9]) & data_wire[2822..2822]; + l2_w6_n40_mux_dataout = sel_wire[9..9] & data_wire[2897..2897] # !(sel_wire[9..9]) & data_wire[2896..2896]; + l2_w6_n41_mux_dataout = sel_wire[9..9] & data_wire[2899..2899] # !(sel_wire[9..9]) & data_wire[2898..2898]; + l2_w6_n42_mux_dataout = sel_wire[9..9] & data_wire[2901..2901] # !(sel_wire[9..9]) & data_wire[2900..2900]; + l2_w6_n43_mux_dataout = sel_wire[9..9] & data_wire[2903..2903] # !(sel_wire[9..9]) & data_wire[2902..2902]; + l2_w6_n44_mux_dataout = sel_wire[9..9] & data_wire[2905..2905] # !(sel_wire[9..9]) & data_wire[2904..2904]; + l2_w6_n45_mux_dataout = sel_wire[9..9] & data_wire[2907..2907] # !(sel_wire[9..9]) & data_wire[2906..2906]; + l2_w6_n46_mux_dataout = sel_wire[9..9] & data_wire[2909..2909] # !(sel_wire[9..9]) & data_wire[2908..2908]; + l2_w6_n47_mux_dataout = sel_wire[9..9] & data_wire[2911..2911] # !(sel_wire[9..9]) & data_wire[2910..2910]; + l2_w6_n48_mux_dataout = sel_wire[9..9] & data_wire[2913..2913] # !(sel_wire[9..9]) & data_wire[2912..2912]; + l2_w6_n49_mux_dataout = sel_wire[9..9] & data_wire[2915..2915] # !(sel_wire[9..9]) & data_wire[2914..2914]; + l2_w6_n4_mux_dataout = sel_wire[9..9] & data_wire[2825..2825] # !(sel_wire[9..9]) & data_wire[2824..2824]; + l2_w6_n50_mux_dataout = sel_wire[9..9] & data_wire[2917..2917] # !(sel_wire[9..9]) & data_wire[2916..2916]; + l2_w6_n51_mux_dataout = sel_wire[9..9] & data_wire[2919..2919] # !(sel_wire[9..9]) & data_wire[2918..2918]; + l2_w6_n52_mux_dataout = sel_wire[9..9] & data_wire[2921..2921] # !(sel_wire[9..9]) & data_wire[2920..2920]; + l2_w6_n53_mux_dataout = sel_wire[9..9] & data_wire[2923..2923] # !(sel_wire[9..9]) & data_wire[2922..2922]; + l2_w6_n54_mux_dataout = sel_wire[9..9] & data_wire[2925..2925] # !(sel_wire[9..9]) & data_wire[2924..2924]; + l2_w6_n55_mux_dataout = sel_wire[9..9] & data_wire[2927..2927] # !(sel_wire[9..9]) & data_wire[2926..2926]; + l2_w6_n56_mux_dataout = sel_wire[9..9] & data_wire[2929..2929] # !(sel_wire[9..9]) & data_wire[2928..2928]; + l2_w6_n57_mux_dataout = sel_wire[9..9] & data_wire[2931..2931] # !(sel_wire[9..9]) & data_wire[2930..2930]; + l2_w6_n58_mux_dataout = sel_wire[9..9] & data_wire[2933..2933] # !(sel_wire[9..9]) & data_wire[2932..2932]; + l2_w6_n59_mux_dataout = sel_wire[9..9] & data_wire[2935..2935] # !(sel_wire[9..9]) & data_wire[2934..2934]; + l2_w6_n5_mux_dataout = sel_wire[9..9] & data_wire[2827..2827] # !(sel_wire[9..9]) & data_wire[2826..2826]; + l2_w6_n60_mux_dataout = sel_wire[9..9] & data_wire[2937..2937] # !(sel_wire[9..9]) & data_wire[2936..2936]; + l2_w6_n61_mux_dataout = sel_wire[9..9] & data_wire[2939..2939] # !(sel_wire[9..9]) & data_wire[2938..2938]; + l2_w6_n62_mux_dataout = sel_wire[9..9] & data_wire[2941..2941] # !(sel_wire[9..9]) & data_wire[2940..2940]; + l2_w6_n63_mux_dataout = sel_wire[9..9] & data_wire[2943..2943] # !(sel_wire[9..9]) & data_wire[2942..2942]; + l2_w6_n6_mux_dataout = sel_wire[9..9] & data_wire[2829..2829] # !(sel_wire[9..9]) & data_wire[2828..2828]; + l2_w6_n7_mux_dataout = sel_wire[9..9] & data_wire[2831..2831] # !(sel_wire[9..9]) & data_wire[2830..2830]; + l2_w6_n8_mux_dataout = sel_wire[9..9] & data_wire[2833..2833] # !(sel_wire[9..9]) & data_wire[2832..2832]; + l2_w6_n9_mux_dataout = sel_wire[9..9] & data_wire[2835..2835] # !(sel_wire[9..9]) & data_wire[2834..2834]; + l2_w7_n0_mux_dataout = sel_wire[9..9] & data_wire[2945..2945] # !(sel_wire[9..9]) & data_wire[2944..2944]; + l2_w7_n10_mux_dataout = sel_wire[9..9] & data_wire[2965..2965] # !(sel_wire[9..9]) & data_wire[2964..2964]; + l2_w7_n11_mux_dataout = sel_wire[9..9] & data_wire[2967..2967] # !(sel_wire[9..9]) & data_wire[2966..2966]; + l2_w7_n12_mux_dataout = sel_wire[9..9] & data_wire[2969..2969] # !(sel_wire[9..9]) & data_wire[2968..2968]; + l2_w7_n13_mux_dataout = sel_wire[9..9] & data_wire[2971..2971] # !(sel_wire[9..9]) & data_wire[2970..2970]; + l2_w7_n14_mux_dataout = sel_wire[9..9] & data_wire[2973..2973] # !(sel_wire[9..9]) & data_wire[2972..2972]; + l2_w7_n15_mux_dataout = sel_wire[9..9] & data_wire[2975..2975] # !(sel_wire[9..9]) & data_wire[2974..2974]; + l2_w7_n16_mux_dataout = sel_wire[9..9] & data_wire[2977..2977] # !(sel_wire[9..9]) & data_wire[2976..2976]; + l2_w7_n17_mux_dataout = sel_wire[9..9] & data_wire[2979..2979] # !(sel_wire[9..9]) & data_wire[2978..2978]; + l2_w7_n18_mux_dataout = sel_wire[9..9] & data_wire[2981..2981] # !(sel_wire[9..9]) & data_wire[2980..2980]; + l2_w7_n19_mux_dataout = sel_wire[9..9] & data_wire[2983..2983] # !(sel_wire[9..9]) & data_wire[2982..2982]; + l2_w7_n1_mux_dataout = sel_wire[9..9] & data_wire[2947..2947] # !(sel_wire[9..9]) & data_wire[2946..2946]; + l2_w7_n20_mux_dataout = sel_wire[9..9] & data_wire[2985..2985] # !(sel_wire[9..9]) & data_wire[2984..2984]; + l2_w7_n21_mux_dataout = sel_wire[9..9] & data_wire[2987..2987] # !(sel_wire[9..9]) & data_wire[2986..2986]; + l2_w7_n22_mux_dataout = sel_wire[9..9] & data_wire[2989..2989] # !(sel_wire[9..9]) & data_wire[2988..2988]; + l2_w7_n23_mux_dataout = sel_wire[9..9] & data_wire[2991..2991] # !(sel_wire[9..9]) & data_wire[2990..2990]; + l2_w7_n24_mux_dataout = sel_wire[9..9] & data_wire[2993..2993] # !(sel_wire[9..9]) & data_wire[2992..2992]; + l2_w7_n25_mux_dataout = sel_wire[9..9] & data_wire[2995..2995] # !(sel_wire[9..9]) & data_wire[2994..2994]; + l2_w7_n26_mux_dataout = sel_wire[9..9] & data_wire[2997..2997] # !(sel_wire[9..9]) & data_wire[2996..2996]; + l2_w7_n27_mux_dataout = sel_wire[9..9] & data_wire[2999..2999] # !(sel_wire[9..9]) & data_wire[2998..2998]; + l2_w7_n28_mux_dataout = sel_wire[9..9] & data_wire[3001..3001] # !(sel_wire[9..9]) & data_wire[3000..3000]; + l2_w7_n29_mux_dataout = sel_wire[9..9] & data_wire[3003..3003] # !(sel_wire[9..9]) & data_wire[3002..3002]; + l2_w7_n2_mux_dataout = sel_wire[9..9] & data_wire[2949..2949] # !(sel_wire[9..9]) & data_wire[2948..2948]; + l2_w7_n30_mux_dataout = sel_wire[9..9] & data_wire[3005..3005] # !(sel_wire[9..9]) & data_wire[3004..3004]; + l2_w7_n31_mux_dataout = sel_wire[9..9] & data_wire[3007..3007] # !(sel_wire[9..9]) & data_wire[3006..3006]; + l2_w7_n32_mux_dataout = sel_wire[9..9] & data_wire[3009..3009] # !(sel_wire[9..9]) & data_wire[3008..3008]; + l2_w7_n33_mux_dataout = sel_wire[9..9] & data_wire[3011..3011] # !(sel_wire[9..9]) & data_wire[3010..3010]; + l2_w7_n34_mux_dataout = sel_wire[9..9] & data_wire[3013..3013] # !(sel_wire[9..9]) & data_wire[3012..3012]; + l2_w7_n35_mux_dataout = sel_wire[9..9] & data_wire[3015..3015] # !(sel_wire[9..9]) & data_wire[3014..3014]; + l2_w7_n36_mux_dataout = sel_wire[9..9] & data_wire[3017..3017] # !(sel_wire[9..9]) & data_wire[3016..3016]; + l2_w7_n37_mux_dataout = sel_wire[9..9] & data_wire[3019..3019] # !(sel_wire[9..9]) & data_wire[3018..3018]; + l2_w7_n38_mux_dataout = sel_wire[9..9] & data_wire[3021..3021] # !(sel_wire[9..9]) & data_wire[3020..3020]; + l2_w7_n39_mux_dataout = sel_wire[9..9] & data_wire[3023..3023] # !(sel_wire[9..9]) & data_wire[3022..3022]; + l2_w7_n3_mux_dataout = sel_wire[9..9] & data_wire[2951..2951] # !(sel_wire[9..9]) & data_wire[2950..2950]; + l2_w7_n40_mux_dataout = sel_wire[9..9] & data_wire[3025..3025] # !(sel_wire[9..9]) & data_wire[3024..3024]; + l2_w7_n41_mux_dataout = sel_wire[9..9] & data_wire[3027..3027] # !(sel_wire[9..9]) & data_wire[3026..3026]; + l2_w7_n42_mux_dataout = sel_wire[9..9] & data_wire[3029..3029] # !(sel_wire[9..9]) & data_wire[3028..3028]; + l2_w7_n43_mux_dataout = sel_wire[9..9] & data_wire[3031..3031] # !(sel_wire[9..9]) & data_wire[3030..3030]; + l2_w7_n44_mux_dataout = sel_wire[9..9] & data_wire[3033..3033] # !(sel_wire[9..9]) & data_wire[3032..3032]; + l2_w7_n45_mux_dataout = sel_wire[9..9] & data_wire[3035..3035] # !(sel_wire[9..9]) & data_wire[3034..3034]; + l2_w7_n46_mux_dataout = sel_wire[9..9] & data_wire[3037..3037] # !(sel_wire[9..9]) & data_wire[3036..3036]; + l2_w7_n47_mux_dataout = sel_wire[9..9] & data_wire[3039..3039] # !(sel_wire[9..9]) & data_wire[3038..3038]; + l2_w7_n48_mux_dataout = sel_wire[9..9] & data_wire[3041..3041] # !(sel_wire[9..9]) & data_wire[3040..3040]; + l2_w7_n49_mux_dataout = sel_wire[9..9] & data_wire[3043..3043] # !(sel_wire[9..9]) & data_wire[3042..3042]; + l2_w7_n4_mux_dataout = sel_wire[9..9] & data_wire[2953..2953] # !(sel_wire[9..9]) & data_wire[2952..2952]; + l2_w7_n50_mux_dataout = sel_wire[9..9] & data_wire[3045..3045] # !(sel_wire[9..9]) & data_wire[3044..3044]; + l2_w7_n51_mux_dataout = sel_wire[9..9] & data_wire[3047..3047] # !(sel_wire[9..9]) & data_wire[3046..3046]; + l2_w7_n52_mux_dataout = sel_wire[9..9] & data_wire[3049..3049] # !(sel_wire[9..9]) & data_wire[3048..3048]; + l2_w7_n53_mux_dataout = sel_wire[9..9] & data_wire[3051..3051] # !(sel_wire[9..9]) & data_wire[3050..3050]; + l2_w7_n54_mux_dataout = sel_wire[9..9] & data_wire[3053..3053] # !(sel_wire[9..9]) & data_wire[3052..3052]; + l2_w7_n55_mux_dataout = sel_wire[9..9] & data_wire[3055..3055] # !(sel_wire[9..9]) & data_wire[3054..3054]; + l2_w7_n56_mux_dataout = sel_wire[9..9] & data_wire[3057..3057] # !(sel_wire[9..9]) & data_wire[3056..3056]; + l2_w7_n57_mux_dataout = sel_wire[9..9] & data_wire[3059..3059] # !(sel_wire[9..9]) & data_wire[3058..3058]; + l2_w7_n58_mux_dataout = sel_wire[9..9] & data_wire[3061..3061] # !(sel_wire[9..9]) & data_wire[3060..3060]; + l2_w7_n59_mux_dataout = sel_wire[9..9] & data_wire[3063..3063] # !(sel_wire[9..9]) & data_wire[3062..3062]; + l2_w7_n5_mux_dataout = sel_wire[9..9] & data_wire[2955..2955] # !(sel_wire[9..9]) & data_wire[2954..2954]; + l2_w7_n60_mux_dataout = sel_wire[9..9] & data_wire[3065..3065] # !(sel_wire[9..9]) & data_wire[3064..3064]; + l2_w7_n61_mux_dataout = sel_wire[9..9] & data_wire[3067..3067] # !(sel_wire[9..9]) & data_wire[3066..3066]; + l2_w7_n62_mux_dataout = sel_wire[9..9] & data_wire[3069..3069] # !(sel_wire[9..9]) & data_wire[3068..3068]; + l2_w7_n63_mux_dataout = sel_wire[9..9] & data_wire[3071..3071] # !(sel_wire[9..9]) & data_wire[3070..3070]; + l2_w7_n6_mux_dataout = sel_wire[9..9] & data_wire[2957..2957] # !(sel_wire[9..9]) & data_wire[2956..2956]; + l2_w7_n7_mux_dataout = sel_wire[9..9] & data_wire[2959..2959] # !(sel_wire[9..9]) & data_wire[2958..2958]; + l2_w7_n8_mux_dataout = sel_wire[9..9] & data_wire[2961..2961] # !(sel_wire[9..9]) & data_wire[2960..2960]; + l2_w7_n9_mux_dataout = sel_wire[9..9] & data_wire[2963..2963] # !(sel_wire[9..9]) & data_wire[2962..2962]; + l3_w0_n0_mux_dataout = sel_wire[18..18] & data_wire[3073..3073] # !(sel_wire[18..18]) & data_wire[3072..3072]; + l3_w0_n10_mux_dataout = sel_wire[18..18] & data_wire[3093..3093] # !(sel_wire[18..18]) & data_wire[3092..3092]; + l3_w0_n11_mux_dataout = sel_wire[18..18] & data_wire[3095..3095] # !(sel_wire[18..18]) & data_wire[3094..3094]; + l3_w0_n12_mux_dataout = sel_wire[18..18] & data_wire[3097..3097] # !(sel_wire[18..18]) & data_wire[3096..3096]; + l3_w0_n13_mux_dataout = sel_wire[18..18] & data_wire[3099..3099] # !(sel_wire[18..18]) & data_wire[3098..3098]; + l3_w0_n14_mux_dataout = sel_wire[18..18] & data_wire[3101..3101] # !(sel_wire[18..18]) & data_wire[3100..3100]; + l3_w0_n15_mux_dataout = sel_wire[18..18] & data_wire[3103..3103] # !(sel_wire[18..18]) & data_wire[3102..3102]; + l3_w0_n16_mux_dataout = sel_wire[18..18] & data_wire[3105..3105] # !(sel_wire[18..18]) & data_wire[3104..3104]; + l3_w0_n17_mux_dataout = sel_wire[18..18] & data_wire[3107..3107] # !(sel_wire[18..18]) & data_wire[3106..3106]; + l3_w0_n18_mux_dataout = sel_wire[18..18] & data_wire[3109..3109] # !(sel_wire[18..18]) & data_wire[3108..3108]; + l3_w0_n19_mux_dataout = sel_wire[18..18] & data_wire[3111..3111] # !(sel_wire[18..18]) & data_wire[3110..3110]; + l3_w0_n1_mux_dataout = sel_wire[18..18] & data_wire[3075..3075] # !(sel_wire[18..18]) & data_wire[3074..3074]; + l3_w0_n20_mux_dataout = sel_wire[18..18] & data_wire[3113..3113] # !(sel_wire[18..18]) & data_wire[3112..3112]; + l3_w0_n21_mux_dataout = sel_wire[18..18] & data_wire[3115..3115] # !(sel_wire[18..18]) & data_wire[3114..3114]; + l3_w0_n22_mux_dataout = sel_wire[18..18] & data_wire[3117..3117] # !(sel_wire[18..18]) & data_wire[3116..3116]; + l3_w0_n23_mux_dataout = sel_wire[18..18] & data_wire[3119..3119] # !(sel_wire[18..18]) & data_wire[3118..3118]; + l3_w0_n24_mux_dataout = sel_wire[18..18] & data_wire[3121..3121] # !(sel_wire[18..18]) & data_wire[3120..3120]; + l3_w0_n25_mux_dataout = sel_wire[18..18] & data_wire[3123..3123] # !(sel_wire[18..18]) & data_wire[3122..3122]; + l3_w0_n26_mux_dataout = sel_wire[18..18] & data_wire[3125..3125] # !(sel_wire[18..18]) & data_wire[3124..3124]; + l3_w0_n27_mux_dataout = sel_wire[18..18] & data_wire[3127..3127] # !(sel_wire[18..18]) & data_wire[3126..3126]; + l3_w0_n28_mux_dataout = sel_wire[18..18] & data_wire[3129..3129] # !(sel_wire[18..18]) & data_wire[3128..3128]; + l3_w0_n29_mux_dataout = sel_wire[18..18] & data_wire[3131..3131] # !(sel_wire[18..18]) & data_wire[3130..3130]; + l3_w0_n2_mux_dataout = sel_wire[18..18] & data_wire[3077..3077] # !(sel_wire[18..18]) & data_wire[3076..3076]; + l3_w0_n30_mux_dataout = sel_wire[18..18] & data_wire[3133..3133] # !(sel_wire[18..18]) & data_wire[3132..3132]; + l3_w0_n31_mux_dataout = sel_wire[18..18] & data_wire[3135..3135] # !(sel_wire[18..18]) & data_wire[3134..3134]; + l3_w0_n3_mux_dataout = sel_wire[18..18] & data_wire[3079..3079] # !(sel_wire[18..18]) & data_wire[3078..3078]; + l3_w0_n4_mux_dataout = sel_wire[18..18] & data_wire[3081..3081] # !(sel_wire[18..18]) & data_wire[3080..3080]; + l3_w0_n5_mux_dataout = sel_wire[18..18] & data_wire[3083..3083] # !(sel_wire[18..18]) & data_wire[3082..3082]; + l3_w0_n6_mux_dataout = sel_wire[18..18] & data_wire[3085..3085] # !(sel_wire[18..18]) & data_wire[3084..3084]; + l3_w0_n7_mux_dataout = sel_wire[18..18] & data_wire[3087..3087] # !(sel_wire[18..18]) & data_wire[3086..3086]; + l3_w0_n8_mux_dataout = sel_wire[18..18] & data_wire[3089..3089] # !(sel_wire[18..18]) & data_wire[3088..3088]; + l3_w0_n9_mux_dataout = sel_wire[18..18] & data_wire[3091..3091] # !(sel_wire[18..18]) & data_wire[3090..3090]; + l3_w1_n0_mux_dataout = sel_wire[18..18] & data_wire[3137..3137] # !(sel_wire[18..18]) & data_wire[3136..3136]; + l3_w1_n10_mux_dataout = sel_wire[18..18] & data_wire[3157..3157] # !(sel_wire[18..18]) & data_wire[3156..3156]; + l3_w1_n11_mux_dataout = sel_wire[18..18] & data_wire[3159..3159] # !(sel_wire[18..18]) & data_wire[3158..3158]; + l3_w1_n12_mux_dataout = sel_wire[18..18] & data_wire[3161..3161] # !(sel_wire[18..18]) & data_wire[3160..3160]; + l3_w1_n13_mux_dataout = sel_wire[18..18] & data_wire[3163..3163] # !(sel_wire[18..18]) & data_wire[3162..3162]; + l3_w1_n14_mux_dataout = sel_wire[18..18] & data_wire[3165..3165] # !(sel_wire[18..18]) & data_wire[3164..3164]; + l3_w1_n15_mux_dataout = sel_wire[18..18] & data_wire[3167..3167] # !(sel_wire[18..18]) & data_wire[3166..3166]; + l3_w1_n16_mux_dataout = sel_wire[18..18] & data_wire[3169..3169] # !(sel_wire[18..18]) & data_wire[3168..3168]; + l3_w1_n17_mux_dataout = sel_wire[18..18] & data_wire[3171..3171] # !(sel_wire[18..18]) & data_wire[3170..3170]; + l3_w1_n18_mux_dataout = sel_wire[18..18] & data_wire[3173..3173] # !(sel_wire[18..18]) & data_wire[3172..3172]; + l3_w1_n19_mux_dataout = sel_wire[18..18] & data_wire[3175..3175] # !(sel_wire[18..18]) & data_wire[3174..3174]; + l3_w1_n1_mux_dataout = sel_wire[18..18] & data_wire[3139..3139] # !(sel_wire[18..18]) & data_wire[3138..3138]; + l3_w1_n20_mux_dataout = sel_wire[18..18] & data_wire[3177..3177] # !(sel_wire[18..18]) & data_wire[3176..3176]; + l3_w1_n21_mux_dataout = sel_wire[18..18] & data_wire[3179..3179] # !(sel_wire[18..18]) & data_wire[3178..3178]; + l3_w1_n22_mux_dataout = sel_wire[18..18] & data_wire[3181..3181] # !(sel_wire[18..18]) & data_wire[3180..3180]; + l3_w1_n23_mux_dataout = sel_wire[18..18] & data_wire[3183..3183] # !(sel_wire[18..18]) & data_wire[3182..3182]; + l3_w1_n24_mux_dataout = sel_wire[18..18] & data_wire[3185..3185] # !(sel_wire[18..18]) & data_wire[3184..3184]; + l3_w1_n25_mux_dataout = sel_wire[18..18] & data_wire[3187..3187] # !(sel_wire[18..18]) & data_wire[3186..3186]; + l3_w1_n26_mux_dataout = sel_wire[18..18] & data_wire[3189..3189] # !(sel_wire[18..18]) & data_wire[3188..3188]; + l3_w1_n27_mux_dataout = sel_wire[18..18] & data_wire[3191..3191] # !(sel_wire[18..18]) & data_wire[3190..3190]; + l3_w1_n28_mux_dataout = sel_wire[18..18] & data_wire[3193..3193] # !(sel_wire[18..18]) & data_wire[3192..3192]; + l3_w1_n29_mux_dataout = sel_wire[18..18] & data_wire[3195..3195] # !(sel_wire[18..18]) & data_wire[3194..3194]; + l3_w1_n2_mux_dataout = sel_wire[18..18] & data_wire[3141..3141] # !(sel_wire[18..18]) & data_wire[3140..3140]; + l3_w1_n30_mux_dataout = sel_wire[18..18] & data_wire[3197..3197] # !(sel_wire[18..18]) & data_wire[3196..3196]; + l3_w1_n31_mux_dataout = sel_wire[18..18] & data_wire[3199..3199] # !(sel_wire[18..18]) & data_wire[3198..3198]; + l3_w1_n3_mux_dataout = sel_wire[18..18] & data_wire[3143..3143] # !(sel_wire[18..18]) & data_wire[3142..3142]; + l3_w1_n4_mux_dataout = sel_wire[18..18] & data_wire[3145..3145] # !(sel_wire[18..18]) & data_wire[3144..3144]; + l3_w1_n5_mux_dataout = sel_wire[18..18] & data_wire[3147..3147] # !(sel_wire[18..18]) & data_wire[3146..3146]; + l3_w1_n6_mux_dataout = sel_wire[18..18] & data_wire[3149..3149] # !(sel_wire[18..18]) & data_wire[3148..3148]; + l3_w1_n7_mux_dataout = sel_wire[18..18] & data_wire[3151..3151] # !(sel_wire[18..18]) & data_wire[3150..3150]; + l3_w1_n8_mux_dataout = sel_wire[18..18] & data_wire[3153..3153] # !(sel_wire[18..18]) & data_wire[3152..3152]; + l3_w1_n9_mux_dataout = sel_wire[18..18] & data_wire[3155..3155] # !(sel_wire[18..18]) & data_wire[3154..3154]; + l3_w2_n0_mux_dataout = sel_wire[18..18] & data_wire[3201..3201] # !(sel_wire[18..18]) & data_wire[3200..3200]; + l3_w2_n10_mux_dataout = sel_wire[18..18] & data_wire[3221..3221] # !(sel_wire[18..18]) & data_wire[3220..3220]; + l3_w2_n11_mux_dataout = sel_wire[18..18] & data_wire[3223..3223] # !(sel_wire[18..18]) & data_wire[3222..3222]; + l3_w2_n12_mux_dataout = sel_wire[18..18] & data_wire[3225..3225] # !(sel_wire[18..18]) & data_wire[3224..3224]; + l3_w2_n13_mux_dataout = sel_wire[18..18] & data_wire[3227..3227] # !(sel_wire[18..18]) & data_wire[3226..3226]; + l3_w2_n14_mux_dataout = sel_wire[18..18] & data_wire[3229..3229] # !(sel_wire[18..18]) & data_wire[3228..3228]; + l3_w2_n15_mux_dataout = sel_wire[18..18] & data_wire[3231..3231] # !(sel_wire[18..18]) & data_wire[3230..3230]; + l3_w2_n16_mux_dataout = sel_wire[18..18] & data_wire[3233..3233] # !(sel_wire[18..18]) & data_wire[3232..3232]; + l3_w2_n17_mux_dataout = sel_wire[18..18] & data_wire[3235..3235] # !(sel_wire[18..18]) & data_wire[3234..3234]; + l3_w2_n18_mux_dataout = sel_wire[18..18] & data_wire[3237..3237] # !(sel_wire[18..18]) & data_wire[3236..3236]; + l3_w2_n19_mux_dataout = sel_wire[18..18] & data_wire[3239..3239] # !(sel_wire[18..18]) & data_wire[3238..3238]; + l3_w2_n1_mux_dataout = sel_wire[18..18] & data_wire[3203..3203] # !(sel_wire[18..18]) & data_wire[3202..3202]; + l3_w2_n20_mux_dataout = sel_wire[18..18] & data_wire[3241..3241] # !(sel_wire[18..18]) & data_wire[3240..3240]; + l3_w2_n21_mux_dataout = sel_wire[18..18] & data_wire[3243..3243] # !(sel_wire[18..18]) & data_wire[3242..3242]; + l3_w2_n22_mux_dataout = sel_wire[18..18] & data_wire[3245..3245] # !(sel_wire[18..18]) & data_wire[3244..3244]; + l3_w2_n23_mux_dataout = sel_wire[18..18] & data_wire[3247..3247] # !(sel_wire[18..18]) & data_wire[3246..3246]; + l3_w2_n24_mux_dataout = sel_wire[18..18] & data_wire[3249..3249] # !(sel_wire[18..18]) & data_wire[3248..3248]; + l3_w2_n25_mux_dataout = sel_wire[18..18] & data_wire[3251..3251] # !(sel_wire[18..18]) & data_wire[3250..3250]; + l3_w2_n26_mux_dataout = sel_wire[18..18] & data_wire[3253..3253] # !(sel_wire[18..18]) & data_wire[3252..3252]; + l3_w2_n27_mux_dataout = sel_wire[18..18] & data_wire[3255..3255] # !(sel_wire[18..18]) & data_wire[3254..3254]; + l3_w2_n28_mux_dataout = sel_wire[18..18] & data_wire[3257..3257] # !(sel_wire[18..18]) & data_wire[3256..3256]; + l3_w2_n29_mux_dataout = sel_wire[18..18] & data_wire[3259..3259] # !(sel_wire[18..18]) & data_wire[3258..3258]; + l3_w2_n2_mux_dataout = sel_wire[18..18] & data_wire[3205..3205] # !(sel_wire[18..18]) & data_wire[3204..3204]; + l3_w2_n30_mux_dataout = sel_wire[18..18] & data_wire[3261..3261] # !(sel_wire[18..18]) & data_wire[3260..3260]; + l3_w2_n31_mux_dataout = sel_wire[18..18] & data_wire[3263..3263] # !(sel_wire[18..18]) & data_wire[3262..3262]; + l3_w2_n3_mux_dataout = sel_wire[18..18] & data_wire[3207..3207] # !(sel_wire[18..18]) & data_wire[3206..3206]; + l3_w2_n4_mux_dataout = sel_wire[18..18] & data_wire[3209..3209] # !(sel_wire[18..18]) & data_wire[3208..3208]; + l3_w2_n5_mux_dataout = sel_wire[18..18] & data_wire[3211..3211] # !(sel_wire[18..18]) & data_wire[3210..3210]; + l3_w2_n6_mux_dataout = sel_wire[18..18] & data_wire[3213..3213] # !(sel_wire[18..18]) & data_wire[3212..3212]; + l3_w2_n7_mux_dataout = sel_wire[18..18] & data_wire[3215..3215] # !(sel_wire[18..18]) & data_wire[3214..3214]; + l3_w2_n8_mux_dataout = sel_wire[18..18] & data_wire[3217..3217] # !(sel_wire[18..18]) & data_wire[3216..3216]; + l3_w2_n9_mux_dataout = sel_wire[18..18] & data_wire[3219..3219] # !(sel_wire[18..18]) & data_wire[3218..3218]; + l3_w3_n0_mux_dataout = sel_wire[18..18] & data_wire[3265..3265] # !(sel_wire[18..18]) & data_wire[3264..3264]; + l3_w3_n10_mux_dataout = sel_wire[18..18] & data_wire[3285..3285] # !(sel_wire[18..18]) & data_wire[3284..3284]; + l3_w3_n11_mux_dataout = sel_wire[18..18] & data_wire[3287..3287] # !(sel_wire[18..18]) & data_wire[3286..3286]; + l3_w3_n12_mux_dataout = sel_wire[18..18] & data_wire[3289..3289] # !(sel_wire[18..18]) & data_wire[3288..3288]; + l3_w3_n13_mux_dataout = sel_wire[18..18] & data_wire[3291..3291] # !(sel_wire[18..18]) & data_wire[3290..3290]; + l3_w3_n14_mux_dataout = sel_wire[18..18] & data_wire[3293..3293] # !(sel_wire[18..18]) & data_wire[3292..3292]; + l3_w3_n15_mux_dataout = sel_wire[18..18] & data_wire[3295..3295] # !(sel_wire[18..18]) & data_wire[3294..3294]; + l3_w3_n16_mux_dataout = sel_wire[18..18] & data_wire[3297..3297] # !(sel_wire[18..18]) & data_wire[3296..3296]; + l3_w3_n17_mux_dataout = sel_wire[18..18] & data_wire[3299..3299] # !(sel_wire[18..18]) & data_wire[3298..3298]; + l3_w3_n18_mux_dataout = sel_wire[18..18] & data_wire[3301..3301] # !(sel_wire[18..18]) & data_wire[3300..3300]; + l3_w3_n19_mux_dataout = sel_wire[18..18] & data_wire[3303..3303] # !(sel_wire[18..18]) & data_wire[3302..3302]; + l3_w3_n1_mux_dataout = sel_wire[18..18] & data_wire[3267..3267] # !(sel_wire[18..18]) & data_wire[3266..3266]; + l3_w3_n20_mux_dataout = sel_wire[18..18] & data_wire[3305..3305] # !(sel_wire[18..18]) & data_wire[3304..3304]; + l3_w3_n21_mux_dataout = sel_wire[18..18] & data_wire[3307..3307] # !(sel_wire[18..18]) & data_wire[3306..3306]; + l3_w3_n22_mux_dataout = sel_wire[18..18] & data_wire[3309..3309] # !(sel_wire[18..18]) & data_wire[3308..3308]; + l3_w3_n23_mux_dataout = sel_wire[18..18] & data_wire[3311..3311] # !(sel_wire[18..18]) & data_wire[3310..3310]; + l3_w3_n24_mux_dataout = sel_wire[18..18] & data_wire[3313..3313] # !(sel_wire[18..18]) & data_wire[3312..3312]; + l3_w3_n25_mux_dataout = sel_wire[18..18] & data_wire[3315..3315] # !(sel_wire[18..18]) & data_wire[3314..3314]; + l3_w3_n26_mux_dataout = sel_wire[18..18] & data_wire[3317..3317] # !(sel_wire[18..18]) & data_wire[3316..3316]; + l3_w3_n27_mux_dataout = sel_wire[18..18] & data_wire[3319..3319] # !(sel_wire[18..18]) & data_wire[3318..3318]; + l3_w3_n28_mux_dataout = sel_wire[18..18] & data_wire[3321..3321] # !(sel_wire[18..18]) & data_wire[3320..3320]; + l3_w3_n29_mux_dataout = sel_wire[18..18] & data_wire[3323..3323] # !(sel_wire[18..18]) & data_wire[3322..3322]; + l3_w3_n2_mux_dataout = sel_wire[18..18] & data_wire[3269..3269] # !(sel_wire[18..18]) & data_wire[3268..3268]; + l3_w3_n30_mux_dataout = sel_wire[18..18] & data_wire[3325..3325] # !(sel_wire[18..18]) & data_wire[3324..3324]; + l3_w3_n31_mux_dataout = sel_wire[18..18] & data_wire[3327..3327] # !(sel_wire[18..18]) & data_wire[3326..3326]; + l3_w3_n3_mux_dataout = sel_wire[18..18] & data_wire[3271..3271] # !(sel_wire[18..18]) & data_wire[3270..3270]; + l3_w3_n4_mux_dataout = sel_wire[18..18] & data_wire[3273..3273] # !(sel_wire[18..18]) & data_wire[3272..3272]; + l3_w3_n5_mux_dataout = sel_wire[18..18] & data_wire[3275..3275] # !(sel_wire[18..18]) & data_wire[3274..3274]; + l3_w3_n6_mux_dataout = sel_wire[18..18] & data_wire[3277..3277] # !(sel_wire[18..18]) & data_wire[3276..3276]; + l3_w3_n7_mux_dataout = sel_wire[18..18] & data_wire[3279..3279] # !(sel_wire[18..18]) & data_wire[3278..3278]; + l3_w3_n8_mux_dataout = sel_wire[18..18] & data_wire[3281..3281] # !(sel_wire[18..18]) & data_wire[3280..3280]; + l3_w3_n9_mux_dataout = sel_wire[18..18] & data_wire[3283..3283] # !(sel_wire[18..18]) & data_wire[3282..3282]; + l3_w4_n0_mux_dataout = sel_wire[18..18] & data_wire[3329..3329] # !(sel_wire[18..18]) & data_wire[3328..3328]; + l3_w4_n10_mux_dataout = sel_wire[18..18] & data_wire[3349..3349] # !(sel_wire[18..18]) & data_wire[3348..3348]; + l3_w4_n11_mux_dataout = sel_wire[18..18] & data_wire[3351..3351] # !(sel_wire[18..18]) & data_wire[3350..3350]; + l3_w4_n12_mux_dataout = sel_wire[18..18] & data_wire[3353..3353] # !(sel_wire[18..18]) & data_wire[3352..3352]; + l3_w4_n13_mux_dataout = sel_wire[18..18] & data_wire[3355..3355] # !(sel_wire[18..18]) & data_wire[3354..3354]; + l3_w4_n14_mux_dataout = sel_wire[18..18] & data_wire[3357..3357] # !(sel_wire[18..18]) & data_wire[3356..3356]; + l3_w4_n15_mux_dataout = sel_wire[18..18] & data_wire[3359..3359] # !(sel_wire[18..18]) & data_wire[3358..3358]; + l3_w4_n16_mux_dataout = sel_wire[18..18] & data_wire[3361..3361] # !(sel_wire[18..18]) & data_wire[3360..3360]; + l3_w4_n17_mux_dataout = sel_wire[18..18] & data_wire[3363..3363] # !(sel_wire[18..18]) & data_wire[3362..3362]; + l3_w4_n18_mux_dataout = sel_wire[18..18] & data_wire[3365..3365] # !(sel_wire[18..18]) & data_wire[3364..3364]; + l3_w4_n19_mux_dataout = sel_wire[18..18] & data_wire[3367..3367] # !(sel_wire[18..18]) & data_wire[3366..3366]; + l3_w4_n1_mux_dataout = sel_wire[18..18] & data_wire[3331..3331] # !(sel_wire[18..18]) & data_wire[3330..3330]; + l3_w4_n20_mux_dataout = sel_wire[18..18] & data_wire[3369..3369] # !(sel_wire[18..18]) & data_wire[3368..3368]; + l3_w4_n21_mux_dataout = sel_wire[18..18] & data_wire[3371..3371] # !(sel_wire[18..18]) & data_wire[3370..3370]; + l3_w4_n22_mux_dataout = sel_wire[18..18] & data_wire[3373..3373] # !(sel_wire[18..18]) & data_wire[3372..3372]; + l3_w4_n23_mux_dataout = sel_wire[18..18] & data_wire[3375..3375] # !(sel_wire[18..18]) & data_wire[3374..3374]; + l3_w4_n24_mux_dataout = sel_wire[18..18] & data_wire[3377..3377] # !(sel_wire[18..18]) & data_wire[3376..3376]; + l3_w4_n25_mux_dataout = sel_wire[18..18] & data_wire[3379..3379] # !(sel_wire[18..18]) & data_wire[3378..3378]; + l3_w4_n26_mux_dataout = sel_wire[18..18] & data_wire[3381..3381] # !(sel_wire[18..18]) & data_wire[3380..3380]; + l3_w4_n27_mux_dataout = sel_wire[18..18] & data_wire[3383..3383] # !(sel_wire[18..18]) & data_wire[3382..3382]; + l3_w4_n28_mux_dataout = sel_wire[18..18] & data_wire[3385..3385] # !(sel_wire[18..18]) & data_wire[3384..3384]; + l3_w4_n29_mux_dataout = sel_wire[18..18] & data_wire[3387..3387] # !(sel_wire[18..18]) & data_wire[3386..3386]; + l3_w4_n2_mux_dataout = sel_wire[18..18] & data_wire[3333..3333] # !(sel_wire[18..18]) & data_wire[3332..3332]; + l3_w4_n30_mux_dataout = sel_wire[18..18] & data_wire[3389..3389] # !(sel_wire[18..18]) & data_wire[3388..3388]; + l3_w4_n31_mux_dataout = sel_wire[18..18] & data_wire[3391..3391] # !(sel_wire[18..18]) & data_wire[3390..3390]; + l3_w4_n3_mux_dataout = sel_wire[18..18] & data_wire[3335..3335] # !(sel_wire[18..18]) & data_wire[3334..3334]; + l3_w4_n4_mux_dataout = sel_wire[18..18] & data_wire[3337..3337] # !(sel_wire[18..18]) & data_wire[3336..3336]; + l3_w4_n5_mux_dataout = sel_wire[18..18] & data_wire[3339..3339] # !(sel_wire[18..18]) & data_wire[3338..3338]; + l3_w4_n6_mux_dataout = sel_wire[18..18] & data_wire[3341..3341] # !(sel_wire[18..18]) & data_wire[3340..3340]; + l3_w4_n7_mux_dataout = sel_wire[18..18] & data_wire[3343..3343] # !(sel_wire[18..18]) & data_wire[3342..3342]; + l3_w4_n8_mux_dataout = sel_wire[18..18] & data_wire[3345..3345] # !(sel_wire[18..18]) & data_wire[3344..3344]; + l3_w4_n9_mux_dataout = sel_wire[18..18] & data_wire[3347..3347] # !(sel_wire[18..18]) & data_wire[3346..3346]; + l3_w5_n0_mux_dataout = sel_wire[18..18] & data_wire[3393..3393] # !(sel_wire[18..18]) & data_wire[3392..3392]; + l3_w5_n10_mux_dataout = sel_wire[18..18] & data_wire[3413..3413] # !(sel_wire[18..18]) & data_wire[3412..3412]; + l3_w5_n11_mux_dataout = sel_wire[18..18] & data_wire[3415..3415] # !(sel_wire[18..18]) & data_wire[3414..3414]; + l3_w5_n12_mux_dataout = sel_wire[18..18] & data_wire[3417..3417] # !(sel_wire[18..18]) & data_wire[3416..3416]; + l3_w5_n13_mux_dataout = sel_wire[18..18] & data_wire[3419..3419] # !(sel_wire[18..18]) & data_wire[3418..3418]; + l3_w5_n14_mux_dataout = sel_wire[18..18] & data_wire[3421..3421] # !(sel_wire[18..18]) & data_wire[3420..3420]; + l3_w5_n15_mux_dataout = sel_wire[18..18] & data_wire[3423..3423] # !(sel_wire[18..18]) & data_wire[3422..3422]; + l3_w5_n16_mux_dataout = sel_wire[18..18] & data_wire[3425..3425] # !(sel_wire[18..18]) & data_wire[3424..3424]; + l3_w5_n17_mux_dataout = sel_wire[18..18] & data_wire[3427..3427] # !(sel_wire[18..18]) & data_wire[3426..3426]; + l3_w5_n18_mux_dataout = sel_wire[18..18] & data_wire[3429..3429] # !(sel_wire[18..18]) & data_wire[3428..3428]; + l3_w5_n19_mux_dataout = sel_wire[18..18] & data_wire[3431..3431] # !(sel_wire[18..18]) & data_wire[3430..3430]; + l3_w5_n1_mux_dataout = sel_wire[18..18] & data_wire[3395..3395] # !(sel_wire[18..18]) & data_wire[3394..3394]; + l3_w5_n20_mux_dataout = sel_wire[18..18] & data_wire[3433..3433] # !(sel_wire[18..18]) & data_wire[3432..3432]; + l3_w5_n21_mux_dataout = sel_wire[18..18] & data_wire[3435..3435] # !(sel_wire[18..18]) & data_wire[3434..3434]; + l3_w5_n22_mux_dataout = sel_wire[18..18] & data_wire[3437..3437] # !(sel_wire[18..18]) & data_wire[3436..3436]; + l3_w5_n23_mux_dataout = sel_wire[18..18] & data_wire[3439..3439] # !(sel_wire[18..18]) & data_wire[3438..3438]; + l3_w5_n24_mux_dataout = sel_wire[18..18] & data_wire[3441..3441] # !(sel_wire[18..18]) & data_wire[3440..3440]; + l3_w5_n25_mux_dataout = sel_wire[18..18] & data_wire[3443..3443] # !(sel_wire[18..18]) & data_wire[3442..3442]; + l3_w5_n26_mux_dataout = sel_wire[18..18] & data_wire[3445..3445] # !(sel_wire[18..18]) & data_wire[3444..3444]; + l3_w5_n27_mux_dataout = sel_wire[18..18] & data_wire[3447..3447] # !(sel_wire[18..18]) & data_wire[3446..3446]; + l3_w5_n28_mux_dataout = sel_wire[18..18] & data_wire[3449..3449] # !(sel_wire[18..18]) & data_wire[3448..3448]; + l3_w5_n29_mux_dataout = sel_wire[18..18] & data_wire[3451..3451] # !(sel_wire[18..18]) & data_wire[3450..3450]; + l3_w5_n2_mux_dataout = sel_wire[18..18] & data_wire[3397..3397] # !(sel_wire[18..18]) & data_wire[3396..3396]; + l3_w5_n30_mux_dataout = sel_wire[18..18] & data_wire[3453..3453] # !(sel_wire[18..18]) & data_wire[3452..3452]; + l3_w5_n31_mux_dataout = sel_wire[18..18] & data_wire[3455..3455] # !(sel_wire[18..18]) & data_wire[3454..3454]; + l3_w5_n3_mux_dataout = sel_wire[18..18] & data_wire[3399..3399] # !(sel_wire[18..18]) & data_wire[3398..3398]; + l3_w5_n4_mux_dataout = sel_wire[18..18] & data_wire[3401..3401] # !(sel_wire[18..18]) & data_wire[3400..3400]; + l3_w5_n5_mux_dataout = sel_wire[18..18] & data_wire[3403..3403] # !(sel_wire[18..18]) & data_wire[3402..3402]; + l3_w5_n6_mux_dataout = sel_wire[18..18] & data_wire[3405..3405] # !(sel_wire[18..18]) & data_wire[3404..3404]; + l3_w5_n7_mux_dataout = sel_wire[18..18] & data_wire[3407..3407] # !(sel_wire[18..18]) & data_wire[3406..3406]; + l3_w5_n8_mux_dataout = sel_wire[18..18] & data_wire[3409..3409] # !(sel_wire[18..18]) & data_wire[3408..3408]; + l3_w5_n9_mux_dataout = sel_wire[18..18] & data_wire[3411..3411] # !(sel_wire[18..18]) & data_wire[3410..3410]; + l3_w6_n0_mux_dataout = sel_wire[18..18] & data_wire[3457..3457] # !(sel_wire[18..18]) & data_wire[3456..3456]; + l3_w6_n10_mux_dataout = sel_wire[18..18] & data_wire[3477..3477] # !(sel_wire[18..18]) & data_wire[3476..3476]; + l3_w6_n11_mux_dataout = sel_wire[18..18] & data_wire[3479..3479] # !(sel_wire[18..18]) & data_wire[3478..3478]; + l3_w6_n12_mux_dataout = sel_wire[18..18] & data_wire[3481..3481] # !(sel_wire[18..18]) & data_wire[3480..3480]; + l3_w6_n13_mux_dataout = sel_wire[18..18] & data_wire[3483..3483] # !(sel_wire[18..18]) & data_wire[3482..3482]; + l3_w6_n14_mux_dataout = sel_wire[18..18] & data_wire[3485..3485] # !(sel_wire[18..18]) & data_wire[3484..3484]; + l3_w6_n15_mux_dataout = sel_wire[18..18] & data_wire[3487..3487] # !(sel_wire[18..18]) & data_wire[3486..3486]; + l3_w6_n16_mux_dataout = sel_wire[18..18] & data_wire[3489..3489] # !(sel_wire[18..18]) & data_wire[3488..3488]; + l3_w6_n17_mux_dataout = sel_wire[18..18] & data_wire[3491..3491] # !(sel_wire[18..18]) & data_wire[3490..3490]; + l3_w6_n18_mux_dataout = sel_wire[18..18] & data_wire[3493..3493] # !(sel_wire[18..18]) & data_wire[3492..3492]; + l3_w6_n19_mux_dataout = sel_wire[18..18] & data_wire[3495..3495] # !(sel_wire[18..18]) & data_wire[3494..3494]; + l3_w6_n1_mux_dataout = sel_wire[18..18] & data_wire[3459..3459] # !(sel_wire[18..18]) & data_wire[3458..3458]; + l3_w6_n20_mux_dataout = sel_wire[18..18] & data_wire[3497..3497] # !(sel_wire[18..18]) & data_wire[3496..3496]; + l3_w6_n21_mux_dataout = sel_wire[18..18] & data_wire[3499..3499] # !(sel_wire[18..18]) & data_wire[3498..3498]; + l3_w6_n22_mux_dataout = sel_wire[18..18] & data_wire[3501..3501] # !(sel_wire[18..18]) & data_wire[3500..3500]; + l3_w6_n23_mux_dataout = sel_wire[18..18] & data_wire[3503..3503] # !(sel_wire[18..18]) & data_wire[3502..3502]; + l3_w6_n24_mux_dataout = sel_wire[18..18] & data_wire[3505..3505] # !(sel_wire[18..18]) & data_wire[3504..3504]; + l3_w6_n25_mux_dataout = sel_wire[18..18] & data_wire[3507..3507] # !(sel_wire[18..18]) & data_wire[3506..3506]; + l3_w6_n26_mux_dataout = sel_wire[18..18] & data_wire[3509..3509] # !(sel_wire[18..18]) & data_wire[3508..3508]; + l3_w6_n27_mux_dataout = sel_wire[18..18] & data_wire[3511..3511] # !(sel_wire[18..18]) & data_wire[3510..3510]; + l3_w6_n28_mux_dataout = sel_wire[18..18] & data_wire[3513..3513] # !(sel_wire[18..18]) & data_wire[3512..3512]; + l3_w6_n29_mux_dataout = sel_wire[18..18] & data_wire[3515..3515] # !(sel_wire[18..18]) & data_wire[3514..3514]; + l3_w6_n2_mux_dataout = sel_wire[18..18] & data_wire[3461..3461] # !(sel_wire[18..18]) & data_wire[3460..3460]; + l3_w6_n30_mux_dataout = sel_wire[18..18] & data_wire[3517..3517] # !(sel_wire[18..18]) & data_wire[3516..3516]; + l3_w6_n31_mux_dataout = sel_wire[18..18] & data_wire[3519..3519] # !(sel_wire[18..18]) & data_wire[3518..3518]; + l3_w6_n3_mux_dataout = sel_wire[18..18] & data_wire[3463..3463] # !(sel_wire[18..18]) & data_wire[3462..3462]; + l3_w6_n4_mux_dataout = sel_wire[18..18] & data_wire[3465..3465] # !(sel_wire[18..18]) & data_wire[3464..3464]; + l3_w6_n5_mux_dataout = sel_wire[18..18] & data_wire[3467..3467] # !(sel_wire[18..18]) & data_wire[3466..3466]; + l3_w6_n6_mux_dataout = sel_wire[18..18] & data_wire[3469..3469] # !(sel_wire[18..18]) & data_wire[3468..3468]; + l3_w6_n7_mux_dataout = sel_wire[18..18] & data_wire[3471..3471] # !(sel_wire[18..18]) & data_wire[3470..3470]; + l3_w6_n8_mux_dataout = sel_wire[18..18] & data_wire[3473..3473] # !(sel_wire[18..18]) & data_wire[3472..3472]; + l3_w6_n9_mux_dataout = sel_wire[18..18] & data_wire[3475..3475] # !(sel_wire[18..18]) & data_wire[3474..3474]; + l3_w7_n0_mux_dataout = sel_wire[18..18] & data_wire[3521..3521] # !(sel_wire[18..18]) & data_wire[3520..3520]; + l3_w7_n10_mux_dataout = sel_wire[18..18] & data_wire[3541..3541] # !(sel_wire[18..18]) & data_wire[3540..3540]; + l3_w7_n11_mux_dataout = sel_wire[18..18] & data_wire[3543..3543] # !(sel_wire[18..18]) & data_wire[3542..3542]; + l3_w7_n12_mux_dataout = sel_wire[18..18] & data_wire[3545..3545] # !(sel_wire[18..18]) & data_wire[3544..3544]; + l3_w7_n13_mux_dataout = sel_wire[18..18] & data_wire[3547..3547] # !(sel_wire[18..18]) & data_wire[3546..3546]; + l3_w7_n14_mux_dataout = sel_wire[18..18] & data_wire[3549..3549] # !(sel_wire[18..18]) & data_wire[3548..3548]; + l3_w7_n15_mux_dataout = sel_wire[18..18] & data_wire[3551..3551] # !(sel_wire[18..18]) & data_wire[3550..3550]; + l3_w7_n16_mux_dataout = sel_wire[18..18] & data_wire[3553..3553] # !(sel_wire[18..18]) & data_wire[3552..3552]; + l3_w7_n17_mux_dataout = sel_wire[18..18] & data_wire[3555..3555] # !(sel_wire[18..18]) & data_wire[3554..3554]; + l3_w7_n18_mux_dataout = sel_wire[18..18] & data_wire[3557..3557] # !(sel_wire[18..18]) & data_wire[3556..3556]; + l3_w7_n19_mux_dataout = sel_wire[18..18] & data_wire[3559..3559] # !(sel_wire[18..18]) & data_wire[3558..3558]; + l3_w7_n1_mux_dataout = sel_wire[18..18] & data_wire[3523..3523] # !(sel_wire[18..18]) & data_wire[3522..3522]; + l3_w7_n20_mux_dataout = sel_wire[18..18] & data_wire[3561..3561] # !(sel_wire[18..18]) & data_wire[3560..3560]; + l3_w7_n21_mux_dataout = sel_wire[18..18] & data_wire[3563..3563] # !(sel_wire[18..18]) & data_wire[3562..3562]; + l3_w7_n22_mux_dataout = sel_wire[18..18] & data_wire[3565..3565] # !(sel_wire[18..18]) & data_wire[3564..3564]; + l3_w7_n23_mux_dataout = sel_wire[18..18] & data_wire[3567..3567] # !(sel_wire[18..18]) & data_wire[3566..3566]; + l3_w7_n24_mux_dataout = sel_wire[18..18] & data_wire[3569..3569] # !(sel_wire[18..18]) & data_wire[3568..3568]; + l3_w7_n25_mux_dataout = sel_wire[18..18] & data_wire[3571..3571] # !(sel_wire[18..18]) & data_wire[3570..3570]; + l3_w7_n26_mux_dataout = sel_wire[18..18] & data_wire[3573..3573] # !(sel_wire[18..18]) & data_wire[3572..3572]; + l3_w7_n27_mux_dataout = sel_wire[18..18] & data_wire[3575..3575] # !(sel_wire[18..18]) & data_wire[3574..3574]; + l3_w7_n28_mux_dataout = sel_wire[18..18] & data_wire[3577..3577] # !(sel_wire[18..18]) & data_wire[3576..3576]; + l3_w7_n29_mux_dataout = sel_wire[18..18] & data_wire[3579..3579] # !(sel_wire[18..18]) & data_wire[3578..3578]; + l3_w7_n2_mux_dataout = sel_wire[18..18] & data_wire[3525..3525] # !(sel_wire[18..18]) & data_wire[3524..3524]; + l3_w7_n30_mux_dataout = sel_wire[18..18] & data_wire[3581..3581] # !(sel_wire[18..18]) & data_wire[3580..3580]; + l3_w7_n31_mux_dataout = sel_wire[18..18] & data_wire[3583..3583] # !(sel_wire[18..18]) & data_wire[3582..3582]; + l3_w7_n3_mux_dataout = sel_wire[18..18] & data_wire[3527..3527] # !(sel_wire[18..18]) & data_wire[3526..3526]; + l3_w7_n4_mux_dataout = sel_wire[18..18] & data_wire[3529..3529] # !(sel_wire[18..18]) & data_wire[3528..3528]; + l3_w7_n5_mux_dataout = sel_wire[18..18] & data_wire[3531..3531] # !(sel_wire[18..18]) & data_wire[3530..3530]; + l3_w7_n6_mux_dataout = sel_wire[18..18] & data_wire[3533..3533] # !(sel_wire[18..18]) & data_wire[3532..3532]; + l3_w7_n7_mux_dataout = sel_wire[18..18] & data_wire[3535..3535] # !(sel_wire[18..18]) & data_wire[3534..3534]; + l3_w7_n8_mux_dataout = sel_wire[18..18] & data_wire[3537..3537] # !(sel_wire[18..18]) & data_wire[3536..3536]; + l3_w7_n9_mux_dataout = sel_wire[18..18] & data_wire[3539..3539] # !(sel_wire[18..18]) & data_wire[3538..3538]; + l4_w0_n0_mux_dataout = sel_wire[27..27] & data_wire[3585..3585] # !(sel_wire[27..27]) & data_wire[3584..3584]; + l4_w0_n10_mux_dataout = sel_wire[27..27] & data_wire[3605..3605] # !(sel_wire[27..27]) & data_wire[3604..3604]; + l4_w0_n11_mux_dataout = sel_wire[27..27] & data_wire[3607..3607] # !(sel_wire[27..27]) & data_wire[3606..3606]; + l4_w0_n12_mux_dataout = sel_wire[27..27] & data_wire[3609..3609] # !(sel_wire[27..27]) & data_wire[3608..3608]; + l4_w0_n13_mux_dataout = sel_wire[27..27] & data_wire[3611..3611] # !(sel_wire[27..27]) & data_wire[3610..3610]; + l4_w0_n14_mux_dataout = sel_wire[27..27] & data_wire[3613..3613] # !(sel_wire[27..27]) & data_wire[3612..3612]; + l4_w0_n15_mux_dataout = sel_wire[27..27] & data_wire[3615..3615] # !(sel_wire[27..27]) & data_wire[3614..3614]; + l4_w0_n1_mux_dataout = sel_wire[27..27] & data_wire[3587..3587] # !(sel_wire[27..27]) & data_wire[3586..3586]; + l4_w0_n2_mux_dataout = sel_wire[27..27] & data_wire[3589..3589] # !(sel_wire[27..27]) & data_wire[3588..3588]; + l4_w0_n3_mux_dataout = sel_wire[27..27] & data_wire[3591..3591] # !(sel_wire[27..27]) & data_wire[3590..3590]; + l4_w0_n4_mux_dataout = sel_wire[27..27] & data_wire[3593..3593] # !(sel_wire[27..27]) & data_wire[3592..3592]; + l4_w0_n5_mux_dataout = sel_wire[27..27] & data_wire[3595..3595] # !(sel_wire[27..27]) & data_wire[3594..3594]; + l4_w0_n6_mux_dataout = sel_wire[27..27] & data_wire[3597..3597] # !(sel_wire[27..27]) & data_wire[3596..3596]; + l4_w0_n7_mux_dataout = sel_wire[27..27] & data_wire[3599..3599] # !(sel_wire[27..27]) & data_wire[3598..3598]; + l4_w0_n8_mux_dataout = sel_wire[27..27] & data_wire[3601..3601] # !(sel_wire[27..27]) & data_wire[3600..3600]; + l4_w0_n9_mux_dataout = sel_wire[27..27] & data_wire[3603..3603] # !(sel_wire[27..27]) & data_wire[3602..3602]; + l4_w1_n0_mux_dataout = sel_wire[27..27] & data_wire[3617..3617] # !(sel_wire[27..27]) & data_wire[3616..3616]; + l4_w1_n10_mux_dataout = sel_wire[27..27] & data_wire[3637..3637] # !(sel_wire[27..27]) & data_wire[3636..3636]; + l4_w1_n11_mux_dataout = sel_wire[27..27] & data_wire[3639..3639] # !(sel_wire[27..27]) & data_wire[3638..3638]; + l4_w1_n12_mux_dataout = sel_wire[27..27] & data_wire[3641..3641] # !(sel_wire[27..27]) & data_wire[3640..3640]; + l4_w1_n13_mux_dataout = sel_wire[27..27] & data_wire[3643..3643] # !(sel_wire[27..27]) & data_wire[3642..3642]; + l4_w1_n14_mux_dataout = sel_wire[27..27] & data_wire[3645..3645] # !(sel_wire[27..27]) & data_wire[3644..3644]; + l4_w1_n15_mux_dataout = sel_wire[27..27] & data_wire[3647..3647] # !(sel_wire[27..27]) & data_wire[3646..3646]; + l4_w1_n1_mux_dataout = sel_wire[27..27] & data_wire[3619..3619] # !(sel_wire[27..27]) & data_wire[3618..3618]; + l4_w1_n2_mux_dataout = sel_wire[27..27] & data_wire[3621..3621] # !(sel_wire[27..27]) & data_wire[3620..3620]; + l4_w1_n3_mux_dataout = sel_wire[27..27] & data_wire[3623..3623] # !(sel_wire[27..27]) & data_wire[3622..3622]; + l4_w1_n4_mux_dataout = sel_wire[27..27] & data_wire[3625..3625] # !(sel_wire[27..27]) & data_wire[3624..3624]; + l4_w1_n5_mux_dataout = sel_wire[27..27] & data_wire[3627..3627] # !(sel_wire[27..27]) & data_wire[3626..3626]; + l4_w1_n6_mux_dataout = sel_wire[27..27] & data_wire[3629..3629] # !(sel_wire[27..27]) & data_wire[3628..3628]; + l4_w1_n7_mux_dataout = sel_wire[27..27] & data_wire[3631..3631] # !(sel_wire[27..27]) & data_wire[3630..3630]; + l4_w1_n8_mux_dataout = sel_wire[27..27] & data_wire[3633..3633] # !(sel_wire[27..27]) & data_wire[3632..3632]; + l4_w1_n9_mux_dataout = sel_wire[27..27] & data_wire[3635..3635] # !(sel_wire[27..27]) & data_wire[3634..3634]; + l4_w2_n0_mux_dataout = sel_wire[27..27] & data_wire[3649..3649] # !(sel_wire[27..27]) & data_wire[3648..3648]; + l4_w2_n10_mux_dataout = sel_wire[27..27] & data_wire[3669..3669] # !(sel_wire[27..27]) & data_wire[3668..3668]; + l4_w2_n11_mux_dataout = sel_wire[27..27] & data_wire[3671..3671] # !(sel_wire[27..27]) & data_wire[3670..3670]; + l4_w2_n12_mux_dataout = sel_wire[27..27] & data_wire[3673..3673] # !(sel_wire[27..27]) & data_wire[3672..3672]; + l4_w2_n13_mux_dataout = sel_wire[27..27] & data_wire[3675..3675] # !(sel_wire[27..27]) & data_wire[3674..3674]; + l4_w2_n14_mux_dataout = sel_wire[27..27] & data_wire[3677..3677] # !(sel_wire[27..27]) & data_wire[3676..3676]; + l4_w2_n15_mux_dataout = sel_wire[27..27] & data_wire[3679..3679] # !(sel_wire[27..27]) & data_wire[3678..3678]; + l4_w2_n1_mux_dataout = sel_wire[27..27] & data_wire[3651..3651] # !(sel_wire[27..27]) & data_wire[3650..3650]; + l4_w2_n2_mux_dataout = sel_wire[27..27] & data_wire[3653..3653] # !(sel_wire[27..27]) & data_wire[3652..3652]; + l4_w2_n3_mux_dataout = sel_wire[27..27] & data_wire[3655..3655] # !(sel_wire[27..27]) & data_wire[3654..3654]; + l4_w2_n4_mux_dataout = sel_wire[27..27] & data_wire[3657..3657] # !(sel_wire[27..27]) & data_wire[3656..3656]; + l4_w2_n5_mux_dataout = sel_wire[27..27] & data_wire[3659..3659] # !(sel_wire[27..27]) & data_wire[3658..3658]; + l4_w2_n6_mux_dataout = sel_wire[27..27] & data_wire[3661..3661] # !(sel_wire[27..27]) & data_wire[3660..3660]; + l4_w2_n7_mux_dataout = sel_wire[27..27] & data_wire[3663..3663] # !(sel_wire[27..27]) & data_wire[3662..3662]; + l4_w2_n8_mux_dataout = sel_wire[27..27] & data_wire[3665..3665] # !(sel_wire[27..27]) & data_wire[3664..3664]; + l4_w2_n9_mux_dataout = sel_wire[27..27] & data_wire[3667..3667] # !(sel_wire[27..27]) & data_wire[3666..3666]; + l4_w3_n0_mux_dataout = sel_wire[27..27] & data_wire[3681..3681] # !(sel_wire[27..27]) & data_wire[3680..3680]; + l4_w3_n10_mux_dataout = sel_wire[27..27] & data_wire[3701..3701] # !(sel_wire[27..27]) & data_wire[3700..3700]; + l4_w3_n11_mux_dataout = sel_wire[27..27] & data_wire[3703..3703] # !(sel_wire[27..27]) & data_wire[3702..3702]; + l4_w3_n12_mux_dataout = sel_wire[27..27] & data_wire[3705..3705] # !(sel_wire[27..27]) & data_wire[3704..3704]; + l4_w3_n13_mux_dataout = sel_wire[27..27] & data_wire[3707..3707] # !(sel_wire[27..27]) & data_wire[3706..3706]; + l4_w3_n14_mux_dataout = sel_wire[27..27] & data_wire[3709..3709] # !(sel_wire[27..27]) & data_wire[3708..3708]; + l4_w3_n15_mux_dataout = sel_wire[27..27] & data_wire[3711..3711] # !(sel_wire[27..27]) & data_wire[3710..3710]; + l4_w3_n1_mux_dataout = sel_wire[27..27] & data_wire[3683..3683] # !(sel_wire[27..27]) & data_wire[3682..3682]; + l4_w3_n2_mux_dataout = sel_wire[27..27] & data_wire[3685..3685] # !(sel_wire[27..27]) & data_wire[3684..3684]; + l4_w3_n3_mux_dataout = sel_wire[27..27] & data_wire[3687..3687] # !(sel_wire[27..27]) & data_wire[3686..3686]; + l4_w3_n4_mux_dataout = sel_wire[27..27] & data_wire[3689..3689] # !(sel_wire[27..27]) & data_wire[3688..3688]; + l4_w3_n5_mux_dataout = sel_wire[27..27] & data_wire[3691..3691] # !(sel_wire[27..27]) & data_wire[3690..3690]; + l4_w3_n6_mux_dataout = sel_wire[27..27] & data_wire[3693..3693] # !(sel_wire[27..27]) & data_wire[3692..3692]; + l4_w3_n7_mux_dataout = sel_wire[27..27] & data_wire[3695..3695] # !(sel_wire[27..27]) & data_wire[3694..3694]; + l4_w3_n8_mux_dataout = sel_wire[27..27] & data_wire[3697..3697] # !(sel_wire[27..27]) & data_wire[3696..3696]; + l4_w3_n9_mux_dataout = sel_wire[27..27] & data_wire[3699..3699] # !(sel_wire[27..27]) & data_wire[3698..3698]; + l4_w4_n0_mux_dataout = sel_wire[27..27] & data_wire[3713..3713] # !(sel_wire[27..27]) & data_wire[3712..3712]; + l4_w4_n10_mux_dataout = sel_wire[27..27] & data_wire[3733..3733] # !(sel_wire[27..27]) & data_wire[3732..3732]; + l4_w4_n11_mux_dataout = sel_wire[27..27] & data_wire[3735..3735] # !(sel_wire[27..27]) & data_wire[3734..3734]; + l4_w4_n12_mux_dataout = sel_wire[27..27] & data_wire[3737..3737] # !(sel_wire[27..27]) & data_wire[3736..3736]; + l4_w4_n13_mux_dataout = sel_wire[27..27] & data_wire[3739..3739] # !(sel_wire[27..27]) & data_wire[3738..3738]; + l4_w4_n14_mux_dataout = sel_wire[27..27] & data_wire[3741..3741] # !(sel_wire[27..27]) & data_wire[3740..3740]; + l4_w4_n15_mux_dataout = sel_wire[27..27] & data_wire[3743..3743] # !(sel_wire[27..27]) & data_wire[3742..3742]; + l4_w4_n1_mux_dataout = sel_wire[27..27] & data_wire[3715..3715] # !(sel_wire[27..27]) & data_wire[3714..3714]; + l4_w4_n2_mux_dataout = sel_wire[27..27] & data_wire[3717..3717] # !(sel_wire[27..27]) & data_wire[3716..3716]; + l4_w4_n3_mux_dataout = sel_wire[27..27] & data_wire[3719..3719] # !(sel_wire[27..27]) & data_wire[3718..3718]; + l4_w4_n4_mux_dataout = sel_wire[27..27] & data_wire[3721..3721] # !(sel_wire[27..27]) & data_wire[3720..3720]; + l4_w4_n5_mux_dataout = sel_wire[27..27] & data_wire[3723..3723] # !(sel_wire[27..27]) & data_wire[3722..3722]; + l4_w4_n6_mux_dataout = sel_wire[27..27] & data_wire[3725..3725] # !(sel_wire[27..27]) & data_wire[3724..3724]; + l4_w4_n7_mux_dataout = sel_wire[27..27] & data_wire[3727..3727] # !(sel_wire[27..27]) & data_wire[3726..3726]; + l4_w4_n8_mux_dataout = sel_wire[27..27] & data_wire[3729..3729] # !(sel_wire[27..27]) & data_wire[3728..3728]; + l4_w4_n9_mux_dataout = sel_wire[27..27] & data_wire[3731..3731] # !(sel_wire[27..27]) & data_wire[3730..3730]; + l4_w5_n0_mux_dataout = sel_wire[27..27] & data_wire[3745..3745] # !(sel_wire[27..27]) & data_wire[3744..3744]; + l4_w5_n10_mux_dataout = sel_wire[27..27] & data_wire[3765..3765] # !(sel_wire[27..27]) & data_wire[3764..3764]; + l4_w5_n11_mux_dataout = sel_wire[27..27] & data_wire[3767..3767] # !(sel_wire[27..27]) & data_wire[3766..3766]; + l4_w5_n12_mux_dataout = sel_wire[27..27] & data_wire[3769..3769] # !(sel_wire[27..27]) & data_wire[3768..3768]; + l4_w5_n13_mux_dataout = sel_wire[27..27] & data_wire[3771..3771] # !(sel_wire[27..27]) & data_wire[3770..3770]; + l4_w5_n14_mux_dataout = sel_wire[27..27] & data_wire[3773..3773] # !(sel_wire[27..27]) & data_wire[3772..3772]; + l4_w5_n15_mux_dataout = sel_wire[27..27] & data_wire[3775..3775] # !(sel_wire[27..27]) & data_wire[3774..3774]; + l4_w5_n1_mux_dataout = sel_wire[27..27] & data_wire[3747..3747] # !(sel_wire[27..27]) & data_wire[3746..3746]; + l4_w5_n2_mux_dataout = sel_wire[27..27] & data_wire[3749..3749] # !(sel_wire[27..27]) & data_wire[3748..3748]; + l4_w5_n3_mux_dataout = sel_wire[27..27] & data_wire[3751..3751] # !(sel_wire[27..27]) & data_wire[3750..3750]; + l4_w5_n4_mux_dataout = sel_wire[27..27] & data_wire[3753..3753] # !(sel_wire[27..27]) & data_wire[3752..3752]; + l4_w5_n5_mux_dataout = sel_wire[27..27] & data_wire[3755..3755] # !(sel_wire[27..27]) & data_wire[3754..3754]; + l4_w5_n6_mux_dataout = sel_wire[27..27] & data_wire[3757..3757] # !(sel_wire[27..27]) & data_wire[3756..3756]; + l4_w5_n7_mux_dataout = sel_wire[27..27] & data_wire[3759..3759] # !(sel_wire[27..27]) & data_wire[3758..3758]; + l4_w5_n8_mux_dataout = sel_wire[27..27] & data_wire[3761..3761] # !(sel_wire[27..27]) & data_wire[3760..3760]; + l4_w5_n9_mux_dataout = sel_wire[27..27] & data_wire[3763..3763] # !(sel_wire[27..27]) & data_wire[3762..3762]; + l4_w6_n0_mux_dataout = sel_wire[27..27] & data_wire[3777..3777] # !(sel_wire[27..27]) & data_wire[3776..3776]; + l4_w6_n10_mux_dataout = sel_wire[27..27] & data_wire[3797..3797] # !(sel_wire[27..27]) & data_wire[3796..3796]; + l4_w6_n11_mux_dataout = sel_wire[27..27] & data_wire[3799..3799] # !(sel_wire[27..27]) & data_wire[3798..3798]; + l4_w6_n12_mux_dataout = sel_wire[27..27] & data_wire[3801..3801] # !(sel_wire[27..27]) & data_wire[3800..3800]; + l4_w6_n13_mux_dataout = sel_wire[27..27] & data_wire[3803..3803] # !(sel_wire[27..27]) & data_wire[3802..3802]; + l4_w6_n14_mux_dataout = sel_wire[27..27] & data_wire[3805..3805] # !(sel_wire[27..27]) & data_wire[3804..3804]; + l4_w6_n15_mux_dataout = sel_wire[27..27] & data_wire[3807..3807] # !(sel_wire[27..27]) & data_wire[3806..3806]; + l4_w6_n1_mux_dataout = sel_wire[27..27] & data_wire[3779..3779] # !(sel_wire[27..27]) & data_wire[3778..3778]; + l4_w6_n2_mux_dataout = sel_wire[27..27] & data_wire[3781..3781] # !(sel_wire[27..27]) & data_wire[3780..3780]; + l4_w6_n3_mux_dataout = sel_wire[27..27] & data_wire[3783..3783] # !(sel_wire[27..27]) & data_wire[3782..3782]; + l4_w6_n4_mux_dataout = sel_wire[27..27] & data_wire[3785..3785] # !(sel_wire[27..27]) & data_wire[3784..3784]; + l4_w6_n5_mux_dataout = sel_wire[27..27] & data_wire[3787..3787] # !(sel_wire[27..27]) & data_wire[3786..3786]; + l4_w6_n6_mux_dataout = sel_wire[27..27] & data_wire[3789..3789] # !(sel_wire[27..27]) & data_wire[3788..3788]; + l4_w6_n7_mux_dataout = sel_wire[27..27] & data_wire[3791..3791] # !(sel_wire[27..27]) & data_wire[3790..3790]; + l4_w6_n8_mux_dataout = sel_wire[27..27] & data_wire[3793..3793] # !(sel_wire[27..27]) & data_wire[3792..3792]; + l4_w6_n9_mux_dataout = sel_wire[27..27] & data_wire[3795..3795] # !(sel_wire[27..27]) & data_wire[3794..3794]; + l4_w7_n0_mux_dataout = sel_wire[27..27] & data_wire[3809..3809] # !(sel_wire[27..27]) & data_wire[3808..3808]; + l4_w7_n10_mux_dataout = sel_wire[27..27] & data_wire[3829..3829] # !(sel_wire[27..27]) & data_wire[3828..3828]; + l4_w7_n11_mux_dataout = sel_wire[27..27] & data_wire[3831..3831] # !(sel_wire[27..27]) & data_wire[3830..3830]; + l4_w7_n12_mux_dataout = sel_wire[27..27] & data_wire[3833..3833] # !(sel_wire[27..27]) & data_wire[3832..3832]; + l4_w7_n13_mux_dataout = sel_wire[27..27] & data_wire[3835..3835] # !(sel_wire[27..27]) & data_wire[3834..3834]; + l4_w7_n14_mux_dataout = sel_wire[27..27] & data_wire[3837..3837] # !(sel_wire[27..27]) & data_wire[3836..3836]; + l4_w7_n15_mux_dataout = sel_wire[27..27] & data_wire[3839..3839] # !(sel_wire[27..27]) & data_wire[3838..3838]; + l4_w7_n1_mux_dataout = sel_wire[27..27] & data_wire[3811..3811] # !(sel_wire[27..27]) & data_wire[3810..3810]; + l4_w7_n2_mux_dataout = sel_wire[27..27] & data_wire[3813..3813] # !(sel_wire[27..27]) & data_wire[3812..3812]; + l4_w7_n3_mux_dataout = sel_wire[27..27] & data_wire[3815..3815] # !(sel_wire[27..27]) & data_wire[3814..3814]; + l4_w7_n4_mux_dataout = sel_wire[27..27] & data_wire[3817..3817] # !(sel_wire[27..27]) & data_wire[3816..3816]; + l4_w7_n5_mux_dataout = sel_wire[27..27] & data_wire[3819..3819] # !(sel_wire[27..27]) & data_wire[3818..3818]; + l4_w7_n6_mux_dataout = sel_wire[27..27] & data_wire[3821..3821] # !(sel_wire[27..27]) & data_wire[3820..3820]; + l4_w7_n7_mux_dataout = sel_wire[27..27] & data_wire[3823..3823] # !(sel_wire[27..27]) & data_wire[3822..3822]; + l4_w7_n8_mux_dataout = sel_wire[27..27] & data_wire[3825..3825] # !(sel_wire[27..27]) & data_wire[3824..3824]; + l4_w7_n9_mux_dataout = sel_wire[27..27] & data_wire[3827..3827] # !(sel_wire[27..27]) & data_wire[3826..3826]; + l5_w0_n0_mux_dataout = sel_wire[36..36] & data_wire[3841..3841] # !(sel_wire[36..36]) & data_wire[3840..3840]; + l5_w0_n1_mux_dataout = sel_wire[36..36] & data_wire[3843..3843] # !(sel_wire[36..36]) & data_wire[3842..3842]; + l5_w0_n2_mux_dataout = sel_wire[36..36] & data_wire[3845..3845] # !(sel_wire[36..36]) & data_wire[3844..3844]; + l5_w0_n3_mux_dataout = sel_wire[36..36] & data_wire[3847..3847] # !(sel_wire[36..36]) & data_wire[3846..3846]; + l5_w0_n4_mux_dataout = sel_wire[36..36] & data_wire[3849..3849] # !(sel_wire[36..36]) & data_wire[3848..3848]; + l5_w0_n5_mux_dataout = sel_wire[36..36] & data_wire[3851..3851] # !(sel_wire[36..36]) & data_wire[3850..3850]; + l5_w0_n6_mux_dataout = sel_wire[36..36] & data_wire[3853..3853] # !(sel_wire[36..36]) & data_wire[3852..3852]; + l5_w0_n7_mux_dataout = sel_wire[36..36] & data_wire[3855..3855] # !(sel_wire[36..36]) & data_wire[3854..3854]; + l5_w1_n0_mux_dataout = sel_wire[36..36] & data_wire[3857..3857] # !(sel_wire[36..36]) & data_wire[3856..3856]; + l5_w1_n1_mux_dataout = sel_wire[36..36] & data_wire[3859..3859] # !(sel_wire[36..36]) & data_wire[3858..3858]; + l5_w1_n2_mux_dataout = sel_wire[36..36] & data_wire[3861..3861] # !(sel_wire[36..36]) & data_wire[3860..3860]; + l5_w1_n3_mux_dataout = sel_wire[36..36] & data_wire[3863..3863] # !(sel_wire[36..36]) & data_wire[3862..3862]; + l5_w1_n4_mux_dataout = sel_wire[36..36] & data_wire[3865..3865] # !(sel_wire[36..36]) & data_wire[3864..3864]; + l5_w1_n5_mux_dataout = sel_wire[36..36] & data_wire[3867..3867] # !(sel_wire[36..36]) & data_wire[3866..3866]; + l5_w1_n6_mux_dataout = sel_wire[36..36] & data_wire[3869..3869] # !(sel_wire[36..36]) & data_wire[3868..3868]; + l5_w1_n7_mux_dataout = sel_wire[36..36] & data_wire[3871..3871] # !(sel_wire[36..36]) & data_wire[3870..3870]; + l5_w2_n0_mux_dataout = sel_wire[36..36] & data_wire[3873..3873] # !(sel_wire[36..36]) & data_wire[3872..3872]; + l5_w2_n1_mux_dataout = sel_wire[36..36] & data_wire[3875..3875] # !(sel_wire[36..36]) & data_wire[3874..3874]; + l5_w2_n2_mux_dataout = sel_wire[36..36] & data_wire[3877..3877] # !(sel_wire[36..36]) & data_wire[3876..3876]; + l5_w2_n3_mux_dataout = sel_wire[36..36] & data_wire[3879..3879] # !(sel_wire[36..36]) & data_wire[3878..3878]; + l5_w2_n4_mux_dataout = sel_wire[36..36] & data_wire[3881..3881] # !(sel_wire[36..36]) & data_wire[3880..3880]; + l5_w2_n5_mux_dataout = sel_wire[36..36] & data_wire[3883..3883] # !(sel_wire[36..36]) & data_wire[3882..3882]; + l5_w2_n6_mux_dataout = sel_wire[36..36] & data_wire[3885..3885] # !(sel_wire[36..36]) & data_wire[3884..3884]; + l5_w2_n7_mux_dataout = sel_wire[36..36] & data_wire[3887..3887] # !(sel_wire[36..36]) & data_wire[3886..3886]; + l5_w3_n0_mux_dataout = sel_wire[36..36] & data_wire[3889..3889] # !(sel_wire[36..36]) & data_wire[3888..3888]; + l5_w3_n1_mux_dataout = sel_wire[36..36] & data_wire[3891..3891] # !(sel_wire[36..36]) & data_wire[3890..3890]; + l5_w3_n2_mux_dataout = sel_wire[36..36] & data_wire[3893..3893] # !(sel_wire[36..36]) & data_wire[3892..3892]; + l5_w3_n3_mux_dataout = sel_wire[36..36] & data_wire[3895..3895] # !(sel_wire[36..36]) & data_wire[3894..3894]; + l5_w3_n4_mux_dataout = sel_wire[36..36] & data_wire[3897..3897] # !(sel_wire[36..36]) & data_wire[3896..3896]; + l5_w3_n5_mux_dataout = sel_wire[36..36] & data_wire[3899..3899] # !(sel_wire[36..36]) & data_wire[3898..3898]; + l5_w3_n6_mux_dataout = sel_wire[36..36] & data_wire[3901..3901] # !(sel_wire[36..36]) & data_wire[3900..3900]; + l5_w3_n7_mux_dataout = sel_wire[36..36] & data_wire[3903..3903] # !(sel_wire[36..36]) & data_wire[3902..3902]; + l5_w4_n0_mux_dataout = sel_wire[36..36] & data_wire[3905..3905] # !(sel_wire[36..36]) & data_wire[3904..3904]; + l5_w4_n1_mux_dataout = sel_wire[36..36] & data_wire[3907..3907] # !(sel_wire[36..36]) & data_wire[3906..3906]; + l5_w4_n2_mux_dataout = sel_wire[36..36] & data_wire[3909..3909] # !(sel_wire[36..36]) & data_wire[3908..3908]; + l5_w4_n3_mux_dataout = sel_wire[36..36] & data_wire[3911..3911] # !(sel_wire[36..36]) & data_wire[3910..3910]; + l5_w4_n4_mux_dataout = sel_wire[36..36] & data_wire[3913..3913] # !(sel_wire[36..36]) & data_wire[3912..3912]; + l5_w4_n5_mux_dataout = sel_wire[36..36] & data_wire[3915..3915] # !(sel_wire[36..36]) & data_wire[3914..3914]; + l5_w4_n6_mux_dataout = sel_wire[36..36] & data_wire[3917..3917] # !(sel_wire[36..36]) & data_wire[3916..3916]; + l5_w4_n7_mux_dataout = sel_wire[36..36] & data_wire[3919..3919] # !(sel_wire[36..36]) & data_wire[3918..3918]; + l5_w5_n0_mux_dataout = sel_wire[36..36] & data_wire[3921..3921] # !(sel_wire[36..36]) & data_wire[3920..3920]; + l5_w5_n1_mux_dataout = sel_wire[36..36] & data_wire[3923..3923] # !(sel_wire[36..36]) & data_wire[3922..3922]; + l5_w5_n2_mux_dataout = sel_wire[36..36] & data_wire[3925..3925] # !(sel_wire[36..36]) & data_wire[3924..3924]; + l5_w5_n3_mux_dataout = sel_wire[36..36] & data_wire[3927..3927] # !(sel_wire[36..36]) & data_wire[3926..3926]; + l5_w5_n4_mux_dataout = sel_wire[36..36] & data_wire[3929..3929] # !(sel_wire[36..36]) & data_wire[3928..3928]; + l5_w5_n5_mux_dataout = sel_wire[36..36] & data_wire[3931..3931] # !(sel_wire[36..36]) & data_wire[3930..3930]; + l5_w5_n6_mux_dataout = sel_wire[36..36] & data_wire[3933..3933] # !(sel_wire[36..36]) & data_wire[3932..3932]; + l5_w5_n7_mux_dataout = sel_wire[36..36] & data_wire[3935..3935] # !(sel_wire[36..36]) & data_wire[3934..3934]; + l5_w6_n0_mux_dataout = sel_wire[36..36] & data_wire[3937..3937] # !(sel_wire[36..36]) & data_wire[3936..3936]; + l5_w6_n1_mux_dataout = sel_wire[36..36] & data_wire[3939..3939] # !(sel_wire[36..36]) & data_wire[3938..3938]; + l5_w6_n2_mux_dataout = sel_wire[36..36] & data_wire[3941..3941] # !(sel_wire[36..36]) & data_wire[3940..3940]; + l5_w6_n3_mux_dataout = sel_wire[36..36] & data_wire[3943..3943] # !(sel_wire[36..36]) & data_wire[3942..3942]; + l5_w6_n4_mux_dataout = sel_wire[36..36] & data_wire[3945..3945] # !(sel_wire[36..36]) & data_wire[3944..3944]; + l5_w6_n5_mux_dataout = sel_wire[36..36] & data_wire[3947..3947] # !(sel_wire[36..36]) & data_wire[3946..3946]; + l5_w6_n6_mux_dataout = sel_wire[36..36] & data_wire[3949..3949] # !(sel_wire[36..36]) & data_wire[3948..3948]; + l5_w6_n7_mux_dataout = sel_wire[36..36] & data_wire[3951..3951] # !(sel_wire[36..36]) & data_wire[3950..3950]; + l5_w7_n0_mux_dataout = sel_wire[36..36] & data_wire[3953..3953] # !(sel_wire[36..36]) & data_wire[3952..3952]; + l5_w7_n1_mux_dataout = sel_wire[36..36] & data_wire[3955..3955] # !(sel_wire[36..36]) & data_wire[3954..3954]; + l5_w7_n2_mux_dataout = sel_wire[36..36] & data_wire[3957..3957] # !(sel_wire[36..36]) & data_wire[3956..3956]; + l5_w7_n3_mux_dataout = sel_wire[36..36] & data_wire[3959..3959] # !(sel_wire[36..36]) & data_wire[3958..3958]; + l5_w7_n4_mux_dataout = sel_wire[36..36] & data_wire[3961..3961] # !(sel_wire[36..36]) & data_wire[3960..3960]; + l5_w7_n5_mux_dataout = sel_wire[36..36] & data_wire[3963..3963] # !(sel_wire[36..36]) & data_wire[3962..3962]; + l5_w7_n6_mux_dataout = sel_wire[36..36] & data_wire[3965..3965] # !(sel_wire[36..36]) & data_wire[3964..3964]; + l5_w7_n7_mux_dataout = sel_wire[36..36] & data_wire[3967..3967] # !(sel_wire[36..36]) & data_wire[3966..3966]; + l6_w0_n0_mux_dataout = sel_wire[45..45] & data_wire[3969..3969] # !(sel_wire[45..45]) & data_wire[3968..3968]; + l6_w0_n1_mux_dataout = sel_wire[45..45] & data_wire[3971..3971] # !(sel_wire[45..45]) & data_wire[3970..3970]; + l6_w0_n2_mux_dataout = sel_wire[45..45] & data_wire[3973..3973] # !(sel_wire[45..45]) & data_wire[3972..3972]; + l6_w0_n3_mux_dataout = sel_wire[45..45] & data_wire[3975..3975] # !(sel_wire[45..45]) & data_wire[3974..3974]; + l6_w1_n0_mux_dataout = sel_wire[45..45] & data_wire[3977..3977] # !(sel_wire[45..45]) & data_wire[3976..3976]; + l6_w1_n1_mux_dataout = sel_wire[45..45] & data_wire[3979..3979] # !(sel_wire[45..45]) & data_wire[3978..3978]; + l6_w1_n2_mux_dataout = sel_wire[45..45] & data_wire[3981..3981] # !(sel_wire[45..45]) & data_wire[3980..3980]; + l6_w1_n3_mux_dataout = sel_wire[45..45] & data_wire[3983..3983] # !(sel_wire[45..45]) & data_wire[3982..3982]; + l6_w2_n0_mux_dataout = sel_wire[45..45] & data_wire[3985..3985] # !(sel_wire[45..45]) & data_wire[3984..3984]; + l6_w2_n1_mux_dataout = sel_wire[45..45] & data_wire[3987..3987] # !(sel_wire[45..45]) & data_wire[3986..3986]; + l6_w2_n2_mux_dataout = sel_wire[45..45] & data_wire[3989..3989] # !(sel_wire[45..45]) & data_wire[3988..3988]; + l6_w2_n3_mux_dataout = sel_wire[45..45] & data_wire[3991..3991] # !(sel_wire[45..45]) & data_wire[3990..3990]; + l6_w3_n0_mux_dataout = sel_wire[45..45] & data_wire[3993..3993] # !(sel_wire[45..45]) & data_wire[3992..3992]; + l6_w3_n1_mux_dataout = sel_wire[45..45] & data_wire[3995..3995] # !(sel_wire[45..45]) & data_wire[3994..3994]; + l6_w3_n2_mux_dataout = sel_wire[45..45] & data_wire[3997..3997] # !(sel_wire[45..45]) & data_wire[3996..3996]; + l6_w3_n3_mux_dataout = sel_wire[45..45] & data_wire[3999..3999] # !(sel_wire[45..45]) & data_wire[3998..3998]; + l6_w4_n0_mux_dataout = sel_wire[45..45] & data_wire[4001..4001] # !(sel_wire[45..45]) & data_wire[4000..4000]; + l6_w4_n1_mux_dataout = sel_wire[45..45] & data_wire[4003..4003] # !(sel_wire[45..45]) & data_wire[4002..4002]; + l6_w4_n2_mux_dataout = sel_wire[45..45] & data_wire[4005..4005] # !(sel_wire[45..45]) & data_wire[4004..4004]; + l6_w4_n3_mux_dataout = sel_wire[45..45] & data_wire[4007..4007] # !(sel_wire[45..45]) & data_wire[4006..4006]; + l6_w5_n0_mux_dataout = sel_wire[45..45] & data_wire[4009..4009] # !(sel_wire[45..45]) & data_wire[4008..4008]; + l6_w5_n1_mux_dataout = sel_wire[45..45] & data_wire[4011..4011] # !(sel_wire[45..45]) & data_wire[4010..4010]; + l6_w5_n2_mux_dataout = sel_wire[45..45] & data_wire[4013..4013] # !(sel_wire[45..45]) & data_wire[4012..4012]; + l6_w5_n3_mux_dataout = sel_wire[45..45] & data_wire[4015..4015] # !(sel_wire[45..45]) & data_wire[4014..4014]; + l6_w6_n0_mux_dataout = sel_wire[45..45] & data_wire[4017..4017] # !(sel_wire[45..45]) & data_wire[4016..4016]; + l6_w6_n1_mux_dataout = sel_wire[45..45] & data_wire[4019..4019] # !(sel_wire[45..45]) & data_wire[4018..4018]; + l6_w6_n2_mux_dataout = sel_wire[45..45] & data_wire[4021..4021] # !(sel_wire[45..45]) & data_wire[4020..4020]; + l6_w6_n3_mux_dataout = sel_wire[45..45] & data_wire[4023..4023] # !(sel_wire[45..45]) & data_wire[4022..4022]; + l6_w7_n0_mux_dataout = sel_wire[45..45] & data_wire[4025..4025] # !(sel_wire[45..45]) & data_wire[4024..4024]; + l6_w7_n1_mux_dataout = sel_wire[45..45] & data_wire[4027..4027] # !(sel_wire[45..45]) & data_wire[4026..4026]; + l6_w7_n2_mux_dataout = sel_wire[45..45] & data_wire[4029..4029] # !(sel_wire[45..45]) & data_wire[4028..4028]; + l6_w7_n3_mux_dataout = sel_wire[45..45] & data_wire[4031..4031] # !(sel_wire[45..45]) & data_wire[4030..4030]; + l7_w0_n0_mux_dataout = sel_wire[54..54] & data_wire[4033..4033] # !(sel_wire[54..54]) & data_wire[4032..4032]; + l7_w0_n1_mux_dataout = sel_wire[54..54] & data_wire[4035..4035] # !(sel_wire[54..54]) & data_wire[4034..4034]; + l7_w1_n0_mux_dataout = sel_wire[54..54] & data_wire[4037..4037] # !(sel_wire[54..54]) & data_wire[4036..4036]; + l7_w1_n1_mux_dataout = sel_wire[54..54] & data_wire[4039..4039] # !(sel_wire[54..54]) & data_wire[4038..4038]; + l7_w2_n0_mux_dataout = sel_wire[54..54] & data_wire[4041..4041] # !(sel_wire[54..54]) & data_wire[4040..4040]; + l7_w2_n1_mux_dataout = sel_wire[54..54] & data_wire[4043..4043] # !(sel_wire[54..54]) & data_wire[4042..4042]; + l7_w3_n0_mux_dataout = sel_wire[54..54] & data_wire[4045..4045] # !(sel_wire[54..54]) & data_wire[4044..4044]; + l7_w3_n1_mux_dataout = sel_wire[54..54] & data_wire[4047..4047] # !(sel_wire[54..54]) & data_wire[4046..4046]; + l7_w4_n0_mux_dataout = sel_wire[54..54] & data_wire[4049..4049] # !(sel_wire[54..54]) & data_wire[4048..4048]; + l7_w4_n1_mux_dataout = sel_wire[54..54] & data_wire[4051..4051] # !(sel_wire[54..54]) & data_wire[4050..4050]; + l7_w5_n0_mux_dataout = sel_wire[54..54] & data_wire[4053..4053] # !(sel_wire[54..54]) & data_wire[4052..4052]; + l7_w5_n1_mux_dataout = sel_wire[54..54] & data_wire[4055..4055] # !(sel_wire[54..54]) & data_wire[4054..4054]; + l7_w6_n0_mux_dataout = sel_wire[54..54] & data_wire[4057..4057] # !(sel_wire[54..54]) & data_wire[4056..4056]; + l7_w6_n1_mux_dataout = sel_wire[54..54] & data_wire[4059..4059] # !(sel_wire[54..54]) & data_wire[4058..4058]; + l7_w7_n0_mux_dataout = sel_wire[54..54] & data_wire[4061..4061] # !(sel_wire[54..54]) & data_wire[4060..4060]; + l7_w7_n1_mux_dataout = sel_wire[54..54] & data_wire[4063..4063] # !(sel_wire[54..54]) & data_wire[4062..4062]; + l8_w0_n0_mux_dataout = sel_wire[63..63] & data_wire[4065..4065] # !(sel_wire[63..63]) & data_wire[4064..4064]; + l8_w1_n0_mux_dataout = sel_wire[63..63] & data_wire[4067..4067] # !(sel_wire[63..63]) & data_wire[4066..4066]; + l8_w2_n0_mux_dataout = sel_wire[63..63] & data_wire[4069..4069] # !(sel_wire[63..63]) & data_wire[4068..4068]; + l8_w3_n0_mux_dataout = sel_wire[63..63] & data_wire[4071..4071] # !(sel_wire[63..63]) & data_wire[4070..4070]; + l8_w4_n0_mux_dataout = sel_wire[63..63] & data_wire[4073..4073] # !(sel_wire[63..63]) & data_wire[4072..4072]; + l8_w5_n0_mux_dataout = sel_wire[63..63] & data_wire[4075..4075] # !(sel_wire[63..63]) & data_wire[4074..4074]; + l8_w6_n0_mux_dataout = sel_wire[63..63] & data_wire[4077..4077] # !(sel_wire[63..63]) & data_wire[4076..4076]; + l8_w7_n0_mux_dataout = sel_wire[63..63] & data_wire[4079..4079] # !(sel_wire[63..63]) & data_wire[4078..4078]; + data_wire[] = ( l7_w7_n1_mux_dataout, l7_w7_n0_mux_dataout, l7_w6_n1_mux_dataout, l7_w6_n0_mux_dataout, l7_w5_n1_mux_dataout, l7_w5_n0_mux_dataout, l7_w4_n1_mux_dataout, l7_w4_n0_mux_dataout, l7_w3_n1_mux_dataout, l7_w3_n0_mux_dataout, l7_w2_n1_mux_dataout, l7_w2_n0_mux_dataout, l7_w1_n1_mux_dataout, l7_w1_n0_mux_dataout, l7_w0_n1_mux_dataout, l7_w0_n0_mux_dataout, l6_w7_n3_mux_dataout, l6_w7_n2_mux_dataout, l6_w7_n1_mux_dataout, l6_w7_n0_mux_dataout, l6_w6_n3_mux_dataout, l6_w6_n2_mux_dataout, l6_w6_n1_mux_dataout, l6_w6_n0_mux_dataout, l6_w5_n3_mux_dataout, l6_w5_n2_mux_dataout, l6_w5_n1_mux_dataout, l6_w5_n0_mux_dataout, l6_w4_n3_mux_dataout, l6_w4_n2_mux_dataout, l6_w4_n1_mux_dataout, l6_w4_n0_mux_dataout, l6_w3_n3_mux_dataout, l6_w3_n2_mux_dataout, l6_w3_n1_mux_dataout, l6_w3_n0_mux_dataout, l6_w2_n3_mux_dataout, l6_w2_n2_mux_dataout, l6_w2_n1_mux_dataout, l6_w2_n0_mux_dataout, l6_w1_n3_mux_dataout, l6_w1_n2_mux_dataout, l6_w1_n1_mux_dataout, l6_w1_n0_mux_dataout, l6_w0_n3_mux_dataout, l6_w0_n2_mux_dataout, l6_w0_n1_mux_dataout, l6_w0_n0_mux_dataout, l5_w7_n7_mux_dataout, l5_w7_n6_mux_dataout, l5_w7_n5_mux_dataout, l5_w7_n4_mux_dataout, l5_w7_n3_mux_dataout, l5_w7_n2_mux_dataout, l5_w7_n1_mux_dataout, l5_w7_n0_mux_dataout, l5_w6_n7_mux_dataout, l5_w6_n6_mux_dataout, l5_w6_n5_mux_dataout, l5_w6_n4_mux_dataout, l5_w6_n3_mux_dataout, l5_w6_n2_mux_dataout, l5_w6_n1_mux_dataout, l5_w6_n0_mux_dataout, l5_w5_n7_mux_dataout, l5_w5_n6_mux_dataout, l5_w5_n5_mux_dataout, l5_w5_n4_mux_dataout, l5_w5_n3_mux_dataout, l5_w5_n2_mux_dataout, l5_w5_n1_mux_dataout, l5_w5_n0_mux_dataout, l5_w4_n7_mux_dataout, l5_w4_n6_mux_dataout, l5_w4_n5_mux_dataout, l5_w4_n4_mux_dataout, l5_w4_n3_mux_dataout, l5_w4_n2_mux_dataout, l5_w4_n1_mux_dataout, l5_w4_n0_mux_dataout, l5_w3_n7_mux_dataout, l5_w3_n6_mux_dataout, l5_w3_n5_mux_dataout, l5_w3_n4_mux_dataout, l5_w3_n3_mux_dataout, l5_w3_n2_mux_dataout, l5_w3_n1_mux_dataout, l5_w3_n0_mux_dataout, l5_w2_n7_mux_dataout, l5_w2_n6_mux_dataout, l5_w2_n5_mux_dataout, l5_w2_n4_mux_dataout, l5_w2_n3_mux_dataout, l5_w2_n2_mux_dataout, l5_w2_n1_mux_dataout, l5_w2_n0_mux_dataout, l5_w1_n7_mux_dataout, l5_w1_n6_mux_dataout, l5_w1_n5_mux_dataout, l5_w1_n4_mux_dataout, l5_w1_n3_mux_dataout, l5_w1_n2_mux_dataout, l5_w1_n1_mux_dataout, l5_w1_n0_mux_dataout, l5_w0_n7_mux_dataout, l5_w0_n6_mux_dataout, l5_w0_n5_mux_dataout, l5_w0_n4_mux_dataout, l5_w0_n3_mux_dataout, l5_w0_n2_mux_dataout, l5_w0_n1_mux_dataout, l5_w0_n0_mux_dataout, l4_w7_n15_mux_dataout, l4_w7_n14_mux_dataout, l4_w7_n13_mux_dataout, l4_w7_n12_mux_dataout, l4_w7_n11_mux_dataout, l4_w7_n10_mux_dataout, l4_w7_n9_mux_dataout, l4_w7_n8_mux_dataout, l4_w7_n7_mux_dataout, l4_w7_n6_mux_dataout, l4_w7_n5_mux_dataout, l4_w7_n4_mux_dataout, l4_w7_n3_mux_dataout, l4_w7_n2_mux_dataout, l4_w7_n1_mux_dataout, l4_w7_n0_mux_dataout, l4_w6_n15_mux_dataout, l4_w6_n14_mux_dataout, l4_w6_n13_mux_dataout, l4_w6_n12_mux_dataout, l4_w6_n11_mux_dataout, l4_w6_n10_mux_dataout, l4_w6_n9_mux_dataout, l4_w6_n8_mux_dataout, l4_w6_n7_mux_dataout, l4_w6_n6_mux_dataout, l4_w6_n5_mux_dataout, l4_w6_n4_mux_dataout, l4_w6_n3_mux_dataout, l4_w6_n2_mux_dataout, l4_w6_n1_mux_dataout, l4_w6_n0_mux_dataout, l4_w5_n15_mux_dataout, l4_w5_n14_mux_dataout, l4_w5_n13_mux_dataout, l4_w5_n12_mux_dataout, l4_w5_n11_mux_dataout, l4_w5_n10_mux_dataout, l4_w5_n9_mux_dataout, l4_w5_n8_mux_dataout, l4_w5_n7_mux_dataout, l4_w5_n6_mux_dataout, l4_w5_n5_mux_dataout, l4_w5_n4_mux_dataout, l4_w5_n3_mux_dataout, l4_w5_n2_mux_dataout, l4_w5_n1_mux_dataout, l4_w5_n0_mux_dataout, l4_w4_n15_mux_dataout, l4_w4_n14_mux_dataout, l4_w4_n13_mux_dataout, l4_w4_n12_mux_dataout, l4_w4_n11_mux_dataout, l4_w4_n10_mux_dataout, l4_w4_n9_mux_dataout, l4_w4_n8_mux_dataout, l4_w4_n7_mux_dataout, l4_w4_n6_mux_dataout, l4_w4_n5_mux_dataout, l4_w4_n4_mux_dataout, l4_w4_n3_mux_dataout, l4_w4_n2_mux_dataout, l4_w4_n1_mux_dataout, l4_w4_n0_mux_dataout, l4_w3_n15_mux_dataout, l4_w3_n14_mux_dataout, l4_w3_n13_mux_dataout, l4_w3_n12_mux_dataout, l4_w3_n11_mux_dataout, l4_w3_n10_mux_dataout, l4_w3_n9_mux_dataout, l4_w3_n8_mux_dataout, l4_w3_n7_mux_dataout, l4_w3_n6_mux_dataout, l4_w3_n5_mux_dataout, l4_w3_n4_mux_dataout, l4_w3_n3_mux_dataout, l4_w3_n2_mux_dataout, l4_w3_n1_mux_dataout, l4_w3_n0_mux_dataout, l4_w2_n15_mux_dataout, l4_w2_n14_mux_dataout, l4_w2_n13_mux_dataout, l4_w2_n12_mux_dataout, l4_w2_n11_mux_dataout, l4_w2_n10_mux_dataout, l4_w2_n9_mux_dataout, l4_w2_n8_mux_dataout, l4_w2_n7_mux_dataout, l4_w2_n6_mux_dataout, l4_w2_n5_mux_dataout, l4_w2_n4_mux_dataout, l4_w2_n3_mux_dataout, l4_w2_n2_mux_dataout, l4_w2_n1_mux_dataout, l4_w2_n0_mux_dataout, l4_w1_n15_mux_dataout, l4_w1_n14_mux_dataout, l4_w1_n13_mux_dataout, l4_w1_n12_mux_dataout, l4_w1_n11_mux_dataout, l4_w1_n10_mux_dataout, l4_w1_n9_mux_dataout, l4_w1_n8_mux_dataout, l4_w1_n7_mux_dataout, l4_w1_n6_mux_dataout, l4_w1_n5_mux_dataout, l4_w1_n4_mux_dataout, l4_w1_n3_mux_dataout, l4_w1_n2_mux_dataout, l4_w1_n1_mux_dataout, l4_w1_n0_mux_dataout, l4_w0_n15_mux_dataout, l4_w0_n14_mux_dataout, l4_w0_n13_mux_dataout, l4_w0_n12_mux_dataout, l4_w0_n11_mux_dataout, l4_w0_n10_mux_dataout, l4_w0_n9_mux_dataout, l4_w0_n8_mux_dataout, l4_w0_n7_mux_dataout, l4_w0_n6_mux_dataout, l4_w0_n5_mux_dataout, l4_w0_n4_mux_dataout, l4_w0_n3_mux_dataout, l4_w0_n2_mux_dataout, l4_w0_n1_mux_dataout, l4_w0_n0_mux_dataout, l3_w7_n31_mux_dataout, l3_w7_n30_mux_dataout, l3_w7_n29_mux_dataout, l3_w7_n28_mux_dataout, l3_w7_n27_mux_dataout, l3_w7_n26_mux_dataout, l3_w7_n25_mux_dataout, l3_w7_n24_mux_dataout, l3_w7_n23_mux_dataout, l3_w7_n22_mux_dataout, l3_w7_n21_mux_dataout, l3_w7_n20_mux_dataout, l3_w7_n19_mux_dataout, l3_w7_n18_mux_dataout, l3_w7_n17_mux_dataout, l3_w7_n16_mux_dataout, l3_w7_n15_mux_dataout, l3_w7_n14_mux_dataout, l3_w7_n13_mux_dataout, l3_w7_n12_mux_dataout, l3_w7_n11_mux_dataout, l3_w7_n10_mux_dataout, l3_w7_n9_mux_dataout, l3_w7_n8_mux_dataout, l3_w7_n7_mux_dataout, l3_w7_n6_mux_dataout, l3_w7_n5_mux_dataout, l3_w7_n4_mux_dataout, l3_w7_n3_mux_dataout, l3_w7_n2_mux_dataout, l3_w7_n1_mux_dataout, l3_w7_n0_mux_dataout, l3_w6_n31_mux_dataout, l3_w6_n30_mux_dataout, l3_w6_n29_mux_dataout, l3_w6_n28_mux_dataout, l3_w6_n27_mux_dataout, l3_w6_n26_mux_dataout, l3_w6_n25_mux_dataout, l3_w6_n24_mux_dataout, l3_w6_n23_mux_dataout, l3_w6_n22_mux_dataout, l3_w6_n21_mux_dataout, l3_w6_n20_mux_dataout, l3_w6_n19_mux_dataout, l3_w6_n18_mux_dataout, l3_w6_n17_mux_dataout, l3_w6_n16_mux_dataout, l3_w6_n15_mux_dataout, l3_w6_n14_mux_dataout, l3_w6_n13_mux_dataout, l3_w6_n12_mux_dataout, l3_w6_n11_mux_dataout, l3_w6_n10_mux_dataout, l3_w6_n9_mux_dataout, l3_w6_n8_mux_dataout, l3_w6_n7_mux_dataout, l3_w6_n6_mux_dataout, l3_w6_n5_mux_dataout, l3_w6_n4_mux_dataout, l3_w6_n3_mux_dataout, l3_w6_n2_mux_dataout, l3_w6_n1_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n31_mux_dataout, l3_w5_n30_mux_dataout, l3_w5_n29_mux_dataout, l3_w5_n28_mux_dataout, l3_w5_n27_mux_dataout, l3_w5_n26_mux_dataout, l3_w5_n25_mux_dataout, l3_w5_n24_mux_dataout, l3_w5_n23_mux_dataout, l3_w5_n22_mux_dataout, l3_w5_n21_mux_dataout, l3_w5_n20_mux_dataout, l3_w5_n19_mux_dataout, l3_w5_n18_mux_dataout, l3_w5_n17_mux_dataout, l3_w5_n16_mux_dataout, l3_w5_n15_mux_dataout, l3_w5_n14_mux_dataout, l3_w5_n13_mux_dataout, l3_w5_n12_mux_dataout, l3_w5_n11_mux_dataout, l3_w5_n10_mux_dataout, l3_w5_n9_mux_dataout, l3_w5_n8_mux_dataout, l3_w5_n7_mux_dataout, l3_w5_n6_mux_dataout, l3_w5_n5_mux_dataout, l3_w5_n4_mux_dataout, l3_w5_n3_mux_dataout, l3_w5_n2_mux_dataout, l3_w5_n1_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n31_mux_dataout, l3_w4_n30_mux_dataout, l3_w4_n29_mux_dataout, l3_w4_n28_mux_dataout, l3_w4_n27_mux_dataout, l3_w4_n26_mux_dataout, l3_w4_n25_mux_dataout, l3_w4_n24_mux_dataout, l3_w4_n23_mux_dataout, l3_w4_n22_mux_dataout, l3_w4_n21_mux_dataout, l3_w4_n20_mux_dataout, l3_w4_n19_mux_dataout, l3_w4_n18_mux_dataout, l3_w4_n17_mux_dataout, l3_w4_n16_mux_dataout, l3_w4_n15_mux_dataout, l3_w4_n14_mux_dataout, l3_w4_n13_mux_dataout, l3_w4_n12_mux_dataout, l3_w4_n11_mux_dataout, l3_w4_n10_mux_dataout, l3_w4_n9_mux_dataout, l3_w4_n8_mux_dataout, l3_w4_n7_mux_dataout, l3_w4_n6_mux_dataout, l3_w4_n5_mux_dataout, l3_w4_n4_mux_dataout, l3_w4_n3_mux_dataout, l3_w4_n2_mux_dataout, l3_w4_n1_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n31_mux_dataout, l3_w3_n30_mux_dataout, l3_w3_n29_mux_dataout, l3_w3_n28_mux_dataout, l3_w3_n27_mux_dataout, l3_w3_n26_mux_dataout, l3_w3_n25_mux_dataout, l3_w3_n24_mux_dataout, l3_w3_n23_mux_dataout, l3_w3_n22_mux_dataout, l3_w3_n21_mux_dataout, l3_w3_n20_mux_dataout, l3_w3_n19_mux_dataout, l3_w3_n18_mux_dataout, l3_w3_n17_mux_dataout, l3_w3_n16_mux_dataout, l3_w3_n15_mux_dataout, l3_w3_n14_mux_dataout, l3_w3_n13_mux_dataout, l3_w3_n12_mux_dataout, l3_w3_n11_mux_dataout, l3_w3_n10_mux_dataout, l3_w3_n9_mux_dataout, l3_w3_n8_mux_dataout, l3_w3_n7_mux_dataout, l3_w3_n6_mux_dataout, l3_w3_n5_mux_dataout, l3_w3_n4_mux_dataout, l3_w3_n3_mux_dataout, l3_w3_n2_mux_dataout, l3_w3_n1_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n31_mux_dataout, l3_w2_n30_mux_dataout, l3_w2_n29_mux_dataout, l3_w2_n28_mux_dataout, l3_w2_n27_mux_dataout, l3_w2_n26_mux_dataout, l3_w2_n25_mux_dataout, l3_w2_n24_mux_dataout, l3_w2_n23_mux_dataout, l3_w2_n22_mux_dataout, l3_w2_n21_mux_dataout, l3_w2_n20_mux_dataout, l3_w2_n19_mux_dataout, l3_w2_n18_mux_dataout, l3_w2_n17_mux_dataout, l3_w2_n16_mux_dataout, l3_w2_n15_mux_dataout, l3_w2_n14_mux_dataout, l3_w2_n13_mux_dataout, l3_w2_n12_mux_dataout, l3_w2_n11_mux_dataout, l3_w2_n10_mux_dataout, l3_w2_n9_mux_dataout, l3_w2_n8_mux_dataout, l3_w2_n7_mux_dataout, l3_w2_n6_mux_dataout, l3_w2_n5_mux_dataout, l3_w2_n4_mux_dataout, l3_w2_n3_mux_dataout, l3_w2_n2_mux_dataout, l3_w2_n1_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n31_mux_dataout, l3_w1_n30_mux_dataout, l3_w1_n29_mux_dataout, l3_w1_n28_mux_dataout, l3_w1_n27_mux_dataout, l3_w1_n26_mux_dataout, l3_w1_n25_mux_dataout, l3_w1_n24_mux_dataout, l3_w1_n23_mux_dataout, l3_w1_n22_mux_dataout, l3_w1_n21_mux_dataout, l3_w1_n20_mux_dataout, l3_w1_n19_mux_dataout, l3_w1_n18_mux_dataout, l3_w1_n17_mux_dataout, l3_w1_n16_mux_dataout, l3_w1_n15_mux_dataout, l3_w1_n14_mux_dataout, l3_w1_n13_mux_dataout, l3_w1_n12_mux_dataout, l3_w1_n11_mux_dataout, l3_w1_n10_mux_dataout, l3_w1_n9_mux_dataout, l3_w1_n8_mux_dataout, l3_w1_n7_mux_dataout, l3_w1_n6_mux_dataout, l3_w1_n5_mux_dataout, l3_w1_n4_mux_dataout, l3_w1_n3_mux_dataout, l3_w1_n2_mux_dataout, l3_w1_n1_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n31_mux_dataout, l3_w0_n30_mux_dataout, l3_w0_n29_mux_dataout, l3_w0_n28_mux_dataout, l3_w0_n27_mux_dataout, l3_w0_n26_mux_dataout, l3_w0_n25_mux_dataout, l3_w0_n24_mux_dataout, l3_w0_n23_mux_dataout, l3_w0_n22_mux_dataout, l3_w0_n21_mux_dataout, l3_w0_n20_mux_dataout, l3_w0_n19_mux_dataout, l3_w0_n18_mux_dataout, l3_w0_n17_mux_dataout, l3_w0_n16_mux_dataout, l3_w0_n15_mux_dataout, l3_w0_n14_mux_dataout, l3_w0_n13_mux_dataout, l3_w0_n12_mux_dataout, l3_w0_n11_mux_dataout, l3_w0_n10_mux_dataout, l3_w0_n9_mux_dataout, l3_w0_n8_mux_dataout, l3_w0_n7_mux_dataout, l3_w0_n6_mux_dataout, l3_w0_n5_mux_dataout, l3_w0_n4_mux_dataout, l3_w0_n3_mux_dataout, l3_w0_n2_mux_dataout, l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w7_n63_mux_dataout, l2_w7_n62_mux_dataout, l2_w7_n61_mux_dataout, l2_w7_n60_mux_dataout, l2_w7_n59_mux_dataout, l2_w7_n58_mux_dataout, l2_w7_n57_mux_dataout, l2_w7_n56_mux_dataout, l2_w7_n55_mux_dataout, l2_w7_n54_mux_dataout, l2_w7_n53_mux_dataout, l2_w7_n52_mux_dataout, l2_w7_n51_mux_dataout, l2_w7_n50_mux_dataout, l2_w7_n49_mux_dataout, l2_w7_n48_mux_dataout, l2_w7_n47_mux_dataout, l2_w7_n46_mux_dataout, l2_w7_n45_mux_dataout, l2_w7_n44_mux_dataout, l2_w7_n43_mux_dataout, l2_w7_n42_mux_dataout, l2_w7_n41_mux_dataout, l2_w7_n40_mux_dataout, l2_w7_n39_mux_dataout, l2_w7_n38_mux_dataout, l2_w7_n37_mux_dataout, l2_w7_n36_mux_dataout, l2_w7_n35_mux_dataout, l2_w7_n34_mux_dataout, l2_w7_n33_mux_dataout, l2_w7_n32_mux_dataout, l2_w7_n31_mux_dataout, l2_w7_n30_mux_dataout, l2_w7_n29_mux_dataout, l2_w7_n28_mux_dataout, l2_w7_n27_mux_dataout, l2_w7_n26_mux_dataout, l2_w7_n25_mux_dataout, l2_w7_n24_mux_dataout, l2_w7_n23_mux_dataout, l2_w7_n22_mux_dataout, l2_w7_n21_mux_dataout, l2_w7_n20_mux_dataout, l2_w7_n19_mux_dataout, l2_w7_n18_mux_dataout, l2_w7_n17_mux_dataout, l2_w7_n16_mux_dataout, l2_w7_n15_mux_dataout, l2_w7_n14_mux_dataout, l2_w7_n13_mux_dataout, l2_w7_n12_mux_dataout, l2_w7_n11_mux_dataout, l2_w7_n10_mux_dataout, l2_w7_n9_mux_dataout, l2_w7_n8_mux_dataout, l2_w7_n7_mux_dataout, l2_w7_n6_mux_dataout, l2_w7_n5_mux_dataout, l2_w7_n4_mux_dataout, l2_w7_n3_mux_dataout, l2_w7_n2_mux_dataout, l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n63_mux_dataout, l2_w6_n62_mux_dataout, l2_w6_n61_mux_dataout, l2_w6_n60_mux_dataout, l2_w6_n59_mux_dataout, l2_w6_n58_mux_dataout, l2_w6_n57_mux_dataout, l2_w6_n56_mux_dataout, l2_w6_n55_mux_dataout, l2_w6_n54_mux_dataout, l2_w6_n53_mux_dataout, l2_w6_n52_mux_dataout, l2_w6_n51_mux_dataout, l2_w6_n50_mux_dataout, l2_w6_n49_mux_dataout, l2_w6_n48_mux_dataout, l2_w6_n47_mux_dataout, l2_w6_n46_mux_dataout, l2_w6_n45_mux_dataout, l2_w6_n44_mux_dataout, l2_w6_n43_mux_dataout, l2_w6_n42_mux_dataout, l2_w6_n41_mux_dataout, l2_w6_n40_mux_dataout, l2_w6_n39_mux_dataout, l2_w6_n38_mux_dataout, l2_w6_n37_mux_dataout, l2_w6_n36_mux_dataout, l2_w6_n35_mux_dataout, l2_w6_n34_mux_dataout, l2_w6_n33_mux_dataout, l2_w6_n32_mux_dataout, l2_w6_n31_mux_dataout, l2_w6_n30_mux_dataout, l2_w6_n29_mux_dataout, l2_w6_n28_mux_dataout, l2_w6_n27_mux_dataout, l2_w6_n26_mux_dataout, l2_w6_n25_mux_dataout, l2_w6_n24_mux_dataout, l2_w6_n23_mux_dataout, l2_w6_n22_mux_dataout, l2_w6_n21_mux_dataout, l2_w6_n20_mux_dataout, l2_w6_n19_mux_dataout, l2_w6_n18_mux_dataout, l2_w6_n17_mux_dataout, l2_w6_n16_mux_dataout, l2_w6_n15_mux_dataout, l2_w6_n14_mux_dataout, l2_w6_n13_mux_dataout, l2_w6_n12_mux_dataout, l2_w6_n11_mux_dataout, l2_w6_n10_mux_dataout, l2_w6_n9_mux_dataout, l2_w6_n8_mux_dataout, l2_w6_n7_mux_dataout, l2_w6_n6_mux_dataout, l2_w6_n5_mux_dataout, l2_w6_n4_mux_dataout, l2_w6_n3_mux_dataout, l2_w6_n2_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n63_mux_dataout, l2_w5_n62_mux_dataout, l2_w5_n61_mux_dataout, l2_w5_n60_mux_dataout, l2_w5_n59_mux_dataout, l2_w5_n58_mux_dataout, l2_w5_n57_mux_dataout, l2_w5_n56_mux_dataout, l2_w5_n55_mux_dataout, l2_w5_n54_mux_dataout, l2_w5_n53_mux_dataout, l2_w5_n52_mux_dataout, l2_w5_n51_mux_dataout, l2_w5_n50_mux_dataout, l2_w5_n49_mux_dataout, l2_w5_n48_mux_dataout, l2_w5_n47_mux_dataout, l2_w5_n46_mux_dataout, l2_w5_n45_mux_dataout, l2_w5_n44_mux_dataout, l2_w5_n43_mux_dataout, l2_w5_n42_mux_dataout, l2_w5_n41_mux_dataout, l2_w5_n40_mux_dataout, l2_w5_n39_mux_dataout, l2_w5_n38_mux_dataout, l2_w5_n37_mux_dataout, l2_w5_n36_mux_dataout, l2_w5_n35_mux_dataout, l2_w5_n34_mux_dataout, l2_w5_n33_mux_dataout, l2_w5_n32_mux_dataout, l2_w5_n31_mux_dataout, l2_w5_n30_mux_dataout, l2_w5_n29_mux_dataout, l2_w5_n28_mux_dataout, l2_w5_n27_mux_dataout, l2_w5_n26_mux_dataout, l2_w5_n25_mux_dataout, l2_w5_n24_mux_dataout, l2_w5_n23_mux_dataout, l2_w5_n22_mux_dataout, l2_w5_n21_mux_dataout, l2_w5_n20_mux_dataout, l2_w5_n19_mux_dataout, l2_w5_n18_mux_dataout, l2_w5_n17_mux_dataout, l2_w5_n16_mux_dataout, l2_w5_n15_mux_dataout, l2_w5_n14_mux_dataout, l2_w5_n13_mux_dataout, l2_w5_n12_mux_dataout, l2_w5_n11_mux_dataout, l2_w5_n10_mux_dataout, l2_w5_n9_mux_dataout, l2_w5_n8_mux_dataout, l2_w5_n7_mux_dataout, l2_w5_n6_mux_dataout, l2_w5_n5_mux_dataout, l2_w5_n4_mux_dataout, l2_w5_n3_mux_dataout, l2_w5_n2_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n63_mux_dataout, l2_w4_n62_mux_dataout, l2_w4_n61_mux_dataout, l2_w4_n60_mux_dataout, l2_w4_n59_mux_dataout, l2_w4_n58_mux_dataout, l2_w4_n57_mux_dataout, l2_w4_n56_mux_dataout, l2_w4_n55_mux_dataout, l2_w4_n54_mux_dataout, l2_w4_n53_mux_dataout, l2_w4_n52_mux_dataout, l2_w4_n51_mux_dataout, l2_w4_n50_mux_dataout, l2_w4_n49_mux_dataout, l2_w4_n48_mux_dataout, l2_w4_n47_mux_dataout, l2_w4_n46_mux_dataout, l2_w4_n45_mux_dataout, l2_w4_n44_mux_dataout, l2_w4_n43_mux_dataout, l2_w4_n42_mux_dataout, l2_w4_n41_mux_dataout, l2_w4_n40_mux_dataout, l2_w4_n39_mux_dataout, l2_w4_n38_mux_dataout, l2_w4_n37_mux_dataout, l2_w4_n36_mux_dataout, l2_w4_n35_mux_dataout, l2_w4_n34_mux_dataout, l2_w4_n33_mux_dataout, l2_w4_n32_mux_dataout, l2_w4_n31_mux_dataout, l2_w4_n30_mux_dataout, l2_w4_n29_mux_dataout, l2_w4_n28_mux_dataout, l2_w4_n27_mux_dataout, l2_w4_n26_mux_dataout, l2_w4_n25_mux_dataout, l2_w4_n24_mux_dataout, l2_w4_n23_mux_dataout, l2_w4_n22_mux_dataout, l2_w4_n21_mux_dataout, l2_w4_n20_mux_dataout, l2_w4_n19_mux_dataout, l2_w4_n18_mux_dataout, l2_w4_n17_mux_dataout, l2_w4_n16_mux_dataout, l2_w4_n15_mux_dataout, l2_w4_n14_mux_dataout, l2_w4_n13_mux_dataout, l2_w4_n12_mux_dataout, l2_w4_n11_mux_dataout, l2_w4_n10_mux_dataout, l2_w4_n9_mux_dataout, l2_w4_n8_mux_dataout, l2_w4_n7_mux_dataout, l2_w4_n6_mux_dataout, l2_w4_n5_mux_dataout, l2_w4_n4_mux_dataout, l2_w4_n3_mux_dataout, l2_w4_n2_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n63_mux_dataout, l2_w3_n62_mux_dataout, l2_w3_n61_mux_dataout, l2_w3_n60_mux_dataout, l2_w3_n59_mux_dataout, l2_w3_n58_mux_dataout, l2_w3_n57_mux_dataout, l2_w3_n56_mux_dataout, l2_w3_n55_mux_dataout, l2_w3_n54_mux_dataout, l2_w3_n53_mux_dataout, l2_w3_n52_mux_dataout, l2_w3_n51_mux_dataout, l2_w3_n50_mux_dataout, l2_w3_n49_mux_dataout, l2_w3_n48_mux_dataout, l2_w3_n47_mux_dataout, l2_w3_n46_mux_dataout, l2_w3_n45_mux_dataout, l2_w3_n44_mux_dataout, l2_w3_n43_mux_dataout, l2_w3_n42_mux_dataout, l2_w3_n41_mux_dataout, l2_w3_n40_mux_dataout, l2_w3_n39_mux_dataout, l2_w3_n38_mux_dataout, l2_w3_n37_mux_dataout, l2_w3_n36_mux_dataout, l2_w3_n35_mux_dataout, l2_w3_n34_mux_dataout, l2_w3_n33_mux_dataout, l2_w3_n32_mux_dataout, l2_w3_n31_mux_dataout, l2_w3_n30_mux_dataout, l2_w3_n29_mux_dataout, l2_w3_n28_mux_dataout, l2_w3_n27_mux_dataout, l2_w3_n26_mux_dataout, l2_w3_n25_mux_dataout, l2_w3_n24_mux_dataout, l2_w3_n23_mux_dataout, l2_w3_n22_mux_dataout, l2_w3_n21_mux_dataout, l2_w3_n20_mux_dataout, l2_w3_n19_mux_dataout, l2_w3_n18_mux_dataout, l2_w3_n17_mux_dataout, l2_w3_n16_mux_dataout, l2_w3_n15_mux_dataout, l2_w3_n14_mux_dataout, l2_w3_n13_mux_dataout, l2_w3_n12_mux_dataout, l2_w3_n11_mux_dataout, l2_w3_n10_mux_dataout, l2_w3_n9_mux_dataout, l2_w3_n8_mux_dataout, l2_w3_n7_mux_dataout, l2_w3_n6_mux_dataout, l2_w3_n5_mux_dataout, l2_w3_n4_mux_dataout, l2_w3_n3_mux_dataout, l2_w3_n2_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n63_mux_dataout, l2_w2_n62_mux_dataout, l2_w2_n61_mux_dataout, l2_w2_n60_mux_dataout, l2_w2_n59_mux_dataout, l2_w2_n58_mux_dataout, l2_w2_n57_mux_dataout, l2_w2_n56_mux_dataout, l2_w2_n55_mux_dataout, l2_w2_n54_mux_dataout, l2_w2_n53_mux_dataout, l2_w2_n52_mux_dataout, l2_w2_n51_mux_dataout, l2_w2_n50_mux_dataout, l2_w2_n49_mux_dataout, l2_w2_n48_mux_dataout, l2_w2_n47_mux_dataout, l2_w2_n46_mux_dataout, l2_w2_n45_mux_dataout, l2_w2_n44_mux_dataout, l2_w2_n43_mux_dataout, l2_w2_n42_mux_dataout, l2_w2_n41_mux_dataout, l2_w2_n40_mux_dataout, l2_w2_n39_mux_dataout, l2_w2_n38_mux_dataout, l2_w2_n37_mux_dataout, l2_w2_n36_mux_dataout, l2_w2_n35_mux_dataout, l2_w2_n34_mux_dataout, l2_w2_n33_mux_dataout, l2_w2_n32_mux_dataout, l2_w2_n31_mux_dataout, l2_w2_n30_mux_dataout, l2_w2_n29_mux_dataout, l2_w2_n28_mux_dataout, l2_w2_n27_mux_dataout, l2_w2_n26_mux_dataout, l2_w2_n25_mux_dataout, l2_w2_n24_mux_dataout, l2_w2_n23_mux_dataout, l2_w2_n22_mux_dataout, l2_w2_n21_mux_dataout, l2_w2_n20_mux_dataout, l2_w2_n19_mux_dataout, l2_w2_n18_mux_dataout, l2_w2_n17_mux_dataout, l2_w2_n16_mux_dataout, l2_w2_n15_mux_dataout, l2_w2_n14_mux_dataout, l2_w2_n13_mux_dataout, l2_w2_n12_mux_dataout, l2_w2_n11_mux_dataout, l2_w2_n10_mux_dataout, l2_w2_n9_mux_dataout, l2_w2_n8_mux_dataout, l2_w2_n7_mux_dataout, l2_w2_n6_mux_dataout, l2_w2_n5_mux_dataout, l2_w2_n4_mux_dataout, l2_w2_n3_mux_dataout, l2_w2_n2_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n63_mux_dataout, l2_w1_n62_mux_dataout, l2_w1_n61_mux_dataout, l2_w1_n60_mux_dataout, l2_w1_n59_mux_dataout, l2_w1_n58_mux_dataout, l2_w1_n57_mux_dataout, l2_w1_n56_mux_dataout, l2_w1_n55_mux_dataout, l2_w1_n54_mux_dataout, l2_w1_n53_mux_dataout, l2_w1_n52_mux_dataout, l2_w1_n51_mux_dataout, l2_w1_n50_mux_dataout, l2_w1_n49_mux_dataout, l2_w1_n48_mux_dataout, l2_w1_n47_mux_dataout, l2_w1_n46_mux_dataout, l2_w1_n45_mux_dataout, l2_w1_n44_mux_dataout, l2_w1_n43_mux_dataout, l2_w1_n42_mux_dataout, l2_w1_n41_mux_dataout, l2_w1_n40_mux_dataout, l2_w1_n39_mux_dataout, l2_w1_n38_mux_dataout, l2_w1_n37_mux_dataout, l2_w1_n36_mux_dataout, l2_w1_n35_mux_dataout, l2_w1_n34_mux_dataout, l2_w1_n33_mux_dataout, l2_w1_n32_mux_dataout, l2_w1_n31_mux_dataout, l2_w1_n30_mux_dataout, l2_w1_n29_mux_dataout, l2_w1_n28_mux_dataout, l2_w1_n27_mux_dataout, l2_w1_n26_mux_dataout, l2_w1_n25_mux_dataout, l2_w1_n24_mux_dataout, l2_w1_n23_mux_dataout, l2_w1_n22_mux_dataout, l2_w1_n21_mux_dataout, l2_w1_n20_mux_dataout, l2_w1_n19_mux_dataout, l2_w1_n18_mux_dataout, l2_w1_n17_mux_dataout, l2_w1_n16_mux_dataout, l2_w1_n15_mux_dataout, l2_w1_n14_mux_dataout, l2_w1_n13_mux_dataout, l2_w1_n12_mux_dataout, l2_w1_n11_mux_dataout, l2_w1_n10_mux_dataout, l2_w1_n9_mux_dataout, l2_w1_n8_mux_dataout, l2_w1_n7_mux_dataout, l2_w1_n6_mux_dataout, l2_w1_n5_mux_dataout, l2_w1_n4_mux_dataout, l2_w1_n3_mux_dataout, l2_w1_n2_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n63_mux_dataout, l2_w0_n62_mux_dataout, l2_w0_n61_mux_dataout, l2_w0_n60_mux_dataout, l2_w0_n59_mux_dataout, l2_w0_n58_mux_dataout, l2_w0_n57_mux_dataout, l2_w0_n56_mux_dataout, l2_w0_n55_mux_dataout, l2_w0_n54_mux_dataout, l2_w0_n53_mux_dataout, l2_w0_n52_mux_dataout, l2_w0_n51_mux_dataout, l2_w0_n50_mux_dataout, l2_w0_n49_mux_dataout, l2_w0_n48_mux_dataout, l2_w0_n47_mux_dataout, l2_w0_n46_mux_dataout, l2_w0_n45_mux_dataout, l2_w0_n44_mux_dataout, l2_w0_n43_mux_dataout, l2_w0_n42_mux_dataout, l2_w0_n41_mux_dataout, l2_w0_n40_mux_dataout, l2_w0_n39_mux_dataout, l2_w0_n38_mux_dataout, l2_w0_n37_mux_dataout, l2_w0_n36_mux_dataout, l2_w0_n35_mux_dataout, l2_w0_n34_mux_dataout, l2_w0_n33_mux_dataout, l2_w0_n32_mux_dataout, l2_w0_n31_mux_dataout, l2_w0_n30_mux_dataout, l2_w0_n29_mux_dataout, l2_w0_n28_mux_dataout, l2_w0_n27_mux_dataout, l2_w0_n26_mux_dataout, l2_w0_n25_mux_dataout, l2_w0_n24_mux_dataout, l2_w0_n23_mux_dataout, l2_w0_n22_mux_dataout, l2_w0_n21_mux_dataout, l2_w0_n20_mux_dataout, l2_w0_n19_mux_dataout, l2_w0_n18_mux_dataout, l2_w0_n17_mux_dataout, l2_w0_n16_mux_dataout, l2_w0_n15_mux_dataout, l2_w0_n14_mux_dataout, l2_w0_n13_mux_dataout, l2_w0_n12_mux_dataout, l2_w0_n11_mux_dataout, l2_w0_n10_mux_dataout, l2_w0_n9_mux_dataout, l2_w0_n8_mux_dataout, l2_w0_n7_mux_dataout, l2_w0_n6_mux_dataout, l2_w0_n5_mux_dataout, l2_w0_n4_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n127_mux_dataout, l1_w7_n126_mux_dataout, l1_w7_n125_mux_dataout, l1_w7_n124_mux_dataout, l1_w7_n123_mux_dataout, l1_w7_n122_mux_dataout, l1_w7_n121_mux_dataout, l1_w7_n120_mux_dataout, l1_w7_n119_mux_dataout, l1_w7_n118_mux_dataout, l1_w7_n117_mux_dataout, l1_w7_n116_mux_dataout, l1_w7_n115_mux_dataout, l1_w7_n114_mux_dataout, l1_w7_n113_mux_dataout, l1_w7_n112_mux_dataout, l1_w7_n111_mux_dataout, l1_w7_n110_mux_dataout, l1_w7_n109_mux_dataout, l1_w7_n108_mux_dataout, l1_w7_n107_mux_dataout, l1_w7_n106_mux_dataout, l1_w7_n105_mux_dataout, l1_w7_n104_mux_dataout, l1_w7_n103_mux_dataout, l1_w7_n102_mux_dataout, l1_w7_n101_mux_dataout, l1_w7_n100_mux_dataout, l1_w7_n99_mux_dataout, l1_w7_n98_mux_dataout, l1_w7_n97_mux_dataout, l1_w7_n96_mux_dataout, l1_w7_n95_mux_dataout, l1_w7_n94_mux_dataout, l1_w7_n93_mux_dataout, l1_w7_n92_mux_dataout, l1_w7_n91_mux_dataout, l1_w7_n90_mux_dataout, l1_w7_n89_mux_dataout, l1_w7_n88_mux_dataout, l1_w7_n87_mux_dataout, l1_w7_n86_mux_dataout, l1_w7_n85_mux_dataout, l1_w7_n84_mux_dataout, l1_w7_n83_mux_dataout, l1_w7_n82_mux_dataout, l1_w7_n81_mux_dataout, l1_w7_n80_mux_dataout, l1_w7_n79_mux_dataout, l1_w7_n78_mux_dataout, l1_w7_n77_mux_dataout, l1_w7_n76_mux_dataout, l1_w7_n75_mux_dataout, l1_w7_n74_mux_dataout, l1_w7_n73_mux_dataout, l1_w7_n72_mux_dataout, l1_w7_n71_mux_dataout, l1_w7_n70_mux_dataout, l1_w7_n69_mux_dataout, l1_w7_n68_mux_dataout, l1_w7_n67_mux_dataout, l1_w7_n66_mux_dataout, l1_w7_n65_mux_dataout, l1_w7_n64_mux_dataout, l1_w7_n63_mux_dataout, l1_w7_n62_mux_dataout, l1_w7_n61_mux_dataout, l1_w7_n60_mux_dataout, l1_w7_n59_mux_dataout, l1_w7_n58_mux_dataout, l1_w7_n57_mux_dataout, l1_w7_n56_mux_dataout, l1_w7_n55_mux_dataout, l1_w7_n54_mux_dataout, l1_w7_n53_mux_dataout, l1_w7_n52_mux_dataout, l1_w7_n51_mux_dataout, l1_w7_n50_mux_dataout, l1_w7_n49_mux_dataout, l1_w7_n48_mux_dataout, l1_w7_n47_mux_dataout, l1_w7_n46_mux_dataout, l1_w7_n45_mux_dataout, l1_w7_n44_mux_dataout, l1_w7_n43_mux_dataout, l1_w7_n42_mux_dataout, l1_w7_n41_mux_dataout, l1_w7_n40_mux_dataout, l1_w7_n39_mux_dataout, l1_w7_n38_mux_dataout, l1_w7_n37_mux_dataout, l1_w7_n36_mux_dataout, l1_w7_n35_mux_dataout, l1_w7_n34_mux_dataout, l1_w7_n33_mux_dataout, l1_w7_n32_mux_dataout, l1_w7_n31_mux_dataout, l1_w7_n30_mux_dataout, l1_w7_n29_mux_dataout, l1_w7_n28_mux_dataout, l1_w7_n27_mux_dataout, l1_w7_n26_mux_dataout, l1_w7_n25_mux_dataout, l1_w7_n24_mux_dataout, l1_w7_n23_mux_dataout, l1_w7_n22_mux_dataout, l1_w7_n21_mux_dataout, l1_w7_n20_mux_dataout, l1_w7_n19_mux_dataout, l1_w7_n18_mux_dataout, l1_w7_n17_mux_dataout, l1_w7_n16_mux_dataout, l1_w7_n15_mux_dataout, l1_w7_n14_mux_dataout, l1_w7_n13_mux_dataout, l1_w7_n12_mux_dataout, l1_w7_n11_mux_dataout, l1_w7_n10_mux_dataout, l1_w7_n9_mux_dataout, l1_w7_n8_mux_dataout, l1_w7_n7_mux_dataout, l1_w7_n6_mux_dataout, l1_w7_n5_mux_dataout, l1_w7_n4_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n127_mux_dataout, l1_w6_n126_mux_dataout, l1_w6_n125_mux_dataout, l1_w6_n124_mux_dataout, l1_w6_n123_mux_dataout, l1_w6_n122_mux_dataout, l1_w6_n121_mux_dataout, l1_w6_n120_mux_dataout, l1_w6_n119_mux_dataout, l1_w6_n118_mux_dataout, l1_w6_n117_mux_dataout, l1_w6_n116_mux_dataout, l1_w6_n115_mux_dataout, l1_w6_n114_mux_dataout, l1_w6_n113_mux_dataout, l1_w6_n112_mux_dataout, l1_w6_n111_mux_dataout, l1_w6_n110_mux_dataout, l1_w6_n109_mux_dataout, l1_w6_n108_mux_dataout, l1_w6_n107_mux_dataout, l1_w6_n106_mux_dataout, l1_w6_n105_mux_dataout, l1_w6_n104_mux_dataout, l1_w6_n103_mux_dataout, l1_w6_n102_mux_dataout, l1_w6_n101_mux_dataout, l1_w6_n100_mux_dataout, l1_w6_n99_mux_dataout, l1_w6_n98_mux_dataout, l1_w6_n97_mux_dataout, l1_w6_n96_mux_dataout, l1_w6_n95_mux_dataout, l1_w6_n94_mux_dataout, l1_w6_n93_mux_dataout, l1_w6_n92_mux_dataout, l1_w6_n91_mux_dataout, l1_w6_n90_mux_dataout, l1_w6_n89_mux_dataout, l1_w6_n88_mux_dataout, l1_w6_n87_mux_dataout, l1_w6_n86_mux_dataout, l1_w6_n85_mux_dataout, l1_w6_n84_mux_dataout, l1_w6_n83_mux_dataout, l1_w6_n82_mux_dataout, l1_w6_n81_mux_dataout, l1_w6_n80_mux_dataout, l1_w6_n79_mux_dataout, l1_w6_n78_mux_dataout, l1_w6_n77_mux_dataout, l1_w6_n76_mux_dataout, l1_w6_n75_mux_dataout, l1_w6_n74_mux_dataout, l1_w6_n73_mux_dataout, l1_w6_n72_mux_dataout, l1_w6_n71_mux_dataout, l1_w6_n70_mux_dataout, l1_w6_n69_mux_dataout, l1_w6_n68_mux_dataout, l1_w6_n67_mux_dataout, l1_w6_n66_mux_dataout, l1_w6_n65_mux_dataout, l1_w6_n64_mux_dataout, l1_w6_n63_mux_dataout, l1_w6_n62_mux_dataout, l1_w6_n61_mux_dataout, l1_w6_n60_mux_dataout, l1_w6_n59_mux_dataout, l1_w6_n58_mux_dataout, l1_w6_n57_mux_dataout, l1_w6_n56_mux_dataout, l1_w6_n55_mux_dataout, l1_w6_n54_mux_dataout, l1_w6_n53_mux_dataout, l1_w6_n52_mux_dataout, l1_w6_n51_mux_dataout, l1_w6_n50_mux_dataout, l1_w6_n49_mux_dataout, l1_w6_n48_mux_dataout, l1_w6_n47_mux_dataout, l1_w6_n46_mux_dataout, l1_w6_n45_mux_dataout, l1_w6_n44_mux_dataout, l1_w6_n43_mux_dataout, l1_w6_n42_mux_dataout, l1_w6_n41_mux_dataout, l1_w6_n40_mux_dataout, l1_w6_n39_mux_dataout, l1_w6_n38_mux_dataout, l1_w6_n37_mux_dataout, l1_w6_n36_mux_dataout, l1_w6_n35_mux_dataout, l1_w6_n34_mux_dataout, l1_w6_n33_mux_dataout, l1_w6_n32_mux_dataout, l1_w6_n31_mux_dataout, l1_w6_n30_mux_dataout, l1_w6_n29_mux_dataout, l1_w6_n28_mux_dataout, l1_w6_n27_mux_dataout, l1_w6_n26_mux_dataout, l1_w6_n25_mux_dataout, l1_w6_n24_mux_dataout, l1_w6_n23_mux_dataout, l1_w6_n22_mux_dataout, l1_w6_n21_mux_dataout, l1_w6_n20_mux_dataout, l1_w6_n19_mux_dataout, l1_w6_n18_mux_dataout, l1_w6_n17_mux_dataout, l1_w6_n16_mux_dataout, l1_w6_n15_mux_dataout, l1_w6_n14_mux_dataout, l1_w6_n13_mux_dataout, l1_w6_n12_mux_dataout, l1_w6_n11_mux_dataout, l1_w6_n10_mux_dataout, l1_w6_n9_mux_dataout, l1_w6_n8_mux_dataout, l1_w6_n7_mux_dataout, l1_w6_n6_mux_dataout, l1_w6_n5_mux_dataout, l1_w6_n4_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n127_mux_dataout, l1_w5_n126_mux_dataout, l1_w5_n125_mux_dataout, l1_w5_n124_mux_dataout, l1_w5_n123_mux_dataout, l1_w5_n122_mux_dataout, l1_w5_n121_mux_dataout, l1_w5_n120_mux_dataout, l1_w5_n119_mux_dataout, l1_w5_n118_mux_dataout, l1_w5_n117_mux_dataout, l1_w5_n116_mux_dataout, l1_w5_n115_mux_dataout, l1_w5_n114_mux_dataout, l1_w5_n113_mux_dataout, l1_w5_n112_mux_dataout, l1_w5_n111_mux_dataout, l1_w5_n110_mux_dataout, l1_w5_n109_mux_dataout, l1_w5_n108_mux_dataout, l1_w5_n107_mux_dataout, l1_w5_n106_mux_dataout, l1_w5_n105_mux_dataout, l1_w5_n104_mux_dataout, l1_w5_n103_mux_dataout, l1_w5_n102_mux_dataout, l1_w5_n101_mux_dataout, l1_w5_n100_mux_dataout, l1_w5_n99_mux_dataout, l1_w5_n98_mux_dataout, l1_w5_n97_mux_dataout, l1_w5_n96_mux_dataout, l1_w5_n95_mux_dataout, l1_w5_n94_mux_dataout, l1_w5_n93_mux_dataout, l1_w5_n92_mux_dataout, l1_w5_n91_mux_dataout, l1_w5_n90_mux_dataout, l1_w5_n89_mux_dataout, l1_w5_n88_mux_dataout, l1_w5_n87_mux_dataout, l1_w5_n86_mux_dataout, l1_w5_n85_mux_dataout, l1_w5_n84_mux_dataout, l1_w5_n83_mux_dataout, l1_w5_n82_mux_dataout, l1_w5_n81_mux_dataout, l1_w5_n80_mux_dataout, l1_w5_n79_mux_dataout, l1_w5_n78_mux_dataout, l1_w5_n77_mux_dataout, l1_w5_n76_mux_dataout, l1_w5_n75_mux_dataout, l1_w5_n74_mux_dataout, l1_w5_n73_mux_dataout, l1_w5_n72_mux_dataout, l1_w5_n71_mux_dataout, l1_w5_n70_mux_dataout, l1_w5_n69_mux_dataout, l1_w5_n68_mux_dataout, l1_w5_n67_mux_dataout, l1_w5_n66_mux_dataout, l1_w5_n65_mux_dataout, l1_w5_n64_mux_dataout, l1_w5_n63_mux_dataout, l1_w5_n62_mux_dataout, l1_w5_n61_mux_dataout, l1_w5_n60_mux_dataout, l1_w5_n59_mux_dataout, l1_w5_n58_mux_dataout, l1_w5_n57_mux_dataout, l1_w5_n56_mux_dataout, l1_w5_n55_mux_dataout, l1_w5_n54_mux_dataout, l1_w5_n53_mux_dataout, l1_w5_n52_mux_dataout, l1_w5_n51_mux_dataout, l1_w5_n50_mux_dataout, l1_w5_n49_mux_dataout, l1_w5_n48_mux_dataout, l1_w5_n47_mux_dataout, l1_w5_n46_mux_dataout, l1_w5_n45_mux_dataout, l1_w5_n44_mux_dataout, l1_w5_n43_mux_dataout, l1_w5_n42_mux_dataout, l1_w5_n41_mux_dataout, l1_w5_n40_mux_dataout, l1_w5_n39_mux_dataout, l1_w5_n38_mux_dataout, l1_w5_n37_mux_dataout, l1_w5_n36_mux_dataout, l1_w5_n35_mux_dataout, l1_w5_n34_mux_dataout, l1_w5_n33_mux_dataout, l1_w5_n32_mux_dataout, l1_w5_n31_mux_dataout, l1_w5_n30_mux_dataout, l1_w5_n29_mux_dataout, l1_w5_n28_mux_dataout, l1_w5_n27_mux_dataout, l1_w5_n26_mux_dataout, l1_w5_n25_mux_dataout, l1_w5_n24_mux_dataout, l1_w5_n23_mux_dataout, l1_w5_n22_mux_dataout, l1_w5_n21_mux_dataout, l1_w5_n20_mux_dataout, l1_w5_n19_mux_dataout, l1_w5_n18_mux_dataout, l1_w5_n17_mux_dataout, l1_w5_n16_mux_dataout, l1_w5_n15_mux_dataout, l1_w5_n14_mux_dataout, l1_w5_n13_mux_dataout, l1_w5_n12_mux_dataout, l1_w5_n11_mux_dataout, l1_w5_n10_mux_dataout, l1_w5_n9_mux_dataout, l1_w5_n8_mux_dataout, l1_w5_n7_mux_dataout, l1_w5_n6_mux_dataout, l1_w5_n5_mux_dataout, l1_w5_n4_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n127_mux_dataout, l1_w4_n126_mux_dataout, l1_w4_n125_mux_dataout, l1_w4_n124_mux_dataout, l1_w4_n123_mux_dataout, l1_w4_n122_mux_dataout, l1_w4_n121_mux_dataout, l1_w4_n120_mux_dataout, l1_w4_n119_mux_dataout, l1_w4_n118_mux_dataout, l1_w4_n117_mux_dataout, l1_w4_n116_mux_dataout, l1_w4_n115_mux_dataout, l1_w4_n114_mux_dataout, l1_w4_n113_mux_dataout, l1_w4_n112_mux_dataout, l1_w4_n111_mux_dataout, l1_w4_n110_mux_dataout, l1_w4_n109_mux_dataout, l1_w4_n108_mux_dataout, l1_w4_n107_mux_dataout, l1_w4_n106_mux_dataout, l1_w4_n105_mux_dataout, l1_w4_n104_mux_dataout, l1_w4_n103_mux_dataout, l1_w4_n102_mux_dataout, l1_w4_n101_mux_dataout, l1_w4_n100_mux_dataout, l1_w4_n99_mux_dataout, l1_w4_n98_mux_dataout, l1_w4_n97_mux_dataout, l1_w4_n96_mux_dataout, l1_w4_n95_mux_dataout, l1_w4_n94_mux_dataout, l1_w4_n93_mux_dataout, l1_w4_n92_mux_dataout, l1_w4_n91_mux_dataout, l1_w4_n90_mux_dataout, l1_w4_n89_mux_dataout, l1_w4_n88_mux_dataout, l1_w4_n87_mux_dataout, l1_w4_n86_mux_dataout, l1_w4_n85_mux_dataout, l1_w4_n84_mux_dataout, l1_w4_n83_mux_dataout, l1_w4_n82_mux_dataout, l1_w4_n81_mux_dataout, l1_w4_n80_mux_dataout, l1_w4_n79_mux_dataout, l1_w4_n78_mux_dataout, l1_w4_n77_mux_dataout, l1_w4_n76_mux_dataout, l1_w4_n75_mux_dataout, l1_w4_n74_mux_dataout, l1_w4_n73_mux_dataout, l1_w4_n72_mux_dataout, l1_w4_n71_mux_dataout, l1_w4_n70_mux_dataout, l1_w4_n69_mux_dataout, l1_w4_n68_mux_dataout, l1_w4_n67_mux_dataout, l1_w4_n66_mux_dataout, l1_w4_n65_mux_dataout, l1_w4_n64_mux_dataout, l1_w4_n63_mux_dataout, l1_w4_n62_mux_dataout, l1_w4_n61_mux_dataout, l1_w4_n60_mux_dataout, l1_w4_n59_mux_dataout, l1_w4_n58_mux_dataout, l1_w4_n57_mux_dataout, l1_w4_n56_mux_dataout, l1_w4_n55_mux_dataout, l1_w4_n54_mux_dataout, l1_w4_n53_mux_dataout, l1_w4_n52_mux_dataout, l1_w4_n51_mux_dataout, l1_w4_n50_mux_dataout, l1_w4_n49_mux_dataout, l1_w4_n48_mux_dataout, l1_w4_n47_mux_dataout, l1_w4_n46_mux_dataout, l1_w4_n45_mux_dataout, l1_w4_n44_mux_dataout, l1_w4_n43_mux_dataout, l1_w4_n42_mux_dataout, l1_w4_n41_mux_dataout, l1_w4_n40_mux_dataout, l1_w4_n39_mux_dataout, l1_w4_n38_mux_dataout, l1_w4_n37_mux_dataout, l1_w4_n36_mux_dataout, l1_w4_n35_mux_dataout, l1_w4_n34_mux_dataout, l1_w4_n33_mux_dataout, l1_w4_n32_mux_dataout, l1_w4_n31_mux_dataout, l1_w4_n30_mux_dataout, l1_w4_n29_mux_dataout, l1_w4_n28_mux_dataout, l1_w4_n27_mux_dataout, l1_w4_n26_mux_dataout, l1_w4_n25_mux_dataout, l1_w4_n24_mux_dataout, l1_w4_n23_mux_dataout, l1_w4_n22_mux_dataout, l1_w4_n21_mux_dataout, l1_w4_n20_mux_dataout, l1_w4_n19_mux_dataout, l1_w4_n18_mux_dataout, l1_w4_n17_mux_dataout, l1_w4_n16_mux_dataout, l1_w4_n15_mux_dataout, l1_w4_n14_mux_dataout, l1_w4_n13_mux_dataout, l1_w4_n12_mux_dataout, l1_w4_n11_mux_dataout, l1_w4_n10_mux_dataout, l1_w4_n9_mux_dataout, l1_w4_n8_mux_dataout, l1_w4_n7_mux_dataout, l1_w4_n6_mux_dataout, l1_w4_n5_mux_dataout, l1_w4_n4_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n127_mux_dataout, l1_w3_n126_mux_dataout, l1_w3_n125_mux_dataout, l1_w3_n124_mux_dataout, l1_w3_n123_mux_dataout, l1_w3_n122_mux_dataout, l1_w3_n121_mux_dataout, l1_w3_n120_mux_dataout, l1_w3_n119_mux_dataout, l1_w3_n118_mux_dataout, l1_w3_n117_mux_dataout, l1_w3_n116_mux_dataout, l1_w3_n115_mux_dataout, l1_w3_n114_mux_dataout, l1_w3_n113_mux_dataout, l1_w3_n112_mux_dataout, l1_w3_n111_mux_dataout, l1_w3_n110_mux_dataout, l1_w3_n109_mux_dataout, l1_w3_n108_mux_dataout, l1_w3_n107_mux_dataout, l1_w3_n106_mux_dataout, l1_w3_n105_mux_dataout, l1_w3_n104_mux_dataout, l1_w3_n103_mux_dataout, l1_w3_n102_mux_dataout, l1_w3_n101_mux_dataout, l1_w3_n100_mux_dataout, l1_w3_n99_mux_dataout, l1_w3_n98_mux_dataout, l1_w3_n97_mux_dataout, l1_w3_n96_mux_dataout, l1_w3_n95_mux_dataout, l1_w3_n94_mux_dataout, l1_w3_n93_mux_dataout, l1_w3_n92_mux_dataout, l1_w3_n91_mux_dataout, l1_w3_n90_mux_dataout, l1_w3_n89_mux_dataout, l1_w3_n88_mux_dataout, l1_w3_n87_mux_dataout, l1_w3_n86_mux_dataout, l1_w3_n85_mux_dataout, l1_w3_n84_mux_dataout, l1_w3_n83_mux_dataout, l1_w3_n82_mux_dataout, l1_w3_n81_mux_dataout, l1_w3_n80_mux_dataout, l1_w3_n79_mux_dataout, l1_w3_n78_mux_dataout, l1_w3_n77_mux_dataout, l1_w3_n76_mux_dataout, l1_w3_n75_mux_dataout, l1_w3_n74_mux_dataout, l1_w3_n73_mux_dataout, l1_w3_n72_mux_dataout, l1_w3_n71_mux_dataout, l1_w3_n70_mux_dataout, l1_w3_n69_mux_dataout, l1_w3_n68_mux_dataout, l1_w3_n67_mux_dataout, l1_w3_n66_mux_dataout, l1_w3_n65_mux_dataout, l1_w3_n64_mux_dataout, l1_w3_n63_mux_dataout, l1_w3_n62_mux_dataout, l1_w3_n61_mux_dataout, l1_w3_n60_mux_dataout, l1_w3_n59_mux_dataout, l1_w3_n58_mux_dataout, l1_w3_n57_mux_dataout, l1_w3_n56_mux_dataout, l1_w3_n55_mux_dataout, l1_w3_n54_mux_dataout, l1_w3_n53_mux_dataout, l1_w3_n52_mux_dataout, l1_w3_n51_mux_dataout, l1_w3_n50_mux_dataout, l1_w3_n49_mux_dataout, l1_w3_n48_mux_dataout, l1_w3_n47_mux_dataout, l1_w3_n46_mux_dataout, l1_w3_n45_mux_dataout, l1_w3_n44_mux_dataout, l1_w3_n43_mux_dataout, l1_w3_n42_mux_dataout, l1_w3_n41_mux_dataout, l1_w3_n40_mux_dataout, l1_w3_n39_mux_dataout, l1_w3_n38_mux_dataout, l1_w3_n37_mux_dataout, l1_w3_n36_mux_dataout, l1_w3_n35_mux_dataout, l1_w3_n34_mux_dataout, l1_w3_n33_mux_dataout, l1_w3_n32_mux_dataout, l1_w3_n31_mux_dataout, l1_w3_n30_mux_dataout, l1_w3_n29_mux_dataout, l1_w3_n28_mux_dataout, l1_w3_n27_mux_dataout, l1_w3_n26_mux_dataout, l1_w3_n25_mux_dataout, l1_w3_n24_mux_dataout, l1_w3_n23_mux_dataout, l1_w3_n22_mux_dataout, l1_w3_n21_mux_dataout, l1_w3_n20_mux_dataout, l1_w3_n19_mux_dataout, l1_w3_n18_mux_dataout, l1_w3_n17_mux_dataout, l1_w3_n16_mux_dataout, l1_w3_n15_mux_dataout, l1_w3_n14_mux_dataout, l1_w3_n13_mux_dataout, l1_w3_n12_mux_dataout, l1_w3_n11_mux_dataout, l1_w3_n10_mux_dataout, l1_w3_n9_mux_dataout, l1_w3_n8_mux_dataout, l1_w3_n7_mux_dataout, l1_w3_n6_mux_dataout, l1_w3_n5_mux_dataout, l1_w3_n4_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n127_mux_dataout, l1_w2_n126_mux_dataout, l1_w2_n125_mux_dataout, l1_w2_n124_mux_dataout, l1_w2_n123_mux_dataout, l1_w2_n122_mux_dataout, l1_w2_n121_mux_dataout, l1_w2_n120_mux_dataout, l1_w2_n119_mux_dataout, l1_w2_n118_mux_dataout, l1_w2_n117_mux_dataout, l1_w2_n116_mux_dataout, l1_w2_n115_mux_dataout, l1_w2_n114_mux_dataout, l1_w2_n113_mux_dataout, l1_w2_n112_mux_dataout, l1_w2_n111_mux_dataout, l1_w2_n110_mux_dataout, l1_w2_n109_mux_dataout, l1_w2_n108_mux_dataout, l1_w2_n107_mux_dataout, l1_w2_n106_mux_dataout, l1_w2_n105_mux_dataout, l1_w2_n104_mux_dataout, l1_w2_n103_mux_dataout, l1_w2_n102_mux_dataout, l1_w2_n101_mux_dataout, l1_w2_n100_mux_dataout, l1_w2_n99_mux_dataout, l1_w2_n98_mux_dataout, l1_w2_n97_mux_dataout, l1_w2_n96_mux_dataout, l1_w2_n95_mux_dataout, l1_w2_n94_mux_dataout, l1_w2_n93_mux_dataout, l1_w2_n92_mux_dataout, l1_w2_n91_mux_dataout, l1_w2_n90_mux_dataout, l1_w2_n89_mux_dataout, l1_w2_n88_mux_dataout, l1_w2_n87_mux_dataout, l1_w2_n86_mux_dataout, l1_w2_n85_mux_dataout, l1_w2_n84_mux_dataout, l1_w2_n83_mux_dataout, l1_w2_n82_mux_dataout, l1_w2_n81_mux_dataout, l1_w2_n80_mux_dataout, l1_w2_n79_mux_dataout, l1_w2_n78_mux_dataout, l1_w2_n77_mux_dataout, l1_w2_n76_mux_dataout, l1_w2_n75_mux_dataout, l1_w2_n74_mux_dataout, l1_w2_n73_mux_dataout, l1_w2_n72_mux_dataout, l1_w2_n71_mux_dataout, l1_w2_n70_mux_dataout, l1_w2_n69_mux_dataout, l1_w2_n68_mux_dataout, l1_w2_n67_mux_dataout, l1_w2_n66_mux_dataout, l1_w2_n65_mux_dataout, l1_w2_n64_mux_dataout, l1_w2_n63_mux_dataout, l1_w2_n62_mux_dataout, l1_w2_n61_mux_dataout, l1_w2_n60_mux_dataout, l1_w2_n59_mux_dataout, l1_w2_n58_mux_dataout, l1_w2_n57_mux_dataout, l1_w2_n56_mux_dataout, l1_w2_n55_mux_dataout, l1_w2_n54_mux_dataout, l1_w2_n53_mux_dataout, l1_w2_n52_mux_dataout, l1_w2_n51_mux_dataout, l1_w2_n50_mux_dataout, l1_w2_n49_mux_dataout, l1_w2_n48_mux_dataout, l1_w2_n47_mux_dataout, l1_w2_n46_mux_dataout, l1_w2_n45_mux_dataout, l1_w2_n44_mux_dataout, l1_w2_n43_mux_dataout, l1_w2_n42_mux_dataout, l1_w2_n41_mux_dataout, l1_w2_n40_mux_dataout, l1_w2_n39_mux_dataout, l1_w2_n38_mux_dataout, l1_w2_n37_mux_dataout, l1_w2_n36_mux_dataout, l1_w2_n35_mux_dataout, l1_w2_n34_mux_dataout, l1_w2_n33_mux_dataout, l1_w2_n32_mux_dataout, l1_w2_n31_mux_dataout, l1_w2_n30_mux_dataout, l1_w2_n29_mux_dataout, l1_w2_n28_mux_dataout, l1_w2_n27_mux_dataout, l1_w2_n26_mux_dataout, l1_w2_n25_mux_dataout, l1_w2_n24_mux_dataout, l1_w2_n23_mux_dataout, l1_w2_n22_mux_dataout, l1_w2_n21_mux_dataout, l1_w2_n20_mux_dataout, l1_w2_n19_mux_dataout, l1_w2_n18_mux_dataout, l1_w2_n17_mux_dataout, l1_w2_n16_mux_dataout, l1_w2_n15_mux_dataout, l1_w2_n14_mux_dataout, l1_w2_n13_mux_dataout, l1_w2_n12_mux_dataout, l1_w2_n11_mux_dataout, l1_w2_n10_mux_dataout, l1_w2_n9_mux_dataout, l1_w2_n8_mux_dataout, l1_w2_n7_mux_dataout, l1_w2_n6_mux_dataout, l1_w2_n5_mux_dataout, l1_w2_n4_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n127_mux_dataout, l1_w1_n126_mux_dataout, l1_w1_n125_mux_dataout, l1_w1_n124_mux_dataout, l1_w1_n123_mux_dataout, l1_w1_n122_mux_dataout, l1_w1_n121_mux_dataout, l1_w1_n120_mux_dataout, l1_w1_n119_mux_dataout, l1_w1_n118_mux_dataout, l1_w1_n117_mux_dataout, l1_w1_n116_mux_dataout, l1_w1_n115_mux_dataout, l1_w1_n114_mux_dataout, l1_w1_n113_mux_dataout, l1_w1_n112_mux_dataout, l1_w1_n111_mux_dataout, l1_w1_n110_mux_dataout, l1_w1_n109_mux_dataout, l1_w1_n108_mux_dataout, l1_w1_n107_mux_dataout, l1_w1_n106_mux_dataout, l1_w1_n105_mux_dataout, l1_w1_n104_mux_dataout, l1_w1_n103_mux_dataout, l1_w1_n102_mux_dataout, l1_w1_n101_mux_dataout, l1_w1_n100_mux_dataout, l1_w1_n99_mux_dataout, l1_w1_n98_mux_dataout, l1_w1_n97_mux_dataout, l1_w1_n96_mux_dataout, l1_w1_n95_mux_dataout, l1_w1_n94_mux_dataout, l1_w1_n93_mux_dataout, l1_w1_n92_mux_dataout, l1_w1_n91_mux_dataout, l1_w1_n90_mux_dataout, l1_w1_n89_mux_dataout, l1_w1_n88_mux_dataout, l1_w1_n87_mux_dataout, l1_w1_n86_mux_dataout, l1_w1_n85_mux_dataout, l1_w1_n84_mux_dataout, l1_w1_n83_mux_dataout, l1_w1_n82_mux_dataout, l1_w1_n81_mux_dataout, l1_w1_n80_mux_dataout, l1_w1_n79_mux_dataout, l1_w1_n78_mux_dataout, l1_w1_n77_mux_dataout, l1_w1_n76_mux_dataout, l1_w1_n75_mux_dataout, l1_w1_n74_mux_dataout, l1_w1_n73_mux_dataout, l1_w1_n72_mux_dataout, l1_w1_n71_mux_dataout, l1_w1_n70_mux_dataout, l1_w1_n69_mux_dataout, l1_w1_n68_mux_dataout, l1_w1_n67_mux_dataout, l1_w1_n66_mux_dataout, l1_w1_n65_mux_dataout, l1_w1_n64_mux_dataout, l1_w1_n63_mux_dataout, l1_w1_n62_mux_dataout, l1_w1_n61_mux_dataout, l1_w1_n60_mux_dataout, l1_w1_n59_mux_dataout, l1_w1_n58_mux_dataout, l1_w1_n57_mux_dataout, l1_w1_n56_mux_dataout, l1_w1_n55_mux_dataout, l1_w1_n54_mux_dataout, l1_w1_n53_mux_dataout, l1_w1_n52_mux_dataout, l1_w1_n51_mux_dataout, l1_w1_n50_mux_dataout, l1_w1_n49_mux_dataout, l1_w1_n48_mux_dataout, l1_w1_n47_mux_dataout, l1_w1_n46_mux_dataout, l1_w1_n45_mux_dataout, l1_w1_n44_mux_dataout, l1_w1_n43_mux_dataout, l1_w1_n42_mux_dataout, l1_w1_n41_mux_dataout, l1_w1_n40_mux_dataout, l1_w1_n39_mux_dataout, l1_w1_n38_mux_dataout, l1_w1_n37_mux_dataout, l1_w1_n36_mux_dataout, l1_w1_n35_mux_dataout, l1_w1_n34_mux_dataout, l1_w1_n33_mux_dataout, l1_w1_n32_mux_dataout, l1_w1_n31_mux_dataout, l1_w1_n30_mux_dataout, l1_w1_n29_mux_dataout, l1_w1_n28_mux_dataout, l1_w1_n27_mux_dataout, l1_w1_n26_mux_dataout, l1_w1_n25_mux_dataout, l1_w1_n24_mux_dataout, l1_w1_n23_mux_dataout, l1_w1_n22_mux_dataout, l1_w1_n21_mux_dataout, l1_w1_n20_mux_dataout, l1_w1_n19_mux_dataout, l1_w1_n18_mux_dataout, l1_w1_n17_mux_dataout, l1_w1_n16_mux_dataout, l1_w1_n15_mux_dataout, l1_w1_n14_mux_dataout, l1_w1_n13_mux_dataout, l1_w1_n12_mux_dataout, l1_w1_n11_mux_dataout, l1_w1_n10_mux_dataout, l1_w1_n9_mux_dataout, l1_w1_n8_mux_dataout, l1_w1_n7_mux_dataout, l1_w1_n6_mux_dataout, l1_w1_n5_mux_dataout, l1_w1_n4_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n127_mux_dataout, l1_w0_n126_mux_dataout, l1_w0_n125_mux_dataout, l1_w0_n124_mux_dataout, l1_w0_n123_mux_dataout, l1_w0_n122_mux_dataout, l1_w0_n121_mux_dataout, l1_w0_n120_mux_dataout, l1_w0_n119_mux_dataout, l1_w0_n118_mux_dataout, l1_w0_n117_mux_dataout, l1_w0_n116_mux_dataout, l1_w0_n115_mux_dataout, l1_w0_n114_mux_dataout, l1_w0_n113_mux_dataout, l1_w0_n112_mux_dataout, l1_w0_n111_mux_dataout, l1_w0_n110_mux_dataout, l1_w0_n109_mux_dataout, l1_w0_n108_mux_dataout, l1_w0_n107_mux_dataout, l1_w0_n106_mux_dataout, l1_w0_n105_mux_dataout, l1_w0_n104_mux_dataout, l1_w0_n103_mux_dataout, l1_w0_n102_mux_dataout, l1_w0_n101_mux_dataout, l1_w0_n100_mux_dataout, l1_w0_n99_mux_dataout, l1_w0_n98_mux_dataout, l1_w0_n97_mux_dataout, l1_w0_n96_mux_dataout, l1_w0_n95_mux_dataout, l1_w0_n94_mux_dataout, l1_w0_n93_mux_dataout, l1_w0_n92_mux_dataout, l1_w0_n91_mux_dataout, l1_w0_n90_mux_dataout, l1_w0_n89_mux_dataout, l1_w0_n88_mux_dataout, l1_w0_n87_mux_dataout, l1_w0_n86_mux_dataout, l1_w0_n85_mux_dataout, l1_w0_n84_mux_dataout, l1_w0_n83_mux_dataout, l1_w0_n82_mux_dataout, l1_w0_n81_mux_dataout, l1_w0_n80_mux_dataout, l1_w0_n79_mux_dataout, l1_w0_n78_mux_dataout, l1_w0_n77_mux_dataout, l1_w0_n76_mux_dataout, l1_w0_n75_mux_dataout, l1_w0_n74_mux_dataout, l1_w0_n73_mux_dataout, l1_w0_n72_mux_dataout, l1_w0_n71_mux_dataout, l1_w0_n70_mux_dataout, l1_w0_n69_mux_dataout, l1_w0_n68_mux_dataout, l1_w0_n67_mux_dataout, l1_w0_n66_mux_dataout, l1_w0_n65_mux_dataout, l1_w0_n64_mux_dataout, l1_w0_n63_mux_dataout, l1_w0_n62_mux_dataout, l1_w0_n61_mux_dataout, l1_w0_n60_mux_dataout, l1_w0_n59_mux_dataout, l1_w0_n58_mux_dataout, l1_w0_n57_mux_dataout, l1_w0_n56_mux_dataout, l1_w0_n55_mux_dataout, l1_w0_n54_mux_dataout, l1_w0_n53_mux_dataout, l1_w0_n52_mux_dataout, l1_w0_n51_mux_dataout, l1_w0_n50_mux_dataout, l1_w0_n49_mux_dataout, l1_w0_n48_mux_dataout, l1_w0_n47_mux_dataout, l1_w0_n46_mux_dataout, l1_w0_n45_mux_dataout, l1_w0_n44_mux_dataout, l1_w0_n43_mux_dataout, l1_w0_n42_mux_dataout, l1_w0_n41_mux_dataout, l1_w0_n40_mux_dataout, l1_w0_n39_mux_dataout, l1_w0_n38_mux_dataout, l1_w0_n37_mux_dataout, l1_w0_n36_mux_dataout, l1_w0_n35_mux_dataout, l1_w0_n34_mux_dataout, l1_w0_n33_mux_dataout, l1_w0_n32_mux_dataout, l1_w0_n31_mux_dataout, l1_w0_n30_mux_dataout, l1_w0_n29_mux_dataout, l1_w0_n28_mux_dataout, l1_w0_n27_mux_dataout, l1_w0_n26_mux_dataout, l1_w0_n25_mux_dataout, l1_w0_n24_mux_dataout, l1_w0_n23_mux_dataout, l1_w0_n22_mux_dataout, l1_w0_n21_mux_dataout, l1_w0_n20_mux_dataout, l1_w0_n19_mux_dataout, l1_w0_n18_mux_dataout, l1_w0_n17_mux_dataout, l1_w0_n16_mux_dataout, l1_w0_n15_mux_dataout, l1_w0_n14_mux_dataout, l1_w0_n13_mux_dataout, l1_w0_n12_mux_dataout, l1_w0_n11_mux_dataout, l1_w0_n10_mux_dataout, l1_w0_n9_mux_dataout, l1_w0_n8_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l8_w7_n0_mux_dataout, l8_w6_n0_mux_dataout, l8_w5_n0_mux_dataout, l8_w4_n0_mux_dataout, l8_w3_n0_mux_dataout, l8_w2_n0_mux_dataout, l8_w1_n0_mux_dataout, l8_w0_n0_mux_dataout); + sel_wire[] = ( sel[7..7], B"00000000", sel[6..6], B"00000000", sel[5..5], B"00000000", sel[4..4], B"00000000", sel[3..3], B"00000000", sel[2..2], B"00000000", sel[1..1], B"00000000", sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/mux_dhb.tdf b/proj_quartus/db/mux_dhb.tdf new file mode 100644 index 000000000..fd2694721 --- /dev/null +++ b/proj_quartus/db/mux_dhb.tdf @@ -0,0 +1,280 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=16 LPM_WIDTH=8 LPM_WIDTHS=4 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 40 +SUBDESIGN mux_dhb +( + data[127..0] : input; + result[7..0] : output; + sel[3..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w0_n1_mux_dataout : WIRE; + l1_w0_n2_mux_dataout : WIRE; + l1_w0_n3_mux_dataout : WIRE; + l1_w0_n4_mux_dataout : WIRE; + l1_w0_n5_mux_dataout : WIRE; + l1_w0_n6_mux_dataout : WIRE; + l1_w0_n7_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w1_n1_mux_dataout : WIRE; + l1_w1_n2_mux_dataout : WIRE; + l1_w1_n3_mux_dataout : WIRE; + l1_w1_n4_mux_dataout : WIRE; + l1_w1_n5_mux_dataout : WIRE; + l1_w1_n6_mux_dataout : WIRE; + l1_w1_n7_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w2_n1_mux_dataout : WIRE; + l1_w2_n2_mux_dataout : WIRE; + l1_w2_n3_mux_dataout : WIRE; + l1_w2_n4_mux_dataout : WIRE; + l1_w2_n5_mux_dataout : WIRE; + l1_w2_n6_mux_dataout : WIRE; + l1_w2_n7_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w3_n1_mux_dataout : WIRE; + l1_w3_n2_mux_dataout : WIRE; + l1_w3_n3_mux_dataout : WIRE; + l1_w3_n4_mux_dataout : WIRE; + l1_w3_n5_mux_dataout : WIRE; + l1_w3_n6_mux_dataout : WIRE; + l1_w3_n7_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w4_n1_mux_dataout : WIRE; + l1_w4_n2_mux_dataout : WIRE; + l1_w4_n3_mux_dataout : WIRE; + l1_w4_n4_mux_dataout : WIRE; + l1_w4_n5_mux_dataout : WIRE; + l1_w4_n6_mux_dataout : WIRE; + l1_w4_n7_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w5_n1_mux_dataout : WIRE; + l1_w5_n2_mux_dataout : WIRE; + l1_w5_n3_mux_dataout : WIRE; + l1_w5_n4_mux_dataout : WIRE; + l1_w5_n5_mux_dataout : WIRE; + l1_w5_n6_mux_dataout : WIRE; + l1_w5_n7_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w6_n1_mux_dataout : WIRE; + l1_w6_n2_mux_dataout : WIRE; + l1_w6_n3_mux_dataout : WIRE; + l1_w6_n4_mux_dataout : WIRE; + l1_w6_n5_mux_dataout : WIRE; + l1_w6_n6_mux_dataout : WIRE; + l1_w6_n7_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + l1_w7_n1_mux_dataout : WIRE; + l1_w7_n2_mux_dataout : WIRE; + l1_w7_n3_mux_dataout : WIRE; + l1_w7_n4_mux_dataout : WIRE; + l1_w7_n5_mux_dataout : WIRE; + l1_w7_n6_mux_dataout : WIRE; + l1_w7_n7_mux_dataout : WIRE; + l2_w0_n0_mux_dataout : WIRE; + l2_w0_n1_mux_dataout : WIRE; + l2_w0_n2_mux_dataout : WIRE; + l2_w0_n3_mux_dataout : WIRE; + l2_w1_n0_mux_dataout : WIRE; + l2_w1_n1_mux_dataout : WIRE; + l2_w1_n2_mux_dataout : WIRE; + l2_w1_n3_mux_dataout : WIRE; + l2_w2_n0_mux_dataout : WIRE; + l2_w2_n1_mux_dataout : WIRE; + l2_w2_n2_mux_dataout : WIRE; + l2_w2_n3_mux_dataout : WIRE; + l2_w3_n0_mux_dataout : WIRE; + l2_w3_n1_mux_dataout : WIRE; + l2_w3_n2_mux_dataout : WIRE; + l2_w3_n3_mux_dataout : WIRE; + l2_w4_n0_mux_dataout : WIRE; + l2_w4_n1_mux_dataout : WIRE; + l2_w4_n2_mux_dataout : WIRE; + l2_w4_n3_mux_dataout : WIRE; + l2_w5_n0_mux_dataout : WIRE; + l2_w5_n1_mux_dataout : WIRE; + l2_w5_n2_mux_dataout : WIRE; + l2_w5_n3_mux_dataout : WIRE; + l2_w6_n0_mux_dataout : WIRE; + l2_w6_n1_mux_dataout : WIRE; + l2_w6_n2_mux_dataout : WIRE; + l2_w6_n3_mux_dataout : WIRE; + l2_w7_n0_mux_dataout : WIRE; + l2_w7_n1_mux_dataout : WIRE; + l2_w7_n2_mux_dataout : WIRE; + l2_w7_n3_mux_dataout : WIRE; + l3_w0_n0_mux_dataout : WIRE; + l3_w0_n1_mux_dataout : WIRE; + l3_w1_n0_mux_dataout : WIRE; + l3_w1_n1_mux_dataout : WIRE; + l3_w2_n0_mux_dataout : WIRE; + l3_w2_n1_mux_dataout : WIRE; + l3_w3_n0_mux_dataout : WIRE; + l3_w3_n1_mux_dataout : WIRE; + l3_w4_n0_mux_dataout : WIRE; + l3_w4_n1_mux_dataout : WIRE; + l3_w5_n0_mux_dataout : WIRE; + l3_w5_n1_mux_dataout : WIRE; + l3_w6_n0_mux_dataout : WIRE; + l3_w6_n1_mux_dataout : WIRE; + l3_w7_n0_mux_dataout : WIRE; + l3_w7_n1_mux_dataout : WIRE; + l4_w0_n0_mux_dataout : WIRE; + l4_w1_n0_mux_dataout : WIRE; + l4_w2_n0_mux_dataout : WIRE; + l4_w3_n0_mux_dataout : WIRE; + l4_w4_n0_mux_dataout : WIRE; + l4_w5_n0_mux_dataout : WIRE; + l4_w6_n0_mux_dataout : WIRE; + l4_w7_n0_mux_dataout : WIRE; + data_wire[239..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[15..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16]; + l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32]; + l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48]; + l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[72..72] # !(sel_wire[0..0]) & data_wire[64..64]; + l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[88..88] # !(sel_wire[0..0]) & data_wire[80..80]; + l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[104..104] # !(sel_wire[0..0]) & data_wire[96..96]; + l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[120..120] # !(sel_wire[0..0]) & data_wire[112..112]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17]; + l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33]; + l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49]; + l1_w1_n4_mux_dataout = sel_wire[0..0] & data_wire[73..73] # !(sel_wire[0..0]) & data_wire[65..65]; + l1_w1_n5_mux_dataout = sel_wire[0..0] & data_wire[89..89] # !(sel_wire[0..0]) & data_wire[81..81]; + l1_w1_n6_mux_dataout = sel_wire[0..0] & data_wire[105..105] # !(sel_wire[0..0]) & data_wire[97..97]; + l1_w1_n7_mux_dataout = sel_wire[0..0] & data_wire[121..121] # !(sel_wire[0..0]) & data_wire[113..113]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18]; + l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34]; + l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50]; + l1_w2_n4_mux_dataout = sel_wire[0..0] & data_wire[74..74] # !(sel_wire[0..0]) & data_wire[66..66]; + l1_w2_n5_mux_dataout = sel_wire[0..0] & data_wire[90..90] # !(sel_wire[0..0]) & data_wire[82..82]; + l1_w2_n6_mux_dataout = sel_wire[0..0] & data_wire[106..106] # !(sel_wire[0..0]) & data_wire[98..98]; + l1_w2_n7_mux_dataout = sel_wire[0..0] & data_wire[122..122] # !(sel_wire[0..0]) & data_wire[114..114]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19]; + l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35]; + l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51]; + l1_w3_n4_mux_dataout = sel_wire[0..0] & data_wire[75..75] # !(sel_wire[0..0]) & data_wire[67..67]; + l1_w3_n5_mux_dataout = sel_wire[0..0] & data_wire[91..91] # !(sel_wire[0..0]) & data_wire[83..83]; + l1_w3_n6_mux_dataout = sel_wire[0..0] & data_wire[107..107] # !(sel_wire[0..0]) & data_wire[99..99]; + l1_w3_n7_mux_dataout = sel_wire[0..0] & data_wire[123..123] # !(sel_wire[0..0]) & data_wire[115..115]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20]; + l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36]; + l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52]; + l1_w4_n4_mux_dataout = sel_wire[0..0] & data_wire[76..76] # !(sel_wire[0..0]) & data_wire[68..68]; + l1_w4_n5_mux_dataout = sel_wire[0..0] & data_wire[92..92] # !(sel_wire[0..0]) & data_wire[84..84]; + l1_w4_n6_mux_dataout = sel_wire[0..0] & data_wire[108..108] # !(sel_wire[0..0]) & data_wire[100..100]; + l1_w4_n7_mux_dataout = sel_wire[0..0] & data_wire[124..124] # !(sel_wire[0..0]) & data_wire[116..116]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21]; + l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37]; + l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53]; + l1_w5_n4_mux_dataout = sel_wire[0..0] & data_wire[77..77] # !(sel_wire[0..0]) & data_wire[69..69]; + l1_w5_n5_mux_dataout = sel_wire[0..0] & data_wire[93..93] # !(sel_wire[0..0]) & data_wire[85..85]; + l1_w5_n6_mux_dataout = sel_wire[0..0] & data_wire[109..109] # !(sel_wire[0..0]) & data_wire[101..101]; + l1_w5_n7_mux_dataout = sel_wire[0..0] & data_wire[125..125] # !(sel_wire[0..0]) & data_wire[117..117]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22]; + l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38]; + l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54]; + l1_w6_n4_mux_dataout = sel_wire[0..0] & data_wire[78..78] # !(sel_wire[0..0]) & data_wire[70..70]; + l1_w6_n5_mux_dataout = sel_wire[0..0] & data_wire[94..94] # !(sel_wire[0..0]) & data_wire[86..86]; + l1_w6_n6_mux_dataout = sel_wire[0..0] & data_wire[110..110] # !(sel_wire[0..0]) & data_wire[102..102]; + l1_w6_n7_mux_dataout = sel_wire[0..0] & data_wire[126..126] # !(sel_wire[0..0]) & data_wire[118..118]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23]; + l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39]; + l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55]; + l1_w7_n4_mux_dataout = sel_wire[0..0] & data_wire[79..79] # !(sel_wire[0..0]) & data_wire[71..71]; + l1_w7_n5_mux_dataout = sel_wire[0..0] & data_wire[95..95] # !(sel_wire[0..0]) & data_wire[87..87]; + l1_w7_n6_mux_dataout = sel_wire[0..0] & data_wire[111..111] # !(sel_wire[0..0]) & data_wire[103..103]; + l1_w7_n7_mux_dataout = sel_wire[0..0] & data_wire[127..127] # !(sel_wire[0..0]) & data_wire[119..119]; + l2_w0_n0_mux_dataout = sel_wire[5..5] & data_wire[129..129] # !(sel_wire[5..5]) & data_wire[128..128]; + l2_w0_n1_mux_dataout = sel_wire[5..5] & data_wire[131..131] # !(sel_wire[5..5]) & data_wire[130..130]; + l2_w0_n2_mux_dataout = sel_wire[5..5] & data_wire[133..133] # !(sel_wire[5..5]) & data_wire[132..132]; + l2_w0_n3_mux_dataout = sel_wire[5..5] & data_wire[135..135] # !(sel_wire[5..5]) & data_wire[134..134]; + l2_w1_n0_mux_dataout = sel_wire[5..5] & data_wire[137..137] # !(sel_wire[5..5]) & data_wire[136..136]; + l2_w1_n1_mux_dataout = sel_wire[5..5] & data_wire[139..139] # !(sel_wire[5..5]) & data_wire[138..138]; + l2_w1_n2_mux_dataout = sel_wire[5..5] & data_wire[141..141] # !(sel_wire[5..5]) & data_wire[140..140]; + l2_w1_n3_mux_dataout = sel_wire[5..5] & data_wire[143..143] # !(sel_wire[5..5]) & data_wire[142..142]; + l2_w2_n0_mux_dataout = sel_wire[5..5] & data_wire[145..145] # !(sel_wire[5..5]) & data_wire[144..144]; + l2_w2_n1_mux_dataout = sel_wire[5..5] & data_wire[147..147] # !(sel_wire[5..5]) & data_wire[146..146]; + l2_w2_n2_mux_dataout = sel_wire[5..5] & data_wire[149..149] # !(sel_wire[5..5]) & data_wire[148..148]; + l2_w2_n3_mux_dataout = sel_wire[5..5] & data_wire[151..151] # !(sel_wire[5..5]) & data_wire[150..150]; + l2_w3_n0_mux_dataout = sel_wire[5..5] & data_wire[153..153] # !(sel_wire[5..5]) & data_wire[152..152]; + l2_w3_n1_mux_dataout = sel_wire[5..5] & data_wire[155..155] # !(sel_wire[5..5]) & data_wire[154..154]; + l2_w3_n2_mux_dataout = sel_wire[5..5] & data_wire[157..157] # !(sel_wire[5..5]) & data_wire[156..156]; + l2_w3_n3_mux_dataout = sel_wire[5..5] & data_wire[159..159] # !(sel_wire[5..5]) & data_wire[158..158]; + l2_w4_n0_mux_dataout = sel_wire[5..5] & data_wire[161..161] # !(sel_wire[5..5]) & data_wire[160..160]; + l2_w4_n1_mux_dataout = sel_wire[5..5] & data_wire[163..163] # !(sel_wire[5..5]) & data_wire[162..162]; + l2_w4_n2_mux_dataout = sel_wire[5..5] & data_wire[165..165] # !(sel_wire[5..5]) & data_wire[164..164]; + l2_w4_n3_mux_dataout = sel_wire[5..5] & data_wire[167..167] # !(sel_wire[5..5]) & data_wire[166..166]; + l2_w5_n0_mux_dataout = sel_wire[5..5] & data_wire[169..169] # !(sel_wire[5..5]) & data_wire[168..168]; + l2_w5_n1_mux_dataout = sel_wire[5..5] & data_wire[171..171] # !(sel_wire[5..5]) & data_wire[170..170]; + l2_w5_n2_mux_dataout = sel_wire[5..5] & data_wire[173..173] # !(sel_wire[5..5]) & data_wire[172..172]; + l2_w5_n3_mux_dataout = sel_wire[5..5] & data_wire[175..175] # !(sel_wire[5..5]) & data_wire[174..174]; + l2_w6_n0_mux_dataout = sel_wire[5..5] & data_wire[177..177] # !(sel_wire[5..5]) & data_wire[176..176]; + l2_w6_n1_mux_dataout = sel_wire[5..5] & data_wire[179..179] # !(sel_wire[5..5]) & data_wire[178..178]; + l2_w6_n2_mux_dataout = sel_wire[5..5] & data_wire[181..181] # !(sel_wire[5..5]) & data_wire[180..180]; + l2_w6_n3_mux_dataout = sel_wire[5..5] & data_wire[183..183] # !(sel_wire[5..5]) & data_wire[182..182]; + l2_w7_n0_mux_dataout = sel_wire[5..5] & data_wire[185..185] # !(sel_wire[5..5]) & data_wire[184..184]; + l2_w7_n1_mux_dataout = sel_wire[5..5] & data_wire[187..187] # !(sel_wire[5..5]) & data_wire[186..186]; + l2_w7_n2_mux_dataout = sel_wire[5..5] & data_wire[189..189] # !(sel_wire[5..5]) & data_wire[188..188]; + l2_w7_n3_mux_dataout = sel_wire[5..5] & data_wire[191..191] # !(sel_wire[5..5]) & data_wire[190..190]; + l3_w0_n0_mux_dataout = sel_wire[10..10] & data_wire[193..193] # !(sel_wire[10..10]) & data_wire[192..192]; + l3_w0_n1_mux_dataout = sel_wire[10..10] & data_wire[195..195] # !(sel_wire[10..10]) & data_wire[194..194]; + l3_w1_n0_mux_dataout = sel_wire[10..10] & data_wire[197..197] # !(sel_wire[10..10]) & data_wire[196..196]; + l3_w1_n1_mux_dataout = sel_wire[10..10] & data_wire[199..199] # !(sel_wire[10..10]) & data_wire[198..198]; + l3_w2_n0_mux_dataout = sel_wire[10..10] & data_wire[201..201] # !(sel_wire[10..10]) & data_wire[200..200]; + l3_w2_n1_mux_dataout = sel_wire[10..10] & data_wire[203..203] # !(sel_wire[10..10]) & data_wire[202..202]; + l3_w3_n0_mux_dataout = sel_wire[10..10] & data_wire[205..205] # !(sel_wire[10..10]) & data_wire[204..204]; + l3_w3_n1_mux_dataout = sel_wire[10..10] & data_wire[207..207] # !(sel_wire[10..10]) & data_wire[206..206]; + l3_w4_n0_mux_dataout = sel_wire[10..10] & data_wire[209..209] # !(sel_wire[10..10]) & data_wire[208..208]; + l3_w4_n1_mux_dataout = sel_wire[10..10] & data_wire[211..211] # !(sel_wire[10..10]) & data_wire[210..210]; + l3_w5_n0_mux_dataout = sel_wire[10..10] & data_wire[213..213] # !(sel_wire[10..10]) & data_wire[212..212]; + l3_w5_n1_mux_dataout = sel_wire[10..10] & data_wire[215..215] # !(sel_wire[10..10]) & data_wire[214..214]; + l3_w6_n0_mux_dataout = sel_wire[10..10] & data_wire[217..217] # !(sel_wire[10..10]) & data_wire[216..216]; + l3_w6_n1_mux_dataout = sel_wire[10..10] & data_wire[219..219] # !(sel_wire[10..10]) & data_wire[218..218]; + l3_w7_n0_mux_dataout = sel_wire[10..10] & data_wire[221..221] # !(sel_wire[10..10]) & data_wire[220..220]; + l3_w7_n1_mux_dataout = sel_wire[10..10] & data_wire[223..223] # !(sel_wire[10..10]) & data_wire[222..222]; + l4_w0_n0_mux_dataout = sel_wire[15..15] & data_wire[225..225] # !(sel_wire[15..15]) & data_wire[224..224]; + l4_w1_n0_mux_dataout = sel_wire[15..15] & data_wire[227..227] # !(sel_wire[15..15]) & data_wire[226..226]; + l4_w2_n0_mux_dataout = sel_wire[15..15] & data_wire[229..229] # !(sel_wire[15..15]) & data_wire[228..228]; + l4_w3_n0_mux_dataout = sel_wire[15..15] & data_wire[231..231] # !(sel_wire[15..15]) & data_wire[230..230]; + l4_w4_n0_mux_dataout = sel_wire[15..15] & data_wire[233..233] # !(sel_wire[15..15]) & data_wire[232..232]; + l4_w5_n0_mux_dataout = sel_wire[15..15] & data_wire[235..235] # !(sel_wire[15..15]) & data_wire[234..234]; + l4_w6_n0_mux_dataout = sel_wire[15..15] & data_wire[237..237] # !(sel_wire[15..15]) & data_wire[236..236]; + l4_w7_n0_mux_dataout = sel_wire[15..15] & data_wire[239..239] # !(sel_wire[15..15]) & data_wire[238..238]; + data_wire[] = ( l3_w7_n1_mux_dataout, l3_w7_n0_mux_dataout, l3_w6_n1_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n1_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n1_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n1_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n1_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n1_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w7_n3_mux_dataout, l2_w7_n2_mux_dataout, l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n3_mux_dataout, l2_w6_n2_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n3_mux_dataout, l2_w5_n2_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n3_mux_dataout, l2_w4_n2_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n3_mux_dataout, l2_w3_n2_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n3_mux_dataout, l2_w2_n2_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n3_mux_dataout, l2_w1_n2_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n7_mux_dataout, l1_w7_n6_mux_dataout, l1_w7_n5_mux_dataout, l1_w7_n4_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n7_mux_dataout, l1_w6_n6_mux_dataout, l1_w6_n5_mux_dataout, l1_w6_n4_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n7_mux_dataout, l1_w5_n6_mux_dataout, l1_w5_n5_mux_dataout, l1_w5_n4_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n7_mux_dataout, l1_w4_n6_mux_dataout, l1_w4_n5_mux_dataout, l1_w4_n4_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n7_mux_dataout, l1_w3_n6_mux_dataout, l1_w3_n5_mux_dataout, l1_w3_n4_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n7_mux_dataout, l1_w2_n6_mux_dataout, l1_w2_n5_mux_dataout, l1_w2_n4_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n7_mux_dataout, l1_w1_n6_mux_dataout, l1_w1_n5_mux_dataout, l1_w1_n4_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l4_w7_n0_mux_dataout, l4_w6_n0_mux_dataout, l4_w5_n0_mux_dataout, l4_w4_n0_mux_dataout, l4_w3_n0_mux_dataout, l4_w2_n0_mux_dataout, l4_w1_n0_mux_dataout, l4_w0_n0_mux_dataout); + sel_wire[] = ( sel[3..3], B"0000", sel[2..2], B"0000", sel[1..1], B"0000", sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/mux_ihb.tdf b/proj_quartus/db/mux_ihb.tdf new file mode 100644 index 000000000..634563b16 --- /dev/null +++ b/proj_quartus/db/mux_ihb.tdf @@ -0,0 +1,1048 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=64 LPM_WIDTH=8 LPM_WIDTHS=6 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 168 +SUBDESIGN mux_ihb +( + data[511..0] : input; + result[7..0] : output; + sel[5..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w0_n10_mux_dataout : WIRE; + l1_w0_n11_mux_dataout : WIRE; + l1_w0_n12_mux_dataout : WIRE; + l1_w0_n13_mux_dataout : WIRE; + l1_w0_n14_mux_dataout : WIRE; + l1_w0_n15_mux_dataout : WIRE; + l1_w0_n16_mux_dataout : WIRE; + l1_w0_n17_mux_dataout : WIRE; + l1_w0_n18_mux_dataout : WIRE; + l1_w0_n19_mux_dataout : WIRE; + l1_w0_n1_mux_dataout : WIRE; + l1_w0_n20_mux_dataout : WIRE; + l1_w0_n21_mux_dataout : WIRE; + l1_w0_n22_mux_dataout : WIRE; + l1_w0_n23_mux_dataout : WIRE; + l1_w0_n24_mux_dataout : WIRE; + l1_w0_n25_mux_dataout : WIRE; + l1_w0_n26_mux_dataout : WIRE; + l1_w0_n27_mux_dataout : WIRE; + l1_w0_n28_mux_dataout : WIRE; + l1_w0_n29_mux_dataout : WIRE; + l1_w0_n2_mux_dataout : WIRE; + l1_w0_n30_mux_dataout : WIRE; + l1_w0_n31_mux_dataout : WIRE; + l1_w0_n3_mux_dataout : WIRE; + l1_w0_n4_mux_dataout : WIRE; + l1_w0_n5_mux_dataout : WIRE; + l1_w0_n6_mux_dataout : WIRE; + l1_w0_n7_mux_dataout : WIRE; + l1_w0_n8_mux_dataout : WIRE; + l1_w0_n9_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w1_n10_mux_dataout : WIRE; + l1_w1_n11_mux_dataout : WIRE; + l1_w1_n12_mux_dataout : WIRE; + l1_w1_n13_mux_dataout : WIRE; + l1_w1_n14_mux_dataout : WIRE; + l1_w1_n15_mux_dataout : WIRE; + l1_w1_n16_mux_dataout : WIRE; + l1_w1_n17_mux_dataout : WIRE; + l1_w1_n18_mux_dataout : WIRE; + l1_w1_n19_mux_dataout : WIRE; + l1_w1_n1_mux_dataout : WIRE; + l1_w1_n20_mux_dataout : WIRE; + l1_w1_n21_mux_dataout : WIRE; + l1_w1_n22_mux_dataout : WIRE; + l1_w1_n23_mux_dataout : WIRE; + l1_w1_n24_mux_dataout : WIRE; + l1_w1_n25_mux_dataout : WIRE; + l1_w1_n26_mux_dataout : WIRE; + l1_w1_n27_mux_dataout : WIRE; + l1_w1_n28_mux_dataout : WIRE; + l1_w1_n29_mux_dataout : WIRE; + l1_w1_n2_mux_dataout : WIRE; + l1_w1_n30_mux_dataout : WIRE; + l1_w1_n31_mux_dataout : WIRE; + l1_w1_n3_mux_dataout : WIRE; + l1_w1_n4_mux_dataout : WIRE; + l1_w1_n5_mux_dataout : WIRE; + l1_w1_n6_mux_dataout : WIRE; + l1_w1_n7_mux_dataout : WIRE; + l1_w1_n8_mux_dataout : WIRE; + l1_w1_n9_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w2_n10_mux_dataout : WIRE; + l1_w2_n11_mux_dataout : WIRE; + l1_w2_n12_mux_dataout : WIRE; + l1_w2_n13_mux_dataout : WIRE; + l1_w2_n14_mux_dataout : WIRE; + l1_w2_n15_mux_dataout : WIRE; + l1_w2_n16_mux_dataout : WIRE; + l1_w2_n17_mux_dataout : WIRE; + l1_w2_n18_mux_dataout : WIRE; + l1_w2_n19_mux_dataout : WIRE; + l1_w2_n1_mux_dataout : WIRE; + l1_w2_n20_mux_dataout : WIRE; + l1_w2_n21_mux_dataout : WIRE; + l1_w2_n22_mux_dataout : WIRE; + l1_w2_n23_mux_dataout : WIRE; + l1_w2_n24_mux_dataout : WIRE; + l1_w2_n25_mux_dataout : WIRE; + l1_w2_n26_mux_dataout : WIRE; + l1_w2_n27_mux_dataout : WIRE; + l1_w2_n28_mux_dataout : WIRE; + l1_w2_n29_mux_dataout : WIRE; + l1_w2_n2_mux_dataout : WIRE; + l1_w2_n30_mux_dataout : WIRE; + l1_w2_n31_mux_dataout : WIRE; + l1_w2_n3_mux_dataout : WIRE; + l1_w2_n4_mux_dataout : WIRE; + l1_w2_n5_mux_dataout : WIRE; + l1_w2_n6_mux_dataout : WIRE; + l1_w2_n7_mux_dataout : WIRE; + l1_w2_n8_mux_dataout : WIRE; + l1_w2_n9_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w3_n10_mux_dataout : WIRE; + l1_w3_n11_mux_dataout : WIRE; + l1_w3_n12_mux_dataout : WIRE; + l1_w3_n13_mux_dataout : WIRE; + l1_w3_n14_mux_dataout : WIRE; + l1_w3_n15_mux_dataout : WIRE; + l1_w3_n16_mux_dataout : WIRE; + l1_w3_n17_mux_dataout : WIRE; + l1_w3_n18_mux_dataout : WIRE; + l1_w3_n19_mux_dataout : WIRE; + l1_w3_n1_mux_dataout : WIRE; + l1_w3_n20_mux_dataout : WIRE; + l1_w3_n21_mux_dataout : WIRE; + l1_w3_n22_mux_dataout : WIRE; + l1_w3_n23_mux_dataout : WIRE; + l1_w3_n24_mux_dataout : WIRE; + l1_w3_n25_mux_dataout : WIRE; + l1_w3_n26_mux_dataout : WIRE; + l1_w3_n27_mux_dataout : WIRE; + l1_w3_n28_mux_dataout : WIRE; + l1_w3_n29_mux_dataout : WIRE; + l1_w3_n2_mux_dataout : WIRE; + l1_w3_n30_mux_dataout : WIRE; + l1_w3_n31_mux_dataout : WIRE; + l1_w3_n3_mux_dataout : WIRE; + l1_w3_n4_mux_dataout : WIRE; + l1_w3_n5_mux_dataout : WIRE; + l1_w3_n6_mux_dataout : WIRE; + l1_w3_n7_mux_dataout : WIRE; + l1_w3_n8_mux_dataout : WIRE; + l1_w3_n9_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w4_n10_mux_dataout : WIRE; + l1_w4_n11_mux_dataout : WIRE; + l1_w4_n12_mux_dataout : WIRE; + l1_w4_n13_mux_dataout : WIRE; + l1_w4_n14_mux_dataout : WIRE; + l1_w4_n15_mux_dataout : WIRE; + l1_w4_n16_mux_dataout : WIRE; + l1_w4_n17_mux_dataout : WIRE; + l1_w4_n18_mux_dataout : WIRE; + l1_w4_n19_mux_dataout : WIRE; + l1_w4_n1_mux_dataout : WIRE; + l1_w4_n20_mux_dataout : WIRE; + l1_w4_n21_mux_dataout : WIRE; + l1_w4_n22_mux_dataout : WIRE; + l1_w4_n23_mux_dataout : WIRE; + l1_w4_n24_mux_dataout : WIRE; + l1_w4_n25_mux_dataout : WIRE; + l1_w4_n26_mux_dataout : WIRE; + l1_w4_n27_mux_dataout : WIRE; + l1_w4_n28_mux_dataout : WIRE; + l1_w4_n29_mux_dataout : WIRE; + l1_w4_n2_mux_dataout : WIRE; + l1_w4_n30_mux_dataout : WIRE; + l1_w4_n31_mux_dataout : WIRE; + l1_w4_n3_mux_dataout : WIRE; + l1_w4_n4_mux_dataout : WIRE; + l1_w4_n5_mux_dataout : WIRE; + l1_w4_n6_mux_dataout : WIRE; + l1_w4_n7_mux_dataout : WIRE; + l1_w4_n8_mux_dataout : WIRE; + l1_w4_n9_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w5_n10_mux_dataout : WIRE; + l1_w5_n11_mux_dataout : WIRE; + l1_w5_n12_mux_dataout : WIRE; + l1_w5_n13_mux_dataout : WIRE; + l1_w5_n14_mux_dataout : WIRE; + l1_w5_n15_mux_dataout : WIRE; + l1_w5_n16_mux_dataout : WIRE; + l1_w5_n17_mux_dataout : WIRE; + l1_w5_n18_mux_dataout : WIRE; + l1_w5_n19_mux_dataout : WIRE; + l1_w5_n1_mux_dataout : WIRE; + l1_w5_n20_mux_dataout : WIRE; + l1_w5_n21_mux_dataout : WIRE; + l1_w5_n22_mux_dataout : WIRE; + l1_w5_n23_mux_dataout : WIRE; + l1_w5_n24_mux_dataout : WIRE; + l1_w5_n25_mux_dataout : WIRE; + l1_w5_n26_mux_dataout : WIRE; + l1_w5_n27_mux_dataout : WIRE; + l1_w5_n28_mux_dataout : WIRE; + l1_w5_n29_mux_dataout : WIRE; + l1_w5_n2_mux_dataout : WIRE; + l1_w5_n30_mux_dataout : WIRE; + l1_w5_n31_mux_dataout : WIRE; + l1_w5_n3_mux_dataout : WIRE; + l1_w5_n4_mux_dataout : WIRE; + l1_w5_n5_mux_dataout : WIRE; + l1_w5_n6_mux_dataout : WIRE; + l1_w5_n7_mux_dataout : WIRE; + l1_w5_n8_mux_dataout : WIRE; + l1_w5_n9_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w6_n10_mux_dataout : WIRE; + l1_w6_n11_mux_dataout : WIRE; + l1_w6_n12_mux_dataout : WIRE; + l1_w6_n13_mux_dataout : WIRE; + l1_w6_n14_mux_dataout : WIRE; + l1_w6_n15_mux_dataout : WIRE; + l1_w6_n16_mux_dataout : WIRE; + l1_w6_n17_mux_dataout : WIRE; + l1_w6_n18_mux_dataout : WIRE; + l1_w6_n19_mux_dataout : WIRE; + l1_w6_n1_mux_dataout : WIRE; + l1_w6_n20_mux_dataout : WIRE; + l1_w6_n21_mux_dataout : WIRE; + l1_w6_n22_mux_dataout : WIRE; + l1_w6_n23_mux_dataout : WIRE; + l1_w6_n24_mux_dataout : WIRE; + l1_w6_n25_mux_dataout : WIRE; + l1_w6_n26_mux_dataout : WIRE; + l1_w6_n27_mux_dataout : WIRE; + l1_w6_n28_mux_dataout : WIRE; + l1_w6_n29_mux_dataout : WIRE; + l1_w6_n2_mux_dataout : WIRE; + l1_w6_n30_mux_dataout : WIRE; + l1_w6_n31_mux_dataout : WIRE; + l1_w6_n3_mux_dataout : WIRE; + l1_w6_n4_mux_dataout : WIRE; + l1_w6_n5_mux_dataout : WIRE; + l1_w6_n6_mux_dataout : WIRE; + l1_w6_n7_mux_dataout : WIRE; + l1_w6_n8_mux_dataout : WIRE; + l1_w6_n9_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + l1_w7_n10_mux_dataout : WIRE; + l1_w7_n11_mux_dataout : WIRE; + l1_w7_n12_mux_dataout : WIRE; + l1_w7_n13_mux_dataout : WIRE; + l1_w7_n14_mux_dataout : WIRE; + l1_w7_n15_mux_dataout : WIRE; + l1_w7_n16_mux_dataout : WIRE; + l1_w7_n17_mux_dataout : WIRE; + l1_w7_n18_mux_dataout : WIRE; + l1_w7_n19_mux_dataout : WIRE; + l1_w7_n1_mux_dataout : WIRE; + l1_w7_n20_mux_dataout : WIRE; + l1_w7_n21_mux_dataout : WIRE; + l1_w7_n22_mux_dataout : WIRE; + l1_w7_n23_mux_dataout : WIRE; + l1_w7_n24_mux_dataout : WIRE; + l1_w7_n25_mux_dataout : WIRE; + l1_w7_n26_mux_dataout : WIRE; + l1_w7_n27_mux_dataout : WIRE; + l1_w7_n28_mux_dataout : WIRE; + l1_w7_n29_mux_dataout : WIRE; + l1_w7_n2_mux_dataout : WIRE; + l1_w7_n30_mux_dataout : WIRE; + l1_w7_n31_mux_dataout : WIRE; + l1_w7_n3_mux_dataout : WIRE; + l1_w7_n4_mux_dataout : WIRE; + l1_w7_n5_mux_dataout : WIRE; + l1_w7_n6_mux_dataout : WIRE; + l1_w7_n7_mux_dataout : WIRE; + l1_w7_n8_mux_dataout : WIRE; + l1_w7_n9_mux_dataout : WIRE; + l2_w0_n0_mux_dataout : WIRE; + l2_w0_n10_mux_dataout : WIRE; + l2_w0_n11_mux_dataout : WIRE; + l2_w0_n12_mux_dataout : WIRE; + l2_w0_n13_mux_dataout : WIRE; + l2_w0_n14_mux_dataout : WIRE; + l2_w0_n15_mux_dataout : WIRE; + l2_w0_n1_mux_dataout : WIRE; + l2_w0_n2_mux_dataout : WIRE; + l2_w0_n3_mux_dataout : WIRE; + l2_w0_n4_mux_dataout : WIRE; + l2_w0_n5_mux_dataout : WIRE; + l2_w0_n6_mux_dataout : WIRE; + l2_w0_n7_mux_dataout : WIRE; + l2_w0_n8_mux_dataout : WIRE; + l2_w0_n9_mux_dataout : WIRE; + l2_w1_n0_mux_dataout : WIRE; + l2_w1_n10_mux_dataout : WIRE; + l2_w1_n11_mux_dataout : WIRE; + l2_w1_n12_mux_dataout : WIRE; + l2_w1_n13_mux_dataout : WIRE; + l2_w1_n14_mux_dataout : WIRE; + l2_w1_n15_mux_dataout : WIRE; + l2_w1_n1_mux_dataout : WIRE; + l2_w1_n2_mux_dataout : WIRE; + l2_w1_n3_mux_dataout : WIRE; + l2_w1_n4_mux_dataout : WIRE; + l2_w1_n5_mux_dataout : WIRE; + l2_w1_n6_mux_dataout : WIRE; + l2_w1_n7_mux_dataout : WIRE; + l2_w1_n8_mux_dataout : WIRE; + l2_w1_n9_mux_dataout : WIRE; + l2_w2_n0_mux_dataout : WIRE; + l2_w2_n10_mux_dataout : WIRE; + l2_w2_n11_mux_dataout : WIRE; + l2_w2_n12_mux_dataout : WIRE; + l2_w2_n13_mux_dataout : WIRE; + l2_w2_n14_mux_dataout : WIRE; + l2_w2_n15_mux_dataout : WIRE; + l2_w2_n1_mux_dataout : WIRE; + l2_w2_n2_mux_dataout : WIRE; + l2_w2_n3_mux_dataout : WIRE; + l2_w2_n4_mux_dataout : WIRE; + l2_w2_n5_mux_dataout : WIRE; + l2_w2_n6_mux_dataout : WIRE; + l2_w2_n7_mux_dataout : WIRE; + l2_w2_n8_mux_dataout : WIRE; + l2_w2_n9_mux_dataout : WIRE; + l2_w3_n0_mux_dataout : WIRE; + l2_w3_n10_mux_dataout : WIRE; + l2_w3_n11_mux_dataout : WIRE; + l2_w3_n12_mux_dataout : WIRE; + l2_w3_n13_mux_dataout : WIRE; + l2_w3_n14_mux_dataout : WIRE; + l2_w3_n15_mux_dataout : WIRE; + l2_w3_n1_mux_dataout : WIRE; + l2_w3_n2_mux_dataout : WIRE; + l2_w3_n3_mux_dataout : WIRE; + l2_w3_n4_mux_dataout : WIRE; + l2_w3_n5_mux_dataout : WIRE; + l2_w3_n6_mux_dataout : WIRE; + l2_w3_n7_mux_dataout : WIRE; + l2_w3_n8_mux_dataout : WIRE; + l2_w3_n9_mux_dataout : WIRE; + l2_w4_n0_mux_dataout : WIRE; + l2_w4_n10_mux_dataout : WIRE; + l2_w4_n11_mux_dataout : WIRE; + l2_w4_n12_mux_dataout : WIRE; + l2_w4_n13_mux_dataout : WIRE; + l2_w4_n14_mux_dataout : WIRE; + l2_w4_n15_mux_dataout : WIRE; + l2_w4_n1_mux_dataout : WIRE; + l2_w4_n2_mux_dataout : WIRE; + l2_w4_n3_mux_dataout : WIRE; + l2_w4_n4_mux_dataout : WIRE; + l2_w4_n5_mux_dataout : WIRE; + l2_w4_n6_mux_dataout : WIRE; + l2_w4_n7_mux_dataout : WIRE; + l2_w4_n8_mux_dataout : WIRE; + l2_w4_n9_mux_dataout : WIRE; + l2_w5_n0_mux_dataout : WIRE; + l2_w5_n10_mux_dataout : WIRE; + l2_w5_n11_mux_dataout : WIRE; + l2_w5_n12_mux_dataout : WIRE; + l2_w5_n13_mux_dataout : WIRE; + l2_w5_n14_mux_dataout : WIRE; + l2_w5_n15_mux_dataout : WIRE; + l2_w5_n1_mux_dataout : WIRE; + l2_w5_n2_mux_dataout : WIRE; + l2_w5_n3_mux_dataout : WIRE; + l2_w5_n4_mux_dataout : WIRE; + l2_w5_n5_mux_dataout : WIRE; + l2_w5_n6_mux_dataout : WIRE; + l2_w5_n7_mux_dataout : WIRE; + l2_w5_n8_mux_dataout : WIRE; + l2_w5_n9_mux_dataout : WIRE; + l2_w6_n0_mux_dataout : WIRE; + l2_w6_n10_mux_dataout : WIRE; + l2_w6_n11_mux_dataout : WIRE; + l2_w6_n12_mux_dataout : WIRE; + l2_w6_n13_mux_dataout : WIRE; + l2_w6_n14_mux_dataout : WIRE; + l2_w6_n15_mux_dataout : WIRE; + l2_w6_n1_mux_dataout : WIRE; + l2_w6_n2_mux_dataout : WIRE; + l2_w6_n3_mux_dataout : WIRE; + l2_w6_n4_mux_dataout : WIRE; + l2_w6_n5_mux_dataout : WIRE; + l2_w6_n6_mux_dataout : WIRE; + l2_w6_n7_mux_dataout : WIRE; + l2_w6_n8_mux_dataout : WIRE; + l2_w6_n9_mux_dataout : WIRE; + l2_w7_n0_mux_dataout : WIRE; + l2_w7_n10_mux_dataout : WIRE; + l2_w7_n11_mux_dataout : WIRE; + l2_w7_n12_mux_dataout : WIRE; + l2_w7_n13_mux_dataout : WIRE; + l2_w7_n14_mux_dataout : WIRE; + l2_w7_n15_mux_dataout : WIRE; + l2_w7_n1_mux_dataout : WIRE; + l2_w7_n2_mux_dataout : WIRE; + l2_w7_n3_mux_dataout : WIRE; + l2_w7_n4_mux_dataout : WIRE; + l2_w7_n5_mux_dataout : WIRE; + l2_w7_n6_mux_dataout : WIRE; + l2_w7_n7_mux_dataout : WIRE; + l2_w7_n8_mux_dataout : WIRE; + l2_w7_n9_mux_dataout : WIRE; + l3_w0_n0_mux_dataout : WIRE; + l3_w0_n1_mux_dataout : WIRE; + l3_w0_n2_mux_dataout : WIRE; + l3_w0_n3_mux_dataout : WIRE; + l3_w0_n4_mux_dataout : WIRE; + l3_w0_n5_mux_dataout : WIRE; + l3_w0_n6_mux_dataout : WIRE; + l3_w0_n7_mux_dataout : WIRE; + l3_w1_n0_mux_dataout : WIRE; + l3_w1_n1_mux_dataout : WIRE; + l3_w1_n2_mux_dataout : WIRE; + l3_w1_n3_mux_dataout : WIRE; + l3_w1_n4_mux_dataout : WIRE; + l3_w1_n5_mux_dataout : WIRE; + l3_w1_n6_mux_dataout : WIRE; + l3_w1_n7_mux_dataout : WIRE; + l3_w2_n0_mux_dataout : WIRE; + l3_w2_n1_mux_dataout : WIRE; + l3_w2_n2_mux_dataout : WIRE; + l3_w2_n3_mux_dataout : WIRE; + l3_w2_n4_mux_dataout : WIRE; + l3_w2_n5_mux_dataout : WIRE; + l3_w2_n6_mux_dataout : WIRE; + l3_w2_n7_mux_dataout : WIRE; + l3_w3_n0_mux_dataout : WIRE; + l3_w3_n1_mux_dataout : WIRE; + l3_w3_n2_mux_dataout : WIRE; + l3_w3_n3_mux_dataout : WIRE; + l3_w3_n4_mux_dataout : WIRE; + l3_w3_n5_mux_dataout : WIRE; + l3_w3_n6_mux_dataout : WIRE; + l3_w3_n7_mux_dataout : WIRE; + l3_w4_n0_mux_dataout : WIRE; + l3_w4_n1_mux_dataout : WIRE; + l3_w4_n2_mux_dataout : WIRE; + l3_w4_n3_mux_dataout : WIRE; + l3_w4_n4_mux_dataout : WIRE; + l3_w4_n5_mux_dataout : WIRE; + l3_w4_n6_mux_dataout : WIRE; + l3_w4_n7_mux_dataout : WIRE; + l3_w5_n0_mux_dataout : WIRE; + l3_w5_n1_mux_dataout : WIRE; + l3_w5_n2_mux_dataout : WIRE; + l3_w5_n3_mux_dataout : WIRE; + l3_w5_n4_mux_dataout : WIRE; + l3_w5_n5_mux_dataout : WIRE; + l3_w5_n6_mux_dataout : WIRE; + l3_w5_n7_mux_dataout : WIRE; + l3_w6_n0_mux_dataout : WIRE; + l3_w6_n1_mux_dataout : WIRE; + l3_w6_n2_mux_dataout : WIRE; + l3_w6_n3_mux_dataout : WIRE; + l3_w6_n4_mux_dataout : WIRE; + l3_w6_n5_mux_dataout : WIRE; + l3_w6_n6_mux_dataout : WIRE; + l3_w6_n7_mux_dataout : WIRE; + l3_w7_n0_mux_dataout : WIRE; + l3_w7_n1_mux_dataout : WIRE; + l3_w7_n2_mux_dataout : WIRE; + l3_w7_n3_mux_dataout : WIRE; + l3_w7_n4_mux_dataout : WIRE; + l3_w7_n5_mux_dataout : WIRE; + l3_w7_n6_mux_dataout : WIRE; + l3_w7_n7_mux_dataout : WIRE; + l4_w0_n0_mux_dataout : WIRE; + l4_w0_n1_mux_dataout : WIRE; + l4_w0_n2_mux_dataout : WIRE; + l4_w0_n3_mux_dataout : WIRE; + l4_w1_n0_mux_dataout : WIRE; + l4_w1_n1_mux_dataout : WIRE; + l4_w1_n2_mux_dataout : WIRE; + l4_w1_n3_mux_dataout : WIRE; + l4_w2_n0_mux_dataout : WIRE; + l4_w2_n1_mux_dataout : WIRE; + l4_w2_n2_mux_dataout : WIRE; + l4_w2_n3_mux_dataout : WIRE; + l4_w3_n0_mux_dataout : WIRE; + l4_w3_n1_mux_dataout : WIRE; + l4_w3_n2_mux_dataout : WIRE; + l4_w3_n3_mux_dataout : WIRE; + l4_w4_n0_mux_dataout : WIRE; + l4_w4_n1_mux_dataout : WIRE; + l4_w4_n2_mux_dataout : WIRE; + l4_w4_n3_mux_dataout : WIRE; + l4_w5_n0_mux_dataout : WIRE; + l4_w5_n1_mux_dataout : WIRE; + l4_w5_n2_mux_dataout : WIRE; + l4_w5_n3_mux_dataout : WIRE; + l4_w6_n0_mux_dataout : WIRE; + l4_w6_n1_mux_dataout : WIRE; + l4_w6_n2_mux_dataout : WIRE; + l4_w6_n3_mux_dataout : WIRE; + l4_w7_n0_mux_dataout : WIRE; + l4_w7_n1_mux_dataout : WIRE; + l4_w7_n2_mux_dataout : WIRE; + l4_w7_n3_mux_dataout : WIRE; + l5_w0_n0_mux_dataout : WIRE; + l5_w0_n1_mux_dataout : WIRE; + l5_w1_n0_mux_dataout : WIRE; + l5_w1_n1_mux_dataout : WIRE; + l5_w2_n0_mux_dataout : WIRE; + l5_w2_n1_mux_dataout : WIRE; + l5_w3_n0_mux_dataout : WIRE; + l5_w3_n1_mux_dataout : WIRE; + l5_w4_n0_mux_dataout : WIRE; + l5_w4_n1_mux_dataout : WIRE; + l5_w5_n0_mux_dataout : WIRE; + l5_w5_n1_mux_dataout : WIRE; + l5_w6_n0_mux_dataout : WIRE; + l5_w6_n1_mux_dataout : WIRE; + l5_w7_n0_mux_dataout : WIRE; + l5_w7_n1_mux_dataout : WIRE; + l6_w0_n0_mux_dataout : WIRE; + l6_w1_n0_mux_dataout : WIRE; + l6_w2_n0_mux_dataout : WIRE; + l6_w3_n0_mux_dataout : WIRE; + l6_w4_n0_mux_dataout : WIRE; + l6_w5_n0_mux_dataout : WIRE; + l6_w6_n0_mux_dataout : WIRE; + l6_w7_n0_mux_dataout : WIRE; + data_wire[1007..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[35..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w0_n10_mux_dataout = sel_wire[0..0] & data_wire[168..168] # !(sel_wire[0..0]) & data_wire[160..160]; + l1_w0_n11_mux_dataout = sel_wire[0..0] & data_wire[184..184] # !(sel_wire[0..0]) & data_wire[176..176]; + l1_w0_n12_mux_dataout = sel_wire[0..0] & data_wire[200..200] # !(sel_wire[0..0]) & data_wire[192..192]; + l1_w0_n13_mux_dataout = sel_wire[0..0] & data_wire[216..216] # !(sel_wire[0..0]) & data_wire[208..208]; + l1_w0_n14_mux_dataout = sel_wire[0..0] & data_wire[232..232] # !(sel_wire[0..0]) & data_wire[224..224]; + l1_w0_n15_mux_dataout = sel_wire[0..0] & data_wire[248..248] # !(sel_wire[0..0]) & data_wire[240..240]; + l1_w0_n16_mux_dataout = sel_wire[0..0] & data_wire[264..264] # !(sel_wire[0..0]) & data_wire[256..256]; + l1_w0_n17_mux_dataout = sel_wire[0..0] & data_wire[280..280] # !(sel_wire[0..0]) & data_wire[272..272]; + l1_w0_n18_mux_dataout = sel_wire[0..0] & data_wire[296..296] # !(sel_wire[0..0]) & data_wire[288..288]; + l1_w0_n19_mux_dataout = sel_wire[0..0] & data_wire[312..312] # !(sel_wire[0..0]) & data_wire[304..304]; + l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16]; + l1_w0_n20_mux_dataout = sel_wire[0..0] & data_wire[328..328] # !(sel_wire[0..0]) & data_wire[320..320]; + l1_w0_n21_mux_dataout = sel_wire[0..0] & data_wire[344..344] # !(sel_wire[0..0]) & data_wire[336..336]; + l1_w0_n22_mux_dataout = sel_wire[0..0] & data_wire[360..360] # !(sel_wire[0..0]) & data_wire[352..352]; + l1_w0_n23_mux_dataout = sel_wire[0..0] & data_wire[376..376] # !(sel_wire[0..0]) & data_wire[368..368]; + l1_w0_n24_mux_dataout = sel_wire[0..0] & data_wire[392..392] # !(sel_wire[0..0]) & data_wire[384..384]; + l1_w0_n25_mux_dataout = sel_wire[0..0] & data_wire[408..408] # !(sel_wire[0..0]) & data_wire[400..400]; + l1_w0_n26_mux_dataout = sel_wire[0..0] & data_wire[424..424] # !(sel_wire[0..0]) & data_wire[416..416]; + l1_w0_n27_mux_dataout = sel_wire[0..0] & data_wire[440..440] # !(sel_wire[0..0]) & data_wire[432..432]; + l1_w0_n28_mux_dataout = sel_wire[0..0] & data_wire[456..456] # !(sel_wire[0..0]) & data_wire[448..448]; + l1_w0_n29_mux_dataout = sel_wire[0..0] & data_wire[472..472] # !(sel_wire[0..0]) & data_wire[464..464]; + l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32]; + l1_w0_n30_mux_dataout = sel_wire[0..0] & data_wire[488..488] # !(sel_wire[0..0]) & data_wire[480..480]; + l1_w0_n31_mux_dataout = sel_wire[0..0] & data_wire[504..504] # !(sel_wire[0..0]) & data_wire[496..496]; + l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48]; + l1_w0_n4_mux_dataout = sel_wire[0..0] & data_wire[72..72] # !(sel_wire[0..0]) & data_wire[64..64]; + l1_w0_n5_mux_dataout = sel_wire[0..0] & data_wire[88..88] # !(sel_wire[0..0]) & data_wire[80..80]; + l1_w0_n6_mux_dataout = sel_wire[0..0] & data_wire[104..104] # !(sel_wire[0..0]) & data_wire[96..96]; + l1_w0_n7_mux_dataout = sel_wire[0..0] & data_wire[120..120] # !(sel_wire[0..0]) & data_wire[112..112]; + l1_w0_n8_mux_dataout = sel_wire[0..0] & data_wire[136..136] # !(sel_wire[0..0]) & data_wire[128..128]; + l1_w0_n9_mux_dataout = sel_wire[0..0] & data_wire[152..152] # !(sel_wire[0..0]) & data_wire[144..144]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w1_n10_mux_dataout = sel_wire[0..0] & data_wire[169..169] # !(sel_wire[0..0]) & data_wire[161..161]; + l1_w1_n11_mux_dataout = sel_wire[0..0] & data_wire[185..185] # !(sel_wire[0..0]) & data_wire[177..177]; + l1_w1_n12_mux_dataout = sel_wire[0..0] & data_wire[201..201] # !(sel_wire[0..0]) & data_wire[193..193]; + l1_w1_n13_mux_dataout = sel_wire[0..0] & data_wire[217..217] # !(sel_wire[0..0]) & data_wire[209..209]; + l1_w1_n14_mux_dataout = sel_wire[0..0] & data_wire[233..233] # !(sel_wire[0..0]) & data_wire[225..225]; + l1_w1_n15_mux_dataout = sel_wire[0..0] & data_wire[249..249] # !(sel_wire[0..0]) & data_wire[241..241]; + l1_w1_n16_mux_dataout = sel_wire[0..0] & data_wire[265..265] # !(sel_wire[0..0]) & data_wire[257..257]; + l1_w1_n17_mux_dataout = sel_wire[0..0] & data_wire[281..281] # !(sel_wire[0..0]) & data_wire[273..273]; + l1_w1_n18_mux_dataout = sel_wire[0..0] & data_wire[297..297] # !(sel_wire[0..0]) & data_wire[289..289]; + l1_w1_n19_mux_dataout = sel_wire[0..0] & data_wire[313..313] # !(sel_wire[0..0]) & data_wire[305..305]; + l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17]; + l1_w1_n20_mux_dataout = sel_wire[0..0] & data_wire[329..329] # !(sel_wire[0..0]) & data_wire[321..321]; + l1_w1_n21_mux_dataout = sel_wire[0..0] & data_wire[345..345] # !(sel_wire[0..0]) & data_wire[337..337]; + l1_w1_n22_mux_dataout = sel_wire[0..0] & data_wire[361..361] # !(sel_wire[0..0]) & data_wire[353..353]; + l1_w1_n23_mux_dataout = sel_wire[0..0] & data_wire[377..377] # !(sel_wire[0..0]) & data_wire[369..369]; + l1_w1_n24_mux_dataout = sel_wire[0..0] & data_wire[393..393] # !(sel_wire[0..0]) & data_wire[385..385]; + l1_w1_n25_mux_dataout = sel_wire[0..0] & data_wire[409..409] # !(sel_wire[0..0]) & data_wire[401..401]; + l1_w1_n26_mux_dataout = sel_wire[0..0] & data_wire[425..425] # !(sel_wire[0..0]) & data_wire[417..417]; + l1_w1_n27_mux_dataout = sel_wire[0..0] & data_wire[441..441] # !(sel_wire[0..0]) & data_wire[433..433]; + l1_w1_n28_mux_dataout = sel_wire[0..0] & data_wire[457..457] # !(sel_wire[0..0]) & data_wire[449..449]; + l1_w1_n29_mux_dataout = sel_wire[0..0] & data_wire[473..473] # !(sel_wire[0..0]) & data_wire[465..465]; + l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33]; + l1_w1_n30_mux_dataout = sel_wire[0..0] & data_wire[489..489] # !(sel_wire[0..0]) & data_wire[481..481]; + l1_w1_n31_mux_dataout = sel_wire[0..0] & data_wire[505..505] # !(sel_wire[0..0]) & data_wire[497..497]; + l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49]; + l1_w1_n4_mux_dataout = sel_wire[0..0] & data_wire[73..73] # !(sel_wire[0..0]) & data_wire[65..65]; + l1_w1_n5_mux_dataout = sel_wire[0..0] & data_wire[89..89] # !(sel_wire[0..0]) & data_wire[81..81]; + l1_w1_n6_mux_dataout = sel_wire[0..0] & data_wire[105..105] # !(sel_wire[0..0]) & data_wire[97..97]; + l1_w1_n7_mux_dataout = sel_wire[0..0] & data_wire[121..121] # !(sel_wire[0..0]) & data_wire[113..113]; + l1_w1_n8_mux_dataout = sel_wire[0..0] & data_wire[137..137] # !(sel_wire[0..0]) & data_wire[129..129]; + l1_w1_n9_mux_dataout = sel_wire[0..0] & data_wire[153..153] # !(sel_wire[0..0]) & data_wire[145..145]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w2_n10_mux_dataout = sel_wire[0..0] & data_wire[170..170] # !(sel_wire[0..0]) & data_wire[162..162]; + l1_w2_n11_mux_dataout = sel_wire[0..0] & data_wire[186..186] # !(sel_wire[0..0]) & data_wire[178..178]; + l1_w2_n12_mux_dataout = sel_wire[0..0] & data_wire[202..202] # !(sel_wire[0..0]) & data_wire[194..194]; + l1_w2_n13_mux_dataout = sel_wire[0..0] & data_wire[218..218] # !(sel_wire[0..0]) & data_wire[210..210]; + l1_w2_n14_mux_dataout = sel_wire[0..0] & data_wire[234..234] # !(sel_wire[0..0]) & data_wire[226..226]; + l1_w2_n15_mux_dataout = sel_wire[0..0] & data_wire[250..250] # !(sel_wire[0..0]) & data_wire[242..242]; + l1_w2_n16_mux_dataout = sel_wire[0..0] & data_wire[266..266] # !(sel_wire[0..0]) & data_wire[258..258]; + l1_w2_n17_mux_dataout = sel_wire[0..0] & data_wire[282..282] # !(sel_wire[0..0]) & data_wire[274..274]; + l1_w2_n18_mux_dataout = sel_wire[0..0] & data_wire[298..298] # !(sel_wire[0..0]) & data_wire[290..290]; + l1_w2_n19_mux_dataout = sel_wire[0..0] & data_wire[314..314] # !(sel_wire[0..0]) & data_wire[306..306]; + l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18]; + l1_w2_n20_mux_dataout = sel_wire[0..0] & data_wire[330..330] # !(sel_wire[0..0]) & data_wire[322..322]; + l1_w2_n21_mux_dataout = sel_wire[0..0] & data_wire[346..346] # !(sel_wire[0..0]) & data_wire[338..338]; + l1_w2_n22_mux_dataout = sel_wire[0..0] & data_wire[362..362] # !(sel_wire[0..0]) & data_wire[354..354]; + l1_w2_n23_mux_dataout = sel_wire[0..0] & data_wire[378..378] # !(sel_wire[0..0]) & data_wire[370..370]; + l1_w2_n24_mux_dataout = sel_wire[0..0] & data_wire[394..394] # !(sel_wire[0..0]) & data_wire[386..386]; + l1_w2_n25_mux_dataout = sel_wire[0..0] & data_wire[410..410] # !(sel_wire[0..0]) & data_wire[402..402]; + l1_w2_n26_mux_dataout = sel_wire[0..0] & data_wire[426..426] # !(sel_wire[0..0]) & data_wire[418..418]; + l1_w2_n27_mux_dataout = sel_wire[0..0] & data_wire[442..442] # !(sel_wire[0..0]) & data_wire[434..434]; + l1_w2_n28_mux_dataout = sel_wire[0..0] & data_wire[458..458] # !(sel_wire[0..0]) & data_wire[450..450]; + l1_w2_n29_mux_dataout = sel_wire[0..0] & data_wire[474..474] # !(sel_wire[0..0]) & data_wire[466..466]; + l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34]; + l1_w2_n30_mux_dataout = sel_wire[0..0] & data_wire[490..490] # !(sel_wire[0..0]) & data_wire[482..482]; + l1_w2_n31_mux_dataout = sel_wire[0..0] & data_wire[506..506] # !(sel_wire[0..0]) & data_wire[498..498]; + l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50]; + l1_w2_n4_mux_dataout = sel_wire[0..0] & data_wire[74..74] # !(sel_wire[0..0]) & data_wire[66..66]; + l1_w2_n5_mux_dataout = sel_wire[0..0] & data_wire[90..90] # !(sel_wire[0..0]) & data_wire[82..82]; + l1_w2_n6_mux_dataout = sel_wire[0..0] & data_wire[106..106] # !(sel_wire[0..0]) & data_wire[98..98]; + l1_w2_n7_mux_dataout = sel_wire[0..0] & data_wire[122..122] # !(sel_wire[0..0]) & data_wire[114..114]; + l1_w2_n8_mux_dataout = sel_wire[0..0] & data_wire[138..138] # !(sel_wire[0..0]) & data_wire[130..130]; + l1_w2_n9_mux_dataout = sel_wire[0..0] & data_wire[154..154] # !(sel_wire[0..0]) & data_wire[146..146]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w3_n10_mux_dataout = sel_wire[0..0] & data_wire[171..171] # !(sel_wire[0..0]) & data_wire[163..163]; + l1_w3_n11_mux_dataout = sel_wire[0..0] & data_wire[187..187] # !(sel_wire[0..0]) & data_wire[179..179]; + l1_w3_n12_mux_dataout = sel_wire[0..0] & data_wire[203..203] # !(sel_wire[0..0]) & data_wire[195..195]; + l1_w3_n13_mux_dataout = sel_wire[0..0] & data_wire[219..219] # !(sel_wire[0..0]) & data_wire[211..211]; + l1_w3_n14_mux_dataout = sel_wire[0..0] & data_wire[235..235] # !(sel_wire[0..0]) & data_wire[227..227]; + l1_w3_n15_mux_dataout = sel_wire[0..0] & data_wire[251..251] # !(sel_wire[0..0]) & data_wire[243..243]; + l1_w3_n16_mux_dataout = sel_wire[0..0] & data_wire[267..267] # !(sel_wire[0..0]) & data_wire[259..259]; + l1_w3_n17_mux_dataout = sel_wire[0..0] & data_wire[283..283] # !(sel_wire[0..0]) & data_wire[275..275]; + l1_w3_n18_mux_dataout = sel_wire[0..0] & data_wire[299..299] # !(sel_wire[0..0]) & data_wire[291..291]; + l1_w3_n19_mux_dataout = sel_wire[0..0] & data_wire[315..315] # !(sel_wire[0..0]) & data_wire[307..307]; + l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19]; + l1_w3_n20_mux_dataout = sel_wire[0..0] & data_wire[331..331] # !(sel_wire[0..0]) & data_wire[323..323]; + l1_w3_n21_mux_dataout = sel_wire[0..0] & data_wire[347..347] # !(sel_wire[0..0]) & data_wire[339..339]; + l1_w3_n22_mux_dataout = sel_wire[0..0] & data_wire[363..363] # !(sel_wire[0..0]) & data_wire[355..355]; + l1_w3_n23_mux_dataout = sel_wire[0..0] & data_wire[379..379] # !(sel_wire[0..0]) & data_wire[371..371]; + l1_w3_n24_mux_dataout = sel_wire[0..0] & data_wire[395..395] # !(sel_wire[0..0]) & data_wire[387..387]; + l1_w3_n25_mux_dataout = sel_wire[0..0] & data_wire[411..411] # !(sel_wire[0..0]) & data_wire[403..403]; + l1_w3_n26_mux_dataout = sel_wire[0..0] & data_wire[427..427] # !(sel_wire[0..0]) & data_wire[419..419]; + l1_w3_n27_mux_dataout = sel_wire[0..0] & data_wire[443..443] # !(sel_wire[0..0]) & data_wire[435..435]; + l1_w3_n28_mux_dataout = sel_wire[0..0] & data_wire[459..459] # !(sel_wire[0..0]) & data_wire[451..451]; + l1_w3_n29_mux_dataout = sel_wire[0..0] & data_wire[475..475] # !(sel_wire[0..0]) & data_wire[467..467]; + l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35]; + l1_w3_n30_mux_dataout = sel_wire[0..0] & data_wire[491..491] # !(sel_wire[0..0]) & data_wire[483..483]; + l1_w3_n31_mux_dataout = sel_wire[0..0] & data_wire[507..507] # !(sel_wire[0..0]) & data_wire[499..499]; + l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51]; + l1_w3_n4_mux_dataout = sel_wire[0..0] & data_wire[75..75] # !(sel_wire[0..0]) & data_wire[67..67]; + l1_w3_n5_mux_dataout = sel_wire[0..0] & data_wire[91..91] # !(sel_wire[0..0]) & data_wire[83..83]; + l1_w3_n6_mux_dataout = sel_wire[0..0] & data_wire[107..107] # !(sel_wire[0..0]) & data_wire[99..99]; + l1_w3_n7_mux_dataout = sel_wire[0..0] & data_wire[123..123] # !(sel_wire[0..0]) & data_wire[115..115]; + l1_w3_n8_mux_dataout = sel_wire[0..0] & data_wire[139..139] # !(sel_wire[0..0]) & data_wire[131..131]; + l1_w3_n9_mux_dataout = sel_wire[0..0] & data_wire[155..155] # !(sel_wire[0..0]) & data_wire[147..147]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w4_n10_mux_dataout = sel_wire[0..0] & data_wire[172..172] # !(sel_wire[0..0]) & data_wire[164..164]; + l1_w4_n11_mux_dataout = sel_wire[0..0] & data_wire[188..188] # !(sel_wire[0..0]) & data_wire[180..180]; + l1_w4_n12_mux_dataout = sel_wire[0..0] & data_wire[204..204] # !(sel_wire[0..0]) & data_wire[196..196]; + l1_w4_n13_mux_dataout = sel_wire[0..0] & data_wire[220..220] # !(sel_wire[0..0]) & data_wire[212..212]; + l1_w4_n14_mux_dataout = sel_wire[0..0] & data_wire[236..236] # !(sel_wire[0..0]) & data_wire[228..228]; + l1_w4_n15_mux_dataout = sel_wire[0..0] & data_wire[252..252] # !(sel_wire[0..0]) & data_wire[244..244]; + l1_w4_n16_mux_dataout = sel_wire[0..0] & data_wire[268..268] # !(sel_wire[0..0]) & data_wire[260..260]; + l1_w4_n17_mux_dataout = sel_wire[0..0] & data_wire[284..284] # !(sel_wire[0..0]) & data_wire[276..276]; + l1_w4_n18_mux_dataout = sel_wire[0..0] & data_wire[300..300] # !(sel_wire[0..0]) & data_wire[292..292]; + l1_w4_n19_mux_dataout = sel_wire[0..0] & data_wire[316..316] # !(sel_wire[0..0]) & data_wire[308..308]; + l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20]; + l1_w4_n20_mux_dataout = sel_wire[0..0] & data_wire[332..332] # !(sel_wire[0..0]) & data_wire[324..324]; + l1_w4_n21_mux_dataout = sel_wire[0..0] & data_wire[348..348] # !(sel_wire[0..0]) & data_wire[340..340]; + l1_w4_n22_mux_dataout = sel_wire[0..0] & data_wire[364..364] # !(sel_wire[0..0]) & data_wire[356..356]; + l1_w4_n23_mux_dataout = sel_wire[0..0] & data_wire[380..380] # !(sel_wire[0..0]) & data_wire[372..372]; + l1_w4_n24_mux_dataout = sel_wire[0..0] & data_wire[396..396] # !(sel_wire[0..0]) & data_wire[388..388]; + l1_w4_n25_mux_dataout = sel_wire[0..0] & data_wire[412..412] # !(sel_wire[0..0]) & data_wire[404..404]; + l1_w4_n26_mux_dataout = sel_wire[0..0] & data_wire[428..428] # !(sel_wire[0..0]) & data_wire[420..420]; + l1_w4_n27_mux_dataout = sel_wire[0..0] & data_wire[444..444] # !(sel_wire[0..0]) & data_wire[436..436]; + l1_w4_n28_mux_dataout = sel_wire[0..0] & data_wire[460..460] # !(sel_wire[0..0]) & data_wire[452..452]; + l1_w4_n29_mux_dataout = sel_wire[0..0] & data_wire[476..476] # !(sel_wire[0..0]) & data_wire[468..468]; + l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36]; + l1_w4_n30_mux_dataout = sel_wire[0..0] & data_wire[492..492] # !(sel_wire[0..0]) & data_wire[484..484]; + l1_w4_n31_mux_dataout = sel_wire[0..0] & data_wire[508..508] # !(sel_wire[0..0]) & data_wire[500..500]; + l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52]; + l1_w4_n4_mux_dataout = sel_wire[0..0] & data_wire[76..76] # !(sel_wire[0..0]) & data_wire[68..68]; + l1_w4_n5_mux_dataout = sel_wire[0..0] & data_wire[92..92] # !(sel_wire[0..0]) & data_wire[84..84]; + l1_w4_n6_mux_dataout = sel_wire[0..0] & data_wire[108..108] # !(sel_wire[0..0]) & data_wire[100..100]; + l1_w4_n7_mux_dataout = sel_wire[0..0] & data_wire[124..124] # !(sel_wire[0..0]) & data_wire[116..116]; + l1_w4_n8_mux_dataout = sel_wire[0..0] & data_wire[140..140] # !(sel_wire[0..0]) & data_wire[132..132]; + l1_w4_n9_mux_dataout = sel_wire[0..0] & data_wire[156..156] # !(sel_wire[0..0]) & data_wire[148..148]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w5_n10_mux_dataout = sel_wire[0..0] & data_wire[173..173] # !(sel_wire[0..0]) & data_wire[165..165]; + l1_w5_n11_mux_dataout = sel_wire[0..0] & data_wire[189..189] # !(sel_wire[0..0]) & data_wire[181..181]; + l1_w5_n12_mux_dataout = sel_wire[0..0] & data_wire[205..205] # !(sel_wire[0..0]) & data_wire[197..197]; + l1_w5_n13_mux_dataout = sel_wire[0..0] & data_wire[221..221] # !(sel_wire[0..0]) & data_wire[213..213]; + l1_w5_n14_mux_dataout = sel_wire[0..0] & data_wire[237..237] # !(sel_wire[0..0]) & data_wire[229..229]; + l1_w5_n15_mux_dataout = sel_wire[0..0] & data_wire[253..253] # !(sel_wire[0..0]) & data_wire[245..245]; + l1_w5_n16_mux_dataout = sel_wire[0..0] & data_wire[269..269] # !(sel_wire[0..0]) & data_wire[261..261]; + l1_w5_n17_mux_dataout = sel_wire[0..0] & data_wire[285..285] # !(sel_wire[0..0]) & data_wire[277..277]; + l1_w5_n18_mux_dataout = sel_wire[0..0] & data_wire[301..301] # !(sel_wire[0..0]) & data_wire[293..293]; + l1_w5_n19_mux_dataout = sel_wire[0..0] & data_wire[317..317] # !(sel_wire[0..0]) & data_wire[309..309]; + l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21]; + l1_w5_n20_mux_dataout = sel_wire[0..0] & data_wire[333..333] # !(sel_wire[0..0]) & data_wire[325..325]; + l1_w5_n21_mux_dataout = sel_wire[0..0] & data_wire[349..349] # !(sel_wire[0..0]) & data_wire[341..341]; + l1_w5_n22_mux_dataout = sel_wire[0..0] & data_wire[365..365] # !(sel_wire[0..0]) & data_wire[357..357]; + l1_w5_n23_mux_dataout = sel_wire[0..0] & data_wire[381..381] # !(sel_wire[0..0]) & data_wire[373..373]; + l1_w5_n24_mux_dataout = sel_wire[0..0] & data_wire[397..397] # !(sel_wire[0..0]) & data_wire[389..389]; + l1_w5_n25_mux_dataout = sel_wire[0..0] & data_wire[413..413] # !(sel_wire[0..0]) & data_wire[405..405]; + l1_w5_n26_mux_dataout = sel_wire[0..0] & data_wire[429..429] # !(sel_wire[0..0]) & data_wire[421..421]; + l1_w5_n27_mux_dataout = sel_wire[0..0] & data_wire[445..445] # !(sel_wire[0..0]) & data_wire[437..437]; + l1_w5_n28_mux_dataout = sel_wire[0..0] & data_wire[461..461] # !(sel_wire[0..0]) & data_wire[453..453]; + l1_w5_n29_mux_dataout = sel_wire[0..0] & data_wire[477..477] # !(sel_wire[0..0]) & data_wire[469..469]; + l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37]; + l1_w5_n30_mux_dataout = sel_wire[0..0] & data_wire[493..493] # !(sel_wire[0..0]) & data_wire[485..485]; + l1_w5_n31_mux_dataout = sel_wire[0..0] & data_wire[509..509] # !(sel_wire[0..0]) & data_wire[501..501]; + l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53]; + l1_w5_n4_mux_dataout = sel_wire[0..0] & data_wire[77..77] # !(sel_wire[0..0]) & data_wire[69..69]; + l1_w5_n5_mux_dataout = sel_wire[0..0] & data_wire[93..93] # !(sel_wire[0..0]) & data_wire[85..85]; + l1_w5_n6_mux_dataout = sel_wire[0..0] & data_wire[109..109] # !(sel_wire[0..0]) & data_wire[101..101]; + l1_w5_n7_mux_dataout = sel_wire[0..0] & data_wire[125..125] # !(sel_wire[0..0]) & data_wire[117..117]; + l1_w5_n8_mux_dataout = sel_wire[0..0] & data_wire[141..141] # !(sel_wire[0..0]) & data_wire[133..133]; + l1_w5_n9_mux_dataout = sel_wire[0..0] & data_wire[157..157] # !(sel_wire[0..0]) & data_wire[149..149]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w6_n10_mux_dataout = sel_wire[0..0] & data_wire[174..174] # !(sel_wire[0..0]) & data_wire[166..166]; + l1_w6_n11_mux_dataout = sel_wire[0..0] & data_wire[190..190] # !(sel_wire[0..0]) & data_wire[182..182]; + l1_w6_n12_mux_dataout = sel_wire[0..0] & data_wire[206..206] # !(sel_wire[0..0]) & data_wire[198..198]; + l1_w6_n13_mux_dataout = sel_wire[0..0] & data_wire[222..222] # !(sel_wire[0..0]) & data_wire[214..214]; + l1_w6_n14_mux_dataout = sel_wire[0..0] & data_wire[238..238] # !(sel_wire[0..0]) & data_wire[230..230]; + l1_w6_n15_mux_dataout = sel_wire[0..0] & data_wire[254..254] # !(sel_wire[0..0]) & data_wire[246..246]; + l1_w6_n16_mux_dataout = sel_wire[0..0] & data_wire[270..270] # !(sel_wire[0..0]) & data_wire[262..262]; + l1_w6_n17_mux_dataout = sel_wire[0..0] & data_wire[286..286] # !(sel_wire[0..0]) & data_wire[278..278]; + l1_w6_n18_mux_dataout = sel_wire[0..0] & data_wire[302..302] # !(sel_wire[0..0]) & data_wire[294..294]; + l1_w6_n19_mux_dataout = sel_wire[0..0] & data_wire[318..318] # !(sel_wire[0..0]) & data_wire[310..310]; + l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22]; + l1_w6_n20_mux_dataout = sel_wire[0..0] & data_wire[334..334] # !(sel_wire[0..0]) & data_wire[326..326]; + l1_w6_n21_mux_dataout = sel_wire[0..0] & data_wire[350..350] # !(sel_wire[0..0]) & data_wire[342..342]; + l1_w6_n22_mux_dataout = sel_wire[0..0] & data_wire[366..366] # !(sel_wire[0..0]) & data_wire[358..358]; + l1_w6_n23_mux_dataout = sel_wire[0..0] & data_wire[382..382] # !(sel_wire[0..0]) & data_wire[374..374]; + l1_w6_n24_mux_dataout = sel_wire[0..0] & data_wire[398..398] # !(sel_wire[0..0]) & data_wire[390..390]; + l1_w6_n25_mux_dataout = sel_wire[0..0] & data_wire[414..414] # !(sel_wire[0..0]) & data_wire[406..406]; + l1_w6_n26_mux_dataout = sel_wire[0..0] & data_wire[430..430] # !(sel_wire[0..0]) & data_wire[422..422]; + l1_w6_n27_mux_dataout = sel_wire[0..0] & data_wire[446..446] # !(sel_wire[0..0]) & data_wire[438..438]; + l1_w6_n28_mux_dataout = sel_wire[0..0] & data_wire[462..462] # !(sel_wire[0..0]) & data_wire[454..454]; + l1_w6_n29_mux_dataout = sel_wire[0..0] & data_wire[478..478] # !(sel_wire[0..0]) & data_wire[470..470]; + l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38]; + l1_w6_n30_mux_dataout = sel_wire[0..0] & data_wire[494..494] # !(sel_wire[0..0]) & data_wire[486..486]; + l1_w6_n31_mux_dataout = sel_wire[0..0] & data_wire[510..510] # !(sel_wire[0..0]) & data_wire[502..502]; + l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54]; + l1_w6_n4_mux_dataout = sel_wire[0..0] & data_wire[78..78] # !(sel_wire[0..0]) & data_wire[70..70]; + l1_w6_n5_mux_dataout = sel_wire[0..0] & data_wire[94..94] # !(sel_wire[0..0]) & data_wire[86..86]; + l1_w6_n6_mux_dataout = sel_wire[0..0] & data_wire[110..110] # !(sel_wire[0..0]) & data_wire[102..102]; + l1_w6_n7_mux_dataout = sel_wire[0..0] & data_wire[126..126] # !(sel_wire[0..0]) & data_wire[118..118]; + l1_w6_n8_mux_dataout = sel_wire[0..0] & data_wire[142..142] # !(sel_wire[0..0]) & data_wire[134..134]; + l1_w6_n9_mux_dataout = sel_wire[0..0] & data_wire[158..158] # !(sel_wire[0..0]) & data_wire[150..150]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + l1_w7_n10_mux_dataout = sel_wire[0..0] & data_wire[175..175] # !(sel_wire[0..0]) & data_wire[167..167]; + l1_w7_n11_mux_dataout = sel_wire[0..0] & data_wire[191..191] # !(sel_wire[0..0]) & data_wire[183..183]; + l1_w7_n12_mux_dataout = sel_wire[0..0] & data_wire[207..207] # !(sel_wire[0..0]) & data_wire[199..199]; + l1_w7_n13_mux_dataout = sel_wire[0..0] & data_wire[223..223] # !(sel_wire[0..0]) & data_wire[215..215]; + l1_w7_n14_mux_dataout = sel_wire[0..0] & data_wire[239..239] # !(sel_wire[0..0]) & data_wire[231..231]; + l1_w7_n15_mux_dataout = sel_wire[0..0] & data_wire[255..255] # !(sel_wire[0..0]) & data_wire[247..247]; + l1_w7_n16_mux_dataout = sel_wire[0..0] & data_wire[271..271] # !(sel_wire[0..0]) & data_wire[263..263]; + l1_w7_n17_mux_dataout = sel_wire[0..0] & data_wire[287..287] # !(sel_wire[0..0]) & data_wire[279..279]; + l1_w7_n18_mux_dataout = sel_wire[0..0] & data_wire[303..303] # !(sel_wire[0..0]) & data_wire[295..295]; + l1_w7_n19_mux_dataout = sel_wire[0..0] & data_wire[319..319] # !(sel_wire[0..0]) & data_wire[311..311]; + l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23]; + l1_w7_n20_mux_dataout = sel_wire[0..0] & data_wire[335..335] # !(sel_wire[0..0]) & data_wire[327..327]; + l1_w7_n21_mux_dataout = sel_wire[0..0] & data_wire[351..351] # !(sel_wire[0..0]) & data_wire[343..343]; + l1_w7_n22_mux_dataout = sel_wire[0..0] & data_wire[367..367] # !(sel_wire[0..0]) & data_wire[359..359]; + l1_w7_n23_mux_dataout = sel_wire[0..0] & data_wire[383..383] # !(sel_wire[0..0]) & data_wire[375..375]; + l1_w7_n24_mux_dataout = sel_wire[0..0] & data_wire[399..399] # !(sel_wire[0..0]) & data_wire[391..391]; + l1_w7_n25_mux_dataout = sel_wire[0..0] & data_wire[415..415] # !(sel_wire[0..0]) & data_wire[407..407]; + l1_w7_n26_mux_dataout = sel_wire[0..0] & data_wire[431..431] # !(sel_wire[0..0]) & data_wire[423..423]; + l1_w7_n27_mux_dataout = sel_wire[0..0] & data_wire[447..447] # !(sel_wire[0..0]) & data_wire[439..439]; + l1_w7_n28_mux_dataout = sel_wire[0..0] & data_wire[463..463] # !(sel_wire[0..0]) & data_wire[455..455]; + l1_w7_n29_mux_dataout = sel_wire[0..0] & data_wire[479..479] # !(sel_wire[0..0]) & data_wire[471..471]; + l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39]; + l1_w7_n30_mux_dataout = sel_wire[0..0] & data_wire[495..495] # !(sel_wire[0..0]) & data_wire[487..487]; + l1_w7_n31_mux_dataout = sel_wire[0..0] & data_wire[511..511] # !(sel_wire[0..0]) & data_wire[503..503]; + l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55]; + l1_w7_n4_mux_dataout = sel_wire[0..0] & data_wire[79..79] # !(sel_wire[0..0]) & data_wire[71..71]; + l1_w7_n5_mux_dataout = sel_wire[0..0] & data_wire[95..95] # !(sel_wire[0..0]) & data_wire[87..87]; + l1_w7_n6_mux_dataout = sel_wire[0..0] & data_wire[111..111] # !(sel_wire[0..0]) & data_wire[103..103]; + l1_w7_n7_mux_dataout = sel_wire[0..0] & data_wire[127..127] # !(sel_wire[0..0]) & data_wire[119..119]; + l1_w7_n8_mux_dataout = sel_wire[0..0] & data_wire[143..143] # !(sel_wire[0..0]) & data_wire[135..135]; + l1_w7_n9_mux_dataout = sel_wire[0..0] & data_wire[159..159] # !(sel_wire[0..0]) & data_wire[151..151]; + l2_w0_n0_mux_dataout = sel_wire[7..7] & data_wire[513..513] # !(sel_wire[7..7]) & data_wire[512..512]; + l2_w0_n10_mux_dataout = sel_wire[7..7] & data_wire[533..533] # !(sel_wire[7..7]) & data_wire[532..532]; + l2_w0_n11_mux_dataout = sel_wire[7..7] & data_wire[535..535] # !(sel_wire[7..7]) & data_wire[534..534]; + l2_w0_n12_mux_dataout = sel_wire[7..7] & data_wire[537..537] # !(sel_wire[7..7]) & data_wire[536..536]; + l2_w0_n13_mux_dataout = sel_wire[7..7] & data_wire[539..539] # !(sel_wire[7..7]) & data_wire[538..538]; + l2_w0_n14_mux_dataout = sel_wire[7..7] & data_wire[541..541] # !(sel_wire[7..7]) & data_wire[540..540]; + l2_w0_n15_mux_dataout = sel_wire[7..7] & data_wire[543..543] # !(sel_wire[7..7]) & data_wire[542..542]; + l2_w0_n1_mux_dataout = sel_wire[7..7] & data_wire[515..515] # !(sel_wire[7..7]) & data_wire[514..514]; + l2_w0_n2_mux_dataout = sel_wire[7..7] & data_wire[517..517] # !(sel_wire[7..7]) & data_wire[516..516]; + l2_w0_n3_mux_dataout = sel_wire[7..7] & data_wire[519..519] # !(sel_wire[7..7]) & data_wire[518..518]; + l2_w0_n4_mux_dataout = sel_wire[7..7] & data_wire[521..521] # !(sel_wire[7..7]) & data_wire[520..520]; + l2_w0_n5_mux_dataout = sel_wire[7..7] & data_wire[523..523] # !(sel_wire[7..7]) & data_wire[522..522]; + l2_w0_n6_mux_dataout = sel_wire[7..7] & data_wire[525..525] # !(sel_wire[7..7]) & data_wire[524..524]; + l2_w0_n7_mux_dataout = sel_wire[7..7] & data_wire[527..527] # !(sel_wire[7..7]) & data_wire[526..526]; + l2_w0_n8_mux_dataout = sel_wire[7..7] & data_wire[529..529] # !(sel_wire[7..7]) & data_wire[528..528]; + l2_w0_n9_mux_dataout = sel_wire[7..7] & data_wire[531..531] # !(sel_wire[7..7]) & data_wire[530..530]; + l2_w1_n0_mux_dataout = sel_wire[7..7] & data_wire[545..545] # !(sel_wire[7..7]) & data_wire[544..544]; + l2_w1_n10_mux_dataout = sel_wire[7..7] & data_wire[565..565] # !(sel_wire[7..7]) & data_wire[564..564]; + l2_w1_n11_mux_dataout = sel_wire[7..7] & data_wire[567..567] # !(sel_wire[7..7]) & data_wire[566..566]; + l2_w1_n12_mux_dataout = sel_wire[7..7] & data_wire[569..569] # !(sel_wire[7..7]) & data_wire[568..568]; + l2_w1_n13_mux_dataout = sel_wire[7..7] & data_wire[571..571] # !(sel_wire[7..7]) & data_wire[570..570]; + l2_w1_n14_mux_dataout = sel_wire[7..7] & data_wire[573..573] # !(sel_wire[7..7]) & data_wire[572..572]; + l2_w1_n15_mux_dataout = sel_wire[7..7] & data_wire[575..575] # !(sel_wire[7..7]) & data_wire[574..574]; + l2_w1_n1_mux_dataout = sel_wire[7..7] & data_wire[547..547] # !(sel_wire[7..7]) & data_wire[546..546]; + l2_w1_n2_mux_dataout = sel_wire[7..7] & data_wire[549..549] # !(sel_wire[7..7]) & data_wire[548..548]; + l2_w1_n3_mux_dataout = sel_wire[7..7] & data_wire[551..551] # !(sel_wire[7..7]) & data_wire[550..550]; + l2_w1_n4_mux_dataout = sel_wire[7..7] & data_wire[553..553] # !(sel_wire[7..7]) & data_wire[552..552]; + l2_w1_n5_mux_dataout = sel_wire[7..7] & data_wire[555..555] # !(sel_wire[7..7]) & data_wire[554..554]; + l2_w1_n6_mux_dataout = sel_wire[7..7] & data_wire[557..557] # !(sel_wire[7..7]) & data_wire[556..556]; + l2_w1_n7_mux_dataout = sel_wire[7..7] & data_wire[559..559] # !(sel_wire[7..7]) & data_wire[558..558]; + l2_w1_n8_mux_dataout = sel_wire[7..7] & data_wire[561..561] # !(sel_wire[7..7]) & data_wire[560..560]; + l2_w1_n9_mux_dataout = sel_wire[7..7] & data_wire[563..563] # !(sel_wire[7..7]) & data_wire[562..562]; + l2_w2_n0_mux_dataout = sel_wire[7..7] & data_wire[577..577] # !(sel_wire[7..7]) & data_wire[576..576]; + l2_w2_n10_mux_dataout = sel_wire[7..7] & data_wire[597..597] # !(sel_wire[7..7]) & data_wire[596..596]; + l2_w2_n11_mux_dataout = sel_wire[7..7] & data_wire[599..599] # !(sel_wire[7..7]) & data_wire[598..598]; + l2_w2_n12_mux_dataout = sel_wire[7..7] & data_wire[601..601] # !(sel_wire[7..7]) & data_wire[600..600]; + l2_w2_n13_mux_dataout = sel_wire[7..7] & data_wire[603..603] # !(sel_wire[7..7]) & data_wire[602..602]; + l2_w2_n14_mux_dataout = sel_wire[7..7] & data_wire[605..605] # !(sel_wire[7..7]) & data_wire[604..604]; + l2_w2_n15_mux_dataout = sel_wire[7..7] & data_wire[607..607] # !(sel_wire[7..7]) & data_wire[606..606]; + l2_w2_n1_mux_dataout = sel_wire[7..7] & data_wire[579..579] # !(sel_wire[7..7]) & data_wire[578..578]; + l2_w2_n2_mux_dataout = sel_wire[7..7] & data_wire[581..581] # !(sel_wire[7..7]) & data_wire[580..580]; + l2_w2_n3_mux_dataout = sel_wire[7..7] & data_wire[583..583] # !(sel_wire[7..7]) & data_wire[582..582]; + l2_w2_n4_mux_dataout = sel_wire[7..7] & data_wire[585..585] # !(sel_wire[7..7]) & data_wire[584..584]; + l2_w2_n5_mux_dataout = sel_wire[7..7] & data_wire[587..587] # !(sel_wire[7..7]) & data_wire[586..586]; + l2_w2_n6_mux_dataout = sel_wire[7..7] & data_wire[589..589] # !(sel_wire[7..7]) & data_wire[588..588]; + l2_w2_n7_mux_dataout = sel_wire[7..7] & data_wire[591..591] # !(sel_wire[7..7]) & data_wire[590..590]; + l2_w2_n8_mux_dataout = sel_wire[7..7] & data_wire[593..593] # !(sel_wire[7..7]) & data_wire[592..592]; + l2_w2_n9_mux_dataout = sel_wire[7..7] & data_wire[595..595] # !(sel_wire[7..7]) & data_wire[594..594]; + l2_w3_n0_mux_dataout = sel_wire[7..7] & data_wire[609..609] # !(sel_wire[7..7]) & data_wire[608..608]; + l2_w3_n10_mux_dataout = sel_wire[7..7] & data_wire[629..629] # !(sel_wire[7..7]) & data_wire[628..628]; + l2_w3_n11_mux_dataout = sel_wire[7..7] & data_wire[631..631] # !(sel_wire[7..7]) & data_wire[630..630]; + l2_w3_n12_mux_dataout = sel_wire[7..7] & data_wire[633..633] # !(sel_wire[7..7]) & data_wire[632..632]; + l2_w3_n13_mux_dataout = sel_wire[7..7] & data_wire[635..635] # !(sel_wire[7..7]) & data_wire[634..634]; + l2_w3_n14_mux_dataout = sel_wire[7..7] & data_wire[637..637] # !(sel_wire[7..7]) & data_wire[636..636]; + l2_w3_n15_mux_dataout = sel_wire[7..7] & data_wire[639..639] # !(sel_wire[7..7]) & data_wire[638..638]; + l2_w3_n1_mux_dataout = sel_wire[7..7] & data_wire[611..611] # !(sel_wire[7..7]) & data_wire[610..610]; + l2_w3_n2_mux_dataout = sel_wire[7..7] & data_wire[613..613] # !(sel_wire[7..7]) & data_wire[612..612]; + l2_w3_n3_mux_dataout = sel_wire[7..7] & data_wire[615..615] # !(sel_wire[7..7]) & data_wire[614..614]; + l2_w3_n4_mux_dataout = sel_wire[7..7] & data_wire[617..617] # !(sel_wire[7..7]) & data_wire[616..616]; + l2_w3_n5_mux_dataout = sel_wire[7..7] & data_wire[619..619] # !(sel_wire[7..7]) & data_wire[618..618]; + l2_w3_n6_mux_dataout = sel_wire[7..7] & data_wire[621..621] # !(sel_wire[7..7]) & data_wire[620..620]; + l2_w3_n7_mux_dataout = sel_wire[7..7] & data_wire[623..623] # !(sel_wire[7..7]) & data_wire[622..622]; + l2_w3_n8_mux_dataout = sel_wire[7..7] & data_wire[625..625] # !(sel_wire[7..7]) & data_wire[624..624]; + l2_w3_n9_mux_dataout = sel_wire[7..7] & data_wire[627..627] # !(sel_wire[7..7]) & data_wire[626..626]; + l2_w4_n0_mux_dataout = sel_wire[7..7] & data_wire[641..641] # !(sel_wire[7..7]) & data_wire[640..640]; + l2_w4_n10_mux_dataout = sel_wire[7..7] & data_wire[661..661] # !(sel_wire[7..7]) & data_wire[660..660]; + l2_w4_n11_mux_dataout = sel_wire[7..7] & data_wire[663..663] # !(sel_wire[7..7]) & data_wire[662..662]; + l2_w4_n12_mux_dataout = sel_wire[7..7] & data_wire[665..665] # !(sel_wire[7..7]) & data_wire[664..664]; + l2_w4_n13_mux_dataout = sel_wire[7..7] & data_wire[667..667] # !(sel_wire[7..7]) & data_wire[666..666]; + l2_w4_n14_mux_dataout = sel_wire[7..7] & data_wire[669..669] # !(sel_wire[7..7]) & data_wire[668..668]; + l2_w4_n15_mux_dataout = sel_wire[7..7] & data_wire[671..671] # !(sel_wire[7..7]) & data_wire[670..670]; + l2_w4_n1_mux_dataout = sel_wire[7..7] & data_wire[643..643] # !(sel_wire[7..7]) & data_wire[642..642]; + l2_w4_n2_mux_dataout = sel_wire[7..7] & data_wire[645..645] # !(sel_wire[7..7]) & data_wire[644..644]; + l2_w4_n3_mux_dataout = sel_wire[7..7] & data_wire[647..647] # !(sel_wire[7..7]) & data_wire[646..646]; + l2_w4_n4_mux_dataout = sel_wire[7..7] & data_wire[649..649] # !(sel_wire[7..7]) & data_wire[648..648]; + l2_w4_n5_mux_dataout = sel_wire[7..7] & data_wire[651..651] # !(sel_wire[7..7]) & data_wire[650..650]; + l2_w4_n6_mux_dataout = sel_wire[7..7] & data_wire[653..653] # !(sel_wire[7..7]) & data_wire[652..652]; + l2_w4_n7_mux_dataout = sel_wire[7..7] & data_wire[655..655] # !(sel_wire[7..7]) & data_wire[654..654]; + l2_w4_n8_mux_dataout = sel_wire[7..7] & data_wire[657..657] # !(sel_wire[7..7]) & data_wire[656..656]; + l2_w4_n9_mux_dataout = sel_wire[7..7] & data_wire[659..659] # !(sel_wire[7..7]) & data_wire[658..658]; + l2_w5_n0_mux_dataout = sel_wire[7..7] & data_wire[673..673] # !(sel_wire[7..7]) & data_wire[672..672]; + l2_w5_n10_mux_dataout = sel_wire[7..7] & data_wire[693..693] # !(sel_wire[7..7]) & data_wire[692..692]; + l2_w5_n11_mux_dataout = sel_wire[7..7] & data_wire[695..695] # !(sel_wire[7..7]) & data_wire[694..694]; + l2_w5_n12_mux_dataout = sel_wire[7..7] & data_wire[697..697] # !(sel_wire[7..7]) & data_wire[696..696]; + l2_w5_n13_mux_dataout = sel_wire[7..7] & data_wire[699..699] # !(sel_wire[7..7]) & data_wire[698..698]; + l2_w5_n14_mux_dataout = sel_wire[7..7] & data_wire[701..701] # !(sel_wire[7..7]) & data_wire[700..700]; + l2_w5_n15_mux_dataout = sel_wire[7..7] & data_wire[703..703] # !(sel_wire[7..7]) & data_wire[702..702]; + l2_w5_n1_mux_dataout = sel_wire[7..7] & data_wire[675..675] # !(sel_wire[7..7]) & data_wire[674..674]; + l2_w5_n2_mux_dataout = sel_wire[7..7] & data_wire[677..677] # !(sel_wire[7..7]) & data_wire[676..676]; + l2_w5_n3_mux_dataout = sel_wire[7..7] & data_wire[679..679] # !(sel_wire[7..7]) & data_wire[678..678]; + l2_w5_n4_mux_dataout = sel_wire[7..7] & data_wire[681..681] # !(sel_wire[7..7]) & data_wire[680..680]; + l2_w5_n5_mux_dataout = sel_wire[7..7] & data_wire[683..683] # !(sel_wire[7..7]) & data_wire[682..682]; + l2_w5_n6_mux_dataout = sel_wire[7..7] & data_wire[685..685] # !(sel_wire[7..7]) & data_wire[684..684]; + l2_w5_n7_mux_dataout = sel_wire[7..7] & data_wire[687..687] # !(sel_wire[7..7]) & data_wire[686..686]; + l2_w5_n8_mux_dataout = sel_wire[7..7] & data_wire[689..689] # !(sel_wire[7..7]) & data_wire[688..688]; + l2_w5_n9_mux_dataout = sel_wire[7..7] & data_wire[691..691] # !(sel_wire[7..7]) & data_wire[690..690]; + l2_w6_n0_mux_dataout = sel_wire[7..7] & data_wire[705..705] # !(sel_wire[7..7]) & data_wire[704..704]; + l2_w6_n10_mux_dataout = sel_wire[7..7] & data_wire[725..725] # !(sel_wire[7..7]) & data_wire[724..724]; + l2_w6_n11_mux_dataout = sel_wire[7..7] & data_wire[727..727] # !(sel_wire[7..7]) & data_wire[726..726]; + l2_w6_n12_mux_dataout = sel_wire[7..7] & data_wire[729..729] # !(sel_wire[7..7]) & data_wire[728..728]; + l2_w6_n13_mux_dataout = sel_wire[7..7] & data_wire[731..731] # !(sel_wire[7..7]) & data_wire[730..730]; + l2_w6_n14_mux_dataout = sel_wire[7..7] & data_wire[733..733] # !(sel_wire[7..7]) & data_wire[732..732]; + l2_w6_n15_mux_dataout = sel_wire[7..7] & data_wire[735..735] # !(sel_wire[7..7]) & data_wire[734..734]; + l2_w6_n1_mux_dataout = sel_wire[7..7] & data_wire[707..707] # !(sel_wire[7..7]) & data_wire[706..706]; + l2_w6_n2_mux_dataout = sel_wire[7..7] & data_wire[709..709] # !(sel_wire[7..7]) & data_wire[708..708]; + l2_w6_n3_mux_dataout = sel_wire[7..7] & data_wire[711..711] # !(sel_wire[7..7]) & data_wire[710..710]; + l2_w6_n4_mux_dataout = sel_wire[7..7] & data_wire[713..713] # !(sel_wire[7..7]) & data_wire[712..712]; + l2_w6_n5_mux_dataout = sel_wire[7..7] & data_wire[715..715] # !(sel_wire[7..7]) & data_wire[714..714]; + l2_w6_n6_mux_dataout = sel_wire[7..7] & data_wire[717..717] # !(sel_wire[7..7]) & data_wire[716..716]; + l2_w6_n7_mux_dataout = sel_wire[7..7] & data_wire[719..719] # !(sel_wire[7..7]) & data_wire[718..718]; + l2_w6_n8_mux_dataout = sel_wire[7..7] & data_wire[721..721] # !(sel_wire[7..7]) & data_wire[720..720]; + l2_w6_n9_mux_dataout = sel_wire[7..7] & data_wire[723..723] # !(sel_wire[7..7]) & data_wire[722..722]; + l2_w7_n0_mux_dataout = sel_wire[7..7] & data_wire[737..737] # !(sel_wire[7..7]) & data_wire[736..736]; + l2_w7_n10_mux_dataout = sel_wire[7..7] & data_wire[757..757] # !(sel_wire[7..7]) & data_wire[756..756]; + l2_w7_n11_mux_dataout = sel_wire[7..7] & data_wire[759..759] # !(sel_wire[7..7]) & data_wire[758..758]; + l2_w7_n12_mux_dataout = sel_wire[7..7] & data_wire[761..761] # !(sel_wire[7..7]) & data_wire[760..760]; + l2_w7_n13_mux_dataout = sel_wire[7..7] & data_wire[763..763] # !(sel_wire[7..7]) & data_wire[762..762]; + l2_w7_n14_mux_dataout = sel_wire[7..7] & data_wire[765..765] # !(sel_wire[7..7]) & data_wire[764..764]; + l2_w7_n15_mux_dataout = sel_wire[7..7] & data_wire[767..767] # !(sel_wire[7..7]) & data_wire[766..766]; + l2_w7_n1_mux_dataout = sel_wire[7..7] & data_wire[739..739] # !(sel_wire[7..7]) & data_wire[738..738]; + l2_w7_n2_mux_dataout = sel_wire[7..7] & data_wire[741..741] # !(sel_wire[7..7]) & data_wire[740..740]; + l2_w7_n3_mux_dataout = sel_wire[7..7] & data_wire[743..743] # !(sel_wire[7..7]) & data_wire[742..742]; + l2_w7_n4_mux_dataout = sel_wire[7..7] & data_wire[745..745] # !(sel_wire[7..7]) & data_wire[744..744]; + l2_w7_n5_mux_dataout = sel_wire[7..7] & data_wire[747..747] # !(sel_wire[7..7]) & data_wire[746..746]; + l2_w7_n6_mux_dataout = sel_wire[7..7] & data_wire[749..749] # !(sel_wire[7..7]) & data_wire[748..748]; + l2_w7_n7_mux_dataout = sel_wire[7..7] & data_wire[751..751] # !(sel_wire[7..7]) & data_wire[750..750]; + l2_w7_n8_mux_dataout = sel_wire[7..7] & data_wire[753..753] # !(sel_wire[7..7]) & data_wire[752..752]; + l2_w7_n9_mux_dataout = sel_wire[7..7] & data_wire[755..755] # !(sel_wire[7..7]) & data_wire[754..754]; + l3_w0_n0_mux_dataout = sel_wire[14..14] & data_wire[769..769] # !(sel_wire[14..14]) & data_wire[768..768]; + l3_w0_n1_mux_dataout = sel_wire[14..14] & data_wire[771..771] # !(sel_wire[14..14]) & data_wire[770..770]; + l3_w0_n2_mux_dataout = sel_wire[14..14] & data_wire[773..773] # !(sel_wire[14..14]) & data_wire[772..772]; + l3_w0_n3_mux_dataout = sel_wire[14..14] & data_wire[775..775] # !(sel_wire[14..14]) & data_wire[774..774]; + l3_w0_n4_mux_dataout = sel_wire[14..14] & data_wire[777..777] # !(sel_wire[14..14]) & data_wire[776..776]; + l3_w0_n5_mux_dataout = sel_wire[14..14] & data_wire[779..779] # !(sel_wire[14..14]) & data_wire[778..778]; + l3_w0_n6_mux_dataout = sel_wire[14..14] & data_wire[781..781] # !(sel_wire[14..14]) & data_wire[780..780]; + l3_w0_n7_mux_dataout = sel_wire[14..14] & data_wire[783..783] # !(sel_wire[14..14]) & data_wire[782..782]; + l3_w1_n0_mux_dataout = sel_wire[14..14] & data_wire[785..785] # !(sel_wire[14..14]) & data_wire[784..784]; + l3_w1_n1_mux_dataout = sel_wire[14..14] & data_wire[787..787] # !(sel_wire[14..14]) & data_wire[786..786]; + l3_w1_n2_mux_dataout = sel_wire[14..14] & data_wire[789..789] # !(sel_wire[14..14]) & data_wire[788..788]; + l3_w1_n3_mux_dataout = sel_wire[14..14] & data_wire[791..791] # !(sel_wire[14..14]) & data_wire[790..790]; + l3_w1_n4_mux_dataout = sel_wire[14..14] & data_wire[793..793] # !(sel_wire[14..14]) & data_wire[792..792]; + l3_w1_n5_mux_dataout = sel_wire[14..14] & data_wire[795..795] # !(sel_wire[14..14]) & data_wire[794..794]; + l3_w1_n6_mux_dataout = sel_wire[14..14] & data_wire[797..797] # !(sel_wire[14..14]) & data_wire[796..796]; + l3_w1_n7_mux_dataout = sel_wire[14..14] & data_wire[799..799] # !(sel_wire[14..14]) & data_wire[798..798]; + l3_w2_n0_mux_dataout = sel_wire[14..14] & data_wire[801..801] # !(sel_wire[14..14]) & data_wire[800..800]; + l3_w2_n1_mux_dataout = sel_wire[14..14] & data_wire[803..803] # !(sel_wire[14..14]) & data_wire[802..802]; + l3_w2_n2_mux_dataout = sel_wire[14..14] & data_wire[805..805] # !(sel_wire[14..14]) & data_wire[804..804]; + l3_w2_n3_mux_dataout = sel_wire[14..14] & data_wire[807..807] # !(sel_wire[14..14]) & data_wire[806..806]; + l3_w2_n4_mux_dataout = sel_wire[14..14] & data_wire[809..809] # !(sel_wire[14..14]) & data_wire[808..808]; + l3_w2_n5_mux_dataout = sel_wire[14..14] & data_wire[811..811] # !(sel_wire[14..14]) & data_wire[810..810]; + l3_w2_n6_mux_dataout = sel_wire[14..14] & data_wire[813..813] # !(sel_wire[14..14]) & data_wire[812..812]; + l3_w2_n7_mux_dataout = sel_wire[14..14] & data_wire[815..815] # !(sel_wire[14..14]) & data_wire[814..814]; + l3_w3_n0_mux_dataout = sel_wire[14..14] & data_wire[817..817] # !(sel_wire[14..14]) & data_wire[816..816]; + l3_w3_n1_mux_dataout = sel_wire[14..14] & data_wire[819..819] # !(sel_wire[14..14]) & data_wire[818..818]; + l3_w3_n2_mux_dataout = sel_wire[14..14] & data_wire[821..821] # !(sel_wire[14..14]) & data_wire[820..820]; + l3_w3_n3_mux_dataout = sel_wire[14..14] & data_wire[823..823] # !(sel_wire[14..14]) & data_wire[822..822]; + l3_w3_n4_mux_dataout = sel_wire[14..14] & data_wire[825..825] # !(sel_wire[14..14]) & data_wire[824..824]; + l3_w3_n5_mux_dataout = sel_wire[14..14] & data_wire[827..827] # !(sel_wire[14..14]) & data_wire[826..826]; + l3_w3_n6_mux_dataout = sel_wire[14..14] & data_wire[829..829] # !(sel_wire[14..14]) & data_wire[828..828]; + l3_w3_n7_mux_dataout = sel_wire[14..14] & data_wire[831..831] # !(sel_wire[14..14]) & data_wire[830..830]; + l3_w4_n0_mux_dataout = sel_wire[14..14] & data_wire[833..833] # !(sel_wire[14..14]) & data_wire[832..832]; + l3_w4_n1_mux_dataout = sel_wire[14..14] & data_wire[835..835] # !(sel_wire[14..14]) & data_wire[834..834]; + l3_w4_n2_mux_dataout = sel_wire[14..14] & data_wire[837..837] # !(sel_wire[14..14]) & data_wire[836..836]; + l3_w4_n3_mux_dataout = sel_wire[14..14] & data_wire[839..839] # !(sel_wire[14..14]) & data_wire[838..838]; + l3_w4_n4_mux_dataout = sel_wire[14..14] & data_wire[841..841] # !(sel_wire[14..14]) & data_wire[840..840]; + l3_w4_n5_mux_dataout = sel_wire[14..14] & data_wire[843..843] # !(sel_wire[14..14]) & data_wire[842..842]; + l3_w4_n6_mux_dataout = sel_wire[14..14] & data_wire[845..845] # !(sel_wire[14..14]) & data_wire[844..844]; + l3_w4_n7_mux_dataout = sel_wire[14..14] & data_wire[847..847] # !(sel_wire[14..14]) & data_wire[846..846]; + l3_w5_n0_mux_dataout = sel_wire[14..14] & data_wire[849..849] # !(sel_wire[14..14]) & data_wire[848..848]; + l3_w5_n1_mux_dataout = sel_wire[14..14] & data_wire[851..851] # !(sel_wire[14..14]) & data_wire[850..850]; + l3_w5_n2_mux_dataout = sel_wire[14..14] & data_wire[853..853] # !(sel_wire[14..14]) & data_wire[852..852]; + l3_w5_n3_mux_dataout = sel_wire[14..14] & data_wire[855..855] # !(sel_wire[14..14]) & data_wire[854..854]; + l3_w5_n4_mux_dataout = sel_wire[14..14] & data_wire[857..857] # !(sel_wire[14..14]) & data_wire[856..856]; + l3_w5_n5_mux_dataout = sel_wire[14..14] & data_wire[859..859] # !(sel_wire[14..14]) & data_wire[858..858]; + l3_w5_n6_mux_dataout = sel_wire[14..14] & data_wire[861..861] # !(sel_wire[14..14]) & data_wire[860..860]; + l3_w5_n7_mux_dataout = sel_wire[14..14] & data_wire[863..863] # !(sel_wire[14..14]) & data_wire[862..862]; + l3_w6_n0_mux_dataout = sel_wire[14..14] & data_wire[865..865] # !(sel_wire[14..14]) & data_wire[864..864]; + l3_w6_n1_mux_dataout = sel_wire[14..14] & data_wire[867..867] # !(sel_wire[14..14]) & data_wire[866..866]; + l3_w6_n2_mux_dataout = sel_wire[14..14] & data_wire[869..869] # !(sel_wire[14..14]) & data_wire[868..868]; + l3_w6_n3_mux_dataout = sel_wire[14..14] & data_wire[871..871] # !(sel_wire[14..14]) & data_wire[870..870]; + l3_w6_n4_mux_dataout = sel_wire[14..14] & data_wire[873..873] # !(sel_wire[14..14]) & data_wire[872..872]; + l3_w6_n5_mux_dataout = sel_wire[14..14] & data_wire[875..875] # !(sel_wire[14..14]) & data_wire[874..874]; + l3_w6_n6_mux_dataout = sel_wire[14..14] & data_wire[877..877] # !(sel_wire[14..14]) & data_wire[876..876]; + l3_w6_n7_mux_dataout = sel_wire[14..14] & data_wire[879..879] # !(sel_wire[14..14]) & data_wire[878..878]; + l3_w7_n0_mux_dataout = sel_wire[14..14] & data_wire[881..881] # !(sel_wire[14..14]) & data_wire[880..880]; + l3_w7_n1_mux_dataout = sel_wire[14..14] & data_wire[883..883] # !(sel_wire[14..14]) & data_wire[882..882]; + l3_w7_n2_mux_dataout = sel_wire[14..14] & data_wire[885..885] # !(sel_wire[14..14]) & data_wire[884..884]; + l3_w7_n3_mux_dataout = sel_wire[14..14] & data_wire[887..887] # !(sel_wire[14..14]) & data_wire[886..886]; + l3_w7_n4_mux_dataout = sel_wire[14..14] & data_wire[889..889] # !(sel_wire[14..14]) & data_wire[888..888]; + l3_w7_n5_mux_dataout = sel_wire[14..14] & data_wire[891..891] # !(sel_wire[14..14]) & data_wire[890..890]; + l3_w7_n6_mux_dataout = sel_wire[14..14] & data_wire[893..893] # !(sel_wire[14..14]) & data_wire[892..892]; + l3_w7_n7_mux_dataout = sel_wire[14..14] & data_wire[895..895] # !(sel_wire[14..14]) & data_wire[894..894]; + l4_w0_n0_mux_dataout = sel_wire[21..21] & data_wire[897..897] # !(sel_wire[21..21]) & data_wire[896..896]; + l4_w0_n1_mux_dataout = sel_wire[21..21] & data_wire[899..899] # !(sel_wire[21..21]) & data_wire[898..898]; + l4_w0_n2_mux_dataout = sel_wire[21..21] & data_wire[901..901] # !(sel_wire[21..21]) & data_wire[900..900]; + l4_w0_n3_mux_dataout = sel_wire[21..21] & data_wire[903..903] # !(sel_wire[21..21]) & data_wire[902..902]; + l4_w1_n0_mux_dataout = sel_wire[21..21] & data_wire[905..905] # !(sel_wire[21..21]) & data_wire[904..904]; + l4_w1_n1_mux_dataout = sel_wire[21..21] & data_wire[907..907] # !(sel_wire[21..21]) & data_wire[906..906]; + l4_w1_n2_mux_dataout = sel_wire[21..21] & data_wire[909..909] # !(sel_wire[21..21]) & data_wire[908..908]; + l4_w1_n3_mux_dataout = sel_wire[21..21] & data_wire[911..911] # !(sel_wire[21..21]) & data_wire[910..910]; + l4_w2_n0_mux_dataout = sel_wire[21..21] & data_wire[913..913] # !(sel_wire[21..21]) & data_wire[912..912]; + l4_w2_n1_mux_dataout = sel_wire[21..21] & data_wire[915..915] # !(sel_wire[21..21]) & data_wire[914..914]; + l4_w2_n2_mux_dataout = sel_wire[21..21] & data_wire[917..917] # !(sel_wire[21..21]) & data_wire[916..916]; + l4_w2_n3_mux_dataout = sel_wire[21..21] & data_wire[919..919] # !(sel_wire[21..21]) & data_wire[918..918]; + l4_w3_n0_mux_dataout = sel_wire[21..21] & data_wire[921..921] # !(sel_wire[21..21]) & data_wire[920..920]; + l4_w3_n1_mux_dataout = sel_wire[21..21] & data_wire[923..923] # !(sel_wire[21..21]) & data_wire[922..922]; + l4_w3_n2_mux_dataout = sel_wire[21..21] & data_wire[925..925] # !(sel_wire[21..21]) & data_wire[924..924]; + l4_w3_n3_mux_dataout = sel_wire[21..21] & data_wire[927..927] # !(sel_wire[21..21]) & data_wire[926..926]; + l4_w4_n0_mux_dataout = sel_wire[21..21] & data_wire[929..929] # !(sel_wire[21..21]) & data_wire[928..928]; + l4_w4_n1_mux_dataout = sel_wire[21..21] & data_wire[931..931] # !(sel_wire[21..21]) & data_wire[930..930]; + l4_w4_n2_mux_dataout = sel_wire[21..21] & data_wire[933..933] # !(sel_wire[21..21]) & data_wire[932..932]; + l4_w4_n3_mux_dataout = sel_wire[21..21] & data_wire[935..935] # !(sel_wire[21..21]) & data_wire[934..934]; + l4_w5_n0_mux_dataout = sel_wire[21..21] & data_wire[937..937] # !(sel_wire[21..21]) & data_wire[936..936]; + l4_w5_n1_mux_dataout = sel_wire[21..21] & data_wire[939..939] # !(sel_wire[21..21]) & data_wire[938..938]; + l4_w5_n2_mux_dataout = sel_wire[21..21] & data_wire[941..941] # !(sel_wire[21..21]) & data_wire[940..940]; + l4_w5_n3_mux_dataout = sel_wire[21..21] & data_wire[943..943] # !(sel_wire[21..21]) & data_wire[942..942]; + l4_w6_n0_mux_dataout = sel_wire[21..21] & data_wire[945..945] # !(sel_wire[21..21]) & data_wire[944..944]; + l4_w6_n1_mux_dataout = sel_wire[21..21] & data_wire[947..947] # !(sel_wire[21..21]) & data_wire[946..946]; + l4_w6_n2_mux_dataout = sel_wire[21..21] & data_wire[949..949] # !(sel_wire[21..21]) & data_wire[948..948]; + l4_w6_n3_mux_dataout = sel_wire[21..21] & data_wire[951..951] # !(sel_wire[21..21]) & data_wire[950..950]; + l4_w7_n0_mux_dataout = sel_wire[21..21] & data_wire[953..953] # !(sel_wire[21..21]) & data_wire[952..952]; + l4_w7_n1_mux_dataout = sel_wire[21..21] & data_wire[955..955] # !(sel_wire[21..21]) & data_wire[954..954]; + l4_w7_n2_mux_dataout = sel_wire[21..21] & data_wire[957..957] # !(sel_wire[21..21]) & data_wire[956..956]; + l4_w7_n3_mux_dataout = sel_wire[21..21] & data_wire[959..959] # !(sel_wire[21..21]) & data_wire[958..958]; + l5_w0_n0_mux_dataout = sel_wire[28..28] & data_wire[961..961] # !(sel_wire[28..28]) & data_wire[960..960]; + l5_w0_n1_mux_dataout = sel_wire[28..28] & data_wire[963..963] # !(sel_wire[28..28]) & data_wire[962..962]; + l5_w1_n0_mux_dataout = sel_wire[28..28] & data_wire[965..965] # !(sel_wire[28..28]) & data_wire[964..964]; + l5_w1_n1_mux_dataout = sel_wire[28..28] & data_wire[967..967] # !(sel_wire[28..28]) & data_wire[966..966]; + l5_w2_n0_mux_dataout = sel_wire[28..28] & data_wire[969..969] # !(sel_wire[28..28]) & data_wire[968..968]; + l5_w2_n1_mux_dataout = sel_wire[28..28] & data_wire[971..971] # !(sel_wire[28..28]) & data_wire[970..970]; + l5_w3_n0_mux_dataout = sel_wire[28..28] & data_wire[973..973] # !(sel_wire[28..28]) & data_wire[972..972]; + l5_w3_n1_mux_dataout = sel_wire[28..28] & data_wire[975..975] # !(sel_wire[28..28]) & data_wire[974..974]; + l5_w4_n0_mux_dataout = sel_wire[28..28] & data_wire[977..977] # !(sel_wire[28..28]) & data_wire[976..976]; + l5_w4_n1_mux_dataout = sel_wire[28..28] & data_wire[979..979] # !(sel_wire[28..28]) & data_wire[978..978]; + l5_w5_n0_mux_dataout = sel_wire[28..28] & data_wire[981..981] # !(sel_wire[28..28]) & data_wire[980..980]; + l5_w5_n1_mux_dataout = sel_wire[28..28] & data_wire[983..983] # !(sel_wire[28..28]) & data_wire[982..982]; + l5_w6_n0_mux_dataout = sel_wire[28..28] & data_wire[985..985] # !(sel_wire[28..28]) & data_wire[984..984]; + l5_w6_n1_mux_dataout = sel_wire[28..28] & data_wire[987..987] # !(sel_wire[28..28]) & data_wire[986..986]; + l5_w7_n0_mux_dataout = sel_wire[28..28] & data_wire[989..989] # !(sel_wire[28..28]) & data_wire[988..988]; + l5_w7_n1_mux_dataout = sel_wire[28..28] & data_wire[991..991] # !(sel_wire[28..28]) & data_wire[990..990]; + l6_w0_n0_mux_dataout = sel_wire[35..35] & data_wire[993..993] # !(sel_wire[35..35]) & data_wire[992..992]; + l6_w1_n0_mux_dataout = sel_wire[35..35] & data_wire[995..995] # !(sel_wire[35..35]) & data_wire[994..994]; + l6_w2_n0_mux_dataout = sel_wire[35..35] & data_wire[997..997] # !(sel_wire[35..35]) & data_wire[996..996]; + l6_w3_n0_mux_dataout = sel_wire[35..35] & data_wire[999..999] # !(sel_wire[35..35]) & data_wire[998..998]; + l6_w4_n0_mux_dataout = sel_wire[35..35] & data_wire[1001..1001] # !(sel_wire[35..35]) & data_wire[1000..1000]; + l6_w5_n0_mux_dataout = sel_wire[35..35] & data_wire[1003..1003] # !(sel_wire[35..35]) & data_wire[1002..1002]; + l6_w6_n0_mux_dataout = sel_wire[35..35] & data_wire[1005..1005] # !(sel_wire[35..35]) & data_wire[1004..1004]; + l6_w7_n0_mux_dataout = sel_wire[35..35] & data_wire[1007..1007] # !(sel_wire[35..35]) & data_wire[1006..1006]; + data_wire[] = ( l5_w7_n1_mux_dataout, l5_w7_n0_mux_dataout, l5_w6_n1_mux_dataout, l5_w6_n0_mux_dataout, l5_w5_n1_mux_dataout, l5_w5_n0_mux_dataout, l5_w4_n1_mux_dataout, l5_w4_n0_mux_dataout, l5_w3_n1_mux_dataout, l5_w3_n0_mux_dataout, l5_w2_n1_mux_dataout, l5_w2_n0_mux_dataout, l5_w1_n1_mux_dataout, l5_w1_n0_mux_dataout, l5_w0_n1_mux_dataout, l5_w0_n0_mux_dataout, l4_w7_n3_mux_dataout, l4_w7_n2_mux_dataout, l4_w7_n1_mux_dataout, l4_w7_n0_mux_dataout, l4_w6_n3_mux_dataout, l4_w6_n2_mux_dataout, l4_w6_n1_mux_dataout, l4_w6_n0_mux_dataout, l4_w5_n3_mux_dataout, l4_w5_n2_mux_dataout, l4_w5_n1_mux_dataout, l4_w5_n0_mux_dataout, l4_w4_n3_mux_dataout, l4_w4_n2_mux_dataout, l4_w4_n1_mux_dataout, l4_w4_n0_mux_dataout, l4_w3_n3_mux_dataout, l4_w3_n2_mux_dataout, l4_w3_n1_mux_dataout, l4_w3_n0_mux_dataout, l4_w2_n3_mux_dataout, l4_w2_n2_mux_dataout, l4_w2_n1_mux_dataout, l4_w2_n0_mux_dataout, l4_w1_n3_mux_dataout, l4_w1_n2_mux_dataout, l4_w1_n1_mux_dataout, l4_w1_n0_mux_dataout, l4_w0_n3_mux_dataout, l4_w0_n2_mux_dataout, l4_w0_n1_mux_dataout, l4_w0_n0_mux_dataout, l3_w7_n7_mux_dataout, l3_w7_n6_mux_dataout, l3_w7_n5_mux_dataout, l3_w7_n4_mux_dataout, l3_w7_n3_mux_dataout, l3_w7_n2_mux_dataout, l3_w7_n1_mux_dataout, l3_w7_n0_mux_dataout, l3_w6_n7_mux_dataout, l3_w6_n6_mux_dataout, l3_w6_n5_mux_dataout, l3_w6_n4_mux_dataout, l3_w6_n3_mux_dataout, l3_w6_n2_mux_dataout, l3_w6_n1_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n7_mux_dataout, l3_w5_n6_mux_dataout, l3_w5_n5_mux_dataout, l3_w5_n4_mux_dataout, l3_w5_n3_mux_dataout, l3_w5_n2_mux_dataout, l3_w5_n1_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n7_mux_dataout, l3_w4_n6_mux_dataout, l3_w4_n5_mux_dataout, l3_w4_n4_mux_dataout, l3_w4_n3_mux_dataout, l3_w4_n2_mux_dataout, l3_w4_n1_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n7_mux_dataout, l3_w3_n6_mux_dataout, l3_w3_n5_mux_dataout, l3_w3_n4_mux_dataout, l3_w3_n3_mux_dataout, l3_w3_n2_mux_dataout, l3_w3_n1_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n7_mux_dataout, l3_w2_n6_mux_dataout, l3_w2_n5_mux_dataout, l3_w2_n4_mux_dataout, l3_w2_n3_mux_dataout, l3_w2_n2_mux_dataout, l3_w2_n1_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n7_mux_dataout, l3_w1_n6_mux_dataout, l3_w1_n5_mux_dataout, l3_w1_n4_mux_dataout, l3_w1_n3_mux_dataout, l3_w1_n2_mux_dataout, l3_w1_n1_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n7_mux_dataout, l3_w0_n6_mux_dataout, l3_w0_n5_mux_dataout, l3_w0_n4_mux_dataout, l3_w0_n3_mux_dataout, l3_w0_n2_mux_dataout, l3_w0_n1_mux_dataout, l3_w0_n0_mux_dataout, l2_w7_n15_mux_dataout, l2_w7_n14_mux_dataout, l2_w7_n13_mux_dataout, l2_w7_n12_mux_dataout, l2_w7_n11_mux_dataout, l2_w7_n10_mux_dataout, l2_w7_n9_mux_dataout, l2_w7_n8_mux_dataout, l2_w7_n7_mux_dataout, l2_w7_n6_mux_dataout, l2_w7_n5_mux_dataout, l2_w7_n4_mux_dataout, l2_w7_n3_mux_dataout, l2_w7_n2_mux_dataout, l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n15_mux_dataout, l2_w6_n14_mux_dataout, l2_w6_n13_mux_dataout, l2_w6_n12_mux_dataout, l2_w6_n11_mux_dataout, l2_w6_n10_mux_dataout, l2_w6_n9_mux_dataout, l2_w6_n8_mux_dataout, l2_w6_n7_mux_dataout, l2_w6_n6_mux_dataout, l2_w6_n5_mux_dataout, l2_w6_n4_mux_dataout, l2_w6_n3_mux_dataout, l2_w6_n2_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n15_mux_dataout, l2_w5_n14_mux_dataout, l2_w5_n13_mux_dataout, l2_w5_n12_mux_dataout, l2_w5_n11_mux_dataout, l2_w5_n10_mux_dataout, l2_w5_n9_mux_dataout, l2_w5_n8_mux_dataout, l2_w5_n7_mux_dataout, l2_w5_n6_mux_dataout, l2_w5_n5_mux_dataout, l2_w5_n4_mux_dataout, l2_w5_n3_mux_dataout, l2_w5_n2_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n15_mux_dataout, l2_w4_n14_mux_dataout, l2_w4_n13_mux_dataout, l2_w4_n12_mux_dataout, l2_w4_n11_mux_dataout, l2_w4_n10_mux_dataout, l2_w4_n9_mux_dataout, l2_w4_n8_mux_dataout, l2_w4_n7_mux_dataout, l2_w4_n6_mux_dataout, l2_w4_n5_mux_dataout, l2_w4_n4_mux_dataout, l2_w4_n3_mux_dataout, l2_w4_n2_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n15_mux_dataout, l2_w3_n14_mux_dataout, l2_w3_n13_mux_dataout, l2_w3_n12_mux_dataout, l2_w3_n11_mux_dataout, l2_w3_n10_mux_dataout, l2_w3_n9_mux_dataout, l2_w3_n8_mux_dataout, l2_w3_n7_mux_dataout, l2_w3_n6_mux_dataout, l2_w3_n5_mux_dataout, l2_w3_n4_mux_dataout, l2_w3_n3_mux_dataout, l2_w3_n2_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n15_mux_dataout, l2_w2_n14_mux_dataout, l2_w2_n13_mux_dataout, l2_w2_n12_mux_dataout, l2_w2_n11_mux_dataout, l2_w2_n10_mux_dataout, l2_w2_n9_mux_dataout, l2_w2_n8_mux_dataout, l2_w2_n7_mux_dataout, l2_w2_n6_mux_dataout, l2_w2_n5_mux_dataout, l2_w2_n4_mux_dataout, l2_w2_n3_mux_dataout, l2_w2_n2_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n15_mux_dataout, l2_w1_n14_mux_dataout, l2_w1_n13_mux_dataout, l2_w1_n12_mux_dataout, l2_w1_n11_mux_dataout, l2_w1_n10_mux_dataout, l2_w1_n9_mux_dataout, l2_w1_n8_mux_dataout, l2_w1_n7_mux_dataout, l2_w1_n6_mux_dataout, l2_w1_n5_mux_dataout, l2_w1_n4_mux_dataout, l2_w1_n3_mux_dataout, l2_w1_n2_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n15_mux_dataout, l2_w0_n14_mux_dataout, l2_w0_n13_mux_dataout, l2_w0_n12_mux_dataout, l2_w0_n11_mux_dataout, l2_w0_n10_mux_dataout, l2_w0_n9_mux_dataout, l2_w0_n8_mux_dataout, l2_w0_n7_mux_dataout, l2_w0_n6_mux_dataout, l2_w0_n5_mux_dataout, l2_w0_n4_mux_dataout, l2_w0_n3_mux_dataout, l2_w0_n2_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n31_mux_dataout, l1_w7_n30_mux_dataout, l1_w7_n29_mux_dataout, l1_w7_n28_mux_dataout, l1_w7_n27_mux_dataout, l1_w7_n26_mux_dataout, l1_w7_n25_mux_dataout, l1_w7_n24_mux_dataout, l1_w7_n23_mux_dataout, l1_w7_n22_mux_dataout, l1_w7_n21_mux_dataout, l1_w7_n20_mux_dataout, l1_w7_n19_mux_dataout, l1_w7_n18_mux_dataout, l1_w7_n17_mux_dataout, l1_w7_n16_mux_dataout, l1_w7_n15_mux_dataout, l1_w7_n14_mux_dataout, l1_w7_n13_mux_dataout, l1_w7_n12_mux_dataout, l1_w7_n11_mux_dataout, l1_w7_n10_mux_dataout, l1_w7_n9_mux_dataout, l1_w7_n8_mux_dataout, l1_w7_n7_mux_dataout, l1_w7_n6_mux_dataout, l1_w7_n5_mux_dataout, l1_w7_n4_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n31_mux_dataout, l1_w6_n30_mux_dataout, l1_w6_n29_mux_dataout, l1_w6_n28_mux_dataout, l1_w6_n27_mux_dataout, l1_w6_n26_mux_dataout, l1_w6_n25_mux_dataout, l1_w6_n24_mux_dataout, l1_w6_n23_mux_dataout, l1_w6_n22_mux_dataout, l1_w6_n21_mux_dataout, l1_w6_n20_mux_dataout, l1_w6_n19_mux_dataout, l1_w6_n18_mux_dataout, l1_w6_n17_mux_dataout, l1_w6_n16_mux_dataout, l1_w6_n15_mux_dataout, l1_w6_n14_mux_dataout, l1_w6_n13_mux_dataout, l1_w6_n12_mux_dataout, l1_w6_n11_mux_dataout, l1_w6_n10_mux_dataout, l1_w6_n9_mux_dataout, l1_w6_n8_mux_dataout, l1_w6_n7_mux_dataout, l1_w6_n6_mux_dataout, l1_w6_n5_mux_dataout, l1_w6_n4_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n31_mux_dataout, l1_w5_n30_mux_dataout, l1_w5_n29_mux_dataout, l1_w5_n28_mux_dataout, l1_w5_n27_mux_dataout, l1_w5_n26_mux_dataout, l1_w5_n25_mux_dataout, l1_w5_n24_mux_dataout, l1_w5_n23_mux_dataout, l1_w5_n22_mux_dataout, l1_w5_n21_mux_dataout, l1_w5_n20_mux_dataout, l1_w5_n19_mux_dataout, l1_w5_n18_mux_dataout, l1_w5_n17_mux_dataout, l1_w5_n16_mux_dataout, l1_w5_n15_mux_dataout, l1_w5_n14_mux_dataout, l1_w5_n13_mux_dataout, l1_w5_n12_mux_dataout, l1_w5_n11_mux_dataout, l1_w5_n10_mux_dataout, l1_w5_n9_mux_dataout, l1_w5_n8_mux_dataout, l1_w5_n7_mux_dataout, l1_w5_n6_mux_dataout, l1_w5_n5_mux_dataout, l1_w5_n4_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n31_mux_dataout, l1_w4_n30_mux_dataout, l1_w4_n29_mux_dataout, l1_w4_n28_mux_dataout, l1_w4_n27_mux_dataout, l1_w4_n26_mux_dataout, l1_w4_n25_mux_dataout, l1_w4_n24_mux_dataout, l1_w4_n23_mux_dataout, l1_w4_n22_mux_dataout, l1_w4_n21_mux_dataout, l1_w4_n20_mux_dataout, l1_w4_n19_mux_dataout, l1_w4_n18_mux_dataout, l1_w4_n17_mux_dataout, l1_w4_n16_mux_dataout, l1_w4_n15_mux_dataout, l1_w4_n14_mux_dataout, l1_w4_n13_mux_dataout, l1_w4_n12_mux_dataout, l1_w4_n11_mux_dataout, l1_w4_n10_mux_dataout, l1_w4_n9_mux_dataout, l1_w4_n8_mux_dataout, l1_w4_n7_mux_dataout, l1_w4_n6_mux_dataout, l1_w4_n5_mux_dataout, l1_w4_n4_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n31_mux_dataout, l1_w3_n30_mux_dataout, l1_w3_n29_mux_dataout, l1_w3_n28_mux_dataout, l1_w3_n27_mux_dataout, l1_w3_n26_mux_dataout, l1_w3_n25_mux_dataout, l1_w3_n24_mux_dataout, l1_w3_n23_mux_dataout, l1_w3_n22_mux_dataout, l1_w3_n21_mux_dataout, l1_w3_n20_mux_dataout, l1_w3_n19_mux_dataout, l1_w3_n18_mux_dataout, l1_w3_n17_mux_dataout, l1_w3_n16_mux_dataout, l1_w3_n15_mux_dataout, l1_w3_n14_mux_dataout, l1_w3_n13_mux_dataout, l1_w3_n12_mux_dataout, l1_w3_n11_mux_dataout, l1_w3_n10_mux_dataout, l1_w3_n9_mux_dataout, l1_w3_n8_mux_dataout, l1_w3_n7_mux_dataout, l1_w3_n6_mux_dataout, l1_w3_n5_mux_dataout, l1_w3_n4_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n31_mux_dataout, l1_w2_n30_mux_dataout, l1_w2_n29_mux_dataout, l1_w2_n28_mux_dataout, l1_w2_n27_mux_dataout, l1_w2_n26_mux_dataout, l1_w2_n25_mux_dataout, l1_w2_n24_mux_dataout, l1_w2_n23_mux_dataout, l1_w2_n22_mux_dataout, l1_w2_n21_mux_dataout, l1_w2_n20_mux_dataout, l1_w2_n19_mux_dataout, l1_w2_n18_mux_dataout, l1_w2_n17_mux_dataout, l1_w2_n16_mux_dataout, l1_w2_n15_mux_dataout, l1_w2_n14_mux_dataout, l1_w2_n13_mux_dataout, l1_w2_n12_mux_dataout, l1_w2_n11_mux_dataout, l1_w2_n10_mux_dataout, l1_w2_n9_mux_dataout, l1_w2_n8_mux_dataout, l1_w2_n7_mux_dataout, l1_w2_n6_mux_dataout, l1_w2_n5_mux_dataout, l1_w2_n4_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n31_mux_dataout, l1_w1_n30_mux_dataout, l1_w1_n29_mux_dataout, l1_w1_n28_mux_dataout, l1_w1_n27_mux_dataout, l1_w1_n26_mux_dataout, l1_w1_n25_mux_dataout, l1_w1_n24_mux_dataout, l1_w1_n23_mux_dataout, l1_w1_n22_mux_dataout, l1_w1_n21_mux_dataout, l1_w1_n20_mux_dataout, l1_w1_n19_mux_dataout, l1_w1_n18_mux_dataout, l1_w1_n17_mux_dataout, l1_w1_n16_mux_dataout, l1_w1_n15_mux_dataout, l1_w1_n14_mux_dataout, l1_w1_n13_mux_dataout, l1_w1_n12_mux_dataout, l1_w1_n11_mux_dataout, l1_w1_n10_mux_dataout, l1_w1_n9_mux_dataout, l1_w1_n8_mux_dataout, l1_w1_n7_mux_dataout, l1_w1_n6_mux_dataout, l1_w1_n5_mux_dataout, l1_w1_n4_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n31_mux_dataout, l1_w0_n30_mux_dataout, l1_w0_n29_mux_dataout, l1_w0_n28_mux_dataout, l1_w0_n27_mux_dataout, l1_w0_n26_mux_dataout, l1_w0_n25_mux_dataout, l1_w0_n24_mux_dataout, l1_w0_n23_mux_dataout, l1_w0_n22_mux_dataout, l1_w0_n21_mux_dataout, l1_w0_n20_mux_dataout, l1_w0_n19_mux_dataout, l1_w0_n18_mux_dataout, l1_w0_n17_mux_dataout, l1_w0_n16_mux_dataout, l1_w0_n15_mux_dataout, l1_w0_n14_mux_dataout, l1_w0_n13_mux_dataout, l1_w0_n12_mux_dataout, l1_w0_n11_mux_dataout, l1_w0_n10_mux_dataout, l1_w0_n9_mux_dataout, l1_w0_n8_mux_dataout, l1_w0_n7_mux_dataout, l1_w0_n6_mux_dataout, l1_w0_n5_mux_dataout, l1_w0_n4_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l6_w7_n0_mux_dataout, l6_w6_n0_mux_dataout, l6_w5_n0_mux_dataout, l6_w4_n0_mux_dataout, l6_w3_n0_mux_dataout, l6_w2_n0_mux_dataout, l6_w1_n0_mux_dataout, l6_w0_n0_mux_dataout); + sel_wire[] = ( sel[5..5], B"000000", sel[4..4], B"000000", sel[3..3], B"000000", sel[2..2], B"000000", sel[1..1], B"000000", sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/mux_lfb.tdf b/proj_quartus/db/mux_lfb.tdf new file mode 100644 index 000000000..e80ed2f08 --- /dev/null +++ b/proj_quartus/db/mux_lfb.tdf @@ -0,0 +1,56 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 3 +SUBDESIGN mux_lfb +( + data[15..0] : input; + result[7..0] : output; + sel[0..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + data_wire[15..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[0..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + data_wire[] = ( data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l1_w7_n0_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n0_mux_dataout); + sel_wire[] = ( sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/mux_ofb.tdf b/proj_quartus/db/mux_ofb.tdf new file mode 100644 index 000000000..250a9de42 --- /dev/null +++ b/proj_quartus/db/mux_ofb.tdf @@ -0,0 +1,88 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 8 +SUBDESIGN mux_ofb +( + data[31..0] : input; + result[7..0] : output; + sel[1..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w0_n1_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w1_n1_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w2_n1_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w3_n1_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w4_n1_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w5_n1_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w6_n1_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + l1_w7_n1_mux_dataout : WIRE; + l2_w0_n0_mux_dataout : WIRE; + l2_w1_n0_mux_dataout : WIRE; + l2_w2_n0_mux_dataout : WIRE; + l2_w3_n0_mux_dataout : WIRE; + l2_w4_n0_mux_dataout : WIRE; + l2_w5_n0_mux_dataout : WIRE; + l2_w6_n0_mux_dataout : WIRE; + l2_w7_n0_mux_dataout : WIRE; + data_wire[47..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[3..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23]; + l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[33..33] # !(sel_wire[3..3]) & data_wire[32..32]; + l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[35..35] # !(sel_wire[3..3]) & data_wire[34..34]; + l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[37..37] # !(sel_wire[3..3]) & data_wire[36..36]; + l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[39..39] # !(sel_wire[3..3]) & data_wire[38..38]; + l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[41..41] # !(sel_wire[3..3]) & data_wire[40..40]; + l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[43..43] # !(sel_wire[3..3]) & data_wire[42..42]; + l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[45..45] # !(sel_wire[3..3]) & data_wire[44..44]; + l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[47..47] # !(sel_wire[3..3]) & data_wire[46..46]; + data_wire[] = ( l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout); + sel_wire[] = ( sel[1..1], B"00", sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/mux_tfb.tdf b/proj_quartus/db/mux_tfb.tdf new file mode 100644 index 000000000..781658c8e --- /dev/null +++ b/proj_quartus/db/mux_tfb.tdf @@ -0,0 +1,152 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=8 LPM_WIDTH=8 LPM_WIDTHS=3 data result sel +--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END + + +-- Copyright (C) 2022 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + + + +--synthesis_resources = lut 19 +SUBDESIGN mux_tfb +( + data[63..0] : input; + result[7..0] : output; + sel[2..0] : input; +) +VARIABLE + l1_w0_n0_mux_dataout : WIRE; + l1_w0_n1_mux_dataout : WIRE; + l1_w0_n2_mux_dataout : WIRE; + l1_w0_n3_mux_dataout : WIRE; + l1_w1_n0_mux_dataout : WIRE; + l1_w1_n1_mux_dataout : WIRE; + l1_w1_n2_mux_dataout : WIRE; + l1_w1_n3_mux_dataout : WIRE; + l1_w2_n0_mux_dataout : WIRE; + l1_w2_n1_mux_dataout : WIRE; + l1_w2_n2_mux_dataout : WIRE; + l1_w2_n3_mux_dataout : WIRE; + l1_w3_n0_mux_dataout : WIRE; + l1_w3_n1_mux_dataout : WIRE; + l1_w3_n2_mux_dataout : WIRE; + l1_w3_n3_mux_dataout : WIRE; + l1_w4_n0_mux_dataout : WIRE; + l1_w4_n1_mux_dataout : WIRE; + l1_w4_n2_mux_dataout : WIRE; + l1_w4_n3_mux_dataout : WIRE; + l1_w5_n0_mux_dataout : WIRE; + l1_w5_n1_mux_dataout : WIRE; + l1_w5_n2_mux_dataout : WIRE; + l1_w5_n3_mux_dataout : WIRE; + l1_w6_n0_mux_dataout : WIRE; + l1_w6_n1_mux_dataout : WIRE; + l1_w6_n2_mux_dataout : WIRE; + l1_w6_n3_mux_dataout : WIRE; + l1_w7_n0_mux_dataout : WIRE; + l1_w7_n1_mux_dataout : WIRE; + l1_w7_n2_mux_dataout : WIRE; + l1_w7_n3_mux_dataout : WIRE; + l2_w0_n0_mux_dataout : WIRE; + l2_w0_n1_mux_dataout : WIRE; + l2_w1_n0_mux_dataout : WIRE; + l2_w1_n1_mux_dataout : WIRE; + l2_w2_n0_mux_dataout : WIRE; + l2_w2_n1_mux_dataout : WIRE; + l2_w3_n0_mux_dataout : WIRE; + l2_w3_n1_mux_dataout : WIRE; + l2_w4_n0_mux_dataout : WIRE; + l2_w4_n1_mux_dataout : WIRE; + l2_w5_n0_mux_dataout : WIRE; + l2_w5_n1_mux_dataout : WIRE; + l2_w6_n0_mux_dataout : WIRE; + l2_w6_n1_mux_dataout : WIRE; + l2_w7_n0_mux_dataout : WIRE; + l2_w7_n1_mux_dataout : WIRE; + l3_w0_n0_mux_dataout : WIRE; + l3_w1_n0_mux_dataout : WIRE; + l3_w2_n0_mux_dataout : WIRE; + l3_w3_n0_mux_dataout : WIRE; + l3_w4_n0_mux_dataout : WIRE; + l3_w5_n0_mux_dataout : WIRE; + l3_w6_n0_mux_dataout : WIRE; + l3_w7_n0_mux_dataout : WIRE; + data_wire[111..0] : WIRE; + result_wire_ext[7..0] : WIRE; + sel_wire[8..0] : WIRE; + +BEGIN + l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0]; + l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16]; + l1_w0_n2_mux_dataout = sel_wire[0..0] & data_wire[40..40] # !(sel_wire[0..0]) & data_wire[32..32]; + l1_w0_n3_mux_dataout = sel_wire[0..0] & data_wire[56..56] # !(sel_wire[0..0]) & data_wire[48..48]; + l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1]; + l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17]; + l1_w1_n2_mux_dataout = sel_wire[0..0] & data_wire[41..41] # !(sel_wire[0..0]) & data_wire[33..33]; + l1_w1_n3_mux_dataout = sel_wire[0..0] & data_wire[57..57] # !(sel_wire[0..0]) & data_wire[49..49]; + l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2]; + l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18]; + l1_w2_n2_mux_dataout = sel_wire[0..0] & data_wire[42..42] # !(sel_wire[0..0]) & data_wire[34..34]; + l1_w2_n3_mux_dataout = sel_wire[0..0] & data_wire[58..58] # !(sel_wire[0..0]) & data_wire[50..50]; + l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3]; + l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19]; + l1_w3_n2_mux_dataout = sel_wire[0..0] & data_wire[43..43] # !(sel_wire[0..0]) & data_wire[35..35]; + l1_w3_n3_mux_dataout = sel_wire[0..0] & data_wire[59..59] # !(sel_wire[0..0]) & data_wire[51..51]; + l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4]; + l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20]; + l1_w4_n2_mux_dataout = sel_wire[0..0] & data_wire[44..44] # !(sel_wire[0..0]) & data_wire[36..36]; + l1_w4_n3_mux_dataout = sel_wire[0..0] & data_wire[60..60] # !(sel_wire[0..0]) & data_wire[52..52]; + l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5]; + l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21]; + l1_w5_n2_mux_dataout = sel_wire[0..0] & data_wire[45..45] # !(sel_wire[0..0]) & data_wire[37..37]; + l1_w5_n3_mux_dataout = sel_wire[0..0] & data_wire[61..61] # !(sel_wire[0..0]) & data_wire[53..53]; + l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6]; + l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22]; + l1_w6_n2_mux_dataout = sel_wire[0..0] & data_wire[46..46] # !(sel_wire[0..0]) & data_wire[38..38]; + l1_w6_n3_mux_dataout = sel_wire[0..0] & data_wire[62..62] # !(sel_wire[0..0]) & data_wire[54..54]; + l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7]; + l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23]; + l1_w7_n2_mux_dataout = sel_wire[0..0] & data_wire[47..47] # !(sel_wire[0..0]) & data_wire[39..39]; + l1_w7_n3_mux_dataout = sel_wire[0..0] & data_wire[63..63] # !(sel_wire[0..0]) & data_wire[55..55]; + l2_w0_n0_mux_dataout = sel_wire[4..4] & data_wire[65..65] # !(sel_wire[4..4]) & data_wire[64..64]; + l2_w0_n1_mux_dataout = sel_wire[4..4] & data_wire[67..67] # !(sel_wire[4..4]) & data_wire[66..66]; + l2_w1_n0_mux_dataout = sel_wire[4..4] & data_wire[69..69] # !(sel_wire[4..4]) & data_wire[68..68]; + l2_w1_n1_mux_dataout = sel_wire[4..4] & data_wire[71..71] # !(sel_wire[4..4]) & data_wire[70..70]; + l2_w2_n0_mux_dataout = sel_wire[4..4] & data_wire[73..73] # !(sel_wire[4..4]) & data_wire[72..72]; + l2_w2_n1_mux_dataout = sel_wire[4..4] & data_wire[75..75] # !(sel_wire[4..4]) & data_wire[74..74]; + l2_w3_n0_mux_dataout = sel_wire[4..4] & data_wire[77..77] # !(sel_wire[4..4]) & data_wire[76..76]; + l2_w3_n1_mux_dataout = sel_wire[4..4] & data_wire[79..79] # !(sel_wire[4..4]) & data_wire[78..78]; + l2_w4_n0_mux_dataout = sel_wire[4..4] & data_wire[81..81] # !(sel_wire[4..4]) & data_wire[80..80]; + l2_w4_n1_mux_dataout = sel_wire[4..4] & data_wire[83..83] # !(sel_wire[4..4]) & data_wire[82..82]; + l2_w5_n0_mux_dataout = sel_wire[4..4] & data_wire[85..85] # !(sel_wire[4..4]) & data_wire[84..84]; + l2_w5_n1_mux_dataout = sel_wire[4..4] & data_wire[87..87] # !(sel_wire[4..4]) & data_wire[86..86]; + l2_w6_n0_mux_dataout = sel_wire[4..4] & data_wire[89..89] # !(sel_wire[4..4]) & data_wire[88..88]; + l2_w6_n1_mux_dataout = sel_wire[4..4] & data_wire[91..91] # !(sel_wire[4..4]) & data_wire[90..90]; + l2_w7_n0_mux_dataout = sel_wire[4..4] & data_wire[93..93] # !(sel_wire[4..4]) & data_wire[92..92]; + l2_w7_n1_mux_dataout = sel_wire[4..4] & data_wire[95..95] # !(sel_wire[4..4]) & data_wire[94..94]; + l3_w0_n0_mux_dataout = sel_wire[8..8] & data_wire[97..97] # !(sel_wire[8..8]) & data_wire[96..96]; + l3_w1_n0_mux_dataout = sel_wire[8..8] & data_wire[99..99] # !(sel_wire[8..8]) & data_wire[98..98]; + l3_w2_n0_mux_dataout = sel_wire[8..8] & data_wire[101..101] # !(sel_wire[8..8]) & data_wire[100..100]; + l3_w3_n0_mux_dataout = sel_wire[8..8] & data_wire[103..103] # !(sel_wire[8..8]) & data_wire[102..102]; + l3_w4_n0_mux_dataout = sel_wire[8..8] & data_wire[105..105] # !(sel_wire[8..8]) & data_wire[104..104]; + l3_w5_n0_mux_dataout = sel_wire[8..8] & data_wire[107..107] # !(sel_wire[8..8]) & data_wire[106..106]; + l3_w6_n0_mux_dataout = sel_wire[8..8] & data_wire[109..109] # !(sel_wire[8..8]) & data_wire[108..108]; + l3_w7_n0_mux_dataout = sel_wire[8..8] & data_wire[111..111] # !(sel_wire[8..8]) & data_wire[110..110]; + data_wire[] = ( l2_w7_n1_mux_dataout, l2_w7_n0_mux_dataout, l2_w6_n1_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n1_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n1_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n1_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n1_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n1_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n1_mux_dataout, l2_w0_n0_mux_dataout, l1_w7_n3_mux_dataout, l1_w7_n2_mux_dataout, l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n3_mux_dataout, l1_w6_n2_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n3_mux_dataout, l1_w5_n2_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n3_mux_dataout, l1_w4_n2_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n3_mux_dataout, l1_w3_n2_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n3_mux_dataout, l1_w2_n2_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n3_mux_dataout, l1_w1_n2_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n3_mux_dataout, l1_w0_n2_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]); + result[] = result_wire_ext[]; + result_wire_ext[] = ( l3_w7_n0_mux_dataout, l3_w6_n0_mux_dataout, l3_w5_n0_mux_dataout, l3_w4_n0_mux_dataout, l3_w3_n0_mux_dataout, l3_w2_n0_mux_dataout, l3_w1_n0_mux_dataout, l3_w0_n0_mux_dataout); + sel_wire[] = ( sel[2..2], B"000", sel[1..1], B"000", sel[0..0]); +END; +--VALID FILE diff --git a/proj_quartus/db/test.(35).cnf.cdb b/proj_quartus/db/test.(35).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..10906d5ec294eaf9351a1196efb5b83b34db5094 GIT binary patch literal 7428 zcmY*e1y~ea+Xh|bSvvhH_ade>P=jY~g zb+h2+rI&TLv9q8T!#9V|>;Ea<@&Hg4!HL74wx`au0J zAqEWVKmM9=%*pj4EfFH06#hsD;mnn-lOUPQWXTWAT%h{x930WbsYe_E<;g7R$liS5$VJvb~@2fW^0DY_~?|J9MbbhVWndzgV-Z6_BCkIx=TbhI35 z6xarRK3fsIc~91fON?5282RWE733fiviAlIB=KDoq_t&HVinHpQ@4A?l{s%`C{{CB z=Vq2*vu|P;^lslj`4_#acPdMT?8UT(I&%y_L7Za^EWU?T$4x|f`BESxno zWX+tjwfzN1>rz zurY||U=iJG4AJsmD1p*Fv#t1W3vA5Fb0CI>1`#dlCNu76!v8`$U}F)UgBCP2ifC~_ zLukTuO7|6Xum3>aXlNMGVq!9Lkx|@3e%lJ~u^3w2_1`(cyw~(kAk?V3aV3y!U(<>G}Dh<(agtI&nl&QLm^fu{Wcaqd?4d^IgS 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