memory
This commit is contained in:
parent
41846f6936
commit
311eadc3a4
149 changed files with 106633 additions and 97770 deletions
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@ -30,8 +30,9 @@ plt.legend()
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plt.title("Cycles d'exécution en fonction de n_max")
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plt.title("Cycles d'exécution en fonction de n_max")
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plt.ylabel("Cycles")
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plt.ylabel("Cycles")
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plt.xlabel("N_max")
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plt.xlabel("N_max")
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plt.show()
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plt.savefig("fibonacci_cycles.png")
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plt.savefig("fibonacci_cycles.png")
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plt.show()
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for i in range(9) :
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for i in range(9) :
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Y[i] = (Y[i]*1e9)/f_RISCV1
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Y[i] = (Y[i]*1e9)/f_RISCV1
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@ -59,5 +60,5 @@ plt.legend()
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plt.title("Temps d'exécution en fonction de n_max")
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plt.title("Temps d'exécution en fonction de n_max")
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plt.ylabel("T (ns)")
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plt.ylabel("T (ns)")
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plt.xlabel("N_max")
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plt.xlabel("N_max")
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plt.show()
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plt.savefig("fibonacci_temps.png")
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plt.savefig("fibonacci_temps.png")
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plt.show()
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@ -50,13 +50,9 @@
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#define BAUD_RATE 19200
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#define BAUD_RATE 19200
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/**@}*/
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/**@}*/
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void mult(uint32_t *n, uint32_t *y){
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void fn_mem(uint32_t N, uint32_t *y){
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uint32_t N = *n;
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uint32_t x[N];
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uint32_t a = 10;
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for(uint32_t i=0; i<N; i++){
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for(uint32_t i=0; i<N; i++){
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y[i] = a * x[i];
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y[i] = N;
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}
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}
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}
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}
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@ -85,14 +81,13 @@ int main() {
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neorv32_uart0_puts("Memory management cycles measure :\n");
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neorv32_uart0_puts("Memory management cycles measure :\n");
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neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
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neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
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uint32_t y[2000];
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uint32_t y[1024];
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for(uint8_t i=1; i<10; i++){
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for(n_max=0; n_max<1024+1; n_max+=128){
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n_max = 200*i;
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Begin_Time = (long)neorv32_mtime_get_time();
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Begin_Time = (long)neorv32_mtime_get_time();
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for(uint32_t j=0; j<10; j++){
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for(uint32_t j=0; j<10; j++){
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mult(&n_max, y);
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fn_mem(n_max, y);
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}
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}
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End_Time = (long)neorv32_mtime_get_time();
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End_Time = (long)neorv32_mtime_get_time();
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@ -88,7 +88,7 @@ entity neorv32_top is
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-- Internal Data memory (DMEM) --
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-- Internal Data memory (DMEM) --
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 16*1024; -- size of processor-internal data memory in bytes
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-- Internal Instruction Cache (iCACHE) --
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-- Internal Instruction Cache (iCACHE) --
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ICACHE_EN : boolean := false; -- implement instruction cache
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ICACHE_EN : boolean := false; -- implement instruction cache
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@ -43,8 +43,8 @@ entity neorv32_test_setup_bootloader is
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generic (
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generic (
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-- adapt these for your setup --
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-- adapt these for your setup --
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CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz
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MEM_INT_IMEM_SIZE : natural := 32*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_DMEM_SIZE : natural := 32*1024 -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 128*1024 -- size of processor-internal data memory in bytes
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);
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);
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port (
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port (
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-- Global control --
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-- Global control --
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@ -1,6 +1,6 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678285658625 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678361180216 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285658625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:27:38 2023 " "Processing started: Wed Mar 8 15:27:38 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285658625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678285658625 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678361180217 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 12:26:20 2023 " "Processing started: Thu Mar 9 12:26:20 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678361180217 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678361180217 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678285658625 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_asm --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678361180217 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678285659231 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678361180832 ""}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678285664207 ""}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678361186334 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "559 " "Peak virtual memory: 559 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:27:44 2023 " "Processing ended: Wed Mar 8 15:27:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285664411 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678285664411 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "567 " "Peak virtual memory: 567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678361186542 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 12:26:26 2023 " "Processing ended: Thu Mar 9 12:26:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678361186542 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678361186542 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678361186542 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678361186542 ""}
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@ -1,3 +1,3 @@
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Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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Version_Index = 553882368
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Version_Index = 553882368
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Creation_Time = Wed Mar 8 14:51:20 2023
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Creation_Time = Thu Mar 9 10:59:19 2023
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@ -1,6 +1,6 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678285674725 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678361197829 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678285674726 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 15:27:54 2023 " "Processing started: Wed Mar 8 15:27:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678285674726 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285674726 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition " "Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678361197830 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 9 12:26:37 2023 " "Processing started: Thu Mar 9 12:26:37 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678361197830 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678361197830 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285674726 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test " "Command: quartus_eda --read_settings_files=off --write_settings_files=off bootloarder_1 -c test" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678361197830 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678285675462 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678361198503 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "test.vo /home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/ simulation " "Generated file test.vo in folder \"/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678285676004 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "test.vo /home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/ simulation " "Generated file test.vo in folder \"/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/simulation/questa/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678361199081 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "729 " "Peak virtual memory: 729 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285676074 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:27:56 2023 " "Processing ended: Wed Mar 8 15:27:56 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285676074 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285676074 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285676074 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678285676074 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "733 " "Peak virtual memory: 733 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678361199150 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 12:26:39 2023 " "Processing ended: Thu Mar 9 12:26:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678361199150 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678361199150 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678361199150 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678361199150 ""}
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@ -1,43 +1,43 @@
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678285581377 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678361089537 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678285581377 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "6 6 " "Parallel compilation is enabled and will use 6 of the 6 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678361089537 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "test 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678285581401 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "test 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"test\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678361089571 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678285581444 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678361089615 ""}
|
||||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678285581444 ""}
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678361089615 ""}
|
||||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678285581853 ""}
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678361090041 ""}
|
||||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678285582002 ""}
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678361090192 ""}
|
||||||
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1678285582057 ""}
|
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1678361090257 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1678285592316 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1678361100635 ""}
|
||||||
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_i~inputCLKENA0 1617 global CLKCTRL_G6 " "clk_i~inputCLKENA0 with 1617 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1678285592439 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1678285592439 ""}
|
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "clk_i~inputCLKENA0 1721 global CLKCTRL_G6 " "clk_i~inputCLKENA0 with 1721 fanout uses global clock CLKCTRL_G6" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1678361100763 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1678361100763 ""}
|
||||||
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285592440 ""}
|
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361100764 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678285592469 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678361100800 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678285592473 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678361100805 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678285592483 ""}
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678361100814 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678285592491 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678361100823 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678285592491 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678361100823 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678285592495 ""}
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678361100827 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678285593365 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "test.sdc " "Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678361101682 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678285593366 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678361101683 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678285593414 ""}
|
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678361101737 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1678285593415 ""}
|
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1678361101737 ""}
|
||||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678285593416 ""}
|
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678361101738 ""}
|
||||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678285593663 ""}
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678361102008 ""}
|
||||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678285593669 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678285593669 ""}
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678361102014 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678361102014 ""}
|
||||||
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285593806 ""}
|
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361102185 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678285599222 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678361106569 ""}
|
||||||
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1678285599803 ""}
|
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1678361107202 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:19 " "Fitter placement preparation operations ending: elapsed time is 00:00:19" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285618119 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:19 " "Fitter placement preparation operations ending: elapsed time is 00:00:19" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361125373 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678285623743 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678361141604 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678285631419 ""}
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678361149290 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Fitter placement operations ending: elapsed time is 00:00:08" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285631419 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Fitter placement operations ending: elapsed time is 00:00:08" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361149290 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678285632758 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678361150690 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Router estimated average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "27 X45_Y11 X55_Y22 " "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22" { } { { "loc" "" { Generic "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22"} { { 12 { 0 ""} 45 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678285639503 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678285639503 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X45_Y11 X55_Y22 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22" { } { { "loc" "" { Generic "/home/seti/Desktop/Projet_SETI_RISC-V/proj_quartus/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22"} { { 12 { 0 ""} 45 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678361157629 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678361157629 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678285645682 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678285645682 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678361166168 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678361166168 ""}
|
||||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Fitter routing operations ending: elapsed time is 00:00:09" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285645685 ""}
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:12 " "Fitter routing operations ending: elapsed time is 00:00:12" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361166171 ""}
|
||||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 4.90 " "Total time spent on timing analysis during the Fitter is 4.90 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678285648974 ""}
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 5.21 " "Total time spent on timing analysis during the Fitter is 5.21 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678361169581 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678285649063 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678361169699 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678285650163 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678361171037 ""}
|
||||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678285650166 ""}
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678361171040 ""}
|
||||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678285651216 ""}
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678361172286 ""}
|
||||||
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:06 " "Fitter post-fit operations ending: elapsed time is 00:00:06" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678285655573 ""}
|
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:08 " "Fitter post-fit operations ending: elapsed time is 00:00:08" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678361177047 ""}
|
||||||
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678285655869 ""}
|
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678361177355 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2076 " "Peak virtual memory: 2076 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678285657212 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 15:27:37 2023 " "Processing ended: Wed Mar 8 15:27:37 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678285657212 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:17 " "Elapsed time: 00:01:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678285657212 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:02:59 " "Total CPU time (on all processors): 00:02:59" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678285657212 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678285657212 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2087 " "Peak virtual memory: 2087 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678361178874 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 9 12:26:18 2023 " "Processing ended: Thu Mar 9 12:26:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678361178874 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:29 " "Elapsed time: 00:01:29" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678361178874 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:03:02 " "Total CPU time (on all processors): 00:03:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678361178874 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678361178874 ""}
|
||||||
|
|
|
||||||
|
|
@ -1,15 +1,15 @@
|
||||||
|neorv32_test_setup_bootloader
|
|neorv32_test_setup_bootloader
|
||||||
clk_i => neorv32_top:neorv32_top_inst.clk_i
|
clk_i => neorv32_top:neorv32_top_inst.clk_i
|
||||||
rstn_i => neorv32_top:neorv32_top_inst.rstn_i
|
rstn_i => neorv32_top:neorv32_top_inst.rstn_i
|
||||||
gpio_o[0] <= neorv32_top:neorv32_top_inst.gpio_o[0]
|
gpio_o[0] << neorv32_top:neorv32_top_inst.gpio_o[0]
|
||||||
gpio_o[1] <= neorv32_top:neorv32_top_inst.gpio_o[1]
|
gpio_o[1] << neorv32_top:neorv32_top_inst.gpio_o[1]
|
||||||
gpio_o[2] <= neorv32_top:neorv32_top_inst.gpio_o[2]
|
gpio_o[2] << neorv32_top:neorv32_top_inst.gpio_o[2]
|
||||||
gpio_o[3] <= neorv32_top:neorv32_top_inst.gpio_o[3]
|
gpio_o[3] << neorv32_top:neorv32_top_inst.gpio_o[3]
|
||||||
gpio_o[4] <= neorv32_top:neorv32_top_inst.gpio_o[4]
|
gpio_o[4] << neorv32_top:neorv32_top_inst.gpio_o[4]
|
||||||
gpio_o[5] <= neorv32_top:neorv32_top_inst.gpio_o[5]
|
gpio_o[5] << neorv32_top:neorv32_top_inst.gpio_o[5]
|
||||||
gpio_o[6] <= neorv32_top:neorv32_top_inst.gpio_o[6]
|
gpio_o[6] << neorv32_top:neorv32_top_inst.gpio_o[6]
|
||||||
gpio_o[7] <= neorv32_top:neorv32_top_inst.gpio_o[7]
|
gpio_o[7] << neorv32_top:neorv32_top_inst.gpio_o[7]
|
||||||
uart0_txd_o <= neorv32_top:neorv32_top_inst.uart0_txd_o
|
uart0_txd_o << neorv32_top:neorv32_top_inst.uart0_txd_o
|
||||||
uart0_rxd_i => neorv32_top:neorv32_top_inst.uart0_rxd_i
|
uart0_rxd_i => neorv32_top:neorv32_top_inst.uart0_rxd_i
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -11180,7 +11180,7 @@ bus_xip_i => ignore.IN1
|
||||||
|
|
||||||
|
|
||||||
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_imem:\neorv32_int_imem_inst_true:neorv32_int_imem_inst
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_imem:\neorv32_int_imem_inst_true:neorv32_int_imem_inst
|
||||||
clk_i => mem_ram_b0~21.CLK
|
clk_i => mem_ram_b0~20.CLK
|
||||||
clk_i => mem_ram_b0~0.CLK
|
clk_i => mem_ram_b0~0.CLK
|
||||||
clk_i => mem_ram_b0~1.CLK
|
clk_i => mem_ram_b0~1.CLK
|
||||||
clk_i => mem_ram_b0~2.CLK
|
clk_i => mem_ram_b0~2.CLK
|
||||||
|
|
@ -11201,7 +11201,6 @@ clk_i => mem_ram_b0~16.CLK
|
||||||
clk_i => mem_ram_b0~17.CLK
|
clk_i => mem_ram_b0~17.CLK
|
||||||
clk_i => mem_ram_b0~18.CLK
|
clk_i => mem_ram_b0~18.CLK
|
||||||
clk_i => mem_ram_b0~19.CLK
|
clk_i => mem_ram_b0~19.CLK
|
||||||
clk_i => mem_ram_b0~20.CLK
|
|
||||||
clk_i => mem_ram_b1~0.CLK
|
clk_i => mem_ram_b1~0.CLK
|
||||||
clk_i => mem_ram_b1~1.CLK
|
clk_i => mem_ram_b1~1.CLK
|
||||||
clk_i => mem_ram_b1~2.CLK
|
clk_i => mem_ram_b1~2.CLK
|
||||||
|
|
@ -11223,7 +11222,6 @@ clk_i => mem_ram_b1~17.CLK
|
||||||
clk_i => mem_ram_b1~18.CLK
|
clk_i => mem_ram_b1~18.CLK
|
||||||
clk_i => mem_ram_b1~19.CLK
|
clk_i => mem_ram_b1~19.CLK
|
||||||
clk_i => mem_ram_b1~20.CLK
|
clk_i => mem_ram_b1~20.CLK
|
||||||
clk_i => mem_ram_b1~21.CLK
|
|
||||||
clk_i => mem_ram_b2~0.CLK
|
clk_i => mem_ram_b2~0.CLK
|
||||||
clk_i => mem_ram_b2~1.CLK
|
clk_i => mem_ram_b2~1.CLK
|
||||||
clk_i => mem_ram_b2~2.CLK
|
clk_i => mem_ram_b2~2.CLK
|
||||||
|
|
@ -11245,7 +11243,6 @@ clk_i => mem_ram_b2~17.CLK
|
||||||
clk_i => mem_ram_b2~18.CLK
|
clk_i => mem_ram_b2~18.CLK
|
||||||
clk_i => mem_ram_b2~19.CLK
|
clk_i => mem_ram_b2~19.CLK
|
||||||
clk_i => mem_ram_b2~20.CLK
|
clk_i => mem_ram_b2~20.CLK
|
||||||
clk_i => mem_ram_b2~21.CLK
|
|
||||||
clk_i => mem_ram_b3~0.CLK
|
clk_i => mem_ram_b3~0.CLK
|
||||||
clk_i => mem_ram_b3~1.CLK
|
clk_i => mem_ram_b3~1.CLK
|
||||||
clk_i => mem_ram_b3~2.CLK
|
clk_i => mem_ram_b3~2.CLK
|
||||||
|
|
@ -11267,7 +11264,6 @@ clk_i => mem_ram_b3~17.CLK
|
||||||
clk_i => mem_ram_b3~18.CLK
|
clk_i => mem_ram_b3~18.CLK
|
||||||
clk_i => mem_ram_b3~19.CLK
|
clk_i => mem_ram_b3~19.CLK
|
||||||
clk_i => mem_ram_b3~20.CLK
|
clk_i => mem_ram_b3~20.CLK
|
||||||
clk_i => mem_ram_b3~21.CLK
|
|
||||||
clk_i => err_o~reg0.CLK
|
clk_i => err_o~reg0.CLK
|
||||||
clk_i => ack_o~reg0.CLK
|
clk_i => ack_o~reg0.CLK
|
||||||
clk_i => rden.CLK
|
clk_i => rden.CLK
|
||||||
|
|
@ -11320,10 +11316,10 @@ ben_i[2] => mem_access.IN1
|
||||||
ben_i[3] => mem_access.IN1
|
ben_i[3] => mem_access.IN1
|
||||||
addr_i[0] => ~NO_FANOUT~
|
addr_i[0] => ~NO_FANOUT~
|
||||||
addr_i[1] => ~NO_FANOUT~
|
addr_i[1] => ~NO_FANOUT~
|
||||||
addr_i[2] => mem_ram_b0~12.DATAIN
|
addr_i[2] => mem_ram_b0~11.DATAIN
|
||||||
addr_i[2] => mem_ram_b1~13.DATAIN
|
addr_i[2] => mem_ram_b1~12.DATAIN
|
||||||
addr_i[2] => mem_ram_b2~13.DATAIN
|
addr_i[2] => mem_ram_b2~12.DATAIN
|
||||||
addr_i[2] => mem_ram_b3~13.DATAIN
|
addr_i[2] => mem_ram_b3~12.DATAIN
|
||||||
addr_i[2] => mem_ram_b0.WADDR
|
addr_i[2] => mem_ram_b0.WADDR
|
||||||
addr_i[2] => mem_ram_b0.RADDR
|
addr_i[2] => mem_ram_b0.RADDR
|
||||||
addr_i[2] => mem_ram_b1.WADDR
|
addr_i[2] => mem_ram_b1.WADDR
|
||||||
|
|
@ -11332,10 +11328,10 @@ addr_i[2] => mem_ram_b2.WADDR
|
||||||
addr_i[2] => mem_ram_b2.RADDR
|
addr_i[2] => mem_ram_b2.RADDR
|
||||||
addr_i[2] => mem_ram_b3.WADDR
|
addr_i[2] => mem_ram_b3.WADDR
|
||||||
addr_i[2] => mem_ram_b3.RADDR
|
addr_i[2] => mem_ram_b3.RADDR
|
||||||
addr_i[3] => mem_ram_b0~11.DATAIN
|
addr_i[3] => mem_ram_b0~10.DATAIN
|
||||||
addr_i[3] => mem_ram_b1~12.DATAIN
|
addr_i[3] => mem_ram_b1~11.DATAIN
|
||||||
addr_i[3] => mem_ram_b2~12.DATAIN
|
addr_i[3] => mem_ram_b2~11.DATAIN
|
||||||
addr_i[3] => mem_ram_b3~12.DATAIN
|
addr_i[3] => mem_ram_b3~11.DATAIN
|
||||||
addr_i[3] => mem_ram_b0.WADDR1
|
addr_i[3] => mem_ram_b0.WADDR1
|
||||||
addr_i[3] => mem_ram_b0.RADDR1
|
addr_i[3] => mem_ram_b0.RADDR1
|
||||||
addr_i[3] => mem_ram_b1.WADDR1
|
addr_i[3] => mem_ram_b1.WADDR1
|
||||||
|
|
@ -11344,10 +11340,10 @@ addr_i[3] => mem_ram_b2.WADDR1
|
||||||
addr_i[3] => mem_ram_b2.RADDR1
|
addr_i[3] => mem_ram_b2.RADDR1
|
||||||
addr_i[3] => mem_ram_b3.WADDR1
|
addr_i[3] => mem_ram_b3.WADDR1
|
||||||
addr_i[3] => mem_ram_b3.RADDR1
|
addr_i[3] => mem_ram_b3.RADDR1
|
||||||
addr_i[4] => mem_ram_b0~10.DATAIN
|
addr_i[4] => mem_ram_b0~9.DATAIN
|
||||||
addr_i[4] => mem_ram_b1~11.DATAIN
|
addr_i[4] => mem_ram_b1~10.DATAIN
|
||||||
addr_i[4] => mem_ram_b2~11.DATAIN
|
addr_i[4] => mem_ram_b2~10.DATAIN
|
||||||
addr_i[4] => mem_ram_b3~11.DATAIN
|
addr_i[4] => mem_ram_b3~10.DATAIN
|
||||||
addr_i[4] => mem_ram_b0.WADDR2
|
addr_i[4] => mem_ram_b0.WADDR2
|
||||||
addr_i[4] => mem_ram_b0.RADDR2
|
addr_i[4] => mem_ram_b0.RADDR2
|
||||||
addr_i[4] => mem_ram_b1.WADDR2
|
addr_i[4] => mem_ram_b1.WADDR2
|
||||||
|
|
@ -11356,10 +11352,10 @@ addr_i[4] => mem_ram_b2.WADDR2
|
||||||
addr_i[4] => mem_ram_b2.RADDR2
|
addr_i[4] => mem_ram_b2.RADDR2
|
||||||
addr_i[4] => mem_ram_b3.WADDR2
|
addr_i[4] => mem_ram_b3.WADDR2
|
||||||
addr_i[4] => mem_ram_b3.RADDR2
|
addr_i[4] => mem_ram_b3.RADDR2
|
||||||
addr_i[5] => mem_ram_b0~9.DATAIN
|
addr_i[5] => mem_ram_b0~8.DATAIN
|
||||||
addr_i[5] => mem_ram_b1~10.DATAIN
|
addr_i[5] => mem_ram_b1~9.DATAIN
|
||||||
addr_i[5] => mem_ram_b2~10.DATAIN
|
addr_i[5] => mem_ram_b2~9.DATAIN
|
||||||
addr_i[5] => mem_ram_b3~10.DATAIN
|
addr_i[5] => mem_ram_b3~9.DATAIN
|
||||||
addr_i[5] => mem_ram_b0.WADDR3
|
addr_i[5] => mem_ram_b0.WADDR3
|
||||||
addr_i[5] => mem_ram_b0.RADDR3
|
addr_i[5] => mem_ram_b0.RADDR3
|
||||||
addr_i[5] => mem_ram_b1.WADDR3
|
addr_i[5] => mem_ram_b1.WADDR3
|
||||||
|
|
@ -11368,10 +11364,10 @@ addr_i[5] => mem_ram_b2.WADDR3
|
||||||
addr_i[5] => mem_ram_b2.RADDR3
|
addr_i[5] => mem_ram_b2.RADDR3
|
||||||
addr_i[5] => mem_ram_b3.WADDR3
|
addr_i[5] => mem_ram_b3.WADDR3
|
||||||
addr_i[5] => mem_ram_b3.RADDR3
|
addr_i[5] => mem_ram_b3.RADDR3
|
||||||
addr_i[6] => mem_ram_b0~8.DATAIN
|
addr_i[6] => mem_ram_b0~7.DATAIN
|
||||||
addr_i[6] => mem_ram_b1~9.DATAIN
|
addr_i[6] => mem_ram_b1~8.DATAIN
|
||||||
addr_i[6] => mem_ram_b2~9.DATAIN
|
addr_i[6] => mem_ram_b2~8.DATAIN
|
||||||
addr_i[6] => mem_ram_b3~9.DATAIN
|
addr_i[6] => mem_ram_b3~8.DATAIN
|
||||||
addr_i[6] => mem_ram_b0.WADDR4
|
addr_i[6] => mem_ram_b0.WADDR4
|
||||||
addr_i[6] => mem_ram_b0.RADDR4
|
addr_i[6] => mem_ram_b0.RADDR4
|
||||||
addr_i[6] => mem_ram_b1.WADDR4
|
addr_i[6] => mem_ram_b1.WADDR4
|
||||||
|
|
@ -11380,10 +11376,10 @@ addr_i[6] => mem_ram_b2.WADDR4
|
||||||
addr_i[6] => mem_ram_b2.RADDR4
|
addr_i[6] => mem_ram_b2.RADDR4
|
||||||
addr_i[6] => mem_ram_b3.WADDR4
|
addr_i[6] => mem_ram_b3.WADDR4
|
||||||
addr_i[6] => mem_ram_b3.RADDR4
|
addr_i[6] => mem_ram_b3.RADDR4
|
||||||
addr_i[7] => mem_ram_b0~7.DATAIN
|
addr_i[7] => mem_ram_b0~6.DATAIN
|
||||||
addr_i[7] => mem_ram_b1~8.DATAIN
|
addr_i[7] => mem_ram_b1~7.DATAIN
|
||||||
addr_i[7] => mem_ram_b2~8.DATAIN
|
addr_i[7] => mem_ram_b2~7.DATAIN
|
||||||
addr_i[7] => mem_ram_b3~8.DATAIN
|
addr_i[7] => mem_ram_b3~7.DATAIN
|
||||||
addr_i[7] => mem_ram_b0.WADDR5
|
addr_i[7] => mem_ram_b0.WADDR5
|
||||||
addr_i[7] => mem_ram_b0.RADDR5
|
addr_i[7] => mem_ram_b0.RADDR5
|
||||||
addr_i[7] => mem_ram_b1.WADDR5
|
addr_i[7] => mem_ram_b1.WADDR5
|
||||||
|
|
@ -11392,10 +11388,10 @@ addr_i[7] => mem_ram_b2.WADDR5
|
||||||
addr_i[7] => mem_ram_b2.RADDR5
|
addr_i[7] => mem_ram_b2.RADDR5
|
||||||
addr_i[7] => mem_ram_b3.WADDR5
|
addr_i[7] => mem_ram_b3.WADDR5
|
||||||
addr_i[7] => mem_ram_b3.RADDR5
|
addr_i[7] => mem_ram_b3.RADDR5
|
||||||
addr_i[8] => mem_ram_b0~6.DATAIN
|
addr_i[8] => mem_ram_b0~5.DATAIN
|
||||||
addr_i[8] => mem_ram_b1~7.DATAIN
|
addr_i[8] => mem_ram_b1~6.DATAIN
|
||||||
addr_i[8] => mem_ram_b2~7.DATAIN
|
addr_i[8] => mem_ram_b2~6.DATAIN
|
||||||
addr_i[8] => mem_ram_b3~7.DATAIN
|
addr_i[8] => mem_ram_b3~6.DATAIN
|
||||||
addr_i[8] => mem_ram_b0.WADDR6
|
addr_i[8] => mem_ram_b0.WADDR6
|
||||||
addr_i[8] => mem_ram_b0.RADDR6
|
addr_i[8] => mem_ram_b0.RADDR6
|
||||||
addr_i[8] => mem_ram_b1.WADDR6
|
addr_i[8] => mem_ram_b1.WADDR6
|
||||||
|
|
@ -11404,10 +11400,10 @@ addr_i[8] => mem_ram_b2.WADDR6
|
||||||
addr_i[8] => mem_ram_b2.RADDR6
|
addr_i[8] => mem_ram_b2.RADDR6
|
||||||
addr_i[8] => mem_ram_b3.WADDR6
|
addr_i[8] => mem_ram_b3.WADDR6
|
||||||
addr_i[8] => mem_ram_b3.RADDR6
|
addr_i[8] => mem_ram_b3.RADDR6
|
||||||
addr_i[9] => mem_ram_b0~5.DATAIN
|
addr_i[9] => mem_ram_b0~4.DATAIN
|
||||||
addr_i[9] => mem_ram_b1~6.DATAIN
|
addr_i[9] => mem_ram_b1~5.DATAIN
|
||||||
addr_i[9] => mem_ram_b2~6.DATAIN
|
addr_i[9] => mem_ram_b2~5.DATAIN
|
||||||
addr_i[9] => mem_ram_b3~6.DATAIN
|
addr_i[9] => mem_ram_b3~5.DATAIN
|
||||||
addr_i[9] => mem_ram_b0.WADDR7
|
addr_i[9] => mem_ram_b0.WADDR7
|
||||||
addr_i[9] => mem_ram_b0.RADDR7
|
addr_i[9] => mem_ram_b0.RADDR7
|
||||||
addr_i[9] => mem_ram_b1.WADDR7
|
addr_i[9] => mem_ram_b1.WADDR7
|
||||||
|
|
@ -11416,10 +11412,10 @@ addr_i[9] => mem_ram_b2.WADDR7
|
||||||
addr_i[9] => mem_ram_b2.RADDR7
|
addr_i[9] => mem_ram_b2.RADDR7
|
||||||
addr_i[9] => mem_ram_b3.WADDR7
|
addr_i[9] => mem_ram_b3.WADDR7
|
||||||
addr_i[9] => mem_ram_b3.RADDR7
|
addr_i[9] => mem_ram_b3.RADDR7
|
||||||
addr_i[10] => mem_ram_b0~4.DATAIN
|
addr_i[10] => mem_ram_b0~3.DATAIN
|
||||||
addr_i[10] => mem_ram_b1~5.DATAIN
|
addr_i[10] => mem_ram_b1~4.DATAIN
|
||||||
addr_i[10] => mem_ram_b2~5.DATAIN
|
addr_i[10] => mem_ram_b2~4.DATAIN
|
||||||
addr_i[10] => mem_ram_b3~5.DATAIN
|
addr_i[10] => mem_ram_b3~4.DATAIN
|
||||||
addr_i[10] => mem_ram_b0.WADDR8
|
addr_i[10] => mem_ram_b0.WADDR8
|
||||||
addr_i[10] => mem_ram_b0.RADDR8
|
addr_i[10] => mem_ram_b0.RADDR8
|
||||||
addr_i[10] => mem_ram_b1.WADDR8
|
addr_i[10] => mem_ram_b1.WADDR8
|
||||||
|
|
@ -11428,10 +11424,10 @@ addr_i[10] => mem_ram_b2.WADDR8
|
||||||
addr_i[10] => mem_ram_b2.RADDR8
|
addr_i[10] => mem_ram_b2.RADDR8
|
||||||
addr_i[10] => mem_ram_b3.WADDR8
|
addr_i[10] => mem_ram_b3.WADDR8
|
||||||
addr_i[10] => mem_ram_b3.RADDR8
|
addr_i[10] => mem_ram_b3.RADDR8
|
||||||
addr_i[11] => mem_ram_b0~3.DATAIN
|
addr_i[11] => mem_ram_b0~2.DATAIN
|
||||||
addr_i[11] => mem_ram_b1~4.DATAIN
|
addr_i[11] => mem_ram_b1~3.DATAIN
|
||||||
addr_i[11] => mem_ram_b2~4.DATAIN
|
addr_i[11] => mem_ram_b2~3.DATAIN
|
||||||
addr_i[11] => mem_ram_b3~4.DATAIN
|
addr_i[11] => mem_ram_b3~3.DATAIN
|
||||||
addr_i[11] => mem_ram_b0.WADDR9
|
addr_i[11] => mem_ram_b0.WADDR9
|
||||||
addr_i[11] => mem_ram_b0.RADDR9
|
addr_i[11] => mem_ram_b0.RADDR9
|
||||||
addr_i[11] => mem_ram_b1.WADDR9
|
addr_i[11] => mem_ram_b1.WADDR9
|
||||||
|
|
@ -11440,10 +11436,10 @@ addr_i[11] => mem_ram_b2.WADDR9
|
||||||
addr_i[11] => mem_ram_b2.RADDR9
|
addr_i[11] => mem_ram_b2.RADDR9
|
||||||
addr_i[11] => mem_ram_b3.WADDR9
|
addr_i[11] => mem_ram_b3.WADDR9
|
||||||
addr_i[11] => mem_ram_b3.RADDR9
|
addr_i[11] => mem_ram_b3.RADDR9
|
||||||
addr_i[12] => mem_ram_b0~2.DATAIN
|
addr_i[12] => mem_ram_b0~1.DATAIN
|
||||||
addr_i[12] => mem_ram_b1~3.DATAIN
|
addr_i[12] => mem_ram_b1~2.DATAIN
|
||||||
addr_i[12] => mem_ram_b2~3.DATAIN
|
addr_i[12] => mem_ram_b2~2.DATAIN
|
||||||
addr_i[12] => mem_ram_b3~3.DATAIN
|
addr_i[12] => mem_ram_b3~2.DATAIN
|
||||||
addr_i[12] => mem_ram_b0.WADDR10
|
addr_i[12] => mem_ram_b0.WADDR10
|
||||||
addr_i[12] => mem_ram_b0.RADDR10
|
addr_i[12] => mem_ram_b0.RADDR10
|
||||||
addr_i[12] => mem_ram_b1.WADDR10
|
addr_i[12] => mem_ram_b1.WADDR10
|
||||||
|
|
@ -11452,10 +11448,10 @@ addr_i[12] => mem_ram_b2.WADDR10
|
||||||
addr_i[12] => mem_ram_b2.RADDR10
|
addr_i[12] => mem_ram_b2.RADDR10
|
||||||
addr_i[12] => mem_ram_b3.WADDR10
|
addr_i[12] => mem_ram_b3.WADDR10
|
||||||
addr_i[12] => mem_ram_b3.RADDR10
|
addr_i[12] => mem_ram_b3.RADDR10
|
||||||
addr_i[13] => mem_ram_b0~1.DATAIN
|
addr_i[13] => mem_ram_b0~0.DATAIN
|
||||||
addr_i[13] => mem_ram_b1~2.DATAIN
|
addr_i[13] => mem_ram_b1~1.DATAIN
|
||||||
addr_i[13] => mem_ram_b2~2.DATAIN
|
addr_i[13] => mem_ram_b2~1.DATAIN
|
||||||
addr_i[13] => mem_ram_b3~2.DATAIN
|
addr_i[13] => mem_ram_b3~1.DATAIN
|
||||||
addr_i[13] => mem_ram_b0.WADDR11
|
addr_i[13] => mem_ram_b0.WADDR11
|
||||||
addr_i[13] => mem_ram_b0.RADDR11
|
addr_i[13] => mem_ram_b0.RADDR11
|
||||||
addr_i[13] => mem_ram_b1.WADDR11
|
addr_i[13] => mem_ram_b1.WADDR11
|
||||||
|
|
@ -11464,18 +11460,7 @@ addr_i[13] => mem_ram_b2.WADDR11
|
||||||
addr_i[13] => mem_ram_b2.RADDR11
|
addr_i[13] => mem_ram_b2.RADDR11
|
||||||
addr_i[13] => mem_ram_b3.WADDR11
|
addr_i[13] => mem_ram_b3.WADDR11
|
||||||
addr_i[13] => mem_ram_b3.RADDR11
|
addr_i[13] => mem_ram_b3.RADDR11
|
||||||
addr_i[14] => mem_ram_b0~0.DATAIN
|
addr_i[14] => Equal0.IN17
|
||||||
addr_i[14] => mem_ram_b1~1.DATAIN
|
|
||||||
addr_i[14] => mem_ram_b2~1.DATAIN
|
|
||||||
addr_i[14] => mem_ram_b3~1.DATAIN
|
|
||||||
addr_i[14] => mem_ram_b0.WADDR12
|
|
||||||
addr_i[14] => mem_ram_b0.RADDR12
|
|
||||||
addr_i[14] => mem_ram_b1.WADDR12
|
|
||||||
addr_i[14] => mem_ram_b1.RADDR12
|
|
||||||
addr_i[14] => mem_ram_b2.WADDR12
|
|
||||||
addr_i[14] => mem_ram_b2.RADDR12
|
|
||||||
addr_i[14] => mem_ram_b3.WADDR12
|
|
||||||
addr_i[14] => mem_ram_b3.RADDR12
|
|
||||||
addr_i[15] => Equal0.IN16
|
addr_i[15] => Equal0.IN16
|
||||||
addr_i[16] => Equal0.IN15
|
addr_i[16] => Equal0.IN15
|
||||||
addr_i[17] => Equal0.IN14
|
addr_i[17] => Equal0.IN14
|
||||||
|
|
@ -11493,69 +11478,69 @@ addr_i[28] => Equal0.IN3
|
||||||
addr_i[29] => Equal0.IN2
|
addr_i[29] => Equal0.IN2
|
||||||
addr_i[30] => Equal0.IN1
|
addr_i[30] => Equal0.IN1
|
||||||
addr_i[31] => Equal0.IN0
|
addr_i[31] => Equal0.IN0
|
||||||
data_i[0] => mem_ram_b0~20.DATAIN
|
data_i[0] => mem_ram_b0~19.DATAIN
|
||||||
data_i[0] => mem_ram_b0.DATAIN
|
data_i[0] => mem_ram_b0.DATAIN
|
||||||
data_i[1] => mem_ram_b0~19.DATAIN
|
data_i[1] => mem_ram_b0~18.DATAIN
|
||||||
data_i[1] => mem_ram_b0.DATAIN1
|
data_i[1] => mem_ram_b0.DATAIN1
|
||||||
data_i[2] => mem_ram_b0~18.DATAIN
|
data_i[2] => mem_ram_b0~17.DATAIN
|
||||||
data_i[2] => mem_ram_b0.DATAIN2
|
data_i[2] => mem_ram_b0.DATAIN2
|
||||||
data_i[3] => mem_ram_b0~17.DATAIN
|
data_i[3] => mem_ram_b0~16.DATAIN
|
||||||
data_i[3] => mem_ram_b0.DATAIN3
|
data_i[3] => mem_ram_b0.DATAIN3
|
||||||
data_i[4] => mem_ram_b0~16.DATAIN
|
data_i[4] => mem_ram_b0~15.DATAIN
|
||||||
data_i[4] => mem_ram_b0.DATAIN4
|
data_i[4] => mem_ram_b0.DATAIN4
|
||||||
data_i[5] => mem_ram_b0~15.DATAIN
|
data_i[5] => mem_ram_b0~14.DATAIN
|
||||||
data_i[5] => mem_ram_b0.DATAIN5
|
data_i[5] => mem_ram_b0.DATAIN5
|
||||||
data_i[6] => mem_ram_b0~14.DATAIN
|
data_i[6] => mem_ram_b0~13.DATAIN
|
||||||
data_i[6] => mem_ram_b0.DATAIN6
|
data_i[6] => mem_ram_b0.DATAIN6
|
||||||
data_i[7] => mem_ram_b0~13.DATAIN
|
data_i[7] => mem_ram_b0~12.DATAIN
|
||||||
data_i[7] => mem_ram_b0.DATAIN7
|
data_i[7] => mem_ram_b0.DATAIN7
|
||||||
data_i[8] => mem_ram_b1~21.DATAIN
|
data_i[8] => mem_ram_b1~20.DATAIN
|
||||||
data_i[8] => mem_ram_b1.DATAIN
|
data_i[8] => mem_ram_b1.DATAIN
|
||||||
data_i[9] => mem_ram_b1~20.DATAIN
|
data_i[9] => mem_ram_b1~19.DATAIN
|
||||||
data_i[9] => mem_ram_b1.DATAIN1
|
data_i[9] => mem_ram_b1.DATAIN1
|
||||||
data_i[10] => mem_ram_b1~19.DATAIN
|
data_i[10] => mem_ram_b1~18.DATAIN
|
||||||
data_i[10] => mem_ram_b1.DATAIN2
|
data_i[10] => mem_ram_b1.DATAIN2
|
||||||
data_i[11] => mem_ram_b1~18.DATAIN
|
data_i[11] => mem_ram_b1~17.DATAIN
|
||||||
data_i[11] => mem_ram_b1.DATAIN3
|
data_i[11] => mem_ram_b1.DATAIN3
|
||||||
data_i[12] => mem_ram_b1~17.DATAIN
|
data_i[12] => mem_ram_b1~16.DATAIN
|
||||||
data_i[12] => mem_ram_b1.DATAIN4
|
data_i[12] => mem_ram_b1.DATAIN4
|
||||||
data_i[13] => mem_ram_b1~16.DATAIN
|
data_i[13] => mem_ram_b1~15.DATAIN
|
||||||
data_i[13] => mem_ram_b1.DATAIN5
|
data_i[13] => mem_ram_b1.DATAIN5
|
||||||
data_i[14] => mem_ram_b1~15.DATAIN
|
data_i[14] => mem_ram_b1~14.DATAIN
|
||||||
data_i[14] => mem_ram_b1.DATAIN6
|
data_i[14] => mem_ram_b1.DATAIN6
|
||||||
data_i[15] => mem_ram_b1~14.DATAIN
|
data_i[15] => mem_ram_b1~13.DATAIN
|
||||||
data_i[15] => mem_ram_b1.DATAIN7
|
data_i[15] => mem_ram_b1.DATAIN7
|
||||||
data_i[16] => mem_ram_b2~21.DATAIN
|
data_i[16] => mem_ram_b2~20.DATAIN
|
||||||
data_i[16] => mem_ram_b2.DATAIN
|
data_i[16] => mem_ram_b2.DATAIN
|
||||||
data_i[17] => mem_ram_b2~20.DATAIN
|
data_i[17] => mem_ram_b2~19.DATAIN
|
||||||
data_i[17] => mem_ram_b2.DATAIN1
|
data_i[17] => mem_ram_b2.DATAIN1
|
||||||
data_i[18] => mem_ram_b2~19.DATAIN
|
data_i[18] => mem_ram_b2~18.DATAIN
|
||||||
data_i[18] => mem_ram_b2.DATAIN2
|
data_i[18] => mem_ram_b2.DATAIN2
|
||||||
data_i[19] => mem_ram_b2~18.DATAIN
|
data_i[19] => mem_ram_b2~17.DATAIN
|
||||||
data_i[19] => mem_ram_b2.DATAIN3
|
data_i[19] => mem_ram_b2.DATAIN3
|
||||||
data_i[20] => mem_ram_b2~17.DATAIN
|
data_i[20] => mem_ram_b2~16.DATAIN
|
||||||
data_i[20] => mem_ram_b2.DATAIN4
|
data_i[20] => mem_ram_b2.DATAIN4
|
||||||
data_i[21] => mem_ram_b2~16.DATAIN
|
data_i[21] => mem_ram_b2~15.DATAIN
|
||||||
data_i[21] => mem_ram_b2.DATAIN5
|
data_i[21] => mem_ram_b2.DATAIN5
|
||||||
data_i[22] => mem_ram_b2~15.DATAIN
|
data_i[22] => mem_ram_b2~14.DATAIN
|
||||||
data_i[22] => mem_ram_b2.DATAIN6
|
data_i[22] => mem_ram_b2.DATAIN6
|
||||||
data_i[23] => mem_ram_b2~14.DATAIN
|
data_i[23] => mem_ram_b2~13.DATAIN
|
||||||
data_i[23] => mem_ram_b2.DATAIN7
|
data_i[23] => mem_ram_b2.DATAIN7
|
||||||
data_i[24] => mem_ram_b3~21.DATAIN
|
data_i[24] => mem_ram_b3~20.DATAIN
|
||||||
data_i[24] => mem_ram_b3.DATAIN
|
data_i[24] => mem_ram_b3.DATAIN
|
||||||
data_i[25] => mem_ram_b3~20.DATAIN
|
data_i[25] => mem_ram_b3~19.DATAIN
|
||||||
data_i[25] => mem_ram_b3.DATAIN1
|
data_i[25] => mem_ram_b3.DATAIN1
|
||||||
data_i[26] => mem_ram_b3~19.DATAIN
|
data_i[26] => mem_ram_b3~18.DATAIN
|
||||||
data_i[26] => mem_ram_b3.DATAIN2
|
data_i[26] => mem_ram_b3.DATAIN2
|
||||||
data_i[27] => mem_ram_b3~18.DATAIN
|
data_i[27] => mem_ram_b3~17.DATAIN
|
||||||
data_i[27] => mem_ram_b3.DATAIN3
|
data_i[27] => mem_ram_b3.DATAIN3
|
||||||
data_i[28] => mem_ram_b3~17.DATAIN
|
data_i[28] => mem_ram_b3~16.DATAIN
|
||||||
data_i[28] => mem_ram_b3.DATAIN4
|
data_i[28] => mem_ram_b3.DATAIN4
|
||||||
data_i[29] => mem_ram_b3~16.DATAIN
|
data_i[29] => mem_ram_b3~15.DATAIN
|
||||||
data_i[29] => mem_ram_b3.DATAIN5
|
data_i[29] => mem_ram_b3.DATAIN5
|
||||||
data_i[30] => mem_ram_b3~15.DATAIN
|
data_i[30] => mem_ram_b3~14.DATAIN
|
||||||
data_i[30] => mem_ram_b3.DATAIN6
|
data_i[30] => mem_ram_b3.DATAIN6
|
||||||
data_i[31] => mem_ram_b3~14.DATAIN
|
data_i[31] => mem_ram_b3~13.DATAIN
|
||||||
data_i[31] => mem_ram_b3.DATAIN7
|
data_i[31] => mem_ram_b3.DATAIN7
|
||||||
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
@ -11594,7 +11579,7 @@ err_o <= err_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
||||||
|
|
||||||
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_dmem:\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_dmem:\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst
|
||||||
clk_i => mem_ram_b0~21.CLK
|
clk_i => mem_ram_b0~23.CLK
|
||||||
clk_i => mem_ram_b0~0.CLK
|
clk_i => mem_ram_b0~0.CLK
|
||||||
clk_i => mem_ram_b0~1.CLK
|
clk_i => mem_ram_b0~1.CLK
|
||||||
clk_i => mem_ram_b0~2.CLK
|
clk_i => mem_ram_b0~2.CLK
|
||||||
|
|
@ -11616,6 +11601,8 @@ clk_i => mem_ram_b0~17.CLK
|
||||||
clk_i => mem_ram_b0~18.CLK
|
clk_i => mem_ram_b0~18.CLK
|
||||||
clk_i => mem_ram_b0~19.CLK
|
clk_i => mem_ram_b0~19.CLK
|
||||||
clk_i => mem_ram_b0~20.CLK
|
clk_i => mem_ram_b0~20.CLK
|
||||||
|
clk_i => mem_ram_b0~21.CLK
|
||||||
|
clk_i => mem_ram_b0~22.CLK
|
||||||
clk_i => mem_ram_b1~0.CLK
|
clk_i => mem_ram_b1~0.CLK
|
||||||
clk_i => mem_ram_b1~1.CLK
|
clk_i => mem_ram_b1~1.CLK
|
||||||
clk_i => mem_ram_b1~2.CLK
|
clk_i => mem_ram_b1~2.CLK
|
||||||
|
|
@ -11638,6 +11625,8 @@ clk_i => mem_ram_b1~18.CLK
|
||||||
clk_i => mem_ram_b1~19.CLK
|
clk_i => mem_ram_b1~19.CLK
|
||||||
clk_i => mem_ram_b1~20.CLK
|
clk_i => mem_ram_b1~20.CLK
|
||||||
clk_i => mem_ram_b1~21.CLK
|
clk_i => mem_ram_b1~21.CLK
|
||||||
|
clk_i => mem_ram_b1~22.CLK
|
||||||
|
clk_i => mem_ram_b1~23.CLK
|
||||||
clk_i => mem_ram_b2~0.CLK
|
clk_i => mem_ram_b2~0.CLK
|
||||||
clk_i => mem_ram_b2~1.CLK
|
clk_i => mem_ram_b2~1.CLK
|
||||||
clk_i => mem_ram_b2~2.CLK
|
clk_i => mem_ram_b2~2.CLK
|
||||||
|
|
@ -11660,6 +11649,8 @@ clk_i => mem_ram_b2~18.CLK
|
||||||
clk_i => mem_ram_b2~19.CLK
|
clk_i => mem_ram_b2~19.CLK
|
||||||
clk_i => mem_ram_b2~20.CLK
|
clk_i => mem_ram_b2~20.CLK
|
||||||
clk_i => mem_ram_b2~21.CLK
|
clk_i => mem_ram_b2~21.CLK
|
||||||
|
clk_i => mem_ram_b2~22.CLK
|
||||||
|
clk_i => mem_ram_b2~23.CLK
|
||||||
clk_i => mem_ram_b3~0.CLK
|
clk_i => mem_ram_b3~0.CLK
|
||||||
clk_i => mem_ram_b3~1.CLK
|
clk_i => mem_ram_b3~1.CLK
|
||||||
clk_i => mem_ram_b3~2.CLK
|
clk_i => mem_ram_b3~2.CLK
|
||||||
|
|
@ -11682,6 +11673,8 @@ clk_i => mem_ram_b3~18.CLK
|
||||||
clk_i => mem_ram_b3~19.CLK
|
clk_i => mem_ram_b3~19.CLK
|
||||||
clk_i => mem_ram_b3~20.CLK
|
clk_i => mem_ram_b3~20.CLK
|
||||||
clk_i => mem_ram_b3~21.CLK
|
clk_i => mem_ram_b3~21.CLK
|
||||||
|
clk_i => mem_ram_b3~22.CLK
|
||||||
|
clk_i => mem_ram_b3~23.CLK
|
||||||
clk_i => ack_o~reg0.CLK
|
clk_i => ack_o~reg0.CLK
|
||||||
clk_i => rden.CLK
|
clk_i => rden.CLK
|
||||||
clk_i => mem_ram_b3_rd[0].CLK
|
clk_i => mem_ram_b3_rd[0].CLK
|
||||||
|
|
@ -11733,10 +11726,10 @@ ben_i[2] => mem_access.IN1
|
||||||
ben_i[3] => mem_access.IN1
|
ben_i[3] => mem_access.IN1
|
||||||
addr_i[0] => ~NO_FANOUT~
|
addr_i[0] => ~NO_FANOUT~
|
||||||
addr_i[1] => ~NO_FANOUT~
|
addr_i[1] => ~NO_FANOUT~
|
||||||
addr_i[2] => mem_ram_b0~12.DATAIN
|
addr_i[2] => mem_ram_b0~14.DATAIN
|
||||||
addr_i[2] => mem_ram_b1~13.DATAIN
|
addr_i[2] => mem_ram_b1~15.DATAIN
|
||||||
addr_i[2] => mem_ram_b2~13.DATAIN
|
addr_i[2] => mem_ram_b2~15.DATAIN
|
||||||
addr_i[2] => mem_ram_b3~13.DATAIN
|
addr_i[2] => mem_ram_b3~15.DATAIN
|
||||||
addr_i[2] => mem_ram_b0.WADDR
|
addr_i[2] => mem_ram_b0.WADDR
|
||||||
addr_i[2] => mem_ram_b0.RADDR
|
addr_i[2] => mem_ram_b0.RADDR
|
||||||
addr_i[2] => mem_ram_b1.WADDR
|
addr_i[2] => mem_ram_b1.WADDR
|
||||||
|
|
@ -11745,10 +11738,10 @@ addr_i[2] => mem_ram_b2.WADDR
|
||||||
addr_i[2] => mem_ram_b2.RADDR
|
addr_i[2] => mem_ram_b2.RADDR
|
||||||
addr_i[2] => mem_ram_b3.WADDR
|
addr_i[2] => mem_ram_b3.WADDR
|
||||||
addr_i[2] => mem_ram_b3.RADDR
|
addr_i[2] => mem_ram_b3.RADDR
|
||||||
addr_i[3] => mem_ram_b0~11.DATAIN
|
addr_i[3] => mem_ram_b0~13.DATAIN
|
||||||
addr_i[3] => mem_ram_b1~12.DATAIN
|
addr_i[3] => mem_ram_b1~14.DATAIN
|
||||||
addr_i[3] => mem_ram_b2~12.DATAIN
|
addr_i[3] => mem_ram_b2~14.DATAIN
|
||||||
addr_i[3] => mem_ram_b3~12.DATAIN
|
addr_i[3] => mem_ram_b3~14.DATAIN
|
||||||
addr_i[3] => mem_ram_b0.WADDR1
|
addr_i[3] => mem_ram_b0.WADDR1
|
||||||
addr_i[3] => mem_ram_b0.RADDR1
|
addr_i[3] => mem_ram_b0.RADDR1
|
||||||
addr_i[3] => mem_ram_b1.WADDR1
|
addr_i[3] => mem_ram_b1.WADDR1
|
||||||
|
|
@ -11757,10 +11750,10 @@ addr_i[3] => mem_ram_b2.WADDR1
|
||||||
addr_i[3] => mem_ram_b2.RADDR1
|
addr_i[3] => mem_ram_b2.RADDR1
|
||||||
addr_i[3] => mem_ram_b3.WADDR1
|
addr_i[3] => mem_ram_b3.WADDR1
|
||||||
addr_i[3] => mem_ram_b3.RADDR1
|
addr_i[3] => mem_ram_b3.RADDR1
|
||||||
addr_i[4] => mem_ram_b0~10.DATAIN
|
addr_i[4] => mem_ram_b0~12.DATAIN
|
||||||
addr_i[4] => mem_ram_b1~11.DATAIN
|
addr_i[4] => mem_ram_b1~13.DATAIN
|
||||||
addr_i[4] => mem_ram_b2~11.DATAIN
|
addr_i[4] => mem_ram_b2~13.DATAIN
|
||||||
addr_i[4] => mem_ram_b3~11.DATAIN
|
addr_i[4] => mem_ram_b3~13.DATAIN
|
||||||
addr_i[4] => mem_ram_b0.WADDR2
|
addr_i[4] => mem_ram_b0.WADDR2
|
||||||
addr_i[4] => mem_ram_b0.RADDR2
|
addr_i[4] => mem_ram_b0.RADDR2
|
||||||
addr_i[4] => mem_ram_b1.WADDR2
|
addr_i[4] => mem_ram_b1.WADDR2
|
||||||
|
|
@ -11769,10 +11762,10 @@ addr_i[4] => mem_ram_b2.WADDR2
|
||||||
addr_i[4] => mem_ram_b2.RADDR2
|
addr_i[4] => mem_ram_b2.RADDR2
|
||||||
addr_i[4] => mem_ram_b3.WADDR2
|
addr_i[4] => mem_ram_b3.WADDR2
|
||||||
addr_i[4] => mem_ram_b3.RADDR2
|
addr_i[4] => mem_ram_b3.RADDR2
|
||||||
addr_i[5] => mem_ram_b0~9.DATAIN
|
addr_i[5] => mem_ram_b0~11.DATAIN
|
||||||
addr_i[5] => mem_ram_b1~10.DATAIN
|
addr_i[5] => mem_ram_b1~12.DATAIN
|
||||||
addr_i[5] => mem_ram_b2~10.DATAIN
|
addr_i[5] => mem_ram_b2~12.DATAIN
|
||||||
addr_i[5] => mem_ram_b3~10.DATAIN
|
addr_i[5] => mem_ram_b3~12.DATAIN
|
||||||
addr_i[5] => mem_ram_b0.WADDR3
|
addr_i[5] => mem_ram_b0.WADDR3
|
||||||
addr_i[5] => mem_ram_b0.RADDR3
|
addr_i[5] => mem_ram_b0.RADDR3
|
||||||
addr_i[5] => mem_ram_b1.WADDR3
|
addr_i[5] => mem_ram_b1.WADDR3
|
||||||
|
|
@ -11781,10 +11774,10 @@ addr_i[5] => mem_ram_b2.WADDR3
|
||||||
addr_i[5] => mem_ram_b2.RADDR3
|
addr_i[5] => mem_ram_b2.RADDR3
|
||||||
addr_i[5] => mem_ram_b3.WADDR3
|
addr_i[5] => mem_ram_b3.WADDR3
|
||||||
addr_i[5] => mem_ram_b3.RADDR3
|
addr_i[5] => mem_ram_b3.RADDR3
|
||||||
addr_i[6] => mem_ram_b0~8.DATAIN
|
addr_i[6] => mem_ram_b0~10.DATAIN
|
||||||
addr_i[6] => mem_ram_b1~9.DATAIN
|
addr_i[6] => mem_ram_b1~11.DATAIN
|
||||||
addr_i[6] => mem_ram_b2~9.DATAIN
|
addr_i[6] => mem_ram_b2~11.DATAIN
|
||||||
addr_i[6] => mem_ram_b3~9.DATAIN
|
addr_i[6] => mem_ram_b3~11.DATAIN
|
||||||
addr_i[6] => mem_ram_b0.WADDR4
|
addr_i[6] => mem_ram_b0.WADDR4
|
||||||
addr_i[6] => mem_ram_b0.RADDR4
|
addr_i[6] => mem_ram_b0.RADDR4
|
||||||
addr_i[6] => mem_ram_b1.WADDR4
|
addr_i[6] => mem_ram_b1.WADDR4
|
||||||
|
|
@ -11793,10 +11786,10 @@ addr_i[6] => mem_ram_b2.WADDR4
|
||||||
addr_i[6] => mem_ram_b2.RADDR4
|
addr_i[6] => mem_ram_b2.RADDR4
|
||||||
addr_i[6] => mem_ram_b3.WADDR4
|
addr_i[6] => mem_ram_b3.WADDR4
|
||||||
addr_i[6] => mem_ram_b3.RADDR4
|
addr_i[6] => mem_ram_b3.RADDR4
|
||||||
addr_i[7] => mem_ram_b0~7.DATAIN
|
addr_i[7] => mem_ram_b0~9.DATAIN
|
||||||
addr_i[7] => mem_ram_b1~8.DATAIN
|
addr_i[7] => mem_ram_b1~10.DATAIN
|
||||||
addr_i[7] => mem_ram_b2~8.DATAIN
|
addr_i[7] => mem_ram_b2~10.DATAIN
|
||||||
addr_i[7] => mem_ram_b3~8.DATAIN
|
addr_i[7] => mem_ram_b3~10.DATAIN
|
||||||
addr_i[7] => mem_ram_b0.WADDR5
|
addr_i[7] => mem_ram_b0.WADDR5
|
||||||
addr_i[7] => mem_ram_b0.RADDR5
|
addr_i[7] => mem_ram_b0.RADDR5
|
||||||
addr_i[7] => mem_ram_b1.WADDR5
|
addr_i[7] => mem_ram_b1.WADDR5
|
||||||
|
|
@ -11805,10 +11798,10 @@ addr_i[7] => mem_ram_b2.WADDR5
|
||||||
addr_i[7] => mem_ram_b2.RADDR5
|
addr_i[7] => mem_ram_b2.RADDR5
|
||||||
addr_i[7] => mem_ram_b3.WADDR5
|
addr_i[7] => mem_ram_b3.WADDR5
|
||||||
addr_i[7] => mem_ram_b3.RADDR5
|
addr_i[7] => mem_ram_b3.RADDR5
|
||||||
addr_i[8] => mem_ram_b0~6.DATAIN
|
addr_i[8] => mem_ram_b0~8.DATAIN
|
||||||
addr_i[8] => mem_ram_b1~7.DATAIN
|
addr_i[8] => mem_ram_b1~9.DATAIN
|
||||||
addr_i[8] => mem_ram_b2~7.DATAIN
|
addr_i[8] => mem_ram_b2~9.DATAIN
|
||||||
addr_i[8] => mem_ram_b3~7.DATAIN
|
addr_i[8] => mem_ram_b3~9.DATAIN
|
||||||
addr_i[8] => mem_ram_b0.WADDR6
|
addr_i[8] => mem_ram_b0.WADDR6
|
||||||
addr_i[8] => mem_ram_b0.RADDR6
|
addr_i[8] => mem_ram_b0.RADDR6
|
||||||
addr_i[8] => mem_ram_b1.WADDR6
|
addr_i[8] => mem_ram_b1.WADDR6
|
||||||
|
|
@ -11817,10 +11810,10 @@ addr_i[8] => mem_ram_b2.WADDR6
|
||||||
addr_i[8] => mem_ram_b2.RADDR6
|
addr_i[8] => mem_ram_b2.RADDR6
|
||||||
addr_i[8] => mem_ram_b3.WADDR6
|
addr_i[8] => mem_ram_b3.WADDR6
|
||||||
addr_i[8] => mem_ram_b3.RADDR6
|
addr_i[8] => mem_ram_b3.RADDR6
|
||||||
addr_i[9] => mem_ram_b0~5.DATAIN
|
addr_i[9] => mem_ram_b0~7.DATAIN
|
||||||
addr_i[9] => mem_ram_b1~6.DATAIN
|
addr_i[9] => mem_ram_b1~8.DATAIN
|
||||||
addr_i[9] => mem_ram_b2~6.DATAIN
|
addr_i[9] => mem_ram_b2~8.DATAIN
|
||||||
addr_i[9] => mem_ram_b3~6.DATAIN
|
addr_i[9] => mem_ram_b3~8.DATAIN
|
||||||
addr_i[9] => mem_ram_b0.WADDR7
|
addr_i[9] => mem_ram_b0.WADDR7
|
||||||
addr_i[9] => mem_ram_b0.RADDR7
|
addr_i[9] => mem_ram_b0.RADDR7
|
||||||
addr_i[9] => mem_ram_b1.WADDR7
|
addr_i[9] => mem_ram_b1.WADDR7
|
||||||
|
|
@ -11829,10 +11822,10 @@ addr_i[9] => mem_ram_b2.WADDR7
|
||||||
addr_i[9] => mem_ram_b2.RADDR7
|
addr_i[9] => mem_ram_b2.RADDR7
|
||||||
addr_i[9] => mem_ram_b3.WADDR7
|
addr_i[9] => mem_ram_b3.WADDR7
|
||||||
addr_i[9] => mem_ram_b3.RADDR7
|
addr_i[9] => mem_ram_b3.RADDR7
|
||||||
addr_i[10] => mem_ram_b0~4.DATAIN
|
addr_i[10] => mem_ram_b0~6.DATAIN
|
||||||
addr_i[10] => mem_ram_b1~5.DATAIN
|
addr_i[10] => mem_ram_b1~7.DATAIN
|
||||||
addr_i[10] => mem_ram_b2~5.DATAIN
|
addr_i[10] => mem_ram_b2~7.DATAIN
|
||||||
addr_i[10] => mem_ram_b3~5.DATAIN
|
addr_i[10] => mem_ram_b3~7.DATAIN
|
||||||
addr_i[10] => mem_ram_b0.WADDR8
|
addr_i[10] => mem_ram_b0.WADDR8
|
||||||
addr_i[10] => mem_ram_b0.RADDR8
|
addr_i[10] => mem_ram_b0.RADDR8
|
||||||
addr_i[10] => mem_ram_b1.WADDR8
|
addr_i[10] => mem_ram_b1.WADDR8
|
||||||
|
|
@ -11841,10 +11834,10 @@ addr_i[10] => mem_ram_b2.WADDR8
|
||||||
addr_i[10] => mem_ram_b2.RADDR8
|
addr_i[10] => mem_ram_b2.RADDR8
|
||||||
addr_i[10] => mem_ram_b3.WADDR8
|
addr_i[10] => mem_ram_b3.WADDR8
|
||||||
addr_i[10] => mem_ram_b3.RADDR8
|
addr_i[10] => mem_ram_b3.RADDR8
|
||||||
addr_i[11] => mem_ram_b0~3.DATAIN
|
addr_i[11] => mem_ram_b0~5.DATAIN
|
||||||
addr_i[11] => mem_ram_b1~4.DATAIN
|
addr_i[11] => mem_ram_b1~6.DATAIN
|
||||||
addr_i[11] => mem_ram_b2~4.DATAIN
|
addr_i[11] => mem_ram_b2~6.DATAIN
|
||||||
addr_i[11] => mem_ram_b3~4.DATAIN
|
addr_i[11] => mem_ram_b3~6.DATAIN
|
||||||
addr_i[11] => mem_ram_b0.WADDR9
|
addr_i[11] => mem_ram_b0.WADDR9
|
||||||
addr_i[11] => mem_ram_b0.RADDR9
|
addr_i[11] => mem_ram_b0.RADDR9
|
||||||
addr_i[11] => mem_ram_b1.WADDR9
|
addr_i[11] => mem_ram_b1.WADDR9
|
||||||
|
|
@ -11853,10 +11846,10 @@ addr_i[11] => mem_ram_b2.WADDR9
|
||||||
addr_i[11] => mem_ram_b2.RADDR9
|
addr_i[11] => mem_ram_b2.RADDR9
|
||||||
addr_i[11] => mem_ram_b3.WADDR9
|
addr_i[11] => mem_ram_b3.WADDR9
|
||||||
addr_i[11] => mem_ram_b3.RADDR9
|
addr_i[11] => mem_ram_b3.RADDR9
|
||||||
addr_i[12] => mem_ram_b0~2.DATAIN
|
addr_i[12] => mem_ram_b0~4.DATAIN
|
||||||
addr_i[12] => mem_ram_b1~3.DATAIN
|
addr_i[12] => mem_ram_b1~5.DATAIN
|
||||||
addr_i[12] => mem_ram_b2~3.DATAIN
|
addr_i[12] => mem_ram_b2~5.DATAIN
|
||||||
addr_i[12] => mem_ram_b3~3.DATAIN
|
addr_i[12] => mem_ram_b3~5.DATAIN
|
||||||
addr_i[12] => mem_ram_b0.WADDR10
|
addr_i[12] => mem_ram_b0.WADDR10
|
||||||
addr_i[12] => mem_ram_b0.RADDR10
|
addr_i[12] => mem_ram_b0.RADDR10
|
||||||
addr_i[12] => mem_ram_b1.WADDR10
|
addr_i[12] => mem_ram_b1.WADDR10
|
||||||
|
|
@ -11865,10 +11858,10 @@ addr_i[12] => mem_ram_b2.WADDR10
|
||||||
addr_i[12] => mem_ram_b2.RADDR10
|
addr_i[12] => mem_ram_b2.RADDR10
|
||||||
addr_i[12] => mem_ram_b3.WADDR10
|
addr_i[12] => mem_ram_b3.WADDR10
|
||||||
addr_i[12] => mem_ram_b3.RADDR10
|
addr_i[12] => mem_ram_b3.RADDR10
|
||||||
addr_i[13] => mem_ram_b0~1.DATAIN
|
addr_i[13] => mem_ram_b0~3.DATAIN
|
||||||
addr_i[13] => mem_ram_b1~2.DATAIN
|
addr_i[13] => mem_ram_b1~4.DATAIN
|
||||||
addr_i[13] => mem_ram_b2~2.DATAIN
|
addr_i[13] => mem_ram_b2~4.DATAIN
|
||||||
addr_i[13] => mem_ram_b3~2.DATAIN
|
addr_i[13] => mem_ram_b3~4.DATAIN
|
||||||
addr_i[13] => mem_ram_b0.WADDR11
|
addr_i[13] => mem_ram_b0.WADDR11
|
||||||
addr_i[13] => mem_ram_b0.RADDR11
|
addr_i[13] => mem_ram_b0.RADDR11
|
||||||
addr_i[13] => mem_ram_b1.WADDR11
|
addr_i[13] => mem_ram_b1.WADDR11
|
||||||
|
|
@ -11877,10 +11870,10 @@ addr_i[13] => mem_ram_b2.WADDR11
|
||||||
addr_i[13] => mem_ram_b2.RADDR11
|
addr_i[13] => mem_ram_b2.RADDR11
|
||||||
addr_i[13] => mem_ram_b3.WADDR11
|
addr_i[13] => mem_ram_b3.WADDR11
|
||||||
addr_i[13] => mem_ram_b3.RADDR11
|
addr_i[13] => mem_ram_b3.RADDR11
|
||||||
addr_i[14] => mem_ram_b0~0.DATAIN
|
addr_i[14] => mem_ram_b0~2.DATAIN
|
||||||
addr_i[14] => mem_ram_b1~1.DATAIN
|
addr_i[14] => mem_ram_b1~3.DATAIN
|
||||||
addr_i[14] => mem_ram_b2~1.DATAIN
|
addr_i[14] => mem_ram_b2~3.DATAIN
|
||||||
addr_i[14] => mem_ram_b3~1.DATAIN
|
addr_i[14] => mem_ram_b3~3.DATAIN
|
||||||
addr_i[14] => mem_ram_b0.WADDR12
|
addr_i[14] => mem_ram_b0.WADDR12
|
||||||
addr_i[14] => mem_ram_b0.RADDR12
|
addr_i[14] => mem_ram_b0.RADDR12
|
||||||
addr_i[14] => mem_ram_b1.WADDR12
|
addr_i[14] => mem_ram_b1.WADDR12
|
||||||
|
|
@ -11889,8 +11882,30 @@ addr_i[14] => mem_ram_b2.WADDR12
|
||||||
addr_i[14] => mem_ram_b2.RADDR12
|
addr_i[14] => mem_ram_b2.RADDR12
|
||||||
addr_i[14] => mem_ram_b3.WADDR12
|
addr_i[14] => mem_ram_b3.WADDR12
|
||||||
addr_i[14] => mem_ram_b3.RADDR12
|
addr_i[14] => mem_ram_b3.RADDR12
|
||||||
addr_i[15] => Equal0.IN15
|
addr_i[15] => mem_ram_b0~1.DATAIN
|
||||||
addr_i[16] => Equal0.IN14
|
addr_i[15] => mem_ram_b1~2.DATAIN
|
||||||
|
addr_i[15] => mem_ram_b2~2.DATAIN
|
||||||
|
addr_i[15] => mem_ram_b3~2.DATAIN
|
||||||
|
addr_i[15] => mem_ram_b0.WADDR13
|
||||||
|
addr_i[15] => mem_ram_b0.RADDR13
|
||||||
|
addr_i[15] => mem_ram_b1.WADDR13
|
||||||
|
addr_i[15] => mem_ram_b1.RADDR13
|
||||||
|
addr_i[15] => mem_ram_b2.WADDR13
|
||||||
|
addr_i[15] => mem_ram_b2.RADDR13
|
||||||
|
addr_i[15] => mem_ram_b3.WADDR13
|
||||||
|
addr_i[15] => mem_ram_b3.RADDR13
|
||||||
|
addr_i[16] => mem_ram_b0~0.DATAIN
|
||||||
|
addr_i[16] => mem_ram_b1~1.DATAIN
|
||||||
|
addr_i[16] => mem_ram_b2~1.DATAIN
|
||||||
|
addr_i[16] => mem_ram_b3~1.DATAIN
|
||||||
|
addr_i[16] => mem_ram_b0.WADDR14
|
||||||
|
addr_i[16] => mem_ram_b0.RADDR14
|
||||||
|
addr_i[16] => mem_ram_b1.WADDR14
|
||||||
|
addr_i[16] => mem_ram_b1.RADDR14
|
||||||
|
addr_i[16] => mem_ram_b2.WADDR14
|
||||||
|
addr_i[16] => mem_ram_b2.RADDR14
|
||||||
|
addr_i[16] => mem_ram_b3.WADDR14
|
||||||
|
addr_i[16] => mem_ram_b3.RADDR14
|
||||||
addr_i[17] => Equal0.IN13
|
addr_i[17] => Equal0.IN13
|
||||||
addr_i[18] => Equal0.IN12
|
addr_i[18] => Equal0.IN12
|
||||||
addr_i[19] => Equal0.IN11
|
addr_i[19] => Equal0.IN11
|
||||||
|
|
@ -11905,70 +11920,70 @@ addr_i[27] => Equal0.IN3
|
||||||
addr_i[28] => Equal0.IN2
|
addr_i[28] => Equal0.IN2
|
||||||
addr_i[29] => Equal0.IN1
|
addr_i[29] => Equal0.IN1
|
||||||
addr_i[30] => Equal0.IN0
|
addr_i[30] => Equal0.IN0
|
||||||
addr_i[31] => Equal0.IN16
|
addr_i[31] => Equal0.IN14
|
||||||
data_i[0] => mem_ram_b0~20.DATAIN
|
data_i[0] => mem_ram_b0~22.DATAIN
|
||||||
data_i[0] => mem_ram_b0.DATAIN
|
data_i[0] => mem_ram_b0.DATAIN
|
||||||
data_i[1] => mem_ram_b0~19.DATAIN
|
data_i[1] => mem_ram_b0~21.DATAIN
|
||||||
data_i[1] => mem_ram_b0.DATAIN1
|
data_i[1] => mem_ram_b0.DATAIN1
|
||||||
data_i[2] => mem_ram_b0~18.DATAIN
|
data_i[2] => mem_ram_b0~20.DATAIN
|
||||||
data_i[2] => mem_ram_b0.DATAIN2
|
data_i[2] => mem_ram_b0.DATAIN2
|
||||||
data_i[3] => mem_ram_b0~17.DATAIN
|
data_i[3] => mem_ram_b0~19.DATAIN
|
||||||
data_i[3] => mem_ram_b0.DATAIN3
|
data_i[3] => mem_ram_b0.DATAIN3
|
||||||
data_i[4] => mem_ram_b0~16.DATAIN
|
data_i[4] => mem_ram_b0~18.DATAIN
|
||||||
data_i[4] => mem_ram_b0.DATAIN4
|
data_i[4] => mem_ram_b0.DATAIN4
|
||||||
data_i[5] => mem_ram_b0~15.DATAIN
|
data_i[5] => mem_ram_b0~17.DATAIN
|
||||||
data_i[5] => mem_ram_b0.DATAIN5
|
data_i[5] => mem_ram_b0.DATAIN5
|
||||||
data_i[6] => mem_ram_b0~14.DATAIN
|
data_i[6] => mem_ram_b0~16.DATAIN
|
||||||
data_i[6] => mem_ram_b0.DATAIN6
|
data_i[6] => mem_ram_b0.DATAIN6
|
||||||
data_i[7] => mem_ram_b0~13.DATAIN
|
data_i[7] => mem_ram_b0~15.DATAIN
|
||||||
data_i[7] => mem_ram_b0.DATAIN7
|
data_i[7] => mem_ram_b0.DATAIN7
|
||||||
data_i[8] => mem_ram_b1~21.DATAIN
|
data_i[8] => mem_ram_b1~23.DATAIN
|
||||||
data_i[8] => mem_ram_b1.DATAIN
|
data_i[8] => mem_ram_b1.DATAIN
|
||||||
data_i[9] => mem_ram_b1~20.DATAIN
|
data_i[9] => mem_ram_b1~22.DATAIN
|
||||||
data_i[9] => mem_ram_b1.DATAIN1
|
data_i[9] => mem_ram_b1.DATAIN1
|
||||||
data_i[10] => mem_ram_b1~19.DATAIN
|
data_i[10] => mem_ram_b1~21.DATAIN
|
||||||
data_i[10] => mem_ram_b1.DATAIN2
|
data_i[10] => mem_ram_b1.DATAIN2
|
||||||
data_i[11] => mem_ram_b1~18.DATAIN
|
data_i[11] => mem_ram_b1~20.DATAIN
|
||||||
data_i[11] => mem_ram_b1.DATAIN3
|
data_i[11] => mem_ram_b1.DATAIN3
|
||||||
data_i[12] => mem_ram_b1~17.DATAIN
|
data_i[12] => mem_ram_b1~19.DATAIN
|
||||||
data_i[12] => mem_ram_b1.DATAIN4
|
data_i[12] => mem_ram_b1.DATAIN4
|
||||||
data_i[13] => mem_ram_b1~16.DATAIN
|
data_i[13] => mem_ram_b1~18.DATAIN
|
||||||
data_i[13] => mem_ram_b1.DATAIN5
|
data_i[13] => mem_ram_b1.DATAIN5
|
||||||
data_i[14] => mem_ram_b1~15.DATAIN
|
data_i[14] => mem_ram_b1~17.DATAIN
|
||||||
data_i[14] => mem_ram_b1.DATAIN6
|
data_i[14] => mem_ram_b1.DATAIN6
|
||||||
data_i[15] => mem_ram_b1~14.DATAIN
|
data_i[15] => mem_ram_b1~16.DATAIN
|
||||||
data_i[15] => mem_ram_b1.DATAIN7
|
data_i[15] => mem_ram_b1.DATAIN7
|
||||||
data_i[16] => mem_ram_b2~21.DATAIN
|
data_i[16] => mem_ram_b2~23.DATAIN
|
||||||
data_i[16] => mem_ram_b2.DATAIN
|
data_i[16] => mem_ram_b2.DATAIN
|
||||||
data_i[17] => mem_ram_b2~20.DATAIN
|
data_i[17] => mem_ram_b2~22.DATAIN
|
||||||
data_i[17] => mem_ram_b2.DATAIN1
|
data_i[17] => mem_ram_b2.DATAIN1
|
||||||
data_i[18] => mem_ram_b2~19.DATAIN
|
data_i[18] => mem_ram_b2~21.DATAIN
|
||||||
data_i[18] => mem_ram_b2.DATAIN2
|
data_i[18] => mem_ram_b2.DATAIN2
|
||||||
data_i[19] => mem_ram_b2~18.DATAIN
|
data_i[19] => mem_ram_b2~20.DATAIN
|
||||||
data_i[19] => mem_ram_b2.DATAIN3
|
data_i[19] => mem_ram_b2.DATAIN3
|
||||||
data_i[20] => mem_ram_b2~17.DATAIN
|
data_i[20] => mem_ram_b2~19.DATAIN
|
||||||
data_i[20] => mem_ram_b2.DATAIN4
|
data_i[20] => mem_ram_b2.DATAIN4
|
||||||
data_i[21] => mem_ram_b2~16.DATAIN
|
data_i[21] => mem_ram_b2~18.DATAIN
|
||||||
data_i[21] => mem_ram_b2.DATAIN5
|
data_i[21] => mem_ram_b2.DATAIN5
|
||||||
data_i[22] => mem_ram_b2~15.DATAIN
|
data_i[22] => mem_ram_b2~17.DATAIN
|
||||||
data_i[22] => mem_ram_b2.DATAIN6
|
data_i[22] => mem_ram_b2.DATAIN6
|
||||||
data_i[23] => mem_ram_b2~14.DATAIN
|
data_i[23] => mem_ram_b2~16.DATAIN
|
||||||
data_i[23] => mem_ram_b2.DATAIN7
|
data_i[23] => mem_ram_b2.DATAIN7
|
||||||
data_i[24] => mem_ram_b3~21.DATAIN
|
data_i[24] => mem_ram_b3~23.DATAIN
|
||||||
data_i[24] => mem_ram_b3.DATAIN
|
data_i[24] => mem_ram_b3.DATAIN
|
||||||
data_i[25] => mem_ram_b3~20.DATAIN
|
data_i[25] => mem_ram_b3~22.DATAIN
|
||||||
data_i[25] => mem_ram_b3.DATAIN1
|
data_i[25] => mem_ram_b3.DATAIN1
|
||||||
data_i[26] => mem_ram_b3~19.DATAIN
|
data_i[26] => mem_ram_b3~21.DATAIN
|
||||||
data_i[26] => mem_ram_b3.DATAIN2
|
data_i[26] => mem_ram_b3.DATAIN2
|
||||||
data_i[27] => mem_ram_b3~18.DATAIN
|
data_i[27] => mem_ram_b3~20.DATAIN
|
||||||
data_i[27] => mem_ram_b3.DATAIN3
|
data_i[27] => mem_ram_b3.DATAIN3
|
||||||
data_i[28] => mem_ram_b3~17.DATAIN
|
data_i[28] => mem_ram_b3~19.DATAIN
|
||||||
data_i[28] => mem_ram_b3.DATAIN4
|
data_i[28] => mem_ram_b3.DATAIN4
|
||||||
data_i[29] => mem_ram_b3~16.DATAIN
|
data_i[29] => mem_ram_b3~18.DATAIN
|
||||||
data_i[29] => mem_ram_b3.DATAIN5
|
data_i[29] => mem_ram_b3.DATAIN5
|
||||||
data_i[30] => mem_ram_b3~15.DATAIN
|
data_i[30] => mem_ram_b3~17.DATAIN
|
||||||
data_i[30] => mem_ram_b3.DATAIN6
|
data_i[30] => mem_ram_b3.DATAIN6
|
||||||
data_i[31] => mem_ram_b3~14.DATAIN
|
data_i[31] => mem_ram_b3~16.DATAIN
|
||||||
data_i[31] => mem_ram_b3.DATAIN7
|
data_i[31] => mem_ram_b3.DATAIN7
|
||||||
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
||||||
|
|
|
||||||
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Reference in a new issue