Projet_SETI_RISC-V/proj_quartus/test.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2022  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
# Date created = 14:15:36  March 06, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		test_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:15:36  MARCH 06, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "DE1-SoC Board"
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE ../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/mem/neorv32_imem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_xirq.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_xip.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_wishbone.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_wdt.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_uart.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_twi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_trng.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_top.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_sysinfo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_spi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_sdi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_pwm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_package.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_onewire.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_neoled.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_mtime.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_imem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_icache.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_gptmr.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_gpio.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_fifo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_dmem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_debug_dtm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_debug_dm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_regfile.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_decompressor.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_control.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_bus.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu_alu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_cfs.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_busswitch.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_bus_keeper.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_bootloader_image.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_boot_rom.vhd -library neorv32
set_global_assignment -name VHDL_FILE ../neorv32/rtl/core/neorv32_application_image.vhd -library neorv32
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AF14 -to clk_i
set_location_assignment PIN_V16 -to gpio_o[7]
set_location_assignment PIN_W16 -to gpio_o[6]
set_location_assignment PIN_V17 -to gpio_o[5]
set_location_assignment PIN_V18 -to gpio_o[4]
set_location_assignment PIN_W17 -to gpio_o[3]
set_location_assignment PIN_W19 -to gpio_o[2]
set_location_assignment PIN_Y19 -to gpio_o[1]
set_location_assignment PIN_W20 -to gpio_o[0]
set_location_assignment PIN_AA15 -to rstn_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rstn_i
set_location_assignment PIN_AC18 -to uart0_rxd_i
set_location_assignment PIN_Y17 -to uart0_txd_o
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_rxd_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart0_txd_o
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to gpio_o
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity gfsdg -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top