59 lines
3.2 KiB
Text
59 lines
3.2 KiB
Text
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
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--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
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-- Copyright (C) 2022 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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--synthesis_resources = lut 8
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SUBDESIGN decode_dla
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(
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data[2..0] : input;
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enable : input;
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eq[7..0] : output;
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)
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VARIABLE
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data_wire[2..0] : WIRE;
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enable_wire : WIRE;
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eq_node[7..0] : WIRE;
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eq_wire[7..0] : WIRE;
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w_anode543w[3..0] : WIRE;
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w_anode560w[3..0] : WIRE;
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w_anode570w[3..0] : WIRE;
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w_anode580w[3..0] : WIRE;
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w_anode590w[3..0] : WIRE;
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w_anode600w[3..0] : WIRE;
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w_anode610w[3..0] : WIRE;
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w_anode620w[3..0] : WIRE;
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BEGIN
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data_wire[] = data[];
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enable_wire = enable;
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eq[] = eq_node[];
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eq_node[7..0] = eq_wire[7..0];
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eq_wire[] = ( w_anode620w[3..3], w_anode610w[3..3], w_anode600w[3..3], w_anode590w[3..3], w_anode580w[3..3], w_anode570w[3..3], w_anode560w[3..3], w_anode543w[3..3]);
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w_anode543w[] = ( (w_anode543w[2..2] & (! data_wire[2..2])), (w_anode543w[1..1] & (! data_wire[1..1])), (w_anode543w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode560w[] = ( (w_anode560w[2..2] & (! data_wire[2..2])), (w_anode560w[1..1] & (! data_wire[1..1])), (w_anode560w[0..0] & data_wire[0..0]), enable_wire);
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w_anode570w[] = ( (w_anode570w[2..2] & (! data_wire[2..2])), (w_anode570w[1..1] & data_wire[1..1]), (w_anode570w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode580w[] = ( (w_anode580w[2..2] & (! data_wire[2..2])), (w_anode580w[1..1] & data_wire[1..1]), (w_anode580w[0..0] & data_wire[0..0]), enable_wire);
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w_anode590w[] = ( (w_anode590w[2..2] & data_wire[2..2]), (w_anode590w[1..1] & (! data_wire[1..1])), (w_anode590w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode600w[] = ( (w_anode600w[2..2] & data_wire[2..2]), (w_anode600w[1..1] & (! data_wire[1..1])), (w_anode600w[0..0] & data_wire[0..0]), enable_wire);
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w_anode610w[] = ( (w_anode610w[2..2] & data_wire[2..2]), (w_anode610w[1..1] & data_wire[1..1]), (w_anode610w[0..0] & (! data_wire[0..0])), enable_wire);
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w_anode620w[] = ( (w_anode620w[2..2] & data_wire[2..2]), (w_anode620w[1..1] & data_wire[1..1]), (w_anode620w[0..0] & data_wire[0..0]), enable_wire);
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END;
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--VALID FILE
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