--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=8 LPM_WIDTH=3 data enable eq --VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END -- Copyright (C) 2022 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details, at -- https://fpgasoftware.intel.com/eula. --synthesis_resources = lut 8 SUBDESIGN decode_dla ( data[2..0] : input; enable : input; eq[7..0] : output; ) VARIABLE data_wire[2..0] : WIRE; enable_wire : WIRE; eq_node[7..0] : WIRE; eq_wire[7..0] : WIRE; w_anode543w[3..0] : WIRE; w_anode560w[3..0] : WIRE; w_anode570w[3..0] : WIRE; w_anode580w[3..0] : WIRE; w_anode590w[3..0] : WIRE; w_anode600w[3..0] : WIRE; w_anode610w[3..0] : WIRE; w_anode620w[3..0] : WIRE; BEGIN data_wire[] = data[]; enable_wire = enable; eq[] = eq_node[]; eq_node[7..0] = eq_wire[7..0]; eq_wire[] = ( w_anode620w[3..3], w_anode610w[3..3], w_anode600w[3..3], w_anode590w[3..3], w_anode580w[3..3], w_anode570w[3..3], w_anode560w[3..3], w_anode543w[3..3]); w_anode543w[] = ( (w_anode543w[2..2] & (! data_wire[2..2])), (w_anode543w[1..1] & (! data_wire[1..1])), (w_anode543w[0..0] & (! data_wire[0..0])), enable_wire); w_anode560w[] = ( (w_anode560w[2..2] & (! data_wire[2..2])), (w_anode560w[1..1] & (! data_wire[1..1])), (w_anode560w[0..0] & data_wire[0..0]), enable_wire); w_anode570w[] = ( (w_anode570w[2..2] & (! data_wire[2..2])), (w_anode570w[1..1] & data_wire[1..1]), (w_anode570w[0..0] & (! data_wire[0..0])), enable_wire); w_anode580w[] = ( (w_anode580w[2..2] & (! data_wire[2..2])), (w_anode580w[1..1] & data_wire[1..1]), (w_anode580w[0..0] & data_wire[0..0]), enable_wire); w_anode590w[] = ( (w_anode590w[2..2] & data_wire[2..2]), (w_anode590w[1..1] & (! data_wire[1..1])), (w_anode590w[0..0] & (! data_wire[0..0])), enable_wire); w_anode600w[] = ( (w_anode600w[2..2] & data_wire[2..2]), (w_anode600w[1..1] & (! data_wire[1..1])), (w_anode600w[0..0] & data_wire[0..0]), enable_wire); w_anode610w[] = ( (w_anode610w[2..2] & data_wire[2..2]), (w_anode610w[1..1] & data_wire[1..1]), (w_anode610w[0..0] & (! data_wire[0..0])), enable_wire); w_anode620w[] = ( (w_anode620w[2..2] & data_wire[2..2]), (w_anode620w[1..1] & data_wire[1..1]), (w_anode620w[0..0] & data_wire[0..0]), enable_wire); END; --VALID FILE