960 lines
51 KiB
C
960 lines
51 KiB
C
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/**
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******************************************************************************
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* @file stm32f7xx_hal_adc.h
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* @author MCD Application Team
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* @brief Header file of ADC HAL extension module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32F7xx_ADC_H
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#define STM32F7xx_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal_def.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup ADC_Exported_Types ADC Exported Types
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* @{
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*/
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/**
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* @brief Structure definition of ADC and regular group initialization
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* @note Parameters of this structure are shared within 2 scopes:
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* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
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* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
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* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
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* ADC state can be either:
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* - For all parameters: ADC disabled
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* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
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* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
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* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
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* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
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*/
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typedef struct
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{
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uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
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all the ADCs.
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This parameter can be a value of @ref ADC_ClockPrescaler */
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uint32_t Resolution; /*!< Configures the ADC resolution.
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This parameter can be a value of @ref ADC_Resolution */
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uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
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or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
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This parameter can be a value of @ref ADC_Data_Align */
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uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
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This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
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If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
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Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
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If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
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Scan direction is upward: from rank1 to rank 'n'.
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This parameter can be a value of @ref ADC_Scan_mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
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This parameter can be a value of @ref ADC_EOCSelection.
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Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
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Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
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or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
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Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
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If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
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uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
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after the selected trigger occurred (software start or external trigger).
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
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To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
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FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
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Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
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Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
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This parameter can be set to ENABLE or DISABLE. */
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
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If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
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uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
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If set to ADC_SOFTWARE_START, external triggers are disabled.
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If set to external trigger source, triggering is on event rising edge by default.
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This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
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uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
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If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
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This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
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FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
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or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
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Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
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Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
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This parameter can be set to ENABLE or DISABLE. */
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}ADC_InitTypeDef;
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/**
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* @brief Structure definition of ADC channel for regular group
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* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
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* ADC can be either disabled or enabled without conversion on going on regular group.
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*/
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typedef struct
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{
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uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
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This parameter can be a value of @ref ADC_channels */
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uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
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This parameter must be a number between Min_Data = 1 and Max_Data = 16
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This parameter can be a value of @ref ADC_regular_rank */
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uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
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Unit: ADC clock cycles
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Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
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This parameter can be a value of @ref ADC_sampling_times
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Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
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If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
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Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
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sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
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Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
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uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
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}ADC_ChannelConfTypeDef;
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/**
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* @brief ADC Configuration multi-mode structure definition
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*/
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typedef struct
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{
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uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
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This parameter can be a value of @ref ADC_analog_watchdog_selection */
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uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a 12-bit value. */
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uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
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This parameter must be a 12-bit value. */
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uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
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This parameter has an effect only if watchdog mode is configured on single channel
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This parameter can be a value of @ref ADC_channels */
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FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
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is interrupt mode or in polling mode.
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This parameter can be set to ENABLE or DISABLE */
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uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
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}ADC_AnalogWDGConfTypeDef;
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/**
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* @brief HAL ADC state machine: ADC states definition (bitfields)
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*/
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/* States of ADC global scope */
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#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
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#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
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#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
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#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
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/* States of ADC errors */
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#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
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#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
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#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
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/* States of ADC group regular */
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#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
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external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
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#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
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#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
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/* States of ADC group injected */
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#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
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external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
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#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
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/* States of ADC analog watchdogs */
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#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
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#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
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#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
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/* States of ADC multi-mode */
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#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
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/**
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* @brief ADC handle Structure definition
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*/
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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typedef struct __ADC_HandleTypeDef
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#else
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typedef struct
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#endif
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{
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ADC_TypeDef *Instance; /*!< Register base address */
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ADC_InitTypeDef Init; /*!< ADC required parameters */
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__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
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DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
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HAL_LockTypeDef Lock; /*!< ADC locking object */
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__IO uint32_t State; /*!< ADC communication state */
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__IO uint32_t ErrorCode; /*!< ADC Error code */
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
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void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
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void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
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void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
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void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
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void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
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void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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}ADC_HandleTypeDef;
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL ADC Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
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HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
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HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
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HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
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HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
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HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */
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HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */
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} HAL_ADC_CallbackIDTypeDef;
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/**
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* @brief HAL ADC Callback pointer definition
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*/
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typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup ADC_Exported_Constants ADC Exported Constants
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* @{
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*/
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/** @defgroup ADC_Error_Code ADC Error Code
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* @{
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*/
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#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
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#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
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enable/disable, erroneous state */
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#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
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#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
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#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
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#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
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#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
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* @{
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*/
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#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
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#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
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#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
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#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
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/**
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* @}
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*/
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/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
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* @{
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*/
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#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
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#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
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#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
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#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
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#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
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#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||
|
|
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_Resolution ADC Resolution
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
|
||
|
|
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
|
||
|
|
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
|
||
|
|
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
|
||
|
|
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
|
||
|
|
/* compatibility with other STM32 devices. */
|
||
|
|
|
||
|
|
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
|
||
|
|
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||
|
|
|
||
|
|
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
|
||
|
|
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_Data_Align ADC Data Align
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
|
||
|
|
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
|
||
|
|
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
|
||
|
|
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
|
||
|
|
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
|
||
|
|
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
|
||
|
|
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
|
||
|
|
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
|
||
|
|
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
|
||
|
|
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
|
||
|
|
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
|
||
|
|
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
|
||
|
|
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
|
||
|
|
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
|
||
|
|
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
|
||
|
|
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
|
||
|
|
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_channels ADC Common Channels
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
|
||
|
|
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
|
||
|
|
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
|
||
|
|
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||
|
|
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
|
||
|
|
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
|
||
|
|
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
|
||
|
|
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||
|
|
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
|
||
|
|
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
|
||
|
|
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
|
||
|
|
|
||
|
|
#define ADC_INTERNAL_NONE 0x80000000U
|
||
|
|
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
|
||
|
|
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
|
||
|
|
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U))
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_sampling_times ADC Sampling Times
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
||
|
|
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
||
|
|
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
||
|
|
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
|
||
|
|
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
||
|
|
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
||
|
|
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
|
||
|
|
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
|
||
|
|
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_Event_type ADC Event Type
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
||
|
|
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||
|
|
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||
|
|
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
||
|
|
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
||
|
|
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||
|
|
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
||
|
|
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
||
|
|
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
||
|
|
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_flags_definition ADC Flags Definition
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
||
|
|
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
||
|
|
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
||
|
|
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
||
|
|
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
||
|
|
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @defgroup ADC_channels_type ADC Channels Type
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
|
||
|
|
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
|
||
|
|
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Exported macro ------------------------------------------------------------*/
|
||
|
|
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @brief Reset ADC handle state
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||
|
|
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||
|
|
do{ \
|
||
|
|
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
|
||
|
|
(__HANDLE__)->MspInitCallback = NULL; \
|
||
|
|
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||
|
|
} while(0)
|
||
|
|
#else
|
||
|
|
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||
|
|
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the ADC peripheral.
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the ADC peripheral.
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the ADC end of conversion interrupt.
|
||
|
|
* @param __HANDLE__ specifies the ADC Handle.
|
||
|
|
* @param __INTERRUPT__ ADC Interrupt.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the ADC end of conversion interrupt.
|
||
|
|
* @param __HANDLE__ specifies the ADC Handle.
|
||
|
|
* @param __INTERRUPT__ ADC interrupt.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
||
|
|
|
||
|
|
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
||
|
|
* @param __HANDLE__ specifies the ADC Handle.
|
||
|
|
* @param __INTERRUPT__ specifies the ADC interrupt source to check.
|
||
|
|
* @retval The new state of __IT__ (TRUE or FALSE).
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear the ADC's pending flags.
|
||
|
|
* @param __HANDLE__ specifies the ADC Handle.
|
||
|
|
* @param __FLAG__ ADC flag.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get the selected ADC's flag status.
|
||
|
|
* @param __HANDLE__ specifies the ADC Handle.
|
||
|
|
* @param __FLAG__ ADC flag.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Include ADC HAL Extension module */
|
||
|
|
#include "stm32f7xx_hal_adc_ex.h"
|
||
|
|
|
||
|
|
/* Exported functions --------------------------------------------------------*/
|
||
|
|
/** @addtogroup ADC_Exported_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup ADC_Exported_Functions_Group1
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Initialization/de-initialization functions ***********************************/
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||
|
|
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||
|
|
|
||
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||
|
|
/* Callbacks Register/UnRegister functions ***********************************/
|
||
|
|
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
|
||
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup ADC_Exported_Functions_Group2
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* I/O operation functions ******************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||
|
|
|
||
|
|
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||
|
|
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||
|
|
|
||
|
|
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||
|
|
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||
|
|
|
||
|
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||
|
|
|
||
|
|
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||
|
|
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||
|
|
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||
|
|
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup ADC_Exported_Functions_Group3
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Peripheral Control functions *************************************************/
|
||
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||
|
|
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup ADC_Exported_Functions_Group4
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Peripheral State functions ***************************************************/
|
||
|
|
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||
|
|
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private types -------------------------------------------------------------*/
|
||
|
|
/* Private variables ---------------------------------------------------------*/
|
||
|
|
/* Private constants ---------------------------------------------------------*/
|
||
|
|
/** @defgroup ADC_Private_Constants ADC Private Constants
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Delay for ADC stabilization time. */
|
||
|
|
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
||
|
|
/* Unit: us */
|
||
|
|
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
|
||
|
|
/* Delay for temperature sensor stabilization time. */
|
||
|
|
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||
|
|
/* Unit: us */
|
||
|
|
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private macros ------------------------------------------------------------*/
|
||
|
|
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
/* Macro reserved for internal HAL driver usage, not intended to be used in
|
||
|
|
code of final user */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Verification of ADC state: enabled or disabled
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
||
|
|
*/
|
||
|
|
#define ADC_IS_ENABLE(__HANDLE__) \
|
||
|
|
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
|
||
|
|
) ? SET : RESET)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Test if conversion trigger of regular group is software start
|
||
|
|
* or external trigger.
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval SET (software start) or RESET (external trigger)
|
||
|
|
*/
|
||
|
|
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
||
|
|
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Test if conversion trigger of injected group is software start
|
||
|
|
* or external trigger.
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval SET (software start) or RESET (external trigger)
|
||
|
|
*/
|
||
|
|
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||
|
|
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Simultaneously clears and sets specific bits of the handle State
|
||
|
|
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||
|
|
* the first parameter is the ADC handle State, the second parameter is the
|
||
|
|
* bit field to clear, the third and last parameter is the bit field to set.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_STATE_CLR_SET MODIFY_REG
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Clear ADC error code (set it to error code: "no error")
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
||
|
|
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||
|
|
|
||
|
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
|
||
|
|
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
|
||
|
|
((CHANNEL) == ADC_INTERNAL_NONE))
|
||
|
|
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
||
|
|
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
||
|
|
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
|
||
|
|
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
|
||
|
|
#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
|
||
|
|
((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
|
||
|
|
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
|
||
|
|
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
|
||
|
|
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
|
||
|
|
((__RESOLUTION__) == ADC_RESOLUTION_6B))
|
||
|
|
#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||
|
|
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||
|
|
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||
|
|
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
|
||
|
|
#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
|
||
|
|
((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
|
||
|
|
((__REGTRIG__) == ADC_SOFTWARE_START))
|
||
|
|
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
|
||
|
|
((__ALIGN__) == ADC_DATAALIGN_LEFT))
|
||
|
|
|
||
|
|
|
||
|
|
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
|
||
|
|
((__TIME__) == ADC_SAMPLETIME_480CYCLES))
|
||
|
|
#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
|
||
|
|
((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
|
||
|
|
((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
|
||
|
|
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
|
||
|
|
((__EVENT__) == ADC_OVR_EVENT))
|
||
|
|
#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
||
|
|
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
|
||
|
|
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
||
|
|
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
||
|
|
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
||
|
|
|
||
|
|
#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_2 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_3 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_4 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_5 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_6 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_7 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_8 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_9 ) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_10) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_11) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_12) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_13) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_14) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_15) || \
|
||
|
|
((__RANK__) == ADC_REGULAR_RANK_16))
|
||
|
|
|
||
|
|
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
|
||
|
|
((__SCAN_MODE__) == ADC_SCAN_ENABLE))
|
||
|
|
|
||
|
|
#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
|
||
|
|
#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
|
||
|
|
#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
|
||
|
|
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
|
||
|
|
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
|
||
|
|
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
|
||
|
|
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
|
||
|
|
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set ADC Regular channel sequence length.
|
||
|
|
* @param _NbrOfConversion_ Regular channel sequence length.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
||
|
|
* @param _SAMPLETIME_ Sample time parameter.
|
||
|
|
* @param _CHANNELNB_ Channel number.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
||
|
|
* @param _SAMPLETIME_ Sample time parameter.
|
||
|
|
* @param _CHANNELNB_ Channel number.
|
||
|
|
* @retval None
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*/
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#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
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/**
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* @brief Set the selected regular channel rank for rank between 1 and 6.
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* @param _CHANNELNB_ Channel number.
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* @param _RANKNB_ Rank number.
|
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* @retval None
|
||
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*/
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#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
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/**
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* @brief Set the selected regular channel rank for rank between 7 and 12.
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* @param _CHANNELNB_ Channel number.
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* @param _RANKNB_ Rank number.
|
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* @retval None
|
||
|
|
*/
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||
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#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
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/**
|
||
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* @brief Set the selected regular channel rank for rank between 13 and 16.
|
||
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* @param _CHANNELNB_ Channel number.
|
||
|
|
* @param _RANKNB_ Rank number.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
|
||
|
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|
||
|
|
/**
|
||
|
|
* @brief Enable ADC continuous conversion mode.
|
||
|
|
* @param _CONTINUOUS_MODE_ Continuous mode.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
||
|
|
* @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable ADC scan mode.
|
||
|
|
* @param _SCANCONV_MODE_ Scan conversion mode.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the ADC end of conversion selection.
|
||
|
|
* @param _EOCSelection_MODE_ End of conversion selection mode.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable the ADC DMA continuous request.
|
||
|
|
* @param _DMAContReq_MODE_ DMA continuous request mode.
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return resolution bits in CR1 register.
|
||
|
|
* @param __HANDLE__ ADC handle
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Private functions ---------------------------------------------------------*/
|
||
|
|
/** @defgroup ADC_Private_Functions ADC Private Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* STM32F7xx_ADC_H */
|
||
|
|
|
||
|
|
|
||
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|