59460 lines
1.9 MiB
59460 lines
1.9 MiB
--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=2097152 NUMWORDS_B=2097152 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=21 WIDTHAD_B=21 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END
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-- Copyright (C) 2022 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION decode_noa (data[7..0], enable)
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RETURNS ( eq[255..0]);
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FUNCTION mux_7jb (data[2047..0], sel[7..0])
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RETURNS ( result[7..0]);
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FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
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RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = lut 972 M10K 2048 reg 8
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_6gq1
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(
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address_a[20..0] : input;
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address_b[20..0] : input;
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clock0 : input;
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data_a[7..0] : input;
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q_b[7..0] : output;
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rden_b : input;
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wren_a : input;
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)
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VARIABLE
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address_reg_b[7..0] : dffe;
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decode2 : decode_noa;
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mux3 : mux_7jb;
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ram_block1a0 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 2,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a3 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 3,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 3,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a4 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 4,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 4,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a5 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 5,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 5,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a6 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 6,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 6,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a7 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 7,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
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PORT_A_LOGICAL_RAM_WIDTH = 8,
|
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PORT_B_ADDRESS_CLEAR = "none",
|
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PORT_B_ADDRESS_CLOCK = "clock0",
|
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PORT_B_ADDRESS_WIDTH = 13,
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
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PORT_B_DATA_WIDTH = 1,
|
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PORT_B_FIRST_ADDRESS = 0,
|
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PORT_B_FIRST_BIT_NUMBER = 7,
|
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PORT_B_LAST_ADDRESS = 8191,
|
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PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
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PORT_B_LOGICAL_RAM_WIDTH = 8,
|
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PORT_B_READ_ENABLE_CLOCK = "clock0",
|
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RAM_BLOCK_TYPE = "AUTO"
|
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);
|
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ram_block1a8 : cyclonev_ram_block
|
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WITH (
|
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CLK0_CORE_CLOCK_ENABLE = "none",
|
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CLK0_INPUT_CLOCK_ENABLE = "none",
|
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CONNECTIVITY_CHECKING = "OFF",
|
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
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OPERATION_MODE = "dual_port",
|
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PORT_A_ADDRESS_WIDTH = 13,
|
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PORT_A_DATA_WIDTH = 1,
|
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PORT_A_FIRST_ADDRESS = 8192,
|
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PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a9 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a10 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a11 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a12 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a13 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a14 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a15 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a16 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a17 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a18 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a19 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a20 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a21 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a22 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a23 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a24 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a25 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a26 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a27 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a28 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a29 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a30 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a31 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a32 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a33 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a34 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a35 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a36 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a37 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a38 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a39 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a40 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a41 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a42 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a43 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a44 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a45 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a46 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a47 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a48 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a49 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a50 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a51 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a52 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a53 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a54 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a55 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a56 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a57 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a58 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a59 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a60 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a61 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a62 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a63 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a64 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a65 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a66 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a67 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a68 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a69 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a70 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a71 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a72 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a73 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a74 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a75 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a76 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a77 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a78 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a79 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a80 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a81 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a82 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a83 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a84 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a85 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a86 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a87 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a88 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a89 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a90 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a91 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a92 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a93 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a94 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a95 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a96 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a97 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a98 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a99 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a100 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a101 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a102 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a103 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a104 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a105 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a106 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a107 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a108 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a109 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a110 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a111 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a112 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a113 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a114 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a115 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a116 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a117 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a118 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a119 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a120 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a121 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a122 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a123 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a124 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a125 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a126 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a127 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a128 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a129 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a130 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a131 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a132 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a133 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a134 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a135 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a136 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a137 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a138 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a139 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a140 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a141 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a142 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a143 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a144 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a145 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a146 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a147 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a148 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a149 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a150 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a151 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a152 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a153 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a154 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a155 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a156 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a157 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a158 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a159 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a160 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a161 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a162 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a163 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a164 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a165 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a166 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a167 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a168 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a169 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a170 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a171 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a172 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a173 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a174 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a175 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a176 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a177 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a178 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a179 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a180 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a181 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a182 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a183 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a184 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a185 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a186 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a187 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a188 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a189 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a190 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a191 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a192 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a193 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a194 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a195 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a196 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a197 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a198 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a199 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a200 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a201 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a202 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a203 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a204 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a205 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a206 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a207 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a208 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a209 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a210 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a211 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a212 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a213 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a214 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a215 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a216 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a217 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a218 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a219 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a220 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a221 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a222 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a223 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a224 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a225 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a226 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a227 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a228 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a229 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a230 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a231 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a232 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a233 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a234 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a235 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a236 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a237 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a238 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a239 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a240 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a241 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a242 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a243 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a244 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a245 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a246 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a247 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a248 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a249 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a250 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a251 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a252 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a253 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a254 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a255 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a256 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a257 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a258 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a259 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a260 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a261 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a262 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a263 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a264 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a265 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a266 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a267 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a268 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a269 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a270 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a271 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a272 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a273 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a274 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a275 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a276 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a277 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a278 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a279 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a280 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a281 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a282 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a283 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a284 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a285 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a286 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a287 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a288 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a289 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a290 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a291 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a292 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a293 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a294 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a295 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a296 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a297 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a298 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a299 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a300 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a301 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a302 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a303 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a304 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a305 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a306 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a307 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a308 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a309 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a310 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a311 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a312 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a313 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a314 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a315 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a316 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a317 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a318 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a319 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a320 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a321 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a322 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a323 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a324 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a325 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a326 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a327 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a328 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a329 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a330 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a331 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a332 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a333 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a334 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a335 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a336 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a337 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a338 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a339 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a340 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a341 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a342 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a343 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a344 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a345 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a346 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a347 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a348 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a349 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a350 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a351 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a352 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a353 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a354 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a355 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a356 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a357 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a358 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a359 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a360 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a361 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a362 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a363 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a364 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a365 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a366 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a367 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a368 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a369 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a370 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a371 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a372 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a373 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a374 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a375 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a376 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a377 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a378 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a379 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a380 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a381 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a382 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a383 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a384 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a385 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a386 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a387 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a388 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a389 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a390 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a391 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a392 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a393 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a394 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a395 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a396 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a397 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a398 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a399 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a400 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a401 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a402 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a403 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a404 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a405 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a406 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a407 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a408 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a409 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a410 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a411 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a412 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a413 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a414 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a415 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a416 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a417 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a418 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a419 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a420 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a421 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a422 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a423 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a424 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a425 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a426 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a427 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a428 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a429 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a430 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a431 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a432 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a433 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a434 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a435 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a436 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a437 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a438 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a439 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a440 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a441 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a442 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a443 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a444 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a445 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a446 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a447 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a448 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a449 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a450 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a451 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a452 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a453 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a454 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a455 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a456 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a457 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a458 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a459 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a460 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a461 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a462 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a463 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a464 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a465 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a466 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a467 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a468 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a469 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a470 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a471 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a472 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a473 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a474 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a475 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a476 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a477 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a478 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a479 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a480 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a481 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a482 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a483 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a484 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a485 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a486 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a487 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a488 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a489 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a490 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a491 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a492 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a493 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a494 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a495 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a496 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a497 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a498 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a499 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a500 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a501 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a502 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a503 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a504 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a505 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a506 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a507 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a508 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a509 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a510 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a511 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a512 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a513 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a514 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a515 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a516 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a517 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a518 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a519 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 524288,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 532479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 524288,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 532479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a520 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a521 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a522 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a523 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a524 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a525 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a526 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a527 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 532480,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 540671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 532480,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 540671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a528 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a529 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a530 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a531 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a532 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a533 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a534 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a535 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 540672,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 548863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 540672,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 548863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a536 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a537 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a538 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a539 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a540 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a541 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a542 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a543 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 548864,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 557055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 548864,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 557055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a544 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a545 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a546 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a547 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a548 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a549 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a550 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a551 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 557056,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 565247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 557056,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 565247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a552 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a553 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a554 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a555 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a556 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a557 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a558 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a559 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 565248,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 573439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 565248,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 573439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a560 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a561 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a562 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a563 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a564 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a565 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a566 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a567 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 573440,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 581631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 573440,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 581631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a568 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a569 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a570 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a571 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a572 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a573 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a574 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a575 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 581632,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 589823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 581632,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 589823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a576 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a577 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a578 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a579 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a580 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a581 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a582 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a583 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 589824,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 598015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 589824,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 598015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a584 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a585 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a586 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a587 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a588 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a589 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a590 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a591 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 598016,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 606207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 598016,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 606207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a592 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a593 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a594 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a595 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a596 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a597 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a598 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a599 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 606208,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 614399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 606208,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 614399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a600 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a601 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a602 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a603 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a604 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a605 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a606 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a607 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 614400,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 622591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 614400,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 622591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a608 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a609 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a610 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a611 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a612 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a613 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a614 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a615 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 622592,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 630783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 622592,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 630783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a616 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a617 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a618 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a619 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a620 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a621 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a622 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a623 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 630784,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 638975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 630784,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 638975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a624 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a625 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a626 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a627 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a628 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a629 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a630 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a631 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 638976,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 647167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 638976,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 647167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a632 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a633 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a634 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a635 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a636 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a637 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a638 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a639 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 647168,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 655359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 647168,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 655359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a640 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a641 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a642 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a643 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a644 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a645 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a646 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a647 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 655360,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 663551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 655360,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 663551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a648 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a649 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a650 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a651 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a652 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a653 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a654 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a655 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 663552,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 671743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 663552,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 671743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a656 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a657 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a658 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a659 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a660 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a661 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a662 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a663 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 671744,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 679935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 671744,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 679935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a664 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a665 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a666 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a667 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a668 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a669 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a670 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a671 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 679936,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 688127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 679936,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 688127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a672 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a673 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a674 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a675 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a676 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a677 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a678 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a679 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 688128,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 696319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 688128,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 696319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a680 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a681 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a682 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a683 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a684 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a685 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a686 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a687 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 696320,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 704511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 696320,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 704511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a688 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a689 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a690 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a691 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a692 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a693 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a694 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a695 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 704512,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 712703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 704512,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 712703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a696 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a697 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a698 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a699 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a700 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a701 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a702 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a703 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 712704,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 720895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 712704,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 720895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a704 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a705 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a706 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a707 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a708 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a709 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a710 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a711 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 720896,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 729087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 720896,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 729087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a712 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a713 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a714 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a715 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a716 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a717 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a718 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a719 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 729088,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 737279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 729088,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 737279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a720 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a721 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a722 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a723 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a724 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a725 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a726 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a727 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 737280,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 745471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 737280,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 745471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a728 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a729 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a730 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a731 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a732 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a733 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a734 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a735 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 745472,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 753663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 745472,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 753663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a736 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a737 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a738 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a739 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a740 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a741 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a742 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a743 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 753664,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 761855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 753664,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 761855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a744 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a745 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a746 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a747 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a748 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a749 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a750 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a751 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 761856,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 770047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 761856,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 770047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a752 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a753 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a754 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a755 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a756 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a757 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a758 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a759 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 770048,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 778239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 770048,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 778239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a760 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a761 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a762 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a763 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a764 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a765 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a766 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a767 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 778240,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 786431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 778240,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 786431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a768 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a769 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a770 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a771 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a772 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a773 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a774 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a775 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 786432,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 794623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 786432,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 794623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a776 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a777 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a778 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a779 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a780 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a781 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a782 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a783 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 794624,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 802815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 794624,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 802815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a784 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a785 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a786 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a787 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a788 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a789 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a790 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a791 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 802816,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 811007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 802816,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 811007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a792 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a793 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a794 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a795 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a796 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a797 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a798 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a799 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 811008,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 819199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 811008,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 819199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a800 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a801 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a802 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a803 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a804 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a805 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a806 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a807 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 819200,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 827391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 819200,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 827391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a808 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a809 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a810 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a811 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a812 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a813 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a814 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a815 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 827392,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 835583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 827392,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 835583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a816 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a817 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a818 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a819 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a820 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a821 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a822 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a823 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 835584,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 843775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 835584,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 843775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a824 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a825 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a826 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a827 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a828 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a829 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a830 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a831 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 843776,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 851967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 843776,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 851967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a832 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a833 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a834 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a835 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a836 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a837 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a838 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a839 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 851968,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 860159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 851968,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 860159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a840 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a841 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a842 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a843 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a844 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a845 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a846 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a847 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 860160,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 868351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 860160,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 868351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a848 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a849 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a850 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a851 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a852 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a853 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a854 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a855 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 868352,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 876543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 868352,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 876543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a856 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a857 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a858 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a859 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a860 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a861 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a862 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a863 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 876544,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 884735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 876544,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 884735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a864 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a865 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a866 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a867 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a868 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a869 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a870 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a871 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 884736,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 892927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 884736,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 892927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a872 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a873 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a874 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a875 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a876 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a877 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a878 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a879 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 892928,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 901119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 892928,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 901119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a880 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a881 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a882 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a883 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a884 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a885 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a886 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a887 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 901120,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 909311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 901120,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 909311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a888 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a889 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a890 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a891 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a892 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a893 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a894 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a895 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 909312,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 917503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 909312,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 917503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a896 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a897 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a898 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a899 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a900 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a901 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a902 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a903 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 917504,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 925695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 917504,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 925695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a904 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a905 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a906 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a907 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a908 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a909 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a910 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a911 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 925696,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 933887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 925696,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 933887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a912 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a913 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a914 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a915 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a916 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a917 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a918 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a919 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 933888,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 942079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 933888,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 942079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a920 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a921 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a922 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a923 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a924 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a925 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a926 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a927 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 942080,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 950271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 942080,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 950271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a928 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a929 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a930 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a931 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a932 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a933 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a934 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a935 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 950272,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 958463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 950272,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 958463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a936 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a937 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a938 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a939 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a940 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a941 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a942 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a943 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 958464,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 966655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 958464,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 966655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a944 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a945 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a946 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a947 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a948 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a949 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a950 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a951 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 966656,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 974847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 966656,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 974847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a952 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a953 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a954 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a955 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a956 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a957 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a958 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a959 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 974848,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 983039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 974848,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 983039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a960 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a961 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a962 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a963 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a964 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a965 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a966 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a967 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 983040,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 991231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 983040,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 991231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a968 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a969 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a970 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a971 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a972 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a973 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a974 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a975 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 991232,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 999423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 991232,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 999423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a976 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a977 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a978 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a979 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a980 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a981 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a982 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a983 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 999424,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1007615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 999424,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1007615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a984 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a985 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a986 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a987 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a988 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a989 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a990 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a991 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1007616,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1015807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1007616,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1015807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a992 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a993 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a994 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a995 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a996 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a997 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a998 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a999 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1015808,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1023999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1015808,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1023999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1000 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1001 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1002 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1003 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1004 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1005 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1006 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1007 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1024000,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1032191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1024000,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1032191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1008 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1009 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1010 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1011 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1012 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1013 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1014 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1015 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1032192,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1040383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1032192,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1040383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1016 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1017 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1018 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1019 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1020 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1021 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1022 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1023 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1040384,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1048575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1040384,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1048575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1024 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1025 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1026 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1027 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1028 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1029 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1030 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1031 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1048576,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1056767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1048576,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1056767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1032 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1033 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1034 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1035 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1036 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1037 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1038 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1039 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1056768,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1064959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1056768,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1064959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1040 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1041 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1042 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1043 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1044 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1045 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1046 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1047 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1064960,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1073151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1064960,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1073151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1048 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1049 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1050 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1051 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1052 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1053 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1054 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1055 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1073152,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1081343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1073152,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1081343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1056 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1057 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1058 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1059 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1060 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1061 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1062 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1063 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1081344,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1089535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1081344,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1089535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1064 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1065 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1066 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1067 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1068 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1069 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1070 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1071 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1089536,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1097727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1089536,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1097727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1072 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1073 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1074 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1075 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1076 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1077 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1078 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1079 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1097728,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1105919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1097728,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1105919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1080 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1081 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1082 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1083 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1084 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1085 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1086 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1087 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1105920,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1114111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1105920,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1114111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1088 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1089 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1090 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1091 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1092 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1093 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1094 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1095 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1114112,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1122303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1114112,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1122303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1096 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1097 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1098 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1099 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1100 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1101 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1102 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1103 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1122304,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1130495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1122304,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1130495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1104 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1105 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1106 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1107 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1108 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1109 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1110 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1111 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1130496,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1138687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1130496,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1138687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1112 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1113 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1114 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1115 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1116 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1117 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1118 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1119 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1138688,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1146879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1138688,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1146879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1120 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1121 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1122 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1123 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1124 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1125 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1126 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1127 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1146880,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1155071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1146880,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1155071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1128 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1129 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1130 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1131 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1132 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1133 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1134 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1135 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1155072,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1163263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1155072,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1163263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1136 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1137 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1138 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1139 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1140 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1141 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1142 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1143 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1163264,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1171455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1163264,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1171455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1144 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1145 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1146 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1147 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1148 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1149 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1150 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1151 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1171456,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1179647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1171456,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1179647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1152 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1153 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1154 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1155 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1156 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1157 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1158 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1159 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1179648,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1187839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1179648,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1187839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1160 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1161 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1162 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1163 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1164 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1165 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1166 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1167 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1187840,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1196031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1187840,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1196031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1168 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1169 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1170 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1171 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1172 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1173 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1174 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1175 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1196032,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1204223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1196032,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1204223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1176 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1177 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1178 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1179 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1180 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1181 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1182 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1183 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1204224,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1212415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1204224,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1212415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1184 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1185 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1186 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1187 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1188 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1189 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1190 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1191 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1212416,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1220607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1212416,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1220607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1192 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1193 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1194 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1195 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1196 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1197 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1198 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1199 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1220608,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1228799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1220608,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1228799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1200 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1201 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1202 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1203 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1204 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1205 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1206 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1207 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1228800,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1236991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1228800,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1236991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1208 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1209 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1210 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1211 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1212 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1213 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1214 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1215 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1236992,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1245183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1236992,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1245183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1216 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1217 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1218 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1219 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1220 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1221 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1222 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1223 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1245184,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1253375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1245184,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1253375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1224 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1225 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1226 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1227 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1228 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1229 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1230 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1231 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1253376,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1261567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1253376,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1261567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1232 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1233 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1234 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1235 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1236 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1237 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1238 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1239 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1261568,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1269759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1261568,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1269759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1240 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1241 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1242 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1243 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1244 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1245 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1246 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1247 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1269760,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1277951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1269760,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1277951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1248 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1249 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1250 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1251 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1252 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1253 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1254 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1255 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1277952,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1286143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1277952,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1286143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1256 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1257 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1258 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1259 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1260 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1261 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1262 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1263 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1286144,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1294335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1286144,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1294335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1264 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1265 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1266 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1267 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1268 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1269 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1270 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1271 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1294336,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1302527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1294336,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1302527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1272 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1273 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1274 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1275 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1276 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1277 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1278 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1279 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1302528,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1310719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1302528,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1310719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1280 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1281 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1282 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1283 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1284 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1285 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1286 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1287 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1310720,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1318911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1310720,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1318911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1288 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1289 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1290 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1291 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1292 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1293 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1294 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1295 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1318912,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1327103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1318912,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1327103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1296 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1297 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1298 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1299 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1300 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1301 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1302 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1303 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1327104,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1335295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1327104,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1335295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1304 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1305 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1306 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1307 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1308 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1309 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1310 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1311 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1335296,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1343487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1335296,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1343487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1312 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1313 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1314 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1315 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1316 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1317 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1318 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1319 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1343488,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1351679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1343488,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1351679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1320 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1321 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1322 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1323 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1324 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1325 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1326 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1327 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1351680,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1359871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1351680,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1359871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1328 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1329 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1330 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1331 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1332 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1333 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1334 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1335 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1359872,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1368063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1359872,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1368063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1336 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1337 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1338 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1339 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1340 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1341 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1342 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1343 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1368064,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1376255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1368064,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1376255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1344 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1345 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1346 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1347 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1348 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1349 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1350 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1351 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1376256,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1384447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1376256,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1384447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1352 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1353 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1354 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1355 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1356 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1357 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1358 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1359 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1384448,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1392639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1384448,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1392639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1360 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1361 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1362 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1363 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1364 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1365 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1366 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1367 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1392640,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1400831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1392640,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1400831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1368 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1369 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1370 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1371 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1372 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1373 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1374 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1375 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1400832,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1409023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1400832,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1409023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1376 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1377 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1378 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1379 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1380 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1381 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1382 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1383 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1409024,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1417215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1409024,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1417215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1384 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1385 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1386 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1387 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1388 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1389 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1390 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1391 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1417216,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1425407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1417216,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1425407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1392 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1393 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1394 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1395 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1396 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1397 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1398 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1399 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1425408,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1433599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1425408,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1433599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1400 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1401 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1402 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1403 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1404 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1405 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1406 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1407 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1433600,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1441791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1433600,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1441791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1408 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1409 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1410 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1411 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1412 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1413 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1414 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1415 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1441792,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1449983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1441792,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1449983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1416 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1417 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1418 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1419 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1420 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1421 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1422 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1423 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1449984,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1458175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1449984,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1458175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1424 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1425 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1426 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1427 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1428 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1429 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1430 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1431 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1458176,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1466367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1458176,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1466367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1432 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1433 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1434 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1435 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1436 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1437 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1438 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1439 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1466368,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1474559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1466368,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1474559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1440 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1441 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1442 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1443 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1444 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1445 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1446 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1447 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1474560,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1482751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1474560,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1482751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1448 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1449 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1450 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1451 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1452 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1453 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1454 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1455 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1482752,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1490943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1482752,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1490943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1456 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1457 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1458 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1459 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1460 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1461 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1462 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1463 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1490944,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1499135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1490944,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1499135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1464 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1465 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1466 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1467 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1468 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1469 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1470 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1471 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1499136,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1507327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1499136,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1507327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1472 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1473 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1474 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1475 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1476 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1477 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1478 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1479 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1507328,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1515519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1507328,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1515519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1480 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1481 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1482 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1483 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1484 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1485 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1486 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1487 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1515520,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1523711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1515520,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1523711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1488 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1489 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1490 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1491 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1492 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1493 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1494 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1495 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1523712,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1531903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1523712,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1531903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1496 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1497 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1498 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1499 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1500 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1501 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1502 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1503 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1531904,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1540095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1531904,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1540095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1504 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1505 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1506 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1507 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1508 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1509 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1510 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1511 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1540096,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1548287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1540096,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1548287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1512 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1513 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1514 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1515 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1516 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1517 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1518 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1519 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1548288,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1556479,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1548288,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1556479,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1520 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1521 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1522 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1523 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1524 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1525 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1526 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1527 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1556480,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1564671,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1556480,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1564671,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1528 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1529 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1530 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1531 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1532 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1533 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1534 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1535 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1564672,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1572863,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1564672,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1572863,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1536 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1537 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1538 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1539 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1540 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1541 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1542 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1543 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1572864,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1581055,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1572864,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1581055,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1544 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1545 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1546 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1547 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1548 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1549 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1550 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1551 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1581056,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1589247,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1581056,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1589247,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1552 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1553 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1554 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1555 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1556 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1557 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1558 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1559 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1589248,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1597439,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1589248,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1597439,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1560 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1561 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1562 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1563 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1564 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1565 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1566 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1567 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1597440,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1605631,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1597440,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1605631,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1568 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1569 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1570 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1571 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1572 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1573 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1574 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1575 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1605632,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1613823,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1605632,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1613823,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1576 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1577 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1578 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1579 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1580 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1581 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1582 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1583 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1613824,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1622015,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1613824,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1622015,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1584 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1585 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1586 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1587 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1588 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1589 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1590 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1591 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1622016,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1630207,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1622016,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1630207,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1592 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1593 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1594 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1595 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1596 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1597 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1598 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1599 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1630208,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1638399,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1630208,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1638399,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1600 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1601 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1602 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1603 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1604 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1605 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1606 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1607 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1638400,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1646591,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1638400,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1646591,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1608 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1609 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1610 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1611 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1612 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1613 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1614 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1615 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1646592,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1654783,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1646592,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1654783,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1616 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1617 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1618 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1619 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1620 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1621 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1622 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1623 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1654784,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1662975,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1654784,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1662975,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1624 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1625 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1626 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1627 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1628 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1629 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1630 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1631 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1662976,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1671167,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1662976,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1671167,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1632 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1633 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1634 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1635 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1636 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1637 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1638 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1639 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1671168,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1679359,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1671168,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1679359,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1640 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1641 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1642 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1643 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1644 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1645 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1646 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1647 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1679360,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1687551,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1679360,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1687551,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1648 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1649 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1650 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1651 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1652 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1653 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1654 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1655 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1687552,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1695743,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1687552,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1695743,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1656 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1657 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1658 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1659 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1660 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1661 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1662 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1663 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1695744,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1703935,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1695744,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1703935,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1664 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1665 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1666 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1667 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1668 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1669 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1670 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1671 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1703936,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1712127,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1703936,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1712127,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1672 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1673 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1674 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1675 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1676 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1677 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1678 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1679 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1712128,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1720319,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1712128,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1720319,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1680 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1681 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1682 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1683 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1684 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1685 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1686 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1687 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1720320,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1728511,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1720320,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1728511,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1688 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1689 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1690 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1691 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1692 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1693 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1694 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1695 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1728512,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1736703,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1728512,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1736703,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1696 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1697 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1698 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1699 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1700 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1701 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1702 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1703 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1736704,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1744895,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1736704,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1744895,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1704 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1705 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1706 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1707 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1708 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1709 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1710 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1711 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1744896,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1753087,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1744896,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1753087,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1712 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1713 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1714 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1715 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1716 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1717 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1718 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1719 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1753088,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1761279,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1753088,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1761279,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1720 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1721 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1722 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1723 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1724 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1725 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1726 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1727 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1761280,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1769471,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1761280,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1769471,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1728 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1729 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1730 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1731 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1732 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1733 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1734 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1735 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1769472,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1777663,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1769472,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1777663,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1736 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1737 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1738 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1739 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1740 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1741 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1742 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1743 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1777664,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1785855,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1777664,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1785855,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1744 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1745 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1746 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1747 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1748 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1749 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1750 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1751 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1785856,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1794047,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1785856,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1794047,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1752 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1753 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1754 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1755 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1756 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1757 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1758 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1759 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1794048,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1802239,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1794048,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1802239,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1760 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1761 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1762 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1763 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1764 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1765 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1766 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1767 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1802240,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1810431,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1802240,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1810431,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1768 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1769 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1770 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1771 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1772 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1773 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1774 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1775 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1810432,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1818623,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1810432,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1818623,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1776 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1777 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1778 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1779 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1780 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1781 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1782 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1783 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1818624,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1826815,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1818624,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1826815,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1784 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1785 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1786 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1787 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1788 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1789 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1790 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1791 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1826816,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1835007,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1826816,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1835007,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1792 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1793 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1794 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1795 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1796 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1797 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1798 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1799 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1835008,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1843199,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1835008,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1843199,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1800 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1801 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1802 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1803 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1804 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1805 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1806 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1807 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1843200,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1851391,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1843200,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1851391,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1808 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1809 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1810 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1811 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1812 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1813 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1814 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1815 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1851392,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1859583,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1851392,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1859583,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1816 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1817 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1818 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1819 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1820 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1821 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1822 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1823 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1859584,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1867775,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1859584,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1867775,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1824 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1825 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1826 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1827 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1828 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1829 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1830 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1831 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1867776,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1875967,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1867776,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1875967,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1832 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1833 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1834 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1835 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1836 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1837 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1838 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1839 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1875968,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1884159,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1875968,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1884159,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1840 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1841 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1842 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1843 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1844 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1845 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1846 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1847 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1884160,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1892351,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1884160,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1892351,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1848 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1849 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1850 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1851 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1852 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1853 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1854 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1855 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1892352,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1900543,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1892352,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1900543,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1856 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1857 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1858 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1859 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1860 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1861 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1862 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1863 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1900544,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1908735,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1900544,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1908735,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1864 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1865 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1866 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1867 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1868 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1869 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1870 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1871 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1908736,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1916927,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1908736,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1916927,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1872 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1873 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1874 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1875 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1876 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1877 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1878 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1879 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1916928,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1925119,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1916928,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1925119,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1880 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1881 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1882 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1883 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1884 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1885 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1886 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1887 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1925120,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1933311,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1925120,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1933311,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1888 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1889 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1890 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1891 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1892 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1893 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1894 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1895 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1933312,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1941503,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1933312,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1941503,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1896 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1897 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1898 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1899 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1900 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1901 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1902 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1903 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1941504,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1949695,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1941504,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1949695,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1904 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1905 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1906 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1907 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1908 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1909 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1910 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1911 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1949696,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1957887,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1949696,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1957887,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1912 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1913 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1914 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1915 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1916 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1917 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1918 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1919 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1957888,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1966079,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1957888,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1966079,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1920 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1921 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1922 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1923 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1924 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1925 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1926 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1927 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1966080,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1974271,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1966080,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1974271,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1928 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1929 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1930 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1931 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1932 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1933 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1934 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1935 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1974272,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1982463,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1974272,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1982463,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1936 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1937 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1938 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1939 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1940 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1941 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1942 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1943 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1982464,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1990655,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1982464,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1990655,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1944 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1945 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1946 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1947 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1948 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1949 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1950 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1951 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1990656,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 1998847,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1990656,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 1998847,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1952 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1953 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1954 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1955 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1956 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1957 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1958 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1959 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 1998848,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2007039,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 1998848,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2007039,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1960 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1961 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1962 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1963 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1964 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1965 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1966 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1967 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2007040,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2015231,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2007040,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2015231,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1968 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1969 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1970 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1971 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1972 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1973 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1974 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1975 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2015232,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2023423,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2015232,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2023423,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1976 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1977 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1978 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1979 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1980 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1981 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1982 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1983 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2023424,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2031615,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2023424,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2031615,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1984 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1985 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1986 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1987 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1988 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1989 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1990 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1991 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2031616,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2039807,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2031616,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2039807,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1992 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1993 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1994 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1995 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1996 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1997 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1998 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a1999 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2039808,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2047999,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2039808,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2047999,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2000 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2001 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2002 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2003 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2004 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2005 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2006 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2007 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2048000,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2056191,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2048000,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2056191,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2008 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2009 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2010 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2011 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2012 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2013 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2014 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2015 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2056192,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2064383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2056192,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2064383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2016 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2017 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2018 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2019 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2020 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2021 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2022 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2023 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2064384,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2072575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2064384,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2072575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2024 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2025 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2026 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2027 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2028 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2029 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2030 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2031 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2072576,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2080767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2072576,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2080767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2032 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2033 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2034 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2035 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2036 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2037 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2038 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2039 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2080768,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2088959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2080768,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2088959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2040 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2041 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2042 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2043 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2044 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2045 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2046 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a2047 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 2088960,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 2097151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 2088960,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 2097151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 2097152,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
address_a_wire[20..0] : WIRE;
|
|
address_b_sel[7..0] : WIRE;
|
|
address_b_wire[20..0] : WIRE;
|
|
|
|
BEGIN
|
|
address_reg_b[].clk = clock0;
|
|
address_reg_b[].d = address_b_sel[];
|
|
address_reg_b[].ena = rden_b;
|
|
decode2.data[7..0] = address_a_wire[20..13];
|
|
decode2.enable = wren_a;
|
|
mux3.data[] = ( ram_block1a[2047..0].portbdataout[0..0]);
|
|
mux3.sel[] = address_reg_b[].q;
|
|
ram_block1a[2047..0].clk0 = clock0;
|
|
ram_block1a[2047..0].portaaddr[] = ( address_a_wire[12..0]);
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[8].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[9].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[10].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[11].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[12].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[13].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[14].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[15].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[16].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[17].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[18].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[19].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[20].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[21].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[22].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[23].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[24].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[25].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[26].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[27].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[28].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[29].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[30].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[31].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[32].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[33].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[34].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[35].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[36].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[37].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[38].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[39].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[40].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[41].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[42].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[43].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[44].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[45].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[46].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[47].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[48].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[49].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[50].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[51].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[52].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[53].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[54].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[55].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[56].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[57].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[58].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[59].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[60].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[61].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[62].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[63].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[64].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[65].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[66].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[67].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[68].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[69].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[70].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[71].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[72].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[73].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[74].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[75].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[76].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[77].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[78].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[79].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[80].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[81].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[82].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[83].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[84].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[85].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[86].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[87].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[88].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[89].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[90].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[91].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[92].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[93].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[94].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[95].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[96].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[97].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[98].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[99].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[100].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[101].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[102].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[103].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[104].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[105].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[106].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[107].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[108].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[109].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[110].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[111].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[112].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[113].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[114].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[115].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[116].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[117].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[118].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[119].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[120].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[121].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[122].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[123].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[124].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[125].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[126].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[127].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[128].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[129].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[130].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[131].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[132].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[133].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[134].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[135].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[136].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[137].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[138].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[139].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[140].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[141].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[142].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[143].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[144].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[145].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[146].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[147].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[148].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[149].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[150].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[151].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[152].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[153].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[154].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[155].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[156].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[157].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[158].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[159].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[160].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[161].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[162].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[163].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[164].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[165].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[166].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[167].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[168].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[169].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[170].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[171].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[172].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[173].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[174].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[175].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[176].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[177].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[178].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[179].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[180].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[181].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[182].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[183].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[184].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[185].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[186].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[187].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[188].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[189].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[190].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[191].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[192].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[193].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[194].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[195].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[196].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[197].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[198].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[199].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[200].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[201].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[202].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[203].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[204].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[205].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[206].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[207].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[208].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[209].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[210].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[211].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[212].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[213].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[214].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[215].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[216].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[217].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[218].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[219].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[220].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[221].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[222].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[223].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[224].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[225].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[226].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[227].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[228].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[229].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[230].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[231].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[232].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[233].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[234].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[235].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[236].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[237].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[238].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[239].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[240].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[241].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[242].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[243].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[244].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[245].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[246].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[247].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[248].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[249].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[250].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[251].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[252].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[253].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[254].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[255].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[256].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[257].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[258].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[259].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[260].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[261].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[262].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[263].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[264].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[265].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[266].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[267].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[268].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[269].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[270].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[271].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[272].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[273].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[274].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[275].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[276].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[277].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[278].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[279].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[280].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[281].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[282].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[283].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[284].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[285].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[286].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[287].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[288].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[289].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[290].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[291].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[292].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[293].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[294].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[295].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[296].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[297].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[298].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[299].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[300].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[301].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[302].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[303].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[304].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[305].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[306].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[307].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[308].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[309].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[310].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[311].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[312].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[313].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[314].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[315].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[316].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[317].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[318].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[319].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[320].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[321].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[322].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[323].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[324].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[325].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[326].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[327].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[328].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[329].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[330].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[331].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[332].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[333].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[334].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[335].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[336].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[337].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[338].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[339].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[340].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[341].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[342].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[343].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[344].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[345].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[346].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[347].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[348].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[349].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[350].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[351].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[352].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[353].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[354].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[355].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[356].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[357].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[358].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[359].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[360].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[361].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[362].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[363].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[364].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[365].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[366].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[367].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[368].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[369].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[370].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[371].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[372].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[373].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[374].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[375].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[376].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[377].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[378].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[379].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[380].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[381].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[382].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[383].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[384].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[385].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[386].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[387].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[388].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[389].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[390].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[391].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[392].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[393].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[394].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[395].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[396].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[397].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[398].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[399].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[400].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[401].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[402].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[403].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[404].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[405].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[406].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[407].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[408].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[409].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[410].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[411].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[412].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[413].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[414].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[415].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[416].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[417].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[418].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[419].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[420].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[421].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[422].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[423].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[424].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[425].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[426].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[427].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[428].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[429].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[430].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[431].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[432].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[433].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[434].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[435].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[436].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[437].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[438].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[439].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[440].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[441].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[442].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[443].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[444].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[445].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[446].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[447].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[448].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[449].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[450].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[451].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[452].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[453].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[454].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[455].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[456].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[457].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[458].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[459].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[460].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[461].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[462].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[463].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[464].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[465].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[466].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[467].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[468].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[469].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[470].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[471].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[472].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[473].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[474].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[475].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[476].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[477].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[478].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[479].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[480].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[481].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[482].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[483].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[484].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[485].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[486].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[487].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[488].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[489].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[490].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[491].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[492].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[493].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[494].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[495].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[496].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[497].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[498].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[499].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[500].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[501].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[502].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[503].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[504].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[505].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[506].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[507].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[508].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[509].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[510].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[511].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[512].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[513].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[514].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[515].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[516].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[517].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[518].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[519].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[520].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[521].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[522].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[523].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[524].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[525].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[526].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[527].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[528].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[529].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[530].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[531].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[532].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[533].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[534].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[535].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[536].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[537].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[538].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[539].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[540].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[541].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[542].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[543].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[544].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[545].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[546].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[547].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[548].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[549].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[550].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[551].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[552].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[553].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[554].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[555].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[556].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[557].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[558].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[559].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[560].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[561].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[562].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[563].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[564].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[565].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[566].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[567].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[568].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[569].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[570].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[571].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[572].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[573].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[574].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[575].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[576].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[577].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[578].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[579].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[580].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[581].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[582].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[583].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[584].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[585].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[586].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[587].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[588].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[589].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[590].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[591].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[592].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[593].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[594].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[595].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[596].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[597].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[598].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[599].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[600].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[601].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[602].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[603].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[604].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[605].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[606].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[607].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[608].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[609].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[610].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[611].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[612].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[613].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[614].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[615].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[616].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[617].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[618].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[619].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[620].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[621].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[622].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[623].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[624].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[625].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[626].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[627].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[628].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[629].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[630].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[631].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[632].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[633].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[634].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[635].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[636].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[637].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[638].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[639].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[640].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[641].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[642].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[643].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[644].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[645].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[646].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[647].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[648].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[649].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[650].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[651].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[652].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[653].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[654].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[655].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[656].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[657].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[658].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[659].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[660].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[661].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[662].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[663].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[664].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[665].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[666].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[667].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[668].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[669].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[670].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[671].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[672].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[673].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[674].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[675].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[676].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[677].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[678].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[679].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[680].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[681].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[682].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[683].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[684].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[685].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[686].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[687].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[688].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[689].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[690].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[691].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[692].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[693].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[694].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[695].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[696].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[697].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[698].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[699].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[700].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[701].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[702].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[703].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[704].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[705].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[706].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[707].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[708].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[709].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[710].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[711].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[712].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[713].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[714].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[715].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[716].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[717].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[718].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[719].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[720].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[721].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[722].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[723].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[724].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[725].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[726].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[727].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[728].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[729].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[730].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[731].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[732].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[733].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[734].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[735].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[736].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[737].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[738].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[739].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[740].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[741].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[742].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[743].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[744].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[745].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[746].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[747].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[748].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[749].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[750].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[751].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[752].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[753].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[754].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[755].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[756].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[757].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[758].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[759].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[760].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[761].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[762].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[763].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[764].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[765].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[766].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[767].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[768].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[769].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[770].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[771].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[772].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[773].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[774].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[775].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[776].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[777].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[778].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[779].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[780].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[781].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[782].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[783].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[784].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[785].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[786].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[787].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[788].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[789].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[790].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[791].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[792].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[793].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[794].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[795].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[796].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[797].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[798].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[799].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[800].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[801].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[802].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[803].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[804].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[805].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[806].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[807].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[808].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[809].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[810].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[811].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[812].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[813].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[814].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[815].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[816].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[817].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[818].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[819].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[820].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[821].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[822].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[823].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[824].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[825].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[826].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[827].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[828].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[829].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[830].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[831].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[832].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[833].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[834].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[835].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[836].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[837].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[838].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[839].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[840].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[841].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[842].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[843].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[844].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[845].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[846].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[847].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[848].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[849].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[850].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[851].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[852].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[853].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[854].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[855].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[856].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[857].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[858].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[859].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[860].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[861].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[862].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[863].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[864].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[865].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[866].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[867].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[868].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[869].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[870].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[871].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[872].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[873].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[874].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[875].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[876].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[877].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[878].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[879].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[880].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[881].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[882].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[883].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[884].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[885].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[886].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[887].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[888].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[889].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[890].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[891].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[892].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[893].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[894].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[895].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[896].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[897].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[898].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[899].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[900].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[901].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[902].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[903].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[904].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[905].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[906].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[907].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[908].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[909].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[910].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[911].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[912].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[913].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[914].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[915].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[916].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[917].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[918].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[919].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[920].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[921].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[922].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[923].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[924].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[925].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[926].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[927].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[928].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[929].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[930].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[931].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[932].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[933].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[934].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[935].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[936].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[937].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[938].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[939].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[940].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[941].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[942].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[943].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[944].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[945].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[946].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[947].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[948].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[949].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[950].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[951].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[952].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[953].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[954].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[955].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[956].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[957].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[958].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[959].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[960].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[961].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[962].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[963].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[964].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[965].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[966].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[967].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[968].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[969].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[970].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[971].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[972].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[973].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[974].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[975].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[976].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[977].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[978].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[979].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[980].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[981].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[982].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[983].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[984].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[985].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[986].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[987].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[988].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[989].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[990].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[991].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[992].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[993].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[994].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[995].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[996].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[997].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[998].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[999].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1000].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1001].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1002].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1003].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1004].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1005].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1006].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1007].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1008].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1009].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1010].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1011].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1012].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1013].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1014].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1015].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1016].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1017].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1018].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1019].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1020].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1021].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1022].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1023].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1024].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1025].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1026].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1027].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1028].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1029].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1030].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1031].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1032].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1033].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1034].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1035].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1036].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1037].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1038].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1039].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1040].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1041].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1042].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1043].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1044].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1045].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1046].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1047].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1048].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1049].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1050].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1051].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1052].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1053].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1054].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1055].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1056].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1057].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1058].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1059].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1060].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1061].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1062].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1063].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1064].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1065].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1066].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1067].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1068].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1069].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1070].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1071].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1072].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1073].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1074].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1075].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1076].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1077].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1078].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1079].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1080].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1081].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1082].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1083].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1084].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1085].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1086].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1087].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1088].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1089].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1090].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1091].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1092].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1093].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1094].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1095].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1096].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1097].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1098].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1099].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1100].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1101].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1102].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1103].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1104].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1105].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1106].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1107].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1108].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1109].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1110].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1111].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1112].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1113].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1114].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1115].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1116].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1117].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1118].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1119].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1120].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1121].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1122].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1123].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1124].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1125].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1126].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1127].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1128].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1129].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1130].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1131].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1132].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1133].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1134].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1135].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1136].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1137].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1138].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1139].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1140].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1141].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1142].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1143].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1144].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1145].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1146].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1147].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1148].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1149].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1150].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1151].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1152].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1153].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1154].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1155].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1156].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1157].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1158].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1159].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1160].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1161].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1162].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1163].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1164].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1165].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1166].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1167].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1168].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1169].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1170].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1171].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1172].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1173].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1174].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1175].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1176].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1177].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1178].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1179].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1180].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1181].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1182].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1183].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1184].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1185].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1186].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1187].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1188].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1189].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1190].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1191].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1192].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1193].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1194].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1195].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1196].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1197].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1198].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1199].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1200].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1201].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1202].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1203].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1204].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1205].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1206].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1207].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1208].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1209].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1210].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1211].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1212].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1213].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1214].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1215].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1216].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1217].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1218].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1219].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1220].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1221].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1222].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1223].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1224].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1225].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1226].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1227].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1228].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1229].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1230].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1231].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1232].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1233].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1234].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1235].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1236].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1237].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1238].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1239].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1240].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1241].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1242].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1243].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1244].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1245].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1246].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1247].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1248].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1249].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1250].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1251].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1252].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1253].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1254].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1255].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1256].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1257].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1258].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1259].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1260].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1261].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1262].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1263].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1264].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1265].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1266].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1267].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1268].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1269].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1270].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1271].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1272].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1273].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1274].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1275].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1276].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1277].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1278].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1279].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1280].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1281].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1282].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1283].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1284].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1285].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1286].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1287].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1288].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1289].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1290].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1291].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1292].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1293].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1294].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1295].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1296].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1297].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1298].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1299].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1300].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1301].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1302].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1303].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1304].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1305].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1306].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1307].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1308].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1309].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1310].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1311].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1312].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1313].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1314].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1315].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1316].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1317].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1318].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1319].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1320].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1321].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1322].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1323].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1324].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1325].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1326].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1327].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1328].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1329].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1330].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1331].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1332].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1333].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1334].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1335].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1336].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1337].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1338].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1339].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1340].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1341].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1342].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1343].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1344].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1345].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1346].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1347].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1348].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1349].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1350].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1351].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1352].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1353].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1354].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1355].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1356].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1357].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1358].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1359].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1360].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1361].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1362].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1363].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1364].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1365].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1366].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1367].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1368].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1369].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1370].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1371].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1372].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1373].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1374].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1375].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1376].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1377].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1378].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1379].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1380].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1381].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1382].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1383].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1384].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1385].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1386].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1387].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1388].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1389].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1390].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1391].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1392].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1393].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1394].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1395].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1396].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1397].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1398].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1399].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1400].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1401].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1402].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1403].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1404].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1405].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1406].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1407].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1408].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1409].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1410].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1411].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1412].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1413].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1414].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1415].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1416].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1417].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1418].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1419].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1420].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1421].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1422].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1423].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1424].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1425].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1426].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1427].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1428].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1429].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1430].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1431].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1432].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1433].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1434].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1435].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1436].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1437].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1438].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1439].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1440].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1441].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1442].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1443].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1444].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1445].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1446].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1447].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1448].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1449].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1450].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1451].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1452].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1453].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1454].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1455].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1456].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1457].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1458].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1459].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1460].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1461].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1462].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1463].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1464].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1465].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1466].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1467].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1468].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1469].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1470].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1471].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1472].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1473].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1474].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1475].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1476].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1477].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1478].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1479].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1480].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1481].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1482].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1483].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1484].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1485].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1486].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1487].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1488].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1489].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1490].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1491].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1492].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1493].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1494].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1495].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1496].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1497].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1498].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1499].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1500].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1501].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1502].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1503].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1504].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1505].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1506].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1507].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1508].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1509].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1510].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1511].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1512].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1513].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1514].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1515].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1516].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1517].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1518].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1519].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1520].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1521].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1522].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1523].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1524].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1525].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1526].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1527].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1528].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1529].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1530].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1531].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1532].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1533].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1534].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1535].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1536].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1537].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1538].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1539].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1540].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1541].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1542].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1543].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1544].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1545].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1546].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1547].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1548].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1549].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1550].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1551].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1552].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1553].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1554].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1555].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1556].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1557].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1558].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1559].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1560].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1561].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1562].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1563].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1564].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1565].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1566].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1567].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1568].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1569].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1570].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1571].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1572].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1573].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1574].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1575].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1576].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1577].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1578].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1579].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1580].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1581].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1582].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1583].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1584].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1585].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1586].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1587].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1588].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1589].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1590].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1591].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1592].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1593].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1594].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1595].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1596].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1597].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1598].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1599].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1600].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1601].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1602].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1603].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1604].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1605].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1606].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1607].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1608].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1609].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1610].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1611].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1612].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1613].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1614].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1615].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1616].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1617].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1618].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1619].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1620].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1621].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1622].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1623].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1624].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1625].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1626].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1627].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1628].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1629].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1630].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1631].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1632].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1633].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1634].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1635].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1636].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1637].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1638].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1639].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1640].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1641].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1642].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1643].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1644].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1645].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1646].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1647].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1648].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1649].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1650].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1651].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1652].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1653].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1654].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1655].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1656].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1657].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1658].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1659].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1660].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1661].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1662].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1663].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1664].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1665].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1666].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1667].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1668].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1669].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1670].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1671].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1672].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1673].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1674].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1675].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1676].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1677].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1678].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1679].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1680].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1681].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1682].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1683].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1684].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1685].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1686].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1687].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1688].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1689].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1690].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1691].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1692].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1693].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1694].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1695].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1696].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1697].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1698].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1699].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1700].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1701].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1702].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1703].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1704].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1705].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1706].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1707].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1708].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1709].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1710].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1711].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1712].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1713].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1714].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1715].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1716].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1717].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1718].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1719].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1720].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1721].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1722].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1723].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1724].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1725].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1726].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1727].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1728].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1729].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1730].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1731].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1732].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1733].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1734].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1735].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1736].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1737].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1738].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1739].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1740].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1741].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1742].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1743].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1744].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1745].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1746].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1747].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1748].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1749].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1750].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1751].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1752].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1753].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1754].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1755].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1756].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1757].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1758].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1759].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1760].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1761].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1762].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1763].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1764].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1765].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1766].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1767].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1768].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1769].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1770].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1771].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1772].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1773].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1774].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1775].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1776].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1777].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1778].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1779].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1780].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1781].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1782].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1783].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1784].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1785].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1786].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1787].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1788].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1789].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1790].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1791].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1792].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1793].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1794].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1795].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1796].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1797].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1798].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1799].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1800].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1801].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1802].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1803].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1804].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1805].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1806].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1807].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1808].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1809].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1810].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1811].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1812].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1813].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1814].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1815].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1816].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1817].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1818].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1819].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1820].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1821].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1822].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1823].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1824].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1825].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1826].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1827].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1828].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1829].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1830].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1831].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1832].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1833].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1834].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1835].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1836].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1837].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1838].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1839].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1840].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1841].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1842].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1843].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1844].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1845].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1846].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1847].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1848].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1849].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1850].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1851].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1852].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1853].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1854].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1855].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1856].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1857].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1858].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1859].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1860].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1861].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1862].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1863].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1864].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1865].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1866].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1867].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1868].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1869].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1870].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1871].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1872].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1873].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1874].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1875].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1876].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1877].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1878].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1879].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1880].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1881].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1882].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1883].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1884].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1885].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1886].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1887].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1888].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1889].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1890].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1891].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1892].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1893].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1894].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1895].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1896].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1897].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1898].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1899].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1900].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1901].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1902].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1903].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1904].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1905].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1906].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1907].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1908].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1909].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1910].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1911].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1912].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1913].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1914].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1915].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1916].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1917].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1918].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1919].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1920].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1921].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1922].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1923].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1924].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1925].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1926].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1927].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1928].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1929].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1930].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1931].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1932].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1933].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1934].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1935].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1936].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1937].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1938].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1939].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1940].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1941].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1942].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1943].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1944].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1945].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1946].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1947].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1948].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1949].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1950].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1951].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1952].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1953].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1954].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1955].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1956].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1957].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1958].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1959].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1960].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1961].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1962].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1963].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1964].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1965].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1966].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1967].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1968].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1969].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1970].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1971].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1972].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1973].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1974].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1975].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1976].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1977].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1978].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1979].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1980].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1981].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1982].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1983].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1984].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1985].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1986].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1987].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1988].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1989].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1990].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1991].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[1992].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1993].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[1994].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[1995].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[1996].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[1997].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[1998].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[1999].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2000].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2001].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2002].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2003].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2004].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2005].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2006].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2007].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2008].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2009].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2010].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2011].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2012].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2013].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2014].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2015].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2016].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2017].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2018].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2019].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2020].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2021].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2022].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2023].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2024].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2025].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2026].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2027].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2028].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2029].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2030].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2031].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2032].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2033].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2034].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2035].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2036].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2037].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2038].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2039].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2040].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[2041].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2042].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[2043].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[2044].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[2045].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[2046].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[2047].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[2047..0].portawe = ( decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..255], decode2.eq[255..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..254], decode2.eq[254..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..253], decode2.eq[253..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..252], decode2.eq[252..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..251], decode2.eq[251..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..250], decode2.eq[250..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..249], decode2.eq[249..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..248], decode2.eq[248..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..247], decode2.eq[247..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..246], decode2.eq[246..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..245], decode2.eq[245..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..244], decode2.eq[244..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..243], decode2.eq[243..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..242], decode2.eq[242..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..241], decode2.eq[241..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..240], decode2.eq[240..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..239], decode2.eq[239..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..238], decode2.eq[238..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..237], decode2.eq[237..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..236], decode2.eq[236..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..235], decode2.eq[235..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..234], decode2.eq[234..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..233], decode2.eq[233..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..232], decode2.eq[232..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..231], decode2.eq[231..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..230], decode2.eq[230..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..229], decode2.eq[229..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..228], decode2.eq[228..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..227], decode2.eq[227..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..226], decode2.eq[226..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..225], decode2.eq[225..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..224], decode2.eq[224..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..223], decode2.eq[223..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..222], decode2.eq[222..221], decode2.eq[221..221], decode2.eq[221..221], decode2.eq[221..221], decode2.eq[221..221], decode2.eq[221..221], decode2.eq[221..221], decode2.eq[221..220], decode2.eq[220..220], decode2.eq[220..220], decode2.eq[220..220], decode2.eq[220..220], decode2.eq[220..220], decode2.eq[220..220], decode2.eq[220..219], decode2.eq[219..219], decode2.eq[219..219], decode2.eq[219..219], decode2.eq[219..219], decode2.eq[219..219], decode2.eq[219..219], decode2.eq[219..218], decode2.eq[218..218], decode2.eq[218..218], decode2.eq[218..218], decode2.eq[218..218], decode2.eq[218..218], decode2.eq[218..218], decode2.eq[218..217], decode2.eq[217..217], decode2.eq[217..217], decode2.eq[217..217], decode2.eq[217..217], decode2.eq[217..217], decode2.eq[217..217], decode2.eq[217..216], decode2.eq[216..216], decode2.eq[216..216], decode2.eq[216..216], decode2.eq[216..216], decode2.eq[216..216], decode2.eq[216..216], decode2.eq[216..215], decode2.eq[215..215], decode2.eq[215..215], decode2.eq[215..215], decode2.eq[215..215], decode2.eq[215..215], decode2.eq[215..215], decode2.eq[215..214], decode2.eq[214..214], decode2.eq[214..214], decode2.eq[214..214], decode2.eq[214..214], decode2.eq[214..214], decode2.eq[214..214], decode2.eq[214..213], decode2.eq[213..213], decode2.eq[213..213], decode2.eq[213..213], decode2.eq[213..213], decode2.eq[213..213], decode2.eq[213..213], decode2.eq[213..212], decode2.eq[212..212], decode2.eq[212..212], decode2.eq[212..212], decode2.eq[212..212], decode2.eq[212..212], decode2.eq[212..212], decode2.eq[212..211], decode2.eq[211..211], decode2.eq[211..211], decode2.eq[211..211], decode2.eq[211..211], decode2.eq[211..211], decode2.eq[211..211], decode2.eq[211..210], decode2.eq[210..210], decode2.eq[210..210], decode2.eq[210..210], decode2.eq[210..210], decode2.eq[210..210], decode2.eq[210..210], decode2.eq[210..209], decode2.eq[209..209], decode2.eq[209..209], decode2.eq[209..209], decode2.eq[209..209], decode2.eq[209..209], decode2.eq[209..209], decode2.eq[209..208], decode2.eq[208..208], decode2.eq[208..208], decode2.eq[208..208], decode2.eq[208..208], decode2.eq[208..208], decode2.eq[208..208], decode2.eq[208..207], decode2.eq[207..207], decode2.eq[207..207], decode2.eq[207..207], decode2.eq[207..207], decode2.eq[207..207], decode2.eq[207..207], decode2.eq[207..206], decode2.eq[206..206], decode2.eq[206..206], decode2.eq[206..206], decode2.eq[206..206], decode2.eq[206..206], decode2.eq[206..206], decode2.eq[206..205], decode2.eq[205..205], decode2.eq[205..205], decode2.eq[205..205], decode2.eq[205..205], decode2.eq[205..205], decode2.eq[205..205], decode2.eq[205..204], decode2.eq[204..204], decode2.eq[204..204], decode2.eq[204..204], decode2.eq[204..204], decode2.eq[204..204], decode2.eq[204..204], decode2.eq[204..203], decode2.eq[203..203], decode2.eq[203..203], decode2.eq[203..203], decode2.eq[203..203], decode2.eq[203..203], decode2.eq[203..203], decode2.eq[203..202], decode2.eq[202..202], decode2.eq[202..202], decode2.eq[202..202], decode2.eq[202..202], decode2.eq[202..202], decode2.eq[202..202], decode2.eq[202..201], decode2.eq[201..201], decode2.eq[201..201], decode2.eq[201..201], decode2.eq[201..201], decode2.eq[201..201], decode2.eq[201..201], decode2.eq[201..200], decode2.eq[200..200], decode2.eq[200..200], decode2.eq[200..200], decode2.eq[200..200], decode2.eq[200..200], decode2.eq[200..200], decode2.eq[200..199], decode2.eq[199..199], decode2.eq[199..199], decode2.eq[199..199], decode2.eq[199..199], decode2.eq[199..199], decode2.eq[199..199], decode2.eq[199..198], decode2.eq[198..198], decode2.eq[198..198], decode2.eq[198..198], decode2.eq[198..198], decode2.eq[198..198], decode2.eq[198..198], decode2.eq[198..197], decode2.eq[197..197], decode2.eq[197..197], decode2.eq[197..197], decode2.eq[197..197], decode2.eq[197..197], decode2.eq[197..197], decode2.eq[197..196], decode2.eq[196..196], decode2.eq[196..196], decode2.eq[196..196], decode2.eq[196..196], decode2.eq[196..196], decode2.eq[196..196], decode2.eq[196..195], decode2.eq[195..195], decode2.eq[195..195], decode2.eq[195..195], decode2.eq[195..195], decode2.eq[195..195], decode2.eq[195..195], decode2.eq[195..194], decode2.eq[194..194], decode2.eq[194..194], decode2.eq[194..194], decode2.eq[194..194], decode2.eq[194..194], decode2.eq[194..194], decode2.eq[194..193], decode2.eq[193..193], decode2.eq[193..193], decode2.eq[193..193], decode2.eq[193..193], decode2.eq[193..193], decode2.eq[193..193], decode2.eq[193..192], decode2.eq[192..192], decode2.eq[192..192], decode2.eq[192..192], decode2.eq[192..192], decode2.eq[192..192], decode2.eq[192..192], decode2.eq[192..191], decode2.eq[191..191], decode2.eq[191..191], decode2.eq[191..191], decode2.eq[191..191], decode2.eq[191..191], decode2.eq[191..191], decode2.eq[191..190], decode2.eq[190..190], decode2.eq[190..190], decode2.eq[190..190], decode2.eq[190..190], decode2.eq[190..190], decode2.eq[190..190], decode2.eq[190..189], decode2.eq[189..189], decode2.eq[189..189], decode2.eq[189..189], decode2.eq[189..189], decode2.eq[189..189], decode2.eq[189..189], decode2.eq[189..188], decode2.eq[188..188], decode2.eq[188..188], decode2.eq[188..188], decode2.eq[188..188], decode2.eq[188..188], decode2.eq[188..188], decode2.eq[188..187], decode2.eq[187..187], decode2.eq[187..187], decode2.eq[187..187], decode2.eq[187..187], decode2.eq[187..187], decode2.eq[187..187], decode2.eq[187..186], decode2.eq[186..186], decode2.eq[186..186], decode2.eq[186..186], decode2.eq[186..186], decode2.eq[186..186], decode2.eq[186..186], decode2.eq[186..185], decode2.eq[185..185], decode2.eq[185..185], decode2.eq[185..185], decode2.eq[185..185], decode2.eq[185..185], decode2.eq[185..185], decode2.eq[185..184], decode2.eq[184..184], decode2.eq[184..184], decode2.eq[184..184], decode2.eq[184..184], decode2.eq[184..184], decode2.eq[184..184], decode2.eq[184..183], decode2.eq[183..183], decode2.eq[183..183], decode2.eq[183..183], decode2.eq[183..183], decode2.eq[183..183], decode2.eq[183..183], decode2.eq[183..182], decode2.eq[182..182], decode2.eq[182..182], decode2.eq[182..182], decode2.eq[182..182], decode2.eq[182..182], decode2.eq[182..182], decode2.eq[182..181], decode2.eq[181..181], decode2.eq[181..181], decode2.eq[181..181], decode2.eq[181..181], decode2.eq[181..181], decode2.eq[181..181], decode2.eq[181..180], decode2.eq[180..180], decode2.eq[180..180], decode2.eq[180..180], decode2.eq[180..180], decode2.eq[180..180], decode2.eq[180..180], decode2.eq[180..179], decode2.eq[179..179], decode2.eq[179..179], decode2.eq[179..179], decode2.eq[179..179], decode2.eq[179..179], decode2.eq[179..179], decode2.eq[179..178], decode2.eq[178..178], decode2.eq[178..178], decode2.eq[178..178], decode2.eq[178..178], decode2.eq[178..178], decode2.eq[178..178], decode2.eq[178..177], decode2.eq[177..177], decode2.eq[177..177], decode2.eq[177..177], decode2.eq[177..177], decode2.eq[177..177], decode2.eq[177..177], decode2.eq[177..176], decode2.eq[176..176], decode2.eq[176..176], decode2.eq[176..176], decode2.eq[176..176], decode2.eq[176..176], decode2.eq[176..176], decode2.eq[176..175], decode2.eq[175..175], decode2.eq[175..175], decode2.eq[175..175], decode2.eq[175..175], decode2.eq[175..175], decode2.eq[175..175], decode2.eq[175..174], decode2.eq[174..174], decode2.eq[174..174], decode2.eq[174..174], decode2.eq[174..174], decode2.eq[174..174], decode2.eq[174..174], decode2.eq[174..173], decode2.eq[173..173], decode2.eq[173..173], decode2.eq[173..173], decode2.eq[173..173], decode2.eq[173..173], decode2.eq[173..173], decode2.eq[173..172], decode2.eq[172..172], decode2.eq[172..172], decode2.eq[172..172], decode2.eq[172..172], decode2.eq[172..172], decode2.eq[172..172], decode2.eq[172..171], decode2.eq[171..171], decode2.eq[171..171], decode2.eq[171..171], decode2.eq[171..171], decode2.eq[171..171], decode2.eq[171..171], decode2.eq[171..170], decode2.eq[170..170], decode2.eq[170..170], decode2.eq[170..170], decode2.eq[170..170], decode2.eq[170..170], decode2.eq[170..170], decode2.eq[170..169], decode2.eq[169..169], decode2.eq[169..169], decode2.eq[169..169], decode2.eq[169..169], decode2.eq[169..169], decode2.eq[169..169], decode2.eq[169..168], decode2.eq[168..168], decode2.eq[168..168], decode2.eq[168..168], decode2.eq[168..168], decode2.eq[168..168], decode2.eq[168..168], decode2.eq[168..167], decode2.eq[167..167], decode2.eq[167..167], decode2.eq[167..167], decode2.eq[167..167], decode2.eq[167..167], decode2.eq[167..167], decode2.eq[167..166], decode2.eq[166..166], decode2.eq[166..166], decode2.eq[166..166], decode2.eq[166..166], decode2.eq[166..166], decode2.eq[166..166], decode2.eq[166..165], decode2.eq[165..165], decode2.eq[165..165], decode2.eq[165..165], decode2.eq[165..165], decode2.eq[165..165], decode2.eq[165..165], decode2.eq[165..164], decode2.eq[164..164], decode2.eq[164..164], decode2.eq[164..164], decode2.eq[164..164], decode2.eq[164..164], decode2.eq[164..164], decode2.eq[164..163], decode2.eq[163..163], decode2.eq[163..163], decode2.eq[163..163], decode2.eq[163..163], decode2.eq[163..163], decode2.eq[163..163], decode2.eq[163..162], decode2.eq[162..162], decode2.eq[162..162], decode2.eq[162..162], decode2.eq[162..162], decode2.eq[162..162], decode2.eq[162..162], decode2.eq[162..161], decode2.eq[161..161], decode2.eq[161..161], decode2.eq[161..161], decode2.eq[161..161], decode2.eq[161..161], decode2.eq[161..161], decode2.eq[161..160], decode2.eq[160..160], decode2.eq[160..160], decode2.eq[160..160], decode2.eq[160..160], decode2.eq[160..160], decode2.eq[160..160], decode2.eq[160..159], decode2.eq[159..159], decode2.eq[159..159], decode2.eq[159..159], decode2.eq[159..159], decode2.eq[159..159], decode2.eq[159..159], decode2.eq[159..158], decode2.eq[158..158], decode2.eq[158..158], decode2.eq[158..158], decode2.eq[158..158], decode2.eq[158..158], decode2.eq[158..158], decode2.eq[158..157], decode2.eq[157..157], decode2.eq[157..157], decode2.eq[157..157], decode2.eq[157..157], decode2.eq[157..157], decode2.eq[157..157], decode2.eq[157..156], decode2.eq[156..156], decode2.eq[156..156], decode2.eq[156..156], decode2.eq[156..156], decode2.eq[156..156], decode2.eq[156..156], decode2.eq[156..155], decode2.eq[155..155], decode2.eq[155..155], decode2.eq[155..155], decode2.eq[155..155], decode2.eq[155..155], decode2.eq[155..155], decode2.eq[155..154], decode2.eq[154..154], decode2.eq[154..154], decode2.eq[154..154], decode2.eq[154..154], decode2.eq[154..154], decode2.eq[154..154], decode2.eq[154..153], decode2.eq[153..153], decode2.eq[153..153], decode2.eq[153..153], decode2.eq[153..153], decode2.eq[153..153], decode2.eq[153..153], decode2.eq[153..152], decode2.eq[152..152], decode2.eq[152..152], decode2.eq[152..152], decode2.eq[152..152], decode2.eq[152..152], decode2.eq[152..152], decode2.eq[152..151], decode2.eq[151..151], decode2.eq[151..151], decode2.eq[151..151], decode2.eq[151..151], decode2.eq[151..151], decode2.eq[151..151], decode2.eq[151..150], decode2.eq[150..150], decode2.eq[150..150], decode2.eq[150..150], decode2.eq[150..150], decode2.eq[150..150], decode2.eq[150..150], decode2.eq[150..149], decode2.eq[149..149], decode2.eq[149..149], decode2.eq[149..149], decode2.eq[149..149], decode2.eq[149..149], decode2.eq[149..149], decode2.eq[149..148], decode2.eq[148..148], decode2.eq[148..148], decode2.eq[148..148], decode2.eq[148..148], decode2.eq[148..148], decode2.eq[148..148], decode2.eq[148..147], decode2.eq[147..147], decode2.eq[147..147], decode2.eq[147..147], decode2.eq[147..147], decode2.eq[147..147], decode2.eq[147..147], decode2.eq[147..146], decode2.eq[146..146], decode2.eq[146..146], decode2.eq[146..146], decode2.eq[146..146], decode2.eq[146..146], decode2.eq[146..146], decode2.eq[146..145], decode2.eq[145..145], decode2.eq[145..145], decode2.eq[145..145], decode2.eq[145..145], decode2.eq[145..145], decode2.eq[145..145], decode2.eq[145..144], decode2.eq[144..144], decode2.eq[144..144], decode2.eq[144..144], decode2.eq[144..144], decode2.eq[144..144], decode2.eq[144..144], decode2.eq[144..143], decode2.eq[143..143], decode2.eq[143..143], decode2.eq[143..143], decode2.eq[143..143], decode2.eq[143..143], decode2.eq[143..143], decode2.eq[143..142], decode2.eq[142..142], decode2.eq[142..142], decode2.eq[142..142], decode2.eq[142..142], decode2.eq[142..142], decode2.eq[142..142], decode2.eq[142..141], decode2.eq[141..141], decode2.eq[141..141], decode2.eq[141..141], decode2.eq[141..141], decode2.eq[141..141], decode2.eq[141..141], decode2.eq[141..140], decode2.eq[140..140], decode2.eq[140..140], decode2.eq[140..140], decode2.eq[140..140], decode2.eq[140..140], decode2.eq[140..140], decode2.eq[140..139], decode2.eq[139..139], decode2.eq[139..139], decode2.eq[139..139], decode2.eq[139..139], decode2.eq[139..139], decode2.eq[139..139], decode2.eq[139..138], decode2.eq[138..138], decode2.eq[138..138], decode2.eq[138..138], decode2.eq[138..138], decode2.eq[138..138], decode2.eq[138..138], decode2.eq[138..137], decode2.eq[137..137], decode2.eq[137..137], decode2.eq[137..137], decode2.eq[137..137], decode2.eq[137..137], decode2.eq[137..137], decode2.eq[137..136], decode2.eq[136..136], decode2.eq[136..136], decode2.eq[136..136], decode2.eq[136..136], decode2.eq[136..136], decode2.eq[136..136], decode2.eq[136..135], decode2.eq[135..135], decode2.eq[135..135], decode2.eq[135..135], decode2.eq[135..135], decode2.eq[135..135], decode2.eq[135..135], decode2.eq[135..134], decode2.eq[134..134], decode2.eq[134..134], decode2.eq[134..134], decode2.eq[134..134], decode2.eq[134..134], decode2.eq[134..134], decode2.eq[134..133], decode2.eq[133..133], decode2.eq[133..133], decode2.eq[133..133], decode2.eq[133..133], decode2.eq[133..133], decode2.eq[133..133], decode2.eq[133..132], decode2.eq[132..132], decode2.eq[132..132], decode2.eq[132..132], decode2.eq[132..132], decode2.eq[132..132], decode2.eq[132..132], decode2.eq[132..131], decode2.eq[131..131], decode2.eq[131..131], decode2.eq[131..131], decode2.eq[131..131], decode2.eq[131..131], decode2.eq[131..131], decode2.eq[131..130], decode2.eq[130..130], decode2.eq[130..130], decode2.eq[130..130], decode2.eq[130..130], decode2.eq[130..130], decode2.eq[130..130], decode2.eq[130..129], decode2.eq[129..129], decode2.eq[129..129], decode2.eq[129..129], decode2.eq[129..129], decode2.eq[129..129], decode2.eq[129..129], decode2.eq[129..128], decode2.eq[128..128], decode2.eq[128..128], decode2.eq[128..128], decode2.eq[128..128], decode2.eq[128..128], decode2.eq[128..128], decode2.eq[128..127], decode2.eq[127..127], decode2.eq[127..127], decode2.eq[127..127], decode2.eq[127..127], decode2.eq[127..127], decode2.eq[127..127], decode2.eq[127..126], decode2.eq[126..126], decode2.eq[126..126], decode2.eq[126..126], decode2.eq[126..126], decode2.eq[126..126], decode2.eq[126..126], decode2.eq[126..125], decode2.eq[125..125], decode2.eq[125..125], decode2.eq[125..125], decode2.eq[125..125], decode2.eq[125..125], decode2.eq[125..125], decode2.eq[125..124], decode2.eq[124..124], decode2.eq[124..124], decode2.eq[124..124], decode2.eq[124..124], decode2.eq[124..124], decode2.eq[124..124], decode2.eq[124..123], decode2.eq[123..123], decode2.eq[123..123], decode2.eq[123..123], decode2.eq[123..123], decode2.eq[123..123], decode2.eq[123..123], decode2.eq[123..122], decode2.eq[122..122], decode2.eq[122..122], decode2.eq[122..122], decode2.eq[122..122], decode2.eq[122..122], decode2.eq[122..122], decode2.eq[122..121], decode2.eq[121..121], decode2.eq[121..121], decode2.eq[121..121], decode2.eq[121..121], decode2.eq[121..121], decode2.eq[121..121], decode2.eq[121..120], decode2.eq[120..120], decode2.eq[120..120], decode2.eq[120..120], decode2.eq[120..120], decode2.eq[120..120], decode2.eq[120..120], decode2.eq[120..119], decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..119], decode2.eq[119..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..118], decode2.eq[118..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..117], decode2.eq[117..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..116], decode2.eq[116..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..115], decode2.eq[115..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..114], decode2.eq[114..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..113], decode2.eq[113..112], decode2.eq[112..112], decode2.eq[112..112], decode2.eq[112..112], decode2.eq[112..112], decode2.eq[112..112], decode2.eq[112..112], decode2.eq[112..111], decode2.eq[111..111], decode2.eq[111..111], decode2.eq[111..111], decode2.eq[111..111], decode2.eq[111..111], decode2.eq[111..111], decode2.eq[111..110], decode2.eq[110..110], decode2.eq[110..110], decode2.eq[110..110], decode2.eq[110..110], decode2.eq[110..110], decode2.eq[110..110], decode2.eq[110..109], decode2.eq[109..109], decode2.eq[109..109], decode2.eq[109..109], decode2.eq[109..109], decode2.eq[109..109], decode2.eq[109..109], decode2.eq[109..108], decode2.eq[108..108], decode2.eq[108..108], decode2.eq[108..108], decode2.eq[108..108], decode2.eq[108..108], decode2.eq[108..108], decode2.eq[108..107], decode2.eq[107..107], decode2.eq[107..107], decode2.eq[107..107], decode2.eq[107..107], decode2.eq[107..107], decode2.eq[107..107], decode2.eq[107..106], decode2.eq[106..106], decode2.eq[106..106], decode2.eq[106..106], decode2.eq[106..106], decode2.eq[106..106], decode2.eq[106..106], decode2.eq[106..105], decode2.eq[105..105], decode2.eq[105..105], decode2.eq[105..105], decode2.eq[105..105], decode2.eq[105..105], decode2.eq[105..105], decode2.eq[105..104], decode2.eq[104..104], decode2.eq[104..104], decode2.eq[104..104], decode2.eq[104..104], decode2.eq[104..104], decode2.eq[104..104], decode2.eq[104..103], decode2.eq[103..103], decode2.eq[103..103], decode2.eq[103..103], decode2.eq[103..103], decode2.eq[103..103], decode2.eq[103..103], decode2.eq[103..102], decode2.eq[102..102], decode2.eq[102..102], decode2.eq[102..102], decode2.eq[102..102], decode2.eq[102..102], decode2.eq[102..102], decode2.eq[102..101], decode2.eq[101..101], decode2.eq[101..101], decode2.eq[101..101], decode2.eq[101..101], decode2.eq[101..101], decode2.eq[101..101], decode2.eq[101..100], decode2.eq[100..100], decode2.eq[100..100], decode2.eq[100..100], decode2.eq[100..100], decode2.eq[100..100], decode2.eq[100..100], decode2.eq[100..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..99], decode2.eq[99..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..98], decode2.eq[98..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..97], decode2.eq[97..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..96], decode2.eq[96..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..95], decode2.eq[95..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..94], decode2.eq[94..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..93], decode2.eq[93..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..92], decode2.eq[92..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..91], decode2.eq[91..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..90], decode2.eq[90..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..89], decode2.eq[89..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..88], decode2.eq[88..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..87], decode2.eq[87..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..86], decode2.eq[86..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..85], decode2.eq[85..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..84], decode2.eq[84..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..83], decode2.eq[83..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..82], decode2.eq[82..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..81], decode2.eq[81..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..80], decode2.eq[80..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..79], decode2.eq[79..78], decode2.eq[78..78], decode2.eq[78..78], decode2.eq[78..78], decode2.eq[78..78], decode2.eq[78..78], decode2.eq[78..78], decode2.eq[78..77], decode2.eq[77..77], decode2.eq[77..77], decode2.eq[77..77], decode2.eq[77..77], decode2.eq[77..77], decode2.eq[77..77], decode2.eq[77..76], decode2.eq[76..76], decode2.eq[76..76], decode2.eq[76..76], decode2.eq[76..76], decode2.eq[76..76], decode2.eq[76..76], decode2.eq[76..75], decode2.eq[75..75], decode2.eq[75..75], decode2.eq[75..75], decode2.eq[75..75], decode2.eq[75..75], decode2.eq[75..75], decode2.eq[75..74], decode2.eq[74..74], decode2.eq[74..74], decode2.eq[74..74], decode2.eq[74..74], decode2.eq[74..74], decode2.eq[74..74], decode2.eq[74..73], decode2.eq[73..73], decode2.eq[73..73], decode2.eq[73..73], decode2.eq[73..73], decode2.eq[73..73], decode2.eq[73..73], decode2.eq[73..72], decode2.eq[72..72], decode2.eq[72..72], decode2.eq[72..72], decode2.eq[72..72], decode2.eq[72..72], decode2.eq[72..72], decode2.eq[72..71], decode2.eq[71..71], decode2.eq[71..71], decode2.eq[71..71], decode2.eq[71..71], decode2.eq[71..71], decode2.eq[71..71], decode2.eq[71..70], decode2.eq[70..70], decode2.eq[70..70], decode2.eq[70..70], decode2.eq[70..70], decode2.eq[70..70], decode2.eq[70..70], decode2.eq[70..69], decode2.eq[69..69], decode2.eq[69..69], decode2.eq[69..69], decode2.eq[69..69], decode2.eq[69..69], decode2.eq[69..69], decode2.eq[69..68], decode2.eq[68..68], decode2.eq[68..68], decode2.eq[68..68], decode2.eq[68..68], decode2.eq[68..68], decode2.eq[68..68], decode2.eq[68..67], decode2.eq[67..67], decode2.eq[67..67], decode2.eq[67..67], decode2.eq[67..67], decode2.eq[67..67], decode2.eq[67..67], decode2.eq[67..66], decode2.eq[66..66], decode2.eq[66..66], decode2.eq[66..66], decode2.eq[66..66], decode2.eq[66..66], decode2.eq[66..66], decode2.eq[66..65], decode2.eq[65..65], decode2.eq[65..65], decode2.eq[65..65], decode2.eq[65..65], decode2.eq[65..65], decode2.eq[65..65], decode2.eq[65..64], decode2.eq[64..64], decode2.eq[64..64], decode2.eq[64..64], decode2.eq[64..64], decode2.eq[64..64], decode2.eq[64..64], decode2.eq[64..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
|
|
ram_block1a[2047..0].portbaddr[] = ( address_b_wire[12..0]);
|
|
ram_block1a[2047..0].portbre = rden_b;
|
|
address_a_wire[] = address_a[];
|
|
address_b_sel[7..0] = address_b[20..13];
|
|
address_b_wire[] = address_b[];
|
|
q_b[] = mux3.result[];
|
|
END;
|
|
--VALID FILE
|