225 lines
15 KiB
VHDL
225 lines
15 KiB
VHDL
-- #################################################################################################
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-- # << The NEORV32 RISC-V Processor - LiteX NEORV32 Core Complex Wrapper >> #
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-- # ********************************************************************************************* #
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-- # __ _ __ _ __ #
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-- # / / (_) /____ | |/_/ #
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-- # / /__/ / __/ -_)> < #
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-- # /____/_/\__/\__/_/|_| #
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-- # Build your hardware, easily! #
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-- # #
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-- # Unless otherwise noted, LiteX is copyright (C) 2012-2022 Enjoy-Digital. All rights reserved. #
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-- # LiteX HQ: https://github.com/enjoy-digital/litex #
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-- # #
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-- # ********************************************************************************************* #
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-- # NEORV32 Core Complex wrapper for the LiteX SoC builder framework. #
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-- # https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/neorv32 #
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-- # #
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-- # This wrapper provides four pre-configured core complex configurations: "minimal", "lite", #
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-- # "standard" and "full". See the 'configs_c' table for more details which RISC-V ISA extensions #
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-- # and module parameters are used by each of the these configurations. All configurations can be #
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-- # used with the RISC-V-compatible on-chip debugger. #
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-- # #
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-- # === Bus Interface === #
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-- # This wrappers uses the "pipelined" Wishbone b4 protocol for the bus interface. See the #
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-- # "global configuration" constants for further bus configuration parameters (endianness, #
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-- # timeout, etc.). #
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-- # #
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-- # === Interrupt ==== #
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-- # The external interrupt signal is delegated to the CPU as RISC-V "machine external interrupt #
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-- # (MTI)". Note that this IRQ signal is high-active - once set the signal has to stay high until #
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-- # the interrupt request is explicitly acknowledged (e.g. writing to a memory-mapped register)! #
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-- # #
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-- # === Core Complex Address Space === #
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-- # Note that the NEORV32 core complex occupies a small fraction of the total 32-bit address #
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-- # space for internal components (machine timer, on-chip-debugger, ...). This address space #
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-- # starts at address 0xffff0000 and ends at 0xffffffff. Any CPU access to this address space #
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-- # will NOT be delegated to bus interface of the core complex! #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_litex_core_complex is
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generic (
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CONFIG : natural; -- configuration select (0=minimal, 1=lite, 2=standard, 3=full)
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DEBUG : boolean -- enable on-chip debugger, valid for all configurations
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);
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port (
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-- Global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- JTAG on-chip debugger interface --
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jtag_trst_i : in std_ulogic; -- low-active TAP reset (optional)
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jtag_tck_i : in std_ulogic; -- serial clock
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jtag_tdi_i : in std_ulogic; -- serial data input
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jtag_tdo_o : out std_ulogic; -- serial data output
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jtag_tms_i : in std_ulogic; -- mode select
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-- Wishbone bus interface --
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_err_i : in std_ulogic; -- transfer error
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-- CPU interrupt --
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mext_irq_i : in std_ulogic -- RISC-V machine external interrupt (MEI)
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);
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end neorv32_litex_core_complex;
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architecture neorv32_litex_core_complex_rtl of neorv32_litex_core_complex is
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-- advance configuration --
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constant num_configs_c : natural := 4; -- number of pre-defined configurations
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constant wb_timeout_c : natural := 4096; -- external bus interface timeout cycles
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constant big_endian_c : boolean := false; -- external bus interface endianness; default is little-endian
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-- helpers --
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type bool_t is array (0 to num_configs_c-1) of boolean;
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type natural_t is array (0 to num_configs_c-1) of natural;
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type configs_t is record
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riscv_c : bool_t;
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riscv_m : bool_t;
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riscv_u : bool_t;
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riscv_zicntr : bool_t;
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riscv_zihpm : bool_t;
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fast_ops : bool_t;
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ipb : natural_t;
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pmp_nr : natural_t;
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hpm_nr : natural_t;
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icache_en : bool_t;
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icache_nb : natural_t;
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icache_bs : natural_t;
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icache_as : natural_t;
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mtime : bool_t;
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end record;
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-- core complex configurations --
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constant configs_c : configs_t := (
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-- minimal lite standard full
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riscv_c => ( false, true, true, true ), -- RISC-V compressed instructions 'C'
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riscv_m => ( false, true, true, true ), -- RISC-V hardware mul/div 'M'
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riscv_u => ( false, false, false, true ), -- RISC-V user mode 'U'
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riscv_zicntr => ( false, false, true, true ), -- RISC-V standard CPU counters 'Zicntr'
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riscv_zihpm => ( false, false, false, true ), -- RISC-V hardware performance monitors 'Zihpm'
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fast_ops => ( false, false, true, true ), -- use DSPs and barrel-shifters
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ipb => ( 2, 2, 4, 4 ), -- instruction prefetch buffer depth, power of two, min 2
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pmp_nr => ( 0, 0, 0, 8 ), -- number of PMP regions (0..16)
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hpm_nr => ( 0, 0, 0, 8 ), -- number of HPM counters (0..29)
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icache_en => ( false, false, true, true ), -- instruction cache enabled
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icache_nb => ( 0, 0, 8, 8 ), -- number of cache blocks (lines), power of two
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icache_bs => ( 0, 0, 64, 256 ), -- size of cache clock (lines) in bytes, power of two
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icache_as => ( 1, 1, 1, 2 ), -- associativity (1 or 2)
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mtime => ( false, true, true, true ) -- RISC-V machine system timers
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);
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begin
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-- NEORV32 Core Complex -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_core_complex: neorv32_top
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generic map (
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-- General --
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CLOCK_FREQUENCY => 0, -- clock frequency of clk_i in Hz [not required by the core complex]
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => DEBUG, -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => configs_c.riscv_c(CONFIG), -- implement compressed extension?
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CPU_EXTENSION_RISCV_M => configs_c.riscv_m(CONFIG), -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U => configs_c.riscv_u(CONFIG), -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicntr => configs_c.riscv_zicntr(CONFIG), -- implement base counters?
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CPU_EXTENSION_RISCV_Zihpm => configs_c.riscv_zihpm(CONFIG), -- implement hardware performance monitors?
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CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
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-- Tuning Options --
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FAST_MUL_EN => configs_c.fast_ops(CONFIG), -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => configs_c.fast_ops(CONFIG), -- use barrel shifter for shift operations
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CPU_IPB_ENTRIES => configs_c.ipb(CONFIG), -- entries in instruction prefetch buffer, has to be a power of 2, min 2
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => configs_c.pmp_nr(CONFIG), -- number of regions (0..16)
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PMP_MIN_GRANULARITY => 4, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => configs_c.hpm_nr(CONFIG), -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH => 64, -- total size of HPM counters (0..64)
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-- Internal Instruction Cache (iCACHE) --
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ICACHE_EN => configs_c.icache_en(CONFIG), -- implement instruction cache
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ICACHE_NUM_BLOCKS => configs_c.icache_nb(CONFIG), -- i-cache: number of blocks (min 1), has to be a power of 2
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ICACHE_BLOCK_SIZE => configs_c.icache_bs(CONFIG), -- i-cache: block size in bytes (min 4), has to be a power of 2
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ICACHE_ASSOCIATIVITY => configs_c.icache_as(CONFIG), -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
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-- External memory interface (WISHBONE) --
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MEM_EXT_EN => true, -- implement external memory bus interface?
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MEM_EXT_TIMEOUT => wb_timeout_c, -- cycles after a pending bus access auto-terminates (0 = disabled)
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MEM_EXT_PIPE_MODE => true, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
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MEM_EXT_BIG_ENDIAN => big_endian_c, -- byte order: true=big-endian, false=little-endian
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MEM_EXT_ASYNC_RX => true, -- use register buffer for RX data when false
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MEM_EXT_ASYNC_TX => true, -- use register buffer for TX data when false
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-- Processor peripherals --
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IO_MTIME_EN => configs_c.mtime(CONFIG) -- implement machine system timer (MTIME)?
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)
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port map (
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-- Global control --
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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-- JTAG on-chip debugger interface --
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jtag_trst_i => jtag_trst_i, -- low-active TAP reset (optional)
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jtag_tck_i => jtag_tck_i, -- serial clock
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jtag_tdi_i => jtag_tdi_i, -- serial data input
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jtag_tdo_o => jtag_tdo_o, -- serial data output
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jtag_tms_i => jtag_tms_i, -- mode select
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-- Wishbone bus interface --
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wb_tag_o => open, -- request tag
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wb_adr_o => wb_adr_o, -- address
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wb_dat_i => wb_dat_i, -- read data
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wb_dat_o => wb_dat_o, -- write data
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wb_we_o => wb_we_o, -- read/write
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wb_sel_o => wb_sel_o, -- byte enable
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wb_stb_o => wb_stb_o, -- strobe
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wb_cyc_o => wb_cyc_o, -- valid cycle
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wb_ack_i => wb_ack_i, -- transfer acknowledge
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wb_err_i => wb_err_i, -- transfer error
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-- CPU Interrupts --
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mext_irq_i => mext_irq_i -- machine external interrupt
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);
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end neorv32_litex_core_complex_rtl;
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