784 lines
23 KiB
Text
784 lines
23 KiB
Text
Tiny Code Generator - Fabrice Bellard.
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1) Introduction
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TCG (Tiny Code Generator) began as a generic backend for a C
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compiler. It was simplified to be used in QEMU. It also has its roots
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in the QOP code generator written by Paul Brook.
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2) Definitions
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TCG receives RISC-like "TCG ops" and performs some optimizations on them,
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including liveness analysis and trivial constant expression
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evaluation. TCG ops are then implemented in the host CPU back end,
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also known as the TCG "target".
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The TCG "target" is the architecture for which we generate the
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code. It is of course not the same as the "target" of QEMU which is
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the emulated architecture. As TCG started as a generic C backend used
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for cross compiling, it is assumed that the TCG target is different
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from the host, although it is never the case for QEMU.
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In this document, we use "guest" to specify what architecture we are
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emulating; "target" always means the TCG target, the machine on which
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we are running QEMU.
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A TCG "function" corresponds to a QEMU Translated Block (TB).
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A TCG "temporary" is a variable only live in a basic
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block. Temporaries are allocated explicitly in each function.
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A TCG "local temporary" is a variable only live in a function. Local
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temporaries are allocated explicitly in each function.
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A TCG "global" is a variable which is live in all the functions
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(equivalent of a C global variable). They are defined before the
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functions defined. A TCG global can be a memory location (e.g. a QEMU
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CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
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or a memory location which is stored in a register outside QEMU TBs
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(not implemented yet).
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A TCG "basic block" corresponds to a list of instructions terminated
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by a branch instruction.
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An operation with "undefined behavior" may result in a crash.
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An operation with "unspecified behavior" shall not crash. However,
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the result may be one of several possibilities so may be considered
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an "undefined result".
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3) Intermediate representation
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3.1) Introduction
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TCG instructions operate on variables which are temporaries, local
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temporaries or globals. TCG instructions and variables are strongly
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typed. Two types are supported: 32 bit integers and 64 bit
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integers. Pointers are defined as an alias to 32 bit or 64 bit
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integers depending on the TCG target word size.
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Each instruction has a fixed number of output variable operands, input
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variable operands and always constant operands.
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The notable exception is the call instruction which has a variable
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number of outputs and inputs.
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In the textual form, output operands usually come first, followed by
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input operands, followed by constant operands. The output type is
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included in the instruction name. Constants are prefixed with a '$'.
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add_i32 t0, t1, t2 (t0 <- t1 + t2)
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3.2) Assumptions
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* Basic blocks
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- Basic blocks end after branches (e.g. brcond_i32 instruction),
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goto_tb and exit_tb instructions.
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- Basic blocks start after the end of a previous basic block, or at a
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set_label instruction.
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After the end of a basic block, the content of temporaries is
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destroyed, but local temporaries and globals are preserved.
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* Floating point types are not supported yet
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* Pointers: depending on the TCG target, pointer size is 32 bit or 64
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bit. The type TCG_TYPE_PTR is an alias to TCG_TYPE_I32 or
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TCG_TYPE_I64.
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* Helpers:
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Using the tcg_gen_helper_x_y it is possible to call any function
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taking i32, i64 or pointer types. By default, before calling a helper,
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all globals are stored at their canonical location and it is assumed
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that the function can modify them. By default, the helper is allowed to
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modify the CPU state or raise an exception.
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This can be overridden using the following function modifiers:
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- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,
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either directly or via an exception. They will not be saved to their
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canonical locations before calling the helper.
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- TCG_CALL_NO_WRITE_GLOBALS means that the helper does not modify any globals.
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They will only be saved to their canonical location before calling helpers,
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but they won't be reloaded afterwards.
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- TCG_CALL_NO_SIDE_EFFECTS means that the call to the function is removed if
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the return value is not used.
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Note that TCG_CALL_NO_READ_GLOBALS implies TCG_CALL_NO_WRITE_GLOBALS.
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On some TCG targets (e.g. x86), several calling conventions are
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supported.
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* Branches:
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Use the instruction 'br' to jump to a label.
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3.3) Code Optimizations
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When generating instructions, you can count on at least the following
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optimizations:
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- Single instructions are simplified, e.g.
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and_i32 t0, t0, $0xffffffff
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is suppressed.
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- A liveness analysis is done at the basic block level. The
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information is used to suppress moves from a dead variable to
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another one. It is also used to remove instructions which compute
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dead results. The later is especially useful for condition code
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optimization in QEMU.
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In the following example:
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add_i32 t0, t1, t2
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add_i32 t0, t0, $1
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mov_i32 t0, $1
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only the last instruction is kept.
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3.4) Instruction Reference
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********* Function call
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* call <ret> <params> ptr
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call function 'ptr' (pointer type)
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<ret> optional 32 bit or 64 bit return value
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<params> optional 32 bit or 64 bit parameters
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********* Jumps/Labels
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* set_label $label
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Define label 'label' at the current program point.
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* br $label
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Jump to label.
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* brcond_i32/i64 t0, t1, cond, label
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Conditional jump if t0 cond t1 is true. cond can be:
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TCG_COND_EQ
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TCG_COND_NE
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TCG_COND_LT /* signed */
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TCG_COND_GE /* signed */
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TCG_COND_LE /* signed */
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TCG_COND_GT /* signed */
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TCG_COND_LTU /* unsigned */
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TCG_COND_GEU /* unsigned */
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TCG_COND_LEU /* unsigned */
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TCG_COND_GTU /* unsigned */
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********* Arithmetic
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* add_i32/i64 t0, t1, t2
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t0=t1+t2
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* sub_i32/i64 t0, t1, t2
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t0=t1-t2
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* neg_i32/i64 t0, t1
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t0=-t1 (two's complement)
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* mul_i32/i64 t0, t1, t2
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t0=t1*t2
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* div_i32/i64 t0, t1, t2
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t0=t1/t2 (signed). Undefined behavior if division by zero or overflow.
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* divu_i32/i64 t0, t1, t2
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t0=t1/t2 (unsigned). Undefined behavior if division by zero.
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* rem_i32/i64 t0, t1, t2
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t0=t1%t2 (signed). Undefined behavior if division by zero or overflow.
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* remu_i32/i64 t0, t1, t2
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t0=t1%t2 (unsigned). Undefined behavior if division by zero.
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********* Logical
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* and_i32/i64 t0, t1, t2
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t0=t1&t2
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* or_i32/i64 t0, t1, t2
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t0=t1|t2
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* xor_i32/i64 t0, t1, t2
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t0=t1^t2
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* not_i32/i64 t0, t1
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t0=~t1
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* andc_i32/i64 t0, t1, t2
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t0=t1&~t2
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* eqv_i32/i64 t0, t1, t2
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t0=~(t1^t2), or equivalently, t0=t1^~t2
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* nand_i32/i64 t0, t1, t2
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t0=~(t1&t2)
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* nor_i32/i64 t0, t1, t2
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t0=~(t1|t2)
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* orc_i32/i64 t0, t1, t2
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t0=t1|~t2
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* clz_i32/i64 t0, t1, t2
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t0 = t1 ? clz(t1) : t2
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* ctz_i32/i64 t0, t1, t2
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t0 = t1 ? ctz(t1) : t2
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* ctpop_i32/i64 t0, t1
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t0 = number of bits set in t1
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With "ctpop" short for "count population", matching
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the function name used in include/qemu/host-utils.h.
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********* Shifts/Rotates
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* shl_i32/i64 t0, t1, t2
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t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
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* shr_i32/i64 t0, t1, t2
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t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
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* sar_i32/i64 t0, t1, t2
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t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
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* rotl_i32/i64 t0, t1, t2
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Rotation of t2 bits to the left.
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Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
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* rotr_i32/i64 t0, t1, t2
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Rotation of t2 bits to the right.
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Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64)
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********* Misc
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* mov_i32/i64 t0, t1
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t0 = t1
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Move t1 to t0 (both operands must have the same type).
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* ext8s_i32/i64 t0, t1
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ext8u_i32/i64 t0, t1
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ext16s_i32/i64 t0, t1
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ext16u_i32/i64 t0, t1
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ext32s_i64 t0, t1
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ext32u_i64 t0, t1
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8, 16 or 32 bit sign/zero extension (both operands must have the same type)
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* bswap16_i32/i64 t0, t1, flags
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16 bit byte swap on the low bits of a 32/64 bit input.
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If flags & TCG_BSWAP_IZ, then t1 is known to be zero-extended from bit 15.
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If flags & TCG_BSWAP_OZ, then t0 will be zero-extended from bit 15.
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If flags & TCG_BSWAP_OS, then t0 will be sign-extended from bit 15.
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If neither TCG_BSWAP_OZ nor TCG_BSWAP_OS are set, then the bits of
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t0 above bit 15 may contain any value.
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* bswap32_i64 t0, t1, flags
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32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
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except they apply from bit 31 instead of bit 15.
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* bswap32_i32 t0, t1, flags
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* bswap64_i64 t0, t1, flags
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32/64 bit byte swap. The flags are ignored, but still present
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for consistency with the other bswap opcodes.
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* discard_i32/i64 t0
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Indicate that the value of t0 won't be used later. It is useful to
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force dead code elimination.
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* deposit_i32/i64 dest, t1, t2, pos, len
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Deposit T2 as a bitfield into T1, placing the result in DEST.
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The bitfield is described by POS/LEN, which are immediate values:
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LEN - the length of the bitfield
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POS - the position of the first bit, counting from the LSB
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For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
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at bit 8. This operation would be equivalent to
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dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
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* extract_i32/i64 dest, t1, pos, len
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* sextract_i32/i64 dest, t1, pos, len
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Extract a bitfield from T1, placing the result in DEST.
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The bitfield is described by POS/LEN, which are immediate values,
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as above for deposit. For extract_*, the result will be extended
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to the left with zeros; for sextract_*, the result will be extended
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to the left with copies of the bitfield sign bit at pos + len - 1.
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For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
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at bit 8. This operation would be equivalent to
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dest = (t1 << 20) >> 28
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(using an arithmetic right shift).
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* extract2_i32/i64 dest, t1, t2, pos
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For N = {32,64}, extract an N-bit quantity from the concatenation
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of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander
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accepts 0 <= pos <= N as inputs. The backend code generator will
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not see either 0 or N as inputs for these opcodes.
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* extrl_i64_i32 t0, t1
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For 64-bit hosts only, extract the low 32-bits of input T1 and place it
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into 32-bit output T0. Depending on the host, this may be a simple move,
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or may require additional canonicalization.
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* extrh_i64_i32 t0, t1
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For 64-bit hosts only, extract the high 32-bits of input T1 and place it
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into 32-bit output T0. Depending on the host, this may be a simple shift,
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or may require additional canonicalization.
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********* Conditional moves
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* setcond_i32/i64 dest, t1, t2, cond
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dest = (t1 cond t2)
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Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
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* movcond_i32/i64 dest, c1, c2, v1, v2, cond
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dest = (c1 cond c2 ? v1 : v2)
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Set DEST to V1 if (C1 cond C2) is true, otherwise set to V2.
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********* Type conversions
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* ext_i32_i64 t0, t1
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Convert t1 (32 bit) to t0 (64 bit) and does sign extension
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* extu_i32_i64 t0, t1
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Convert t1 (32 bit) to t0 (64 bit) and does zero extension
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* trunc_i64_i32 t0, t1
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Truncate t1 (64 bit) to t0 (32 bit)
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* concat_i32_i64 t0, t1, t2
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Construct t0 (64-bit) taking the low half from t1 (32 bit) and the high half
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from t2 (32 bit).
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* concat32_i64 t0, t1, t2
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Construct t0 (64-bit) taking the low half from t1 (64 bit) and the high half
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from t2 (64 bit).
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********* Load/Store
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* ld_i32/i64 t0, t1, offset
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ld8s_i32/i64 t0, t1, offset
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ld8u_i32/i64 t0, t1, offset
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ld16s_i32/i64 t0, t1, offset
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ld16u_i32/i64 t0, t1, offset
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ld32s_i64 t0, t1, offset
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ld32u_i64 t0, t1, offset
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t0 = read(t1 + offset)
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Load 8, 16, 32 or 64 bits with or without sign extension from host memory.
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offset must be a constant.
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* st_i32/i64 t0, t1, offset
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st8_i32/i64 t0, t1, offset
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st16_i32/i64 t0, t1, offset
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st32_i64 t0, t1, offset
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write(t0, t1 + offset)
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Write 8, 16, 32 or 64 bits to host memory.
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All this opcodes assume that the pointed host memory doesn't correspond
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to a global. In the latter case the behaviour is unpredictable.
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********* Multiword arithmetic support
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* add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
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* sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high
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Similar to add/sub, except that the double-word inputs T1 and T2 are
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formed from two single-word arguments, and the double-word output T0
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is returned in two single-word outputs.
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* mulu2_i32/i64 t0_low, t0_high, t1, t2
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Similar to mul, except two unsigned inputs T1 and T2 yielding the full
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double-word product T0. The later is returned in two single-word outputs.
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* muls2_i32/i64 t0_low, t0_high, t1, t2
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Similar to mulu2, except the two inputs T1 and T2 are signed.
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* mulsh_i32/i64 t0, t1, t2
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* muluh_i32/i64 t0, t1, t2
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Provide the high part of a signed or unsigned multiply, respectively.
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If mulu2/muls2 are not provided by the backend, the tcg-op generator
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can obtain the same results can be obtained by emitting a pair of
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opcodes, mul+muluh/mulsh.
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********* Memory Barrier support
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* mb <$arg>
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Generate a target memory barrier instruction to ensure memory ordering as being
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enforced by a corresponding guest memory barrier instruction. The ordering
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enforced by the backend may be stricter than the ordering required by the guest.
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It cannot be weaker. This opcode takes a constant argument which is required to
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generate the appropriate barrier instruction. The backend should take care to
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emit the target barrier instruction only when necessary i.e., for SMP guests and
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when MTTCG is enabled.
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The guest translators should generate this opcode for all guest instructions
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which have ordering side effects.
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Please see docs/devel/atomics.rst for more information on memory barriers.
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********* 64-bit guest on 32-bit host support
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The following opcodes are internal to TCG. Thus they are to be implemented by
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32-bit host code generators, but are not to be emitted by guest translators.
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They are emitted as needed by inline functions within "tcg-op.h".
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* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
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Similar to brcond, except that the 64-bit values T0 and T1
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are formed from two 32-bit arguments.
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* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
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Similar to setcond, except that the 64-bit values T1 and T2 are
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formed from two 32-bit arguments. The result is a 32-bit value.
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********* QEMU specific operations
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* exit_tb t0
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Exit the current TB and return the value t0 (word type).
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* goto_tb index
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Exit the current TB and jump to the TB index 'index' (constant) if the
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current TB was linked to this TB. Otherwise execute the next
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instructions. Only indices 0 and 1 are valid and tcg_gen_goto_tb may be issued
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at most once with each slot index per TB.
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* lookup_and_goto_ptr tb_addr
|
|
|
|
Look up a TB address ('tb_addr') and jump to it if valid. If not valid,
|
|
jump to the TCG epilogue to go back to the exec loop.
|
|
|
|
This operation is optional. If the TCG backend does not implement the
|
|
goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0).
|
|
|
|
* qemu_ld_i32/i64 t0, t1, flags, memidx
|
|
* qemu_st_i32/i64 t0, t1, flags, memidx
|
|
* qemu_st8_i32 t0, t1, flags, memidx
|
|
|
|
Load data at the guest address t1 into t0, or store data in t0 at guest
|
|
address t1. The _i32/_i64 size applies to the size of the input/output
|
|
register t0 only. The address t1 is always sized according to the guest,
|
|
and the width of the memory operation is controlled by flags.
|
|
|
|
Both t0 and t1 may be split into little-endian ordered pairs of registers
|
|
if dealing with 64-bit quantities on a 32-bit host.
|
|
|
|
The memidx selects the qemu tlb index to use (e.g. user or kernel access).
|
|
The flags are the MemOp bits, selecting the sign, width, and endianness
|
|
of the memory access.
|
|
|
|
For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
|
|
64-bit memory access specified in flags.
|
|
|
|
For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of
|
|
the memory operation is known to be 8-bit. This allows the backend to
|
|
provide a different set of register constraints.
|
|
|
|
********* Host vector operations
|
|
|
|
All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
|
|
The former specifies the length of the vector in log2 64-bit units; the
|
|
later specifies the length of the element (if applicable) in log2 8-bit units.
|
|
E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
|
|
|
|
* mov_vec v0, v1
|
|
* ld_vec v0, t1
|
|
* st_vec v0, t1
|
|
|
|
Move, load and store.
|
|
|
|
* dup_vec v0, r1
|
|
|
|
Duplicate the low N bits of R1 into VECL/VECE copies across V0.
|
|
|
|
* dupi_vec v0, c
|
|
|
|
Similarly, for a constant.
|
|
Smaller values will be replicated to host register size by the expanders.
|
|
|
|
* dup2_vec v0, r1, r2
|
|
|
|
Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
|
|
only present for 32-bit hosts.
|
|
|
|
* add_vec v0, v1, v2
|
|
|
|
v0 = v1 + v2, in elements across the vector.
|
|
|
|
* sub_vec v0, v1, v2
|
|
|
|
Similarly, v0 = v1 - v2.
|
|
|
|
* mul_vec v0, v1, v2
|
|
|
|
Similarly, v0 = v1 * v2.
|
|
|
|
* neg_vec v0, v1
|
|
|
|
Similarly, v0 = -v1.
|
|
|
|
* abs_vec v0, v1
|
|
|
|
Similarly, v0 = v1 < 0 ? -v1 : v1, in elements across the vector.
|
|
|
|
* smin_vec:
|
|
* umin_vec:
|
|
|
|
Similarly, v0 = MIN(v1, v2), for signed and unsigned element types.
|
|
|
|
* smax_vec:
|
|
* umax_vec:
|
|
|
|
Similarly, v0 = MAX(v1, v2), for signed and unsigned element types.
|
|
|
|
* ssadd_vec:
|
|
* sssub_vec:
|
|
* usadd_vec:
|
|
* ussub_vec:
|
|
|
|
Signed and unsigned saturating addition and subtraction. If the true
|
|
result is not representable within the element type, the element is
|
|
set to the minimum or maximum value for the type.
|
|
|
|
* and_vec v0, v1, v2
|
|
* or_vec v0, v1, v2
|
|
* xor_vec v0, v1, v2
|
|
* andc_vec v0, v1, v2
|
|
* orc_vec v0, v1, v2
|
|
* not_vec v0, v1
|
|
|
|
Similarly, logical operations with and without complement.
|
|
Note that VECE is unused.
|
|
|
|
* shli_vec v0, v1, i2
|
|
* shls_vec v0, v1, s2
|
|
|
|
Shift all elements from v1 by a scalar i2/s2. I.e.
|
|
|
|
for (i = 0; i < VECL/VECE; ++i) {
|
|
v0[i] = v1[i] << s2;
|
|
}
|
|
|
|
* shri_vec v0, v1, i2
|
|
* sari_vec v0, v1, i2
|
|
* rotli_vec v0, v1, i2
|
|
* shrs_vec v0, v1, s2
|
|
* sars_vec v0, v1, s2
|
|
|
|
Similarly for logical and arithmetic right shift, and left rotate.
|
|
|
|
* shlv_vec v0, v1, v2
|
|
|
|
Shift elements from v1 by elements from v2. I.e.
|
|
|
|
for (i = 0; i < VECL/VECE; ++i) {
|
|
v0[i] = v1[i] << v2[i];
|
|
}
|
|
|
|
* shrv_vec v0, v1, v2
|
|
* sarv_vec v0, v1, v2
|
|
* rotlv_vec v0, v1, v2
|
|
* rotrv_vec v0, v1, v2
|
|
|
|
Similarly for logical and arithmetic right shift, and rotates.
|
|
|
|
* cmp_vec v0, v1, v2, cond
|
|
|
|
Compare vectors by element, storing -1 for true and 0 for false.
|
|
|
|
* bitsel_vec v0, v1, v2, v3
|
|
|
|
Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
|
|
|
|
* cmpsel_vec v0, c1, c2, v3, v4, cond
|
|
|
|
Select elements based on comparison results:
|
|
for (i = 0; i < n; ++i) {
|
|
v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i].
|
|
}
|
|
|
|
*********
|
|
|
|
Note 1: Some shortcuts are defined when the last operand is known to be
|
|
a constant (e.g. addi for add, movi for mov).
|
|
|
|
Note 2: When using TCG, the opcodes must never be generated directly
|
|
as some of them may not be available as "real" opcodes. Always use the
|
|
function tcg_gen_xxx(args).
|
|
|
|
4) Backend
|
|
|
|
tcg-target.h contains the target specific definitions. tcg-target.c.inc
|
|
contains the target specific code; it is #included by tcg/tcg.c, rather
|
|
than being a standalone C file.
|
|
|
|
4.1) Assumptions
|
|
|
|
The target word size (TCG_TARGET_REG_BITS) is expected to be 32 bit or
|
|
64 bit. It is expected that the pointer has the same size as the word.
|
|
|
|
On a 32 bit target, all 64 bit operations are converted to 32 bits. A
|
|
few specific operations must be implemented to allow it (see add2_i32,
|
|
sub2_i32, brcond2_i32).
|
|
|
|
On a 64 bit target, the values are transferred between 32 and 64-bit
|
|
registers using the following ops:
|
|
- trunc_shr_i64_i32
|
|
- ext_i32_i64
|
|
- extu_i32_i64
|
|
|
|
They ensure that the values are correctly truncated or extended when
|
|
moved from a 32-bit to a 64-bit register or vice-versa. Note that the
|
|
trunc_shr_i64_i32 is an optional op. It is not necessary to implement
|
|
it if all the following conditions are met:
|
|
- 64-bit registers can hold 32-bit values
|
|
- 32-bit values in a 64-bit register do not need to stay zero or
|
|
sign extended
|
|
- all 32-bit TCG ops ignore the high part of 64-bit registers
|
|
|
|
Floating point operations are not supported in this version. A
|
|
previous incarnation of the code generator had full support of them,
|
|
but it is better to concentrate on integer operations first.
|
|
|
|
4.2) Constraints
|
|
|
|
GCC like constraints are used to define the constraints of every
|
|
instruction. Memory constraints are not supported in this
|
|
version. Aliases are specified in the input operands as for GCC.
|
|
|
|
The same register may be used for both an input and an output, even when
|
|
they are not explicitly aliased. If an op expands to multiple target
|
|
instructions then care must be taken to avoid clobbering input values.
|
|
GCC style "early clobber" outputs are supported, with '&'.
|
|
|
|
A target can define specific register or constant constraints. If an
|
|
operation uses a constant input constraint which does not allow all
|
|
constants, it must also accept registers in order to have a fallback.
|
|
The constraint 'i' is defined generically to accept any constant.
|
|
The constraint 'r' is not defined generically, but is consistently
|
|
used by each backend to indicate all registers.
|
|
|
|
The movi_i32 and movi_i64 operations must accept any constants.
|
|
|
|
The mov_i32 and mov_i64 operations must accept any registers of the
|
|
same type.
|
|
|
|
The ld/st/sti instructions must accept signed 32 bit constant offsets.
|
|
This can be implemented by reserving a specific register in which to
|
|
compute the address if the offset is too big.
|
|
|
|
The ld/st instructions must accept any destination (ld) or source (st)
|
|
register.
|
|
|
|
The sti instruction may fail if it cannot store the given constant.
|
|
|
|
4.3) Function call assumptions
|
|
|
|
- The only supported types for parameters and return value are: 32 and
|
|
64 bit integers and pointer.
|
|
- The stack grows downwards.
|
|
- The first N parameters are passed in registers.
|
|
- The next parameters are passed on the stack by storing them as words.
|
|
- Some registers are clobbered during the call.
|
|
- The function can return 0 or 1 value in registers. On a 32 bit
|
|
target, functions must be able to return 2 values in registers for
|
|
64 bit return type.
|
|
|
|
5) Recommended coding rules for best performance
|
|
|
|
- Use globals to represent the parts of the QEMU CPU state which are
|
|
often modified, e.g. the integer registers and the condition
|
|
codes. TCG will be able to use host registers to store them.
|
|
|
|
- Avoid globals stored in fixed registers. They must be used only to
|
|
store the pointer to the CPU state and possibly to store a pointer
|
|
to a register window.
|
|
|
|
- Use temporaries. Use local temporaries only when really needed,
|
|
e.g. when you need to use a value after a jump. Local temporaries
|
|
introduce a performance hit in the current TCG implementation: their
|
|
content is saved to memory at end of each basic block.
|
|
|
|
- Free temporaries and local temporaries when they are no longer used
|
|
(tcg_temp_free). Since tcg_const_x() also creates a temporary, you
|
|
should free it after it is used. Freeing temporaries does not yield
|
|
a better generated code, but it reduces the memory usage of TCG and
|
|
the speed of the translation.
|
|
|
|
- Don't hesitate to use helpers for complicated or seldom used guest
|
|
instructions. There is little performance advantage in using TCG to
|
|
implement guest instructions taking more than about twenty TCG
|
|
instructions. Note that this rule of thumb is more applicable to
|
|
helpers doing complex logic or arithmetic, where the C compiler has
|
|
scope to do a good job of optimisation; it is less relevant where
|
|
the instruction is mostly doing loads and stores, and in those cases
|
|
inline TCG may still be faster for longer sequences.
|
|
|
|
- The hard limit on the number of TCG instructions you can generate
|
|
per guest instruction is set by MAX_OP_PER_INSTR in exec-all.h --
|
|
you cannot exceed this without risking a buffer overrun.
|
|
|
|
- Use the 'discard' instruction if you know that TCG won't be able to
|
|
prove that a given global is "dead" at a given program point. The
|
|
x86 guest uses it to improve the condition codes optimisation.
|