14122 lines
478 KiB
Text
14122 lines
478 KiB
Text
|neorv32_test_setup_bootloader
|
|
clk_i => neorv32_top:neorv32_top_inst.clk_i
|
|
rstn_i => neorv32_top:neorv32_top_inst.rstn_i
|
|
gpio_o[0] << neorv32_top:neorv32_top_inst.gpio_o[0]
|
|
gpio_o[1] << neorv32_top:neorv32_top_inst.gpio_o[1]
|
|
gpio_o[2] << neorv32_top:neorv32_top_inst.gpio_o[2]
|
|
gpio_o[3] << neorv32_top:neorv32_top_inst.gpio_o[3]
|
|
gpio_o[4] << neorv32_top:neorv32_top_inst.gpio_o[4]
|
|
gpio_o[5] << neorv32_top:neorv32_top_inst.gpio_o[5]
|
|
gpio_o[6] << neorv32_top:neorv32_top_inst.gpio_o[6]
|
|
gpio_o[7] << neorv32_top:neorv32_top_inst.gpio_o[7]
|
|
uart0_txd_o << neorv32_top:neorv32_top_inst.uart0_txd_o
|
|
uart0_rxd_i => neorv32_top:neorv32_top_inst.uart0_rxd_i
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst
|
|
clk_i => neorv32_cpu:neorv32_cpu_inst.clk_i
|
|
clk_i => clk_div_ff[0].CLK
|
|
clk_i => clk_div_ff[1].CLK
|
|
clk_i => clk_div_ff[2].CLK
|
|
clk_i => clk_div_ff[5].CLK
|
|
clk_i => clk_div_ff[6].CLK
|
|
clk_i => clk_div_ff[9].CLK
|
|
clk_i => clk_div_ff[10].CLK
|
|
clk_i => clk_div_ff[11].CLK
|
|
clk_i => clk_div[0].CLK
|
|
clk_i => clk_div[1].CLK
|
|
clk_i => clk_div[2].CLK
|
|
clk_i => clk_div[3].CLK
|
|
clk_i => clk_div[4].CLK
|
|
clk_i => clk_div[5].CLK
|
|
clk_i => clk_div[6].CLK
|
|
clk_i => clk_div[7].CLK
|
|
clk_i => clk_div[8].CLK
|
|
clk_i => clk_div[9].CLK
|
|
clk_i => clk_div[10].CLK
|
|
clk_i => clk_div[11].CLK
|
|
clk_i => clk_gen_en_ff.CLK
|
|
clk_i => neorv32_busswitch:neorv32_busswitch_inst.clk_i
|
|
clk_i => neorv32_bus_keeper:neorv32_bus_keeper_inst.clk_i
|
|
clk_i => neorv32_imem:neorv32_int_imem_inst_true:neorv32_int_imem_inst.clk_i
|
|
clk_i => neorv32_dmem:neorv32_int_dmem_inst_true:neorv32_int_dmem_inst.clk_i
|
|
clk_i => neorv32_boot_rom:neorv32_boot_rom_inst_true:neorv32_boot_rom_inst.clk_i
|
|
clk_i => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.clk_i
|
|
clk_i => neorv32_mtime:neorv32_mtime_inst_true:neorv32_mtime_inst.clk_i
|
|
clk_i => neorv32_uart:neorv32_uart0_inst_true:neorv32_uart0_inst.clk_i
|
|
clk_i => neorv32_sysinfo:neorv32_sysinfo_inst.clk_i
|
|
clk_i => rstn_int.CLK
|
|
clk_i => rstn_int_sreg[0].CLK
|
|
clk_i => rstn_int_sreg[1].CLK
|
|
clk_i => rstn_int_sreg[2].CLK
|
|
clk_i => rstn_int_sreg[3].CLK
|
|
rstn_i => rstn_int.ACLR
|
|
rstn_i => rstn_int_sreg[0].ACLR
|
|
rstn_i => rstn_int_sreg[1].ACLR
|
|
rstn_i => rstn_int_sreg[2].ACLR
|
|
rstn_i => rstn_int_sreg[3].ACLR
|
|
jtag_trst_i => ~NO_FANOUT~
|
|
jtag_tck_i => ~NO_FANOUT~
|
|
jtag_tdi_i => jtag_tdo_o.DATAIN
|
|
jtag_tdo_o <= jtag_tdi_i.DB_MAX_OUTPUT_PORT_TYPE
|
|
jtag_tms_i => ~NO_FANOUT~
|
|
wb_tag_o[0] <= <GND>
|
|
wb_tag_o[1] <= <GND>
|
|
wb_tag_o[2] <= <GND>
|
|
wb_adr_o[0] <= <GND>
|
|
wb_adr_o[1] <= <GND>
|
|
wb_adr_o[2] <= <GND>
|
|
wb_adr_o[3] <= <GND>
|
|
wb_adr_o[4] <= <GND>
|
|
wb_adr_o[5] <= <GND>
|
|
wb_adr_o[6] <= <GND>
|
|
wb_adr_o[7] <= <GND>
|
|
wb_adr_o[8] <= <GND>
|
|
wb_adr_o[9] <= <GND>
|
|
wb_adr_o[10] <= <GND>
|
|
wb_adr_o[11] <= <GND>
|
|
wb_adr_o[12] <= <GND>
|
|
wb_adr_o[13] <= <GND>
|
|
wb_adr_o[14] <= <GND>
|
|
wb_adr_o[15] <= <GND>
|
|
wb_adr_o[16] <= <GND>
|
|
wb_adr_o[17] <= <GND>
|
|
wb_adr_o[18] <= <GND>
|
|
wb_adr_o[19] <= <GND>
|
|
wb_adr_o[20] <= <GND>
|
|
wb_adr_o[21] <= <GND>
|
|
wb_adr_o[22] <= <GND>
|
|
wb_adr_o[23] <= <GND>
|
|
wb_adr_o[24] <= <GND>
|
|
wb_adr_o[25] <= <GND>
|
|
wb_adr_o[26] <= <GND>
|
|
wb_adr_o[27] <= <GND>
|
|
wb_adr_o[28] <= <GND>
|
|
wb_adr_o[29] <= <GND>
|
|
wb_adr_o[30] <= <GND>
|
|
wb_adr_o[31] <= <GND>
|
|
wb_dat_i[0] => ~NO_FANOUT~
|
|
wb_dat_i[1] => ~NO_FANOUT~
|
|
wb_dat_i[2] => ~NO_FANOUT~
|
|
wb_dat_i[3] => ~NO_FANOUT~
|
|
wb_dat_i[4] => ~NO_FANOUT~
|
|
wb_dat_i[5] => ~NO_FANOUT~
|
|
wb_dat_i[6] => ~NO_FANOUT~
|
|
wb_dat_i[7] => ~NO_FANOUT~
|
|
wb_dat_i[8] => ~NO_FANOUT~
|
|
wb_dat_i[9] => ~NO_FANOUT~
|
|
wb_dat_i[10] => ~NO_FANOUT~
|
|
wb_dat_i[11] => ~NO_FANOUT~
|
|
wb_dat_i[12] => ~NO_FANOUT~
|
|
wb_dat_i[13] => ~NO_FANOUT~
|
|
wb_dat_i[14] => ~NO_FANOUT~
|
|
wb_dat_i[15] => ~NO_FANOUT~
|
|
wb_dat_i[16] => ~NO_FANOUT~
|
|
wb_dat_i[17] => ~NO_FANOUT~
|
|
wb_dat_i[18] => ~NO_FANOUT~
|
|
wb_dat_i[19] => ~NO_FANOUT~
|
|
wb_dat_i[20] => ~NO_FANOUT~
|
|
wb_dat_i[21] => ~NO_FANOUT~
|
|
wb_dat_i[22] => ~NO_FANOUT~
|
|
wb_dat_i[23] => ~NO_FANOUT~
|
|
wb_dat_i[24] => ~NO_FANOUT~
|
|
wb_dat_i[25] => ~NO_FANOUT~
|
|
wb_dat_i[26] => ~NO_FANOUT~
|
|
wb_dat_i[27] => ~NO_FANOUT~
|
|
wb_dat_i[28] => ~NO_FANOUT~
|
|
wb_dat_i[29] => ~NO_FANOUT~
|
|
wb_dat_i[30] => ~NO_FANOUT~
|
|
wb_dat_i[31] => ~NO_FANOUT~
|
|
wb_dat_o[0] <= <GND>
|
|
wb_dat_o[1] <= <GND>
|
|
wb_dat_o[2] <= <GND>
|
|
wb_dat_o[3] <= <GND>
|
|
wb_dat_o[4] <= <GND>
|
|
wb_dat_o[5] <= <GND>
|
|
wb_dat_o[6] <= <GND>
|
|
wb_dat_o[7] <= <GND>
|
|
wb_dat_o[8] <= <GND>
|
|
wb_dat_o[9] <= <GND>
|
|
wb_dat_o[10] <= <GND>
|
|
wb_dat_o[11] <= <GND>
|
|
wb_dat_o[12] <= <GND>
|
|
wb_dat_o[13] <= <GND>
|
|
wb_dat_o[14] <= <GND>
|
|
wb_dat_o[15] <= <GND>
|
|
wb_dat_o[16] <= <GND>
|
|
wb_dat_o[17] <= <GND>
|
|
wb_dat_o[18] <= <GND>
|
|
wb_dat_o[19] <= <GND>
|
|
wb_dat_o[20] <= <GND>
|
|
wb_dat_o[21] <= <GND>
|
|
wb_dat_o[22] <= <GND>
|
|
wb_dat_o[23] <= <GND>
|
|
wb_dat_o[24] <= <GND>
|
|
wb_dat_o[25] <= <GND>
|
|
wb_dat_o[26] <= <GND>
|
|
wb_dat_o[27] <= <GND>
|
|
wb_dat_o[28] <= <GND>
|
|
wb_dat_o[29] <= <GND>
|
|
wb_dat_o[30] <= <GND>
|
|
wb_dat_o[31] <= <GND>
|
|
wb_we_o <= <GND>
|
|
wb_sel_o[0] <= <GND>
|
|
wb_sel_o[1] <= <GND>
|
|
wb_sel_o[2] <= <GND>
|
|
wb_sel_o[3] <= <GND>
|
|
wb_stb_o <= <GND>
|
|
wb_cyc_o <= <GND>
|
|
wb_ack_i => ~NO_FANOUT~
|
|
wb_err_i => ~NO_FANOUT~
|
|
fence_o <= neorv32_cpu:neorv32_cpu_inst.d_bus_fence_o
|
|
fencei_o <= neorv32_cpu:neorv32_cpu_inst.i_bus_fence_o
|
|
xip_csn_o <= <VCC>
|
|
xip_clk_o <= <GND>
|
|
xip_sdi_i => ~NO_FANOUT~
|
|
xip_sdo_o <= <GND>
|
|
slink_tx_dat_o[7][0] <= <GND>
|
|
slink_tx_dat_o[7][1] <= <GND>
|
|
slink_tx_dat_o[7][2] <= <GND>
|
|
slink_tx_dat_o[7][3] <= <GND>
|
|
slink_tx_dat_o[7][4] <= <GND>
|
|
slink_tx_dat_o[7][5] <= <GND>
|
|
slink_tx_dat_o[7][6] <= <GND>
|
|
slink_tx_dat_o[7][7] <= <GND>
|
|
slink_tx_dat_o[7][8] <= <GND>
|
|
slink_tx_dat_o[7][9] <= <GND>
|
|
slink_tx_dat_o[7][10] <= <GND>
|
|
slink_tx_dat_o[7][11] <= <GND>
|
|
slink_tx_dat_o[7][12] <= <GND>
|
|
slink_tx_dat_o[7][13] <= <GND>
|
|
slink_tx_dat_o[7][14] <= <GND>
|
|
slink_tx_dat_o[7][15] <= <GND>
|
|
slink_tx_dat_o[7][16] <= <GND>
|
|
slink_tx_dat_o[7][17] <= <GND>
|
|
slink_tx_dat_o[7][18] <= <GND>
|
|
slink_tx_dat_o[7][19] <= <GND>
|
|
slink_tx_dat_o[7][20] <= <GND>
|
|
slink_tx_dat_o[7][21] <= <GND>
|
|
slink_tx_dat_o[7][22] <= <GND>
|
|
slink_tx_dat_o[7][23] <= <GND>
|
|
slink_tx_dat_o[7][24] <= <GND>
|
|
slink_tx_dat_o[7][25] <= <GND>
|
|
slink_tx_dat_o[7][26] <= <GND>
|
|
slink_tx_dat_o[7][27] <= <GND>
|
|
slink_tx_dat_o[7][28] <= <GND>
|
|
slink_tx_dat_o[7][29] <= <GND>
|
|
slink_tx_dat_o[7][30] <= <GND>
|
|
slink_tx_dat_o[7][31] <= <GND>
|
|
slink_tx_dat_o[6][0] <= <GND>
|
|
slink_tx_dat_o[6][1] <= <GND>
|
|
slink_tx_dat_o[6][2] <= <GND>
|
|
slink_tx_dat_o[6][3] <= <GND>
|
|
slink_tx_dat_o[6][4] <= <GND>
|
|
slink_tx_dat_o[6][5] <= <GND>
|
|
slink_tx_dat_o[6][6] <= <GND>
|
|
slink_tx_dat_o[6][7] <= <GND>
|
|
slink_tx_dat_o[6][8] <= <GND>
|
|
slink_tx_dat_o[6][9] <= <GND>
|
|
slink_tx_dat_o[6][10] <= <GND>
|
|
slink_tx_dat_o[6][11] <= <GND>
|
|
slink_tx_dat_o[6][12] <= <GND>
|
|
slink_tx_dat_o[6][13] <= <GND>
|
|
slink_tx_dat_o[6][14] <= <GND>
|
|
slink_tx_dat_o[6][15] <= <GND>
|
|
slink_tx_dat_o[6][16] <= <GND>
|
|
slink_tx_dat_o[6][17] <= <GND>
|
|
slink_tx_dat_o[6][18] <= <GND>
|
|
slink_tx_dat_o[6][19] <= <GND>
|
|
slink_tx_dat_o[6][20] <= <GND>
|
|
slink_tx_dat_o[6][21] <= <GND>
|
|
slink_tx_dat_o[6][22] <= <GND>
|
|
slink_tx_dat_o[6][23] <= <GND>
|
|
slink_tx_dat_o[6][24] <= <GND>
|
|
slink_tx_dat_o[6][25] <= <GND>
|
|
slink_tx_dat_o[6][26] <= <GND>
|
|
slink_tx_dat_o[6][27] <= <GND>
|
|
slink_tx_dat_o[6][28] <= <GND>
|
|
slink_tx_dat_o[6][29] <= <GND>
|
|
slink_tx_dat_o[6][30] <= <GND>
|
|
slink_tx_dat_o[6][31] <= <GND>
|
|
slink_tx_dat_o[5][0] <= <GND>
|
|
slink_tx_dat_o[5][1] <= <GND>
|
|
slink_tx_dat_o[5][2] <= <GND>
|
|
slink_tx_dat_o[5][3] <= <GND>
|
|
slink_tx_dat_o[5][4] <= <GND>
|
|
slink_tx_dat_o[5][5] <= <GND>
|
|
slink_tx_dat_o[5][6] <= <GND>
|
|
slink_tx_dat_o[5][7] <= <GND>
|
|
slink_tx_dat_o[5][8] <= <GND>
|
|
slink_tx_dat_o[5][9] <= <GND>
|
|
slink_tx_dat_o[5][10] <= <GND>
|
|
slink_tx_dat_o[5][11] <= <GND>
|
|
slink_tx_dat_o[5][12] <= <GND>
|
|
slink_tx_dat_o[5][13] <= <GND>
|
|
slink_tx_dat_o[5][14] <= <GND>
|
|
slink_tx_dat_o[5][15] <= <GND>
|
|
slink_tx_dat_o[5][16] <= <GND>
|
|
slink_tx_dat_o[5][17] <= <GND>
|
|
slink_tx_dat_o[5][18] <= <GND>
|
|
slink_tx_dat_o[5][19] <= <GND>
|
|
slink_tx_dat_o[5][20] <= <GND>
|
|
slink_tx_dat_o[5][21] <= <GND>
|
|
slink_tx_dat_o[5][22] <= <GND>
|
|
slink_tx_dat_o[5][23] <= <GND>
|
|
slink_tx_dat_o[5][24] <= <GND>
|
|
slink_tx_dat_o[5][25] <= <GND>
|
|
slink_tx_dat_o[5][26] <= <GND>
|
|
slink_tx_dat_o[5][27] <= <GND>
|
|
slink_tx_dat_o[5][28] <= <GND>
|
|
slink_tx_dat_o[5][29] <= <GND>
|
|
slink_tx_dat_o[5][30] <= <GND>
|
|
slink_tx_dat_o[5][31] <= <GND>
|
|
slink_tx_dat_o[4][0] <= <GND>
|
|
slink_tx_dat_o[4][1] <= <GND>
|
|
slink_tx_dat_o[4][2] <= <GND>
|
|
slink_tx_dat_o[4][3] <= <GND>
|
|
slink_tx_dat_o[4][4] <= <GND>
|
|
slink_tx_dat_o[4][5] <= <GND>
|
|
slink_tx_dat_o[4][6] <= <GND>
|
|
slink_tx_dat_o[4][7] <= <GND>
|
|
slink_tx_dat_o[4][8] <= <GND>
|
|
slink_tx_dat_o[4][9] <= <GND>
|
|
slink_tx_dat_o[4][10] <= <GND>
|
|
slink_tx_dat_o[4][11] <= <GND>
|
|
slink_tx_dat_o[4][12] <= <GND>
|
|
slink_tx_dat_o[4][13] <= <GND>
|
|
slink_tx_dat_o[4][14] <= <GND>
|
|
slink_tx_dat_o[4][15] <= <GND>
|
|
slink_tx_dat_o[4][16] <= <GND>
|
|
slink_tx_dat_o[4][17] <= <GND>
|
|
slink_tx_dat_o[4][18] <= <GND>
|
|
slink_tx_dat_o[4][19] <= <GND>
|
|
slink_tx_dat_o[4][20] <= <GND>
|
|
slink_tx_dat_o[4][21] <= <GND>
|
|
slink_tx_dat_o[4][22] <= <GND>
|
|
slink_tx_dat_o[4][23] <= <GND>
|
|
slink_tx_dat_o[4][24] <= <GND>
|
|
slink_tx_dat_o[4][25] <= <GND>
|
|
slink_tx_dat_o[4][26] <= <GND>
|
|
slink_tx_dat_o[4][27] <= <GND>
|
|
slink_tx_dat_o[4][28] <= <GND>
|
|
slink_tx_dat_o[4][29] <= <GND>
|
|
slink_tx_dat_o[4][30] <= <GND>
|
|
slink_tx_dat_o[4][31] <= <GND>
|
|
slink_tx_dat_o[3][0] <= <GND>
|
|
slink_tx_dat_o[3][1] <= <GND>
|
|
slink_tx_dat_o[3][2] <= <GND>
|
|
slink_tx_dat_o[3][3] <= <GND>
|
|
slink_tx_dat_o[3][4] <= <GND>
|
|
slink_tx_dat_o[3][5] <= <GND>
|
|
slink_tx_dat_o[3][6] <= <GND>
|
|
slink_tx_dat_o[3][7] <= <GND>
|
|
slink_tx_dat_o[3][8] <= <GND>
|
|
slink_tx_dat_o[3][9] <= <GND>
|
|
slink_tx_dat_o[3][10] <= <GND>
|
|
slink_tx_dat_o[3][11] <= <GND>
|
|
slink_tx_dat_o[3][12] <= <GND>
|
|
slink_tx_dat_o[3][13] <= <GND>
|
|
slink_tx_dat_o[3][14] <= <GND>
|
|
slink_tx_dat_o[3][15] <= <GND>
|
|
slink_tx_dat_o[3][16] <= <GND>
|
|
slink_tx_dat_o[3][17] <= <GND>
|
|
slink_tx_dat_o[3][18] <= <GND>
|
|
slink_tx_dat_o[3][19] <= <GND>
|
|
slink_tx_dat_o[3][20] <= <GND>
|
|
slink_tx_dat_o[3][21] <= <GND>
|
|
slink_tx_dat_o[3][22] <= <GND>
|
|
slink_tx_dat_o[3][23] <= <GND>
|
|
slink_tx_dat_o[3][24] <= <GND>
|
|
slink_tx_dat_o[3][25] <= <GND>
|
|
slink_tx_dat_o[3][26] <= <GND>
|
|
slink_tx_dat_o[3][27] <= <GND>
|
|
slink_tx_dat_o[3][28] <= <GND>
|
|
slink_tx_dat_o[3][29] <= <GND>
|
|
slink_tx_dat_o[3][30] <= <GND>
|
|
slink_tx_dat_o[3][31] <= <GND>
|
|
slink_tx_dat_o[2][0] <= <GND>
|
|
slink_tx_dat_o[2][1] <= <GND>
|
|
slink_tx_dat_o[2][2] <= <GND>
|
|
slink_tx_dat_o[2][3] <= <GND>
|
|
slink_tx_dat_o[2][4] <= <GND>
|
|
slink_tx_dat_o[2][5] <= <GND>
|
|
slink_tx_dat_o[2][6] <= <GND>
|
|
slink_tx_dat_o[2][7] <= <GND>
|
|
slink_tx_dat_o[2][8] <= <GND>
|
|
slink_tx_dat_o[2][9] <= <GND>
|
|
slink_tx_dat_o[2][10] <= <GND>
|
|
slink_tx_dat_o[2][11] <= <GND>
|
|
slink_tx_dat_o[2][12] <= <GND>
|
|
slink_tx_dat_o[2][13] <= <GND>
|
|
slink_tx_dat_o[2][14] <= <GND>
|
|
slink_tx_dat_o[2][15] <= <GND>
|
|
slink_tx_dat_o[2][16] <= <GND>
|
|
slink_tx_dat_o[2][17] <= <GND>
|
|
slink_tx_dat_o[2][18] <= <GND>
|
|
slink_tx_dat_o[2][19] <= <GND>
|
|
slink_tx_dat_o[2][20] <= <GND>
|
|
slink_tx_dat_o[2][21] <= <GND>
|
|
slink_tx_dat_o[2][22] <= <GND>
|
|
slink_tx_dat_o[2][23] <= <GND>
|
|
slink_tx_dat_o[2][24] <= <GND>
|
|
slink_tx_dat_o[2][25] <= <GND>
|
|
slink_tx_dat_o[2][26] <= <GND>
|
|
slink_tx_dat_o[2][27] <= <GND>
|
|
slink_tx_dat_o[2][28] <= <GND>
|
|
slink_tx_dat_o[2][29] <= <GND>
|
|
slink_tx_dat_o[2][30] <= <GND>
|
|
slink_tx_dat_o[2][31] <= <GND>
|
|
slink_tx_dat_o[1][0] <= <GND>
|
|
slink_tx_dat_o[1][1] <= <GND>
|
|
slink_tx_dat_o[1][2] <= <GND>
|
|
slink_tx_dat_o[1][3] <= <GND>
|
|
slink_tx_dat_o[1][4] <= <GND>
|
|
slink_tx_dat_o[1][5] <= <GND>
|
|
slink_tx_dat_o[1][6] <= <GND>
|
|
slink_tx_dat_o[1][7] <= <GND>
|
|
slink_tx_dat_o[1][8] <= <GND>
|
|
slink_tx_dat_o[1][9] <= <GND>
|
|
slink_tx_dat_o[1][10] <= <GND>
|
|
slink_tx_dat_o[1][11] <= <GND>
|
|
slink_tx_dat_o[1][12] <= <GND>
|
|
slink_tx_dat_o[1][13] <= <GND>
|
|
slink_tx_dat_o[1][14] <= <GND>
|
|
slink_tx_dat_o[1][15] <= <GND>
|
|
slink_tx_dat_o[1][16] <= <GND>
|
|
slink_tx_dat_o[1][17] <= <GND>
|
|
slink_tx_dat_o[1][18] <= <GND>
|
|
slink_tx_dat_o[1][19] <= <GND>
|
|
slink_tx_dat_o[1][20] <= <GND>
|
|
slink_tx_dat_o[1][21] <= <GND>
|
|
slink_tx_dat_o[1][22] <= <GND>
|
|
slink_tx_dat_o[1][23] <= <GND>
|
|
slink_tx_dat_o[1][24] <= <GND>
|
|
slink_tx_dat_o[1][25] <= <GND>
|
|
slink_tx_dat_o[1][26] <= <GND>
|
|
slink_tx_dat_o[1][27] <= <GND>
|
|
slink_tx_dat_o[1][28] <= <GND>
|
|
slink_tx_dat_o[1][29] <= <GND>
|
|
slink_tx_dat_o[1][30] <= <GND>
|
|
slink_tx_dat_o[1][31] <= <GND>
|
|
slink_tx_dat_o[0][0] <= <GND>
|
|
slink_tx_dat_o[0][1] <= <GND>
|
|
slink_tx_dat_o[0][2] <= <GND>
|
|
slink_tx_dat_o[0][3] <= <GND>
|
|
slink_tx_dat_o[0][4] <= <GND>
|
|
slink_tx_dat_o[0][5] <= <GND>
|
|
slink_tx_dat_o[0][6] <= <GND>
|
|
slink_tx_dat_o[0][7] <= <GND>
|
|
slink_tx_dat_o[0][8] <= <GND>
|
|
slink_tx_dat_o[0][9] <= <GND>
|
|
slink_tx_dat_o[0][10] <= <GND>
|
|
slink_tx_dat_o[0][11] <= <GND>
|
|
slink_tx_dat_o[0][12] <= <GND>
|
|
slink_tx_dat_o[0][13] <= <GND>
|
|
slink_tx_dat_o[0][14] <= <GND>
|
|
slink_tx_dat_o[0][15] <= <GND>
|
|
slink_tx_dat_o[0][16] <= <GND>
|
|
slink_tx_dat_o[0][17] <= <GND>
|
|
slink_tx_dat_o[0][18] <= <GND>
|
|
slink_tx_dat_o[0][19] <= <GND>
|
|
slink_tx_dat_o[0][20] <= <GND>
|
|
slink_tx_dat_o[0][21] <= <GND>
|
|
slink_tx_dat_o[0][22] <= <GND>
|
|
slink_tx_dat_o[0][23] <= <GND>
|
|
slink_tx_dat_o[0][24] <= <GND>
|
|
slink_tx_dat_o[0][25] <= <GND>
|
|
slink_tx_dat_o[0][26] <= <GND>
|
|
slink_tx_dat_o[0][27] <= <GND>
|
|
slink_tx_dat_o[0][28] <= <GND>
|
|
slink_tx_dat_o[0][29] <= <GND>
|
|
slink_tx_dat_o[0][30] <= <GND>
|
|
slink_tx_dat_o[0][31] <= <GND>
|
|
slink_tx_val_o[0] <= <GND>
|
|
slink_tx_val_o[1] <= <GND>
|
|
slink_tx_val_o[2] <= <GND>
|
|
slink_tx_val_o[3] <= <GND>
|
|
slink_tx_val_o[4] <= <GND>
|
|
slink_tx_val_o[5] <= <GND>
|
|
slink_tx_val_o[6] <= <GND>
|
|
slink_tx_val_o[7] <= <GND>
|
|
slink_tx_rdy_i[0] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[1] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[2] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[3] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[4] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[5] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[6] => ~NO_FANOUT~
|
|
slink_tx_rdy_i[7] => ~NO_FANOUT~
|
|
slink_tx_lst_o[0] <= <GND>
|
|
slink_tx_lst_o[1] <= <GND>
|
|
slink_tx_lst_o[2] <= <GND>
|
|
slink_tx_lst_o[3] <= <GND>
|
|
slink_tx_lst_o[4] <= <GND>
|
|
slink_tx_lst_o[5] <= <GND>
|
|
slink_tx_lst_o[6] <= <GND>
|
|
slink_tx_lst_o[7] <= <GND>
|
|
slink_rx_dat_i[7][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[7][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[6][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[5][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[4][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[3][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[2][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[1][31] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][0] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][1] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][2] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][3] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][4] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][5] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][6] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][7] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][8] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][9] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][10] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][11] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][12] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][13] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][14] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][15] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][16] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][17] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][18] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][19] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][20] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][21] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][22] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][23] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][24] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][25] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][26] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][27] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][28] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][29] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][30] => ~NO_FANOUT~
|
|
slink_rx_dat_i[0][31] => ~NO_FANOUT~
|
|
slink_rx_val_i[0] => ~NO_FANOUT~
|
|
slink_rx_val_i[1] => ~NO_FANOUT~
|
|
slink_rx_val_i[2] => ~NO_FANOUT~
|
|
slink_rx_val_i[3] => ~NO_FANOUT~
|
|
slink_rx_val_i[4] => ~NO_FANOUT~
|
|
slink_rx_val_i[5] => ~NO_FANOUT~
|
|
slink_rx_val_i[6] => ~NO_FANOUT~
|
|
slink_rx_val_i[7] => ~NO_FANOUT~
|
|
slink_rx_rdy_o[0] <= <GND>
|
|
slink_rx_rdy_o[1] <= <GND>
|
|
slink_rx_rdy_o[2] <= <GND>
|
|
slink_rx_rdy_o[3] <= <GND>
|
|
slink_rx_rdy_o[4] <= <GND>
|
|
slink_rx_rdy_o[5] <= <GND>
|
|
slink_rx_rdy_o[6] <= <GND>
|
|
slink_rx_rdy_o[7] <= <GND>
|
|
slink_rx_lst_i[0] => ~NO_FANOUT~
|
|
slink_rx_lst_i[1] => ~NO_FANOUT~
|
|
slink_rx_lst_i[2] => ~NO_FANOUT~
|
|
slink_rx_lst_i[3] => ~NO_FANOUT~
|
|
slink_rx_lst_i[4] => ~NO_FANOUT~
|
|
slink_rx_lst_i[5] => ~NO_FANOUT~
|
|
slink_rx_lst_i[6] => ~NO_FANOUT~
|
|
slink_rx_lst_i[7] => ~NO_FANOUT~
|
|
gpio_o[0] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[0]
|
|
gpio_o[1] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[1]
|
|
gpio_o[2] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[2]
|
|
gpio_o[3] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[3]
|
|
gpio_o[4] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[4]
|
|
gpio_o[5] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[5]
|
|
gpio_o[6] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[6]
|
|
gpio_o[7] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[7]
|
|
gpio_o[8] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[8]
|
|
gpio_o[9] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[9]
|
|
gpio_o[10] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[10]
|
|
gpio_o[11] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[11]
|
|
gpio_o[12] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[12]
|
|
gpio_o[13] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[13]
|
|
gpio_o[14] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[14]
|
|
gpio_o[15] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[15]
|
|
gpio_o[16] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[16]
|
|
gpio_o[17] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[17]
|
|
gpio_o[18] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[18]
|
|
gpio_o[19] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[19]
|
|
gpio_o[20] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[20]
|
|
gpio_o[21] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[21]
|
|
gpio_o[22] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[22]
|
|
gpio_o[23] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[23]
|
|
gpio_o[24] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[24]
|
|
gpio_o[25] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[25]
|
|
gpio_o[26] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[26]
|
|
gpio_o[27] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[27]
|
|
gpio_o[28] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[28]
|
|
gpio_o[29] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[29]
|
|
gpio_o[30] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[30]
|
|
gpio_o[31] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[31]
|
|
gpio_o[32] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[32]
|
|
gpio_o[33] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[33]
|
|
gpio_o[34] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[34]
|
|
gpio_o[35] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[35]
|
|
gpio_o[36] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[36]
|
|
gpio_o[37] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[37]
|
|
gpio_o[38] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[38]
|
|
gpio_o[39] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[39]
|
|
gpio_o[40] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[40]
|
|
gpio_o[41] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[41]
|
|
gpio_o[42] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[42]
|
|
gpio_o[43] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[43]
|
|
gpio_o[44] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[44]
|
|
gpio_o[45] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[45]
|
|
gpio_o[46] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[46]
|
|
gpio_o[47] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[47]
|
|
gpio_o[48] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[48]
|
|
gpio_o[49] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[49]
|
|
gpio_o[50] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[50]
|
|
gpio_o[51] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[51]
|
|
gpio_o[52] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[52]
|
|
gpio_o[53] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[53]
|
|
gpio_o[54] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[54]
|
|
gpio_o[55] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[55]
|
|
gpio_o[56] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[56]
|
|
gpio_o[57] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[57]
|
|
gpio_o[58] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[58]
|
|
gpio_o[59] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[59]
|
|
gpio_o[60] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[60]
|
|
gpio_o[61] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[61]
|
|
gpio_o[62] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[62]
|
|
gpio_o[63] <= neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_o[63]
|
|
gpio_i[0] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[0]
|
|
gpio_i[1] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[1]
|
|
gpio_i[2] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[2]
|
|
gpio_i[3] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[3]
|
|
gpio_i[4] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[4]
|
|
gpio_i[5] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[5]
|
|
gpio_i[6] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[6]
|
|
gpio_i[7] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[7]
|
|
gpio_i[8] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[8]
|
|
gpio_i[9] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[9]
|
|
gpio_i[10] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[10]
|
|
gpio_i[11] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[11]
|
|
gpio_i[12] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[12]
|
|
gpio_i[13] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[13]
|
|
gpio_i[14] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[14]
|
|
gpio_i[15] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[15]
|
|
gpio_i[16] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[16]
|
|
gpio_i[17] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[17]
|
|
gpio_i[18] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[18]
|
|
gpio_i[19] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[19]
|
|
gpio_i[20] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[20]
|
|
gpio_i[21] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[21]
|
|
gpio_i[22] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[22]
|
|
gpio_i[23] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[23]
|
|
gpio_i[24] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[24]
|
|
gpio_i[25] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[25]
|
|
gpio_i[26] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[26]
|
|
gpio_i[27] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[27]
|
|
gpio_i[28] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[28]
|
|
gpio_i[29] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[29]
|
|
gpio_i[30] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[30]
|
|
gpio_i[31] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[31]
|
|
gpio_i[32] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[32]
|
|
gpio_i[33] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[33]
|
|
gpio_i[34] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[34]
|
|
gpio_i[35] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[35]
|
|
gpio_i[36] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[36]
|
|
gpio_i[37] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[37]
|
|
gpio_i[38] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[38]
|
|
gpio_i[39] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[39]
|
|
gpio_i[40] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[40]
|
|
gpio_i[41] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[41]
|
|
gpio_i[42] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[42]
|
|
gpio_i[43] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[43]
|
|
gpio_i[44] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[44]
|
|
gpio_i[45] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[45]
|
|
gpio_i[46] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[46]
|
|
gpio_i[47] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[47]
|
|
gpio_i[48] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[48]
|
|
gpio_i[49] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[49]
|
|
gpio_i[50] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[50]
|
|
gpio_i[51] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[51]
|
|
gpio_i[52] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[52]
|
|
gpio_i[53] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[53]
|
|
gpio_i[54] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[54]
|
|
gpio_i[55] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[55]
|
|
gpio_i[56] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[56]
|
|
gpio_i[57] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[57]
|
|
gpio_i[58] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[58]
|
|
gpio_i[59] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[59]
|
|
gpio_i[60] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[60]
|
|
gpio_i[61] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[61]
|
|
gpio_i[62] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[62]
|
|
gpio_i[63] => neorv32_gpio:neorv32_gpio_inst_true:neorv32_gpio_inst.gpio_i[63]
|
|
uart0_txd_o <= neorv32_uart:neorv32_uart0_inst_true:neorv32_uart0_inst.uart_txd_o
|
|
uart0_rxd_i => neorv32_uart:neorv32_uart0_inst_true:neorv32_uart0_inst.uart_rxd_i
|
|
uart0_rts_o <= neorv32_uart:neorv32_uart0_inst_true:neorv32_uart0_inst.uart_rts_o
|
|
uart0_cts_i => neorv32_uart:neorv32_uart0_inst_true:neorv32_uart0_inst.uart_cts_i
|
|
uart1_txd_o <= <GND>
|
|
uart1_rxd_i => ~NO_FANOUT~
|
|
uart1_rts_o <= <GND>
|
|
uart1_cts_i => ~NO_FANOUT~
|
|
spi_sck_o <= <GND>
|
|
spi_sdo_o <= <GND>
|
|
spi_sdi_i => ~NO_FANOUT~
|
|
spi_csn_o[0] <= <VCC>
|
|
spi_csn_o[1] <= <VCC>
|
|
spi_csn_o[2] <= <VCC>
|
|
spi_csn_o[3] <= <VCC>
|
|
spi_csn_o[4] <= <VCC>
|
|
spi_csn_o[5] <= <VCC>
|
|
spi_csn_o[6] <= <VCC>
|
|
spi_csn_o[7] <= <VCC>
|
|
twi_sda_io <> twi_sda_io
|
|
twi_scl_io <> twi_scl_io
|
|
onewire_io <> onewire_io
|
|
pwm_o[0] <= <GND>
|
|
pwm_o[1] <= <GND>
|
|
pwm_o[2] <= <GND>
|
|
pwm_o[3] <= <GND>
|
|
pwm_o[4] <= <GND>
|
|
pwm_o[5] <= <GND>
|
|
pwm_o[6] <= <GND>
|
|
pwm_o[7] <= <GND>
|
|
pwm_o[8] <= <GND>
|
|
pwm_o[9] <= <GND>
|
|
pwm_o[10] <= <GND>
|
|
pwm_o[11] <= <GND>
|
|
pwm_o[12] <= <GND>
|
|
pwm_o[13] <= <GND>
|
|
pwm_o[14] <= <GND>
|
|
pwm_o[15] <= <GND>
|
|
pwm_o[16] <= <GND>
|
|
pwm_o[17] <= <GND>
|
|
pwm_o[18] <= <GND>
|
|
pwm_o[19] <= <GND>
|
|
pwm_o[20] <= <GND>
|
|
pwm_o[21] <= <GND>
|
|
pwm_o[22] <= <GND>
|
|
pwm_o[23] <= <GND>
|
|
pwm_o[24] <= <GND>
|
|
pwm_o[25] <= <GND>
|
|
pwm_o[26] <= <GND>
|
|
pwm_o[27] <= <GND>
|
|
pwm_o[28] <= <GND>
|
|
pwm_o[29] <= <GND>
|
|
pwm_o[30] <= <GND>
|
|
pwm_o[31] <= <GND>
|
|
pwm_o[32] <= <GND>
|
|
pwm_o[33] <= <GND>
|
|
pwm_o[34] <= <GND>
|
|
pwm_o[35] <= <GND>
|
|
pwm_o[36] <= <GND>
|
|
pwm_o[37] <= <GND>
|
|
pwm_o[38] <= <GND>
|
|
pwm_o[39] <= <GND>
|
|
pwm_o[40] <= <GND>
|
|
pwm_o[41] <= <GND>
|
|
pwm_o[42] <= <GND>
|
|
pwm_o[43] <= <GND>
|
|
pwm_o[44] <= <GND>
|
|
pwm_o[45] <= <GND>
|
|
pwm_o[46] <= <GND>
|
|
pwm_o[47] <= <GND>
|
|
pwm_o[48] <= <GND>
|
|
pwm_o[49] <= <GND>
|
|
pwm_o[50] <= <GND>
|
|
pwm_o[51] <= <GND>
|
|
pwm_o[52] <= <GND>
|
|
pwm_o[53] <= <GND>
|
|
pwm_o[54] <= <GND>
|
|
pwm_o[55] <= <GND>
|
|
pwm_o[56] <= <GND>
|
|
pwm_o[57] <= <GND>
|
|
pwm_o[58] <= <GND>
|
|
pwm_o[59] <= <GND>
|
|
cfs_in_i[0] => ~NO_FANOUT~
|
|
cfs_in_i[1] => ~NO_FANOUT~
|
|
cfs_in_i[2] => ~NO_FANOUT~
|
|
cfs_in_i[3] => ~NO_FANOUT~
|
|
cfs_in_i[4] => ~NO_FANOUT~
|
|
cfs_in_i[5] => ~NO_FANOUT~
|
|
cfs_in_i[6] => ~NO_FANOUT~
|
|
cfs_in_i[7] => ~NO_FANOUT~
|
|
cfs_in_i[8] => ~NO_FANOUT~
|
|
cfs_in_i[9] => ~NO_FANOUT~
|
|
cfs_in_i[10] => ~NO_FANOUT~
|
|
cfs_in_i[11] => ~NO_FANOUT~
|
|
cfs_in_i[12] => ~NO_FANOUT~
|
|
cfs_in_i[13] => ~NO_FANOUT~
|
|
cfs_in_i[14] => ~NO_FANOUT~
|
|
cfs_in_i[15] => ~NO_FANOUT~
|
|
cfs_in_i[16] => ~NO_FANOUT~
|
|
cfs_in_i[17] => ~NO_FANOUT~
|
|
cfs_in_i[18] => ~NO_FANOUT~
|
|
cfs_in_i[19] => ~NO_FANOUT~
|
|
cfs_in_i[20] => ~NO_FANOUT~
|
|
cfs_in_i[21] => ~NO_FANOUT~
|
|
cfs_in_i[22] => ~NO_FANOUT~
|
|
cfs_in_i[23] => ~NO_FANOUT~
|
|
cfs_in_i[24] => ~NO_FANOUT~
|
|
cfs_in_i[25] => ~NO_FANOUT~
|
|
cfs_in_i[26] => ~NO_FANOUT~
|
|
cfs_in_i[27] => ~NO_FANOUT~
|
|
cfs_in_i[28] => ~NO_FANOUT~
|
|
cfs_in_i[29] => ~NO_FANOUT~
|
|
cfs_in_i[30] => ~NO_FANOUT~
|
|
cfs_in_i[31] => ~NO_FANOUT~
|
|
cfs_out_o[0] <= <GND>
|
|
cfs_out_o[1] <= <GND>
|
|
cfs_out_o[2] <= <GND>
|
|
cfs_out_o[3] <= <GND>
|
|
cfs_out_o[4] <= <GND>
|
|
cfs_out_o[5] <= <GND>
|
|
cfs_out_o[6] <= <GND>
|
|
cfs_out_o[7] <= <GND>
|
|
cfs_out_o[8] <= <GND>
|
|
cfs_out_o[9] <= <GND>
|
|
cfs_out_o[10] <= <GND>
|
|
cfs_out_o[11] <= <GND>
|
|
cfs_out_o[12] <= <GND>
|
|
cfs_out_o[13] <= <GND>
|
|
cfs_out_o[14] <= <GND>
|
|
cfs_out_o[15] <= <GND>
|
|
cfs_out_o[16] <= <GND>
|
|
cfs_out_o[17] <= <GND>
|
|
cfs_out_o[18] <= <GND>
|
|
cfs_out_o[19] <= <GND>
|
|
cfs_out_o[20] <= <GND>
|
|
cfs_out_o[21] <= <GND>
|
|
cfs_out_o[22] <= <GND>
|
|
cfs_out_o[23] <= <GND>
|
|
cfs_out_o[24] <= <GND>
|
|
cfs_out_o[25] <= <GND>
|
|
cfs_out_o[26] <= <GND>
|
|
cfs_out_o[27] <= <GND>
|
|
cfs_out_o[28] <= <GND>
|
|
cfs_out_o[29] <= <GND>
|
|
cfs_out_o[30] <= <GND>
|
|
cfs_out_o[31] <= <GND>
|
|
neoled_o <= <GND>
|
|
xirq_i[0] => ~NO_FANOUT~
|
|
xirq_i[1] => ~NO_FANOUT~
|
|
xirq_i[2] => ~NO_FANOUT~
|
|
xirq_i[3] => ~NO_FANOUT~
|
|
xirq_i[4] => ~NO_FANOUT~
|
|
xirq_i[5] => ~NO_FANOUT~
|
|
xirq_i[6] => ~NO_FANOUT~
|
|
xirq_i[7] => ~NO_FANOUT~
|
|
xirq_i[8] => ~NO_FANOUT~
|
|
xirq_i[9] => ~NO_FANOUT~
|
|
xirq_i[10] => ~NO_FANOUT~
|
|
xirq_i[11] => ~NO_FANOUT~
|
|
xirq_i[12] => ~NO_FANOUT~
|
|
xirq_i[13] => ~NO_FANOUT~
|
|
xirq_i[14] => ~NO_FANOUT~
|
|
xirq_i[15] => ~NO_FANOUT~
|
|
xirq_i[16] => ~NO_FANOUT~
|
|
xirq_i[17] => ~NO_FANOUT~
|
|
xirq_i[18] => ~NO_FANOUT~
|
|
xirq_i[19] => ~NO_FANOUT~
|
|
xirq_i[20] => ~NO_FANOUT~
|
|
xirq_i[21] => ~NO_FANOUT~
|
|
xirq_i[22] => ~NO_FANOUT~
|
|
xirq_i[23] => ~NO_FANOUT~
|
|
xirq_i[24] => ~NO_FANOUT~
|
|
xirq_i[25] => ~NO_FANOUT~
|
|
xirq_i[26] => ~NO_FANOUT~
|
|
xirq_i[27] => ~NO_FANOUT~
|
|
xirq_i[28] => ~NO_FANOUT~
|
|
xirq_i[29] => ~NO_FANOUT~
|
|
xirq_i[30] => ~NO_FANOUT~
|
|
xirq_i[31] => ~NO_FANOUT~
|
|
mtime_irq_i => ~NO_FANOUT~
|
|
msw_irq_i => neorv32_cpu:neorv32_cpu_inst.msw_irq_i
|
|
mext_irq_i => neorv32_cpu:neorv32_cpu_inst.mext_irq_i
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst
|
|
clk_i => neorv32_cpu_control:neorv32_cpu_control_inst.clk_i
|
|
clk_i => neorv32_cpu_regfile:neorv32_cpu_regfile_inst.clk_i
|
|
clk_i => neorv32_cpu_alu:neorv32_cpu_alu_inst.clk_i
|
|
clk_i => neorv32_cpu_bus:neorv32_cpu_bus_inst.clk_i
|
|
rstn_i => neorv32_cpu_control:neorv32_cpu_control_inst.rstn_i
|
|
rstn_i => neorv32_cpu_alu:neorv32_cpu_alu_inst.rstn_i
|
|
rstn_i => neorv32_cpu_bus:neorv32_cpu_bus_inst.rstn_i
|
|
sleep_o <= neorv32_cpu_control:neorv32_cpu_control_inst.ctrl_o[66]
|
|
debug_o <= neorv32_cpu_control:neorv32_cpu_control_inst.ctrl_o[68]
|
|
i_bus_addr_o[0] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[0]
|
|
i_bus_addr_o[1] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[1]
|
|
i_bus_addr_o[2] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[2]
|
|
i_bus_addr_o[3] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[3]
|
|
i_bus_addr_o[4] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[4]
|
|
i_bus_addr_o[5] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[5]
|
|
i_bus_addr_o[6] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[6]
|
|
i_bus_addr_o[7] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[7]
|
|
i_bus_addr_o[8] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[8]
|
|
i_bus_addr_o[9] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[9]
|
|
i_bus_addr_o[10] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[10]
|
|
i_bus_addr_o[11] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[11]
|
|
i_bus_addr_o[12] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[12]
|
|
i_bus_addr_o[13] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[13]
|
|
i_bus_addr_o[14] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[14]
|
|
i_bus_addr_o[15] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[15]
|
|
i_bus_addr_o[16] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[16]
|
|
i_bus_addr_o[17] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[17]
|
|
i_bus_addr_o[18] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[18]
|
|
i_bus_addr_o[19] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[19]
|
|
i_bus_addr_o[20] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[20]
|
|
i_bus_addr_o[21] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[21]
|
|
i_bus_addr_o[22] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[22]
|
|
i_bus_addr_o[23] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[23]
|
|
i_bus_addr_o[24] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[24]
|
|
i_bus_addr_o[25] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[25]
|
|
i_bus_addr_o[26] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[26]
|
|
i_bus_addr_o[27] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[27]
|
|
i_bus_addr_o[28] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[28]
|
|
i_bus_addr_o[29] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[29]
|
|
i_bus_addr_o[30] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[30]
|
|
i_bus_addr_o[31] <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_addr_o[31]
|
|
i_bus_rdata_i[0] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[0]
|
|
i_bus_rdata_i[1] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[1]
|
|
i_bus_rdata_i[2] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[2]
|
|
i_bus_rdata_i[3] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[3]
|
|
i_bus_rdata_i[4] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[4]
|
|
i_bus_rdata_i[5] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[5]
|
|
i_bus_rdata_i[6] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[6]
|
|
i_bus_rdata_i[7] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[7]
|
|
i_bus_rdata_i[8] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[8]
|
|
i_bus_rdata_i[9] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[9]
|
|
i_bus_rdata_i[10] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[10]
|
|
i_bus_rdata_i[11] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[11]
|
|
i_bus_rdata_i[12] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[12]
|
|
i_bus_rdata_i[13] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[13]
|
|
i_bus_rdata_i[14] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[14]
|
|
i_bus_rdata_i[15] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[15]
|
|
i_bus_rdata_i[16] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[16]
|
|
i_bus_rdata_i[17] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[17]
|
|
i_bus_rdata_i[18] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[18]
|
|
i_bus_rdata_i[19] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[19]
|
|
i_bus_rdata_i[20] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[20]
|
|
i_bus_rdata_i[21] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[21]
|
|
i_bus_rdata_i[22] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[22]
|
|
i_bus_rdata_i[23] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[23]
|
|
i_bus_rdata_i[24] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[24]
|
|
i_bus_rdata_i[25] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[25]
|
|
i_bus_rdata_i[26] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[26]
|
|
i_bus_rdata_i[27] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[27]
|
|
i_bus_rdata_i[28] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[28]
|
|
i_bus_rdata_i[29] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[29]
|
|
i_bus_rdata_i[30] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[30]
|
|
i_bus_rdata_i[31] => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_rdata_i[31]
|
|
i_bus_re_o <= neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_re_o
|
|
i_bus_ack_i => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_ack_i
|
|
i_bus_err_i => neorv32_cpu_control:neorv32_cpu_control_inst.i_bus_err_i
|
|
i_bus_fence_o <= neorv32_cpu_control:neorv32_cpu_control_inst.ctrl_o[41]
|
|
i_bus_priv_o <= neorv32_cpu_control:neorv32_cpu_control_inst.ctrl_o[65]
|
|
d_bus_addr_o[0] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[0]
|
|
d_bus_addr_o[1] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[1]
|
|
d_bus_addr_o[2] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[2]
|
|
d_bus_addr_o[3] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[3]
|
|
d_bus_addr_o[4] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[4]
|
|
d_bus_addr_o[5] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[5]
|
|
d_bus_addr_o[6] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[6]
|
|
d_bus_addr_o[7] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[7]
|
|
d_bus_addr_o[8] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[8]
|
|
d_bus_addr_o[9] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[9]
|
|
d_bus_addr_o[10] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[10]
|
|
d_bus_addr_o[11] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[11]
|
|
d_bus_addr_o[12] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[12]
|
|
d_bus_addr_o[13] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[13]
|
|
d_bus_addr_o[14] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[14]
|
|
d_bus_addr_o[15] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[15]
|
|
d_bus_addr_o[16] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[16]
|
|
d_bus_addr_o[17] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[17]
|
|
d_bus_addr_o[18] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[18]
|
|
d_bus_addr_o[19] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[19]
|
|
d_bus_addr_o[20] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[20]
|
|
d_bus_addr_o[21] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[21]
|
|
d_bus_addr_o[22] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[22]
|
|
d_bus_addr_o[23] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[23]
|
|
d_bus_addr_o[24] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[24]
|
|
d_bus_addr_o[25] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[25]
|
|
d_bus_addr_o[26] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[26]
|
|
d_bus_addr_o[27] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[27]
|
|
d_bus_addr_o[28] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[28]
|
|
d_bus_addr_o[29] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[29]
|
|
d_bus_addr_o[30] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[30]
|
|
d_bus_addr_o[31] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_addr_o[31]
|
|
d_bus_rdata_i[0] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[0]
|
|
d_bus_rdata_i[1] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[1]
|
|
d_bus_rdata_i[2] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[2]
|
|
d_bus_rdata_i[3] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[3]
|
|
d_bus_rdata_i[4] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[4]
|
|
d_bus_rdata_i[5] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[5]
|
|
d_bus_rdata_i[6] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[6]
|
|
d_bus_rdata_i[7] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[7]
|
|
d_bus_rdata_i[8] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[8]
|
|
d_bus_rdata_i[9] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[9]
|
|
d_bus_rdata_i[10] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[10]
|
|
d_bus_rdata_i[11] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[11]
|
|
d_bus_rdata_i[12] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[12]
|
|
d_bus_rdata_i[13] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[13]
|
|
d_bus_rdata_i[14] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[14]
|
|
d_bus_rdata_i[15] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[15]
|
|
d_bus_rdata_i[16] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[16]
|
|
d_bus_rdata_i[17] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[17]
|
|
d_bus_rdata_i[18] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[18]
|
|
d_bus_rdata_i[19] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[19]
|
|
d_bus_rdata_i[20] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[20]
|
|
d_bus_rdata_i[21] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[21]
|
|
d_bus_rdata_i[22] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[22]
|
|
d_bus_rdata_i[23] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[23]
|
|
d_bus_rdata_i[24] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[24]
|
|
d_bus_rdata_i[25] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[25]
|
|
d_bus_rdata_i[26] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[26]
|
|
d_bus_rdata_i[27] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[27]
|
|
d_bus_rdata_i[28] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[28]
|
|
d_bus_rdata_i[29] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[29]
|
|
d_bus_rdata_i[30] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[30]
|
|
d_bus_rdata_i[31] => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_rdata_i[31]
|
|
d_bus_wdata_o[0] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[0]
|
|
d_bus_wdata_o[1] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[1]
|
|
d_bus_wdata_o[2] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[2]
|
|
d_bus_wdata_o[3] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[3]
|
|
d_bus_wdata_o[4] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[4]
|
|
d_bus_wdata_o[5] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[5]
|
|
d_bus_wdata_o[6] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[6]
|
|
d_bus_wdata_o[7] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[7]
|
|
d_bus_wdata_o[8] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[8]
|
|
d_bus_wdata_o[9] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[9]
|
|
d_bus_wdata_o[10] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[10]
|
|
d_bus_wdata_o[11] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[11]
|
|
d_bus_wdata_o[12] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[12]
|
|
d_bus_wdata_o[13] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[13]
|
|
d_bus_wdata_o[14] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[14]
|
|
d_bus_wdata_o[15] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[15]
|
|
d_bus_wdata_o[16] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[16]
|
|
d_bus_wdata_o[17] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[17]
|
|
d_bus_wdata_o[18] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[18]
|
|
d_bus_wdata_o[19] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[19]
|
|
d_bus_wdata_o[20] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[20]
|
|
d_bus_wdata_o[21] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[21]
|
|
d_bus_wdata_o[22] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[22]
|
|
d_bus_wdata_o[23] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[23]
|
|
d_bus_wdata_o[24] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[24]
|
|
d_bus_wdata_o[25] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[25]
|
|
d_bus_wdata_o[26] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[26]
|
|
d_bus_wdata_o[27] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[27]
|
|
d_bus_wdata_o[28] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[28]
|
|
d_bus_wdata_o[29] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[29]
|
|
d_bus_wdata_o[30] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[30]
|
|
d_bus_wdata_o[31] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_wdata_o[31]
|
|
d_bus_ben_o[0] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_ben_o[0]
|
|
d_bus_ben_o[1] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_ben_o[1]
|
|
d_bus_ben_o[2] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_ben_o[2]
|
|
d_bus_ben_o[3] <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_ben_o[3]
|
|
d_bus_we_o <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_we_o
|
|
d_bus_re_o <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_re_o
|
|
d_bus_ack_i => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_ack_i
|
|
d_bus_err_i => neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_err_i
|
|
d_bus_fence_o <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_fence_o
|
|
d_bus_priv_o <= neorv32_cpu_bus:neorv32_cpu_bus_inst.d_bus_priv_o
|
|
msw_irq_i => neorv32_cpu_control:neorv32_cpu_control_inst.msw_irq_i
|
|
mext_irq_i => neorv32_cpu_control:neorv32_cpu_control_inst.mext_irq_i
|
|
mtime_irq_i => neorv32_cpu_control:neorv32_cpu_control_inst.mtime_irq_i
|
|
firq_i[0] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[0]
|
|
firq_i[1] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[1]
|
|
firq_i[2] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[2]
|
|
firq_i[3] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[3]
|
|
firq_i[4] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[4]
|
|
firq_i[5] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[5]
|
|
firq_i[6] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[6]
|
|
firq_i[7] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[7]
|
|
firq_i[8] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[8]
|
|
firq_i[9] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[9]
|
|
firq_i[10] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[10]
|
|
firq_i[11] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[11]
|
|
firq_i[12] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[12]
|
|
firq_i[13] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[13]
|
|
firq_i[14] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[14]
|
|
firq_i[15] => neorv32_cpu_control:neorv32_cpu_control_inst.firq_i[15]
|
|
db_halt_req_i => neorv32_cpu_control:neorv32_cpu_control_inst.db_halt_req_i
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst
|
|
clk_i => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.clk_i
|
|
clk_i => csr.minstreth[0].CLK
|
|
clk_i => csr.minstreth[1].CLK
|
|
clk_i => csr.minstreth[2].CLK
|
|
clk_i => csr.minstreth[3].CLK
|
|
clk_i => csr.minstreth[4].CLK
|
|
clk_i => csr.minstreth[5].CLK
|
|
clk_i => csr.minstreth[6].CLK
|
|
clk_i => csr.minstreth[7].CLK
|
|
clk_i => csr.minstreth[8].CLK
|
|
clk_i => csr.minstreth[9].CLK
|
|
clk_i => csr.minstreth[10].CLK
|
|
clk_i => csr.minstreth[11].CLK
|
|
clk_i => csr.minstreth[12].CLK
|
|
clk_i => csr.minstreth[13].CLK
|
|
clk_i => csr.minstreth[14].CLK
|
|
clk_i => csr.minstreth[15].CLK
|
|
clk_i => csr.minstreth[16].CLK
|
|
clk_i => csr.minstreth[17].CLK
|
|
clk_i => csr.minstreth[18].CLK
|
|
clk_i => csr.minstreth[19].CLK
|
|
clk_i => csr.minstreth[20].CLK
|
|
clk_i => csr.minstreth[21].CLK
|
|
clk_i => csr.minstreth[22].CLK
|
|
clk_i => csr.minstreth[23].CLK
|
|
clk_i => csr.minstreth[24].CLK
|
|
clk_i => csr.minstreth[25].CLK
|
|
clk_i => csr.minstreth[26].CLK
|
|
clk_i => csr.minstreth[27].CLK
|
|
clk_i => csr.minstreth[28].CLK
|
|
clk_i => csr.minstreth[29].CLK
|
|
clk_i => csr.minstreth[30].CLK
|
|
clk_i => csr.minstreth[31].CLK
|
|
clk_i => csr.minstret_ovfl[0].CLK
|
|
clk_i => csr.minstret[0].CLK
|
|
clk_i => csr.minstret[1].CLK
|
|
clk_i => csr.minstret[2].CLK
|
|
clk_i => csr.minstret[3].CLK
|
|
clk_i => csr.minstret[4].CLK
|
|
clk_i => csr.minstret[5].CLK
|
|
clk_i => csr.minstret[6].CLK
|
|
clk_i => csr.minstret[7].CLK
|
|
clk_i => csr.minstret[8].CLK
|
|
clk_i => csr.minstret[9].CLK
|
|
clk_i => csr.minstret[10].CLK
|
|
clk_i => csr.minstret[11].CLK
|
|
clk_i => csr.minstret[12].CLK
|
|
clk_i => csr.minstret[13].CLK
|
|
clk_i => csr.minstret[14].CLK
|
|
clk_i => csr.minstret[15].CLK
|
|
clk_i => csr.minstret[16].CLK
|
|
clk_i => csr.minstret[17].CLK
|
|
clk_i => csr.minstret[18].CLK
|
|
clk_i => csr.minstret[19].CLK
|
|
clk_i => csr.minstret[20].CLK
|
|
clk_i => csr.minstret[21].CLK
|
|
clk_i => csr.minstret[22].CLK
|
|
clk_i => csr.minstret[23].CLK
|
|
clk_i => csr.minstret[24].CLK
|
|
clk_i => csr.minstret[25].CLK
|
|
clk_i => csr.minstret[26].CLK
|
|
clk_i => csr.minstret[27].CLK
|
|
clk_i => csr.minstret[28].CLK
|
|
clk_i => csr.minstret[29].CLK
|
|
clk_i => csr.minstret[30].CLK
|
|
clk_i => csr.minstret[31].CLK
|
|
clk_i => csr.mcycleh[0].CLK
|
|
clk_i => csr.mcycleh[1].CLK
|
|
clk_i => csr.mcycleh[2].CLK
|
|
clk_i => csr.mcycleh[3].CLK
|
|
clk_i => csr.mcycleh[4].CLK
|
|
clk_i => csr.mcycleh[5].CLK
|
|
clk_i => csr.mcycleh[6].CLK
|
|
clk_i => csr.mcycleh[7].CLK
|
|
clk_i => csr.mcycleh[8].CLK
|
|
clk_i => csr.mcycleh[9].CLK
|
|
clk_i => csr.mcycleh[10].CLK
|
|
clk_i => csr.mcycleh[11].CLK
|
|
clk_i => csr.mcycleh[12].CLK
|
|
clk_i => csr.mcycleh[13].CLK
|
|
clk_i => csr.mcycleh[14].CLK
|
|
clk_i => csr.mcycleh[15].CLK
|
|
clk_i => csr.mcycleh[16].CLK
|
|
clk_i => csr.mcycleh[17].CLK
|
|
clk_i => csr.mcycleh[18].CLK
|
|
clk_i => csr.mcycleh[19].CLK
|
|
clk_i => csr.mcycleh[20].CLK
|
|
clk_i => csr.mcycleh[21].CLK
|
|
clk_i => csr.mcycleh[22].CLK
|
|
clk_i => csr.mcycleh[23].CLK
|
|
clk_i => csr.mcycleh[24].CLK
|
|
clk_i => csr.mcycleh[25].CLK
|
|
clk_i => csr.mcycleh[26].CLK
|
|
clk_i => csr.mcycleh[27].CLK
|
|
clk_i => csr.mcycleh[28].CLK
|
|
clk_i => csr.mcycleh[29].CLK
|
|
clk_i => csr.mcycleh[30].CLK
|
|
clk_i => csr.mcycleh[31].CLK
|
|
clk_i => csr.mcycle_ovfl[0].CLK
|
|
clk_i => csr.mcycle[0].CLK
|
|
clk_i => csr.mcycle[1].CLK
|
|
clk_i => csr.mcycle[2].CLK
|
|
clk_i => csr.mcycle[3].CLK
|
|
clk_i => csr.mcycle[4].CLK
|
|
clk_i => csr.mcycle[5].CLK
|
|
clk_i => csr.mcycle[6].CLK
|
|
clk_i => csr.mcycle[7].CLK
|
|
clk_i => csr.mcycle[8].CLK
|
|
clk_i => csr.mcycle[9].CLK
|
|
clk_i => csr.mcycle[10].CLK
|
|
clk_i => csr.mcycle[11].CLK
|
|
clk_i => csr.mcycle[12].CLK
|
|
clk_i => csr.mcycle[13].CLK
|
|
clk_i => csr.mcycle[14].CLK
|
|
clk_i => csr.mcycle[15].CLK
|
|
clk_i => csr.mcycle[16].CLK
|
|
clk_i => csr.mcycle[17].CLK
|
|
clk_i => csr.mcycle[18].CLK
|
|
clk_i => csr.mcycle[19].CLK
|
|
clk_i => csr.mcycle[20].CLK
|
|
clk_i => csr.mcycle[21].CLK
|
|
clk_i => csr.mcycle[22].CLK
|
|
clk_i => csr.mcycle[23].CLK
|
|
clk_i => csr.mcycle[24].CLK
|
|
clk_i => csr.mcycle[25].CLK
|
|
clk_i => csr.mcycle[26].CLK
|
|
clk_i => csr.mcycle[27].CLK
|
|
clk_i => csr.mcycle[28].CLK
|
|
clk_i => csr.mcycle[29].CLK
|
|
clk_i => csr.mcycle[30].CLK
|
|
clk_i => csr.mcycle[31].CLK
|
|
clk_i => cnt_csr_we.instret[0].CLK
|
|
clk_i => cnt_csr_we.instret[1].CLK
|
|
clk_i => cnt_csr_we.cycle[0].CLK
|
|
clk_i => cnt_csr_we.cycle[1].CLK
|
|
clk_i => cnt_csr_we.wdata[0].CLK
|
|
clk_i => cnt_csr_we.wdata[1].CLK
|
|
clk_i => cnt_csr_we.wdata[2].CLK
|
|
clk_i => cnt_csr_we.wdata[3].CLK
|
|
clk_i => cnt_csr_we.wdata[4].CLK
|
|
clk_i => cnt_csr_we.wdata[5].CLK
|
|
clk_i => cnt_csr_we.wdata[6].CLK
|
|
clk_i => cnt_csr_we.wdata[7].CLK
|
|
clk_i => cnt_csr_we.wdata[8].CLK
|
|
clk_i => cnt_csr_we.wdata[9].CLK
|
|
clk_i => cnt_csr_we.wdata[10].CLK
|
|
clk_i => cnt_csr_we.wdata[11].CLK
|
|
clk_i => cnt_csr_we.wdata[12].CLK
|
|
clk_i => cnt_csr_we.wdata[13].CLK
|
|
clk_i => cnt_csr_we.wdata[14].CLK
|
|
clk_i => cnt_csr_we.wdata[15].CLK
|
|
clk_i => cnt_csr_we.wdata[16].CLK
|
|
clk_i => cnt_csr_we.wdata[17].CLK
|
|
clk_i => cnt_csr_we.wdata[18].CLK
|
|
clk_i => cnt_csr_we.wdata[19].CLK
|
|
clk_i => cnt_csr_we.wdata[20].CLK
|
|
clk_i => cnt_csr_we.wdata[21].CLK
|
|
clk_i => cnt_csr_we.wdata[22].CLK
|
|
clk_i => cnt_csr_we.wdata[23].CLK
|
|
clk_i => cnt_csr_we.wdata[24].CLK
|
|
clk_i => cnt_csr_we.wdata[25].CLK
|
|
clk_i => cnt_csr_we.wdata[26].CLK
|
|
clk_i => cnt_csr_we.wdata[27].CLK
|
|
clk_i => cnt_csr_we.wdata[28].CLK
|
|
clk_i => cnt_csr_we.wdata[29].CLK
|
|
clk_i => cnt_csr_we.wdata[30].CLK
|
|
clk_i => cnt_csr_we.wdata[31].CLK
|
|
clk_i => csr.rdata[0].CLK
|
|
clk_i => csr.rdata[1].CLK
|
|
clk_i => csr.rdata[2].CLK
|
|
clk_i => csr.rdata[3].CLK
|
|
clk_i => csr.rdata[4].CLK
|
|
clk_i => csr.rdata[5].CLK
|
|
clk_i => csr.rdata[6].CLK
|
|
clk_i => csr.rdata[7].CLK
|
|
clk_i => csr.rdata[8].CLK
|
|
clk_i => csr.rdata[9].CLK
|
|
clk_i => csr.rdata[10].CLK
|
|
clk_i => csr.rdata[11].CLK
|
|
clk_i => csr.rdata[12].CLK
|
|
clk_i => csr.rdata[13].CLK
|
|
clk_i => csr.rdata[14].CLK
|
|
clk_i => csr.rdata[15].CLK
|
|
clk_i => csr.rdata[16].CLK
|
|
clk_i => csr.rdata[17].CLK
|
|
clk_i => csr.rdata[18].CLK
|
|
clk_i => csr.rdata[19].CLK
|
|
clk_i => csr.rdata[20].CLK
|
|
clk_i => csr.rdata[21].CLK
|
|
clk_i => csr.rdata[22].CLK
|
|
clk_i => csr.rdata[23].CLK
|
|
clk_i => csr.rdata[24].CLK
|
|
clk_i => csr.rdata[25].CLK
|
|
clk_i => csr.rdata[26].CLK
|
|
clk_i => csr.rdata[27].CLK
|
|
clk_i => csr.rdata[28].CLK
|
|
clk_i => csr.rdata[29].CLK
|
|
clk_i => csr.rdata[30].CLK
|
|
clk_i => csr.rdata[31].CLK
|
|
clk_i => csr.re.CLK
|
|
clk_i => csr.dcsr_step.CLK
|
|
clk_i => csr.frm[0].CLK
|
|
clk_i => csr.frm[1].CLK
|
|
clk_i => csr.frm[2].CLK
|
|
clk_i => csr.mscratch[0].CLK
|
|
clk_i => csr.mscratch[1].CLK
|
|
clk_i => csr.mscratch[2].CLK
|
|
clk_i => csr.mscratch[3].CLK
|
|
clk_i => csr.mscratch[4].CLK
|
|
clk_i => csr.mscratch[5].CLK
|
|
clk_i => csr.mscratch[6].CLK
|
|
clk_i => csr.mscratch[7].CLK
|
|
clk_i => csr.mscratch[8].CLK
|
|
clk_i => csr.mscratch[9].CLK
|
|
clk_i => csr.mscratch[10].CLK
|
|
clk_i => csr.mscratch[11].CLK
|
|
clk_i => csr.mscratch[12].CLK
|
|
clk_i => csr.mscratch[13].CLK
|
|
clk_i => csr.mscratch[14].CLK
|
|
clk_i => csr.mscratch[15].CLK
|
|
clk_i => csr.mscratch[16].CLK
|
|
clk_i => csr.mscratch[17].CLK
|
|
clk_i => csr.mscratch[18].CLK
|
|
clk_i => csr.mscratch[19].CLK
|
|
clk_i => csr.mscratch[20].CLK
|
|
clk_i => csr.mscratch[21].CLK
|
|
clk_i => csr.mscratch[22].CLK
|
|
clk_i => csr.mscratch[23].CLK
|
|
clk_i => csr.mscratch[24].CLK
|
|
clk_i => csr.mscratch[25].CLK
|
|
clk_i => csr.mscratch[26].CLK
|
|
clk_i => csr.mscratch[27].CLK
|
|
clk_i => csr.mscratch[28].CLK
|
|
clk_i => csr.mscratch[29].CLK
|
|
clk_i => csr.mscratch[30].CLK
|
|
clk_i => csr.mscratch[31].CLK
|
|
clk_i => csr.mtval[0].CLK
|
|
clk_i => csr.mtval[1].CLK
|
|
clk_i => csr.mtval[2].CLK
|
|
clk_i => csr.mtval[3].CLK
|
|
clk_i => csr.mtval[4].CLK
|
|
clk_i => csr.mtval[5].CLK
|
|
clk_i => csr.mtval[6].CLK
|
|
clk_i => csr.mtval[7].CLK
|
|
clk_i => csr.mtval[8].CLK
|
|
clk_i => csr.mtval[9].CLK
|
|
clk_i => csr.mtval[10].CLK
|
|
clk_i => csr.mtval[11].CLK
|
|
clk_i => csr.mtval[12].CLK
|
|
clk_i => csr.mtval[13].CLK
|
|
clk_i => csr.mtval[14].CLK
|
|
clk_i => csr.mtval[15].CLK
|
|
clk_i => csr.mtval[16].CLK
|
|
clk_i => csr.mtval[17].CLK
|
|
clk_i => csr.mtval[18].CLK
|
|
clk_i => csr.mtval[19].CLK
|
|
clk_i => csr.mtval[20].CLK
|
|
clk_i => csr.mtval[21].CLK
|
|
clk_i => csr.mtval[22].CLK
|
|
clk_i => csr.mtval[23].CLK
|
|
clk_i => csr.mtval[24].CLK
|
|
clk_i => csr.mtval[25].CLK
|
|
clk_i => csr.mtval[26].CLK
|
|
clk_i => csr.mtval[27].CLK
|
|
clk_i => csr.mtval[28].CLK
|
|
clk_i => csr.mtval[29].CLK
|
|
clk_i => csr.mtval[30].CLK
|
|
clk_i => csr.mtval[31].CLK
|
|
clk_i => csr.mtvec[2].CLK
|
|
clk_i => csr.mtvec[3].CLK
|
|
clk_i => csr.mtvec[4].CLK
|
|
clk_i => csr.mtvec[5].CLK
|
|
clk_i => csr.mtvec[6].CLK
|
|
clk_i => csr.mtvec[7].CLK
|
|
clk_i => csr.mtvec[8].CLK
|
|
clk_i => csr.mtvec[9].CLK
|
|
clk_i => csr.mtvec[10].CLK
|
|
clk_i => csr.mtvec[11].CLK
|
|
clk_i => csr.mtvec[12].CLK
|
|
clk_i => csr.mtvec[13].CLK
|
|
clk_i => csr.mtvec[14].CLK
|
|
clk_i => csr.mtvec[15].CLK
|
|
clk_i => csr.mtvec[16].CLK
|
|
clk_i => csr.mtvec[17].CLK
|
|
clk_i => csr.mtvec[18].CLK
|
|
clk_i => csr.mtvec[19].CLK
|
|
clk_i => csr.mtvec[20].CLK
|
|
clk_i => csr.mtvec[21].CLK
|
|
clk_i => csr.mtvec[22].CLK
|
|
clk_i => csr.mtvec[23].CLK
|
|
clk_i => csr.mtvec[24].CLK
|
|
clk_i => csr.mtvec[25].CLK
|
|
clk_i => csr.mtvec[26].CLK
|
|
clk_i => csr.mtvec[27].CLK
|
|
clk_i => csr.mtvec[28].CLK
|
|
clk_i => csr.mtvec[29].CLK
|
|
clk_i => csr.mtvec[30].CLK
|
|
clk_i => csr.mtvec[31].CLK
|
|
clk_i => csr.mcause[0].CLK
|
|
clk_i => csr.mcause[1].CLK
|
|
clk_i => csr.mcause[2].CLK
|
|
clk_i => csr.mcause[3].CLK
|
|
clk_i => csr.mcause[4].CLK
|
|
clk_i => csr.mcause[5].CLK
|
|
clk_i => csr.mepc[1].CLK
|
|
clk_i => csr.mepc[2].CLK
|
|
clk_i => csr.mepc[3].CLK
|
|
clk_i => csr.mepc[4].CLK
|
|
clk_i => csr.mepc[5].CLK
|
|
clk_i => csr.mepc[6].CLK
|
|
clk_i => csr.mepc[7].CLK
|
|
clk_i => csr.mepc[8].CLK
|
|
clk_i => csr.mepc[9].CLK
|
|
clk_i => csr.mepc[10].CLK
|
|
clk_i => csr.mepc[11].CLK
|
|
clk_i => csr.mepc[12].CLK
|
|
clk_i => csr.mepc[13].CLK
|
|
clk_i => csr.mepc[14].CLK
|
|
clk_i => csr.mepc[15].CLK
|
|
clk_i => csr.mepc[16].CLK
|
|
clk_i => csr.mepc[17].CLK
|
|
clk_i => csr.mepc[18].CLK
|
|
clk_i => csr.mepc[19].CLK
|
|
clk_i => csr.mepc[20].CLK
|
|
clk_i => csr.mepc[21].CLK
|
|
clk_i => csr.mepc[22].CLK
|
|
clk_i => csr.mepc[23].CLK
|
|
clk_i => csr.mepc[24].CLK
|
|
clk_i => csr.mepc[25].CLK
|
|
clk_i => csr.mepc[26].CLK
|
|
clk_i => csr.mepc[27].CLK
|
|
clk_i => csr.mepc[28].CLK
|
|
clk_i => csr.mepc[29].CLK
|
|
clk_i => csr.mepc[30].CLK
|
|
clk_i => csr.mepc[31].CLK
|
|
clk_i => csr.privilege.CLK
|
|
clk_i => csr.mcountinhibit_ir.CLK
|
|
clk_i => csr.mcountinhibit_cy.CLK
|
|
clk_i => csr.mip_firq_nclr[0].CLK
|
|
clk_i => csr.mip_firq_nclr[1].CLK
|
|
clk_i => csr.mip_firq_nclr[2].CLK
|
|
clk_i => csr.mip_firq_nclr[3].CLK
|
|
clk_i => csr.mip_firq_nclr[4].CLK
|
|
clk_i => csr.mip_firq_nclr[5].CLK
|
|
clk_i => csr.mip_firq_nclr[6].CLK
|
|
clk_i => csr.mip_firq_nclr[7].CLK
|
|
clk_i => csr.mip_firq_nclr[8].CLK
|
|
clk_i => csr.mip_firq_nclr[9].CLK
|
|
clk_i => csr.mip_firq_nclr[10].CLK
|
|
clk_i => csr.mip_firq_nclr[11].CLK
|
|
clk_i => csr.mip_firq_nclr[12].CLK
|
|
clk_i => csr.mip_firq_nclr[13].CLK
|
|
clk_i => csr.mip_firq_nclr[14].CLK
|
|
clk_i => csr.mip_firq_nclr[15].CLK
|
|
clk_i => csr.mie_firq[0].CLK
|
|
clk_i => csr.mie_firq[1].CLK
|
|
clk_i => csr.mie_firq[2].CLK
|
|
clk_i => csr.mie_firq[3].CLK
|
|
clk_i => csr.mie_firq[4].CLK
|
|
clk_i => csr.mie_firq[5].CLK
|
|
clk_i => csr.mie_firq[6].CLK
|
|
clk_i => csr.mie_firq[7].CLK
|
|
clk_i => csr.mie_firq[8].CLK
|
|
clk_i => csr.mie_firq[9].CLK
|
|
clk_i => csr.mie_firq[10].CLK
|
|
clk_i => csr.mie_firq[11].CLK
|
|
clk_i => csr.mie_firq[12].CLK
|
|
clk_i => csr.mie_firq[13].CLK
|
|
clk_i => csr.mie_firq[14].CLK
|
|
clk_i => csr.mie_firq[15].CLK
|
|
clk_i => csr.mie_mti.CLK
|
|
clk_i => csr.mie_mei.CLK
|
|
clk_i => csr.mie_msi.CLK
|
|
clk_i => csr.mstatus_tw.CLK
|
|
clk_i => csr.mstatus_mprv.CLK
|
|
clk_i => csr.mstatus_mpp.CLK
|
|
clk_i => csr.mstatus_mpie.CLK
|
|
clk_i => csr.mstatus_mie.CLK
|
|
clk_i => csr.we.CLK
|
|
clk_i => trap_ctrl.cause[0].CLK
|
|
clk_i => trap_ctrl.cause[1].CLK
|
|
clk_i => trap_ctrl.cause[2].CLK
|
|
clk_i => trap_ctrl.cause[3].CLK
|
|
clk_i => trap_ctrl.cause[4].CLK
|
|
clk_i => trap_ctrl.cause[5].CLK
|
|
clk_i => trap_ctrl.cause[6].CLK
|
|
clk_i => trap_ctrl.env_start.CLK
|
|
clk_i => trap_ctrl.irq_buf[0].CLK
|
|
clk_i => trap_ctrl.irq_buf[1].CLK
|
|
clk_i => trap_ctrl.irq_buf[2].CLK
|
|
clk_i => trap_ctrl.irq_buf[3].CLK
|
|
clk_i => trap_ctrl.irq_buf[4].CLK
|
|
clk_i => trap_ctrl.irq_buf[5].CLK
|
|
clk_i => trap_ctrl.irq_buf[6].CLK
|
|
clk_i => trap_ctrl.irq_buf[7].CLK
|
|
clk_i => trap_ctrl.irq_buf[8].CLK
|
|
clk_i => trap_ctrl.irq_buf[9].CLK
|
|
clk_i => trap_ctrl.irq_buf[10].CLK
|
|
clk_i => trap_ctrl.irq_buf[11].CLK
|
|
clk_i => trap_ctrl.irq_buf[12].CLK
|
|
clk_i => trap_ctrl.irq_buf[13].CLK
|
|
clk_i => trap_ctrl.irq_buf[14].CLK
|
|
clk_i => trap_ctrl.irq_buf[15].CLK
|
|
clk_i => trap_ctrl.irq_buf[16].CLK
|
|
clk_i => trap_ctrl.irq_buf[17].CLK
|
|
clk_i => trap_ctrl.irq_buf[18].CLK
|
|
clk_i => trap_ctrl.irq_buf[19].CLK
|
|
clk_i => trap_ctrl.irq_buf[20].CLK
|
|
clk_i => trap_ctrl.irq_pnd[0].CLK
|
|
clk_i => trap_ctrl.irq_pnd[1].CLK
|
|
clk_i => trap_ctrl.irq_pnd[2].CLK
|
|
clk_i => trap_ctrl.irq_pnd[3].CLK
|
|
clk_i => trap_ctrl.irq_pnd[4].CLK
|
|
clk_i => trap_ctrl.irq_pnd[5].CLK
|
|
clk_i => trap_ctrl.irq_pnd[6].CLK
|
|
clk_i => trap_ctrl.irq_pnd[7].CLK
|
|
clk_i => trap_ctrl.irq_pnd[8].CLK
|
|
clk_i => trap_ctrl.irq_pnd[9].CLK
|
|
clk_i => trap_ctrl.irq_pnd[10].CLK
|
|
clk_i => trap_ctrl.irq_pnd[11].CLK
|
|
clk_i => trap_ctrl.irq_pnd[12].CLK
|
|
clk_i => trap_ctrl.irq_pnd[13].CLK
|
|
clk_i => trap_ctrl.irq_pnd[14].CLK
|
|
clk_i => trap_ctrl.irq_pnd[15].CLK
|
|
clk_i => trap_ctrl.irq_pnd[16].CLK
|
|
clk_i => trap_ctrl.irq_pnd[17].CLK
|
|
clk_i => trap_ctrl.irq_pnd[18].CLK
|
|
clk_i => trap_ctrl.exc_buf[0].CLK
|
|
clk_i => trap_ctrl.exc_buf[1].CLK
|
|
clk_i => trap_ctrl.exc_buf[2].CLK
|
|
clk_i => trap_ctrl.exc_buf[3].CLK
|
|
clk_i => trap_ctrl.exc_buf[4].CLK
|
|
clk_i => trap_ctrl.exc_buf[5].CLK
|
|
clk_i => trap_ctrl.exc_buf[6].CLK
|
|
clk_i => trap_ctrl.exc_buf[7].CLK
|
|
clk_i => trap_ctrl.exc_buf[8].CLK
|
|
clk_i => trap_ctrl.exc_buf[9].CLK
|
|
clk_i => trap_ctrl.exc_buf[10].CLK
|
|
clk_i => trap_ctrl.exc_buf[11].CLK
|
|
clk_i => ctrl[0].CLK
|
|
clk_i => ctrl[21].CLK
|
|
clk_i => ctrl[22].CLK
|
|
clk_i => ctrl[23].CLK
|
|
clk_i => ctrl[24].CLK
|
|
clk_i => ctrl[25].CLK
|
|
clk_i => ctrl[26].CLK
|
|
clk_i => ctrl[27].CLK
|
|
clk_i => ctrl[28].CLK
|
|
clk_i => ctrl[29].CLK
|
|
clk_i => ctrl[33].CLK
|
|
clk_i => ctrl[34].CLK
|
|
clk_i => ctrl[35].CLK
|
|
clk_i => ctrl[36].CLK
|
|
clk_i => ctrl[37].CLK
|
|
clk_i => ctrl[38].CLK
|
|
clk_i => ctrl[39].CLK
|
|
clk_i => ctrl[40].CLK
|
|
clk_i => ctrl[41].CLK
|
|
clk_i => execute_engine.branched.CLK
|
|
clk_i => execute_engine.sleep.CLK
|
|
clk_i => execute_engine.pc_last[1].CLK
|
|
clk_i => execute_engine.pc_last[2].CLK
|
|
clk_i => execute_engine.pc_last[3].CLK
|
|
clk_i => execute_engine.pc_last[4].CLK
|
|
clk_i => execute_engine.pc_last[5].CLK
|
|
clk_i => execute_engine.pc_last[6].CLK
|
|
clk_i => execute_engine.pc_last[7].CLK
|
|
clk_i => execute_engine.pc_last[8].CLK
|
|
clk_i => execute_engine.pc_last[9].CLK
|
|
clk_i => execute_engine.pc_last[10].CLK
|
|
clk_i => execute_engine.pc_last[11].CLK
|
|
clk_i => execute_engine.pc_last[12].CLK
|
|
clk_i => execute_engine.pc_last[13].CLK
|
|
clk_i => execute_engine.pc_last[14].CLK
|
|
clk_i => execute_engine.pc_last[15].CLK
|
|
clk_i => execute_engine.pc_last[16].CLK
|
|
clk_i => execute_engine.pc_last[17].CLK
|
|
clk_i => execute_engine.pc_last[18].CLK
|
|
clk_i => execute_engine.pc_last[19].CLK
|
|
clk_i => execute_engine.pc_last[20].CLK
|
|
clk_i => execute_engine.pc_last[21].CLK
|
|
clk_i => execute_engine.pc_last[22].CLK
|
|
clk_i => execute_engine.pc_last[23].CLK
|
|
clk_i => execute_engine.pc_last[24].CLK
|
|
clk_i => execute_engine.pc_last[25].CLK
|
|
clk_i => execute_engine.pc_last[26].CLK
|
|
clk_i => execute_engine.pc_last[27].CLK
|
|
clk_i => execute_engine.pc_last[28].CLK
|
|
clk_i => execute_engine.pc_last[29].CLK
|
|
clk_i => execute_engine.pc_last[30].CLK
|
|
clk_i => execute_engine.pc_last[31].CLK
|
|
clk_i => execute_engine.next_pc[1].CLK
|
|
clk_i => execute_engine.next_pc[2].CLK
|
|
clk_i => execute_engine.next_pc[3].CLK
|
|
clk_i => execute_engine.next_pc[4].CLK
|
|
clk_i => execute_engine.next_pc[5].CLK
|
|
clk_i => execute_engine.next_pc[6].CLK
|
|
clk_i => execute_engine.next_pc[7].CLK
|
|
clk_i => execute_engine.next_pc[8].CLK
|
|
clk_i => execute_engine.next_pc[9].CLK
|
|
clk_i => execute_engine.next_pc[10].CLK
|
|
clk_i => execute_engine.next_pc[11].CLK
|
|
clk_i => execute_engine.next_pc[12].CLK
|
|
clk_i => execute_engine.next_pc[13].CLK
|
|
clk_i => execute_engine.next_pc[14].CLK
|
|
clk_i => execute_engine.next_pc[15].CLK
|
|
clk_i => execute_engine.next_pc[16].CLK
|
|
clk_i => execute_engine.next_pc[17].CLK
|
|
clk_i => execute_engine.next_pc[18].CLK
|
|
clk_i => execute_engine.next_pc[19].CLK
|
|
clk_i => execute_engine.next_pc[20].CLK
|
|
clk_i => execute_engine.next_pc[21].CLK
|
|
clk_i => execute_engine.next_pc[22].CLK
|
|
clk_i => execute_engine.next_pc[23].CLK
|
|
clk_i => execute_engine.next_pc[24].CLK
|
|
clk_i => execute_engine.next_pc[25].CLK
|
|
clk_i => execute_engine.next_pc[26].CLK
|
|
clk_i => execute_engine.next_pc[27].CLK
|
|
clk_i => execute_engine.next_pc[28].CLK
|
|
clk_i => execute_engine.next_pc[29].CLK
|
|
clk_i => execute_engine.next_pc[30].CLK
|
|
clk_i => execute_engine.next_pc[31].CLK
|
|
clk_i => execute_engine.pc[0].CLK
|
|
clk_i => execute_engine.pc[1].CLK
|
|
clk_i => execute_engine.pc[2].CLK
|
|
clk_i => execute_engine.pc[3].CLK
|
|
clk_i => execute_engine.pc[4].CLK
|
|
clk_i => execute_engine.pc[5].CLK
|
|
clk_i => execute_engine.pc[6].CLK
|
|
clk_i => execute_engine.pc[7].CLK
|
|
clk_i => execute_engine.pc[8].CLK
|
|
clk_i => execute_engine.pc[9].CLK
|
|
clk_i => execute_engine.pc[10].CLK
|
|
clk_i => execute_engine.pc[11].CLK
|
|
clk_i => execute_engine.pc[12].CLK
|
|
clk_i => execute_engine.pc[13].CLK
|
|
clk_i => execute_engine.pc[14].CLK
|
|
clk_i => execute_engine.pc[15].CLK
|
|
clk_i => execute_engine.pc[16].CLK
|
|
clk_i => execute_engine.pc[17].CLK
|
|
clk_i => execute_engine.pc[18].CLK
|
|
clk_i => execute_engine.pc[19].CLK
|
|
clk_i => execute_engine.pc[20].CLK
|
|
clk_i => execute_engine.pc[21].CLK
|
|
clk_i => execute_engine.pc[22].CLK
|
|
clk_i => execute_engine.pc[23].CLK
|
|
clk_i => execute_engine.pc[24].CLK
|
|
clk_i => execute_engine.pc[25].CLK
|
|
clk_i => execute_engine.pc[26].CLK
|
|
clk_i => execute_engine.pc[27].CLK
|
|
clk_i => execute_engine.pc[28].CLK
|
|
clk_i => execute_engine.pc[29].CLK
|
|
clk_i => execute_engine.pc[30].CLK
|
|
clk_i => execute_engine.pc[31].CLK
|
|
clk_i => execute_engine.is_ici.CLK
|
|
clk_i => execute_engine.is_ci.CLK
|
|
clk_i => execute_engine.i_reg[0].CLK
|
|
clk_i => execute_engine.i_reg[1].CLK
|
|
clk_i => execute_engine.i_reg[2].CLK
|
|
clk_i => execute_engine.i_reg[3].CLK
|
|
clk_i => execute_engine.i_reg[4].CLK
|
|
clk_i => execute_engine.i_reg[5].CLK
|
|
clk_i => execute_engine.i_reg[6].CLK
|
|
clk_i => execute_engine.i_reg[7].CLK
|
|
clk_i => execute_engine.i_reg[8].CLK
|
|
clk_i => execute_engine.i_reg[9].CLK
|
|
clk_i => execute_engine.i_reg[10].CLK
|
|
clk_i => execute_engine.i_reg[11].CLK
|
|
clk_i => execute_engine.i_reg[12].CLK
|
|
clk_i => execute_engine.i_reg[13].CLK
|
|
clk_i => execute_engine.i_reg[14].CLK
|
|
clk_i => execute_engine.i_reg[15].CLK
|
|
clk_i => execute_engine.i_reg[16].CLK
|
|
clk_i => execute_engine.i_reg[17].CLK
|
|
clk_i => execute_engine.i_reg[18].CLK
|
|
clk_i => execute_engine.i_reg[19].CLK
|
|
clk_i => execute_engine.i_reg[20].CLK
|
|
clk_i => execute_engine.i_reg[21].CLK
|
|
clk_i => execute_engine.i_reg[22].CLK
|
|
clk_i => execute_engine.i_reg[23].CLK
|
|
clk_i => execute_engine.i_reg[24].CLK
|
|
clk_i => execute_engine.i_reg[25].CLK
|
|
clk_i => execute_engine.i_reg[26].CLK
|
|
clk_i => execute_engine.i_reg[27].CLK
|
|
clk_i => execute_engine.i_reg[28].CLK
|
|
clk_i => execute_engine.i_reg[29].CLK
|
|
clk_i => execute_engine.i_reg[30].CLK
|
|
clk_i => execute_engine.i_reg[31].CLK
|
|
clk_i => imm_o[0]~reg0.CLK
|
|
clk_i => imm_o[1]~reg0.CLK
|
|
clk_i => imm_o[2]~reg0.CLK
|
|
clk_i => imm_o[3]~reg0.CLK
|
|
clk_i => imm_o[4]~reg0.CLK
|
|
clk_i => imm_o[5]~reg0.CLK
|
|
clk_i => imm_o[6]~reg0.CLK
|
|
clk_i => imm_o[7]~reg0.CLK
|
|
clk_i => imm_o[8]~reg0.CLK
|
|
clk_i => imm_o[9]~reg0.CLK
|
|
clk_i => imm_o[10]~reg0.CLK
|
|
clk_i => imm_o[11]~reg0.CLK
|
|
clk_i => imm_o[12]~reg0.CLK
|
|
clk_i => imm_o[13]~reg0.CLK
|
|
clk_i => imm_o[14]~reg0.CLK
|
|
clk_i => imm_o[15]~reg0.CLK
|
|
clk_i => imm_o[16]~reg0.CLK
|
|
clk_i => imm_o[17]~reg0.CLK
|
|
clk_i => imm_o[18]~reg0.CLK
|
|
clk_i => imm_o[19]~reg0.CLK
|
|
clk_i => imm_o[20]~reg0.CLK
|
|
clk_i => imm_o[21]~reg0.CLK
|
|
clk_i => imm_o[22]~reg0.CLK
|
|
clk_i => imm_o[23]~reg0.CLK
|
|
clk_i => imm_o[24]~reg0.CLK
|
|
clk_i => imm_o[25]~reg0.CLK
|
|
clk_i => imm_o[26]~reg0.CLK
|
|
clk_i => imm_o[27]~reg0.CLK
|
|
clk_i => imm_o[28]~reg0.CLK
|
|
clk_i => imm_o[29]~reg0.CLK
|
|
clk_i => imm_o[30]~reg0.CLK
|
|
clk_i => imm_o[31]~reg0.CLK
|
|
clk_i => issue_engine.align.CLK
|
|
clk_i => fetch_engine.pmp_err.CLK
|
|
clk_i => fetch_engine.pc[2].CLK
|
|
clk_i => fetch_engine.pc[3].CLK
|
|
clk_i => fetch_engine.pc[4].CLK
|
|
clk_i => fetch_engine.pc[5].CLK
|
|
clk_i => fetch_engine.pc[6].CLK
|
|
clk_i => fetch_engine.pc[7].CLK
|
|
clk_i => fetch_engine.pc[8].CLK
|
|
clk_i => fetch_engine.pc[9].CLK
|
|
clk_i => fetch_engine.pc[10].CLK
|
|
clk_i => fetch_engine.pc[11].CLK
|
|
clk_i => fetch_engine.pc[12].CLK
|
|
clk_i => fetch_engine.pc[13].CLK
|
|
clk_i => fetch_engine.pc[14].CLK
|
|
clk_i => fetch_engine.pc[15].CLK
|
|
clk_i => fetch_engine.pc[16].CLK
|
|
clk_i => fetch_engine.pc[17].CLK
|
|
clk_i => fetch_engine.pc[18].CLK
|
|
clk_i => fetch_engine.pc[19].CLK
|
|
clk_i => fetch_engine.pc[20].CLK
|
|
clk_i => fetch_engine.pc[21].CLK
|
|
clk_i => fetch_engine.pc[22].CLK
|
|
clk_i => fetch_engine.pc[23].CLK
|
|
clk_i => fetch_engine.pc[24].CLK
|
|
clk_i => fetch_engine.pc[25].CLK
|
|
clk_i => fetch_engine.pc[26].CLK
|
|
clk_i => fetch_engine.pc[27].CLK
|
|
clk_i => fetch_engine.pc[28].CLK
|
|
clk_i => fetch_engine.pc[29].CLK
|
|
clk_i => fetch_engine.pc[30].CLK
|
|
clk_i => fetch_engine.pc[31].CLK
|
|
clk_i => fetch_engine.unaligned.CLK
|
|
clk_i => fetch_engine.restart.CLK
|
|
clk_i => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.clk_i
|
|
clk_i => debug_ctrl.state~1.DATAIN
|
|
clk_i => execute_engine.state_prev2~1.DATAIN
|
|
clk_i => execute_engine.state_prev~1.DATAIN
|
|
clk_i => execute_engine.state~1.DATAIN
|
|
clk_i => fetch_engine.state_prev~1.DATAIN
|
|
clk_i => fetch_engine.state~1.DATAIN
|
|
rstn_i => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.rstn_i
|
|
rstn_i => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.rstn_i
|
|
rstn_i => ctrl[0].ACLR
|
|
rstn_i => ctrl[21].ACLR
|
|
rstn_i => ctrl[22].ACLR
|
|
rstn_i => ctrl[23].ACLR
|
|
rstn_i => ctrl[24].ACLR
|
|
rstn_i => ctrl[25].ACLR
|
|
rstn_i => ctrl[26].ACLR
|
|
rstn_i => ctrl[27].ACLR
|
|
rstn_i => ctrl[28].ACLR
|
|
rstn_i => ctrl[29].ACLR
|
|
rstn_i => ctrl[33].ACLR
|
|
rstn_i => ctrl[34].ACLR
|
|
rstn_i => ctrl[35].ACLR
|
|
rstn_i => ctrl[36].ACLR
|
|
rstn_i => ctrl[37].ACLR
|
|
rstn_i => ctrl[38].ACLR
|
|
rstn_i => ctrl[39].ACLR
|
|
rstn_i => ctrl[40].ACLR
|
|
rstn_i => ctrl[41].ACLR
|
|
rstn_i => execute_engine.branched.PRESET
|
|
rstn_i => execute_engine.sleep.ACLR
|
|
rstn_i => execute_engine.pc_last[1].ACLR
|
|
rstn_i => execute_engine.pc_last[2].ACLR
|
|
rstn_i => execute_engine.pc_last[3].ACLR
|
|
rstn_i => execute_engine.pc_last[4].ACLR
|
|
rstn_i => execute_engine.pc_last[5].ACLR
|
|
rstn_i => execute_engine.pc_last[6].ACLR
|
|
rstn_i => execute_engine.pc_last[7].ACLR
|
|
rstn_i => execute_engine.pc_last[8].ACLR
|
|
rstn_i => execute_engine.pc_last[9].ACLR
|
|
rstn_i => execute_engine.pc_last[10].ACLR
|
|
rstn_i => execute_engine.pc_last[11].ACLR
|
|
rstn_i => execute_engine.pc_last[12].ACLR
|
|
rstn_i => execute_engine.pc_last[13].ACLR
|
|
rstn_i => execute_engine.pc_last[14].ACLR
|
|
rstn_i => execute_engine.pc_last[15].ACLR
|
|
rstn_i => execute_engine.pc_last[16].ACLR
|
|
rstn_i => execute_engine.pc_last[17].ACLR
|
|
rstn_i => execute_engine.pc_last[18].ACLR
|
|
rstn_i => execute_engine.pc_last[19].ACLR
|
|
rstn_i => execute_engine.pc_last[20].ACLR
|
|
rstn_i => execute_engine.pc_last[21].ACLR
|
|
rstn_i => execute_engine.pc_last[22].ACLR
|
|
rstn_i => execute_engine.pc_last[23].ACLR
|
|
rstn_i => execute_engine.pc_last[24].ACLR
|
|
rstn_i => execute_engine.pc_last[25].ACLR
|
|
rstn_i => execute_engine.pc_last[26].ACLR
|
|
rstn_i => execute_engine.pc_last[27].ACLR
|
|
rstn_i => execute_engine.pc_last[28].ACLR
|
|
rstn_i => execute_engine.pc_last[29].ACLR
|
|
rstn_i => execute_engine.pc_last[30].ACLR
|
|
rstn_i => execute_engine.pc_last[31].ACLR
|
|
rstn_i => execute_engine.next_pc[1].ACLR
|
|
rstn_i => execute_engine.next_pc[2].ACLR
|
|
rstn_i => execute_engine.next_pc[3].ACLR
|
|
rstn_i => execute_engine.next_pc[4].ACLR
|
|
rstn_i => execute_engine.next_pc[5].ACLR
|
|
rstn_i => execute_engine.next_pc[6].ACLR
|
|
rstn_i => execute_engine.next_pc[7].ACLR
|
|
rstn_i => execute_engine.next_pc[8].ACLR
|
|
rstn_i => execute_engine.next_pc[9].ACLR
|
|
rstn_i => execute_engine.next_pc[10].ACLR
|
|
rstn_i => execute_engine.next_pc[11].ACLR
|
|
rstn_i => execute_engine.next_pc[12].ACLR
|
|
rstn_i => execute_engine.next_pc[13].ACLR
|
|
rstn_i => execute_engine.next_pc[14].ACLR
|
|
rstn_i => execute_engine.next_pc[15].ACLR
|
|
rstn_i => execute_engine.next_pc[16].ACLR
|
|
rstn_i => execute_engine.next_pc[17].ACLR
|
|
rstn_i => execute_engine.next_pc[18].ACLR
|
|
rstn_i => execute_engine.next_pc[19].ACLR
|
|
rstn_i => execute_engine.next_pc[20].ACLR
|
|
rstn_i => execute_engine.next_pc[21].ACLR
|
|
rstn_i => execute_engine.next_pc[22].ACLR
|
|
rstn_i => execute_engine.next_pc[23].ACLR
|
|
rstn_i => execute_engine.next_pc[24].ACLR
|
|
rstn_i => execute_engine.next_pc[25].ACLR
|
|
rstn_i => execute_engine.next_pc[26].ACLR
|
|
rstn_i => execute_engine.next_pc[27].ACLR
|
|
rstn_i => execute_engine.next_pc[28].ACLR
|
|
rstn_i => execute_engine.next_pc[29].ACLR
|
|
rstn_i => execute_engine.next_pc[30].ACLR
|
|
rstn_i => execute_engine.next_pc[31].ACLR
|
|
rstn_i => execute_engine.pc[0].ACLR
|
|
rstn_i => execute_engine.pc[1].ACLR
|
|
rstn_i => execute_engine.pc[2].ACLR
|
|
rstn_i => execute_engine.pc[3].ACLR
|
|
rstn_i => execute_engine.pc[4].ACLR
|
|
rstn_i => execute_engine.pc[5].ACLR
|
|
rstn_i => execute_engine.pc[6].ACLR
|
|
rstn_i => execute_engine.pc[7].ACLR
|
|
rstn_i => execute_engine.pc[8].ACLR
|
|
rstn_i => execute_engine.pc[9].ACLR
|
|
rstn_i => execute_engine.pc[10].ACLR
|
|
rstn_i => execute_engine.pc[11].ACLR
|
|
rstn_i => execute_engine.pc[12].ACLR
|
|
rstn_i => execute_engine.pc[13].ACLR
|
|
rstn_i => execute_engine.pc[14].ACLR
|
|
rstn_i => execute_engine.pc[15].ACLR
|
|
rstn_i => execute_engine.pc[16].PRESET
|
|
rstn_i => execute_engine.pc[17].PRESET
|
|
rstn_i => execute_engine.pc[18].PRESET
|
|
rstn_i => execute_engine.pc[19].PRESET
|
|
rstn_i => execute_engine.pc[20].PRESET
|
|
rstn_i => execute_engine.pc[21].PRESET
|
|
rstn_i => execute_engine.pc[22].PRESET
|
|
rstn_i => execute_engine.pc[23].PRESET
|
|
rstn_i => execute_engine.pc[24].PRESET
|
|
rstn_i => execute_engine.pc[25].PRESET
|
|
rstn_i => execute_engine.pc[26].PRESET
|
|
rstn_i => execute_engine.pc[27].PRESET
|
|
rstn_i => execute_engine.pc[28].PRESET
|
|
rstn_i => execute_engine.pc[29].PRESET
|
|
rstn_i => execute_engine.pc[30].PRESET
|
|
rstn_i => execute_engine.pc[31].PRESET
|
|
rstn_i => execute_engine.is_ici.ACLR
|
|
rstn_i => execute_engine.is_ci.ACLR
|
|
rstn_i => execute_engine.i_reg[0].ACLR
|
|
rstn_i => execute_engine.i_reg[1].ACLR
|
|
rstn_i => execute_engine.i_reg[2].ACLR
|
|
rstn_i => execute_engine.i_reg[3].ACLR
|
|
rstn_i => execute_engine.i_reg[4].ACLR
|
|
rstn_i => execute_engine.i_reg[5].ACLR
|
|
rstn_i => execute_engine.i_reg[6].ACLR
|
|
rstn_i => execute_engine.i_reg[7].ACLR
|
|
rstn_i => execute_engine.i_reg[8].ACLR
|
|
rstn_i => execute_engine.i_reg[9].ACLR
|
|
rstn_i => execute_engine.i_reg[10].ACLR
|
|
rstn_i => execute_engine.i_reg[11].ACLR
|
|
rstn_i => execute_engine.i_reg[12].ACLR
|
|
rstn_i => execute_engine.i_reg[13].ACLR
|
|
rstn_i => execute_engine.i_reg[14].ACLR
|
|
rstn_i => execute_engine.i_reg[15].ACLR
|
|
rstn_i => execute_engine.i_reg[16].ACLR
|
|
rstn_i => execute_engine.i_reg[17].ACLR
|
|
rstn_i => execute_engine.i_reg[18].ACLR
|
|
rstn_i => execute_engine.i_reg[19].ACLR
|
|
rstn_i => execute_engine.i_reg[20].ACLR
|
|
rstn_i => execute_engine.i_reg[21].ACLR
|
|
rstn_i => execute_engine.i_reg[22].ACLR
|
|
rstn_i => execute_engine.i_reg[23].ACLR
|
|
rstn_i => execute_engine.i_reg[24].ACLR
|
|
rstn_i => execute_engine.i_reg[25].ACLR
|
|
rstn_i => execute_engine.i_reg[26].ACLR
|
|
rstn_i => execute_engine.i_reg[27].ACLR
|
|
rstn_i => execute_engine.i_reg[28].ACLR
|
|
rstn_i => execute_engine.i_reg[29].ACLR
|
|
rstn_i => execute_engine.i_reg[30].ACLR
|
|
rstn_i => execute_engine.i_reg[31].ACLR
|
|
rstn_i => csr.dcsr_step.ACLR
|
|
rstn_i => csr.frm[0].ACLR
|
|
rstn_i => csr.frm[1].ACLR
|
|
rstn_i => csr.frm[2].ACLR
|
|
rstn_i => csr.mscratch[0].ACLR
|
|
rstn_i => csr.mscratch[1].ACLR
|
|
rstn_i => csr.mscratch[2].PRESET
|
|
rstn_i => csr.mscratch[3].ACLR
|
|
rstn_i => csr.mscratch[4].ACLR
|
|
rstn_i => csr.mscratch[5].ACLR
|
|
rstn_i => csr.mscratch[6].ACLR
|
|
rstn_i => csr.mscratch[7].ACLR
|
|
rstn_i => csr.mscratch[8].PRESET
|
|
rstn_i => csr.mscratch[9].PRESET
|
|
rstn_i => csr.mscratch[10].PRESET
|
|
rstn_i => csr.mscratch[11].ACLR
|
|
rstn_i => csr.mscratch[12].ACLR
|
|
rstn_i => csr.mscratch[13].ACLR
|
|
rstn_i => csr.mscratch[14].ACLR
|
|
rstn_i => csr.mscratch[15].ACLR
|
|
rstn_i => csr.mscratch[16].ACLR
|
|
rstn_i => csr.mscratch[17].ACLR
|
|
rstn_i => csr.mscratch[18].ACLR
|
|
rstn_i => csr.mscratch[19].PRESET
|
|
rstn_i => csr.mscratch[20].ACLR
|
|
rstn_i => csr.mscratch[21].ACLR
|
|
rstn_i => csr.mscratch[22].ACLR
|
|
rstn_i => csr.mscratch[23].PRESET
|
|
rstn_i => csr.mscratch[24].PRESET
|
|
rstn_i => csr.mscratch[25].ACLR
|
|
rstn_i => csr.mscratch[26].ACLR
|
|
rstn_i => csr.mscratch[27].PRESET
|
|
rstn_i => csr.mscratch[28].PRESET
|
|
rstn_i => csr.mscratch[29].ACLR
|
|
rstn_i => csr.mscratch[30].ACLR
|
|
rstn_i => csr.mscratch[31].ACLR
|
|
rstn_i => csr.mtval[0].ACLR
|
|
rstn_i => csr.mtval[1].ACLR
|
|
rstn_i => csr.mtval[2].ACLR
|
|
rstn_i => csr.mtval[3].ACLR
|
|
rstn_i => csr.mtval[4].ACLR
|
|
rstn_i => csr.mtval[5].ACLR
|
|
rstn_i => csr.mtval[6].ACLR
|
|
rstn_i => csr.mtval[7].ACLR
|
|
rstn_i => csr.mtval[8].ACLR
|
|
rstn_i => csr.mtval[9].ACLR
|
|
rstn_i => csr.mtval[10].ACLR
|
|
rstn_i => csr.mtval[11].ACLR
|
|
rstn_i => csr.mtval[12].ACLR
|
|
rstn_i => csr.mtval[13].ACLR
|
|
rstn_i => csr.mtval[14].ACLR
|
|
rstn_i => csr.mtval[15].ACLR
|
|
rstn_i => csr.mtval[16].ACLR
|
|
rstn_i => csr.mtval[17].ACLR
|
|
rstn_i => csr.mtval[18].ACLR
|
|
rstn_i => csr.mtval[19].ACLR
|
|
rstn_i => csr.mtval[20].ACLR
|
|
rstn_i => csr.mtval[21].ACLR
|
|
rstn_i => csr.mtval[22].ACLR
|
|
rstn_i => csr.mtval[23].ACLR
|
|
rstn_i => csr.mtval[24].ACLR
|
|
rstn_i => csr.mtval[25].ACLR
|
|
rstn_i => csr.mtval[26].ACLR
|
|
rstn_i => csr.mtval[27].ACLR
|
|
rstn_i => csr.mtval[28].ACLR
|
|
rstn_i => csr.mtval[29].ACLR
|
|
rstn_i => csr.mtval[30].ACLR
|
|
rstn_i => csr.mtval[31].ACLR
|
|
rstn_i => csr.mtvec[2].ACLR
|
|
rstn_i => csr.mtvec[3].ACLR
|
|
rstn_i => csr.mtvec[4].ACLR
|
|
rstn_i => csr.mtvec[5].ACLR
|
|
rstn_i => csr.mtvec[6].ACLR
|
|
rstn_i => csr.mtvec[7].ACLR
|
|
rstn_i => csr.mtvec[8].ACLR
|
|
rstn_i => csr.mtvec[9].ACLR
|
|
rstn_i => csr.mtvec[10].ACLR
|
|
rstn_i => csr.mtvec[11].ACLR
|
|
rstn_i => csr.mtvec[12].ACLR
|
|
rstn_i => csr.mtvec[13].ACLR
|
|
rstn_i => csr.mtvec[14].ACLR
|
|
rstn_i => csr.mtvec[15].ACLR
|
|
rstn_i => csr.mtvec[16].ACLR
|
|
rstn_i => csr.mtvec[17].ACLR
|
|
rstn_i => csr.mtvec[18].ACLR
|
|
rstn_i => csr.mtvec[19].ACLR
|
|
rstn_i => csr.mtvec[20].ACLR
|
|
rstn_i => csr.mtvec[21].ACLR
|
|
rstn_i => csr.mtvec[22].ACLR
|
|
rstn_i => csr.mtvec[23].ACLR
|
|
rstn_i => csr.mtvec[24].ACLR
|
|
rstn_i => csr.mtvec[25].ACLR
|
|
rstn_i => csr.mtvec[26].ACLR
|
|
rstn_i => csr.mtvec[27].ACLR
|
|
rstn_i => csr.mtvec[28].ACLR
|
|
rstn_i => csr.mtvec[29].ACLR
|
|
rstn_i => csr.mtvec[30].ACLR
|
|
rstn_i => csr.mtvec[31].ACLR
|
|
rstn_i => csr.mcause[0].ACLR
|
|
rstn_i => csr.mcause[1].ACLR
|
|
rstn_i => csr.mcause[2].ACLR
|
|
rstn_i => csr.mcause[3].ACLR
|
|
rstn_i => csr.mcause[4].ACLR
|
|
rstn_i => csr.mcause[5].ACLR
|
|
rstn_i => csr.mepc[1].ACLR
|
|
rstn_i => csr.mepc[2].ACLR
|
|
rstn_i => csr.mepc[3].ACLR
|
|
rstn_i => csr.mepc[4].ACLR
|
|
rstn_i => csr.mepc[5].ACLR
|
|
rstn_i => csr.mepc[6].ACLR
|
|
rstn_i => csr.mepc[7].ACLR
|
|
rstn_i => csr.mepc[8].ACLR
|
|
rstn_i => csr.mepc[9].ACLR
|
|
rstn_i => csr.mepc[10].ACLR
|
|
rstn_i => csr.mepc[11].ACLR
|
|
rstn_i => csr.mepc[12].ACLR
|
|
rstn_i => csr.mepc[13].ACLR
|
|
rstn_i => csr.mepc[14].ACLR
|
|
rstn_i => csr.mepc[15].ACLR
|
|
rstn_i => csr.mepc[16].ACLR
|
|
rstn_i => csr.mepc[17].ACLR
|
|
rstn_i => csr.mepc[18].ACLR
|
|
rstn_i => csr.mepc[19].ACLR
|
|
rstn_i => csr.mepc[20].ACLR
|
|
rstn_i => csr.mepc[21].ACLR
|
|
rstn_i => csr.mepc[22].ACLR
|
|
rstn_i => csr.mepc[23].ACLR
|
|
rstn_i => csr.mepc[24].ACLR
|
|
rstn_i => csr.mepc[25].ACLR
|
|
rstn_i => csr.mepc[26].ACLR
|
|
rstn_i => csr.mepc[27].ACLR
|
|
rstn_i => csr.mepc[28].ACLR
|
|
rstn_i => csr.mepc[29].ACLR
|
|
rstn_i => csr.mepc[30].ACLR
|
|
rstn_i => csr.mepc[31].ACLR
|
|
rstn_i => csr.privilege.PRESET
|
|
rstn_i => csr.mcountinhibit_ir.ACLR
|
|
rstn_i => csr.mcountinhibit_cy.ACLR
|
|
rstn_i => csr.mip_firq_nclr[0].ACLR
|
|
rstn_i => csr.mip_firq_nclr[1].ACLR
|
|
rstn_i => csr.mip_firq_nclr[2].ACLR
|
|
rstn_i => csr.mip_firq_nclr[3].ACLR
|
|
rstn_i => csr.mip_firq_nclr[4].ACLR
|
|
rstn_i => csr.mip_firq_nclr[5].ACLR
|
|
rstn_i => csr.mip_firq_nclr[6].ACLR
|
|
rstn_i => csr.mip_firq_nclr[7].ACLR
|
|
rstn_i => csr.mip_firq_nclr[8].ACLR
|
|
rstn_i => csr.mip_firq_nclr[9].ACLR
|
|
rstn_i => csr.mip_firq_nclr[10].ACLR
|
|
rstn_i => csr.mip_firq_nclr[11].ACLR
|
|
rstn_i => csr.mip_firq_nclr[12].ACLR
|
|
rstn_i => csr.mip_firq_nclr[13].ACLR
|
|
rstn_i => csr.mip_firq_nclr[14].ACLR
|
|
rstn_i => csr.mip_firq_nclr[15].ACLR
|
|
rstn_i => csr.mie_firq[0].ACLR
|
|
rstn_i => csr.mie_firq[1].ACLR
|
|
rstn_i => csr.mie_firq[2].ACLR
|
|
rstn_i => csr.mie_firq[3].ACLR
|
|
rstn_i => csr.mie_firq[4].ACLR
|
|
rstn_i => csr.mie_firq[5].ACLR
|
|
rstn_i => csr.mie_firq[6].ACLR
|
|
rstn_i => csr.mie_firq[7].ACLR
|
|
rstn_i => csr.mie_firq[8].ACLR
|
|
rstn_i => csr.mie_firq[9].ACLR
|
|
rstn_i => csr.mie_firq[10].ACLR
|
|
rstn_i => csr.mie_firq[11].ACLR
|
|
rstn_i => csr.mie_firq[12].ACLR
|
|
rstn_i => csr.mie_firq[13].ACLR
|
|
rstn_i => csr.mie_firq[14].ACLR
|
|
rstn_i => csr.mie_firq[15].ACLR
|
|
rstn_i => csr.mie_mti.ACLR
|
|
rstn_i => csr.mie_mei.ACLR
|
|
rstn_i => csr.mie_msi.ACLR
|
|
rstn_i => csr.mstatus_tw.ACLR
|
|
rstn_i => csr.mstatus_mprv.ACLR
|
|
rstn_i => csr.mstatus_mpp.ACLR
|
|
rstn_i => csr.mstatus_mpie.ACLR
|
|
rstn_i => csr.mstatus_mie.ACLR
|
|
rstn_i => csr.we.ACLR
|
|
rstn_i => fetch_engine.pmp_err.ACLR
|
|
rstn_i => fetch_engine.pc[2].ACLR
|
|
rstn_i => fetch_engine.pc[3].ACLR
|
|
rstn_i => fetch_engine.pc[4].ACLR
|
|
rstn_i => fetch_engine.pc[5].ACLR
|
|
rstn_i => fetch_engine.pc[6].ACLR
|
|
rstn_i => fetch_engine.pc[7].ACLR
|
|
rstn_i => fetch_engine.pc[8].ACLR
|
|
rstn_i => fetch_engine.pc[9].ACLR
|
|
rstn_i => fetch_engine.pc[10].ACLR
|
|
rstn_i => fetch_engine.pc[11].ACLR
|
|
rstn_i => fetch_engine.pc[12].ACLR
|
|
rstn_i => fetch_engine.pc[13].ACLR
|
|
rstn_i => fetch_engine.pc[14].ACLR
|
|
rstn_i => fetch_engine.pc[15].ACLR
|
|
rstn_i => fetch_engine.pc[16].ACLR
|
|
rstn_i => fetch_engine.pc[17].ACLR
|
|
rstn_i => fetch_engine.pc[18].ACLR
|
|
rstn_i => fetch_engine.pc[19].ACLR
|
|
rstn_i => fetch_engine.pc[20].ACLR
|
|
rstn_i => fetch_engine.pc[21].ACLR
|
|
rstn_i => fetch_engine.pc[22].ACLR
|
|
rstn_i => fetch_engine.pc[23].ACLR
|
|
rstn_i => fetch_engine.pc[24].ACLR
|
|
rstn_i => fetch_engine.pc[25].ACLR
|
|
rstn_i => fetch_engine.pc[26].ACLR
|
|
rstn_i => fetch_engine.pc[27].ACLR
|
|
rstn_i => fetch_engine.pc[28].ACLR
|
|
rstn_i => fetch_engine.pc[29].ACLR
|
|
rstn_i => fetch_engine.pc[30].ACLR
|
|
rstn_i => fetch_engine.pc[31].ACLR
|
|
rstn_i => fetch_engine.unaligned.ACLR
|
|
rstn_i => fetch_engine.restart.PRESET
|
|
rstn_i => trap_ctrl.irq_buf[0].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[1].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[2].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[3].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[4].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[5].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[6].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[7].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[8].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[9].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[10].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[11].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[12].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[13].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[14].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[15].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[16].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[17].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[18].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[19].ACLR
|
|
rstn_i => trap_ctrl.irq_buf[20].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[0].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[1].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[2].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[3].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[4].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[5].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[6].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[7].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[8].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[9].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[10].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[11].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[12].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[13].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[14].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[15].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[16].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[17].ACLR
|
|
rstn_i => trap_ctrl.irq_pnd[18].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[0].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[1].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[2].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[3].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[4].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[5].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[6].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[7].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[8].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[9].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[10].ACLR
|
|
rstn_i => trap_ctrl.exc_buf[11].ACLR
|
|
rstn_i => trap_ctrl.env_start.ACLR
|
|
rstn_i => csr.minstreth[0].ACLR
|
|
rstn_i => csr.minstreth[1].ACLR
|
|
rstn_i => csr.minstreth[2].ACLR
|
|
rstn_i => csr.minstreth[3].ACLR
|
|
rstn_i => csr.minstreth[4].ACLR
|
|
rstn_i => csr.minstreth[5].ACLR
|
|
rstn_i => csr.minstreth[6].ACLR
|
|
rstn_i => csr.minstreth[7].ACLR
|
|
rstn_i => csr.minstreth[8].ACLR
|
|
rstn_i => csr.minstreth[9].ACLR
|
|
rstn_i => csr.minstreth[10].ACLR
|
|
rstn_i => csr.minstreth[11].ACLR
|
|
rstn_i => csr.minstreth[12].ACLR
|
|
rstn_i => csr.minstreth[13].ACLR
|
|
rstn_i => csr.minstreth[14].ACLR
|
|
rstn_i => csr.minstreth[15].ACLR
|
|
rstn_i => csr.minstreth[16].ACLR
|
|
rstn_i => csr.minstreth[17].ACLR
|
|
rstn_i => csr.minstreth[18].ACLR
|
|
rstn_i => csr.minstreth[19].ACLR
|
|
rstn_i => csr.minstreth[20].ACLR
|
|
rstn_i => csr.minstreth[21].ACLR
|
|
rstn_i => csr.minstreth[22].ACLR
|
|
rstn_i => csr.minstreth[23].ACLR
|
|
rstn_i => csr.minstreth[24].ACLR
|
|
rstn_i => csr.minstreth[25].ACLR
|
|
rstn_i => csr.minstreth[26].ACLR
|
|
rstn_i => csr.minstreth[27].ACLR
|
|
rstn_i => csr.minstreth[28].ACLR
|
|
rstn_i => csr.minstreth[29].ACLR
|
|
rstn_i => csr.minstreth[30].ACLR
|
|
rstn_i => csr.minstreth[31].ACLR
|
|
rstn_i => csr.minstret_ovfl[0].ACLR
|
|
rstn_i => csr.minstret[0].ACLR
|
|
rstn_i => csr.minstret[1].ACLR
|
|
rstn_i => csr.minstret[2].ACLR
|
|
rstn_i => csr.minstret[3].ACLR
|
|
rstn_i => csr.minstret[4].ACLR
|
|
rstn_i => csr.minstret[5].ACLR
|
|
rstn_i => csr.minstret[6].ACLR
|
|
rstn_i => csr.minstret[7].ACLR
|
|
rstn_i => csr.minstret[8].ACLR
|
|
rstn_i => csr.minstret[9].ACLR
|
|
rstn_i => csr.minstret[10].ACLR
|
|
rstn_i => csr.minstret[11].ACLR
|
|
rstn_i => csr.minstret[12].ACLR
|
|
rstn_i => csr.minstret[13].ACLR
|
|
rstn_i => csr.minstret[14].ACLR
|
|
rstn_i => csr.minstret[15].ACLR
|
|
rstn_i => csr.minstret[16].ACLR
|
|
rstn_i => csr.minstret[17].ACLR
|
|
rstn_i => csr.minstret[18].ACLR
|
|
rstn_i => csr.minstret[19].ACLR
|
|
rstn_i => csr.minstret[20].ACLR
|
|
rstn_i => csr.minstret[21].ACLR
|
|
rstn_i => csr.minstret[22].ACLR
|
|
rstn_i => csr.minstret[23].ACLR
|
|
rstn_i => csr.minstret[24].ACLR
|
|
rstn_i => csr.minstret[25].ACLR
|
|
rstn_i => csr.minstret[26].ACLR
|
|
rstn_i => csr.minstret[27].ACLR
|
|
rstn_i => csr.minstret[28].ACLR
|
|
rstn_i => csr.minstret[29].ACLR
|
|
rstn_i => csr.minstret[30].ACLR
|
|
rstn_i => csr.minstret[31].ACLR
|
|
rstn_i => csr.mcycleh[0].ACLR
|
|
rstn_i => csr.mcycleh[1].ACLR
|
|
rstn_i => csr.mcycleh[2].ACLR
|
|
rstn_i => csr.mcycleh[3].ACLR
|
|
rstn_i => csr.mcycleh[4].ACLR
|
|
rstn_i => csr.mcycleh[5].ACLR
|
|
rstn_i => csr.mcycleh[6].ACLR
|
|
rstn_i => csr.mcycleh[7].ACLR
|
|
rstn_i => csr.mcycleh[8].ACLR
|
|
rstn_i => csr.mcycleh[9].ACLR
|
|
rstn_i => csr.mcycleh[10].ACLR
|
|
rstn_i => csr.mcycleh[11].ACLR
|
|
rstn_i => csr.mcycleh[12].ACLR
|
|
rstn_i => csr.mcycleh[13].ACLR
|
|
rstn_i => csr.mcycleh[14].ACLR
|
|
rstn_i => csr.mcycleh[15].ACLR
|
|
rstn_i => csr.mcycleh[16].ACLR
|
|
rstn_i => csr.mcycleh[17].ACLR
|
|
rstn_i => csr.mcycleh[18].ACLR
|
|
rstn_i => csr.mcycleh[19].ACLR
|
|
rstn_i => csr.mcycleh[20].ACLR
|
|
rstn_i => csr.mcycleh[21].ACLR
|
|
rstn_i => csr.mcycleh[22].ACLR
|
|
rstn_i => csr.mcycleh[23].ACLR
|
|
rstn_i => csr.mcycleh[24].ACLR
|
|
rstn_i => csr.mcycleh[25].ACLR
|
|
rstn_i => csr.mcycleh[26].ACLR
|
|
rstn_i => csr.mcycleh[27].ACLR
|
|
rstn_i => csr.mcycleh[28].ACLR
|
|
rstn_i => csr.mcycleh[29].ACLR
|
|
rstn_i => csr.mcycleh[30].ACLR
|
|
rstn_i => csr.mcycleh[31].ACLR
|
|
rstn_i => csr.mcycle_ovfl[0].ACLR
|
|
rstn_i => csr.mcycle[0].ACLR
|
|
rstn_i => csr.mcycle[1].ACLR
|
|
rstn_i => csr.mcycle[2].ACLR
|
|
rstn_i => csr.mcycle[3].ACLR
|
|
rstn_i => csr.mcycle[4].ACLR
|
|
rstn_i => csr.mcycle[5].ACLR
|
|
rstn_i => csr.mcycle[6].ACLR
|
|
rstn_i => csr.mcycle[7].ACLR
|
|
rstn_i => csr.mcycle[8].ACLR
|
|
rstn_i => csr.mcycle[9].ACLR
|
|
rstn_i => csr.mcycle[10].ACLR
|
|
rstn_i => csr.mcycle[11].ACLR
|
|
rstn_i => csr.mcycle[12].ACLR
|
|
rstn_i => csr.mcycle[13].ACLR
|
|
rstn_i => csr.mcycle[14].ACLR
|
|
rstn_i => csr.mcycle[15].ACLR
|
|
rstn_i => csr.mcycle[16].ACLR
|
|
rstn_i => csr.mcycle[17].ACLR
|
|
rstn_i => csr.mcycle[18].ACLR
|
|
rstn_i => csr.mcycle[19].ACLR
|
|
rstn_i => csr.mcycle[20].ACLR
|
|
rstn_i => csr.mcycle[21].ACLR
|
|
rstn_i => csr.mcycle[22].ACLR
|
|
rstn_i => csr.mcycle[23].ACLR
|
|
rstn_i => csr.mcycle[24].ACLR
|
|
rstn_i => csr.mcycle[25].ACLR
|
|
rstn_i => csr.mcycle[26].ACLR
|
|
rstn_i => csr.mcycle[27].ACLR
|
|
rstn_i => csr.mcycle[28].ACLR
|
|
rstn_i => csr.mcycle[29].ACLR
|
|
rstn_i => csr.mcycle[30].ACLR
|
|
rstn_i => csr.mcycle[31].ACLR
|
|
rstn_i => cnt_csr_we.instret[0].ACLR
|
|
rstn_i => cnt_csr_we.instret[1].ACLR
|
|
rstn_i => cnt_csr_we.cycle[0].ACLR
|
|
rstn_i => cnt_csr_we.cycle[1].ACLR
|
|
rstn_i => cnt_csr_we.wdata[0].ACLR
|
|
rstn_i => cnt_csr_we.wdata[1].ACLR
|
|
rstn_i => cnt_csr_we.wdata[2].ACLR
|
|
rstn_i => cnt_csr_we.wdata[3].ACLR
|
|
rstn_i => cnt_csr_we.wdata[4].ACLR
|
|
rstn_i => cnt_csr_we.wdata[5].ACLR
|
|
rstn_i => cnt_csr_we.wdata[6].ACLR
|
|
rstn_i => cnt_csr_we.wdata[7].ACLR
|
|
rstn_i => cnt_csr_we.wdata[8].ACLR
|
|
rstn_i => cnt_csr_we.wdata[9].ACLR
|
|
rstn_i => cnt_csr_we.wdata[10].ACLR
|
|
rstn_i => cnt_csr_we.wdata[11].ACLR
|
|
rstn_i => cnt_csr_we.wdata[12].ACLR
|
|
rstn_i => cnt_csr_we.wdata[13].ACLR
|
|
rstn_i => cnt_csr_we.wdata[14].ACLR
|
|
rstn_i => cnt_csr_we.wdata[15].ACLR
|
|
rstn_i => cnt_csr_we.wdata[16].ACLR
|
|
rstn_i => cnt_csr_we.wdata[17].ACLR
|
|
rstn_i => cnt_csr_we.wdata[18].ACLR
|
|
rstn_i => cnt_csr_we.wdata[19].ACLR
|
|
rstn_i => cnt_csr_we.wdata[20].ACLR
|
|
rstn_i => cnt_csr_we.wdata[21].ACLR
|
|
rstn_i => cnt_csr_we.wdata[22].ACLR
|
|
rstn_i => cnt_csr_we.wdata[23].ACLR
|
|
rstn_i => cnt_csr_we.wdata[24].ACLR
|
|
rstn_i => cnt_csr_we.wdata[25].ACLR
|
|
rstn_i => cnt_csr_we.wdata[26].ACLR
|
|
rstn_i => cnt_csr_we.wdata[27].ACLR
|
|
rstn_i => cnt_csr_we.wdata[28].ACLR
|
|
rstn_i => cnt_csr_we.wdata[29].ACLR
|
|
rstn_i => cnt_csr_we.wdata[30].ACLR
|
|
rstn_i => cnt_csr_we.wdata[31].ACLR
|
|
rstn_i => debug_ctrl.state~3.DATAIN
|
|
rstn_i => execute_engine.state_prev2~3.DATAIN
|
|
rstn_i => execute_engine.state_prev~3.DATAIN
|
|
rstn_i => execute_engine.state~3.DATAIN
|
|
rstn_i => fetch_engine.state_prev~3.DATAIN
|
|
rstn_i => fetch_engine.state~3.DATAIN
|
|
ctrl_o[0] <= ctrl_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[1] <= execute_engine.i_reg[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[2] <= execute_engine.i_reg[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[3] <= execute_engine.i_reg[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[4] <= execute_engine.i_reg[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[5] <= execute_engine.i_reg[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[6] <= execute_engine.i_reg[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[7] <= execute_engine.i_reg[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[8] <= execute_engine.i_reg[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[9] <= execute_engine.i_reg[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[10] <= execute_engine.i_reg[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[11] <= execute_engine.i_reg[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[12] <= execute_engine.i_reg[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[13] <= execute_engine.i_reg[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[14] <= execute_engine.i_reg[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[15] <= execute_engine.i_reg[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[16] <= execute_engine.i_reg[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[17] <= execute_engine.i_reg[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[18] <= execute_engine.i_reg[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[19] <= execute_engine.i_reg[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[20] <= execute_engine.i_reg[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[21] <= ctrl[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[22] <= ctrl[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[23] <= ctrl[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[24] <= ctrl[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[25] <= ctrl[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[26] <= ctrl[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[27] <= ctrl[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[28] <= ctrl[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[29] <= ctrl[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[30] <= csr.frm[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[31] <= csr.frm[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[32] <= csr.frm[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[33] <= ctrl[33].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[34] <= ctrl[34].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[35] <= ctrl[35].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[36] <= ctrl[36].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[37] <= ctrl[37].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[38] <= ctrl[38].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[39] <= ctrl[39].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[40] <= ctrl[40].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[41] <= ctrl[41].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[42] <= ctrl_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[43] <= execute_engine.i_reg[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[44] <= execute_engine.i_reg[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[45] <= execute_engine.i_reg[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[46] <= execute_engine.i_reg[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[47] <= execute_engine.i_reg[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[48] <= execute_engine.i_reg[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[49] <= execute_engine.i_reg[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[50] <= execute_engine.i_reg[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[51] <= execute_engine.i_reg[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[52] <= execute_engine.i_reg[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[53] <= execute_engine.i_reg[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[54] <= execute_engine.i_reg[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[55] <= execute_engine.i_reg[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[56] <= execute_engine.i_reg[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[57] <= execute_engine.i_reg[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[58] <= execute_engine.i_reg[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[59] <= execute_engine.i_reg[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[60] <= execute_engine.i_reg[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[61] <= execute_engine.i_reg[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[62] <= execute_engine.i_reg[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[63] <= execute_engine.i_reg[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[64] <= execute_engine.i_reg[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[65] <= csr.privilege.DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[66] <= execute_engine.sleep.DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[67] <= trap_ctrl.DB_MAX_OUTPUT_PORT_TYPE
|
|
ctrl_o[68] <= <GND>
|
|
i_bus_addr_o[0] <= <GND>
|
|
i_bus_addr_o[1] <= <GND>
|
|
i_bus_addr_o[2] <= fetch_engine.pc[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[3] <= fetch_engine.pc[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[4] <= fetch_engine.pc[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[5] <= fetch_engine.pc[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[6] <= fetch_engine.pc[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[7] <= fetch_engine.pc[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[8] <= fetch_engine.pc[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[9] <= fetch_engine.pc[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[10] <= fetch_engine.pc[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[11] <= fetch_engine.pc[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[12] <= fetch_engine.pc[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[13] <= fetch_engine.pc[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[14] <= fetch_engine.pc[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[15] <= fetch_engine.pc[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[16] <= fetch_engine.pc[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[17] <= fetch_engine.pc[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[18] <= fetch_engine.pc[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[19] <= fetch_engine.pc[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[20] <= fetch_engine.pc[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[21] <= fetch_engine.pc[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[22] <= fetch_engine.pc[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[23] <= fetch_engine.pc[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[24] <= fetch_engine.pc[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[25] <= fetch_engine.pc[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[26] <= fetch_engine.pc[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[27] <= fetch_engine.pc[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[28] <= fetch_engine.pc[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[29] <= fetch_engine.pc[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[30] <= fetch_engine.pc[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_addr_o[31] <= fetch_engine.pc[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_rdata_i[0] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[0]
|
|
i_bus_rdata_i[1] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[1]
|
|
i_bus_rdata_i[2] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[2]
|
|
i_bus_rdata_i[3] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[3]
|
|
i_bus_rdata_i[4] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[4]
|
|
i_bus_rdata_i[5] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[5]
|
|
i_bus_rdata_i[6] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[6]
|
|
i_bus_rdata_i[7] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[7]
|
|
i_bus_rdata_i[8] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[8]
|
|
i_bus_rdata_i[9] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[9]
|
|
i_bus_rdata_i[10] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[10]
|
|
i_bus_rdata_i[11] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[11]
|
|
i_bus_rdata_i[12] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[12]
|
|
i_bus_rdata_i[13] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[13]
|
|
i_bus_rdata_i[14] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[14]
|
|
i_bus_rdata_i[15] => neorv32_fifo:prefetch_buffer:0:prefetch_buffer_inst.wdata_i[15]
|
|
i_bus_rdata_i[16] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[0]
|
|
i_bus_rdata_i[17] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[1]
|
|
i_bus_rdata_i[18] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[2]
|
|
i_bus_rdata_i[19] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[3]
|
|
i_bus_rdata_i[20] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[4]
|
|
i_bus_rdata_i[21] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[5]
|
|
i_bus_rdata_i[22] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[6]
|
|
i_bus_rdata_i[23] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[7]
|
|
i_bus_rdata_i[24] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[8]
|
|
i_bus_rdata_i[25] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[9]
|
|
i_bus_rdata_i[26] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[10]
|
|
i_bus_rdata_i[27] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[11]
|
|
i_bus_rdata_i[28] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[12]
|
|
i_bus_rdata_i[29] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[13]
|
|
i_bus_rdata_i[30] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[14]
|
|
i_bus_rdata_i[31] => neorv32_fifo:prefetch_buffer:1:prefetch_buffer_inst.wdata_i[15]
|
|
i_bus_re_o <= i_bus_re_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
i_bus_ack_i => fetch_engine.resp.IN0
|
|
i_bus_err_i => fetch_engine.resp.IN1
|
|
i_bus_err_i => ipb.wdata[0][17].IN1
|
|
i_bus_err_i => ipb.wdata[1][17].IN1
|
|
i_pmp_fault_i => Selector35.IN2
|
|
alu_idone_i => execute_engine_fsm_comb.IN1
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => execute_engine.OUTPUTSELECT
|
|
bus_d_wait_i => ctrl_nxt.OUTPUTSELECT
|
|
cmp_i[0] => branch_taken.IN1
|
|
cmp_i[1] => branch_taken.IN1
|
|
alu_add_i[0] => ~NO_FANOUT~
|
|
alu_add_i[1] => execute_engine.DATAA
|
|
alu_add_i[2] => execute_engine.DATAA
|
|
alu_add_i[3] => execute_engine.DATAA
|
|
alu_add_i[4] => execute_engine.DATAA
|
|
alu_add_i[5] => execute_engine.DATAA
|
|
alu_add_i[6] => execute_engine.DATAA
|
|
alu_add_i[7] => execute_engine.DATAA
|
|
alu_add_i[8] => execute_engine.DATAA
|
|
alu_add_i[9] => execute_engine.DATAA
|
|
alu_add_i[10] => execute_engine.DATAA
|
|
alu_add_i[11] => execute_engine.DATAA
|
|
alu_add_i[12] => execute_engine.DATAA
|
|
alu_add_i[13] => execute_engine.DATAA
|
|
alu_add_i[14] => execute_engine.DATAA
|
|
alu_add_i[15] => execute_engine.DATAA
|
|
alu_add_i[16] => execute_engine.DATAA
|
|
alu_add_i[17] => execute_engine.DATAA
|
|
alu_add_i[18] => execute_engine.DATAA
|
|
alu_add_i[19] => execute_engine.DATAA
|
|
alu_add_i[20] => execute_engine.DATAA
|
|
alu_add_i[21] => execute_engine.DATAA
|
|
alu_add_i[22] => execute_engine.DATAA
|
|
alu_add_i[23] => execute_engine.DATAA
|
|
alu_add_i[24] => execute_engine.DATAA
|
|
alu_add_i[25] => execute_engine.DATAA
|
|
alu_add_i[26] => execute_engine.DATAA
|
|
alu_add_i[27] => execute_engine.DATAA
|
|
alu_add_i[28] => execute_engine.DATAA
|
|
alu_add_i[29] => execute_engine.DATAA
|
|
alu_add_i[30] => execute_engine.DATAA
|
|
alu_add_i[31] => execute_engine.DATAA
|
|
rs1_i[0] => \csr_write_data:tmp_v[0].DATAA
|
|
rs1_i[1] => \csr_write_data:tmp_v[1].DATAA
|
|
rs1_i[2] => \csr_write_data:tmp_v[2].DATAA
|
|
rs1_i[3] => \csr_write_data:tmp_v[3].DATAA
|
|
rs1_i[4] => \csr_write_data:tmp_v[4].DATAA
|
|
rs1_i[5] => \csr_write_data:tmp_v[5].DATAA
|
|
rs1_i[6] => \csr_write_data:tmp_v[6].DATAA
|
|
rs1_i[7] => \csr_write_data:tmp_v[7].DATAA
|
|
rs1_i[8] => \csr_write_data:tmp_v[8].DATAA
|
|
rs1_i[9] => \csr_write_data:tmp_v[9].DATAA
|
|
rs1_i[10] => \csr_write_data:tmp_v[10].DATAA
|
|
rs1_i[11] => \csr_write_data:tmp_v[11].DATAA
|
|
rs1_i[12] => \csr_write_data:tmp_v[12].DATAA
|
|
rs1_i[13] => \csr_write_data:tmp_v[13].DATAA
|
|
rs1_i[14] => \csr_write_data:tmp_v[14].DATAA
|
|
rs1_i[15] => \csr_write_data:tmp_v[15].DATAA
|
|
rs1_i[16] => \csr_write_data:tmp_v[16].DATAA
|
|
rs1_i[17] => \csr_write_data:tmp_v[17].DATAA
|
|
rs1_i[18] => \csr_write_data:tmp_v[18].DATAA
|
|
rs1_i[19] => \csr_write_data:tmp_v[19].DATAA
|
|
rs1_i[20] => \csr_write_data:tmp_v[20].DATAA
|
|
rs1_i[21] => \csr_write_data:tmp_v[21].DATAA
|
|
rs1_i[22] => \csr_write_data:tmp_v[22].DATAA
|
|
rs1_i[23] => \csr_write_data:tmp_v[23].DATAA
|
|
rs1_i[24] => \csr_write_data:tmp_v[24].DATAA
|
|
rs1_i[25] => \csr_write_data:tmp_v[25].DATAA
|
|
rs1_i[26] => \csr_write_data:tmp_v[26].DATAA
|
|
rs1_i[27] => \csr_write_data:tmp_v[27].DATAA
|
|
rs1_i[28] => \csr_write_data:tmp_v[28].DATAA
|
|
rs1_i[29] => \csr_write_data:tmp_v[29].DATAA
|
|
rs1_i[30] => \csr_write_data:tmp_v[30].DATAA
|
|
rs1_i[31] => \csr_write_data:tmp_v[31].DATAA
|
|
imm_o[0] <= imm_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[1] <= imm_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[2] <= imm_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[3] <= imm_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[4] <= imm_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[5] <= imm_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[6] <= imm_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[7] <= imm_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[8] <= imm_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[9] <= imm_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[10] <= imm_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[11] <= imm_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[12] <= imm_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[13] <= imm_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[14] <= imm_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[15] <= imm_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[16] <= imm_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[17] <= imm_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[18] <= imm_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[19] <= imm_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[20] <= imm_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[21] <= imm_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[22] <= imm_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[23] <= imm_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[24] <= imm_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[25] <= imm_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[26] <= imm_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[27] <= imm_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[28] <= imm_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[29] <= imm_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[30] <= imm_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
imm_o[31] <= imm_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[0] <= <GND>
|
|
curr_pc_o[1] <= execute_engine.pc[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[2] <= execute_engine.pc[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[3] <= execute_engine.pc[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[4] <= execute_engine.pc[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[5] <= execute_engine.pc[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[6] <= execute_engine.pc[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[7] <= execute_engine.pc[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[8] <= execute_engine.pc[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[9] <= execute_engine.pc[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[10] <= execute_engine.pc[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[11] <= execute_engine.pc[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[12] <= execute_engine.pc[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[13] <= execute_engine.pc[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[14] <= execute_engine.pc[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[15] <= execute_engine.pc[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[16] <= execute_engine.pc[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[17] <= execute_engine.pc[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[18] <= execute_engine.pc[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[19] <= execute_engine.pc[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[20] <= execute_engine.pc[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[21] <= execute_engine.pc[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[22] <= execute_engine.pc[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[23] <= execute_engine.pc[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[24] <= execute_engine.pc[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[25] <= execute_engine.pc[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[26] <= execute_engine.pc[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[27] <= execute_engine.pc[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[28] <= execute_engine.pc[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[29] <= execute_engine.pc[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[30] <= execute_engine.pc[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
curr_pc_o[31] <= execute_engine.pc[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[0] <= <GND>
|
|
next_pc_o[1] <= execute_engine.next_pc[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[2] <= execute_engine.next_pc[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[3] <= execute_engine.next_pc[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[4] <= execute_engine.next_pc[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[5] <= execute_engine.next_pc[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[6] <= execute_engine.next_pc[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[7] <= execute_engine.next_pc[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[8] <= execute_engine.next_pc[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[9] <= execute_engine.next_pc[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[10] <= execute_engine.next_pc[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[11] <= execute_engine.next_pc[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[12] <= execute_engine.next_pc[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[13] <= execute_engine.next_pc[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[14] <= execute_engine.next_pc[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[15] <= execute_engine.next_pc[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[16] <= execute_engine.next_pc[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[17] <= execute_engine.next_pc[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[18] <= execute_engine.next_pc[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[19] <= execute_engine.next_pc[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[20] <= execute_engine.next_pc[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[21] <= execute_engine.next_pc[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[22] <= execute_engine.next_pc[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[23] <= execute_engine.next_pc[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[24] <= execute_engine.next_pc[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[25] <= execute_engine.next_pc[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[26] <= execute_engine.next_pc[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[27] <= execute_engine.next_pc[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[28] <= execute_engine.next_pc[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[29] <= execute_engine.next_pc[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[30] <= execute_engine.next_pc[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
next_pc_o[31] <= execute_engine.next_pc[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[0] <= csr.rdata[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[1] <= csr.rdata[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[2] <= csr.rdata[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[3] <= csr.rdata[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[4] <= csr.rdata[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[5] <= csr.rdata[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[6] <= csr.rdata[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[7] <= csr.rdata[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[8] <= csr.rdata[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[9] <= csr.rdata[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[10] <= csr.rdata[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[11] <= csr.rdata[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[12] <= csr.rdata[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[13] <= csr.rdata[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[14] <= csr.rdata[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[15] <= csr.rdata[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[16] <= csr.rdata[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[17] <= csr.rdata[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[18] <= csr.rdata[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[19] <= csr.rdata[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[20] <= csr.rdata[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[21] <= csr.rdata[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[22] <= csr.rdata[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[23] <= csr.rdata[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[24] <= csr.rdata[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[25] <= csr.rdata[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[26] <= csr.rdata[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[27] <= csr.rdata[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[28] <= csr.rdata[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[29] <= csr.rdata[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[30] <= csr.rdata[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
csr_rdata_o[31] <= csr.rdata[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
fpu_flags_i[0] => ~NO_FANOUT~
|
|
fpu_flags_i[1] => ~NO_FANOUT~
|
|
fpu_flags_i[2] => ~NO_FANOUT~
|
|
fpu_flags_i[3] => ~NO_FANOUT~
|
|
fpu_flags_i[4] => ~NO_FANOUT~
|
|
db_halt_req_i => ~NO_FANOUT~
|
|
msw_irq_i => trap_ctrl.irq_pnd[0].DATAIN
|
|
mext_irq_i => trap_ctrl.irq_pnd[2].DATAIN
|
|
mtime_irq_i => trap_ctrl.irq_pnd[1].DATAIN
|
|
firq_i[0] => irq_pnd.IN1
|
|
firq_i[1] => irq_pnd.IN1
|
|
firq_i[2] => irq_pnd.IN1
|
|
firq_i[3] => irq_pnd.IN1
|
|
firq_i[4] => irq_pnd.IN1
|
|
firq_i[5] => irq_pnd.IN1
|
|
firq_i[6] => irq_pnd.IN1
|
|
firq_i[7] => irq_pnd.IN1
|
|
firq_i[8] => irq_pnd.IN1
|
|
firq_i[9] => irq_pnd.IN1
|
|
firq_i[10] => irq_pnd.IN1
|
|
firq_i[11] => irq_pnd.IN1
|
|
firq_i[12] => irq_pnd.IN1
|
|
firq_i[13] => irq_pnd.IN1
|
|
firq_i[14] => irq_pnd.IN1
|
|
firq_i[15] => irq_pnd.IN1
|
|
pmp_addr_o[15][0] <= <GND>
|
|
pmp_addr_o[15][1] <= <GND>
|
|
pmp_addr_o[15][2] <= <GND>
|
|
pmp_addr_o[15][3] <= <GND>
|
|
pmp_addr_o[15][4] <= <GND>
|
|
pmp_addr_o[15][5] <= <GND>
|
|
pmp_addr_o[15][6] <= <GND>
|
|
pmp_addr_o[15][7] <= <GND>
|
|
pmp_addr_o[15][8] <= <GND>
|
|
pmp_addr_o[15][9] <= <GND>
|
|
pmp_addr_o[15][10] <= <GND>
|
|
pmp_addr_o[15][11] <= <GND>
|
|
pmp_addr_o[15][12] <= <GND>
|
|
pmp_addr_o[15][13] <= <GND>
|
|
pmp_addr_o[15][14] <= <GND>
|
|
pmp_addr_o[15][15] <= <GND>
|
|
pmp_addr_o[15][16] <= <GND>
|
|
pmp_addr_o[15][17] <= <GND>
|
|
pmp_addr_o[15][18] <= <GND>
|
|
pmp_addr_o[15][19] <= <GND>
|
|
pmp_addr_o[15][20] <= <GND>
|
|
pmp_addr_o[15][21] <= <GND>
|
|
pmp_addr_o[15][22] <= <GND>
|
|
pmp_addr_o[15][23] <= <GND>
|
|
pmp_addr_o[15][24] <= <GND>
|
|
pmp_addr_o[15][25] <= <GND>
|
|
pmp_addr_o[15][26] <= <GND>
|
|
pmp_addr_o[15][27] <= <GND>
|
|
pmp_addr_o[15][28] <= <GND>
|
|
pmp_addr_o[15][29] <= <GND>
|
|
pmp_addr_o[15][30] <= <GND>
|
|
pmp_addr_o[15][31] <= <GND>
|
|
pmp_addr_o[15][32] <= <GND>
|
|
pmp_addr_o[15][33] <= <GND>
|
|
pmp_addr_o[14][0] <= <GND>
|
|
pmp_addr_o[14][1] <= <GND>
|
|
pmp_addr_o[14][2] <= <GND>
|
|
pmp_addr_o[14][3] <= <GND>
|
|
pmp_addr_o[14][4] <= <GND>
|
|
pmp_addr_o[14][5] <= <GND>
|
|
pmp_addr_o[14][6] <= <GND>
|
|
pmp_addr_o[14][7] <= <GND>
|
|
pmp_addr_o[14][8] <= <GND>
|
|
pmp_addr_o[14][9] <= <GND>
|
|
pmp_addr_o[14][10] <= <GND>
|
|
pmp_addr_o[14][11] <= <GND>
|
|
pmp_addr_o[14][12] <= <GND>
|
|
pmp_addr_o[14][13] <= <GND>
|
|
pmp_addr_o[14][14] <= <GND>
|
|
pmp_addr_o[14][15] <= <GND>
|
|
pmp_addr_o[14][16] <= <GND>
|
|
pmp_addr_o[14][17] <= <GND>
|
|
pmp_addr_o[14][18] <= <GND>
|
|
pmp_addr_o[14][19] <= <GND>
|
|
pmp_addr_o[14][20] <= <GND>
|
|
pmp_addr_o[14][21] <= <GND>
|
|
pmp_addr_o[14][22] <= <GND>
|
|
pmp_addr_o[14][23] <= <GND>
|
|
pmp_addr_o[14][24] <= <GND>
|
|
pmp_addr_o[14][25] <= <GND>
|
|
pmp_addr_o[14][26] <= <GND>
|
|
pmp_addr_o[14][27] <= <GND>
|
|
pmp_addr_o[14][28] <= <GND>
|
|
pmp_addr_o[14][29] <= <GND>
|
|
pmp_addr_o[14][30] <= <GND>
|
|
pmp_addr_o[14][31] <= <GND>
|
|
pmp_addr_o[14][32] <= <GND>
|
|
pmp_addr_o[14][33] <= <GND>
|
|
pmp_addr_o[13][0] <= <GND>
|
|
pmp_addr_o[13][1] <= <GND>
|
|
pmp_addr_o[13][2] <= <GND>
|
|
pmp_addr_o[13][3] <= <GND>
|
|
pmp_addr_o[13][4] <= <GND>
|
|
pmp_addr_o[13][5] <= <GND>
|
|
pmp_addr_o[13][6] <= <GND>
|
|
pmp_addr_o[13][7] <= <GND>
|
|
pmp_addr_o[13][8] <= <GND>
|
|
pmp_addr_o[13][9] <= <GND>
|
|
pmp_addr_o[13][10] <= <GND>
|
|
pmp_addr_o[13][11] <= <GND>
|
|
pmp_addr_o[13][12] <= <GND>
|
|
pmp_addr_o[13][13] <= <GND>
|
|
pmp_addr_o[13][14] <= <GND>
|
|
pmp_addr_o[13][15] <= <GND>
|
|
pmp_addr_o[13][16] <= <GND>
|
|
pmp_addr_o[13][17] <= <GND>
|
|
pmp_addr_o[13][18] <= <GND>
|
|
pmp_addr_o[13][19] <= <GND>
|
|
pmp_addr_o[13][20] <= <GND>
|
|
pmp_addr_o[13][21] <= <GND>
|
|
pmp_addr_o[13][22] <= <GND>
|
|
pmp_addr_o[13][23] <= <GND>
|
|
pmp_addr_o[13][24] <= <GND>
|
|
pmp_addr_o[13][25] <= <GND>
|
|
pmp_addr_o[13][26] <= <GND>
|
|
pmp_addr_o[13][27] <= <GND>
|
|
pmp_addr_o[13][28] <= <GND>
|
|
pmp_addr_o[13][29] <= <GND>
|
|
pmp_addr_o[13][30] <= <GND>
|
|
pmp_addr_o[13][31] <= <GND>
|
|
pmp_addr_o[13][32] <= <GND>
|
|
pmp_addr_o[13][33] <= <GND>
|
|
pmp_addr_o[12][0] <= <GND>
|
|
pmp_addr_o[12][1] <= <GND>
|
|
pmp_addr_o[12][2] <= <GND>
|
|
pmp_addr_o[12][3] <= <GND>
|
|
pmp_addr_o[12][4] <= <GND>
|
|
pmp_addr_o[12][5] <= <GND>
|
|
pmp_addr_o[12][6] <= <GND>
|
|
pmp_addr_o[12][7] <= <GND>
|
|
pmp_addr_o[12][8] <= <GND>
|
|
pmp_addr_o[12][9] <= <GND>
|
|
pmp_addr_o[12][10] <= <GND>
|
|
pmp_addr_o[12][11] <= <GND>
|
|
pmp_addr_o[12][12] <= <GND>
|
|
pmp_addr_o[12][13] <= <GND>
|
|
pmp_addr_o[12][14] <= <GND>
|
|
pmp_addr_o[12][15] <= <GND>
|
|
pmp_addr_o[12][16] <= <GND>
|
|
pmp_addr_o[12][17] <= <GND>
|
|
pmp_addr_o[12][18] <= <GND>
|
|
pmp_addr_o[12][19] <= <GND>
|
|
pmp_addr_o[12][20] <= <GND>
|
|
pmp_addr_o[12][21] <= <GND>
|
|
pmp_addr_o[12][22] <= <GND>
|
|
pmp_addr_o[12][23] <= <GND>
|
|
pmp_addr_o[12][24] <= <GND>
|
|
pmp_addr_o[12][25] <= <GND>
|
|
pmp_addr_o[12][26] <= <GND>
|
|
pmp_addr_o[12][27] <= <GND>
|
|
pmp_addr_o[12][28] <= <GND>
|
|
pmp_addr_o[12][29] <= <GND>
|
|
pmp_addr_o[12][30] <= <GND>
|
|
pmp_addr_o[12][31] <= <GND>
|
|
pmp_addr_o[12][32] <= <GND>
|
|
pmp_addr_o[12][33] <= <GND>
|
|
pmp_addr_o[11][0] <= <GND>
|
|
pmp_addr_o[11][1] <= <GND>
|
|
pmp_addr_o[11][2] <= <GND>
|
|
pmp_addr_o[11][3] <= <GND>
|
|
pmp_addr_o[11][4] <= <GND>
|
|
pmp_addr_o[11][5] <= <GND>
|
|
pmp_addr_o[11][6] <= <GND>
|
|
pmp_addr_o[11][7] <= <GND>
|
|
pmp_addr_o[11][8] <= <GND>
|
|
pmp_addr_o[11][9] <= <GND>
|
|
pmp_addr_o[11][10] <= <GND>
|
|
pmp_addr_o[11][11] <= <GND>
|
|
pmp_addr_o[11][12] <= <GND>
|
|
pmp_addr_o[11][13] <= <GND>
|
|
pmp_addr_o[11][14] <= <GND>
|
|
pmp_addr_o[11][15] <= <GND>
|
|
pmp_addr_o[11][16] <= <GND>
|
|
pmp_addr_o[11][17] <= <GND>
|
|
pmp_addr_o[11][18] <= <GND>
|
|
pmp_addr_o[11][19] <= <GND>
|
|
pmp_addr_o[11][20] <= <GND>
|
|
pmp_addr_o[11][21] <= <GND>
|
|
pmp_addr_o[11][22] <= <GND>
|
|
pmp_addr_o[11][23] <= <GND>
|
|
pmp_addr_o[11][24] <= <GND>
|
|
pmp_addr_o[11][25] <= <GND>
|
|
pmp_addr_o[11][26] <= <GND>
|
|
pmp_addr_o[11][27] <= <GND>
|
|
pmp_addr_o[11][28] <= <GND>
|
|
pmp_addr_o[11][29] <= <GND>
|
|
pmp_addr_o[11][30] <= <GND>
|
|
pmp_addr_o[11][31] <= <GND>
|
|
pmp_addr_o[11][32] <= <GND>
|
|
pmp_addr_o[11][33] <= <GND>
|
|
pmp_addr_o[10][0] <= <GND>
|
|
pmp_addr_o[10][1] <= <GND>
|
|
pmp_addr_o[10][2] <= <GND>
|
|
pmp_addr_o[10][3] <= <GND>
|
|
pmp_addr_o[10][4] <= <GND>
|
|
pmp_addr_o[10][5] <= <GND>
|
|
pmp_addr_o[10][6] <= <GND>
|
|
pmp_addr_o[10][7] <= <GND>
|
|
pmp_addr_o[10][8] <= <GND>
|
|
pmp_addr_o[10][9] <= <GND>
|
|
pmp_addr_o[10][10] <= <GND>
|
|
pmp_addr_o[10][11] <= <GND>
|
|
pmp_addr_o[10][12] <= <GND>
|
|
pmp_addr_o[10][13] <= <GND>
|
|
pmp_addr_o[10][14] <= <GND>
|
|
pmp_addr_o[10][15] <= <GND>
|
|
pmp_addr_o[10][16] <= <GND>
|
|
pmp_addr_o[10][17] <= <GND>
|
|
pmp_addr_o[10][18] <= <GND>
|
|
pmp_addr_o[10][19] <= <GND>
|
|
pmp_addr_o[10][20] <= <GND>
|
|
pmp_addr_o[10][21] <= <GND>
|
|
pmp_addr_o[10][22] <= <GND>
|
|
pmp_addr_o[10][23] <= <GND>
|
|
pmp_addr_o[10][24] <= <GND>
|
|
pmp_addr_o[10][25] <= <GND>
|
|
pmp_addr_o[10][26] <= <GND>
|
|
pmp_addr_o[10][27] <= <GND>
|
|
pmp_addr_o[10][28] <= <GND>
|
|
pmp_addr_o[10][29] <= <GND>
|
|
pmp_addr_o[10][30] <= <GND>
|
|
pmp_addr_o[10][31] <= <GND>
|
|
pmp_addr_o[10][32] <= <GND>
|
|
pmp_addr_o[10][33] <= <GND>
|
|
pmp_addr_o[9][0] <= <GND>
|
|
pmp_addr_o[9][1] <= <GND>
|
|
pmp_addr_o[9][2] <= <GND>
|
|
pmp_addr_o[9][3] <= <GND>
|
|
pmp_addr_o[9][4] <= <GND>
|
|
pmp_addr_o[9][5] <= <GND>
|
|
pmp_addr_o[9][6] <= <GND>
|
|
pmp_addr_o[9][7] <= <GND>
|
|
pmp_addr_o[9][8] <= <GND>
|
|
pmp_addr_o[9][9] <= <GND>
|
|
pmp_addr_o[9][10] <= <GND>
|
|
pmp_addr_o[9][11] <= <GND>
|
|
pmp_addr_o[9][12] <= <GND>
|
|
pmp_addr_o[9][13] <= <GND>
|
|
pmp_addr_o[9][14] <= <GND>
|
|
pmp_addr_o[9][15] <= <GND>
|
|
pmp_addr_o[9][16] <= <GND>
|
|
pmp_addr_o[9][17] <= <GND>
|
|
pmp_addr_o[9][18] <= <GND>
|
|
pmp_addr_o[9][19] <= <GND>
|
|
pmp_addr_o[9][20] <= <GND>
|
|
pmp_addr_o[9][21] <= <GND>
|
|
pmp_addr_o[9][22] <= <GND>
|
|
pmp_addr_o[9][23] <= <GND>
|
|
pmp_addr_o[9][24] <= <GND>
|
|
pmp_addr_o[9][25] <= <GND>
|
|
pmp_addr_o[9][26] <= <GND>
|
|
pmp_addr_o[9][27] <= <GND>
|
|
pmp_addr_o[9][28] <= <GND>
|
|
pmp_addr_o[9][29] <= <GND>
|
|
pmp_addr_o[9][30] <= <GND>
|
|
pmp_addr_o[9][31] <= <GND>
|
|
pmp_addr_o[9][32] <= <GND>
|
|
pmp_addr_o[9][33] <= <GND>
|
|
pmp_addr_o[8][0] <= <GND>
|
|
pmp_addr_o[8][1] <= <GND>
|
|
pmp_addr_o[8][2] <= <GND>
|
|
pmp_addr_o[8][3] <= <GND>
|
|
pmp_addr_o[8][4] <= <GND>
|
|
pmp_addr_o[8][5] <= <GND>
|
|
pmp_addr_o[8][6] <= <GND>
|
|
pmp_addr_o[8][7] <= <GND>
|
|
pmp_addr_o[8][8] <= <GND>
|
|
pmp_addr_o[8][9] <= <GND>
|
|
pmp_addr_o[8][10] <= <GND>
|
|
pmp_addr_o[8][11] <= <GND>
|
|
pmp_addr_o[8][12] <= <GND>
|
|
pmp_addr_o[8][13] <= <GND>
|
|
pmp_addr_o[8][14] <= <GND>
|
|
pmp_addr_o[8][15] <= <GND>
|
|
pmp_addr_o[8][16] <= <GND>
|
|
pmp_addr_o[8][17] <= <GND>
|
|
pmp_addr_o[8][18] <= <GND>
|
|
pmp_addr_o[8][19] <= <GND>
|
|
pmp_addr_o[8][20] <= <GND>
|
|
pmp_addr_o[8][21] <= <GND>
|
|
pmp_addr_o[8][22] <= <GND>
|
|
pmp_addr_o[8][23] <= <GND>
|
|
pmp_addr_o[8][24] <= <GND>
|
|
pmp_addr_o[8][25] <= <GND>
|
|
pmp_addr_o[8][26] <= <GND>
|
|
pmp_addr_o[8][27] <= <GND>
|
|
pmp_addr_o[8][28] <= <GND>
|
|
pmp_addr_o[8][29] <= <GND>
|
|
pmp_addr_o[8][30] <= <GND>
|
|
pmp_addr_o[8][31] <= <GND>
|
|
pmp_addr_o[8][32] <= <GND>
|
|
pmp_addr_o[8][33] <= <GND>
|
|
pmp_addr_o[7][0] <= <GND>
|
|
pmp_addr_o[7][1] <= <GND>
|
|
pmp_addr_o[7][2] <= <GND>
|
|
pmp_addr_o[7][3] <= <GND>
|
|
pmp_addr_o[7][4] <= <GND>
|
|
pmp_addr_o[7][5] <= <GND>
|
|
pmp_addr_o[7][6] <= <GND>
|
|
pmp_addr_o[7][7] <= <GND>
|
|
pmp_addr_o[7][8] <= <GND>
|
|
pmp_addr_o[7][9] <= <GND>
|
|
pmp_addr_o[7][10] <= <GND>
|
|
pmp_addr_o[7][11] <= <GND>
|
|
pmp_addr_o[7][12] <= <GND>
|
|
pmp_addr_o[7][13] <= <GND>
|
|
pmp_addr_o[7][14] <= <GND>
|
|
pmp_addr_o[7][15] <= <GND>
|
|
pmp_addr_o[7][16] <= <GND>
|
|
pmp_addr_o[7][17] <= <GND>
|
|
pmp_addr_o[7][18] <= <GND>
|
|
pmp_addr_o[7][19] <= <GND>
|
|
pmp_addr_o[7][20] <= <GND>
|
|
pmp_addr_o[7][21] <= <GND>
|
|
pmp_addr_o[7][22] <= <GND>
|
|
pmp_addr_o[7][23] <= <GND>
|
|
pmp_addr_o[7][24] <= <GND>
|
|
pmp_addr_o[7][25] <= <GND>
|
|
pmp_addr_o[7][26] <= <GND>
|
|
pmp_addr_o[7][27] <= <GND>
|
|
pmp_addr_o[7][28] <= <GND>
|
|
pmp_addr_o[7][29] <= <GND>
|
|
pmp_addr_o[7][30] <= <GND>
|
|
pmp_addr_o[7][31] <= <GND>
|
|
pmp_addr_o[7][32] <= <GND>
|
|
pmp_addr_o[7][33] <= <GND>
|
|
pmp_addr_o[6][0] <= <GND>
|
|
pmp_addr_o[6][1] <= <GND>
|
|
pmp_addr_o[6][2] <= <GND>
|
|
pmp_addr_o[6][3] <= <GND>
|
|
pmp_addr_o[6][4] <= <GND>
|
|
pmp_addr_o[6][5] <= <GND>
|
|
pmp_addr_o[6][6] <= <GND>
|
|
pmp_addr_o[6][7] <= <GND>
|
|
pmp_addr_o[6][8] <= <GND>
|
|
pmp_addr_o[6][9] <= <GND>
|
|
pmp_addr_o[6][10] <= <GND>
|
|
pmp_addr_o[6][11] <= <GND>
|
|
pmp_addr_o[6][12] <= <GND>
|
|
pmp_addr_o[6][13] <= <GND>
|
|
pmp_addr_o[6][14] <= <GND>
|
|
pmp_addr_o[6][15] <= <GND>
|
|
pmp_addr_o[6][16] <= <GND>
|
|
pmp_addr_o[6][17] <= <GND>
|
|
pmp_addr_o[6][18] <= <GND>
|
|
pmp_addr_o[6][19] <= <GND>
|
|
pmp_addr_o[6][20] <= <GND>
|
|
pmp_addr_o[6][21] <= <GND>
|
|
pmp_addr_o[6][22] <= <GND>
|
|
pmp_addr_o[6][23] <= <GND>
|
|
pmp_addr_o[6][24] <= <GND>
|
|
pmp_addr_o[6][25] <= <GND>
|
|
pmp_addr_o[6][26] <= <GND>
|
|
pmp_addr_o[6][27] <= <GND>
|
|
pmp_addr_o[6][28] <= <GND>
|
|
pmp_addr_o[6][29] <= <GND>
|
|
pmp_addr_o[6][30] <= <GND>
|
|
pmp_addr_o[6][31] <= <GND>
|
|
pmp_addr_o[6][32] <= <GND>
|
|
pmp_addr_o[6][33] <= <GND>
|
|
pmp_addr_o[5][0] <= <GND>
|
|
pmp_addr_o[5][1] <= <GND>
|
|
pmp_addr_o[5][2] <= <GND>
|
|
pmp_addr_o[5][3] <= <GND>
|
|
pmp_addr_o[5][4] <= <GND>
|
|
pmp_addr_o[5][5] <= <GND>
|
|
pmp_addr_o[5][6] <= <GND>
|
|
pmp_addr_o[5][7] <= <GND>
|
|
pmp_addr_o[5][8] <= <GND>
|
|
pmp_addr_o[5][9] <= <GND>
|
|
pmp_addr_o[5][10] <= <GND>
|
|
pmp_addr_o[5][11] <= <GND>
|
|
pmp_addr_o[5][12] <= <GND>
|
|
pmp_addr_o[5][13] <= <GND>
|
|
pmp_addr_o[5][14] <= <GND>
|
|
pmp_addr_o[5][15] <= <GND>
|
|
pmp_addr_o[5][16] <= <GND>
|
|
pmp_addr_o[5][17] <= <GND>
|
|
pmp_addr_o[5][18] <= <GND>
|
|
pmp_addr_o[5][19] <= <GND>
|
|
pmp_addr_o[5][20] <= <GND>
|
|
pmp_addr_o[5][21] <= <GND>
|
|
pmp_addr_o[5][22] <= <GND>
|
|
pmp_addr_o[5][23] <= <GND>
|
|
pmp_addr_o[5][24] <= <GND>
|
|
pmp_addr_o[5][25] <= <GND>
|
|
pmp_addr_o[5][26] <= <GND>
|
|
pmp_addr_o[5][27] <= <GND>
|
|
pmp_addr_o[5][28] <= <GND>
|
|
pmp_addr_o[5][29] <= <GND>
|
|
pmp_addr_o[5][30] <= <GND>
|
|
pmp_addr_o[5][31] <= <GND>
|
|
pmp_addr_o[5][32] <= <GND>
|
|
pmp_addr_o[5][33] <= <GND>
|
|
pmp_addr_o[4][0] <= <GND>
|
|
pmp_addr_o[4][1] <= <GND>
|
|
pmp_addr_o[4][2] <= <GND>
|
|
pmp_addr_o[4][3] <= <GND>
|
|
pmp_addr_o[4][4] <= <GND>
|
|
pmp_addr_o[4][5] <= <GND>
|
|
pmp_addr_o[4][6] <= <GND>
|
|
pmp_addr_o[4][7] <= <GND>
|
|
pmp_addr_o[4][8] <= <GND>
|
|
pmp_addr_o[4][9] <= <GND>
|
|
pmp_addr_o[4][10] <= <GND>
|
|
pmp_addr_o[4][11] <= <GND>
|
|
pmp_addr_o[4][12] <= <GND>
|
|
pmp_addr_o[4][13] <= <GND>
|
|
pmp_addr_o[4][14] <= <GND>
|
|
pmp_addr_o[4][15] <= <GND>
|
|
pmp_addr_o[4][16] <= <GND>
|
|
pmp_addr_o[4][17] <= <GND>
|
|
pmp_addr_o[4][18] <= <GND>
|
|
pmp_addr_o[4][19] <= <GND>
|
|
pmp_addr_o[4][20] <= <GND>
|
|
pmp_addr_o[4][21] <= <GND>
|
|
pmp_addr_o[4][22] <= <GND>
|
|
pmp_addr_o[4][23] <= <GND>
|
|
pmp_addr_o[4][24] <= <GND>
|
|
pmp_addr_o[4][25] <= <GND>
|
|
pmp_addr_o[4][26] <= <GND>
|
|
pmp_addr_o[4][27] <= <GND>
|
|
pmp_addr_o[4][28] <= <GND>
|
|
pmp_addr_o[4][29] <= <GND>
|
|
pmp_addr_o[4][30] <= <GND>
|
|
pmp_addr_o[4][31] <= <GND>
|
|
pmp_addr_o[4][32] <= <GND>
|
|
pmp_addr_o[4][33] <= <GND>
|
|
pmp_addr_o[3][0] <= <GND>
|
|
pmp_addr_o[3][1] <= <GND>
|
|
pmp_addr_o[3][2] <= <GND>
|
|
pmp_addr_o[3][3] <= <GND>
|
|
pmp_addr_o[3][4] <= <GND>
|
|
pmp_addr_o[3][5] <= <GND>
|
|
pmp_addr_o[3][6] <= <GND>
|
|
pmp_addr_o[3][7] <= <GND>
|
|
pmp_addr_o[3][8] <= <GND>
|
|
pmp_addr_o[3][9] <= <GND>
|
|
pmp_addr_o[3][10] <= <GND>
|
|
pmp_addr_o[3][11] <= <GND>
|
|
pmp_addr_o[3][12] <= <GND>
|
|
pmp_addr_o[3][13] <= <GND>
|
|
pmp_addr_o[3][14] <= <GND>
|
|
pmp_addr_o[3][15] <= <GND>
|
|
pmp_addr_o[3][16] <= <GND>
|
|
pmp_addr_o[3][17] <= <GND>
|
|
pmp_addr_o[3][18] <= <GND>
|
|
pmp_addr_o[3][19] <= <GND>
|
|
pmp_addr_o[3][20] <= <GND>
|
|
pmp_addr_o[3][21] <= <GND>
|
|
pmp_addr_o[3][22] <= <GND>
|
|
pmp_addr_o[3][23] <= <GND>
|
|
pmp_addr_o[3][24] <= <GND>
|
|
pmp_addr_o[3][25] <= <GND>
|
|
pmp_addr_o[3][26] <= <GND>
|
|
pmp_addr_o[3][27] <= <GND>
|
|
pmp_addr_o[3][28] <= <GND>
|
|
pmp_addr_o[3][29] <= <GND>
|
|
pmp_addr_o[3][30] <= <GND>
|
|
pmp_addr_o[3][31] <= <GND>
|
|
pmp_addr_o[3][32] <= <GND>
|
|
pmp_addr_o[3][33] <= <GND>
|
|
pmp_addr_o[2][0] <= <GND>
|
|
pmp_addr_o[2][1] <= <GND>
|
|
pmp_addr_o[2][2] <= <GND>
|
|
pmp_addr_o[2][3] <= <GND>
|
|
pmp_addr_o[2][4] <= <GND>
|
|
pmp_addr_o[2][5] <= <GND>
|
|
pmp_addr_o[2][6] <= <GND>
|
|
pmp_addr_o[2][7] <= <GND>
|
|
pmp_addr_o[2][8] <= <GND>
|
|
pmp_addr_o[2][9] <= <GND>
|
|
pmp_addr_o[2][10] <= <GND>
|
|
pmp_addr_o[2][11] <= <GND>
|
|
pmp_addr_o[2][12] <= <GND>
|
|
pmp_addr_o[2][13] <= <GND>
|
|
pmp_addr_o[2][14] <= <GND>
|
|
pmp_addr_o[2][15] <= <GND>
|
|
pmp_addr_o[2][16] <= <GND>
|
|
pmp_addr_o[2][17] <= <GND>
|
|
pmp_addr_o[2][18] <= <GND>
|
|
pmp_addr_o[2][19] <= <GND>
|
|
pmp_addr_o[2][20] <= <GND>
|
|
pmp_addr_o[2][21] <= <GND>
|
|
pmp_addr_o[2][22] <= <GND>
|
|
pmp_addr_o[2][23] <= <GND>
|
|
pmp_addr_o[2][24] <= <GND>
|
|
pmp_addr_o[2][25] <= <GND>
|
|
pmp_addr_o[2][26] <= <GND>
|
|
pmp_addr_o[2][27] <= <GND>
|
|
pmp_addr_o[2][28] <= <GND>
|
|
pmp_addr_o[2][29] <= <GND>
|
|
pmp_addr_o[2][30] <= <GND>
|
|
pmp_addr_o[2][31] <= <GND>
|
|
pmp_addr_o[2][32] <= <GND>
|
|
pmp_addr_o[2][33] <= <GND>
|
|
pmp_addr_o[1][0] <= <GND>
|
|
pmp_addr_o[1][1] <= <GND>
|
|
pmp_addr_o[1][2] <= <GND>
|
|
pmp_addr_o[1][3] <= <GND>
|
|
pmp_addr_o[1][4] <= <GND>
|
|
pmp_addr_o[1][5] <= <GND>
|
|
pmp_addr_o[1][6] <= <GND>
|
|
pmp_addr_o[1][7] <= <GND>
|
|
pmp_addr_o[1][8] <= <GND>
|
|
pmp_addr_o[1][9] <= <GND>
|
|
pmp_addr_o[1][10] <= <GND>
|
|
pmp_addr_o[1][11] <= <GND>
|
|
pmp_addr_o[1][12] <= <GND>
|
|
pmp_addr_o[1][13] <= <GND>
|
|
pmp_addr_o[1][14] <= <GND>
|
|
pmp_addr_o[1][15] <= <GND>
|
|
pmp_addr_o[1][16] <= <GND>
|
|
pmp_addr_o[1][17] <= <GND>
|
|
pmp_addr_o[1][18] <= <GND>
|
|
pmp_addr_o[1][19] <= <GND>
|
|
pmp_addr_o[1][20] <= <GND>
|
|
pmp_addr_o[1][21] <= <GND>
|
|
pmp_addr_o[1][22] <= <GND>
|
|
pmp_addr_o[1][23] <= <GND>
|
|
pmp_addr_o[1][24] <= <GND>
|
|
pmp_addr_o[1][25] <= <GND>
|
|
pmp_addr_o[1][26] <= <GND>
|
|
pmp_addr_o[1][27] <= <GND>
|
|
pmp_addr_o[1][28] <= <GND>
|
|
pmp_addr_o[1][29] <= <GND>
|
|
pmp_addr_o[1][30] <= <GND>
|
|
pmp_addr_o[1][31] <= <GND>
|
|
pmp_addr_o[1][32] <= <GND>
|
|
pmp_addr_o[1][33] <= <GND>
|
|
pmp_addr_o[0][0] <= <GND>
|
|
pmp_addr_o[0][1] <= <GND>
|
|
pmp_addr_o[0][2] <= <GND>
|
|
pmp_addr_o[0][3] <= <GND>
|
|
pmp_addr_o[0][4] <= <GND>
|
|
pmp_addr_o[0][5] <= <GND>
|
|
pmp_addr_o[0][6] <= <GND>
|
|
pmp_addr_o[0][7] <= <GND>
|
|
pmp_addr_o[0][8] <= <GND>
|
|
pmp_addr_o[0][9] <= <GND>
|
|
pmp_addr_o[0][10] <= <GND>
|
|
pmp_addr_o[0][11] <= <GND>
|
|
pmp_addr_o[0][12] <= <GND>
|
|
pmp_addr_o[0][13] <= <GND>
|
|
pmp_addr_o[0][14] <= <GND>
|
|
pmp_addr_o[0][15] <= <GND>
|
|
pmp_addr_o[0][16] <= <GND>
|
|
pmp_addr_o[0][17] <= <GND>
|
|
pmp_addr_o[0][18] <= <GND>
|
|
pmp_addr_o[0][19] <= <GND>
|
|
pmp_addr_o[0][20] <= <GND>
|
|
pmp_addr_o[0][21] <= <GND>
|
|
pmp_addr_o[0][22] <= <GND>
|
|
pmp_addr_o[0][23] <= <GND>
|
|
pmp_addr_o[0][24] <= <GND>
|
|
pmp_addr_o[0][25] <= <GND>
|
|
pmp_addr_o[0][26] <= <GND>
|
|
pmp_addr_o[0][27] <= <GND>
|
|
pmp_addr_o[0][28] <= <GND>
|
|
pmp_addr_o[0][29] <= <GND>
|
|
pmp_addr_o[0][30] <= <GND>
|
|
pmp_addr_o[0][31] <= <GND>
|
|
pmp_addr_o[0][32] <= <GND>
|
|
pmp_addr_o[0][33] <= <GND>
|
|
pmp_ctrl_o[15][0] <= <GND>
|
|
pmp_ctrl_o[15][1] <= <GND>
|
|
pmp_ctrl_o[15][2] <= <GND>
|
|
pmp_ctrl_o[15][3] <= <GND>
|
|
pmp_ctrl_o[15][4] <= <GND>
|
|
pmp_ctrl_o[15][5] <= <GND>
|
|
pmp_ctrl_o[15][6] <= <GND>
|
|
pmp_ctrl_o[15][7] <= <GND>
|
|
pmp_ctrl_o[14][0] <= <GND>
|
|
pmp_ctrl_o[14][1] <= <GND>
|
|
pmp_ctrl_o[14][2] <= <GND>
|
|
pmp_ctrl_o[14][3] <= <GND>
|
|
pmp_ctrl_o[14][4] <= <GND>
|
|
pmp_ctrl_o[14][5] <= <GND>
|
|
pmp_ctrl_o[14][6] <= <GND>
|
|
pmp_ctrl_o[14][7] <= <GND>
|
|
pmp_ctrl_o[13][0] <= <GND>
|
|
pmp_ctrl_o[13][1] <= <GND>
|
|
pmp_ctrl_o[13][2] <= <GND>
|
|
pmp_ctrl_o[13][3] <= <GND>
|
|
pmp_ctrl_o[13][4] <= <GND>
|
|
pmp_ctrl_o[13][5] <= <GND>
|
|
pmp_ctrl_o[13][6] <= <GND>
|
|
pmp_ctrl_o[13][7] <= <GND>
|
|
pmp_ctrl_o[12][0] <= <GND>
|
|
pmp_ctrl_o[12][1] <= <GND>
|
|
pmp_ctrl_o[12][2] <= <GND>
|
|
pmp_ctrl_o[12][3] <= <GND>
|
|
pmp_ctrl_o[12][4] <= <GND>
|
|
pmp_ctrl_o[12][5] <= <GND>
|
|
pmp_ctrl_o[12][6] <= <GND>
|
|
pmp_ctrl_o[12][7] <= <GND>
|
|
pmp_ctrl_o[11][0] <= <GND>
|
|
pmp_ctrl_o[11][1] <= <GND>
|
|
pmp_ctrl_o[11][2] <= <GND>
|
|
pmp_ctrl_o[11][3] <= <GND>
|
|
pmp_ctrl_o[11][4] <= <GND>
|
|
pmp_ctrl_o[11][5] <= <GND>
|
|
pmp_ctrl_o[11][6] <= <GND>
|
|
pmp_ctrl_o[11][7] <= <GND>
|
|
pmp_ctrl_o[10][0] <= <GND>
|
|
pmp_ctrl_o[10][1] <= <GND>
|
|
pmp_ctrl_o[10][2] <= <GND>
|
|
pmp_ctrl_o[10][3] <= <GND>
|
|
pmp_ctrl_o[10][4] <= <GND>
|
|
pmp_ctrl_o[10][5] <= <GND>
|
|
pmp_ctrl_o[10][6] <= <GND>
|
|
pmp_ctrl_o[10][7] <= <GND>
|
|
pmp_ctrl_o[9][0] <= <GND>
|
|
pmp_ctrl_o[9][1] <= <GND>
|
|
pmp_ctrl_o[9][2] <= <GND>
|
|
pmp_ctrl_o[9][3] <= <GND>
|
|
pmp_ctrl_o[9][4] <= <GND>
|
|
pmp_ctrl_o[9][5] <= <GND>
|
|
pmp_ctrl_o[9][6] <= <GND>
|
|
pmp_ctrl_o[9][7] <= <GND>
|
|
pmp_ctrl_o[8][0] <= <GND>
|
|
pmp_ctrl_o[8][1] <= <GND>
|
|
pmp_ctrl_o[8][2] <= <GND>
|
|
pmp_ctrl_o[8][3] <= <GND>
|
|
pmp_ctrl_o[8][4] <= <GND>
|
|
pmp_ctrl_o[8][5] <= <GND>
|
|
pmp_ctrl_o[8][6] <= <GND>
|
|
pmp_ctrl_o[8][7] <= <GND>
|
|
pmp_ctrl_o[7][0] <= <GND>
|
|
pmp_ctrl_o[7][1] <= <GND>
|
|
pmp_ctrl_o[7][2] <= <GND>
|
|
pmp_ctrl_o[7][3] <= <GND>
|
|
pmp_ctrl_o[7][4] <= <GND>
|
|
pmp_ctrl_o[7][5] <= <GND>
|
|
pmp_ctrl_o[7][6] <= <GND>
|
|
pmp_ctrl_o[7][7] <= <GND>
|
|
pmp_ctrl_o[6][0] <= <GND>
|
|
pmp_ctrl_o[6][1] <= <GND>
|
|
pmp_ctrl_o[6][2] <= <GND>
|
|
pmp_ctrl_o[6][3] <= <GND>
|
|
pmp_ctrl_o[6][4] <= <GND>
|
|
pmp_ctrl_o[6][5] <= <GND>
|
|
pmp_ctrl_o[6][6] <= <GND>
|
|
pmp_ctrl_o[6][7] <= <GND>
|
|
pmp_ctrl_o[5][0] <= <GND>
|
|
pmp_ctrl_o[5][1] <= <GND>
|
|
pmp_ctrl_o[5][2] <= <GND>
|
|
pmp_ctrl_o[5][3] <= <GND>
|
|
pmp_ctrl_o[5][4] <= <GND>
|
|
pmp_ctrl_o[5][5] <= <GND>
|
|
pmp_ctrl_o[5][6] <= <GND>
|
|
pmp_ctrl_o[5][7] <= <GND>
|
|
pmp_ctrl_o[4][0] <= <GND>
|
|
pmp_ctrl_o[4][1] <= <GND>
|
|
pmp_ctrl_o[4][2] <= <GND>
|
|
pmp_ctrl_o[4][3] <= <GND>
|
|
pmp_ctrl_o[4][4] <= <GND>
|
|
pmp_ctrl_o[4][5] <= <GND>
|
|
pmp_ctrl_o[4][6] <= <GND>
|
|
pmp_ctrl_o[4][7] <= <GND>
|
|
pmp_ctrl_o[3][0] <= <GND>
|
|
pmp_ctrl_o[3][1] <= <GND>
|
|
pmp_ctrl_o[3][2] <= <GND>
|
|
pmp_ctrl_o[3][3] <= <GND>
|
|
pmp_ctrl_o[3][4] <= <GND>
|
|
pmp_ctrl_o[3][5] <= <GND>
|
|
pmp_ctrl_o[3][6] <= <GND>
|
|
pmp_ctrl_o[3][7] <= <GND>
|
|
pmp_ctrl_o[2][0] <= <GND>
|
|
pmp_ctrl_o[2][1] <= <GND>
|
|
pmp_ctrl_o[2][2] <= <GND>
|
|
pmp_ctrl_o[2][3] <= <GND>
|
|
pmp_ctrl_o[2][4] <= <GND>
|
|
pmp_ctrl_o[2][5] <= <GND>
|
|
pmp_ctrl_o[2][6] <= <GND>
|
|
pmp_ctrl_o[2][7] <= <GND>
|
|
pmp_ctrl_o[1][0] <= <GND>
|
|
pmp_ctrl_o[1][1] <= <GND>
|
|
pmp_ctrl_o[1][2] <= <GND>
|
|
pmp_ctrl_o[1][3] <= <GND>
|
|
pmp_ctrl_o[1][4] <= <GND>
|
|
pmp_ctrl_o[1][5] <= <GND>
|
|
pmp_ctrl_o[1][6] <= <GND>
|
|
pmp_ctrl_o[1][7] <= <GND>
|
|
pmp_ctrl_o[0][0] <= <GND>
|
|
pmp_ctrl_o[0][1] <= <GND>
|
|
pmp_ctrl_o[0][2] <= <GND>
|
|
pmp_ctrl_o[0][3] <= <GND>
|
|
pmp_ctrl_o[0][4] <= <GND>
|
|
pmp_ctrl_o[0][5] <= <GND>
|
|
pmp_ctrl_o[0][6] <= <GND>
|
|
pmp_ctrl_o[0][7] <= <GND>
|
|
mar_i[0] => Mux117.IN31
|
|
mar_i[1] => Mux116.IN61
|
|
mar_i[1] => Mux116.IN62
|
|
mar_i[2] => Mux115.IN61
|
|
mar_i[2] => Mux115.IN62
|
|
mar_i[3] => Mux114.IN61
|
|
mar_i[3] => Mux114.IN62
|
|
mar_i[4] => Mux113.IN61
|
|
mar_i[4] => Mux113.IN62
|
|
mar_i[5] => Mux112.IN61
|
|
mar_i[5] => Mux112.IN62
|
|
mar_i[6] => Mux111.IN61
|
|
mar_i[6] => Mux111.IN62
|
|
mar_i[7] => Mux110.IN61
|
|
mar_i[7] => Mux110.IN62
|
|
mar_i[8] => Mux109.IN61
|
|
mar_i[8] => Mux109.IN62
|
|
mar_i[9] => Mux108.IN61
|
|
mar_i[9] => Mux108.IN62
|
|
mar_i[10] => Mux107.IN61
|
|
mar_i[10] => Mux107.IN62
|
|
mar_i[11] => Mux106.IN61
|
|
mar_i[11] => Mux106.IN62
|
|
mar_i[12] => Mux105.IN61
|
|
mar_i[12] => Mux105.IN62
|
|
mar_i[13] => Mux104.IN61
|
|
mar_i[13] => Mux104.IN62
|
|
mar_i[14] => Mux103.IN61
|
|
mar_i[14] => Mux103.IN62
|
|
mar_i[15] => Mux102.IN61
|
|
mar_i[15] => Mux102.IN62
|
|
mar_i[16] => Mux101.IN61
|
|
mar_i[16] => Mux101.IN62
|
|
mar_i[17] => Mux100.IN61
|
|
mar_i[17] => Mux100.IN62
|
|
mar_i[18] => Mux99.IN61
|
|
mar_i[18] => Mux99.IN62
|
|
mar_i[19] => Mux98.IN61
|
|
mar_i[19] => Mux98.IN62
|
|
mar_i[20] => Mux97.IN61
|
|
mar_i[20] => Mux97.IN62
|
|
mar_i[21] => Mux96.IN61
|
|
mar_i[21] => Mux96.IN62
|
|
mar_i[22] => Mux95.IN61
|
|
mar_i[22] => Mux95.IN62
|
|
mar_i[23] => Mux94.IN61
|
|
mar_i[23] => Mux94.IN62
|
|
mar_i[24] => Mux93.IN61
|
|
mar_i[24] => Mux93.IN62
|
|
mar_i[25] => Mux92.IN61
|
|
mar_i[25] => Mux92.IN62
|
|
mar_i[26] => Mux91.IN61
|
|
mar_i[26] => Mux91.IN62
|
|
mar_i[27] => Mux90.IN61
|
|
mar_i[27] => Mux90.IN62
|
|
mar_i[28] => Mux89.IN61
|
|
mar_i[28] => Mux89.IN62
|
|
mar_i[29] => Mux88.IN61
|
|
mar_i[29] => Mux88.IN62
|
|
mar_i[30] => Mux87.IN61
|
|
mar_i[30] => Mux87.IN62
|
|
mar_i[31] => Mux86.IN61
|
|
mar_i[31] => Mux86.IN62
|
|
ma_load_i => exc_buf.IN1
|
|
ma_store_i => exc_buf.IN1
|
|
be_load_i => exc_buf.IN1
|
|
be_store_i => exc_buf.IN1
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst|neorv32_fifo:\prefetch_buffer:0:prefetch_buffer_inst
|
|
clk_i => fifo.data[1][0].CLK
|
|
clk_i => fifo.data[1][1].CLK
|
|
clk_i => fifo.data[1][2].CLK
|
|
clk_i => fifo.data[1][3].CLK
|
|
clk_i => fifo.data[1][4].CLK
|
|
clk_i => fifo.data[1][5].CLK
|
|
clk_i => fifo.data[1][6].CLK
|
|
clk_i => fifo.data[1][7].CLK
|
|
clk_i => fifo.data[1][8].CLK
|
|
clk_i => fifo.data[1][9].CLK
|
|
clk_i => fifo.data[1][10].CLK
|
|
clk_i => fifo.data[1][11].CLK
|
|
clk_i => fifo.data[1][12].CLK
|
|
clk_i => fifo.data[1][13].CLK
|
|
clk_i => fifo.data[1][14].CLK
|
|
clk_i => fifo.data[1][15].CLK
|
|
clk_i => fifo.data[1][16].CLK
|
|
clk_i => fifo.data[1][17].CLK
|
|
clk_i => fifo.data[0][0].CLK
|
|
clk_i => fifo.data[0][1].CLK
|
|
clk_i => fifo.data[0][2].CLK
|
|
clk_i => fifo.data[0][3].CLK
|
|
clk_i => fifo.data[0][4].CLK
|
|
clk_i => fifo.data[0][5].CLK
|
|
clk_i => fifo.data[0][6].CLK
|
|
clk_i => fifo.data[0][7].CLK
|
|
clk_i => fifo.data[0][8].CLK
|
|
clk_i => fifo.data[0][9].CLK
|
|
clk_i => fifo.data[0][10].CLK
|
|
clk_i => fifo.data[0][11].CLK
|
|
clk_i => fifo.data[0][12].CLK
|
|
clk_i => fifo.data[0][13].CLK
|
|
clk_i => fifo.data[0][14].CLK
|
|
clk_i => fifo.data[0][15].CLK
|
|
clk_i => fifo.data[0][16].CLK
|
|
clk_i => fifo.data[0][17].CLK
|
|
clk_i => fifo.r_pnt[0].CLK
|
|
clk_i => fifo.r_pnt[1].CLK
|
|
clk_i => fifo.w_pnt[0].CLK
|
|
clk_i => fifo.w_pnt[1].CLK
|
|
rstn_i => fifo.r_pnt[0].ACLR
|
|
rstn_i => fifo.r_pnt[1].ACLR
|
|
rstn_i => fifo.w_pnt[0].ACLR
|
|
rstn_i => fifo.w_pnt[1].ACLR
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
half_o <= half_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
wdata_i[0] => data.DATAB
|
|
wdata_i[0] => data.DATAB
|
|
wdata_i[1] => data.DATAB
|
|
wdata_i[1] => data.DATAB
|
|
wdata_i[2] => data.DATAB
|
|
wdata_i[2] => data.DATAB
|
|
wdata_i[3] => data.DATAB
|
|
wdata_i[3] => data.DATAB
|
|
wdata_i[4] => data.DATAB
|
|
wdata_i[4] => data.DATAB
|
|
wdata_i[5] => data.DATAB
|
|
wdata_i[5] => data.DATAB
|
|
wdata_i[6] => data.DATAB
|
|
wdata_i[6] => data.DATAB
|
|
wdata_i[7] => data.DATAB
|
|
wdata_i[7] => data.DATAB
|
|
wdata_i[8] => data.DATAB
|
|
wdata_i[8] => data.DATAB
|
|
wdata_i[9] => data.DATAB
|
|
wdata_i[9] => data.DATAB
|
|
wdata_i[10] => data.DATAB
|
|
wdata_i[10] => data.DATAB
|
|
wdata_i[11] => data.DATAB
|
|
wdata_i[11] => data.DATAB
|
|
wdata_i[12] => data.DATAB
|
|
wdata_i[12] => data.DATAB
|
|
wdata_i[13] => data.DATAB
|
|
wdata_i[13] => data.DATAB
|
|
wdata_i[14] => data.DATAB
|
|
wdata_i[14] => data.DATAB
|
|
wdata_i[15] => data.DATAB
|
|
wdata_i[15] => data.DATAB
|
|
wdata_i[16] => data.DATAB
|
|
wdata_i[16] => data.DATAB
|
|
wdata_i[17] => data.DATAB
|
|
wdata_i[17] => data.DATAB
|
|
we_i => fifo.OUTPUTSELECT
|
|
we_i => fifo.OUTPUTSELECT
|
|
we_i => fifo.data[1][3].ENA
|
|
we_i => fifo.data[1][2].ENA
|
|
we_i => fifo.data[1][1].ENA
|
|
we_i => fifo.data[1][0].ENA
|
|
we_i => fifo.data[1][4].ENA
|
|
we_i => fifo.data[1][5].ENA
|
|
we_i => fifo.data[1][6].ENA
|
|
we_i => fifo.data[1][7].ENA
|
|
we_i => fifo.data[1][8].ENA
|
|
we_i => fifo.data[1][9].ENA
|
|
we_i => fifo.data[1][10].ENA
|
|
we_i => fifo.data[1][11].ENA
|
|
we_i => fifo.data[1][12].ENA
|
|
we_i => fifo.data[1][13].ENA
|
|
we_i => fifo.data[1][14].ENA
|
|
we_i => fifo.data[1][15].ENA
|
|
we_i => fifo.data[1][16].ENA
|
|
we_i => fifo.data[1][17].ENA
|
|
we_i => fifo.data[0][0].ENA
|
|
we_i => fifo.data[0][1].ENA
|
|
we_i => fifo.data[0][2].ENA
|
|
we_i => fifo.data[0][3].ENA
|
|
we_i => fifo.data[0][4].ENA
|
|
we_i => fifo.data[0][5].ENA
|
|
we_i => fifo.data[0][6].ENA
|
|
we_i => fifo.data[0][7].ENA
|
|
we_i => fifo.data[0][8].ENA
|
|
we_i => fifo.data[0][9].ENA
|
|
we_i => fifo.data[0][10].ENA
|
|
we_i => fifo.data[0][11].ENA
|
|
we_i => fifo.data[0][12].ENA
|
|
we_i => fifo.data[0][13].ENA
|
|
we_i => fifo.data[0][14].ENA
|
|
we_i => fifo.data[0][15].ENA
|
|
we_i => fifo.data[0][16].ENA
|
|
we_i => fifo.data[0][17].ENA
|
|
free_o <= fifo.full.DB_MAX_OUTPUT_PORT_TYPE
|
|
re_i => fifo.OUTPUTSELECT
|
|
re_i => fifo.OUTPUTSELECT
|
|
rdata_o[0] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[1] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[2] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[3] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[4] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[5] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[6] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[7] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[8] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[9] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[10] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[11] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[12] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[13] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[14] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[15] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[16] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[17] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
avail_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst|neorv32_fifo:\prefetch_buffer:1:prefetch_buffer_inst
|
|
clk_i => fifo.data[1][0].CLK
|
|
clk_i => fifo.data[1][1].CLK
|
|
clk_i => fifo.data[1][2].CLK
|
|
clk_i => fifo.data[1][3].CLK
|
|
clk_i => fifo.data[1][4].CLK
|
|
clk_i => fifo.data[1][5].CLK
|
|
clk_i => fifo.data[1][6].CLK
|
|
clk_i => fifo.data[1][7].CLK
|
|
clk_i => fifo.data[1][8].CLK
|
|
clk_i => fifo.data[1][9].CLK
|
|
clk_i => fifo.data[1][10].CLK
|
|
clk_i => fifo.data[1][11].CLK
|
|
clk_i => fifo.data[1][12].CLK
|
|
clk_i => fifo.data[1][13].CLK
|
|
clk_i => fifo.data[1][14].CLK
|
|
clk_i => fifo.data[1][15].CLK
|
|
clk_i => fifo.data[1][16].CLK
|
|
clk_i => fifo.data[1][17].CLK
|
|
clk_i => fifo.data[0][0].CLK
|
|
clk_i => fifo.data[0][1].CLK
|
|
clk_i => fifo.data[0][2].CLK
|
|
clk_i => fifo.data[0][3].CLK
|
|
clk_i => fifo.data[0][4].CLK
|
|
clk_i => fifo.data[0][5].CLK
|
|
clk_i => fifo.data[0][6].CLK
|
|
clk_i => fifo.data[0][7].CLK
|
|
clk_i => fifo.data[0][8].CLK
|
|
clk_i => fifo.data[0][9].CLK
|
|
clk_i => fifo.data[0][10].CLK
|
|
clk_i => fifo.data[0][11].CLK
|
|
clk_i => fifo.data[0][12].CLK
|
|
clk_i => fifo.data[0][13].CLK
|
|
clk_i => fifo.data[0][14].CLK
|
|
clk_i => fifo.data[0][15].CLK
|
|
clk_i => fifo.data[0][16].CLK
|
|
clk_i => fifo.data[0][17].CLK
|
|
clk_i => fifo.r_pnt[0].CLK
|
|
clk_i => fifo.r_pnt[1].CLK
|
|
clk_i => fifo.w_pnt[0].CLK
|
|
clk_i => fifo.w_pnt[1].CLK
|
|
rstn_i => fifo.r_pnt[0].ACLR
|
|
rstn_i => fifo.r_pnt[1].ACLR
|
|
rstn_i => fifo.w_pnt[0].ACLR
|
|
rstn_i => fifo.w_pnt[1].ACLR
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
half_o <= half_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
wdata_i[0] => data.DATAB
|
|
wdata_i[0] => data.DATAB
|
|
wdata_i[1] => data.DATAB
|
|
wdata_i[1] => data.DATAB
|
|
wdata_i[2] => data.DATAB
|
|
wdata_i[2] => data.DATAB
|
|
wdata_i[3] => data.DATAB
|
|
wdata_i[3] => data.DATAB
|
|
wdata_i[4] => data.DATAB
|
|
wdata_i[4] => data.DATAB
|
|
wdata_i[5] => data.DATAB
|
|
wdata_i[5] => data.DATAB
|
|
wdata_i[6] => data.DATAB
|
|
wdata_i[6] => data.DATAB
|
|
wdata_i[7] => data.DATAB
|
|
wdata_i[7] => data.DATAB
|
|
wdata_i[8] => data.DATAB
|
|
wdata_i[8] => data.DATAB
|
|
wdata_i[9] => data.DATAB
|
|
wdata_i[9] => data.DATAB
|
|
wdata_i[10] => data.DATAB
|
|
wdata_i[10] => data.DATAB
|
|
wdata_i[11] => data.DATAB
|
|
wdata_i[11] => data.DATAB
|
|
wdata_i[12] => data.DATAB
|
|
wdata_i[12] => data.DATAB
|
|
wdata_i[13] => data.DATAB
|
|
wdata_i[13] => data.DATAB
|
|
wdata_i[14] => data.DATAB
|
|
wdata_i[14] => data.DATAB
|
|
wdata_i[15] => data.DATAB
|
|
wdata_i[15] => data.DATAB
|
|
wdata_i[16] => data.DATAB
|
|
wdata_i[16] => data.DATAB
|
|
wdata_i[17] => data.DATAB
|
|
wdata_i[17] => data.DATAB
|
|
we_i => fifo.OUTPUTSELECT
|
|
we_i => fifo.OUTPUTSELECT
|
|
we_i => fifo.data[1][3].ENA
|
|
we_i => fifo.data[1][2].ENA
|
|
we_i => fifo.data[1][1].ENA
|
|
we_i => fifo.data[1][0].ENA
|
|
we_i => fifo.data[1][4].ENA
|
|
we_i => fifo.data[1][5].ENA
|
|
we_i => fifo.data[1][6].ENA
|
|
we_i => fifo.data[1][7].ENA
|
|
we_i => fifo.data[1][8].ENA
|
|
we_i => fifo.data[1][9].ENA
|
|
we_i => fifo.data[1][10].ENA
|
|
we_i => fifo.data[1][11].ENA
|
|
we_i => fifo.data[1][12].ENA
|
|
we_i => fifo.data[1][13].ENA
|
|
we_i => fifo.data[1][14].ENA
|
|
we_i => fifo.data[1][15].ENA
|
|
we_i => fifo.data[1][16].ENA
|
|
we_i => fifo.data[1][17].ENA
|
|
we_i => fifo.data[0][0].ENA
|
|
we_i => fifo.data[0][1].ENA
|
|
we_i => fifo.data[0][2].ENA
|
|
we_i => fifo.data[0][3].ENA
|
|
we_i => fifo.data[0][4].ENA
|
|
we_i => fifo.data[0][5].ENA
|
|
we_i => fifo.data[0][6].ENA
|
|
we_i => fifo.data[0][7].ENA
|
|
we_i => fifo.data[0][8].ENA
|
|
we_i => fifo.data[0][9].ENA
|
|
we_i => fifo.data[0][10].ENA
|
|
we_i => fifo.data[0][11].ENA
|
|
we_i => fifo.data[0][12].ENA
|
|
we_i => fifo.data[0][13].ENA
|
|
we_i => fifo.data[0][14].ENA
|
|
we_i => fifo.data[0][15].ENA
|
|
we_i => fifo.data[0][16].ENA
|
|
we_i => fifo.data[0][17].ENA
|
|
free_o <= fifo.full.DB_MAX_OUTPUT_PORT_TYPE
|
|
re_i => fifo.OUTPUTSELECT
|
|
re_i => fifo.OUTPUTSELECT
|
|
rdata_o[0] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[1] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[2] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[3] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[4] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[5] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[6] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[7] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[8] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[9] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[10] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[11] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[12] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[13] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[14] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[15] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[16] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[17] <= rdata.DB_MAX_OUTPUT_PORT_TYPE
|
|
avail_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_control:neorv32_cpu_control_inst|neorv32_cpu_decompressor:\neorv32_cpu_decompressor_inst_true:neorv32_cpu_decompressor_inst
|
|
ci_instr16_i[0] => Mux76.IN5
|
|
ci_instr16_i[0] => Mux77.IN5
|
|
ci_instr16_i[0] => Mux78.IN5
|
|
ci_instr16_i[0] => Mux79.IN5
|
|
ci_instr16_i[0] => Mux80.IN5
|
|
ci_instr16_i[0] => Mux81.IN5
|
|
ci_instr16_i[0] => Mux82.IN5
|
|
ci_instr16_i[0] => Mux83.IN5
|
|
ci_instr16_i[0] => Mux84.IN5
|
|
ci_instr16_i[0] => Mux85.IN5
|
|
ci_instr16_i[0] => Mux86.IN5
|
|
ci_instr16_i[0] => Mux87.IN5
|
|
ci_instr16_i[0] => Mux88.IN5
|
|
ci_instr16_i[0] => Mux89.IN5
|
|
ci_instr16_i[0] => Mux90.IN5
|
|
ci_instr16_i[0] => Mux91.IN5
|
|
ci_instr16_i[0] => Mux92.IN5
|
|
ci_instr16_i[0] => Mux93.IN5
|
|
ci_instr16_i[0] => Mux94.IN5
|
|
ci_instr16_i[0] => Mux95.IN5
|
|
ci_instr16_i[0] => Mux96.IN5
|
|
ci_instr16_i[0] => Mux97.IN5
|
|
ci_instr16_i[0] => Mux98.IN5
|
|
ci_instr16_i[0] => Mux99.IN5
|
|
ci_instr16_i[0] => Mux100.IN5
|
|
ci_instr16_i[0] => Mux101.IN5
|
|
ci_instr16_i[0] => Mux102.IN5
|
|
ci_instr16_i[0] => Mux103.IN5
|
|
ci_instr16_i[0] => Mux104.IN5
|
|
ci_instr16_i[0] => Mux105.IN5
|
|
ci_instr16_i[0] => Mux106.IN5
|
|
ci_instr16_i[1] => Mux76.IN4
|
|
ci_instr16_i[1] => Mux77.IN4
|
|
ci_instr16_i[1] => Mux78.IN4
|
|
ci_instr16_i[1] => Mux79.IN4
|
|
ci_instr16_i[1] => Mux80.IN4
|
|
ci_instr16_i[1] => Mux81.IN4
|
|
ci_instr16_i[1] => Mux82.IN4
|
|
ci_instr16_i[1] => Mux83.IN4
|
|
ci_instr16_i[1] => Mux84.IN4
|
|
ci_instr16_i[1] => Mux85.IN4
|
|
ci_instr16_i[1] => Mux86.IN4
|
|
ci_instr16_i[1] => Mux87.IN4
|
|
ci_instr16_i[1] => Mux88.IN4
|
|
ci_instr16_i[1] => Mux89.IN4
|
|
ci_instr16_i[1] => Mux90.IN4
|
|
ci_instr16_i[1] => Mux91.IN4
|
|
ci_instr16_i[1] => Mux92.IN4
|
|
ci_instr16_i[1] => Mux93.IN4
|
|
ci_instr16_i[1] => Mux94.IN4
|
|
ci_instr16_i[1] => Mux95.IN4
|
|
ci_instr16_i[1] => Mux96.IN4
|
|
ci_instr16_i[1] => Mux97.IN4
|
|
ci_instr16_i[1] => Mux98.IN4
|
|
ci_instr16_i[1] => Mux99.IN4
|
|
ci_instr16_i[1] => Mux100.IN4
|
|
ci_instr16_i[1] => Mux101.IN4
|
|
ci_instr16_i[1] => Mux102.IN4
|
|
ci_instr16_i[1] => Mux103.IN4
|
|
ci_instr16_i[1] => Mux104.IN4
|
|
ci_instr16_i[1] => Mux105.IN4
|
|
ci_instr16_i[1] => Mux106.IN4
|
|
ci_instr16_i[2] => Mux4.IN5
|
|
ci_instr16_i[2] => Mux9.IN3
|
|
ci_instr16_i[2] => Mux9.IN4
|
|
ci_instr16_i[2] => Mux9.IN5
|
|
ci_instr16_i[2] => ci_instr32_o.DATAB
|
|
ci_instr16_i[2] => ci_instr32_o.DATAA
|
|
ci_instr16_i[2] => Mux28.IN7
|
|
ci_instr16_i[2] => Mux28.IN8
|
|
ci_instr16_i[2] => Mux28.IN9
|
|
ci_instr16_i[2] => Mux28.IN10
|
|
ci_instr16_i[2] => Mux33.IN8
|
|
ci_instr16_i[2] => Mux33.IN9
|
|
ci_instr16_i[2] => Mux33.IN10
|
|
ci_instr16_i[2] => ci_instr32_o.DATAA
|
|
ci_instr16_i[2] => ci_instr32_o.DATAA
|
|
ci_instr16_i[2] => Mux54.IN5
|
|
ci_instr16_i[2] => Mux59.IN8
|
|
ci_instr16_i[2] => Mux59.IN9
|
|
ci_instr16_i[2] => Mux59.IN10
|
|
ci_instr16_i[2] => Equal3.IN4
|
|
ci_instr16_i[3] => Mux3.IN5
|
|
ci_instr16_i[3] => Mux8.IN3
|
|
ci_instr16_i[3] => Mux8.IN4
|
|
ci_instr16_i[3] => Mux8.IN5
|
|
ci_instr16_i[3] => ci_instr32_o.DATAB
|
|
ci_instr16_i[3] => ci_instr32_o.DATAA
|
|
ci_instr16_i[3] => Mux32.IN6
|
|
ci_instr16_i[3] => Mux32.IN7
|
|
ci_instr16_i[3] => Mux32.IN8
|
|
ci_instr16_i[3] => Mux32.IN9
|
|
ci_instr16_i[3] => Mux32.IN10
|
|
ci_instr16_i[3] => Mux45.IN9
|
|
ci_instr16_i[3] => Mux45.IN10
|
|
ci_instr16_i[3] => ci_instr32_o.DATAA
|
|
ci_instr16_i[3] => Mux53.IN5
|
|
ci_instr16_i[3] => Mux58.IN8
|
|
ci_instr16_i[3] => Mux58.IN9
|
|
ci_instr16_i[3] => Mux58.IN10
|
|
ci_instr16_i[3] => Equal3.IN3
|
|
ci_instr16_i[4] => Mux2.IN5
|
|
ci_instr16_i[4] => Mux7.IN3
|
|
ci_instr16_i[4] => Mux7.IN4
|
|
ci_instr16_i[4] => Mux7.IN5
|
|
ci_instr16_i[4] => ci_instr32_o.DATAB
|
|
ci_instr16_i[4] => ci_instr32_o.DATAA
|
|
ci_instr16_i[4] => Mux31.IN6
|
|
ci_instr16_i[4] => Mux31.IN7
|
|
ci_instr16_i[4] => Mux31.IN8
|
|
ci_instr16_i[4] => Mux31.IN9
|
|
ci_instr16_i[4] => Mux31.IN10
|
|
ci_instr16_i[4] => Mux44.IN9
|
|
ci_instr16_i[4] => Mux44.IN10
|
|
ci_instr16_i[4] => ci_instr32_o.DATAA
|
|
ci_instr16_i[4] => Mux57.IN6
|
|
ci_instr16_i[4] => Mux57.IN7
|
|
ci_instr16_i[4] => Mux57.IN8
|
|
ci_instr16_i[4] => Mux57.IN9
|
|
ci_instr16_i[4] => Mux57.IN10
|
|
ci_instr16_i[4] => Equal3.IN2
|
|
ci_instr16_i[5] => ci_instr32_o.DATAB
|
|
ci_instr16_i[5] => Mux1.IN4
|
|
ci_instr16_i[5] => Mux1.IN5
|
|
ci_instr16_i[5] => ci_instr32_o.DATAB
|
|
ci_instr16_i[5] => ci_instr32_o.DATAA
|
|
ci_instr16_i[5] => Mux11.IN5
|
|
ci_instr16_i[5] => Mux12.IN5
|
|
ci_instr16_i[5] => Mux13.IN5
|
|
ci_instr16_i[5] => Mux17.IN3
|
|
ci_instr16_i[5] => Mux17.IN4
|
|
ci_instr16_i[5] => Mux17.IN5
|
|
ci_instr16_i[5] => Mux27.IN9
|
|
ci_instr16_i[5] => Mux27.IN10
|
|
ci_instr16_i[5] => Mux30.IN7
|
|
ci_instr16_i[5] => Mux30.IN8
|
|
ci_instr16_i[5] => Mux30.IN9
|
|
ci_instr16_i[5] => Mux30.IN10
|
|
ci_instr16_i[5] => ci_instr32_o.DATAA
|
|
ci_instr16_i[5] => Mux56.IN6
|
|
ci_instr16_i[5] => Mux56.IN7
|
|
ci_instr16_i[5] => Mux56.IN8
|
|
ci_instr16_i[5] => Mux56.IN9
|
|
ci_instr16_i[5] => Mux56.IN10
|
|
ci_instr16_i[5] => Equal0.IN7
|
|
ci_instr16_i[5] => Equal3.IN1
|
|
ci_instr16_i[6] => Mux2.IN2
|
|
ci_instr16_i[6] => Mux2.IN3
|
|
ci_instr16_i[6] => Mux2.IN4
|
|
ci_instr16_i[6] => Mux7.IN2
|
|
ci_instr16_i[6] => ci_instr32_o.DATAB
|
|
ci_instr16_i[6] => ci_instr32_o.DATAA
|
|
ci_instr16_i[6] => Mux11.IN4
|
|
ci_instr16_i[6] => Mux12.IN4
|
|
ci_instr16_i[6] => Mux13.IN4
|
|
ci_instr16_i[6] => Mux16.IN3
|
|
ci_instr16_i[6] => Mux16.IN4
|
|
ci_instr16_i[6] => Mux16.IN5
|
|
ci_instr16_i[6] => Mux19.IN5
|
|
ci_instr16_i[6] => Mux26.IN7
|
|
ci_instr16_i[6] => Mux26.IN8
|
|
ci_instr16_i[6] => Mux26.IN9
|
|
ci_instr16_i[6] => Mux26.IN10
|
|
ci_instr16_i[6] => Mux29.IN9
|
|
ci_instr16_i[6] => Mux29.IN10
|
|
ci_instr16_i[6] => ci_instr32_o.DATAA
|
|
ci_instr16_i[6] => Mux55.IN6
|
|
ci_instr16_i[6] => Mux55.IN7
|
|
ci_instr16_i[6] => Mux55.IN8
|
|
ci_instr16_i[6] => Mux55.IN9
|
|
ci_instr16_i[6] => Mux55.IN10
|
|
ci_instr16_i[6] => Equal0.IN6
|
|
ci_instr16_i[6] => Equal3.IN0
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => ci_instr32_o.DATAB
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => Mux27.IN7
|
|
ci_instr16_i[7] => Mux27.IN8
|
|
ci_instr16_i[7] => Mux38.IN7
|
|
ci_instr16_i[7] => Mux38.IN8
|
|
ci_instr16_i[7] => Mux38.IN9
|
|
ci_instr16_i[7] => Mux38.IN10
|
|
ci_instr16_i[7] => Mux46.IN8
|
|
ci_instr16_i[7] => Mux46.IN9
|
|
ci_instr16_i[7] => Mux46.IN10
|
|
ci_instr16_i[7] => ci_instr32_o.DATAB
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => ci_instr32_o.DATAA
|
|
ci_instr16_i[7] => Mux54.IN4
|
|
ci_instr16_i[7] => Mux64.IN10
|
|
ci_instr16_i[7] => Mux70.IN8
|
|
ci_instr16_i[7] => Mux70.IN9
|
|
ci_instr16_i[7] => Mux70.IN10
|
|
ci_instr16_i[7] => Equal0.IN5
|
|
ci_instr16_i[7] => Equal2.IN3
|
|
ci_instr16_i[7] => Equal4.IN4
|
|
ci_instr16_i[8] => ci_instr32_o.DATAA
|
|
ci_instr16_i[8] => ci_instr32_o.DATAB
|
|
ci_instr16_i[8] => ci_instr32_o.DATAA
|
|
ci_instr16_i[8] => Mux23.IN9
|
|
ci_instr16_i[8] => Mux23.IN10
|
|
ci_instr16_i[8] => Mux37.IN7
|
|
ci_instr16_i[8] => Mux37.IN8
|
|
ci_instr16_i[8] => Mux37.IN9
|
|
ci_instr16_i[8] => Mux37.IN10
|
|
ci_instr16_i[8] => Mux45.IN6
|
|
ci_instr16_i[8] => Mux45.IN7
|
|
ci_instr16_i[8] => Mux45.IN8
|
|
ci_instr16_i[8] => ci_instr32_o.DATAB
|
|
ci_instr16_i[8] => ci_instr32_o.DATAA
|
|
ci_instr16_i[8] => ci_instr32_o.DATAA
|
|
ci_instr16_i[8] => ci_instr32_o.DATAA
|
|
ci_instr16_i[8] => Mux53.IN4
|
|
ci_instr16_i[8] => Mux63.IN10
|
|
ci_instr16_i[8] => Mux69.IN8
|
|
ci_instr16_i[8] => Mux69.IN9
|
|
ci_instr16_i[8] => Mux69.IN10
|
|
ci_instr16_i[8] => Equal0.IN4
|
|
ci_instr16_i[8] => Equal2.IN4
|
|
ci_instr16_i[8] => Equal4.IN3
|
|
ci_instr16_i[9] => ci_instr32_o.DATAA
|
|
ci_instr16_i[9] => ci_instr32_o.DATAB
|
|
ci_instr16_i[9] => ci_instr32_o.DATAA
|
|
ci_instr16_i[9] => Mux25.IN9
|
|
ci_instr16_i[9] => Mux25.IN10
|
|
ci_instr16_i[9] => Mux36.IN7
|
|
ci_instr16_i[9] => Mux36.IN8
|
|
ci_instr16_i[9] => Mux36.IN9
|
|
ci_instr16_i[9] => Mux36.IN10
|
|
ci_instr16_i[9] => Mux44.IN6
|
|
ci_instr16_i[9] => Mux44.IN7
|
|
ci_instr16_i[9] => Mux44.IN8
|
|
ci_instr16_i[9] => ci_instr32_o.DATAB
|
|
ci_instr16_i[9] => ci_instr32_o.DATAA
|
|
ci_instr16_i[9] => ci_instr32_o.DATAA
|
|
ci_instr16_i[9] => ci_instr32_o.DATAA
|
|
ci_instr16_i[9] => Mux62.IN10
|
|
ci_instr16_i[9] => Mux68.IN6
|
|
ci_instr16_i[9] => Mux68.IN7
|
|
ci_instr16_i[9] => Mux68.IN8
|
|
ci_instr16_i[9] => Mux68.IN9
|
|
ci_instr16_i[9] => Mux68.IN10
|
|
ci_instr16_i[9] => Equal0.IN3
|
|
ci_instr16_i[9] => Equal2.IN2
|
|
ci_instr16_i[9] => Equal4.IN2
|
|
ci_instr16_i[10] => ci_instr32_o.DATAA
|
|
ci_instr16_i[10] => Mux1.IN3
|
|
ci_instr16_i[10] => Mux6.IN5
|
|
ci_instr16_i[10] => ci_instr32_o.DATAA
|
|
ci_instr16_i[10] => Mux14.IN5
|
|
ci_instr16_i[10] => Mux15.IN3
|
|
ci_instr16_i[10] => Mux15.IN4
|
|
ci_instr16_i[10] => Mux15.IN5
|
|
ci_instr16_i[10] => Mux16.IN2
|
|
ci_instr16_i[10] => Mux17.IN2
|
|
ci_instr16_i[10] => Mux18.IN5
|
|
ci_instr16_i[10] => Mux19.IN4
|
|
ci_instr16_i[10] => Mux20.IN5
|
|
ci_instr16_i[10] => Mux21.IN5
|
|
ci_instr16_i[10] => Mux24.IN9
|
|
ci_instr16_i[10] => Mux24.IN10
|
|
ci_instr16_i[10] => Mux35.IN10
|
|
ci_instr16_i[10] => Mux43.IN7
|
|
ci_instr16_i[10] => Mux43.IN8
|
|
ci_instr16_i[10] => Mux43.IN9
|
|
ci_instr16_i[10] => Mux43.IN10
|
|
ci_instr16_i[10] => ci_instr32_o.DATAB
|
|
ci_instr16_i[10] => ci_instr32_o.DATAA
|
|
ci_instr16_i[10] => ci_instr32_o.DATAA
|
|
ci_instr16_i[10] => ci_instr32_o.DATAA
|
|
ci_instr16_i[10] => Mux61.IN10
|
|
ci_instr16_i[10] => Mux67.IN6
|
|
ci_instr16_i[10] => Mux67.IN7
|
|
ci_instr16_i[10] => Mux67.IN8
|
|
ci_instr16_i[10] => Mux67.IN9
|
|
ci_instr16_i[10] => Mux67.IN10
|
|
ci_instr16_i[10] => Equal0.IN2
|
|
ci_instr16_i[10] => Equal2.IN1
|
|
ci_instr16_i[10] => Equal4.IN1
|
|
ci_instr16_i[11] => Mux0.IN3
|
|
ci_instr16_i[11] => Mux0.IN4
|
|
ci_instr16_i[11] => Mux0.IN5
|
|
ci_instr16_i[11] => Mux5.IN5
|
|
ci_instr16_i[11] => ci_instr32_o.DATAA
|
|
ci_instr16_i[11] => Mux14.IN4
|
|
ci_instr16_i[11] => Mux15.IN2
|
|
ci_instr16_i[11] => Mux16.IN1
|
|
ci_instr16_i[11] => Mux17.IN1
|
|
ci_instr16_i[11] => Mux18.IN4
|
|
ci_instr16_i[11] => Mux19.IN3
|
|
ci_instr16_i[11] => Mux20.IN4
|
|
ci_instr16_i[11] => Mux21.IN4
|
|
ci_instr16_i[11] => ci_illegal_o.OUTPUTSELECT
|
|
ci_instr16_i[11] => Mux29.IN7
|
|
ci_instr16_i[11] => Mux29.IN8
|
|
ci_instr16_i[11] => Mux34.IN10
|
|
ci_instr16_i[11] => Mux42.IN7
|
|
ci_instr16_i[11] => Mux42.IN8
|
|
ci_instr16_i[11] => Mux42.IN9
|
|
ci_instr16_i[11] => Mux42.IN10
|
|
ci_instr16_i[11] => ci_instr32_o.DATAB
|
|
ci_instr16_i[11] => ci_instr32_o.DATAA
|
|
ci_instr16_i[11] => ci_instr32_o.DATAA
|
|
ci_instr16_i[11] => ci_instr32_o.DATAA
|
|
ci_instr16_i[11] => Mux60.IN10
|
|
ci_instr16_i[11] => Mux66.IN6
|
|
ci_instr16_i[11] => Mux66.IN7
|
|
ci_instr16_i[11] => Mux66.IN8
|
|
ci_instr16_i[11] => Mux66.IN9
|
|
ci_instr16_i[11] => Mux66.IN10
|
|
ci_instr16_i[11] => Equal0.IN1
|
|
ci_instr16_i[11] => Equal2.IN0
|
|
ci_instr16_i[11] => Equal4.IN0
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => ci_instr32_o.DATAA
|
|
ci_instr16_i[12] => Mux14.IN3
|
|
ci_instr16_i[12] => Mux15.IN1
|
|
ci_instr16_i[12] => ci_illegal_o.DATAA
|
|
ci_instr16_i[12] => Mux22.IN4
|
|
ci_instr16_i[12] => Mux22.IN5
|
|
ci_instr16_i[12] => Mux22.IN6
|
|
ci_instr16_i[12] => Mux22.IN7
|
|
ci_instr16_i[12] => Mux22.IN8
|
|
ci_instr16_i[12] => Mux22.IN9
|
|
ci_instr16_i[12] => Mux22.IN10
|
|
ci_instr16_i[12] => Mux23.IN4
|
|
ci_instr16_i[12] => Mux23.IN5
|
|
ci_instr16_i[12] => Mux23.IN6
|
|
ci_instr16_i[12] => Mux23.IN7
|
|
ci_instr16_i[12] => Mux23.IN8
|
|
ci_instr16_i[12] => Mux24.IN4
|
|
ci_instr16_i[12] => Mux24.IN5
|
|
ci_instr16_i[12] => Mux24.IN6
|
|
ci_instr16_i[12] => Mux24.IN7
|
|
ci_instr16_i[12] => Mux24.IN8
|
|
ci_instr16_i[12] => Mux25.IN5
|
|
ci_instr16_i[12] => Mux25.IN6
|
|
ci_instr16_i[12] => Mux25.IN7
|
|
ci_instr16_i[12] => Mux25.IN8
|
|
ci_instr16_i[12] => Mux26.IN5
|
|
ci_instr16_i[12] => Mux26.IN6
|
|
ci_instr16_i[12] => Mux27.IN5
|
|
ci_instr16_i[12] => Mux27.IN6
|
|
ci_instr16_i[12] => Mux28.IN5
|
|
ci_instr16_i[12] => Mux28.IN6
|
|
ci_instr16_i[12] => Mux33.IN6
|
|
ci_instr16_i[12] => Mux33.IN7
|
|
ci_instr16_i[12] => Mux34.IN8
|
|
ci_instr16_i[12] => Mux34.IN9
|
|
ci_instr16_i[12] => Mux35.IN8
|
|
ci_instr16_i[12] => Mux35.IN9
|
|
ci_instr16_i[12] => Mux36.IN5
|
|
ci_instr16_i[12] => Mux36.IN6
|
|
ci_instr16_i[12] => Mux37.IN5
|
|
ci_instr16_i[12] => Mux37.IN6
|
|
ci_instr16_i[12] => Mux38.IN5
|
|
ci_instr16_i[12] => Mux38.IN6
|
|
ci_instr16_i[12] => Mux39.IN9
|
|
ci_instr16_i[12] => Mux39.IN10
|
|
ci_instr16_i[12] => Mux40.IN9
|
|
ci_instr16_i[12] => Mux40.IN10
|
|
ci_instr16_i[12] => Mux41.IN9
|
|
ci_instr16_i[12] => Mux41.IN10
|
|
ci_instr16_i[12] => Mux46.IN6
|
|
ci_instr16_i[12] => Mux46.IN7
|
|
ci_instr16_i[12] => ci_instr32_o.DATAB
|
|
ci_instr16_i[12] => Mux75.IN10
|
|
ci_instr16_i[12] => Mux82.IN3
|
|
ci_instr16_i[12] => Equal0.IN0
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[12] => decompressor.IN1
|
|
ci_instr16_i[13] => ci_illegal_o.DATAB
|
|
ci_instr16_i[13] => Mux22.IN3
|
|
ci_instr16_i[13] => Mux23.IN3
|
|
ci_instr16_i[13] => Mux24.IN3
|
|
ci_instr16_i[13] => Mux25.IN4
|
|
ci_instr16_i[13] => Mux26.IN4
|
|
ci_instr16_i[13] => Mux27.IN4
|
|
ci_instr16_i[13] => Mux28.IN4
|
|
ci_instr16_i[13] => Mux29.IN6
|
|
ci_instr16_i[13] => Mux30.IN6
|
|
ci_instr16_i[13] => Mux31.IN5
|
|
ci_instr16_i[13] => Mux32.IN5
|
|
ci_instr16_i[13] => Mux33.IN5
|
|
ci_instr16_i[13] => Mux34.IN7
|
|
ci_instr16_i[13] => Mux35.IN7
|
|
ci_instr16_i[13] => Mux36.IN4
|
|
ci_instr16_i[13] => Mux37.IN4
|
|
ci_instr16_i[13] => Mux38.IN4
|
|
ci_instr16_i[13] => Mux39.IN8
|
|
ci_instr16_i[13] => Mux40.IN8
|
|
ci_instr16_i[13] => Mux41.IN6
|
|
ci_instr16_i[13] => Mux41.IN7
|
|
ci_instr16_i[13] => Mux41.IN8
|
|
ci_instr16_i[13] => Mux42.IN6
|
|
ci_instr16_i[13] => Mux43.IN6
|
|
ci_instr16_i[13] => Mux44.IN5
|
|
ci_instr16_i[13] => Mux45.IN5
|
|
ci_instr16_i[13] => Mux46.IN5
|
|
ci_instr16_i[13] => Mux47.IN10
|
|
ci_instr16_i[13] => Mux48.IN10
|
|
ci_instr16_i[13] => Mux49.IN10
|
|
ci_instr16_i[13] => Mux50.IN5
|
|
ci_instr16_i[13] => Mux51.IN10
|
|
ci_instr16_i[13] => Mux52.IN10
|
|
ci_instr16_i[13] => Mux55.IN5
|
|
ci_instr16_i[13] => Mux56.IN5
|
|
ci_instr16_i[13] => Mux57.IN5
|
|
ci_instr16_i[13] => Mux58.IN7
|
|
ci_instr16_i[13] => Mux59.IN7
|
|
ci_instr16_i[13] => Mux60.IN9
|
|
ci_instr16_i[13] => Mux61.IN9
|
|
ci_instr16_i[13] => Mux62.IN9
|
|
ci_instr16_i[13] => Mux63.IN9
|
|
ci_instr16_i[13] => Mux64.IN9
|
|
ci_instr16_i[13] => Mux65.IN10
|
|
ci_instr16_i[13] => Mux66.IN5
|
|
ci_instr16_i[13] => Mux67.IN5
|
|
ci_instr16_i[13] => Mux68.IN5
|
|
ci_instr16_i[13] => Mux69.IN7
|
|
ci_instr16_i[13] => Mux70.IN7
|
|
ci_instr16_i[13] => Mux71.IN10
|
|
ci_instr16_i[13] => Mux72.IN10
|
|
ci_instr16_i[13] => Mux73.IN10
|
|
ci_instr16_i[13] => Mux74.IN10
|
|
ci_instr16_i[13] => Mux75.IN5
|
|
ci_instr16_i[13] => Mux75.IN6
|
|
ci_instr16_i[13] => Mux75.IN7
|
|
ci_instr16_i[13] => Mux75.IN8
|
|
ci_instr16_i[13] => Mux75.IN9
|
|
ci_instr16_i[13] => Equal1.IN1
|
|
ci_instr16_i[13] => Equal5.IN2
|
|
ci_instr16_i[13] => Equal6.IN2
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => Mux0.IN2
|
|
ci_instr16_i[14] => Mux1.IN2
|
|
ci_instr16_i[14] => Mux2.IN1
|
|
ci_instr16_i[14] => Mux3.IN4
|
|
ci_instr16_i[14] => Mux4.IN4
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => Mux5.IN4
|
|
ci_instr16_i[14] => Mux6.IN4
|
|
ci_instr16_i[14] => Mux7.IN1
|
|
ci_instr16_i[14] => Mux8.IN2
|
|
ci_instr16_i[14] => Mux9.IN2
|
|
ci_instr16_i[14] => Mux10.IN5
|
|
ci_instr16_i[14] => ci_illegal_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => Mux22.IN2
|
|
ci_instr16_i[14] => Mux23.IN2
|
|
ci_instr16_i[14] => Mux24.IN2
|
|
ci_instr16_i[14] => Mux25.IN3
|
|
ci_instr16_i[14] => Mux26.IN3
|
|
ci_instr16_i[14] => Mux27.IN3
|
|
ci_instr16_i[14] => Mux28.IN3
|
|
ci_instr16_i[14] => Mux29.IN5
|
|
ci_instr16_i[14] => Mux30.IN5
|
|
ci_instr16_i[14] => Mux31.IN4
|
|
ci_instr16_i[14] => Mux32.IN4
|
|
ci_instr16_i[14] => Mux33.IN4
|
|
ci_instr16_i[14] => Mux34.IN6
|
|
ci_instr16_i[14] => Mux35.IN6
|
|
ci_instr16_i[14] => Mux36.IN3
|
|
ci_instr16_i[14] => Mux37.IN3
|
|
ci_instr16_i[14] => Mux38.IN3
|
|
ci_instr16_i[14] => Mux39.IN7
|
|
ci_instr16_i[14] => Mux40.IN7
|
|
ci_instr16_i[14] => Mux41.IN5
|
|
ci_instr16_i[14] => Mux42.IN5
|
|
ci_instr16_i[14] => Mux43.IN5
|
|
ci_instr16_i[14] => Mux44.IN4
|
|
ci_instr16_i[14] => Mux45.IN4
|
|
ci_instr16_i[14] => Mux46.IN4
|
|
ci_instr16_i[14] => Mux47.IN9
|
|
ci_instr16_i[14] => Mux48.IN9
|
|
ci_instr16_i[14] => Mux49.IN9
|
|
ci_instr16_i[14] => Mux50.IN4
|
|
ci_instr16_i[14] => Mux51.IN9
|
|
ci_instr16_i[14] => Mux52.IN9
|
|
ci_instr16_i[14] => Mux53.IN3
|
|
ci_instr16_i[14] => Mux54.IN3
|
|
ci_instr16_i[14] => ci_instr32_o.OUTPUTSELECT
|
|
ci_instr16_i[14] => Mux55.IN4
|
|
ci_instr16_i[14] => Mux56.IN4
|
|
ci_instr16_i[14] => Mux57.IN4
|
|
ci_instr16_i[14] => Mux58.IN6
|
|
ci_instr16_i[14] => Mux59.IN6
|
|
ci_instr16_i[14] => Mux60.IN8
|
|
ci_instr16_i[14] => Mux61.IN8
|
|
ci_instr16_i[14] => Mux62.IN8
|
|
ci_instr16_i[14] => Mux63.IN8
|
|
ci_instr16_i[14] => Mux64.IN8
|
|
ci_instr16_i[14] => Mux65.IN9
|
|
ci_instr16_i[14] => Mux66.IN4
|
|
ci_instr16_i[14] => Mux67.IN4
|
|
ci_instr16_i[14] => Mux68.IN4
|
|
ci_instr16_i[14] => Mux69.IN6
|
|
ci_instr16_i[14] => Mux70.IN6
|
|
ci_instr16_i[14] => Mux71.IN9
|
|
ci_instr16_i[14] => Mux72.IN9
|
|
ci_instr16_i[14] => Mux73.IN9
|
|
ci_instr16_i[14] => Mux74.IN9
|
|
ci_instr16_i[14] => Mux75.IN4
|
|
ci_instr16_i[14] => Mux89.IN3
|
|
ci_instr16_i[14] => Mux94.IN1
|
|
ci_instr16_i[14] => Mux94.IN2
|
|
ci_instr16_i[14] => Mux94.IN3
|
|
ci_instr16_i[14] => Equal1.IN0
|
|
ci_instr16_i[14] => Mux103.IN0
|
|
ci_instr16_i[14] => Equal5.IN1
|
|
ci_instr16_i[14] => Equal6.IN0
|
|
ci_instr16_i[15] => Mux0.IN1
|
|
ci_instr16_i[15] => Mux1.IN1
|
|
ci_instr16_i[15] => Mux2.IN0
|
|
ci_instr16_i[15] => Mux3.IN3
|
|
ci_instr16_i[15] => Mux4.IN3
|
|
ci_instr16_i[15] => Mux5.IN3
|
|
ci_instr16_i[15] => Mux6.IN3
|
|
ci_instr16_i[15] => Mux7.IN0
|
|
ci_instr16_i[15] => Mux8.IN1
|
|
ci_instr16_i[15] => Mux9.IN1
|
|
ci_instr16_i[15] => Mux10.IN4
|
|
ci_instr16_i[15] => Mux22.IN1
|
|
ci_instr16_i[15] => Mux23.IN1
|
|
ci_instr16_i[15] => Mux24.IN1
|
|
ci_instr16_i[15] => Mux25.IN2
|
|
ci_instr16_i[15] => Mux26.IN2
|
|
ci_instr16_i[15] => Mux27.IN2
|
|
ci_instr16_i[15] => Mux28.IN2
|
|
ci_instr16_i[15] => Mux29.IN4
|
|
ci_instr16_i[15] => Mux30.IN4
|
|
ci_instr16_i[15] => Mux31.IN3
|
|
ci_instr16_i[15] => Mux32.IN3
|
|
ci_instr16_i[15] => Mux33.IN3
|
|
ci_instr16_i[15] => Mux34.IN5
|
|
ci_instr16_i[15] => Mux35.IN5
|
|
ci_instr16_i[15] => Mux36.IN2
|
|
ci_instr16_i[15] => Mux37.IN2
|
|
ci_instr16_i[15] => Mux38.IN2
|
|
ci_instr16_i[15] => Mux39.IN6
|
|
ci_instr16_i[15] => Mux40.IN6
|
|
ci_instr16_i[15] => Mux41.IN4
|
|
ci_instr16_i[15] => Mux42.IN4
|
|
ci_instr16_i[15] => Mux43.IN4
|
|
ci_instr16_i[15] => Mux44.IN3
|
|
ci_instr16_i[15] => Mux45.IN3
|
|
ci_instr16_i[15] => Mux46.IN3
|
|
ci_instr16_i[15] => Mux47.IN8
|
|
ci_instr16_i[15] => Mux48.IN8
|
|
ci_instr16_i[15] => Mux49.IN8
|
|
ci_instr16_i[15] => Mux51.IN8
|
|
ci_instr16_i[15] => Mux52.IN8
|
|
ci_instr16_i[15] => Mux53.IN2
|
|
ci_instr16_i[15] => Mux54.IN2
|
|
ci_instr16_i[15] => Mux55.IN3
|
|
ci_instr16_i[15] => Mux56.IN3
|
|
ci_instr16_i[15] => Mux57.IN3
|
|
ci_instr16_i[15] => Mux58.IN5
|
|
ci_instr16_i[15] => Mux59.IN5
|
|
ci_instr16_i[15] => Mux60.IN7
|
|
ci_instr16_i[15] => Mux61.IN7
|
|
ci_instr16_i[15] => Mux62.IN7
|
|
ci_instr16_i[15] => Mux63.IN7
|
|
ci_instr16_i[15] => Mux64.IN7
|
|
ci_instr16_i[15] => Mux65.IN8
|
|
ci_instr16_i[15] => Mux66.IN3
|
|
ci_instr16_i[15] => Mux67.IN3
|
|
ci_instr16_i[15] => Mux68.IN3
|
|
ci_instr16_i[15] => Mux69.IN5
|
|
ci_instr16_i[15] => Mux70.IN5
|
|
ci_instr16_i[15] => Mux71.IN8
|
|
ci_instr16_i[15] => Mux72.IN8
|
|
ci_instr16_i[15] => Mux73.IN8
|
|
ci_instr16_i[15] => Mux74.IN8
|
|
ci_instr16_i[15] => Mux75.IN3
|
|
ci_instr16_i[15] => Equal1.IN2
|
|
ci_instr16_i[15] => Mux46.IN0
|
|
ci_instr16_i[15] => Mux46.IN1
|
|
ci_instr16_i[15] => Equal5.IN0
|
|
ci_instr16_i[15] => Equal6.IN1
|
|
ci_illegal_o <= Mux106.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[0] <= <VCC>
|
|
ci_instr32_o[1] <= <VCC>
|
|
ci_instr32_o[2] <= Mux105.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[3] <= Mux104.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[4] <= Mux103.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[5] <= Mux102.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[6] <= Mux101.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[7] <= Mux100.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[8] <= Mux99.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[9] <= Mux98.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[10] <= Mux97.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[11] <= Mux96.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[12] <= Mux95.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[13] <= Mux94.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[14] <= Mux93.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[15] <= Mux92.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[16] <= Mux91.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[17] <= Mux90.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[18] <= Mux89.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[19] <= Mux88.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[20] <= Mux87.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[21] <= Mux86.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[22] <= Mux85.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[23] <= Mux84.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[24] <= Mux83.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[25] <= Mux82.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[26] <= Mux81.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[27] <= Mux80.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[28] <= Mux79.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[29] <= Mux78.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[30] <= Mux77.DB_MAX_OUTPUT_PORT_TYPE
|
|
ci_instr32_o[31] <= Mux76.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_regfile:neorv32_cpu_regfile_inst
|
|
clk_i => rs4_o[0]~reg0.CLK
|
|
clk_i => rs4_o[1]~reg0.CLK
|
|
clk_i => rs4_o[2]~reg0.CLK
|
|
clk_i => rs4_o[3]~reg0.CLK
|
|
clk_i => rs4_o[4]~reg0.CLK
|
|
clk_i => rs4_o[5]~reg0.CLK
|
|
clk_i => rs4_o[6]~reg0.CLK
|
|
clk_i => rs4_o[7]~reg0.CLK
|
|
clk_i => rs4_o[8]~reg0.CLK
|
|
clk_i => rs4_o[9]~reg0.CLK
|
|
clk_i => rs4_o[10]~reg0.CLK
|
|
clk_i => rs4_o[11]~reg0.CLK
|
|
clk_i => rs4_o[12]~reg0.CLK
|
|
clk_i => rs4_o[13]~reg0.CLK
|
|
clk_i => rs4_o[14]~reg0.CLK
|
|
clk_i => rs4_o[15]~reg0.CLK
|
|
clk_i => rs4_o[16]~reg0.CLK
|
|
clk_i => rs4_o[17]~reg0.CLK
|
|
clk_i => rs4_o[18]~reg0.CLK
|
|
clk_i => rs4_o[19]~reg0.CLK
|
|
clk_i => rs4_o[20]~reg0.CLK
|
|
clk_i => rs4_o[21]~reg0.CLK
|
|
clk_i => rs4_o[22]~reg0.CLK
|
|
clk_i => rs4_o[23]~reg0.CLK
|
|
clk_i => rs4_o[24]~reg0.CLK
|
|
clk_i => rs4_o[25]~reg0.CLK
|
|
clk_i => rs4_o[26]~reg0.CLK
|
|
clk_i => rs4_o[27]~reg0.CLK
|
|
clk_i => rs4_o[28]~reg0.CLK
|
|
clk_i => rs4_o[29]~reg0.CLK
|
|
clk_i => rs4_o[30]~reg0.CLK
|
|
clk_i => rs4_o[31]~reg0.CLK
|
|
clk_i => rs3_o[0]~reg0.CLK
|
|
clk_i => rs3_o[1]~reg0.CLK
|
|
clk_i => rs3_o[2]~reg0.CLK
|
|
clk_i => rs3_o[3]~reg0.CLK
|
|
clk_i => rs3_o[4]~reg0.CLK
|
|
clk_i => rs3_o[5]~reg0.CLK
|
|
clk_i => rs3_o[6]~reg0.CLK
|
|
clk_i => rs3_o[7]~reg0.CLK
|
|
clk_i => rs3_o[8]~reg0.CLK
|
|
clk_i => rs3_o[9]~reg0.CLK
|
|
clk_i => rs3_o[10]~reg0.CLK
|
|
clk_i => rs3_o[11]~reg0.CLK
|
|
clk_i => rs3_o[12]~reg0.CLK
|
|
clk_i => rs3_o[13]~reg0.CLK
|
|
clk_i => rs3_o[14]~reg0.CLK
|
|
clk_i => rs3_o[15]~reg0.CLK
|
|
clk_i => rs3_o[16]~reg0.CLK
|
|
clk_i => rs3_o[17]~reg0.CLK
|
|
clk_i => rs3_o[18]~reg0.CLK
|
|
clk_i => rs3_o[19]~reg0.CLK
|
|
clk_i => rs3_o[20]~reg0.CLK
|
|
clk_i => rs3_o[21]~reg0.CLK
|
|
clk_i => rs3_o[22]~reg0.CLK
|
|
clk_i => rs3_o[23]~reg0.CLK
|
|
clk_i => rs3_o[24]~reg0.CLK
|
|
clk_i => rs3_o[25]~reg0.CLK
|
|
clk_i => rs3_o[26]~reg0.CLK
|
|
clk_i => rs3_o[27]~reg0.CLK
|
|
clk_i => rs3_o[28]~reg0.CLK
|
|
clk_i => rs3_o[29]~reg0.CLK
|
|
clk_i => rs3_o[30]~reg0.CLK
|
|
clk_i => rs3_o[31]~reg0.CLK
|
|
clk_i => reg_file[0][0].CLK
|
|
clk_i => reg_file[0][1].CLK
|
|
clk_i => reg_file[0][2].CLK
|
|
clk_i => reg_file[0][3].CLK
|
|
clk_i => reg_file[0][4].CLK
|
|
clk_i => reg_file[0][5].CLK
|
|
clk_i => reg_file[0][6].CLK
|
|
clk_i => reg_file[0][7].CLK
|
|
clk_i => reg_file[0][8].CLK
|
|
clk_i => reg_file[0][9].CLK
|
|
clk_i => reg_file[0][10].CLK
|
|
clk_i => reg_file[0][11].CLK
|
|
clk_i => reg_file[0][12].CLK
|
|
clk_i => reg_file[0][13].CLK
|
|
clk_i => reg_file[0][14].CLK
|
|
clk_i => reg_file[0][15].CLK
|
|
clk_i => reg_file[0][16].CLK
|
|
clk_i => reg_file[0][17].CLK
|
|
clk_i => reg_file[0][18].CLK
|
|
clk_i => reg_file[0][19].CLK
|
|
clk_i => reg_file[0][20].CLK
|
|
clk_i => reg_file[0][21].CLK
|
|
clk_i => reg_file[0][22].CLK
|
|
clk_i => reg_file[0][23].CLK
|
|
clk_i => reg_file[0][24].CLK
|
|
clk_i => reg_file[0][25].CLK
|
|
clk_i => reg_file[0][26].CLK
|
|
clk_i => reg_file[0][27].CLK
|
|
clk_i => reg_file[0][28].CLK
|
|
clk_i => reg_file[0][29].CLK
|
|
clk_i => reg_file[0][30].CLK
|
|
clk_i => reg_file[0][31].CLK
|
|
clk_i => reg_file[1][0].CLK
|
|
clk_i => reg_file[1][1].CLK
|
|
clk_i => reg_file[1][2].CLK
|
|
clk_i => reg_file[1][3].CLK
|
|
clk_i => reg_file[1][4].CLK
|
|
clk_i => reg_file[1][5].CLK
|
|
clk_i => reg_file[1][6].CLK
|
|
clk_i => reg_file[1][7].CLK
|
|
clk_i => reg_file[1][8].CLK
|
|
clk_i => reg_file[1][9].CLK
|
|
clk_i => reg_file[1][10].CLK
|
|
clk_i => reg_file[1][11].CLK
|
|
clk_i => reg_file[1][12].CLK
|
|
clk_i => reg_file[1][13].CLK
|
|
clk_i => reg_file[1][14].CLK
|
|
clk_i => reg_file[1][15].CLK
|
|
clk_i => reg_file[1][16].CLK
|
|
clk_i => reg_file[1][17].CLK
|
|
clk_i => reg_file[1][18].CLK
|
|
clk_i => reg_file[1][19].CLK
|
|
clk_i => reg_file[1][20].CLK
|
|
clk_i => reg_file[1][21].CLK
|
|
clk_i => reg_file[1][22].CLK
|
|
clk_i => reg_file[1][23].CLK
|
|
clk_i => reg_file[1][24].CLK
|
|
clk_i => reg_file[1][25].CLK
|
|
clk_i => reg_file[1][26].CLK
|
|
clk_i => reg_file[1][27].CLK
|
|
clk_i => reg_file[1][28].CLK
|
|
clk_i => reg_file[1][29].CLK
|
|
clk_i => reg_file[1][30].CLK
|
|
clk_i => reg_file[1][31].CLK
|
|
clk_i => reg_file[2][0].CLK
|
|
clk_i => reg_file[2][1].CLK
|
|
clk_i => reg_file[2][2].CLK
|
|
clk_i => reg_file[2][3].CLK
|
|
clk_i => reg_file[2][4].CLK
|
|
clk_i => reg_file[2][5].CLK
|
|
clk_i => reg_file[2][6].CLK
|
|
clk_i => reg_file[2][7].CLK
|
|
clk_i => reg_file[2][8].CLK
|
|
clk_i => reg_file[2][9].CLK
|
|
clk_i => reg_file[2][10].CLK
|
|
clk_i => reg_file[2][11].CLK
|
|
clk_i => reg_file[2][12].CLK
|
|
clk_i => reg_file[2][13].CLK
|
|
clk_i => reg_file[2][14].CLK
|
|
clk_i => reg_file[2][15].CLK
|
|
clk_i => reg_file[2][16].CLK
|
|
clk_i => reg_file[2][17].CLK
|
|
clk_i => reg_file[2][18].CLK
|
|
clk_i => reg_file[2][19].CLK
|
|
clk_i => reg_file[2][20].CLK
|
|
clk_i => reg_file[2][21].CLK
|
|
clk_i => reg_file[2][22].CLK
|
|
clk_i => reg_file[2][23].CLK
|
|
clk_i => reg_file[2][24].CLK
|
|
clk_i => reg_file[2][25].CLK
|
|
clk_i => reg_file[2][26].CLK
|
|
clk_i => reg_file[2][27].CLK
|
|
clk_i => reg_file[2][28].CLK
|
|
clk_i => reg_file[2][29].CLK
|
|
clk_i => reg_file[2][30].CLK
|
|
clk_i => reg_file[2][31].CLK
|
|
clk_i => reg_file[3][0].CLK
|
|
clk_i => reg_file[3][1].CLK
|
|
clk_i => reg_file[3][2].CLK
|
|
clk_i => reg_file[3][3].CLK
|
|
clk_i => reg_file[3][4].CLK
|
|
clk_i => reg_file[3][5].CLK
|
|
clk_i => reg_file[3][6].CLK
|
|
clk_i => reg_file[3][7].CLK
|
|
clk_i => reg_file[3][8].CLK
|
|
clk_i => reg_file[3][9].CLK
|
|
clk_i => reg_file[3][10].CLK
|
|
clk_i => reg_file[3][11].CLK
|
|
clk_i => reg_file[3][12].CLK
|
|
clk_i => reg_file[3][13].CLK
|
|
clk_i => reg_file[3][14].CLK
|
|
clk_i => reg_file[3][15].CLK
|
|
clk_i => reg_file[3][16].CLK
|
|
clk_i => reg_file[3][17].CLK
|
|
clk_i => reg_file[3][18].CLK
|
|
clk_i => reg_file[3][19].CLK
|
|
clk_i => reg_file[3][20].CLK
|
|
clk_i => reg_file[3][21].CLK
|
|
clk_i => reg_file[3][22].CLK
|
|
clk_i => reg_file[3][23].CLK
|
|
clk_i => reg_file[3][24].CLK
|
|
clk_i => reg_file[3][25].CLK
|
|
clk_i => reg_file[3][26].CLK
|
|
clk_i => reg_file[3][27].CLK
|
|
clk_i => reg_file[3][28].CLK
|
|
clk_i => reg_file[3][29].CLK
|
|
clk_i => reg_file[3][30].CLK
|
|
clk_i => reg_file[3][31].CLK
|
|
clk_i => reg_file[4][0].CLK
|
|
clk_i => reg_file[4][1].CLK
|
|
clk_i => reg_file[4][2].CLK
|
|
clk_i => reg_file[4][3].CLK
|
|
clk_i => reg_file[4][4].CLK
|
|
clk_i => reg_file[4][5].CLK
|
|
clk_i => reg_file[4][6].CLK
|
|
clk_i => reg_file[4][7].CLK
|
|
clk_i => reg_file[4][8].CLK
|
|
clk_i => reg_file[4][9].CLK
|
|
clk_i => reg_file[4][10].CLK
|
|
clk_i => reg_file[4][11].CLK
|
|
clk_i => reg_file[4][12].CLK
|
|
clk_i => reg_file[4][13].CLK
|
|
clk_i => reg_file[4][14].CLK
|
|
clk_i => reg_file[4][15].CLK
|
|
clk_i => reg_file[4][16].CLK
|
|
clk_i => reg_file[4][17].CLK
|
|
clk_i => reg_file[4][18].CLK
|
|
clk_i => reg_file[4][19].CLK
|
|
clk_i => reg_file[4][20].CLK
|
|
clk_i => reg_file[4][21].CLK
|
|
clk_i => reg_file[4][22].CLK
|
|
clk_i => reg_file[4][23].CLK
|
|
clk_i => reg_file[4][24].CLK
|
|
clk_i => reg_file[4][25].CLK
|
|
clk_i => reg_file[4][26].CLK
|
|
clk_i => reg_file[4][27].CLK
|
|
clk_i => reg_file[4][28].CLK
|
|
clk_i => reg_file[4][29].CLK
|
|
clk_i => reg_file[4][30].CLK
|
|
clk_i => reg_file[4][31].CLK
|
|
clk_i => reg_file[5][0].CLK
|
|
clk_i => reg_file[5][1].CLK
|
|
clk_i => reg_file[5][2].CLK
|
|
clk_i => reg_file[5][3].CLK
|
|
clk_i => reg_file[5][4].CLK
|
|
clk_i => reg_file[5][5].CLK
|
|
clk_i => reg_file[5][6].CLK
|
|
clk_i => reg_file[5][7].CLK
|
|
clk_i => reg_file[5][8].CLK
|
|
clk_i => reg_file[5][9].CLK
|
|
clk_i => reg_file[5][10].CLK
|
|
clk_i => reg_file[5][11].CLK
|
|
clk_i => reg_file[5][12].CLK
|
|
clk_i => reg_file[5][13].CLK
|
|
clk_i => reg_file[5][14].CLK
|
|
clk_i => reg_file[5][15].CLK
|
|
clk_i => reg_file[5][16].CLK
|
|
clk_i => reg_file[5][17].CLK
|
|
clk_i => reg_file[5][18].CLK
|
|
clk_i => reg_file[5][19].CLK
|
|
clk_i => reg_file[5][20].CLK
|
|
clk_i => reg_file[5][21].CLK
|
|
clk_i => reg_file[5][22].CLK
|
|
clk_i => reg_file[5][23].CLK
|
|
clk_i => reg_file[5][24].CLK
|
|
clk_i => reg_file[5][25].CLK
|
|
clk_i => reg_file[5][26].CLK
|
|
clk_i => reg_file[5][27].CLK
|
|
clk_i => reg_file[5][28].CLK
|
|
clk_i => reg_file[5][29].CLK
|
|
clk_i => reg_file[5][30].CLK
|
|
clk_i => reg_file[5][31].CLK
|
|
clk_i => reg_file[6][0].CLK
|
|
clk_i => reg_file[6][1].CLK
|
|
clk_i => reg_file[6][2].CLK
|
|
clk_i => reg_file[6][3].CLK
|
|
clk_i => reg_file[6][4].CLK
|
|
clk_i => reg_file[6][5].CLK
|
|
clk_i => reg_file[6][6].CLK
|
|
clk_i => reg_file[6][7].CLK
|
|
clk_i => reg_file[6][8].CLK
|
|
clk_i => reg_file[6][9].CLK
|
|
clk_i => reg_file[6][10].CLK
|
|
clk_i => reg_file[6][11].CLK
|
|
clk_i => reg_file[6][12].CLK
|
|
clk_i => reg_file[6][13].CLK
|
|
clk_i => reg_file[6][14].CLK
|
|
clk_i => reg_file[6][15].CLK
|
|
clk_i => reg_file[6][16].CLK
|
|
clk_i => reg_file[6][17].CLK
|
|
clk_i => reg_file[6][18].CLK
|
|
clk_i => reg_file[6][19].CLK
|
|
clk_i => reg_file[6][20].CLK
|
|
clk_i => reg_file[6][21].CLK
|
|
clk_i => reg_file[6][22].CLK
|
|
clk_i => reg_file[6][23].CLK
|
|
clk_i => reg_file[6][24].CLK
|
|
clk_i => reg_file[6][25].CLK
|
|
clk_i => reg_file[6][26].CLK
|
|
clk_i => reg_file[6][27].CLK
|
|
clk_i => reg_file[6][28].CLK
|
|
clk_i => reg_file[6][29].CLK
|
|
clk_i => reg_file[6][30].CLK
|
|
clk_i => reg_file[6][31].CLK
|
|
clk_i => reg_file[7][0].CLK
|
|
clk_i => reg_file[7][1].CLK
|
|
clk_i => reg_file[7][2].CLK
|
|
clk_i => reg_file[7][3].CLK
|
|
clk_i => reg_file[7][4].CLK
|
|
clk_i => reg_file[7][5].CLK
|
|
clk_i => reg_file[7][6].CLK
|
|
clk_i => reg_file[7][7].CLK
|
|
clk_i => reg_file[7][8].CLK
|
|
clk_i => reg_file[7][9].CLK
|
|
clk_i => reg_file[7][10].CLK
|
|
clk_i => reg_file[7][11].CLK
|
|
clk_i => reg_file[7][12].CLK
|
|
clk_i => reg_file[7][13].CLK
|
|
clk_i => reg_file[7][14].CLK
|
|
clk_i => reg_file[7][15].CLK
|
|
clk_i => reg_file[7][16].CLK
|
|
clk_i => reg_file[7][17].CLK
|
|
clk_i => reg_file[7][18].CLK
|
|
clk_i => reg_file[7][19].CLK
|
|
clk_i => reg_file[7][20].CLK
|
|
clk_i => reg_file[7][21].CLK
|
|
clk_i => reg_file[7][22].CLK
|
|
clk_i => reg_file[7][23].CLK
|
|
clk_i => reg_file[7][24].CLK
|
|
clk_i => reg_file[7][25].CLK
|
|
clk_i => reg_file[7][26].CLK
|
|
clk_i => reg_file[7][27].CLK
|
|
clk_i => reg_file[7][28].CLK
|
|
clk_i => reg_file[7][29].CLK
|
|
clk_i => reg_file[7][30].CLK
|
|
clk_i => reg_file[7][31].CLK
|
|
clk_i => reg_file[8][0].CLK
|
|
clk_i => reg_file[8][1].CLK
|
|
clk_i => reg_file[8][2].CLK
|
|
clk_i => reg_file[8][3].CLK
|
|
clk_i => reg_file[8][4].CLK
|
|
clk_i => reg_file[8][5].CLK
|
|
clk_i => reg_file[8][6].CLK
|
|
clk_i => reg_file[8][7].CLK
|
|
clk_i => reg_file[8][8].CLK
|
|
clk_i => reg_file[8][9].CLK
|
|
clk_i => reg_file[8][10].CLK
|
|
clk_i => reg_file[8][11].CLK
|
|
clk_i => reg_file[8][12].CLK
|
|
clk_i => reg_file[8][13].CLK
|
|
clk_i => reg_file[8][14].CLK
|
|
clk_i => reg_file[8][15].CLK
|
|
clk_i => reg_file[8][16].CLK
|
|
clk_i => reg_file[8][17].CLK
|
|
clk_i => reg_file[8][18].CLK
|
|
clk_i => reg_file[8][19].CLK
|
|
clk_i => reg_file[8][20].CLK
|
|
clk_i => reg_file[8][21].CLK
|
|
clk_i => reg_file[8][22].CLK
|
|
clk_i => reg_file[8][23].CLK
|
|
clk_i => reg_file[8][24].CLK
|
|
clk_i => reg_file[8][25].CLK
|
|
clk_i => reg_file[8][26].CLK
|
|
clk_i => reg_file[8][27].CLK
|
|
clk_i => reg_file[8][28].CLK
|
|
clk_i => reg_file[8][29].CLK
|
|
clk_i => reg_file[8][30].CLK
|
|
clk_i => reg_file[8][31].CLK
|
|
clk_i => reg_file[9][0].CLK
|
|
clk_i => reg_file[9][1].CLK
|
|
clk_i => reg_file[9][2].CLK
|
|
clk_i => reg_file[9][3].CLK
|
|
clk_i => reg_file[9][4].CLK
|
|
clk_i => reg_file[9][5].CLK
|
|
clk_i => reg_file[9][6].CLK
|
|
clk_i => reg_file[9][7].CLK
|
|
clk_i => reg_file[9][8].CLK
|
|
clk_i => reg_file[9][9].CLK
|
|
clk_i => reg_file[9][10].CLK
|
|
clk_i => reg_file[9][11].CLK
|
|
clk_i => reg_file[9][12].CLK
|
|
clk_i => reg_file[9][13].CLK
|
|
clk_i => reg_file[9][14].CLK
|
|
clk_i => reg_file[9][15].CLK
|
|
clk_i => reg_file[9][16].CLK
|
|
clk_i => reg_file[9][17].CLK
|
|
clk_i => reg_file[9][18].CLK
|
|
clk_i => reg_file[9][19].CLK
|
|
clk_i => reg_file[9][20].CLK
|
|
clk_i => reg_file[9][21].CLK
|
|
clk_i => reg_file[9][22].CLK
|
|
clk_i => reg_file[9][23].CLK
|
|
clk_i => reg_file[9][24].CLK
|
|
clk_i => reg_file[9][25].CLK
|
|
clk_i => reg_file[9][26].CLK
|
|
clk_i => reg_file[9][27].CLK
|
|
clk_i => reg_file[9][28].CLK
|
|
clk_i => reg_file[9][29].CLK
|
|
clk_i => reg_file[9][30].CLK
|
|
clk_i => reg_file[9][31].CLK
|
|
clk_i => reg_file[10][0].CLK
|
|
clk_i => reg_file[10][1].CLK
|
|
clk_i => reg_file[10][2].CLK
|
|
clk_i => reg_file[10][3].CLK
|
|
clk_i => reg_file[10][4].CLK
|
|
clk_i => reg_file[10][5].CLK
|
|
clk_i => reg_file[10][6].CLK
|
|
clk_i => reg_file[10][7].CLK
|
|
clk_i => reg_file[10][8].CLK
|
|
clk_i => reg_file[10][9].CLK
|
|
clk_i => reg_file[10][10].CLK
|
|
clk_i => reg_file[10][11].CLK
|
|
clk_i => reg_file[10][12].CLK
|
|
clk_i => reg_file[10][13].CLK
|
|
clk_i => reg_file[10][14].CLK
|
|
clk_i => reg_file[10][15].CLK
|
|
clk_i => reg_file[10][16].CLK
|
|
clk_i => reg_file[10][17].CLK
|
|
clk_i => reg_file[10][18].CLK
|
|
clk_i => reg_file[10][19].CLK
|
|
clk_i => reg_file[10][20].CLK
|
|
clk_i => reg_file[10][21].CLK
|
|
clk_i => reg_file[10][22].CLK
|
|
clk_i => reg_file[10][23].CLK
|
|
clk_i => reg_file[10][24].CLK
|
|
clk_i => reg_file[10][25].CLK
|
|
clk_i => reg_file[10][26].CLK
|
|
clk_i => reg_file[10][27].CLK
|
|
clk_i => reg_file[10][28].CLK
|
|
clk_i => reg_file[10][29].CLK
|
|
clk_i => reg_file[10][30].CLK
|
|
clk_i => reg_file[10][31].CLK
|
|
clk_i => reg_file[11][0].CLK
|
|
clk_i => reg_file[11][1].CLK
|
|
clk_i => reg_file[11][2].CLK
|
|
clk_i => reg_file[11][3].CLK
|
|
clk_i => reg_file[11][4].CLK
|
|
clk_i => reg_file[11][5].CLK
|
|
clk_i => reg_file[11][6].CLK
|
|
clk_i => reg_file[11][7].CLK
|
|
clk_i => reg_file[11][8].CLK
|
|
clk_i => reg_file[11][9].CLK
|
|
clk_i => reg_file[11][10].CLK
|
|
clk_i => reg_file[11][11].CLK
|
|
clk_i => reg_file[11][12].CLK
|
|
clk_i => reg_file[11][13].CLK
|
|
clk_i => reg_file[11][14].CLK
|
|
clk_i => reg_file[11][15].CLK
|
|
clk_i => reg_file[11][16].CLK
|
|
clk_i => reg_file[11][17].CLK
|
|
clk_i => reg_file[11][18].CLK
|
|
clk_i => reg_file[11][19].CLK
|
|
clk_i => reg_file[11][20].CLK
|
|
clk_i => reg_file[11][21].CLK
|
|
clk_i => reg_file[11][22].CLK
|
|
clk_i => reg_file[11][23].CLK
|
|
clk_i => reg_file[11][24].CLK
|
|
clk_i => reg_file[11][25].CLK
|
|
clk_i => reg_file[11][26].CLK
|
|
clk_i => reg_file[11][27].CLK
|
|
clk_i => reg_file[11][28].CLK
|
|
clk_i => reg_file[11][29].CLK
|
|
clk_i => reg_file[11][30].CLK
|
|
clk_i => reg_file[11][31].CLK
|
|
clk_i => reg_file[12][0].CLK
|
|
clk_i => reg_file[12][1].CLK
|
|
clk_i => reg_file[12][2].CLK
|
|
clk_i => reg_file[12][3].CLK
|
|
clk_i => reg_file[12][4].CLK
|
|
clk_i => reg_file[12][5].CLK
|
|
clk_i => reg_file[12][6].CLK
|
|
clk_i => reg_file[12][7].CLK
|
|
clk_i => reg_file[12][8].CLK
|
|
clk_i => reg_file[12][9].CLK
|
|
clk_i => reg_file[12][10].CLK
|
|
clk_i => reg_file[12][11].CLK
|
|
clk_i => reg_file[12][12].CLK
|
|
clk_i => reg_file[12][13].CLK
|
|
clk_i => reg_file[12][14].CLK
|
|
clk_i => reg_file[12][15].CLK
|
|
clk_i => reg_file[12][16].CLK
|
|
clk_i => reg_file[12][17].CLK
|
|
clk_i => reg_file[12][18].CLK
|
|
clk_i => reg_file[12][19].CLK
|
|
clk_i => reg_file[12][20].CLK
|
|
clk_i => reg_file[12][21].CLK
|
|
clk_i => reg_file[12][22].CLK
|
|
clk_i => reg_file[12][23].CLK
|
|
clk_i => reg_file[12][24].CLK
|
|
clk_i => reg_file[12][25].CLK
|
|
clk_i => reg_file[12][26].CLK
|
|
clk_i => reg_file[12][27].CLK
|
|
clk_i => reg_file[12][28].CLK
|
|
clk_i => reg_file[12][29].CLK
|
|
clk_i => reg_file[12][30].CLK
|
|
clk_i => reg_file[12][31].CLK
|
|
clk_i => reg_file[13][0].CLK
|
|
clk_i => reg_file[13][1].CLK
|
|
clk_i => reg_file[13][2].CLK
|
|
clk_i => reg_file[13][3].CLK
|
|
clk_i => reg_file[13][4].CLK
|
|
clk_i => reg_file[13][5].CLK
|
|
clk_i => reg_file[13][6].CLK
|
|
clk_i => reg_file[13][7].CLK
|
|
clk_i => reg_file[13][8].CLK
|
|
clk_i => reg_file[13][9].CLK
|
|
clk_i => reg_file[13][10].CLK
|
|
clk_i => reg_file[13][11].CLK
|
|
clk_i => reg_file[13][12].CLK
|
|
clk_i => reg_file[13][13].CLK
|
|
clk_i => reg_file[13][14].CLK
|
|
clk_i => reg_file[13][15].CLK
|
|
clk_i => reg_file[13][16].CLK
|
|
clk_i => reg_file[13][17].CLK
|
|
clk_i => reg_file[13][18].CLK
|
|
clk_i => reg_file[13][19].CLK
|
|
clk_i => reg_file[13][20].CLK
|
|
clk_i => reg_file[13][21].CLK
|
|
clk_i => reg_file[13][22].CLK
|
|
clk_i => reg_file[13][23].CLK
|
|
clk_i => reg_file[13][24].CLK
|
|
clk_i => reg_file[13][25].CLK
|
|
clk_i => reg_file[13][26].CLK
|
|
clk_i => reg_file[13][27].CLK
|
|
clk_i => reg_file[13][28].CLK
|
|
clk_i => reg_file[13][29].CLK
|
|
clk_i => reg_file[13][30].CLK
|
|
clk_i => reg_file[13][31].CLK
|
|
clk_i => reg_file[14][0].CLK
|
|
clk_i => reg_file[14][1].CLK
|
|
clk_i => reg_file[14][2].CLK
|
|
clk_i => reg_file[14][3].CLK
|
|
clk_i => reg_file[14][4].CLK
|
|
clk_i => reg_file[14][5].CLK
|
|
clk_i => reg_file[14][6].CLK
|
|
clk_i => reg_file[14][7].CLK
|
|
clk_i => reg_file[14][8].CLK
|
|
clk_i => reg_file[14][9].CLK
|
|
clk_i => reg_file[14][10].CLK
|
|
clk_i => reg_file[14][11].CLK
|
|
clk_i => reg_file[14][12].CLK
|
|
clk_i => reg_file[14][13].CLK
|
|
clk_i => reg_file[14][14].CLK
|
|
clk_i => reg_file[14][15].CLK
|
|
clk_i => reg_file[14][16].CLK
|
|
clk_i => reg_file[14][17].CLK
|
|
clk_i => reg_file[14][18].CLK
|
|
clk_i => reg_file[14][19].CLK
|
|
clk_i => reg_file[14][20].CLK
|
|
clk_i => reg_file[14][21].CLK
|
|
clk_i => reg_file[14][22].CLK
|
|
clk_i => reg_file[14][23].CLK
|
|
clk_i => reg_file[14][24].CLK
|
|
clk_i => reg_file[14][25].CLK
|
|
clk_i => reg_file[14][26].CLK
|
|
clk_i => reg_file[14][27].CLK
|
|
clk_i => reg_file[14][28].CLK
|
|
clk_i => reg_file[14][29].CLK
|
|
clk_i => reg_file[14][30].CLK
|
|
clk_i => reg_file[14][31].CLK
|
|
clk_i => reg_file[15][0].CLK
|
|
clk_i => reg_file[15][1].CLK
|
|
clk_i => reg_file[15][2].CLK
|
|
clk_i => reg_file[15][3].CLK
|
|
clk_i => reg_file[15][4].CLK
|
|
clk_i => reg_file[15][5].CLK
|
|
clk_i => reg_file[15][6].CLK
|
|
clk_i => reg_file[15][7].CLK
|
|
clk_i => reg_file[15][8].CLK
|
|
clk_i => reg_file[15][9].CLK
|
|
clk_i => reg_file[15][10].CLK
|
|
clk_i => reg_file[15][11].CLK
|
|
clk_i => reg_file[15][12].CLK
|
|
clk_i => reg_file[15][13].CLK
|
|
clk_i => reg_file[15][14].CLK
|
|
clk_i => reg_file[15][15].CLK
|
|
clk_i => reg_file[15][16].CLK
|
|
clk_i => reg_file[15][17].CLK
|
|
clk_i => reg_file[15][18].CLK
|
|
clk_i => reg_file[15][19].CLK
|
|
clk_i => reg_file[15][20].CLK
|
|
clk_i => reg_file[15][21].CLK
|
|
clk_i => reg_file[15][22].CLK
|
|
clk_i => reg_file[15][23].CLK
|
|
clk_i => reg_file[15][24].CLK
|
|
clk_i => reg_file[15][25].CLK
|
|
clk_i => reg_file[15][26].CLK
|
|
clk_i => reg_file[15][27].CLK
|
|
clk_i => reg_file[15][28].CLK
|
|
clk_i => reg_file[15][29].CLK
|
|
clk_i => reg_file[15][30].CLK
|
|
clk_i => reg_file[15][31].CLK
|
|
clk_i => reg_file[16][0].CLK
|
|
clk_i => reg_file[16][1].CLK
|
|
clk_i => reg_file[16][2].CLK
|
|
clk_i => reg_file[16][3].CLK
|
|
clk_i => reg_file[16][4].CLK
|
|
clk_i => reg_file[16][5].CLK
|
|
clk_i => reg_file[16][6].CLK
|
|
clk_i => reg_file[16][7].CLK
|
|
clk_i => reg_file[16][8].CLK
|
|
clk_i => reg_file[16][9].CLK
|
|
clk_i => reg_file[16][10].CLK
|
|
clk_i => reg_file[16][11].CLK
|
|
clk_i => reg_file[16][12].CLK
|
|
clk_i => reg_file[16][13].CLK
|
|
clk_i => reg_file[16][14].CLK
|
|
clk_i => reg_file[16][15].CLK
|
|
clk_i => reg_file[16][16].CLK
|
|
clk_i => reg_file[16][17].CLK
|
|
clk_i => reg_file[16][18].CLK
|
|
clk_i => reg_file[16][19].CLK
|
|
clk_i => reg_file[16][20].CLK
|
|
clk_i => reg_file[16][21].CLK
|
|
clk_i => reg_file[16][22].CLK
|
|
clk_i => reg_file[16][23].CLK
|
|
clk_i => reg_file[16][24].CLK
|
|
clk_i => reg_file[16][25].CLK
|
|
clk_i => reg_file[16][26].CLK
|
|
clk_i => reg_file[16][27].CLK
|
|
clk_i => reg_file[16][28].CLK
|
|
clk_i => reg_file[16][29].CLK
|
|
clk_i => reg_file[16][30].CLK
|
|
clk_i => reg_file[16][31].CLK
|
|
clk_i => reg_file[17][0].CLK
|
|
clk_i => reg_file[17][1].CLK
|
|
clk_i => reg_file[17][2].CLK
|
|
clk_i => reg_file[17][3].CLK
|
|
clk_i => reg_file[17][4].CLK
|
|
clk_i => reg_file[17][5].CLK
|
|
clk_i => reg_file[17][6].CLK
|
|
clk_i => reg_file[17][7].CLK
|
|
clk_i => reg_file[17][8].CLK
|
|
clk_i => reg_file[17][9].CLK
|
|
clk_i => reg_file[17][10].CLK
|
|
clk_i => reg_file[17][11].CLK
|
|
clk_i => reg_file[17][12].CLK
|
|
clk_i => reg_file[17][13].CLK
|
|
clk_i => reg_file[17][14].CLK
|
|
clk_i => reg_file[17][15].CLK
|
|
clk_i => reg_file[17][16].CLK
|
|
clk_i => reg_file[17][17].CLK
|
|
clk_i => reg_file[17][18].CLK
|
|
clk_i => reg_file[17][19].CLK
|
|
clk_i => reg_file[17][20].CLK
|
|
clk_i => reg_file[17][21].CLK
|
|
clk_i => reg_file[17][22].CLK
|
|
clk_i => reg_file[17][23].CLK
|
|
clk_i => reg_file[17][24].CLK
|
|
clk_i => reg_file[17][25].CLK
|
|
clk_i => reg_file[17][26].CLK
|
|
clk_i => reg_file[17][27].CLK
|
|
clk_i => reg_file[17][28].CLK
|
|
clk_i => reg_file[17][29].CLK
|
|
clk_i => reg_file[17][30].CLK
|
|
clk_i => reg_file[17][31].CLK
|
|
clk_i => reg_file[18][0].CLK
|
|
clk_i => reg_file[18][1].CLK
|
|
clk_i => reg_file[18][2].CLK
|
|
clk_i => reg_file[18][3].CLK
|
|
clk_i => reg_file[18][4].CLK
|
|
clk_i => reg_file[18][5].CLK
|
|
clk_i => reg_file[18][6].CLK
|
|
clk_i => reg_file[18][7].CLK
|
|
clk_i => reg_file[18][8].CLK
|
|
clk_i => reg_file[18][9].CLK
|
|
clk_i => reg_file[18][10].CLK
|
|
clk_i => reg_file[18][11].CLK
|
|
clk_i => reg_file[18][12].CLK
|
|
clk_i => reg_file[18][13].CLK
|
|
clk_i => reg_file[18][14].CLK
|
|
clk_i => reg_file[18][15].CLK
|
|
clk_i => reg_file[18][16].CLK
|
|
clk_i => reg_file[18][17].CLK
|
|
clk_i => reg_file[18][18].CLK
|
|
clk_i => reg_file[18][19].CLK
|
|
clk_i => reg_file[18][20].CLK
|
|
clk_i => reg_file[18][21].CLK
|
|
clk_i => reg_file[18][22].CLK
|
|
clk_i => reg_file[18][23].CLK
|
|
clk_i => reg_file[18][24].CLK
|
|
clk_i => reg_file[18][25].CLK
|
|
clk_i => reg_file[18][26].CLK
|
|
clk_i => reg_file[18][27].CLK
|
|
clk_i => reg_file[18][28].CLK
|
|
clk_i => reg_file[18][29].CLK
|
|
clk_i => reg_file[18][30].CLK
|
|
clk_i => reg_file[18][31].CLK
|
|
clk_i => reg_file[19][0].CLK
|
|
clk_i => reg_file[19][1].CLK
|
|
clk_i => reg_file[19][2].CLK
|
|
clk_i => reg_file[19][3].CLK
|
|
clk_i => reg_file[19][4].CLK
|
|
clk_i => reg_file[19][5].CLK
|
|
clk_i => reg_file[19][6].CLK
|
|
clk_i => reg_file[19][7].CLK
|
|
clk_i => reg_file[19][8].CLK
|
|
clk_i => reg_file[19][9].CLK
|
|
clk_i => reg_file[19][10].CLK
|
|
clk_i => reg_file[19][11].CLK
|
|
clk_i => reg_file[19][12].CLK
|
|
clk_i => reg_file[19][13].CLK
|
|
clk_i => reg_file[19][14].CLK
|
|
clk_i => reg_file[19][15].CLK
|
|
clk_i => reg_file[19][16].CLK
|
|
clk_i => reg_file[19][17].CLK
|
|
clk_i => reg_file[19][18].CLK
|
|
clk_i => reg_file[19][19].CLK
|
|
clk_i => reg_file[19][20].CLK
|
|
clk_i => reg_file[19][21].CLK
|
|
clk_i => reg_file[19][22].CLK
|
|
clk_i => reg_file[19][23].CLK
|
|
clk_i => reg_file[19][24].CLK
|
|
clk_i => reg_file[19][25].CLK
|
|
clk_i => reg_file[19][26].CLK
|
|
clk_i => reg_file[19][27].CLK
|
|
clk_i => reg_file[19][28].CLK
|
|
clk_i => reg_file[19][29].CLK
|
|
clk_i => reg_file[19][30].CLK
|
|
clk_i => reg_file[19][31].CLK
|
|
clk_i => reg_file[20][0].CLK
|
|
clk_i => reg_file[20][1].CLK
|
|
clk_i => reg_file[20][2].CLK
|
|
clk_i => reg_file[20][3].CLK
|
|
clk_i => reg_file[20][4].CLK
|
|
clk_i => reg_file[20][5].CLK
|
|
clk_i => reg_file[20][6].CLK
|
|
clk_i => reg_file[20][7].CLK
|
|
clk_i => reg_file[20][8].CLK
|
|
clk_i => reg_file[20][9].CLK
|
|
clk_i => reg_file[20][10].CLK
|
|
clk_i => reg_file[20][11].CLK
|
|
clk_i => reg_file[20][12].CLK
|
|
clk_i => reg_file[20][13].CLK
|
|
clk_i => reg_file[20][14].CLK
|
|
clk_i => reg_file[20][15].CLK
|
|
clk_i => reg_file[20][16].CLK
|
|
clk_i => reg_file[20][17].CLK
|
|
clk_i => reg_file[20][18].CLK
|
|
clk_i => reg_file[20][19].CLK
|
|
clk_i => reg_file[20][20].CLK
|
|
clk_i => reg_file[20][21].CLK
|
|
clk_i => reg_file[20][22].CLK
|
|
clk_i => reg_file[20][23].CLK
|
|
clk_i => reg_file[20][24].CLK
|
|
clk_i => reg_file[20][25].CLK
|
|
clk_i => reg_file[20][26].CLK
|
|
clk_i => reg_file[20][27].CLK
|
|
clk_i => reg_file[20][28].CLK
|
|
clk_i => reg_file[20][29].CLK
|
|
clk_i => reg_file[20][30].CLK
|
|
clk_i => reg_file[20][31].CLK
|
|
clk_i => reg_file[21][0].CLK
|
|
clk_i => reg_file[21][1].CLK
|
|
clk_i => reg_file[21][2].CLK
|
|
clk_i => reg_file[21][3].CLK
|
|
clk_i => reg_file[21][4].CLK
|
|
clk_i => reg_file[21][5].CLK
|
|
clk_i => reg_file[21][6].CLK
|
|
clk_i => reg_file[21][7].CLK
|
|
clk_i => reg_file[21][8].CLK
|
|
clk_i => reg_file[21][9].CLK
|
|
clk_i => reg_file[21][10].CLK
|
|
clk_i => reg_file[21][11].CLK
|
|
clk_i => reg_file[21][12].CLK
|
|
clk_i => reg_file[21][13].CLK
|
|
clk_i => reg_file[21][14].CLK
|
|
clk_i => reg_file[21][15].CLK
|
|
clk_i => reg_file[21][16].CLK
|
|
clk_i => reg_file[21][17].CLK
|
|
clk_i => reg_file[21][18].CLK
|
|
clk_i => reg_file[21][19].CLK
|
|
clk_i => reg_file[21][20].CLK
|
|
clk_i => reg_file[21][21].CLK
|
|
clk_i => reg_file[21][22].CLK
|
|
clk_i => reg_file[21][23].CLK
|
|
clk_i => reg_file[21][24].CLK
|
|
clk_i => reg_file[21][25].CLK
|
|
clk_i => reg_file[21][26].CLK
|
|
clk_i => reg_file[21][27].CLK
|
|
clk_i => reg_file[21][28].CLK
|
|
clk_i => reg_file[21][29].CLK
|
|
clk_i => reg_file[21][30].CLK
|
|
clk_i => reg_file[21][31].CLK
|
|
clk_i => reg_file[22][0].CLK
|
|
clk_i => reg_file[22][1].CLK
|
|
clk_i => reg_file[22][2].CLK
|
|
clk_i => reg_file[22][3].CLK
|
|
clk_i => reg_file[22][4].CLK
|
|
clk_i => reg_file[22][5].CLK
|
|
clk_i => reg_file[22][6].CLK
|
|
clk_i => reg_file[22][7].CLK
|
|
clk_i => reg_file[22][8].CLK
|
|
clk_i => reg_file[22][9].CLK
|
|
clk_i => reg_file[22][10].CLK
|
|
clk_i => reg_file[22][11].CLK
|
|
clk_i => reg_file[22][12].CLK
|
|
clk_i => reg_file[22][13].CLK
|
|
clk_i => reg_file[22][14].CLK
|
|
clk_i => reg_file[22][15].CLK
|
|
clk_i => reg_file[22][16].CLK
|
|
clk_i => reg_file[22][17].CLK
|
|
clk_i => reg_file[22][18].CLK
|
|
clk_i => reg_file[22][19].CLK
|
|
clk_i => reg_file[22][20].CLK
|
|
clk_i => reg_file[22][21].CLK
|
|
clk_i => reg_file[22][22].CLK
|
|
clk_i => reg_file[22][23].CLK
|
|
clk_i => reg_file[22][24].CLK
|
|
clk_i => reg_file[22][25].CLK
|
|
clk_i => reg_file[22][26].CLK
|
|
clk_i => reg_file[22][27].CLK
|
|
clk_i => reg_file[22][28].CLK
|
|
clk_i => reg_file[22][29].CLK
|
|
clk_i => reg_file[22][30].CLK
|
|
clk_i => reg_file[22][31].CLK
|
|
clk_i => reg_file[23][0].CLK
|
|
clk_i => reg_file[23][1].CLK
|
|
clk_i => reg_file[23][2].CLK
|
|
clk_i => reg_file[23][3].CLK
|
|
clk_i => reg_file[23][4].CLK
|
|
clk_i => reg_file[23][5].CLK
|
|
clk_i => reg_file[23][6].CLK
|
|
clk_i => reg_file[23][7].CLK
|
|
clk_i => reg_file[23][8].CLK
|
|
clk_i => reg_file[23][9].CLK
|
|
clk_i => reg_file[23][10].CLK
|
|
clk_i => reg_file[23][11].CLK
|
|
clk_i => reg_file[23][12].CLK
|
|
clk_i => reg_file[23][13].CLK
|
|
clk_i => reg_file[23][14].CLK
|
|
clk_i => reg_file[23][15].CLK
|
|
clk_i => reg_file[23][16].CLK
|
|
clk_i => reg_file[23][17].CLK
|
|
clk_i => reg_file[23][18].CLK
|
|
clk_i => reg_file[23][19].CLK
|
|
clk_i => reg_file[23][20].CLK
|
|
clk_i => reg_file[23][21].CLK
|
|
clk_i => reg_file[23][22].CLK
|
|
clk_i => reg_file[23][23].CLK
|
|
clk_i => reg_file[23][24].CLK
|
|
clk_i => reg_file[23][25].CLK
|
|
clk_i => reg_file[23][26].CLK
|
|
clk_i => reg_file[23][27].CLK
|
|
clk_i => reg_file[23][28].CLK
|
|
clk_i => reg_file[23][29].CLK
|
|
clk_i => reg_file[23][30].CLK
|
|
clk_i => reg_file[23][31].CLK
|
|
clk_i => reg_file[24][0].CLK
|
|
clk_i => reg_file[24][1].CLK
|
|
clk_i => reg_file[24][2].CLK
|
|
clk_i => reg_file[24][3].CLK
|
|
clk_i => reg_file[24][4].CLK
|
|
clk_i => reg_file[24][5].CLK
|
|
clk_i => reg_file[24][6].CLK
|
|
clk_i => reg_file[24][7].CLK
|
|
clk_i => reg_file[24][8].CLK
|
|
clk_i => reg_file[24][9].CLK
|
|
clk_i => reg_file[24][10].CLK
|
|
clk_i => reg_file[24][11].CLK
|
|
clk_i => reg_file[24][12].CLK
|
|
clk_i => reg_file[24][13].CLK
|
|
clk_i => reg_file[24][14].CLK
|
|
clk_i => reg_file[24][15].CLK
|
|
clk_i => reg_file[24][16].CLK
|
|
clk_i => reg_file[24][17].CLK
|
|
clk_i => reg_file[24][18].CLK
|
|
clk_i => reg_file[24][19].CLK
|
|
clk_i => reg_file[24][20].CLK
|
|
clk_i => reg_file[24][21].CLK
|
|
clk_i => reg_file[24][22].CLK
|
|
clk_i => reg_file[24][23].CLK
|
|
clk_i => reg_file[24][24].CLK
|
|
clk_i => reg_file[24][25].CLK
|
|
clk_i => reg_file[24][26].CLK
|
|
clk_i => reg_file[24][27].CLK
|
|
clk_i => reg_file[24][28].CLK
|
|
clk_i => reg_file[24][29].CLK
|
|
clk_i => reg_file[24][30].CLK
|
|
clk_i => reg_file[24][31].CLK
|
|
clk_i => reg_file[25][0].CLK
|
|
clk_i => reg_file[25][1].CLK
|
|
clk_i => reg_file[25][2].CLK
|
|
clk_i => reg_file[25][3].CLK
|
|
clk_i => reg_file[25][4].CLK
|
|
clk_i => reg_file[25][5].CLK
|
|
clk_i => reg_file[25][6].CLK
|
|
clk_i => reg_file[25][7].CLK
|
|
clk_i => reg_file[25][8].CLK
|
|
clk_i => reg_file[25][9].CLK
|
|
clk_i => reg_file[25][10].CLK
|
|
clk_i => reg_file[25][11].CLK
|
|
clk_i => reg_file[25][12].CLK
|
|
clk_i => reg_file[25][13].CLK
|
|
clk_i => reg_file[25][14].CLK
|
|
clk_i => reg_file[25][15].CLK
|
|
clk_i => reg_file[25][16].CLK
|
|
clk_i => reg_file[25][17].CLK
|
|
clk_i => reg_file[25][18].CLK
|
|
clk_i => reg_file[25][19].CLK
|
|
clk_i => reg_file[25][20].CLK
|
|
clk_i => reg_file[25][21].CLK
|
|
clk_i => reg_file[25][22].CLK
|
|
clk_i => reg_file[25][23].CLK
|
|
clk_i => reg_file[25][24].CLK
|
|
clk_i => reg_file[25][25].CLK
|
|
clk_i => reg_file[25][26].CLK
|
|
clk_i => reg_file[25][27].CLK
|
|
clk_i => reg_file[25][28].CLK
|
|
clk_i => reg_file[25][29].CLK
|
|
clk_i => reg_file[25][30].CLK
|
|
clk_i => reg_file[25][31].CLK
|
|
clk_i => reg_file[26][0].CLK
|
|
clk_i => reg_file[26][1].CLK
|
|
clk_i => reg_file[26][2].CLK
|
|
clk_i => reg_file[26][3].CLK
|
|
clk_i => reg_file[26][4].CLK
|
|
clk_i => reg_file[26][5].CLK
|
|
clk_i => reg_file[26][6].CLK
|
|
clk_i => reg_file[26][7].CLK
|
|
clk_i => reg_file[26][8].CLK
|
|
clk_i => reg_file[26][9].CLK
|
|
clk_i => reg_file[26][10].CLK
|
|
clk_i => reg_file[26][11].CLK
|
|
clk_i => reg_file[26][12].CLK
|
|
clk_i => reg_file[26][13].CLK
|
|
clk_i => reg_file[26][14].CLK
|
|
clk_i => reg_file[26][15].CLK
|
|
clk_i => reg_file[26][16].CLK
|
|
clk_i => reg_file[26][17].CLK
|
|
clk_i => reg_file[26][18].CLK
|
|
clk_i => reg_file[26][19].CLK
|
|
clk_i => reg_file[26][20].CLK
|
|
clk_i => reg_file[26][21].CLK
|
|
clk_i => reg_file[26][22].CLK
|
|
clk_i => reg_file[26][23].CLK
|
|
clk_i => reg_file[26][24].CLK
|
|
clk_i => reg_file[26][25].CLK
|
|
clk_i => reg_file[26][26].CLK
|
|
clk_i => reg_file[26][27].CLK
|
|
clk_i => reg_file[26][28].CLK
|
|
clk_i => reg_file[26][29].CLK
|
|
clk_i => reg_file[26][30].CLK
|
|
clk_i => reg_file[26][31].CLK
|
|
clk_i => reg_file[27][0].CLK
|
|
clk_i => reg_file[27][1].CLK
|
|
clk_i => reg_file[27][2].CLK
|
|
clk_i => reg_file[27][3].CLK
|
|
clk_i => reg_file[27][4].CLK
|
|
clk_i => reg_file[27][5].CLK
|
|
clk_i => reg_file[27][6].CLK
|
|
clk_i => reg_file[27][7].CLK
|
|
clk_i => reg_file[27][8].CLK
|
|
clk_i => reg_file[27][9].CLK
|
|
clk_i => reg_file[27][10].CLK
|
|
clk_i => reg_file[27][11].CLK
|
|
clk_i => reg_file[27][12].CLK
|
|
clk_i => reg_file[27][13].CLK
|
|
clk_i => reg_file[27][14].CLK
|
|
clk_i => reg_file[27][15].CLK
|
|
clk_i => reg_file[27][16].CLK
|
|
clk_i => reg_file[27][17].CLK
|
|
clk_i => reg_file[27][18].CLK
|
|
clk_i => reg_file[27][19].CLK
|
|
clk_i => reg_file[27][20].CLK
|
|
clk_i => reg_file[27][21].CLK
|
|
clk_i => reg_file[27][22].CLK
|
|
clk_i => reg_file[27][23].CLK
|
|
clk_i => reg_file[27][24].CLK
|
|
clk_i => reg_file[27][25].CLK
|
|
clk_i => reg_file[27][26].CLK
|
|
clk_i => reg_file[27][27].CLK
|
|
clk_i => reg_file[27][28].CLK
|
|
clk_i => reg_file[27][29].CLK
|
|
clk_i => reg_file[27][30].CLK
|
|
clk_i => reg_file[27][31].CLK
|
|
clk_i => reg_file[28][0].CLK
|
|
clk_i => reg_file[28][1].CLK
|
|
clk_i => reg_file[28][2].CLK
|
|
clk_i => reg_file[28][3].CLK
|
|
clk_i => reg_file[28][4].CLK
|
|
clk_i => reg_file[28][5].CLK
|
|
clk_i => reg_file[28][6].CLK
|
|
clk_i => reg_file[28][7].CLK
|
|
clk_i => reg_file[28][8].CLK
|
|
clk_i => reg_file[28][9].CLK
|
|
clk_i => reg_file[28][10].CLK
|
|
clk_i => reg_file[28][11].CLK
|
|
clk_i => reg_file[28][12].CLK
|
|
clk_i => reg_file[28][13].CLK
|
|
clk_i => reg_file[28][14].CLK
|
|
clk_i => reg_file[28][15].CLK
|
|
clk_i => reg_file[28][16].CLK
|
|
clk_i => reg_file[28][17].CLK
|
|
clk_i => reg_file[28][18].CLK
|
|
clk_i => reg_file[28][19].CLK
|
|
clk_i => reg_file[28][20].CLK
|
|
clk_i => reg_file[28][21].CLK
|
|
clk_i => reg_file[28][22].CLK
|
|
clk_i => reg_file[28][23].CLK
|
|
clk_i => reg_file[28][24].CLK
|
|
clk_i => reg_file[28][25].CLK
|
|
clk_i => reg_file[28][26].CLK
|
|
clk_i => reg_file[28][27].CLK
|
|
clk_i => reg_file[28][28].CLK
|
|
clk_i => reg_file[28][29].CLK
|
|
clk_i => reg_file[28][30].CLK
|
|
clk_i => reg_file[28][31].CLK
|
|
clk_i => reg_file[29][0].CLK
|
|
clk_i => reg_file[29][1].CLK
|
|
clk_i => reg_file[29][2].CLK
|
|
clk_i => reg_file[29][3].CLK
|
|
clk_i => reg_file[29][4].CLK
|
|
clk_i => reg_file[29][5].CLK
|
|
clk_i => reg_file[29][6].CLK
|
|
clk_i => reg_file[29][7].CLK
|
|
clk_i => reg_file[29][8].CLK
|
|
clk_i => reg_file[29][9].CLK
|
|
clk_i => reg_file[29][10].CLK
|
|
clk_i => reg_file[29][11].CLK
|
|
clk_i => reg_file[29][12].CLK
|
|
clk_i => reg_file[29][13].CLK
|
|
clk_i => reg_file[29][14].CLK
|
|
clk_i => reg_file[29][15].CLK
|
|
clk_i => reg_file[29][16].CLK
|
|
clk_i => reg_file[29][17].CLK
|
|
clk_i => reg_file[29][18].CLK
|
|
clk_i => reg_file[29][19].CLK
|
|
clk_i => reg_file[29][20].CLK
|
|
clk_i => reg_file[29][21].CLK
|
|
clk_i => reg_file[29][22].CLK
|
|
clk_i => reg_file[29][23].CLK
|
|
clk_i => reg_file[29][24].CLK
|
|
clk_i => reg_file[29][25].CLK
|
|
clk_i => reg_file[29][26].CLK
|
|
clk_i => reg_file[29][27].CLK
|
|
clk_i => reg_file[29][28].CLK
|
|
clk_i => reg_file[29][29].CLK
|
|
clk_i => reg_file[29][30].CLK
|
|
clk_i => reg_file[29][31].CLK
|
|
clk_i => reg_file[30][0].CLK
|
|
clk_i => reg_file[30][1].CLK
|
|
clk_i => reg_file[30][2].CLK
|
|
clk_i => reg_file[30][3].CLK
|
|
clk_i => reg_file[30][4].CLK
|
|
clk_i => reg_file[30][5].CLK
|
|
clk_i => reg_file[30][6].CLK
|
|
clk_i => reg_file[30][7].CLK
|
|
clk_i => reg_file[30][8].CLK
|
|
clk_i => reg_file[30][9].CLK
|
|
clk_i => reg_file[30][10].CLK
|
|
clk_i => reg_file[30][11].CLK
|
|
clk_i => reg_file[30][12].CLK
|
|
clk_i => reg_file[30][13].CLK
|
|
clk_i => reg_file[30][14].CLK
|
|
clk_i => reg_file[30][15].CLK
|
|
clk_i => reg_file[30][16].CLK
|
|
clk_i => reg_file[30][17].CLK
|
|
clk_i => reg_file[30][18].CLK
|
|
clk_i => reg_file[30][19].CLK
|
|
clk_i => reg_file[30][20].CLK
|
|
clk_i => reg_file[30][21].CLK
|
|
clk_i => reg_file[30][22].CLK
|
|
clk_i => reg_file[30][23].CLK
|
|
clk_i => reg_file[30][24].CLK
|
|
clk_i => reg_file[30][25].CLK
|
|
clk_i => reg_file[30][26].CLK
|
|
clk_i => reg_file[30][27].CLK
|
|
clk_i => reg_file[30][28].CLK
|
|
clk_i => reg_file[30][29].CLK
|
|
clk_i => reg_file[30][30].CLK
|
|
clk_i => reg_file[30][31].CLK
|
|
clk_i => reg_file[31][0].CLK
|
|
clk_i => reg_file[31][1].CLK
|
|
clk_i => reg_file[31][2].CLK
|
|
clk_i => reg_file[31][3].CLK
|
|
clk_i => reg_file[31][4].CLK
|
|
clk_i => reg_file[31][5].CLK
|
|
clk_i => reg_file[31][6].CLK
|
|
clk_i => reg_file[31][7].CLK
|
|
clk_i => reg_file[31][8].CLK
|
|
clk_i => reg_file[31][9].CLK
|
|
clk_i => reg_file[31][10].CLK
|
|
clk_i => reg_file[31][11].CLK
|
|
clk_i => reg_file[31][12].CLK
|
|
clk_i => reg_file[31][13].CLK
|
|
clk_i => reg_file[31][14].CLK
|
|
clk_i => reg_file[31][15].CLK
|
|
clk_i => reg_file[31][16].CLK
|
|
clk_i => reg_file[31][17].CLK
|
|
clk_i => reg_file[31][18].CLK
|
|
clk_i => reg_file[31][19].CLK
|
|
clk_i => reg_file[31][20].CLK
|
|
clk_i => reg_file[31][21].CLK
|
|
clk_i => reg_file[31][22].CLK
|
|
clk_i => reg_file[31][23].CLK
|
|
clk_i => reg_file[31][24].CLK
|
|
clk_i => reg_file[31][25].CLK
|
|
clk_i => reg_file[31][26].CLK
|
|
clk_i => reg_file[31][27].CLK
|
|
clk_i => reg_file[31][28].CLK
|
|
clk_i => reg_file[31][29].CLK
|
|
clk_i => reg_file[31][30].CLK
|
|
clk_i => reg_file[31][31].CLK
|
|
clk_i => altsyncram:reg_file[0][31]__1.clock0
|
|
clk_i => altsyncram:reg_file[0][31]__2.clock0
|
|
ctrl_i[0] => opa_addr.OUTPUTSELECT
|
|
ctrl_i[0] => opa_addr.OUTPUTSELECT
|
|
ctrl_i[0] => opa_addr.OUTPUTSELECT
|
|
ctrl_i[0] => opa_addr.OUTPUTSELECT
|
|
ctrl_i[0] => opa_addr.OUTPUTSELECT
|
|
ctrl_i[0] => rf_we.IN1
|
|
ctrl_i[1] => opa_addr.DATAA
|
|
ctrl_i[2] => opa_addr.DATAA
|
|
ctrl_i[3] => opa_addr.DATAA
|
|
ctrl_i[4] => opa_addr.DATAA
|
|
ctrl_i[5] => opa_addr.DATAA
|
|
ctrl_i[6] => altsyncram:reg_file[0][31]__2.address_b[0]
|
|
ctrl_i[7] => altsyncram:reg_file[0][31]__2.address_b[1]
|
|
ctrl_i[8] => altsyncram:reg_file[0][31]__2.address_b[2]
|
|
ctrl_i[9] => altsyncram:reg_file[0][31]__2.address_b[3]
|
|
ctrl_i[10] => altsyncram:reg_file[0][31]__2.address_b[4]
|
|
ctrl_i[11] => ~NO_FANOUT~
|
|
ctrl_i[12] => ~NO_FANOUT~
|
|
ctrl_i[13] => ~NO_FANOUT~
|
|
ctrl_i[14] => ~NO_FANOUT~
|
|
ctrl_i[15] => ~NO_FANOUT~
|
|
ctrl_i[16] => opa_addr.DATAB
|
|
ctrl_i[16] => Equal0.IN4
|
|
ctrl_i[17] => opa_addr.DATAB
|
|
ctrl_i[17] => Equal0.IN3
|
|
ctrl_i[18] => opa_addr.DATAB
|
|
ctrl_i[18] => Equal0.IN2
|
|
ctrl_i[19] => opa_addr.DATAB
|
|
ctrl_i[19] => Equal0.IN1
|
|
ctrl_i[20] => opa_addr.DATAB
|
|
ctrl_i[20] => Equal0.IN0
|
|
ctrl_i[21] => Mux0.IN1
|
|
ctrl_i[21] => Mux1.IN1
|
|
ctrl_i[21] => Mux2.IN1
|
|
ctrl_i[21] => Mux3.IN1
|
|
ctrl_i[21] => Mux4.IN1
|
|
ctrl_i[21] => Mux5.IN1
|
|
ctrl_i[21] => Mux6.IN1
|
|
ctrl_i[21] => Mux7.IN1
|
|
ctrl_i[21] => Mux8.IN1
|
|
ctrl_i[21] => Mux9.IN1
|
|
ctrl_i[21] => Mux10.IN1
|
|
ctrl_i[21] => Mux11.IN1
|
|
ctrl_i[21] => Mux12.IN1
|
|
ctrl_i[21] => Mux13.IN1
|
|
ctrl_i[21] => Mux14.IN1
|
|
ctrl_i[21] => Mux15.IN1
|
|
ctrl_i[21] => Mux16.IN1
|
|
ctrl_i[21] => Mux17.IN1
|
|
ctrl_i[21] => Mux18.IN1
|
|
ctrl_i[21] => Mux19.IN1
|
|
ctrl_i[21] => Mux20.IN1
|
|
ctrl_i[21] => Mux21.IN1
|
|
ctrl_i[21] => Mux22.IN1
|
|
ctrl_i[21] => Mux23.IN1
|
|
ctrl_i[21] => Mux24.IN1
|
|
ctrl_i[21] => Mux25.IN1
|
|
ctrl_i[21] => Mux26.IN1
|
|
ctrl_i[21] => Mux27.IN1
|
|
ctrl_i[21] => Mux28.IN1
|
|
ctrl_i[21] => Mux29.IN1
|
|
ctrl_i[21] => Mux30.IN1
|
|
ctrl_i[21] => Mux31.IN1
|
|
ctrl_i[22] => Mux0.IN0
|
|
ctrl_i[22] => Mux1.IN0
|
|
ctrl_i[22] => Mux2.IN0
|
|
ctrl_i[22] => Mux3.IN0
|
|
ctrl_i[22] => Mux4.IN0
|
|
ctrl_i[22] => Mux5.IN0
|
|
ctrl_i[22] => Mux6.IN0
|
|
ctrl_i[22] => Mux7.IN0
|
|
ctrl_i[22] => Mux8.IN0
|
|
ctrl_i[22] => Mux9.IN0
|
|
ctrl_i[22] => Mux10.IN0
|
|
ctrl_i[22] => Mux11.IN0
|
|
ctrl_i[22] => Mux12.IN0
|
|
ctrl_i[22] => Mux13.IN0
|
|
ctrl_i[22] => Mux14.IN0
|
|
ctrl_i[22] => Mux15.IN0
|
|
ctrl_i[22] => Mux16.IN0
|
|
ctrl_i[22] => Mux17.IN0
|
|
ctrl_i[22] => Mux18.IN0
|
|
ctrl_i[22] => Mux19.IN0
|
|
ctrl_i[22] => Mux20.IN0
|
|
ctrl_i[22] => Mux21.IN0
|
|
ctrl_i[22] => Mux22.IN0
|
|
ctrl_i[22] => Mux23.IN0
|
|
ctrl_i[22] => Mux24.IN0
|
|
ctrl_i[22] => Mux25.IN0
|
|
ctrl_i[22] => Mux26.IN0
|
|
ctrl_i[22] => Mux27.IN0
|
|
ctrl_i[22] => Mux28.IN0
|
|
ctrl_i[22] => Mux29.IN0
|
|
ctrl_i[22] => Mux30.IN0
|
|
ctrl_i[22] => Mux31.IN0
|
|
ctrl_i[23] => opa_addr[4].OUTPUTSELECT
|
|
ctrl_i[23] => opa_addr[3].OUTPUTSELECT
|
|
ctrl_i[23] => opa_addr[2].OUTPUTSELECT
|
|
ctrl_i[23] => opa_addr[1].OUTPUTSELECT
|
|
ctrl_i[23] => opa_addr[0].OUTPUTSELECT
|
|
ctrl_i[23] => rf_we.IN1
|
|
ctrl_i[24] => ~NO_FANOUT~
|
|
ctrl_i[25] => ~NO_FANOUT~
|
|
ctrl_i[26] => ~NO_FANOUT~
|
|
ctrl_i[27] => ~NO_FANOUT~
|
|
ctrl_i[28] => ~NO_FANOUT~
|
|
ctrl_i[29] => ~NO_FANOUT~
|
|
ctrl_i[30] => ~NO_FANOUT~
|
|
ctrl_i[31] => ~NO_FANOUT~
|
|
ctrl_i[32] => ~NO_FANOUT~
|
|
ctrl_i[33] => ~NO_FANOUT~
|
|
ctrl_i[34] => ~NO_FANOUT~
|
|
ctrl_i[35] => ~NO_FANOUT~
|
|
ctrl_i[36] => ~NO_FANOUT~
|
|
ctrl_i[37] => ~NO_FANOUT~
|
|
ctrl_i[38] => ~NO_FANOUT~
|
|
ctrl_i[39] => ~NO_FANOUT~
|
|
ctrl_i[40] => ~NO_FANOUT~
|
|
ctrl_i[41] => ~NO_FANOUT~
|
|
ctrl_i[42] => ~NO_FANOUT~
|
|
ctrl_i[43] => ~NO_FANOUT~
|
|
ctrl_i[44] => ~NO_FANOUT~
|
|
ctrl_i[45] => ~NO_FANOUT~
|
|
ctrl_i[46] => ~NO_FANOUT~
|
|
ctrl_i[47] => ~NO_FANOUT~
|
|
ctrl_i[48] => ~NO_FANOUT~
|
|
ctrl_i[49] => ~NO_FANOUT~
|
|
ctrl_i[50] => ~NO_FANOUT~
|
|
ctrl_i[51] => ~NO_FANOUT~
|
|
ctrl_i[52] => ~NO_FANOUT~
|
|
ctrl_i[53] => ~NO_FANOUT~
|
|
ctrl_i[54] => ~NO_FANOUT~
|
|
ctrl_i[55] => ~NO_FANOUT~
|
|
ctrl_i[56] => ~NO_FANOUT~
|
|
ctrl_i[57] => ~NO_FANOUT~
|
|
ctrl_i[58] => ~NO_FANOUT~
|
|
ctrl_i[59] => ~NO_FANOUT~
|
|
ctrl_i[60] => ~NO_FANOUT~
|
|
ctrl_i[61] => ~NO_FANOUT~
|
|
ctrl_i[62] => ~NO_FANOUT~
|
|
ctrl_i[63] => ~NO_FANOUT~
|
|
ctrl_i[64] => ~NO_FANOUT~
|
|
ctrl_i[65] => ~NO_FANOUT~
|
|
ctrl_i[66] => ~NO_FANOUT~
|
|
ctrl_i[67] => ~NO_FANOUT~
|
|
ctrl_i[68] => ~NO_FANOUT~
|
|
alu_i[0] => Mux31.IN2
|
|
alu_i[1] => Mux30.IN2
|
|
alu_i[2] => Mux29.IN2
|
|
alu_i[3] => Mux28.IN2
|
|
alu_i[4] => Mux27.IN2
|
|
alu_i[5] => Mux26.IN2
|
|
alu_i[6] => Mux25.IN2
|
|
alu_i[7] => Mux24.IN2
|
|
alu_i[8] => Mux23.IN2
|
|
alu_i[9] => Mux22.IN2
|
|
alu_i[10] => Mux21.IN2
|
|
alu_i[11] => Mux20.IN2
|
|
alu_i[12] => Mux19.IN2
|
|
alu_i[13] => Mux18.IN2
|
|
alu_i[14] => Mux17.IN2
|
|
alu_i[15] => Mux16.IN2
|
|
alu_i[16] => Mux15.IN2
|
|
alu_i[17] => Mux14.IN2
|
|
alu_i[18] => Mux13.IN2
|
|
alu_i[19] => Mux12.IN2
|
|
alu_i[20] => Mux11.IN2
|
|
alu_i[21] => Mux10.IN2
|
|
alu_i[22] => Mux9.IN2
|
|
alu_i[23] => Mux8.IN2
|
|
alu_i[24] => Mux7.IN2
|
|
alu_i[25] => Mux6.IN2
|
|
alu_i[26] => Mux5.IN2
|
|
alu_i[27] => Mux4.IN2
|
|
alu_i[28] => Mux3.IN2
|
|
alu_i[29] => Mux2.IN2
|
|
alu_i[30] => Mux1.IN2
|
|
alu_i[31] => Mux0.IN2
|
|
mem_i[0] => Mux31.IN3
|
|
mem_i[1] => Mux30.IN3
|
|
mem_i[2] => Mux29.IN3
|
|
mem_i[3] => Mux28.IN3
|
|
mem_i[4] => Mux27.IN3
|
|
mem_i[5] => Mux26.IN3
|
|
mem_i[6] => Mux25.IN3
|
|
mem_i[7] => Mux24.IN3
|
|
mem_i[8] => Mux23.IN3
|
|
mem_i[9] => Mux22.IN3
|
|
mem_i[10] => Mux21.IN3
|
|
mem_i[11] => Mux20.IN3
|
|
mem_i[12] => Mux19.IN3
|
|
mem_i[13] => Mux18.IN3
|
|
mem_i[14] => Mux17.IN3
|
|
mem_i[15] => Mux16.IN3
|
|
mem_i[16] => Mux15.IN3
|
|
mem_i[17] => Mux14.IN3
|
|
mem_i[18] => Mux13.IN3
|
|
mem_i[19] => Mux12.IN3
|
|
mem_i[20] => Mux11.IN3
|
|
mem_i[21] => Mux10.IN3
|
|
mem_i[22] => Mux9.IN3
|
|
mem_i[23] => Mux8.IN3
|
|
mem_i[24] => Mux7.IN3
|
|
mem_i[25] => Mux6.IN3
|
|
mem_i[26] => Mux5.IN3
|
|
mem_i[27] => Mux4.IN3
|
|
mem_i[28] => Mux3.IN3
|
|
mem_i[29] => Mux2.IN3
|
|
mem_i[30] => Mux1.IN3
|
|
mem_i[31] => Mux0.IN3
|
|
csr_i[0] => Mux31.IN4
|
|
csr_i[1] => Mux30.IN4
|
|
csr_i[2] => Mux29.IN4
|
|
csr_i[3] => Mux28.IN4
|
|
csr_i[4] => Mux27.IN4
|
|
csr_i[5] => Mux26.IN4
|
|
csr_i[6] => Mux25.IN4
|
|
csr_i[7] => Mux24.IN4
|
|
csr_i[8] => Mux23.IN4
|
|
csr_i[9] => Mux22.IN4
|
|
csr_i[10] => Mux21.IN4
|
|
csr_i[11] => Mux20.IN4
|
|
csr_i[12] => Mux19.IN4
|
|
csr_i[13] => Mux18.IN4
|
|
csr_i[14] => Mux17.IN4
|
|
csr_i[15] => Mux16.IN4
|
|
csr_i[16] => Mux15.IN4
|
|
csr_i[17] => Mux14.IN4
|
|
csr_i[18] => Mux13.IN4
|
|
csr_i[19] => Mux12.IN4
|
|
csr_i[20] => Mux11.IN4
|
|
csr_i[21] => Mux10.IN4
|
|
csr_i[22] => Mux9.IN4
|
|
csr_i[23] => Mux8.IN4
|
|
csr_i[24] => Mux7.IN4
|
|
csr_i[25] => Mux6.IN4
|
|
csr_i[26] => Mux5.IN4
|
|
csr_i[27] => Mux4.IN4
|
|
csr_i[28] => Mux3.IN4
|
|
csr_i[29] => Mux2.IN4
|
|
csr_i[30] => Mux1.IN4
|
|
csr_i[31] => Mux0.IN4
|
|
pc2_i[0] => Mux31.IN5
|
|
pc2_i[1] => Mux30.IN5
|
|
pc2_i[2] => Mux29.IN5
|
|
pc2_i[3] => Mux28.IN5
|
|
pc2_i[4] => Mux27.IN5
|
|
pc2_i[5] => Mux26.IN5
|
|
pc2_i[6] => Mux25.IN5
|
|
pc2_i[7] => Mux24.IN5
|
|
pc2_i[8] => Mux23.IN5
|
|
pc2_i[9] => Mux22.IN5
|
|
pc2_i[10] => Mux21.IN5
|
|
pc2_i[11] => Mux20.IN5
|
|
pc2_i[12] => Mux19.IN5
|
|
pc2_i[13] => Mux18.IN5
|
|
pc2_i[14] => Mux17.IN5
|
|
pc2_i[15] => Mux16.IN5
|
|
pc2_i[16] => Mux15.IN5
|
|
pc2_i[17] => Mux14.IN5
|
|
pc2_i[18] => Mux13.IN5
|
|
pc2_i[19] => Mux12.IN5
|
|
pc2_i[20] => Mux11.IN5
|
|
pc2_i[21] => Mux10.IN5
|
|
pc2_i[22] => Mux9.IN5
|
|
pc2_i[23] => Mux8.IN5
|
|
pc2_i[24] => Mux7.IN5
|
|
pc2_i[25] => Mux6.IN5
|
|
pc2_i[26] => Mux5.IN5
|
|
pc2_i[27] => Mux4.IN5
|
|
pc2_i[28] => Mux3.IN5
|
|
pc2_i[29] => Mux2.IN5
|
|
pc2_i[30] => Mux1.IN5
|
|
pc2_i[31] => Mux0.IN5
|
|
rs1_o[0] <= altsyncram:reg_file[0][31]__1.q_b[31]
|
|
rs1_o[1] <= altsyncram:reg_file[0][31]__1.q_b[30]
|
|
rs1_o[2] <= altsyncram:reg_file[0][31]__1.q_b[29]
|
|
rs1_o[3] <= altsyncram:reg_file[0][31]__1.q_b[28]
|
|
rs1_o[4] <= altsyncram:reg_file[0][31]__1.q_b[27]
|
|
rs1_o[5] <= altsyncram:reg_file[0][31]__1.q_b[26]
|
|
rs1_o[6] <= altsyncram:reg_file[0][31]__1.q_b[25]
|
|
rs1_o[7] <= altsyncram:reg_file[0][31]__1.q_b[24]
|
|
rs1_o[8] <= altsyncram:reg_file[0][31]__1.q_b[23]
|
|
rs1_o[9] <= altsyncram:reg_file[0][31]__1.q_b[22]
|
|
rs1_o[10] <= altsyncram:reg_file[0][31]__1.q_b[21]
|
|
rs1_o[11] <= altsyncram:reg_file[0][31]__1.q_b[20]
|
|
rs1_o[12] <= altsyncram:reg_file[0][31]__1.q_b[19]
|
|
rs1_o[13] <= altsyncram:reg_file[0][31]__1.q_b[18]
|
|
rs1_o[14] <= altsyncram:reg_file[0][31]__1.q_b[17]
|
|
rs1_o[15] <= altsyncram:reg_file[0][31]__1.q_b[16]
|
|
rs1_o[16] <= altsyncram:reg_file[0][31]__1.q_b[15]
|
|
rs1_o[17] <= altsyncram:reg_file[0][31]__1.q_b[14]
|
|
rs1_o[18] <= altsyncram:reg_file[0][31]__1.q_b[13]
|
|
rs1_o[19] <= altsyncram:reg_file[0][31]__1.q_b[12]
|
|
rs1_o[20] <= altsyncram:reg_file[0][31]__1.q_b[11]
|
|
rs1_o[21] <= altsyncram:reg_file[0][31]__1.q_b[10]
|
|
rs1_o[22] <= altsyncram:reg_file[0][31]__1.q_b[9]
|
|
rs1_o[23] <= altsyncram:reg_file[0][31]__1.q_b[8]
|
|
rs1_o[24] <= altsyncram:reg_file[0][31]__1.q_b[7]
|
|
rs1_o[25] <= altsyncram:reg_file[0][31]__1.q_b[6]
|
|
rs1_o[26] <= altsyncram:reg_file[0][31]__1.q_b[5]
|
|
rs1_o[27] <= altsyncram:reg_file[0][31]__1.q_b[4]
|
|
rs1_o[28] <= altsyncram:reg_file[0][31]__1.q_b[3]
|
|
rs1_o[29] <= altsyncram:reg_file[0][31]__1.q_b[2]
|
|
rs1_o[30] <= altsyncram:reg_file[0][31]__1.q_b[1]
|
|
rs1_o[31] <= altsyncram:reg_file[0][31]__1.q_b[0]
|
|
rs2_o[0] <= altsyncram:reg_file[0][31]__2.q_b[31]
|
|
rs2_o[1] <= altsyncram:reg_file[0][31]__2.q_b[30]
|
|
rs2_o[2] <= altsyncram:reg_file[0][31]__2.q_b[29]
|
|
rs2_o[3] <= altsyncram:reg_file[0][31]__2.q_b[28]
|
|
rs2_o[4] <= altsyncram:reg_file[0][31]__2.q_b[27]
|
|
rs2_o[5] <= altsyncram:reg_file[0][31]__2.q_b[26]
|
|
rs2_o[6] <= altsyncram:reg_file[0][31]__2.q_b[25]
|
|
rs2_o[7] <= altsyncram:reg_file[0][31]__2.q_b[24]
|
|
rs2_o[8] <= altsyncram:reg_file[0][31]__2.q_b[23]
|
|
rs2_o[9] <= altsyncram:reg_file[0][31]__2.q_b[22]
|
|
rs2_o[10] <= altsyncram:reg_file[0][31]__2.q_b[21]
|
|
rs2_o[11] <= altsyncram:reg_file[0][31]__2.q_b[20]
|
|
rs2_o[12] <= altsyncram:reg_file[0][31]__2.q_b[19]
|
|
rs2_o[13] <= altsyncram:reg_file[0][31]__2.q_b[18]
|
|
rs2_o[14] <= altsyncram:reg_file[0][31]__2.q_b[17]
|
|
rs2_o[15] <= altsyncram:reg_file[0][31]__2.q_b[16]
|
|
rs2_o[16] <= altsyncram:reg_file[0][31]__2.q_b[15]
|
|
rs2_o[17] <= altsyncram:reg_file[0][31]__2.q_b[14]
|
|
rs2_o[18] <= altsyncram:reg_file[0][31]__2.q_b[13]
|
|
rs2_o[19] <= altsyncram:reg_file[0][31]__2.q_b[12]
|
|
rs2_o[20] <= altsyncram:reg_file[0][31]__2.q_b[11]
|
|
rs2_o[21] <= altsyncram:reg_file[0][31]__2.q_b[10]
|
|
rs2_o[22] <= altsyncram:reg_file[0][31]__2.q_b[9]
|
|
rs2_o[23] <= altsyncram:reg_file[0][31]__2.q_b[8]
|
|
rs2_o[24] <= altsyncram:reg_file[0][31]__2.q_b[7]
|
|
rs2_o[25] <= altsyncram:reg_file[0][31]__2.q_b[6]
|
|
rs2_o[26] <= altsyncram:reg_file[0][31]__2.q_b[5]
|
|
rs2_o[27] <= altsyncram:reg_file[0][31]__2.q_b[4]
|
|
rs2_o[28] <= altsyncram:reg_file[0][31]__2.q_b[3]
|
|
rs2_o[29] <= altsyncram:reg_file[0][31]__2.q_b[2]
|
|
rs2_o[30] <= altsyncram:reg_file[0][31]__2.q_b[1]
|
|
rs2_o[31] <= altsyncram:reg_file[0][31]__2.q_b[0]
|
|
rs3_o[0] <= rs3_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[1] <= rs3_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[2] <= rs3_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[3] <= rs3_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[4] <= rs3_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[5] <= rs3_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[6] <= rs3_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[7] <= rs3_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[8] <= rs3_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[9] <= rs3_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[10] <= rs3_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[11] <= rs3_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[12] <= rs3_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[13] <= rs3_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[14] <= rs3_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[15] <= rs3_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[16] <= rs3_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[17] <= rs3_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[18] <= rs3_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[19] <= rs3_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[20] <= rs3_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[21] <= rs3_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[22] <= rs3_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[23] <= rs3_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[24] <= rs3_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[25] <= rs3_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[26] <= rs3_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[27] <= rs3_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[28] <= rs3_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[29] <= rs3_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[30] <= rs3_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs3_o[31] <= rs3_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[0] <= rs4_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[1] <= rs4_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[2] <= rs4_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[3] <= rs4_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[4] <= rs4_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[5] <= rs4_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[6] <= rs4_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[7] <= rs4_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[8] <= rs4_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[9] <= rs4_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[10] <= rs4_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[11] <= rs4_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[12] <= rs4_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[13] <= rs4_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[14] <= rs4_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[15] <= rs4_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[16] <= rs4_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[17] <= rs4_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[18] <= rs4_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[19] <= rs4_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[20] <= rs4_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[21] <= rs4_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[22] <= rs4_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[23] <= rs4_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[24] <= rs4_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[25] <= rs4_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[26] <= rs4_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[27] <= rs4_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[28] <= rs4_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[29] <= rs4_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[30] <= rs4_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rs4_o[31] <= rs4_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_regfile:neorv32_cpu_regfile_inst|altsyncram:reg_file[0][31]__1
|
|
wren_a => altsyncram_u2n1:auto_generated.wren_a
|
|
rden_a => ~NO_FANOUT~
|
|
wren_b => ~NO_FANOUT~
|
|
rden_b => ~NO_FANOUT~
|
|
data_a[0] => altsyncram_u2n1:auto_generated.data_a[0]
|
|
data_a[1] => altsyncram_u2n1:auto_generated.data_a[1]
|
|
data_a[2] => altsyncram_u2n1:auto_generated.data_a[2]
|
|
data_a[3] => altsyncram_u2n1:auto_generated.data_a[3]
|
|
data_a[4] => altsyncram_u2n1:auto_generated.data_a[4]
|
|
data_a[5] => altsyncram_u2n1:auto_generated.data_a[5]
|
|
data_a[6] => altsyncram_u2n1:auto_generated.data_a[6]
|
|
data_a[7] => altsyncram_u2n1:auto_generated.data_a[7]
|
|
data_a[8] => altsyncram_u2n1:auto_generated.data_a[8]
|
|
data_a[9] => altsyncram_u2n1:auto_generated.data_a[9]
|
|
data_a[10] => altsyncram_u2n1:auto_generated.data_a[10]
|
|
data_a[11] => altsyncram_u2n1:auto_generated.data_a[11]
|
|
data_a[12] => altsyncram_u2n1:auto_generated.data_a[12]
|
|
data_a[13] => altsyncram_u2n1:auto_generated.data_a[13]
|
|
data_a[14] => altsyncram_u2n1:auto_generated.data_a[14]
|
|
data_a[15] => altsyncram_u2n1:auto_generated.data_a[15]
|
|
data_a[16] => altsyncram_u2n1:auto_generated.data_a[16]
|
|
data_a[17] => altsyncram_u2n1:auto_generated.data_a[17]
|
|
data_a[18] => altsyncram_u2n1:auto_generated.data_a[18]
|
|
data_a[19] => altsyncram_u2n1:auto_generated.data_a[19]
|
|
data_a[20] => altsyncram_u2n1:auto_generated.data_a[20]
|
|
data_a[21] => altsyncram_u2n1:auto_generated.data_a[21]
|
|
data_a[22] => altsyncram_u2n1:auto_generated.data_a[22]
|
|
data_a[23] => altsyncram_u2n1:auto_generated.data_a[23]
|
|
data_a[24] => altsyncram_u2n1:auto_generated.data_a[24]
|
|
data_a[25] => altsyncram_u2n1:auto_generated.data_a[25]
|
|
data_a[26] => altsyncram_u2n1:auto_generated.data_a[26]
|
|
data_a[27] => altsyncram_u2n1:auto_generated.data_a[27]
|
|
data_a[28] => altsyncram_u2n1:auto_generated.data_a[28]
|
|
data_a[29] => altsyncram_u2n1:auto_generated.data_a[29]
|
|
data_a[30] => altsyncram_u2n1:auto_generated.data_a[30]
|
|
data_a[31] => altsyncram_u2n1:auto_generated.data_a[31]
|
|
data_b[0] => ~NO_FANOUT~
|
|
data_b[1] => ~NO_FANOUT~
|
|
data_b[2] => ~NO_FANOUT~
|
|
data_b[3] => ~NO_FANOUT~
|
|
data_b[4] => ~NO_FANOUT~
|
|
data_b[5] => ~NO_FANOUT~
|
|
data_b[6] => ~NO_FANOUT~
|
|
data_b[7] => ~NO_FANOUT~
|
|
data_b[8] => ~NO_FANOUT~
|
|
data_b[9] => ~NO_FANOUT~
|
|
data_b[10] => ~NO_FANOUT~
|
|
data_b[11] => ~NO_FANOUT~
|
|
data_b[12] => ~NO_FANOUT~
|
|
data_b[13] => ~NO_FANOUT~
|
|
data_b[14] => ~NO_FANOUT~
|
|
data_b[15] => ~NO_FANOUT~
|
|
data_b[16] => ~NO_FANOUT~
|
|
data_b[17] => ~NO_FANOUT~
|
|
data_b[18] => ~NO_FANOUT~
|
|
data_b[19] => ~NO_FANOUT~
|
|
data_b[20] => ~NO_FANOUT~
|
|
data_b[21] => ~NO_FANOUT~
|
|
data_b[22] => ~NO_FANOUT~
|
|
data_b[23] => ~NO_FANOUT~
|
|
data_b[24] => ~NO_FANOUT~
|
|
data_b[25] => ~NO_FANOUT~
|
|
data_b[26] => ~NO_FANOUT~
|
|
data_b[27] => ~NO_FANOUT~
|
|
data_b[28] => ~NO_FANOUT~
|
|
data_b[29] => ~NO_FANOUT~
|
|
data_b[30] => ~NO_FANOUT~
|
|
data_b[31] => ~NO_FANOUT~
|
|
address_a[0] => altsyncram_u2n1:auto_generated.address_a[0]
|
|
address_a[1] => altsyncram_u2n1:auto_generated.address_a[1]
|
|
address_a[2] => altsyncram_u2n1:auto_generated.address_a[2]
|
|
address_a[3] => altsyncram_u2n1:auto_generated.address_a[3]
|
|
address_a[4] => altsyncram_u2n1:auto_generated.address_a[4]
|
|
address_b[0] => altsyncram_u2n1:auto_generated.address_b[0]
|
|
address_b[1] => altsyncram_u2n1:auto_generated.address_b[1]
|
|
address_b[2] => altsyncram_u2n1:auto_generated.address_b[2]
|
|
address_b[3] => altsyncram_u2n1:auto_generated.address_b[3]
|
|
address_b[4] => altsyncram_u2n1:auto_generated.address_b[4]
|
|
addressstall_a => ~NO_FANOUT~
|
|
addressstall_b => ~NO_FANOUT~
|
|
clock0 => altsyncram_u2n1:auto_generated.clock0
|
|
clock1 => ~NO_FANOUT~
|
|
clocken0 => ~NO_FANOUT~
|
|
clocken1 => ~NO_FANOUT~
|
|
clocken2 => ~NO_FANOUT~
|
|
clocken3 => ~NO_FANOUT~
|
|
aclr0 => ~NO_FANOUT~
|
|
aclr1 => ~NO_FANOUT~
|
|
byteena_a[0] => ~NO_FANOUT~
|
|
byteena_b[0] => ~NO_FANOUT~
|
|
q_a[0] <= <GND>
|
|
q_a[1] <= <GND>
|
|
q_a[2] <= <GND>
|
|
q_a[3] <= <GND>
|
|
q_a[4] <= <GND>
|
|
q_a[5] <= <GND>
|
|
q_a[6] <= <GND>
|
|
q_a[7] <= <GND>
|
|
q_a[8] <= <GND>
|
|
q_a[9] <= <GND>
|
|
q_a[10] <= <GND>
|
|
q_a[11] <= <GND>
|
|
q_a[12] <= <GND>
|
|
q_a[13] <= <GND>
|
|
q_a[14] <= <GND>
|
|
q_a[15] <= <GND>
|
|
q_a[16] <= <GND>
|
|
q_a[17] <= <GND>
|
|
q_a[18] <= <GND>
|
|
q_a[19] <= <GND>
|
|
q_a[20] <= <GND>
|
|
q_a[21] <= <GND>
|
|
q_a[22] <= <GND>
|
|
q_a[23] <= <GND>
|
|
q_a[24] <= <GND>
|
|
q_a[25] <= <GND>
|
|
q_a[26] <= <GND>
|
|
q_a[27] <= <GND>
|
|
q_a[28] <= <GND>
|
|
q_a[29] <= <GND>
|
|
q_a[30] <= <GND>
|
|
q_a[31] <= <GND>
|
|
q_b[0] <= altsyncram_u2n1:auto_generated.q_b[0]
|
|
q_b[1] <= altsyncram_u2n1:auto_generated.q_b[1]
|
|
q_b[2] <= altsyncram_u2n1:auto_generated.q_b[2]
|
|
q_b[3] <= altsyncram_u2n1:auto_generated.q_b[3]
|
|
q_b[4] <= altsyncram_u2n1:auto_generated.q_b[4]
|
|
q_b[5] <= altsyncram_u2n1:auto_generated.q_b[5]
|
|
q_b[6] <= altsyncram_u2n1:auto_generated.q_b[6]
|
|
q_b[7] <= altsyncram_u2n1:auto_generated.q_b[7]
|
|
q_b[8] <= altsyncram_u2n1:auto_generated.q_b[8]
|
|
q_b[9] <= altsyncram_u2n1:auto_generated.q_b[9]
|
|
q_b[10] <= altsyncram_u2n1:auto_generated.q_b[10]
|
|
q_b[11] <= altsyncram_u2n1:auto_generated.q_b[11]
|
|
q_b[12] <= altsyncram_u2n1:auto_generated.q_b[12]
|
|
q_b[13] <= altsyncram_u2n1:auto_generated.q_b[13]
|
|
q_b[14] <= altsyncram_u2n1:auto_generated.q_b[14]
|
|
q_b[15] <= altsyncram_u2n1:auto_generated.q_b[15]
|
|
q_b[16] <= altsyncram_u2n1:auto_generated.q_b[16]
|
|
q_b[17] <= altsyncram_u2n1:auto_generated.q_b[17]
|
|
q_b[18] <= altsyncram_u2n1:auto_generated.q_b[18]
|
|
q_b[19] <= altsyncram_u2n1:auto_generated.q_b[19]
|
|
q_b[20] <= altsyncram_u2n1:auto_generated.q_b[20]
|
|
q_b[21] <= altsyncram_u2n1:auto_generated.q_b[21]
|
|
q_b[22] <= altsyncram_u2n1:auto_generated.q_b[22]
|
|
q_b[23] <= altsyncram_u2n1:auto_generated.q_b[23]
|
|
q_b[24] <= altsyncram_u2n1:auto_generated.q_b[24]
|
|
q_b[25] <= altsyncram_u2n1:auto_generated.q_b[25]
|
|
q_b[26] <= altsyncram_u2n1:auto_generated.q_b[26]
|
|
q_b[27] <= altsyncram_u2n1:auto_generated.q_b[27]
|
|
q_b[28] <= altsyncram_u2n1:auto_generated.q_b[28]
|
|
q_b[29] <= altsyncram_u2n1:auto_generated.q_b[29]
|
|
q_b[30] <= altsyncram_u2n1:auto_generated.q_b[30]
|
|
q_b[31] <= altsyncram_u2n1:auto_generated.q_b[31]
|
|
eccstatus[0] <= <GND>
|
|
eccstatus[1] <= <GND>
|
|
eccstatus[2] <= <GND>
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_regfile:neorv32_cpu_regfile_inst|altsyncram:reg_file[0][31]__1|altsyncram_u2n1:auto_generated
|
|
address_a[0] => ram_block1a0.PORTAADDR
|
|
address_a[0] => ram_block1a1.PORTAADDR
|
|
address_a[0] => ram_block1a2.PORTAADDR
|
|
address_a[0] => ram_block1a3.PORTAADDR
|
|
address_a[0] => ram_block1a4.PORTAADDR
|
|
address_a[0] => ram_block1a5.PORTAADDR
|
|
address_a[0] => ram_block1a6.PORTAADDR
|
|
address_a[0] => ram_block1a7.PORTAADDR
|
|
address_a[0] => ram_block1a8.PORTAADDR
|
|
address_a[0] => ram_block1a9.PORTAADDR
|
|
address_a[0] => ram_block1a10.PORTAADDR
|
|
address_a[0] => ram_block1a11.PORTAADDR
|
|
address_a[0] => ram_block1a12.PORTAADDR
|
|
address_a[0] => ram_block1a13.PORTAADDR
|
|
address_a[0] => ram_block1a14.PORTAADDR
|
|
address_a[0] => ram_block1a15.PORTAADDR
|
|
address_a[0] => ram_block1a16.PORTAADDR
|
|
address_a[0] => ram_block1a17.PORTAADDR
|
|
address_a[0] => ram_block1a18.PORTAADDR
|
|
address_a[0] => ram_block1a19.PORTAADDR
|
|
address_a[0] => ram_block1a20.PORTAADDR
|
|
address_a[0] => ram_block1a21.PORTAADDR
|
|
address_a[0] => ram_block1a22.PORTAADDR
|
|
address_a[0] => ram_block1a23.PORTAADDR
|
|
address_a[0] => ram_block1a24.PORTAADDR
|
|
address_a[0] => ram_block1a25.PORTAADDR
|
|
address_a[0] => ram_block1a26.PORTAADDR
|
|
address_a[0] => ram_block1a27.PORTAADDR
|
|
address_a[0] => ram_block1a28.PORTAADDR
|
|
address_a[0] => ram_block1a29.PORTAADDR
|
|
address_a[0] => ram_block1a30.PORTAADDR
|
|
address_a[0] => ram_block1a31.PORTAADDR
|
|
address_a[1] => ram_block1a0.PORTAADDR1
|
|
address_a[1] => ram_block1a1.PORTAADDR1
|
|
address_a[1] => ram_block1a2.PORTAADDR1
|
|
address_a[1] => ram_block1a3.PORTAADDR1
|
|
address_a[1] => ram_block1a4.PORTAADDR1
|
|
address_a[1] => ram_block1a5.PORTAADDR1
|
|
address_a[1] => ram_block1a6.PORTAADDR1
|
|
address_a[1] => ram_block1a7.PORTAADDR1
|
|
address_a[1] => ram_block1a8.PORTAADDR1
|
|
address_a[1] => ram_block1a9.PORTAADDR1
|
|
address_a[1] => ram_block1a10.PORTAADDR1
|
|
address_a[1] => ram_block1a11.PORTAADDR1
|
|
address_a[1] => ram_block1a12.PORTAADDR1
|
|
address_a[1] => ram_block1a13.PORTAADDR1
|
|
address_a[1] => ram_block1a14.PORTAADDR1
|
|
address_a[1] => ram_block1a15.PORTAADDR1
|
|
address_a[1] => ram_block1a16.PORTAADDR1
|
|
address_a[1] => ram_block1a17.PORTAADDR1
|
|
address_a[1] => ram_block1a18.PORTAADDR1
|
|
address_a[1] => ram_block1a19.PORTAADDR1
|
|
address_a[1] => ram_block1a20.PORTAADDR1
|
|
address_a[1] => ram_block1a21.PORTAADDR1
|
|
address_a[1] => ram_block1a22.PORTAADDR1
|
|
address_a[1] => ram_block1a23.PORTAADDR1
|
|
address_a[1] => ram_block1a24.PORTAADDR1
|
|
address_a[1] => ram_block1a25.PORTAADDR1
|
|
address_a[1] => ram_block1a26.PORTAADDR1
|
|
address_a[1] => ram_block1a27.PORTAADDR1
|
|
address_a[1] => ram_block1a28.PORTAADDR1
|
|
address_a[1] => ram_block1a29.PORTAADDR1
|
|
address_a[1] => ram_block1a30.PORTAADDR1
|
|
address_a[1] => ram_block1a31.PORTAADDR1
|
|
address_a[2] => ram_block1a0.PORTAADDR2
|
|
address_a[2] => ram_block1a1.PORTAADDR2
|
|
address_a[2] => ram_block1a2.PORTAADDR2
|
|
address_a[2] => ram_block1a3.PORTAADDR2
|
|
address_a[2] => ram_block1a4.PORTAADDR2
|
|
address_a[2] => ram_block1a5.PORTAADDR2
|
|
address_a[2] => ram_block1a6.PORTAADDR2
|
|
address_a[2] => ram_block1a7.PORTAADDR2
|
|
address_a[2] => ram_block1a8.PORTAADDR2
|
|
address_a[2] => ram_block1a9.PORTAADDR2
|
|
address_a[2] => ram_block1a10.PORTAADDR2
|
|
address_a[2] => ram_block1a11.PORTAADDR2
|
|
address_a[2] => ram_block1a12.PORTAADDR2
|
|
address_a[2] => ram_block1a13.PORTAADDR2
|
|
address_a[2] => ram_block1a14.PORTAADDR2
|
|
address_a[2] => ram_block1a15.PORTAADDR2
|
|
address_a[2] => ram_block1a16.PORTAADDR2
|
|
address_a[2] => ram_block1a17.PORTAADDR2
|
|
address_a[2] => ram_block1a18.PORTAADDR2
|
|
address_a[2] => ram_block1a19.PORTAADDR2
|
|
address_a[2] => ram_block1a20.PORTAADDR2
|
|
address_a[2] => ram_block1a21.PORTAADDR2
|
|
address_a[2] => ram_block1a22.PORTAADDR2
|
|
address_a[2] => ram_block1a23.PORTAADDR2
|
|
address_a[2] => ram_block1a24.PORTAADDR2
|
|
address_a[2] => ram_block1a25.PORTAADDR2
|
|
address_a[2] => ram_block1a26.PORTAADDR2
|
|
address_a[2] => ram_block1a27.PORTAADDR2
|
|
address_a[2] => ram_block1a28.PORTAADDR2
|
|
address_a[2] => ram_block1a29.PORTAADDR2
|
|
address_a[2] => ram_block1a30.PORTAADDR2
|
|
address_a[2] => ram_block1a31.PORTAADDR2
|
|
address_a[3] => ram_block1a0.PORTAADDR3
|
|
address_a[3] => ram_block1a1.PORTAADDR3
|
|
address_a[3] => ram_block1a2.PORTAADDR3
|
|
address_a[3] => ram_block1a3.PORTAADDR3
|
|
address_a[3] => ram_block1a4.PORTAADDR3
|
|
address_a[3] => ram_block1a5.PORTAADDR3
|
|
address_a[3] => ram_block1a6.PORTAADDR3
|
|
address_a[3] => ram_block1a7.PORTAADDR3
|
|
address_a[3] => ram_block1a8.PORTAADDR3
|
|
address_a[3] => ram_block1a9.PORTAADDR3
|
|
address_a[3] => ram_block1a10.PORTAADDR3
|
|
address_a[3] => ram_block1a11.PORTAADDR3
|
|
address_a[3] => ram_block1a12.PORTAADDR3
|
|
address_a[3] => ram_block1a13.PORTAADDR3
|
|
address_a[3] => ram_block1a14.PORTAADDR3
|
|
address_a[3] => ram_block1a15.PORTAADDR3
|
|
address_a[3] => ram_block1a16.PORTAADDR3
|
|
address_a[3] => ram_block1a17.PORTAADDR3
|
|
address_a[3] => ram_block1a18.PORTAADDR3
|
|
address_a[3] => ram_block1a19.PORTAADDR3
|
|
address_a[3] => ram_block1a20.PORTAADDR3
|
|
address_a[3] => ram_block1a21.PORTAADDR3
|
|
address_a[3] => ram_block1a22.PORTAADDR3
|
|
address_a[3] => ram_block1a23.PORTAADDR3
|
|
address_a[3] => ram_block1a24.PORTAADDR3
|
|
address_a[3] => ram_block1a25.PORTAADDR3
|
|
address_a[3] => ram_block1a26.PORTAADDR3
|
|
address_a[3] => ram_block1a27.PORTAADDR3
|
|
address_a[3] => ram_block1a28.PORTAADDR3
|
|
address_a[3] => ram_block1a29.PORTAADDR3
|
|
address_a[3] => ram_block1a30.PORTAADDR3
|
|
address_a[3] => ram_block1a31.PORTAADDR3
|
|
address_a[4] => ram_block1a0.PORTAADDR4
|
|
address_a[4] => ram_block1a1.PORTAADDR4
|
|
address_a[4] => ram_block1a2.PORTAADDR4
|
|
address_a[4] => ram_block1a3.PORTAADDR4
|
|
address_a[4] => ram_block1a4.PORTAADDR4
|
|
address_a[4] => ram_block1a5.PORTAADDR4
|
|
address_a[4] => ram_block1a6.PORTAADDR4
|
|
address_a[4] => ram_block1a7.PORTAADDR4
|
|
address_a[4] => ram_block1a8.PORTAADDR4
|
|
address_a[4] => ram_block1a9.PORTAADDR4
|
|
address_a[4] => ram_block1a10.PORTAADDR4
|
|
address_a[4] => ram_block1a11.PORTAADDR4
|
|
address_a[4] => ram_block1a12.PORTAADDR4
|
|
address_a[4] => ram_block1a13.PORTAADDR4
|
|
address_a[4] => ram_block1a14.PORTAADDR4
|
|
address_a[4] => ram_block1a15.PORTAADDR4
|
|
address_a[4] => ram_block1a16.PORTAADDR4
|
|
address_a[4] => ram_block1a17.PORTAADDR4
|
|
address_a[4] => ram_block1a18.PORTAADDR4
|
|
address_a[4] => ram_block1a19.PORTAADDR4
|
|
address_a[4] => ram_block1a20.PORTAADDR4
|
|
address_a[4] => ram_block1a21.PORTAADDR4
|
|
address_a[4] => ram_block1a22.PORTAADDR4
|
|
address_a[4] => ram_block1a23.PORTAADDR4
|
|
address_a[4] => ram_block1a24.PORTAADDR4
|
|
address_a[4] => ram_block1a25.PORTAADDR4
|
|
address_a[4] => ram_block1a26.PORTAADDR4
|
|
address_a[4] => ram_block1a27.PORTAADDR4
|
|
address_a[4] => ram_block1a28.PORTAADDR4
|
|
address_a[4] => ram_block1a29.PORTAADDR4
|
|
address_a[4] => ram_block1a30.PORTAADDR4
|
|
address_a[4] => ram_block1a31.PORTAADDR4
|
|
address_b[0] => ram_block1a0.PORTBADDR
|
|
address_b[0] => ram_block1a1.PORTBADDR
|
|
address_b[0] => ram_block1a2.PORTBADDR
|
|
address_b[0] => ram_block1a3.PORTBADDR
|
|
address_b[0] => ram_block1a4.PORTBADDR
|
|
address_b[0] => ram_block1a5.PORTBADDR
|
|
address_b[0] => ram_block1a6.PORTBADDR
|
|
address_b[0] => ram_block1a7.PORTBADDR
|
|
address_b[0] => ram_block1a8.PORTBADDR
|
|
address_b[0] => ram_block1a9.PORTBADDR
|
|
address_b[0] => ram_block1a10.PORTBADDR
|
|
address_b[0] => ram_block1a11.PORTBADDR
|
|
address_b[0] => ram_block1a12.PORTBADDR
|
|
address_b[0] => ram_block1a13.PORTBADDR
|
|
address_b[0] => ram_block1a14.PORTBADDR
|
|
address_b[0] => ram_block1a15.PORTBADDR
|
|
address_b[0] => ram_block1a16.PORTBADDR
|
|
address_b[0] => ram_block1a17.PORTBADDR
|
|
address_b[0] => ram_block1a18.PORTBADDR
|
|
address_b[0] => ram_block1a19.PORTBADDR
|
|
address_b[0] => ram_block1a20.PORTBADDR
|
|
address_b[0] => ram_block1a21.PORTBADDR
|
|
address_b[0] => ram_block1a22.PORTBADDR
|
|
address_b[0] => ram_block1a23.PORTBADDR
|
|
address_b[0] => ram_block1a24.PORTBADDR
|
|
address_b[0] => ram_block1a25.PORTBADDR
|
|
address_b[0] => ram_block1a26.PORTBADDR
|
|
address_b[0] => ram_block1a27.PORTBADDR
|
|
address_b[0] => ram_block1a28.PORTBADDR
|
|
address_b[0] => ram_block1a29.PORTBADDR
|
|
address_b[0] => ram_block1a30.PORTBADDR
|
|
address_b[0] => ram_block1a31.PORTBADDR
|
|
address_b[1] => ram_block1a0.PORTBADDR1
|
|
address_b[1] => ram_block1a1.PORTBADDR1
|
|
address_b[1] => ram_block1a2.PORTBADDR1
|
|
address_b[1] => ram_block1a3.PORTBADDR1
|
|
address_b[1] => ram_block1a4.PORTBADDR1
|
|
address_b[1] => ram_block1a5.PORTBADDR1
|
|
address_b[1] => ram_block1a6.PORTBADDR1
|
|
address_b[1] => ram_block1a7.PORTBADDR1
|
|
address_b[1] => ram_block1a8.PORTBADDR1
|
|
address_b[1] => ram_block1a9.PORTBADDR1
|
|
address_b[1] => ram_block1a10.PORTBADDR1
|
|
address_b[1] => ram_block1a11.PORTBADDR1
|
|
address_b[1] => ram_block1a12.PORTBADDR1
|
|
address_b[1] => ram_block1a13.PORTBADDR1
|
|
address_b[1] => ram_block1a14.PORTBADDR1
|
|
address_b[1] => ram_block1a15.PORTBADDR1
|
|
address_b[1] => ram_block1a16.PORTBADDR1
|
|
address_b[1] => ram_block1a17.PORTBADDR1
|
|
address_b[1] => ram_block1a18.PORTBADDR1
|
|
address_b[1] => ram_block1a19.PORTBADDR1
|
|
address_b[1] => ram_block1a20.PORTBADDR1
|
|
address_b[1] => ram_block1a21.PORTBADDR1
|
|
address_b[1] => ram_block1a22.PORTBADDR1
|
|
address_b[1] => ram_block1a23.PORTBADDR1
|
|
address_b[1] => ram_block1a24.PORTBADDR1
|
|
address_b[1] => ram_block1a25.PORTBADDR1
|
|
address_b[1] => ram_block1a26.PORTBADDR1
|
|
address_b[1] => ram_block1a27.PORTBADDR1
|
|
address_b[1] => ram_block1a28.PORTBADDR1
|
|
address_b[1] => ram_block1a29.PORTBADDR1
|
|
address_b[1] => ram_block1a30.PORTBADDR1
|
|
address_b[1] => ram_block1a31.PORTBADDR1
|
|
address_b[2] => ram_block1a0.PORTBADDR2
|
|
address_b[2] => ram_block1a1.PORTBADDR2
|
|
address_b[2] => ram_block1a2.PORTBADDR2
|
|
address_b[2] => ram_block1a3.PORTBADDR2
|
|
address_b[2] => ram_block1a4.PORTBADDR2
|
|
address_b[2] => ram_block1a5.PORTBADDR2
|
|
address_b[2] => ram_block1a6.PORTBADDR2
|
|
address_b[2] => ram_block1a7.PORTBADDR2
|
|
address_b[2] => ram_block1a8.PORTBADDR2
|
|
address_b[2] => ram_block1a9.PORTBADDR2
|
|
address_b[2] => ram_block1a10.PORTBADDR2
|
|
address_b[2] => ram_block1a11.PORTBADDR2
|
|
address_b[2] => ram_block1a12.PORTBADDR2
|
|
address_b[2] => ram_block1a13.PORTBADDR2
|
|
address_b[2] => ram_block1a14.PORTBADDR2
|
|
address_b[2] => ram_block1a15.PORTBADDR2
|
|
address_b[2] => ram_block1a16.PORTBADDR2
|
|
address_b[2] => ram_block1a17.PORTBADDR2
|
|
address_b[2] => ram_block1a18.PORTBADDR2
|
|
address_b[2] => ram_block1a19.PORTBADDR2
|
|
address_b[2] => ram_block1a20.PORTBADDR2
|
|
address_b[2] => ram_block1a21.PORTBADDR2
|
|
address_b[2] => ram_block1a22.PORTBADDR2
|
|
address_b[2] => ram_block1a23.PORTBADDR2
|
|
address_b[2] => ram_block1a24.PORTBADDR2
|
|
address_b[2] => ram_block1a25.PORTBADDR2
|
|
address_b[2] => ram_block1a26.PORTBADDR2
|
|
address_b[2] => ram_block1a27.PORTBADDR2
|
|
address_b[2] => ram_block1a28.PORTBADDR2
|
|
address_b[2] => ram_block1a29.PORTBADDR2
|
|
address_b[2] => ram_block1a30.PORTBADDR2
|
|
address_b[2] => ram_block1a31.PORTBADDR2
|
|
address_b[3] => ram_block1a0.PORTBADDR3
|
|
address_b[3] => ram_block1a1.PORTBADDR3
|
|
address_b[3] => ram_block1a2.PORTBADDR3
|
|
address_b[3] => ram_block1a3.PORTBADDR3
|
|
address_b[3] => ram_block1a4.PORTBADDR3
|
|
address_b[3] => ram_block1a5.PORTBADDR3
|
|
address_b[3] => ram_block1a6.PORTBADDR3
|
|
address_b[3] => ram_block1a7.PORTBADDR3
|
|
address_b[3] => ram_block1a8.PORTBADDR3
|
|
address_b[3] => ram_block1a9.PORTBADDR3
|
|
address_b[3] => ram_block1a10.PORTBADDR3
|
|
address_b[3] => ram_block1a11.PORTBADDR3
|
|
address_b[3] => ram_block1a12.PORTBADDR3
|
|
address_b[3] => ram_block1a13.PORTBADDR3
|
|
address_b[3] => ram_block1a14.PORTBADDR3
|
|
address_b[3] => ram_block1a15.PORTBADDR3
|
|
address_b[3] => ram_block1a16.PORTBADDR3
|
|
address_b[3] => ram_block1a17.PORTBADDR3
|
|
address_b[3] => ram_block1a18.PORTBADDR3
|
|
address_b[3] => ram_block1a19.PORTBADDR3
|
|
address_b[3] => ram_block1a20.PORTBADDR3
|
|
address_b[3] => ram_block1a21.PORTBADDR3
|
|
address_b[3] => ram_block1a22.PORTBADDR3
|
|
address_b[3] => ram_block1a23.PORTBADDR3
|
|
address_b[3] => ram_block1a24.PORTBADDR3
|
|
address_b[3] => ram_block1a25.PORTBADDR3
|
|
address_b[3] => ram_block1a26.PORTBADDR3
|
|
address_b[3] => ram_block1a27.PORTBADDR3
|
|
address_b[3] => ram_block1a28.PORTBADDR3
|
|
address_b[3] => ram_block1a29.PORTBADDR3
|
|
address_b[3] => ram_block1a30.PORTBADDR3
|
|
address_b[3] => ram_block1a31.PORTBADDR3
|
|
address_b[4] => ram_block1a0.PORTBADDR4
|
|
address_b[4] => ram_block1a1.PORTBADDR4
|
|
address_b[4] => ram_block1a2.PORTBADDR4
|
|
address_b[4] => ram_block1a3.PORTBADDR4
|
|
address_b[4] => ram_block1a4.PORTBADDR4
|
|
address_b[4] => ram_block1a5.PORTBADDR4
|
|
address_b[4] => ram_block1a6.PORTBADDR4
|
|
address_b[4] => ram_block1a7.PORTBADDR4
|
|
address_b[4] => ram_block1a8.PORTBADDR4
|
|
address_b[4] => ram_block1a9.PORTBADDR4
|
|
address_b[4] => ram_block1a10.PORTBADDR4
|
|
address_b[4] => ram_block1a11.PORTBADDR4
|
|
address_b[4] => ram_block1a12.PORTBADDR4
|
|
address_b[4] => ram_block1a13.PORTBADDR4
|
|
address_b[4] => ram_block1a14.PORTBADDR4
|
|
address_b[4] => ram_block1a15.PORTBADDR4
|
|
address_b[4] => ram_block1a16.PORTBADDR4
|
|
address_b[4] => ram_block1a17.PORTBADDR4
|
|
address_b[4] => ram_block1a18.PORTBADDR4
|
|
address_b[4] => ram_block1a19.PORTBADDR4
|
|
address_b[4] => ram_block1a20.PORTBADDR4
|
|
address_b[4] => ram_block1a21.PORTBADDR4
|
|
address_b[4] => ram_block1a22.PORTBADDR4
|
|
address_b[4] => ram_block1a23.PORTBADDR4
|
|
address_b[4] => ram_block1a24.PORTBADDR4
|
|
address_b[4] => ram_block1a25.PORTBADDR4
|
|
address_b[4] => ram_block1a26.PORTBADDR4
|
|
address_b[4] => ram_block1a27.PORTBADDR4
|
|
address_b[4] => ram_block1a28.PORTBADDR4
|
|
address_b[4] => ram_block1a29.PORTBADDR4
|
|
address_b[4] => ram_block1a30.PORTBADDR4
|
|
address_b[4] => ram_block1a31.PORTBADDR4
|
|
clock0 => ram_block1a0.CLK0
|
|
clock0 => ram_block1a1.CLK0
|
|
clock0 => ram_block1a2.CLK0
|
|
clock0 => ram_block1a3.CLK0
|
|
clock0 => ram_block1a4.CLK0
|
|
clock0 => ram_block1a5.CLK0
|
|
clock0 => ram_block1a6.CLK0
|
|
clock0 => ram_block1a7.CLK0
|
|
clock0 => ram_block1a8.CLK0
|
|
clock0 => ram_block1a9.CLK0
|
|
clock0 => ram_block1a10.CLK0
|
|
clock0 => ram_block1a11.CLK0
|
|
clock0 => ram_block1a12.CLK0
|
|
clock0 => ram_block1a13.CLK0
|
|
clock0 => ram_block1a14.CLK0
|
|
clock0 => ram_block1a15.CLK0
|
|
clock0 => ram_block1a16.CLK0
|
|
clock0 => ram_block1a17.CLK0
|
|
clock0 => ram_block1a18.CLK0
|
|
clock0 => ram_block1a19.CLK0
|
|
clock0 => ram_block1a20.CLK0
|
|
clock0 => ram_block1a21.CLK0
|
|
clock0 => ram_block1a22.CLK0
|
|
clock0 => ram_block1a23.CLK0
|
|
clock0 => ram_block1a24.CLK0
|
|
clock0 => ram_block1a25.CLK0
|
|
clock0 => ram_block1a26.CLK0
|
|
clock0 => ram_block1a27.CLK0
|
|
clock0 => ram_block1a28.CLK0
|
|
clock0 => ram_block1a29.CLK0
|
|
clock0 => ram_block1a30.CLK0
|
|
clock0 => ram_block1a31.CLK0
|
|
data_a[0] => ram_block1a0.PORTADATAIN
|
|
data_a[1] => ram_block1a1.PORTADATAIN
|
|
data_a[2] => ram_block1a2.PORTADATAIN
|
|
data_a[3] => ram_block1a3.PORTADATAIN
|
|
data_a[4] => ram_block1a4.PORTADATAIN
|
|
data_a[5] => ram_block1a5.PORTADATAIN
|
|
data_a[6] => ram_block1a6.PORTADATAIN
|
|
data_a[7] => ram_block1a7.PORTADATAIN
|
|
data_a[8] => ram_block1a8.PORTADATAIN
|
|
data_a[9] => ram_block1a9.PORTADATAIN
|
|
data_a[10] => ram_block1a10.PORTADATAIN
|
|
data_a[11] => ram_block1a11.PORTADATAIN
|
|
data_a[12] => ram_block1a12.PORTADATAIN
|
|
data_a[13] => ram_block1a13.PORTADATAIN
|
|
data_a[14] => ram_block1a14.PORTADATAIN
|
|
data_a[15] => ram_block1a15.PORTADATAIN
|
|
data_a[16] => ram_block1a16.PORTADATAIN
|
|
data_a[17] => ram_block1a17.PORTADATAIN
|
|
data_a[18] => ram_block1a18.PORTADATAIN
|
|
data_a[19] => ram_block1a19.PORTADATAIN
|
|
data_a[20] => ram_block1a20.PORTADATAIN
|
|
data_a[21] => ram_block1a21.PORTADATAIN
|
|
data_a[22] => ram_block1a22.PORTADATAIN
|
|
data_a[23] => ram_block1a23.PORTADATAIN
|
|
data_a[24] => ram_block1a24.PORTADATAIN
|
|
data_a[25] => ram_block1a25.PORTADATAIN
|
|
data_a[26] => ram_block1a26.PORTADATAIN
|
|
data_a[27] => ram_block1a27.PORTADATAIN
|
|
data_a[28] => ram_block1a28.PORTADATAIN
|
|
data_a[29] => ram_block1a29.PORTADATAIN
|
|
data_a[30] => ram_block1a30.PORTADATAIN
|
|
data_a[31] => ram_block1a31.PORTADATAIN
|
|
q_b[0] <= ram_block1a0.PORTBDATAOUT
|
|
q_b[1] <= ram_block1a1.PORTBDATAOUT
|
|
q_b[2] <= ram_block1a2.PORTBDATAOUT
|
|
q_b[3] <= ram_block1a3.PORTBDATAOUT
|
|
q_b[4] <= ram_block1a4.PORTBDATAOUT
|
|
q_b[5] <= ram_block1a5.PORTBDATAOUT
|
|
q_b[6] <= ram_block1a6.PORTBDATAOUT
|
|
q_b[7] <= ram_block1a7.PORTBDATAOUT
|
|
q_b[8] <= ram_block1a8.PORTBDATAOUT
|
|
q_b[9] <= ram_block1a9.PORTBDATAOUT
|
|
q_b[10] <= ram_block1a10.PORTBDATAOUT
|
|
q_b[11] <= ram_block1a11.PORTBDATAOUT
|
|
q_b[12] <= ram_block1a12.PORTBDATAOUT
|
|
q_b[13] <= ram_block1a13.PORTBDATAOUT
|
|
q_b[14] <= ram_block1a14.PORTBDATAOUT
|
|
q_b[15] <= ram_block1a15.PORTBDATAOUT
|
|
q_b[16] <= ram_block1a16.PORTBDATAOUT
|
|
q_b[17] <= ram_block1a17.PORTBDATAOUT
|
|
q_b[18] <= ram_block1a18.PORTBDATAOUT
|
|
q_b[19] <= ram_block1a19.PORTBDATAOUT
|
|
q_b[20] <= ram_block1a20.PORTBDATAOUT
|
|
q_b[21] <= ram_block1a21.PORTBDATAOUT
|
|
q_b[22] <= ram_block1a22.PORTBDATAOUT
|
|
q_b[23] <= ram_block1a23.PORTBDATAOUT
|
|
q_b[24] <= ram_block1a24.PORTBDATAOUT
|
|
q_b[25] <= ram_block1a25.PORTBDATAOUT
|
|
q_b[26] <= ram_block1a26.PORTBDATAOUT
|
|
q_b[27] <= ram_block1a27.PORTBDATAOUT
|
|
q_b[28] <= ram_block1a28.PORTBDATAOUT
|
|
q_b[29] <= ram_block1a29.PORTBDATAOUT
|
|
q_b[30] <= ram_block1a30.PORTBDATAOUT
|
|
q_b[31] <= ram_block1a31.PORTBDATAOUT
|
|
wren_a => ram_block1a0.PORTAWE
|
|
wren_a => ram_block1a1.PORTAWE
|
|
wren_a => ram_block1a2.PORTAWE
|
|
wren_a => ram_block1a3.PORTAWE
|
|
wren_a => ram_block1a4.PORTAWE
|
|
wren_a => ram_block1a5.PORTAWE
|
|
wren_a => ram_block1a6.PORTAWE
|
|
wren_a => ram_block1a7.PORTAWE
|
|
wren_a => ram_block1a8.PORTAWE
|
|
wren_a => ram_block1a9.PORTAWE
|
|
wren_a => ram_block1a10.PORTAWE
|
|
wren_a => ram_block1a11.PORTAWE
|
|
wren_a => ram_block1a12.PORTAWE
|
|
wren_a => ram_block1a13.PORTAWE
|
|
wren_a => ram_block1a14.PORTAWE
|
|
wren_a => ram_block1a15.PORTAWE
|
|
wren_a => ram_block1a16.PORTAWE
|
|
wren_a => ram_block1a17.PORTAWE
|
|
wren_a => ram_block1a18.PORTAWE
|
|
wren_a => ram_block1a19.PORTAWE
|
|
wren_a => ram_block1a20.PORTAWE
|
|
wren_a => ram_block1a21.PORTAWE
|
|
wren_a => ram_block1a22.PORTAWE
|
|
wren_a => ram_block1a23.PORTAWE
|
|
wren_a => ram_block1a24.PORTAWE
|
|
wren_a => ram_block1a25.PORTAWE
|
|
wren_a => ram_block1a26.PORTAWE
|
|
wren_a => ram_block1a27.PORTAWE
|
|
wren_a => ram_block1a28.PORTAWE
|
|
wren_a => ram_block1a29.PORTAWE
|
|
wren_a => ram_block1a30.PORTAWE
|
|
wren_a => ram_block1a31.PORTAWE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_regfile:neorv32_cpu_regfile_inst|altsyncram:reg_file[0][31]__2
|
|
wren_a => altsyncram_u2n1:auto_generated.wren_a
|
|
rden_a => ~NO_FANOUT~
|
|
wren_b => ~NO_FANOUT~
|
|
rden_b => ~NO_FANOUT~
|
|
data_a[0] => altsyncram_u2n1:auto_generated.data_a[0]
|
|
data_a[1] => altsyncram_u2n1:auto_generated.data_a[1]
|
|
data_a[2] => altsyncram_u2n1:auto_generated.data_a[2]
|
|
data_a[3] => altsyncram_u2n1:auto_generated.data_a[3]
|
|
data_a[4] => altsyncram_u2n1:auto_generated.data_a[4]
|
|
data_a[5] => altsyncram_u2n1:auto_generated.data_a[5]
|
|
data_a[6] => altsyncram_u2n1:auto_generated.data_a[6]
|
|
data_a[7] => altsyncram_u2n1:auto_generated.data_a[7]
|
|
data_a[8] => altsyncram_u2n1:auto_generated.data_a[8]
|
|
data_a[9] => altsyncram_u2n1:auto_generated.data_a[9]
|
|
data_a[10] => altsyncram_u2n1:auto_generated.data_a[10]
|
|
data_a[11] => altsyncram_u2n1:auto_generated.data_a[11]
|
|
data_a[12] => altsyncram_u2n1:auto_generated.data_a[12]
|
|
data_a[13] => altsyncram_u2n1:auto_generated.data_a[13]
|
|
data_a[14] => altsyncram_u2n1:auto_generated.data_a[14]
|
|
data_a[15] => altsyncram_u2n1:auto_generated.data_a[15]
|
|
data_a[16] => altsyncram_u2n1:auto_generated.data_a[16]
|
|
data_a[17] => altsyncram_u2n1:auto_generated.data_a[17]
|
|
data_a[18] => altsyncram_u2n1:auto_generated.data_a[18]
|
|
data_a[19] => altsyncram_u2n1:auto_generated.data_a[19]
|
|
data_a[20] => altsyncram_u2n1:auto_generated.data_a[20]
|
|
data_a[21] => altsyncram_u2n1:auto_generated.data_a[21]
|
|
data_a[22] => altsyncram_u2n1:auto_generated.data_a[22]
|
|
data_a[23] => altsyncram_u2n1:auto_generated.data_a[23]
|
|
data_a[24] => altsyncram_u2n1:auto_generated.data_a[24]
|
|
data_a[25] => altsyncram_u2n1:auto_generated.data_a[25]
|
|
data_a[26] => altsyncram_u2n1:auto_generated.data_a[26]
|
|
data_a[27] => altsyncram_u2n1:auto_generated.data_a[27]
|
|
data_a[28] => altsyncram_u2n1:auto_generated.data_a[28]
|
|
data_a[29] => altsyncram_u2n1:auto_generated.data_a[29]
|
|
data_a[30] => altsyncram_u2n1:auto_generated.data_a[30]
|
|
data_a[31] => altsyncram_u2n1:auto_generated.data_a[31]
|
|
data_b[0] => ~NO_FANOUT~
|
|
data_b[1] => ~NO_FANOUT~
|
|
data_b[2] => ~NO_FANOUT~
|
|
data_b[3] => ~NO_FANOUT~
|
|
data_b[4] => ~NO_FANOUT~
|
|
data_b[5] => ~NO_FANOUT~
|
|
data_b[6] => ~NO_FANOUT~
|
|
data_b[7] => ~NO_FANOUT~
|
|
data_b[8] => ~NO_FANOUT~
|
|
data_b[9] => ~NO_FANOUT~
|
|
data_b[10] => ~NO_FANOUT~
|
|
data_b[11] => ~NO_FANOUT~
|
|
data_b[12] => ~NO_FANOUT~
|
|
data_b[13] => ~NO_FANOUT~
|
|
data_b[14] => ~NO_FANOUT~
|
|
data_b[15] => ~NO_FANOUT~
|
|
data_b[16] => ~NO_FANOUT~
|
|
data_b[17] => ~NO_FANOUT~
|
|
data_b[18] => ~NO_FANOUT~
|
|
data_b[19] => ~NO_FANOUT~
|
|
data_b[20] => ~NO_FANOUT~
|
|
data_b[21] => ~NO_FANOUT~
|
|
data_b[22] => ~NO_FANOUT~
|
|
data_b[23] => ~NO_FANOUT~
|
|
data_b[24] => ~NO_FANOUT~
|
|
data_b[25] => ~NO_FANOUT~
|
|
data_b[26] => ~NO_FANOUT~
|
|
data_b[27] => ~NO_FANOUT~
|
|
data_b[28] => ~NO_FANOUT~
|
|
data_b[29] => ~NO_FANOUT~
|
|
data_b[30] => ~NO_FANOUT~
|
|
data_b[31] => ~NO_FANOUT~
|
|
address_a[0] => altsyncram_u2n1:auto_generated.address_a[0]
|
|
address_a[1] => altsyncram_u2n1:auto_generated.address_a[1]
|
|
address_a[2] => altsyncram_u2n1:auto_generated.address_a[2]
|
|
address_a[3] => altsyncram_u2n1:auto_generated.address_a[3]
|
|
address_a[4] => altsyncram_u2n1:auto_generated.address_a[4]
|
|
address_b[0] => altsyncram_u2n1:auto_generated.address_b[0]
|
|
address_b[1] => altsyncram_u2n1:auto_generated.address_b[1]
|
|
address_b[2] => altsyncram_u2n1:auto_generated.address_b[2]
|
|
address_b[3] => altsyncram_u2n1:auto_generated.address_b[3]
|
|
address_b[4] => altsyncram_u2n1:auto_generated.address_b[4]
|
|
addressstall_a => ~NO_FANOUT~
|
|
addressstall_b => ~NO_FANOUT~
|
|
clock0 => altsyncram_u2n1:auto_generated.clock0
|
|
clock1 => ~NO_FANOUT~
|
|
clocken0 => ~NO_FANOUT~
|
|
clocken1 => ~NO_FANOUT~
|
|
clocken2 => ~NO_FANOUT~
|
|
clocken3 => ~NO_FANOUT~
|
|
aclr0 => ~NO_FANOUT~
|
|
aclr1 => ~NO_FANOUT~
|
|
byteena_a[0] => ~NO_FANOUT~
|
|
byteena_b[0] => ~NO_FANOUT~
|
|
q_a[0] <= <GND>
|
|
q_a[1] <= <GND>
|
|
q_a[2] <= <GND>
|
|
q_a[3] <= <GND>
|
|
q_a[4] <= <GND>
|
|
q_a[5] <= <GND>
|
|
q_a[6] <= <GND>
|
|
q_a[7] <= <GND>
|
|
q_a[8] <= <GND>
|
|
q_a[9] <= <GND>
|
|
q_a[10] <= <GND>
|
|
q_a[11] <= <GND>
|
|
q_a[12] <= <GND>
|
|
q_a[13] <= <GND>
|
|
q_a[14] <= <GND>
|
|
q_a[15] <= <GND>
|
|
q_a[16] <= <GND>
|
|
q_a[17] <= <GND>
|
|
q_a[18] <= <GND>
|
|
q_a[19] <= <GND>
|
|
q_a[20] <= <GND>
|
|
q_a[21] <= <GND>
|
|
q_a[22] <= <GND>
|
|
q_a[23] <= <GND>
|
|
q_a[24] <= <GND>
|
|
q_a[25] <= <GND>
|
|
q_a[26] <= <GND>
|
|
q_a[27] <= <GND>
|
|
q_a[28] <= <GND>
|
|
q_a[29] <= <GND>
|
|
q_a[30] <= <GND>
|
|
q_a[31] <= <GND>
|
|
q_b[0] <= altsyncram_u2n1:auto_generated.q_b[0]
|
|
q_b[1] <= altsyncram_u2n1:auto_generated.q_b[1]
|
|
q_b[2] <= altsyncram_u2n1:auto_generated.q_b[2]
|
|
q_b[3] <= altsyncram_u2n1:auto_generated.q_b[3]
|
|
q_b[4] <= altsyncram_u2n1:auto_generated.q_b[4]
|
|
q_b[5] <= altsyncram_u2n1:auto_generated.q_b[5]
|
|
q_b[6] <= altsyncram_u2n1:auto_generated.q_b[6]
|
|
q_b[7] <= altsyncram_u2n1:auto_generated.q_b[7]
|
|
q_b[8] <= altsyncram_u2n1:auto_generated.q_b[8]
|
|
q_b[9] <= altsyncram_u2n1:auto_generated.q_b[9]
|
|
q_b[10] <= altsyncram_u2n1:auto_generated.q_b[10]
|
|
q_b[11] <= altsyncram_u2n1:auto_generated.q_b[11]
|
|
q_b[12] <= altsyncram_u2n1:auto_generated.q_b[12]
|
|
q_b[13] <= altsyncram_u2n1:auto_generated.q_b[13]
|
|
q_b[14] <= altsyncram_u2n1:auto_generated.q_b[14]
|
|
q_b[15] <= altsyncram_u2n1:auto_generated.q_b[15]
|
|
q_b[16] <= altsyncram_u2n1:auto_generated.q_b[16]
|
|
q_b[17] <= altsyncram_u2n1:auto_generated.q_b[17]
|
|
q_b[18] <= altsyncram_u2n1:auto_generated.q_b[18]
|
|
q_b[19] <= altsyncram_u2n1:auto_generated.q_b[19]
|
|
q_b[20] <= altsyncram_u2n1:auto_generated.q_b[20]
|
|
q_b[21] <= altsyncram_u2n1:auto_generated.q_b[21]
|
|
q_b[22] <= altsyncram_u2n1:auto_generated.q_b[22]
|
|
q_b[23] <= altsyncram_u2n1:auto_generated.q_b[23]
|
|
q_b[24] <= altsyncram_u2n1:auto_generated.q_b[24]
|
|
q_b[25] <= altsyncram_u2n1:auto_generated.q_b[25]
|
|
q_b[26] <= altsyncram_u2n1:auto_generated.q_b[26]
|
|
q_b[27] <= altsyncram_u2n1:auto_generated.q_b[27]
|
|
q_b[28] <= altsyncram_u2n1:auto_generated.q_b[28]
|
|
q_b[29] <= altsyncram_u2n1:auto_generated.q_b[29]
|
|
q_b[30] <= altsyncram_u2n1:auto_generated.q_b[30]
|
|
q_b[31] <= altsyncram_u2n1:auto_generated.q_b[31]
|
|
eccstatus[0] <= <GND>
|
|
eccstatus[1] <= <GND>
|
|
eccstatus[2] <= <GND>
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_regfile:neorv32_cpu_regfile_inst|altsyncram:reg_file[0][31]__2|altsyncram_u2n1:auto_generated
|
|
address_a[0] => ram_block1a0.PORTAADDR
|
|
address_a[0] => ram_block1a1.PORTAADDR
|
|
address_a[0] => ram_block1a2.PORTAADDR
|
|
address_a[0] => ram_block1a3.PORTAADDR
|
|
address_a[0] => ram_block1a4.PORTAADDR
|
|
address_a[0] => ram_block1a5.PORTAADDR
|
|
address_a[0] => ram_block1a6.PORTAADDR
|
|
address_a[0] => ram_block1a7.PORTAADDR
|
|
address_a[0] => ram_block1a8.PORTAADDR
|
|
address_a[0] => ram_block1a9.PORTAADDR
|
|
address_a[0] => ram_block1a10.PORTAADDR
|
|
address_a[0] => ram_block1a11.PORTAADDR
|
|
address_a[0] => ram_block1a12.PORTAADDR
|
|
address_a[0] => ram_block1a13.PORTAADDR
|
|
address_a[0] => ram_block1a14.PORTAADDR
|
|
address_a[0] => ram_block1a15.PORTAADDR
|
|
address_a[0] => ram_block1a16.PORTAADDR
|
|
address_a[0] => ram_block1a17.PORTAADDR
|
|
address_a[0] => ram_block1a18.PORTAADDR
|
|
address_a[0] => ram_block1a19.PORTAADDR
|
|
address_a[0] => ram_block1a20.PORTAADDR
|
|
address_a[0] => ram_block1a21.PORTAADDR
|
|
address_a[0] => ram_block1a22.PORTAADDR
|
|
address_a[0] => ram_block1a23.PORTAADDR
|
|
address_a[0] => ram_block1a24.PORTAADDR
|
|
address_a[0] => ram_block1a25.PORTAADDR
|
|
address_a[0] => ram_block1a26.PORTAADDR
|
|
address_a[0] => ram_block1a27.PORTAADDR
|
|
address_a[0] => ram_block1a28.PORTAADDR
|
|
address_a[0] => ram_block1a29.PORTAADDR
|
|
address_a[0] => ram_block1a30.PORTAADDR
|
|
address_a[0] => ram_block1a31.PORTAADDR
|
|
address_a[1] => ram_block1a0.PORTAADDR1
|
|
address_a[1] => ram_block1a1.PORTAADDR1
|
|
address_a[1] => ram_block1a2.PORTAADDR1
|
|
address_a[1] => ram_block1a3.PORTAADDR1
|
|
address_a[1] => ram_block1a4.PORTAADDR1
|
|
address_a[1] => ram_block1a5.PORTAADDR1
|
|
address_a[1] => ram_block1a6.PORTAADDR1
|
|
address_a[1] => ram_block1a7.PORTAADDR1
|
|
address_a[1] => ram_block1a8.PORTAADDR1
|
|
address_a[1] => ram_block1a9.PORTAADDR1
|
|
address_a[1] => ram_block1a10.PORTAADDR1
|
|
address_a[1] => ram_block1a11.PORTAADDR1
|
|
address_a[1] => ram_block1a12.PORTAADDR1
|
|
address_a[1] => ram_block1a13.PORTAADDR1
|
|
address_a[1] => ram_block1a14.PORTAADDR1
|
|
address_a[1] => ram_block1a15.PORTAADDR1
|
|
address_a[1] => ram_block1a16.PORTAADDR1
|
|
address_a[1] => ram_block1a17.PORTAADDR1
|
|
address_a[1] => ram_block1a18.PORTAADDR1
|
|
address_a[1] => ram_block1a19.PORTAADDR1
|
|
address_a[1] => ram_block1a20.PORTAADDR1
|
|
address_a[1] => ram_block1a21.PORTAADDR1
|
|
address_a[1] => ram_block1a22.PORTAADDR1
|
|
address_a[1] => ram_block1a23.PORTAADDR1
|
|
address_a[1] => ram_block1a24.PORTAADDR1
|
|
address_a[1] => ram_block1a25.PORTAADDR1
|
|
address_a[1] => ram_block1a26.PORTAADDR1
|
|
address_a[1] => ram_block1a27.PORTAADDR1
|
|
address_a[1] => ram_block1a28.PORTAADDR1
|
|
address_a[1] => ram_block1a29.PORTAADDR1
|
|
address_a[1] => ram_block1a30.PORTAADDR1
|
|
address_a[1] => ram_block1a31.PORTAADDR1
|
|
address_a[2] => ram_block1a0.PORTAADDR2
|
|
address_a[2] => ram_block1a1.PORTAADDR2
|
|
address_a[2] => ram_block1a2.PORTAADDR2
|
|
address_a[2] => ram_block1a3.PORTAADDR2
|
|
address_a[2] => ram_block1a4.PORTAADDR2
|
|
address_a[2] => ram_block1a5.PORTAADDR2
|
|
address_a[2] => ram_block1a6.PORTAADDR2
|
|
address_a[2] => ram_block1a7.PORTAADDR2
|
|
address_a[2] => ram_block1a8.PORTAADDR2
|
|
address_a[2] => ram_block1a9.PORTAADDR2
|
|
address_a[2] => ram_block1a10.PORTAADDR2
|
|
address_a[2] => ram_block1a11.PORTAADDR2
|
|
address_a[2] => ram_block1a12.PORTAADDR2
|
|
address_a[2] => ram_block1a13.PORTAADDR2
|
|
address_a[2] => ram_block1a14.PORTAADDR2
|
|
address_a[2] => ram_block1a15.PORTAADDR2
|
|
address_a[2] => ram_block1a16.PORTAADDR2
|
|
address_a[2] => ram_block1a17.PORTAADDR2
|
|
address_a[2] => ram_block1a18.PORTAADDR2
|
|
address_a[2] => ram_block1a19.PORTAADDR2
|
|
address_a[2] => ram_block1a20.PORTAADDR2
|
|
address_a[2] => ram_block1a21.PORTAADDR2
|
|
address_a[2] => ram_block1a22.PORTAADDR2
|
|
address_a[2] => ram_block1a23.PORTAADDR2
|
|
address_a[2] => ram_block1a24.PORTAADDR2
|
|
address_a[2] => ram_block1a25.PORTAADDR2
|
|
address_a[2] => ram_block1a26.PORTAADDR2
|
|
address_a[2] => ram_block1a27.PORTAADDR2
|
|
address_a[2] => ram_block1a28.PORTAADDR2
|
|
address_a[2] => ram_block1a29.PORTAADDR2
|
|
address_a[2] => ram_block1a30.PORTAADDR2
|
|
address_a[2] => ram_block1a31.PORTAADDR2
|
|
address_a[3] => ram_block1a0.PORTAADDR3
|
|
address_a[3] => ram_block1a1.PORTAADDR3
|
|
address_a[3] => ram_block1a2.PORTAADDR3
|
|
address_a[3] => ram_block1a3.PORTAADDR3
|
|
address_a[3] => ram_block1a4.PORTAADDR3
|
|
address_a[3] => ram_block1a5.PORTAADDR3
|
|
address_a[3] => ram_block1a6.PORTAADDR3
|
|
address_a[3] => ram_block1a7.PORTAADDR3
|
|
address_a[3] => ram_block1a8.PORTAADDR3
|
|
address_a[3] => ram_block1a9.PORTAADDR3
|
|
address_a[3] => ram_block1a10.PORTAADDR3
|
|
address_a[3] => ram_block1a11.PORTAADDR3
|
|
address_a[3] => ram_block1a12.PORTAADDR3
|
|
address_a[3] => ram_block1a13.PORTAADDR3
|
|
address_a[3] => ram_block1a14.PORTAADDR3
|
|
address_a[3] => ram_block1a15.PORTAADDR3
|
|
address_a[3] => ram_block1a16.PORTAADDR3
|
|
address_a[3] => ram_block1a17.PORTAADDR3
|
|
address_a[3] => ram_block1a18.PORTAADDR3
|
|
address_a[3] => ram_block1a19.PORTAADDR3
|
|
address_a[3] => ram_block1a20.PORTAADDR3
|
|
address_a[3] => ram_block1a21.PORTAADDR3
|
|
address_a[3] => ram_block1a22.PORTAADDR3
|
|
address_a[3] => ram_block1a23.PORTAADDR3
|
|
address_a[3] => ram_block1a24.PORTAADDR3
|
|
address_a[3] => ram_block1a25.PORTAADDR3
|
|
address_a[3] => ram_block1a26.PORTAADDR3
|
|
address_a[3] => ram_block1a27.PORTAADDR3
|
|
address_a[3] => ram_block1a28.PORTAADDR3
|
|
address_a[3] => ram_block1a29.PORTAADDR3
|
|
address_a[3] => ram_block1a30.PORTAADDR3
|
|
address_a[3] => ram_block1a31.PORTAADDR3
|
|
address_a[4] => ram_block1a0.PORTAADDR4
|
|
address_a[4] => ram_block1a1.PORTAADDR4
|
|
address_a[4] => ram_block1a2.PORTAADDR4
|
|
address_a[4] => ram_block1a3.PORTAADDR4
|
|
address_a[4] => ram_block1a4.PORTAADDR4
|
|
address_a[4] => ram_block1a5.PORTAADDR4
|
|
address_a[4] => ram_block1a6.PORTAADDR4
|
|
address_a[4] => ram_block1a7.PORTAADDR4
|
|
address_a[4] => ram_block1a8.PORTAADDR4
|
|
address_a[4] => ram_block1a9.PORTAADDR4
|
|
address_a[4] => ram_block1a10.PORTAADDR4
|
|
address_a[4] => ram_block1a11.PORTAADDR4
|
|
address_a[4] => ram_block1a12.PORTAADDR4
|
|
address_a[4] => ram_block1a13.PORTAADDR4
|
|
address_a[4] => ram_block1a14.PORTAADDR4
|
|
address_a[4] => ram_block1a15.PORTAADDR4
|
|
address_a[4] => ram_block1a16.PORTAADDR4
|
|
address_a[4] => ram_block1a17.PORTAADDR4
|
|
address_a[4] => ram_block1a18.PORTAADDR4
|
|
address_a[4] => ram_block1a19.PORTAADDR4
|
|
address_a[4] => ram_block1a20.PORTAADDR4
|
|
address_a[4] => ram_block1a21.PORTAADDR4
|
|
address_a[4] => ram_block1a22.PORTAADDR4
|
|
address_a[4] => ram_block1a23.PORTAADDR4
|
|
address_a[4] => ram_block1a24.PORTAADDR4
|
|
address_a[4] => ram_block1a25.PORTAADDR4
|
|
address_a[4] => ram_block1a26.PORTAADDR4
|
|
address_a[4] => ram_block1a27.PORTAADDR4
|
|
address_a[4] => ram_block1a28.PORTAADDR4
|
|
address_a[4] => ram_block1a29.PORTAADDR4
|
|
address_a[4] => ram_block1a30.PORTAADDR4
|
|
address_a[4] => ram_block1a31.PORTAADDR4
|
|
address_b[0] => ram_block1a0.PORTBADDR
|
|
address_b[0] => ram_block1a1.PORTBADDR
|
|
address_b[0] => ram_block1a2.PORTBADDR
|
|
address_b[0] => ram_block1a3.PORTBADDR
|
|
address_b[0] => ram_block1a4.PORTBADDR
|
|
address_b[0] => ram_block1a5.PORTBADDR
|
|
address_b[0] => ram_block1a6.PORTBADDR
|
|
address_b[0] => ram_block1a7.PORTBADDR
|
|
address_b[0] => ram_block1a8.PORTBADDR
|
|
address_b[0] => ram_block1a9.PORTBADDR
|
|
address_b[0] => ram_block1a10.PORTBADDR
|
|
address_b[0] => ram_block1a11.PORTBADDR
|
|
address_b[0] => ram_block1a12.PORTBADDR
|
|
address_b[0] => ram_block1a13.PORTBADDR
|
|
address_b[0] => ram_block1a14.PORTBADDR
|
|
address_b[0] => ram_block1a15.PORTBADDR
|
|
address_b[0] => ram_block1a16.PORTBADDR
|
|
address_b[0] => ram_block1a17.PORTBADDR
|
|
address_b[0] => ram_block1a18.PORTBADDR
|
|
address_b[0] => ram_block1a19.PORTBADDR
|
|
address_b[0] => ram_block1a20.PORTBADDR
|
|
address_b[0] => ram_block1a21.PORTBADDR
|
|
address_b[0] => ram_block1a22.PORTBADDR
|
|
address_b[0] => ram_block1a23.PORTBADDR
|
|
address_b[0] => ram_block1a24.PORTBADDR
|
|
address_b[0] => ram_block1a25.PORTBADDR
|
|
address_b[0] => ram_block1a26.PORTBADDR
|
|
address_b[0] => ram_block1a27.PORTBADDR
|
|
address_b[0] => ram_block1a28.PORTBADDR
|
|
address_b[0] => ram_block1a29.PORTBADDR
|
|
address_b[0] => ram_block1a30.PORTBADDR
|
|
address_b[0] => ram_block1a31.PORTBADDR
|
|
address_b[1] => ram_block1a0.PORTBADDR1
|
|
address_b[1] => ram_block1a1.PORTBADDR1
|
|
address_b[1] => ram_block1a2.PORTBADDR1
|
|
address_b[1] => ram_block1a3.PORTBADDR1
|
|
address_b[1] => ram_block1a4.PORTBADDR1
|
|
address_b[1] => ram_block1a5.PORTBADDR1
|
|
address_b[1] => ram_block1a6.PORTBADDR1
|
|
address_b[1] => ram_block1a7.PORTBADDR1
|
|
address_b[1] => ram_block1a8.PORTBADDR1
|
|
address_b[1] => ram_block1a9.PORTBADDR1
|
|
address_b[1] => ram_block1a10.PORTBADDR1
|
|
address_b[1] => ram_block1a11.PORTBADDR1
|
|
address_b[1] => ram_block1a12.PORTBADDR1
|
|
address_b[1] => ram_block1a13.PORTBADDR1
|
|
address_b[1] => ram_block1a14.PORTBADDR1
|
|
address_b[1] => ram_block1a15.PORTBADDR1
|
|
address_b[1] => ram_block1a16.PORTBADDR1
|
|
address_b[1] => ram_block1a17.PORTBADDR1
|
|
address_b[1] => ram_block1a18.PORTBADDR1
|
|
address_b[1] => ram_block1a19.PORTBADDR1
|
|
address_b[1] => ram_block1a20.PORTBADDR1
|
|
address_b[1] => ram_block1a21.PORTBADDR1
|
|
address_b[1] => ram_block1a22.PORTBADDR1
|
|
address_b[1] => ram_block1a23.PORTBADDR1
|
|
address_b[1] => ram_block1a24.PORTBADDR1
|
|
address_b[1] => ram_block1a25.PORTBADDR1
|
|
address_b[1] => ram_block1a26.PORTBADDR1
|
|
address_b[1] => ram_block1a27.PORTBADDR1
|
|
address_b[1] => ram_block1a28.PORTBADDR1
|
|
address_b[1] => ram_block1a29.PORTBADDR1
|
|
address_b[1] => ram_block1a30.PORTBADDR1
|
|
address_b[1] => ram_block1a31.PORTBADDR1
|
|
address_b[2] => ram_block1a0.PORTBADDR2
|
|
address_b[2] => ram_block1a1.PORTBADDR2
|
|
address_b[2] => ram_block1a2.PORTBADDR2
|
|
address_b[2] => ram_block1a3.PORTBADDR2
|
|
address_b[2] => ram_block1a4.PORTBADDR2
|
|
address_b[2] => ram_block1a5.PORTBADDR2
|
|
address_b[2] => ram_block1a6.PORTBADDR2
|
|
address_b[2] => ram_block1a7.PORTBADDR2
|
|
address_b[2] => ram_block1a8.PORTBADDR2
|
|
address_b[2] => ram_block1a9.PORTBADDR2
|
|
address_b[2] => ram_block1a10.PORTBADDR2
|
|
address_b[2] => ram_block1a11.PORTBADDR2
|
|
address_b[2] => ram_block1a12.PORTBADDR2
|
|
address_b[2] => ram_block1a13.PORTBADDR2
|
|
address_b[2] => ram_block1a14.PORTBADDR2
|
|
address_b[2] => ram_block1a15.PORTBADDR2
|
|
address_b[2] => ram_block1a16.PORTBADDR2
|
|
address_b[2] => ram_block1a17.PORTBADDR2
|
|
address_b[2] => ram_block1a18.PORTBADDR2
|
|
address_b[2] => ram_block1a19.PORTBADDR2
|
|
address_b[2] => ram_block1a20.PORTBADDR2
|
|
address_b[2] => ram_block1a21.PORTBADDR2
|
|
address_b[2] => ram_block1a22.PORTBADDR2
|
|
address_b[2] => ram_block1a23.PORTBADDR2
|
|
address_b[2] => ram_block1a24.PORTBADDR2
|
|
address_b[2] => ram_block1a25.PORTBADDR2
|
|
address_b[2] => ram_block1a26.PORTBADDR2
|
|
address_b[2] => ram_block1a27.PORTBADDR2
|
|
address_b[2] => ram_block1a28.PORTBADDR2
|
|
address_b[2] => ram_block1a29.PORTBADDR2
|
|
address_b[2] => ram_block1a30.PORTBADDR2
|
|
address_b[2] => ram_block1a31.PORTBADDR2
|
|
address_b[3] => ram_block1a0.PORTBADDR3
|
|
address_b[3] => ram_block1a1.PORTBADDR3
|
|
address_b[3] => ram_block1a2.PORTBADDR3
|
|
address_b[3] => ram_block1a3.PORTBADDR3
|
|
address_b[3] => ram_block1a4.PORTBADDR3
|
|
address_b[3] => ram_block1a5.PORTBADDR3
|
|
address_b[3] => ram_block1a6.PORTBADDR3
|
|
address_b[3] => ram_block1a7.PORTBADDR3
|
|
address_b[3] => ram_block1a8.PORTBADDR3
|
|
address_b[3] => ram_block1a9.PORTBADDR3
|
|
address_b[3] => ram_block1a10.PORTBADDR3
|
|
address_b[3] => ram_block1a11.PORTBADDR3
|
|
address_b[3] => ram_block1a12.PORTBADDR3
|
|
address_b[3] => ram_block1a13.PORTBADDR3
|
|
address_b[3] => ram_block1a14.PORTBADDR3
|
|
address_b[3] => ram_block1a15.PORTBADDR3
|
|
address_b[3] => ram_block1a16.PORTBADDR3
|
|
address_b[3] => ram_block1a17.PORTBADDR3
|
|
address_b[3] => ram_block1a18.PORTBADDR3
|
|
address_b[3] => ram_block1a19.PORTBADDR3
|
|
address_b[3] => ram_block1a20.PORTBADDR3
|
|
address_b[3] => ram_block1a21.PORTBADDR3
|
|
address_b[3] => ram_block1a22.PORTBADDR3
|
|
address_b[3] => ram_block1a23.PORTBADDR3
|
|
address_b[3] => ram_block1a24.PORTBADDR3
|
|
address_b[3] => ram_block1a25.PORTBADDR3
|
|
address_b[3] => ram_block1a26.PORTBADDR3
|
|
address_b[3] => ram_block1a27.PORTBADDR3
|
|
address_b[3] => ram_block1a28.PORTBADDR3
|
|
address_b[3] => ram_block1a29.PORTBADDR3
|
|
address_b[3] => ram_block1a30.PORTBADDR3
|
|
address_b[3] => ram_block1a31.PORTBADDR3
|
|
address_b[4] => ram_block1a0.PORTBADDR4
|
|
address_b[4] => ram_block1a1.PORTBADDR4
|
|
address_b[4] => ram_block1a2.PORTBADDR4
|
|
address_b[4] => ram_block1a3.PORTBADDR4
|
|
address_b[4] => ram_block1a4.PORTBADDR4
|
|
address_b[4] => ram_block1a5.PORTBADDR4
|
|
address_b[4] => ram_block1a6.PORTBADDR4
|
|
address_b[4] => ram_block1a7.PORTBADDR4
|
|
address_b[4] => ram_block1a8.PORTBADDR4
|
|
address_b[4] => ram_block1a9.PORTBADDR4
|
|
address_b[4] => ram_block1a10.PORTBADDR4
|
|
address_b[4] => ram_block1a11.PORTBADDR4
|
|
address_b[4] => ram_block1a12.PORTBADDR4
|
|
address_b[4] => ram_block1a13.PORTBADDR4
|
|
address_b[4] => ram_block1a14.PORTBADDR4
|
|
address_b[4] => ram_block1a15.PORTBADDR4
|
|
address_b[4] => ram_block1a16.PORTBADDR4
|
|
address_b[4] => ram_block1a17.PORTBADDR4
|
|
address_b[4] => ram_block1a18.PORTBADDR4
|
|
address_b[4] => ram_block1a19.PORTBADDR4
|
|
address_b[4] => ram_block1a20.PORTBADDR4
|
|
address_b[4] => ram_block1a21.PORTBADDR4
|
|
address_b[4] => ram_block1a22.PORTBADDR4
|
|
address_b[4] => ram_block1a23.PORTBADDR4
|
|
address_b[4] => ram_block1a24.PORTBADDR4
|
|
address_b[4] => ram_block1a25.PORTBADDR4
|
|
address_b[4] => ram_block1a26.PORTBADDR4
|
|
address_b[4] => ram_block1a27.PORTBADDR4
|
|
address_b[4] => ram_block1a28.PORTBADDR4
|
|
address_b[4] => ram_block1a29.PORTBADDR4
|
|
address_b[4] => ram_block1a30.PORTBADDR4
|
|
address_b[4] => ram_block1a31.PORTBADDR4
|
|
clock0 => ram_block1a0.CLK0
|
|
clock0 => ram_block1a1.CLK0
|
|
clock0 => ram_block1a2.CLK0
|
|
clock0 => ram_block1a3.CLK0
|
|
clock0 => ram_block1a4.CLK0
|
|
clock0 => ram_block1a5.CLK0
|
|
clock0 => ram_block1a6.CLK0
|
|
clock0 => ram_block1a7.CLK0
|
|
clock0 => ram_block1a8.CLK0
|
|
clock0 => ram_block1a9.CLK0
|
|
clock0 => ram_block1a10.CLK0
|
|
clock0 => ram_block1a11.CLK0
|
|
clock0 => ram_block1a12.CLK0
|
|
clock0 => ram_block1a13.CLK0
|
|
clock0 => ram_block1a14.CLK0
|
|
clock0 => ram_block1a15.CLK0
|
|
clock0 => ram_block1a16.CLK0
|
|
clock0 => ram_block1a17.CLK0
|
|
clock0 => ram_block1a18.CLK0
|
|
clock0 => ram_block1a19.CLK0
|
|
clock0 => ram_block1a20.CLK0
|
|
clock0 => ram_block1a21.CLK0
|
|
clock0 => ram_block1a22.CLK0
|
|
clock0 => ram_block1a23.CLK0
|
|
clock0 => ram_block1a24.CLK0
|
|
clock0 => ram_block1a25.CLK0
|
|
clock0 => ram_block1a26.CLK0
|
|
clock0 => ram_block1a27.CLK0
|
|
clock0 => ram_block1a28.CLK0
|
|
clock0 => ram_block1a29.CLK0
|
|
clock0 => ram_block1a30.CLK0
|
|
clock0 => ram_block1a31.CLK0
|
|
data_a[0] => ram_block1a0.PORTADATAIN
|
|
data_a[1] => ram_block1a1.PORTADATAIN
|
|
data_a[2] => ram_block1a2.PORTADATAIN
|
|
data_a[3] => ram_block1a3.PORTADATAIN
|
|
data_a[4] => ram_block1a4.PORTADATAIN
|
|
data_a[5] => ram_block1a5.PORTADATAIN
|
|
data_a[6] => ram_block1a6.PORTADATAIN
|
|
data_a[7] => ram_block1a7.PORTADATAIN
|
|
data_a[8] => ram_block1a8.PORTADATAIN
|
|
data_a[9] => ram_block1a9.PORTADATAIN
|
|
data_a[10] => ram_block1a10.PORTADATAIN
|
|
data_a[11] => ram_block1a11.PORTADATAIN
|
|
data_a[12] => ram_block1a12.PORTADATAIN
|
|
data_a[13] => ram_block1a13.PORTADATAIN
|
|
data_a[14] => ram_block1a14.PORTADATAIN
|
|
data_a[15] => ram_block1a15.PORTADATAIN
|
|
data_a[16] => ram_block1a16.PORTADATAIN
|
|
data_a[17] => ram_block1a17.PORTADATAIN
|
|
data_a[18] => ram_block1a18.PORTADATAIN
|
|
data_a[19] => ram_block1a19.PORTADATAIN
|
|
data_a[20] => ram_block1a20.PORTADATAIN
|
|
data_a[21] => ram_block1a21.PORTADATAIN
|
|
data_a[22] => ram_block1a22.PORTADATAIN
|
|
data_a[23] => ram_block1a23.PORTADATAIN
|
|
data_a[24] => ram_block1a24.PORTADATAIN
|
|
data_a[25] => ram_block1a25.PORTADATAIN
|
|
data_a[26] => ram_block1a26.PORTADATAIN
|
|
data_a[27] => ram_block1a27.PORTADATAIN
|
|
data_a[28] => ram_block1a28.PORTADATAIN
|
|
data_a[29] => ram_block1a29.PORTADATAIN
|
|
data_a[30] => ram_block1a30.PORTADATAIN
|
|
data_a[31] => ram_block1a31.PORTADATAIN
|
|
q_b[0] <= ram_block1a0.PORTBDATAOUT
|
|
q_b[1] <= ram_block1a1.PORTBDATAOUT
|
|
q_b[2] <= ram_block1a2.PORTBDATAOUT
|
|
q_b[3] <= ram_block1a3.PORTBDATAOUT
|
|
q_b[4] <= ram_block1a4.PORTBDATAOUT
|
|
q_b[5] <= ram_block1a5.PORTBDATAOUT
|
|
q_b[6] <= ram_block1a6.PORTBDATAOUT
|
|
q_b[7] <= ram_block1a7.PORTBDATAOUT
|
|
q_b[8] <= ram_block1a8.PORTBDATAOUT
|
|
q_b[9] <= ram_block1a9.PORTBDATAOUT
|
|
q_b[10] <= ram_block1a10.PORTBDATAOUT
|
|
q_b[11] <= ram_block1a11.PORTBDATAOUT
|
|
q_b[12] <= ram_block1a12.PORTBDATAOUT
|
|
q_b[13] <= ram_block1a13.PORTBDATAOUT
|
|
q_b[14] <= ram_block1a14.PORTBDATAOUT
|
|
q_b[15] <= ram_block1a15.PORTBDATAOUT
|
|
q_b[16] <= ram_block1a16.PORTBDATAOUT
|
|
q_b[17] <= ram_block1a17.PORTBDATAOUT
|
|
q_b[18] <= ram_block1a18.PORTBDATAOUT
|
|
q_b[19] <= ram_block1a19.PORTBDATAOUT
|
|
q_b[20] <= ram_block1a20.PORTBDATAOUT
|
|
q_b[21] <= ram_block1a21.PORTBDATAOUT
|
|
q_b[22] <= ram_block1a22.PORTBDATAOUT
|
|
q_b[23] <= ram_block1a23.PORTBDATAOUT
|
|
q_b[24] <= ram_block1a24.PORTBDATAOUT
|
|
q_b[25] <= ram_block1a25.PORTBDATAOUT
|
|
q_b[26] <= ram_block1a26.PORTBDATAOUT
|
|
q_b[27] <= ram_block1a27.PORTBDATAOUT
|
|
q_b[28] <= ram_block1a28.PORTBDATAOUT
|
|
q_b[29] <= ram_block1a29.PORTBDATAOUT
|
|
q_b[30] <= ram_block1a30.PORTBDATAOUT
|
|
q_b[31] <= ram_block1a31.PORTBDATAOUT
|
|
wren_a => ram_block1a0.PORTAWE
|
|
wren_a => ram_block1a1.PORTAWE
|
|
wren_a => ram_block1a2.PORTAWE
|
|
wren_a => ram_block1a3.PORTAWE
|
|
wren_a => ram_block1a4.PORTAWE
|
|
wren_a => ram_block1a5.PORTAWE
|
|
wren_a => ram_block1a6.PORTAWE
|
|
wren_a => ram_block1a7.PORTAWE
|
|
wren_a => ram_block1a8.PORTAWE
|
|
wren_a => ram_block1a9.PORTAWE
|
|
wren_a => ram_block1a10.PORTAWE
|
|
wren_a => ram_block1a11.PORTAWE
|
|
wren_a => ram_block1a12.PORTAWE
|
|
wren_a => ram_block1a13.PORTAWE
|
|
wren_a => ram_block1a14.PORTAWE
|
|
wren_a => ram_block1a15.PORTAWE
|
|
wren_a => ram_block1a16.PORTAWE
|
|
wren_a => ram_block1a17.PORTAWE
|
|
wren_a => ram_block1a18.PORTAWE
|
|
wren_a => ram_block1a19.PORTAWE
|
|
wren_a => ram_block1a20.PORTAWE
|
|
wren_a => ram_block1a21.PORTAWE
|
|
wren_a => ram_block1a22.PORTAWE
|
|
wren_a => ram_block1a23.PORTAWE
|
|
wren_a => ram_block1a24.PORTAWE
|
|
wren_a => ram_block1a25.PORTAWE
|
|
wren_a => ram_block1a26.PORTAWE
|
|
wren_a => ram_block1a27.PORTAWE
|
|
wren_a => ram_block1a28.PORTAWE
|
|
wren_a => ram_block1a29.PORTAWE
|
|
wren_a => ram_block1a30.PORTAWE
|
|
wren_a => ram_block1a31.PORTAWE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_alu:neorv32_cpu_alu_inst
|
|
clk_i => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.clk_i
|
|
clk_i => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.clk_i
|
|
rstn_i => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rstn_i
|
|
rstn_i => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rstn_i
|
|
ctrl_i[0] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[0]
|
|
ctrl_i[0] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[0]
|
|
ctrl_i[1] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[1]
|
|
ctrl_i[1] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[1]
|
|
ctrl_i[2] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[2]
|
|
ctrl_i[2] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[2]
|
|
ctrl_i[3] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[3]
|
|
ctrl_i[3] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[3]
|
|
ctrl_i[4] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[4]
|
|
ctrl_i[4] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[4]
|
|
ctrl_i[5] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[5]
|
|
ctrl_i[5] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[5]
|
|
ctrl_i[6] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[6]
|
|
ctrl_i[6] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[6]
|
|
ctrl_i[7] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[7]
|
|
ctrl_i[7] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[7]
|
|
ctrl_i[8] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[8]
|
|
ctrl_i[8] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[8]
|
|
ctrl_i[9] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[9]
|
|
ctrl_i[9] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[9]
|
|
ctrl_i[10] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[10]
|
|
ctrl_i[10] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[10]
|
|
ctrl_i[11] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[11]
|
|
ctrl_i[11] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[11]
|
|
ctrl_i[12] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[12]
|
|
ctrl_i[12] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[12]
|
|
ctrl_i[13] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[13]
|
|
ctrl_i[13] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[13]
|
|
ctrl_i[14] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[14]
|
|
ctrl_i[14] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[14]
|
|
ctrl_i[15] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[15]
|
|
ctrl_i[15] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[15]
|
|
ctrl_i[16] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[16]
|
|
ctrl_i[16] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[16]
|
|
ctrl_i[17] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[17]
|
|
ctrl_i[17] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[17]
|
|
ctrl_i[18] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[18]
|
|
ctrl_i[18] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[18]
|
|
ctrl_i[19] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[19]
|
|
ctrl_i[19] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[19]
|
|
ctrl_i[20] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[20]
|
|
ctrl_i[20] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[20]
|
|
ctrl_i[21] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[21]
|
|
ctrl_i[21] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[21]
|
|
ctrl_i[22] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[22]
|
|
ctrl_i[22] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[22]
|
|
ctrl_i[23] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[23]
|
|
ctrl_i[23] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[23]
|
|
ctrl_i[24] => addsub_res[32].OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => addsub_res.OUTPUTSELECT
|
|
ctrl_i[24] => Mux0.IN6
|
|
ctrl_i[24] => Mux1.IN6
|
|
ctrl_i[24] => Mux2.IN6
|
|
ctrl_i[24] => Mux3.IN6
|
|
ctrl_i[24] => Mux4.IN6
|
|
ctrl_i[24] => Mux5.IN6
|
|
ctrl_i[24] => Mux6.IN6
|
|
ctrl_i[24] => Mux7.IN6
|
|
ctrl_i[24] => Mux8.IN6
|
|
ctrl_i[24] => Mux9.IN6
|
|
ctrl_i[24] => Mux10.IN6
|
|
ctrl_i[24] => Mux11.IN6
|
|
ctrl_i[24] => Mux12.IN6
|
|
ctrl_i[24] => Mux13.IN6
|
|
ctrl_i[24] => Mux14.IN6
|
|
ctrl_i[24] => Mux15.IN6
|
|
ctrl_i[24] => Mux16.IN6
|
|
ctrl_i[24] => Mux17.IN6
|
|
ctrl_i[24] => Mux18.IN6
|
|
ctrl_i[24] => Mux19.IN6
|
|
ctrl_i[24] => Mux20.IN6
|
|
ctrl_i[24] => Mux21.IN6
|
|
ctrl_i[24] => Mux22.IN6
|
|
ctrl_i[24] => Mux23.IN6
|
|
ctrl_i[24] => Mux24.IN6
|
|
ctrl_i[24] => Mux25.IN6
|
|
ctrl_i[24] => Mux26.IN6
|
|
ctrl_i[24] => Mux27.IN6
|
|
ctrl_i[24] => Mux28.IN6
|
|
ctrl_i[24] => Mux29.IN6
|
|
ctrl_i[24] => Mux30.IN6
|
|
ctrl_i[24] => Mux31.IN5
|
|
ctrl_i[24] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[24]
|
|
ctrl_i[24] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[24]
|
|
ctrl_i[25] => Mux0.IN5
|
|
ctrl_i[25] => Mux1.IN5
|
|
ctrl_i[25] => Mux2.IN5
|
|
ctrl_i[25] => Mux3.IN5
|
|
ctrl_i[25] => Mux4.IN5
|
|
ctrl_i[25] => Mux5.IN5
|
|
ctrl_i[25] => Mux6.IN5
|
|
ctrl_i[25] => Mux7.IN5
|
|
ctrl_i[25] => Mux8.IN5
|
|
ctrl_i[25] => Mux9.IN5
|
|
ctrl_i[25] => Mux10.IN5
|
|
ctrl_i[25] => Mux11.IN5
|
|
ctrl_i[25] => Mux12.IN5
|
|
ctrl_i[25] => Mux13.IN5
|
|
ctrl_i[25] => Mux14.IN5
|
|
ctrl_i[25] => Mux15.IN5
|
|
ctrl_i[25] => Mux16.IN5
|
|
ctrl_i[25] => Mux17.IN5
|
|
ctrl_i[25] => Mux18.IN5
|
|
ctrl_i[25] => Mux19.IN5
|
|
ctrl_i[25] => Mux20.IN5
|
|
ctrl_i[25] => Mux21.IN5
|
|
ctrl_i[25] => Mux22.IN5
|
|
ctrl_i[25] => Mux23.IN5
|
|
ctrl_i[25] => Mux24.IN5
|
|
ctrl_i[25] => Mux25.IN5
|
|
ctrl_i[25] => Mux26.IN5
|
|
ctrl_i[25] => Mux27.IN5
|
|
ctrl_i[25] => Mux28.IN5
|
|
ctrl_i[25] => Mux29.IN5
|
|
ctrl_i[25] => Mux30.IN5
|
|
ctrl_i[25] => Mux31.IN4
|
|
ctrl_i[25] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[25]
|
|
ctrl_i[25] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[25]
|
|
ctrl_i[26] => Mux0.IN4
|
|
ctrl_i[26] => Mux1.IN4
|
|
ctrl_i[26] => Mux2.IN4
|
|
ctrl_i[26] => Mux3.IN4
|
|
ctrl_i[26] => Mux4.IN4
|
|
ctrl_i[26] => Mux5.IN4
|
|
ctrl_i[26] => Mux6.IN4
|
|
ctrl_i[26] => Mux7.IN4
|
|
ctrl_i[26] => Mux8.IN4
|
|
ctrl_i[26] => Mux9.IN4
|
|
ctrl_i[26] => Mux10.IN4
|
|
ctrl_i[26] => Mux11.IN4
|
|
ctrl_i[26] => Mux12.IN4
|
|
ctrl_i[26] => Mux13.IN4
|
|
ctrl_i[26] => Mux14.IN4
|
|
ctrl_i[26] => Mux15.IN4
|
|
ctrl_i[26] => Mux16.IN4
|
|
ctrl_i[26] => Mux17.IN4
|
|
ctrl_i[26] => Mux18.IN4
|
|
ctrl_i[26] => Mux19.IN4
|
|
ctrl_i[26] => Mux20.IN4
|
|
ctrl_i[26] => Mux21.IN4
|
|
ctrl_i[26] => Mux22.IN4
|
|
ctrl_i[26] => Mux23.IN4
|
|
ctrl_i[26] => Mux24.IN4
|
|
ctrl_i[26] => Mux25.IN4
|
|
ctrl_i[26] => Mux26.IN4
|
|
ctrl_i[26] => Mux27.IN4
|
|
ctrl_i[26] => Mux28.IN4
|
|
ctrl_i[26] => Mux29.IN4
|
|
ctrl_i[26] => Mux30.IN4
|
|
ctrl_i[26] => Mux31.IN3
|
|
ctrl_i[26] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[26]
|
|
ctrl_i[26] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[26]
|
|
ctrl_i[27] => opa[31].OUTPUTSELECT
|
|
ctrl_i[27] => opa[30].OUTPUTSELECT
|
|
ctrl_i[27] => opa[29].OUTPUTSELECT
|
|
ctrl_i[27] => opa[28].OUTPUTSELECT
|
|
ctrl_i[27] => opa[27].OUTPUTSELECT
|
|
ctrl_i[27] => opa[26].OUTPUTSELECT
|
|
ctrl_i[27] => opa[25].OUTPUTSELECT
|
|
ctrl_i[27] => opa[24].OUTPUTSELECT
|
|
ctrl_i[27] => opa[23].OUTPUTSELECT
|
|
ctrl_i[27] => opa[22].OUTPUTSELECT
|
|
ctrl_i[27] => opa[21].OUTPUTSELECT
|
|
ctrl_i[27] => opa[20].OUTPUTSELECT
|
|
ctrl_i[27] => opa[19].OUTPUTSELECT
|
|
ctrl_i[27] => opa[18].OUTPUTSELECT
|
|
ctrl_i[27] => opa[17].OUTPUTSELECT
|
|
ctrl_i[27] => opa[16].OUTPUTSELECT
|
|
ctrl_i[27] => opa[15].OUTPUTSELECT
|
|
ctrl_i[27] => opa[14].OUTPUTSELECT
|
|
ctrl_i[27] => opa[13].OUTPUTSELECT
|
|
ctrl_i[27] => opa[12].OUTPUTSELECT
|
|
ctrl_i[27] => opa[11].OUTPUTSELECT
|
|
ctrl_i[27] => opa[10].OUTPUTSELECT
|
|
ctrl_i[27] => opa[9].OUTPUTSELECT
|
|
ctrl_i[27] => opa[8].OUTPUTSELECT
|
|
ctrl_i[27] => opa[7].OUTPUTSELECT
|
|
ctrl_i[27] => opa[6].OUTPUTSELECT
|
|
ctrl_i[27] => opa[5].OUTPUTSELECT
|
|
ctrl_i[27] => opa[4].OUTPUTSELECT
|
|
ctrl_i[27] => opa[3].OUTPUTSELECT
|
|
ctrl_i[27] => opa[2].OUTPUTSELECT
|
|
ctrl_i[27] => opa[1].OUTPUTSELECT
|
|
ctrl_i[27] => opa[0].OUTPUTSELECT
|
|
ctrl_i[27] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[27]
|
|
ctrl_i[27] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[27]
|
|
ctrl_i[28] => opb[31].OUTPUTSELECT
|
|
ctrl_i[28] => opb[30].OUTPUTSELECT
|
|
ctrl_i[28] => opb[29].OUTPUTSELECT
|
|
ctrl_i[28] => opb[28].OUTPUTSELECT
|
|
ctrl_i[28] => opb[27].OUTPUTSELECT
|
|
ctrl_i[28] => opb[26].OUTPUTSELECT
|
|
ctrl_i[28] => opb[25].OUTPUTSELECT
|
|
ctrl_i[28] => opb[24].OUTPUTSELECT
|
|
ctrl_i[28] => opb[23].OUTPUTSELECT
|
|
ctrl_i[28] => opb[22].OUTPUTSELECT
|
|
ctrl_i[28] => opb[21].OUTPUTSELECT
|
|
ctrl_i[28] => opb[20].OUTPUTSELECT
|
|
ctrl_i[28] => opb[19].OUTPUTSELECT
|
|
ctrl_i[28] => opb[18].OUTPUTSELECT
|
|
ctrl_i[28] => opb[17].OUTPUTSELECT
|
|
ctrl_i[28] => opb[16].OUTPUTSELECT
|
|
ctrl_i[28] => opb[15].OUTPUTSELECT
|
|
ctrl_i[28] => opb[14].OUTPUTSELECT
|
|
ctrl_i[28] => opb[13].OUTPUTSELECT
|
|
ctrl_i[28] => opb[12].OUTPUTSELECT
|
|
ctrl_i[28] => opb[11].OUTPUTSELECT
|
|
ctrl_i[28] => opb[10].OUTPUTSELECT
|
|
ctrl_i[28] => opb[9].OUTPUTSELECT
|
|
ctrl_i[28] => opb[8].OUTPUTSELECT
|
|
ctrl_i[28] => opb[7].OUTPUTSELECT
|
|
ctrl_i[28] => opb[6].OUTPUTSELECT
|
|
ctrl_i[28] => opb[5].OUTPUTSELECT
|
|
ctrl_i[28] => opb[4].OUTPUTSELECT
|
|
ctrl_i[28] => opb[3].OUTPUTSELECT
|
|
ctrl_i[28] => opb[2].OUTPUTSELECT
|
|
ctrl_i[28] => opb[1].OUTPUTSELECT
|
|
ctrl_i[28] => opb[0].OUTPUTSELECT
|
|
ctrl_i[28] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[28]
|
|
ctrl_i[28] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[28]
|
|
ctrl_i[29] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[29]
|
|
ctrl_i[29] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[29]
|
|
ctrl_i[29] => cmp_rs2[32].IN0
|
|
ctrl_i[29] => cmp_rs1[32].IN0
|
|
ctrl_i[29] => \arithmetic_core:opa_v[32].IN1
|
|
ctrl_i[29] => \arithmetic_core:opb_v[32].IN1
|
|
ctrl_i[30] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[30]
|
|
ctrl_i[30] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[30]
|
|
ctrl_i[31] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[31]
|
|
ctrl_i[31] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[31]
|
|
ctrl_i[32] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[32]
|
|
ctrl_i[32] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[32]
|
|
ctrl_i[33] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[33]
|
|
ctrl_i[33] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.start_i
|
|
ctrl_i[33] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[33]
|
|
ctrl_i[34] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[34]
|
|
ctrl_i[34] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[34]
|
|
ctrl_i[34] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.start_i
|
|
ctrl_i[35] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[35]
|
|
ctrl_i[35] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[35]
|
|
ctrl_i[36] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[36]
|
|
ctrl_i[36] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[36]
|
|
ctrl_i[37] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[37]
|
|
ctrl_i[37] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[37]
|
|
ctrl_i[38] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[38]
|
|
ctrl_i[38] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[38]
|
|
ctrl_i[39] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[39]
|
|
ctrl_i[39] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[39]
|
|
ctrl_i[40] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[40]
|
|
ctrl_i[40] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[40]
|
|
ctrl_i[41] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[41]
|
|
ctrl_i[41] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[41]
|
|
ctrl_i[42] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[42]
|
|
ctrl_i[42] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[42]
|
|
ctrl_i[43] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[43]
|
|
ctrl_i[43] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[43]
|
|
ctrl_i[44] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[44]
|
|
ctrl_i[44] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[44]
|
|
ctrl_i[45] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[45]
|
|
ctrl_i[45] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[45]
|
|
ctrl_i[46] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[46]
|
|
ctrl_i[46] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[46]
|
|
ctrl_i[47] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[47]
|
|
ctrl_i[47] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[47]
|
|
ctrl_i[48] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[48]
|
|
ctrl_i[48] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[48]
|
|
ctrl_i[49] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[49]
|
|
ctrl_i[49] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[49]
|
|
ctrl_i[50] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[50]
|
|
ctrl_i[50] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[50]
|
|
ctrl_i[51] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[51]
|
|
ctrl_i[51] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[51]
|
|
ctrl_i[52] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[52]
|
|
ctrl_i[52] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[52]
|
|
ctrl_i[53] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[53]
|
|
ctrl_i[53] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[53]
|
|
ctrl_i[54] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[54]
|
|
ctrl_i[54] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[54]
|
|
ctrl_i[55] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[55]
|
|
ctrl_i[55] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[55]
|
|
ctrl_i[56] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[56]
|
|
ctrl_i[56] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[56]
|
|
ctrl_i[57] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[57]
|
|
ctrl_i[57] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[57]
|
|
ctrl_i[58] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[58]
|
|
ctrl_i[58] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[58]
|
|
ctrl_i[59] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[59]
|
|
ctrl_i[59] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[59]
|
|
ctrl_i[60] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[60]
|
|
ctrl_i[60] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[60]
|
|
ctrl_i[61] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[61]
|
|
ctrl_i[61] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[61]
|
|
ctrl_i[62] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[62]
|
|
ctrl_i[62] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[62]
|
|
ctrl_i[63] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[63]
|
|
ctrl_i[63] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[63]
|
|
ctrl_i[64] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[64]
|
|
ctrl_i[64] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[64]
|
|
ctrl_i[65] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[65]
|
|
ctrl_i[65] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[65]
|
|
ctrl_i[66] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[66]
|
|
ctrl_i[66] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[66]
|
|
ctrl_i[67] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[67]
|
|
ctrl_i[67] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[67]
|
|
ctrl_i[68] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.ctrl_i[68]
|
|
ctrl_i[68] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.ctrl_i[68]
|
|
rs1_i[0] => Equal0.IN31
|
|
rs1_i[0] => opa[0].DATAA
|
|
rs1_i[0] => res_o.IN1
|
|
rs1_i[0] => res_o.IN1
|
|
rs1_i[0] => res_o.IN1
|
|
rs1_i[0] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[0]
|
|
rs1_i[0] => LessThan0.IN32
|
|
rs1_i[0] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[0]
|
|
rs1_i[1] => Equal0.IN30
|
|
rs1_i[1] => opa[1].DATAA
|
|
rs1_i[1] => res_o.IN1
|
|
rs1_i[1] => res_o.IN1
|
|
rs1_i[1] => res_o.IN1
|
|
rs1_i[1] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[1]
|
|
rs1_i[1] => LessThan0.IN31
|
|
rs1_i[1] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[1]
|
|
rs1_i[2] => Equal0.IN29
|
|
rs1_i[2] => opa[2].DATAA
|
|
rs1_i[2] => res_o.IN1
|
|
rs1_i[2] => res_o.IN1
|
|
rs1_i[2] => res_o.IN1
|
|
rs1_i[2] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[2]
|
|
rs1_i[2] => LessThan0.IN30
|
|
rs1_i[2] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[2]
|
|
rs1_i[3] => Equal0.IN28
|
|
rs1_i[3] => opa[3].DATAA
|
|
rs1_i[3] => res_o.IN1
|
|
rs1_i[3] => res_o.IN1
|
|
rs1_i[3] => res_o.IN1
|
|
rs1_i[3] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[3]
|
|
rs1_i[3] => LessThan0.IN29
|
|
rs1_i[3] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[3]
|
|
rs1_i[4] => Equal0.IN27
|
|
rs1_i[4] => opa[4].DATAA
|
|
rs1_i[4] => res_o.IN1
|
|
rs1_i[4] => res_o.IN1
|
|
rs1_i[4] => res_o.IN1
|
|
rs1_i[4] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[4]
|
|
rs1_i[4] => LessThan0.IN28
|
|
rs1_i[4] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[4]
|
|
rs1_i[5] => Equal0.IN26
|
|
rs1_i[5] => opa[5].DATAA
|
|
rs1_i[5] => res_o.IN1
|
|
rs1_i[5] => res_o.IN1
|
|
rs1_i[5] => res_o.IN1
|
|
rs1_i[5] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[5]
|
|
rs1_i[5] => LessThan0.IN27
|
|
rs1_i[5] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[5]
|
|
rs1_i[6] => Equal0.IN25
|
|
rs1_i[6] => opa[6].DATAA
|
|
rs1_i[6] => res_o.IN1
|
|
rs1_i[6] => res_o.IN1
|
|
rs1_i[6] => res_o.IN1
|
|
rs1_i[6] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[6]
|
|
rs1_i[6] => LessThan0.IN26
|
|
rs1_i[6] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[6]
|
|
rs1_i[7] => Equal0.IN24
|
|
rs1_i[7] => opa[7].DATAA
|
|
rs1_i[7] => res_o.IN1
|
|
rs1_i[7] => res_o.IN1
|
|
rs1_i[7] => res_o.IN1
|
|
rs1_i[7] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[7]
|
|
rs1_i[7] => LessThan0.IN25
|
|
rs1_i[7] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[7]
|
|
rs1_i[8] => Equal0.IN23
|
|
rs1_i[8] => opa[8].DATAA
|
|
rs1_i[8] => res_o.IN1
|
|
rs1_i[8] => res_o.IN1
|
|
rs1_i[8] => res_o.IN1
|
|
rs1_i[8] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[8]
|
|
rs1_i[8] => LessThan0.IN24
|
|
rs1_i[8] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[8]
|
|
rs1_i[9] => Equal0.IN22
|
|
rs1_i[9] => opa[9].DATAA
|
|
rs1_i[9] => res_o.IN1
|
|
rs1_i[9] => res_o.IN1
|
|
rs1_i[9] => res_o.IN1
|
|
rs1_i[9] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[9]
|
|
rs1_i[9] => LessThan0.IN23
|
|
rs1_i[9] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[9]
|
|
rs1_i[10] => Equal0.IN21
|
|
rs1_i[10] => opa[10].DATAA
|
|
rs1_i[10] => res_o.IN1
|
|
rs1_i[10] => res_o.IN1
|
|
rs1_i[10] => res_o.IN1
|
|
rs1_i[10] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[10]
|
|
rs1_i[10] => LessThan0.IN22
|
|
rs1_i[10] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[10]
|
|
rs1_i[11] => Equal0.IN20
|
|
rs1_i[11] => opa[11].DATAA
|
|
rs1_i[11] => res_o.IN1
|
|
rs1_i[11] => res_o.IN1
|
|
rs1_i[11] => res_o.IN1
|
|
rs1_i[11] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[11]
|
|
rs1_i[11] => LessThan0.IN21
|
|
rs1_i[11] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[11]
|
|
rs1_i[12] => Equal0.IN19
|
|
rs1_i[12] => opa[12].DATAA
|
|
rs1_i[12] => res_o.IN1
|
|
rs1_i[12] => res_o.IN1
|
|
rs1_i[12] => res_o.IN1
|
|
rs1_i[12] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[12]
|
|
rs1_i[12] => LessThan0.IN20
|
|
rs1_i[12] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[12]
|
|
rs1_i[13] => Equal0.IN18
|
|
rs1_i[13] => opa[13].DATAA
|
|
rs1_i[13] => res_o.IN1
|
|
rs1_i[13] => res_o.IN1
|
|
rs1_i[13] => res_o.IN1
|
|
rs1_i[13] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[13]
|
|
rs1_i[13] => LessThan0.IN19
|
|
rs1_i[13] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[13]
|
|
rs1_i[14] => Equal0.IN17
|
|
rs1_i[14] => opa[14].DATAA
|
|
rs1_i[14] => res_o.IN1
|
|
rs1_i[14] => res_o.IN1
|
|
rs1_i[14] => res_o.IN1
|
|
rs1_i[14] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[14]
|
|
rs1_i[14] => LessThan0.IN18
|
|
rs1_i[14] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[14]
|
|
rs1_i[15] => Equal0.IN16
|
|
rs1_i[15] => opa[15].DATAA
|
|
rs1_i[15] => res_o.IN1
|
|
rs1_i[15] => res_o.IN1
|
|
rs1_i[15] => res_o.IN1
|
|
rs1_i[15] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[15]
|
|
rs1_i[15] => LessThan0.IN17
|
|
rs1_i[15] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[15]
|
|
rs1_i[16] => Equal0.IN15
|
|
rs1_i[16] => opa[16].DATAA
|
|
rs1_i[16] => res_o.IN1
|
|
rs1_i[16] => res_o.IN1
|
|
rs1_i[16] => res_o.IN1
|
|
rs1_i[16] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[16]
|
|
rs1_i[16] => LessThan0.IN16
|
|
rs1_i[16] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[16]
|
|
rs1_i[17] => Equal0.IN14
|
|
rs1_i[17] => opa[17].DATAA
|
|
rs1_i[17] => res_o.IN1
|
|
rs1_i[17] => res_o.IN1
|
|
rs1_i[17] => res_o.IN1
|
|
rs1_i[17] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[17]
|
|
rs1_i[17] => LessThan0.IN15
|
|
rs1_i[17] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[17]
|
|
rs1_i[18] => Equal0.IN13
|
|
rs1_i[18] => opa[18].DATAA
|
|
rs1_i[18] => res_o.IN1
|
|
rs1_i[18] => res_o.IN1
|
|
rs1_i[18] => res_o.IN1
|
|
rs1_i[18] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[18]
|
|
rs1_i[18] => LessThan0.IN14
|
|
rs1_i[18] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[18]
|
|
rs1_i[19] => Equal0.IN12
|
|
rs1_i[19] => opa[19].DATAA
|
|
rs1_i[19] => res_o.IN1
|
|
rs1_i[19] => res_o.IN1
|
|
rs1_i[19] => res_o.IN1
|
|
rs1_i[19] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[19]
|
|
rs1_i[19] => LessThan0.IN13
|
|
rs1_i[19] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[19]
|
|
rs1_i[20] => Equal0.IN11
|
|
rs1_i[20] => opa[20].DATAA
|
|
rs1_i[20] => res_o.IN1
|
|
rs1_i[20] => res_o.IN1
|
|
rs1_i[20] => res_o.IN1
|
|
rs1_i[20] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[20]
|
|
rs1_i[20] => LessThan0.IN12
|
|
rs1_i[20] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[20]
|
|
rs1_i[21] => Equal0.IN10
|
|
rs1_i[21] => opa[21].DATAA
|
|
rs1_i[21] => res_o.IN1
|
|
rs1_i[21] => res_o.IN1
|
|
rs1_i[21] => res_o.IN1
|
|
rs1_i[21] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[21]
|
|
rs1_i[21] => LessThan0.IN11
|
|
rs1_i[21] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[21]
|
|
rs1_i[22] => Equal0.IN9
|
|
rs1_i[22] => opa[22].DATAA
|
|
rs1_i[22] => res_o.IN1
|
|
rs1_i[22] => res_o.IN1
|
|
rs1_i[22] => res_o.IN1
|
|
rs1_i[22] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[22]
|
|
rs1_i[22] => LessThan0.IN10
|
|
rs1_i[22] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[22]
|
|
rs1_i[23] => Equal0.IN8
|
|
rs1_i[23] => opa[23].DATAA
|
|
rs1_i[23] => res_o.IN1
|
|
rs1_i[23] => res_o.IN1
|
|
rs1_i[23] => res_o.IN1
|
|
rs1_i[23] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[23]
|
|
rs1_i[23] => LessThan0.IN9
|
|
rs1_i[23] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[23]
|
|
rs1_i[24] => Equal0.IN7
|
|
rs1_i[24] => opa[24].DATAA
|
|
rs1_i[24] => res_o.IN1
|
|
rs1_i[24] => res_o.IN1
|
|
rs1_i[24] => res_o.IN1
|
|
rs1_i[24] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[24]
|
|
rs1_i[24] => LessThan0.IN8
|
|
rs1_i[24] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[24]
|
|
rs1_i[25] => Equal0.IN6
|
|
rs1_i[25] => opa[25].DATAA
|
|
rs1_i[25] => res_o.IN1
|
|
rs1_i[25] => res_o.IN1
|
|
rs1_i[25] => res_o.IN1
|
|
rs1_i[25] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[25]
|
|
rs1_i[25] => LessThan0.IN7
|
|
rs1_i[25] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[25]
|
|
rs1_i[26] => Equal0.IN5
|
|
rs1_i[26] => opa[26].DATAA
|
|
rs1_i[26] => res_o.IN1
|
|
rs1_i[26] => res_o.IN1
|
|
rs1_i[26] => res_o.IN1
|
|
rs1_i[26] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[26]
|
|
rs1_i[26] => LessThan0.IN6
|
|
rs1_i[26] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[26]
|
|
rs1_i[27] => Equal0.IN4
|
|
rs1_i[27] => opa[27].DATAA
|
|
rs1_i[27] => res_o.IN1
|
|
rs1_i[27] => res_o.IN1
|
|
rs1_i[27] => res_o.IN1
|
|
rs1_i[27] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[27]
|
|
rs1_i[27] => LessThan0.IN5
|
|
rs1_i[27] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[27]
|
|
rs1_i[28] => Equal0.IN3
|
|
rs1_i[28] => opa[28].DATAA
|
|
rs1_i[28] => res_o.IN1
|
|
rs1_i[28] => res_o.IN1
|
|
rs1_i[28] => res_o.IN1
|
|
rs1_i[28] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[28]
|
|
rs1_i[28] => LessThan0.IN4
|
|
rs1_i[28] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[28]
|
|
rs1_i[29] => Equal0.IN2
|
|
rs1_i[29] => opa[29].DATAA
|
|
rs1_i[29] => res_o.IN1
|
|
rs1_i[29] => res_o.IN1
|
|
rs1_i[29] => res_o.IN1
|
|
rs1_i[29] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[29]
|
|
rs1_i[29] => LessThan0.IN3
|
|
rs1_i[29] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[29]
|
|
rs1_i[30] => Equal0.IN1
|
|
rs1_i[30] => opa[30].DATAA
|
|
rs1_i[30] => res_o.IN1
|
|
rs1_i[30] => res_o.IN1
|
|
rs1_i[30] => res_o.IN1
|
|
rs1_i[30] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[30]
|
|
rs1_i[30] => LessThan0.IN2
|
|
rs1_i[30] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[30]
|
|
rs1_i[31] => cmp_rs1[32].IN1
|
|
rs1_i[31] => Equal0.IN0
|
|
rs1_i[31] => opa[31].DATAA
|
|
rs1_i[31] => res_o.IN1
|
|
rs1_i[31] => res_o.IN1
|
|
rs1_i[31] => res_o.IN1
|
|
rs1_i[31] => neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst.rs1_i[31]
|
|
rs1_i[31] => LessThan0.IN1
|
|
rs1_i[31] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs1_i[31]
|
|
rs2_i[0] => Equal0.IN63
|
|
rs2_i[0] => opb[0].DATAA
|
|
rs2_i[0] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[0]
|
|
rs2_i[0] => LessThan0.IN64
|
|
rs2_i[1] => Equal0.IN62
|
|
rs2_i[1] => opb[1].DATAA
|
|
rs2_i[1] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[1]
|
|
rs2_i[1] => LessThan0.IN63
|
|
rs2_i[2] => Equal0.IN61
|
|
rs2_i[2] => opb[2].DATAA
|
|
rs2_i[2] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[2]
|
|
rs2_i[2] => LessThan0.IN62
|
|
rs2_i[3] => Equal0.IN60
|
|
rs2_i[3] => opb[3].DATAA
|
|
rs2_i[3] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[3]
|
|
rs2_i[3] => LessThan0.IN61
|
|
rs2_i[4] => Equal0.IN59
|
|
rs2_i[4] => opb[4].DATAA
|
|
rs2_i[4] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[4]
|
|
rs2_i[4] => LessThan0.IN60
|
|
rs2_i[5] => Equal0.IN58
|
|
rs2_i[5] => opb[5].DATAA
|
|
rs2_i[5] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[5]
|
|
rs2_i[5] => LessThan0.IN59
|
|
rs2_i[6] => Equal0.IN57
|
|
rs2_i[6] => opb[6].DATAA
|
|
rs2_i[6] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[6]
|
|
rs2_i[6] => LessThan0.IN58
|
|
rs2_i[7] => Equal0.IN56
|
|
rs2_i[7] => opb[7].DATAA
|
|
rs2_i[7] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[7]
|
|
rs2_i[7] => LessThan0.IN57
|
|
rs2_i[8] => Equal0.IN55
|
|
rs2_i[8] => opb[8].DATAA
|
|
rs2_i[8] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[8]
|
|
rs2_i[8] => LessThan0.IN56
|
|
rs2_i[9] => Equal0.IN54
|
|
rs2_i[9] => opb[9].DATAA
|
|
rs2_i[9] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[9]
|
|
rs2_i[9] => LessThan0.IN55
|
|
rs2_i[10] => Equal0.IN53
|
|
rs2_i[10] => opb[10].DATAA
|
|
rs2_i[10] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[10]
|
|
rs2_i[10] => LessThan0.IN54
|
|
rs2_i[11] => Equal0.IN52
|
|
rs2_i[11] => opb[11].DATAA
|
|
rs2_i[11] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[11]
|
|
rs2_i[11] => LessThan0.IN53
|
|
rs2_i[12] => Equal0.IN51
|
|
rs2_i[12] => opb[12].DATAA
|
|
rs2_i[12] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[12]
|
|
rs2_i[12] => LessThan0.IN52
|
|
rs2_i[13] => Equal0.IN50
|
|
rs2_i[13] => opb[13].DATAA
|
|
rs2_i[13] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[13]
|
|
rs2_i[13] => LessThan0.IN51
|
|
rs2_i[14] => Equal0.IN49
|
|
rs2_i[14] => opb[14].DATAA
|
|
rs2_i[14] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[14]
|
|
rs2_i[14] => LessThan0.IN50
|
|
rs2_i[15] => Equal0.IN48
|
|
rs2_i[15] => opb[15].DATAA
|
|
rs2_i[15] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[15]
|
|
rs2_i[15] => LessThan0.IN49
|
|
rs2_i[16] => Equal0.IN47
|
|
rs2_i[16] => opb[16].DATAA
|
|
rs2_i[16] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[16]
|
|
rs2_i[16] => LessThan0.IN48
|
|
rs2_i[17] => Equal0.IN46
|
|
rs2_i[17] => opb[17].DATAA
|
|
rs2_i[17] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[17]
|
|
rs2_i[17] => LessThan0.IN47
|
|
rs2_i[18] => Equal0.IN45
|
|
rs2_i[18] => opb[18].DATAA
|
|
rs2_i[18] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[18]
|
|
rs2_i[18] => LessThan0.IN46
|
|
rs2_i[19] => Equal0.IN44
|
|
rs2_i[19] => opb[19].DATAA
|
|
rs2_i[19] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[19]
|
|
rs2_i[19] => LessThan0.IN45
|
|
rs2_i[20] => Equal0.IN43
|
|
rs2_i[20] => opb[20].DATAA
|
|
rs2_i[20] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[20]
|
|
rs2_i[20] => LessThan0.IN44
|
|
rs2_i[21] => Equal0.IN42
|
|
rs2_i[21] => opb[21].DATAA
|
|
rs2_i[21] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[21]
|
|
rs2_i[21] => LessThan0.IN43
|
|
rs2_i[22] => Equal0.IN41
|
|
rs2_i[22] => opb[22].DATAA
|
|
rs2_i[22] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[22]
|
|
rs2_i[22] => LessThan0.IN42
|
|
rs2_i[23] => Equal0.IN40
|
|
rs2_i[23] => opb[23].DATAA
|
|
rs2_i[23] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[23]
|
|
rs2_i[23] => LessThan0.IN41
|
|
rs2_i[24] => Equal0.IN39
|
|
rs2_i[24] => opb[24].DATAA
|
|
rs2_i[24] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[24]
|
|
rs2_i[24] => LessThan0.IN40
|
|
rs2_i[25] => Equal0.IN38
|
|
rs2_i[25] => opb[25].DATAA
|
|
rs2_i[25] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[25]
|
|
rs2_i[25] => LessThan0.IN39
|
|
rs2_i[26] => Equal0.IN37
|
|
rs2_i[26] => opb[26].DATAA
|
|
rs2_i[26] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[26]
|
|
rs2_i[26] => LessThan0.IN38
|
|
rs2_i[27] => Equal0.IN36
|
|
rs2_i[27] => opb[27].DATAA
|
|
rs2_i[27] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[27]
|
|
rs2_i[27] => LessThan0.IN37
|
|
rs2_i[28] => Equal0.IN35
|
|
rs2_i[28] => opb[28].DATAA
|
|
rs2_i[28] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[28]
|
|
rs2_i[28] => LessThan0.IN36
|
|
rs2_i[29] => Equal0.IN34
|
|
rs2_i[29] => opb[29].DATAA
|
|
rs2_i[29] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[29]
|
|
rs2_i[29] => LessThan0.IN35
|
|
rs2_i[30] => Equal0.IN33
|
|
rs2_i[30] => opb[30].DATAA
|
|
rs2_i[30] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[30]
|
|
rs2_i[30] => LessThan0.IN34
|
|
rs2_i[31] => cmp_rs2[32].IN1
|
|
rs2_i[31] => Equal0.IN32
|
|
rs2_i[31] => opb[31].DATAA
|
|
rs2_i[31] => neorv32_cpu_cp_muldiv:neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst.rs2_i[31]
|
|
rs2_i[31] => LessThan0.IN33
|
|
rs3_i[0] => ~NO_FANOUT~
|
|
rs3_i[1] => ~NO_FANOUT~
|
|
rs3_i[2] => ~NO_FANOUT~
|
|
rs3_i[3] => ~NO_FANOUT~
|
|
rs3_i[4] => ~NO_FANOUT~
|
|
rs3_i[5] => ~NO_FANOUT~
|
|
rs3_i[6] => ~NO_FANOUT~
|
|
rs3_i[7] => ~NO_FANOUT~
|
|
rs3_i[8] => ~NO_FANOUT~
|
|
rs3_i[9] => ~NO_FANOUT~
|
|
rs3_i[10] => ~NO_FANOUT~
|
|
rs3_i[11] => ~NO_FANOUT~
|
|
rs3_i[12] => ~NO_FANOUT~
|
|
rs3_i[13] => ~NO_FANOUT~
|
|
rs3_i[14] => ~NO_FANOUT~
|
|
rs3_i[15] => ~NO_FANOUT~
|
|
rs3_i[16] => ~NO_FANOUT~
|
|
rs3_i[17] => ~NO_FANOUT~
|
|
rs3_i[18] => ~NO_FANOUT~
|
|
rs3_i[19] => ~NO_FANOUT~
|
|
rs3_i[20] => ~NO_FANOUT~
|
|
rs3_i[21] => ~NO_FANOUT~
|
|
rs3_i[22] => ~NO_FANOUT~
|
|
rs3_i[23] => ~NO_FANOUT~
|
|
rs3_i[24] => ~NO_FANOUT~
|
|
rs3_i[25] => ~NO_FANOUT~
|
|
rs3_i[26] => ~NO_FANOUT~
|
|
rs3_i[27] => ~NO_FANOUT~
|
|
rs3_i[28] => ~NO_FANOUT~
|
|
rs3_i[29] => ~NO_FANOUT~
|
|
rs3_i[30] => ~NO_FANOUT~
|
|
rs3_i[31] => ~NO_FANOUT~
|
|
rs4_i[0] => ~NO_FANOUT~
|
|
rs4_i[1] => ~NO_FANOUT~
|
|
rs4_i[2] => ~NO_FANOUT~
|
|
rs4_i[3] => ~NO_FANOUT~
|
|
rs4_i[4] => ~NO_FANOUT~
|
|
rs4_i[5] => ~NO_FANOUT~
|
|
rs4_i[6] => ~NO_FANOUT~
|
|
rs4_i[7] => ~NO_FANOUT~
|
|
rs4_i[8] => ~NO_FANOUT~
|
|
rs4_i[9] => ~NO_FANOUT~
|
|
rs4_i[10] => ~NO_FANOUT~
|
|
rs4_i[11] => ~NO_FANOUT~
|
|
rs4_i[12] => ~NO_FANOUT~
|
|
rs4_i[13] => ~NO_FANOUT~
|
|
rs4_i[14] => ~NO_FANOUT~
|
|
rs4_i[15] => ~NO_FANOUT~
|
|
rs4_i[16] => ~NO_FANOUT~
|
|
rs4_i[17] => ~NO_FANOUT~
|
|
rs4_i[18] => ~NO_FANOUT~
|
|
rs4_i[19] => ~NO_FANOUT~
|
|
rs4_i[20] => ~NO_FANOUT~
|
|
rs4_i[21] => ~NO_FANOUT~
|
|
rs4_i[22] => ~NO_FANOUT~
|
|
rs4_i[23] => ~NO_FANOUT~
|
|
rs4_i[24] => ~NO_FANOUT~
|
|
rs4_i[25] => ~NO_FANOUT~
|
|
rs4_i[26] => ~NO_FANOUT~
|
|
rs4_i[27] => ~NO_FANOUT~
|
|
rs4_i[28] => ~NO_FANOUT~
|
|
rs4_i[29] => ~NO_FANOUT~
|
|
rs4_i[30] => ~NO_FANOUT~
|
|
rs4_i[31] => ~NO_FANOUT~
|
|
pc_i[0] => opa[0].DATAB
|
|
pc_i[1] => opa[1].DATAB
|
|
pc_i[2] => opa[2].DATAB
|
|
pc_i[3] => opa[3].DATAB
|
|
pc_i[4] => opa[4].DATAB
|
|
pc_i[5] => opa[5].DATAB
|
|
pc_i[6] => opa[6].DATAB
|
|
pc_i[7] => opa[7].DATAB
|
|
pc_i[8] => opa[8].DATAB
|
|
pc_i[9] => opa[9].DATAB
|
|
pc_i[10] => opa[10].DATAB
|
|
pc_i[11] => opa[11].DATAB
|
|
pc_i[12] => opa[12].DATAB
|
|
pc_i[13] => opa[13].DATAB
|
|
pc_i[14] => opa[14].DATAB
|
|
pc_i[15] => opa[15].DATAB
|
|
pc_i[16] => opa[16].DATAB
|
|
pc_i[17] => opa[17].DATAB
|
|
pc_i[18] => opa[18].DATAB
|
|
pc_i[19] => opa[19].DATAB
|
|
pc_i[20] => opa[20].DATAB
|
|
pc_i[21] => opa[21].DATAB
|
|
pc_i[22] => opa[22].DATAB
|
|
pc_i[23] => opa[23].DATAB
|
|
pc_i[24] => opa[24].DATAB
|
|
pc_i[25] => opa[25].DATAB
|
|
pc_i[26] => opa[26].DATAB
|
|
pc_i[27] => opa[27].DATAB
|
|
pc_i[28] => opa[28].DATAB
|
|
pc_i[29] => opa[29].DATAB
|
|
pc_i[30] => opa[30].DATAB
|
|
pc_i[31] => opa[31].DATAB
|
|
imm_i[0] => opb[0].DATAB
|
|
imm_i[1] => opb[1].DATAB
|
|
imm_i[2] => opb[2].DATAB
|
|
imm_i[3] => opb[3].DATAB
|
|
imm_i[4] => opb[4].DATAB
|
|
imm_i[5] => opb[5].DATAB
|
|
imm_i[6] => opb[6].DATAB
|
|
imm_i[7] => opb[7].DATAB
|
|
imm_i[8] => opb[8].DATAB
|
|
imm_i[9] => opb[9].DATAB
|
|
imm_i[10] => opb[10].DATAB
|
|
imm_i[11] => opb[11].DATAB
|
|
imm_i[12] => opb[12].DATAB
|
|
imm_i[13] => opb[13].DATAB
|
|
imm_i[14] => opb[14].DATAB
|
|
imm_i[15] => opb[15].DATAB
|
|
imm_i[16] => opb[16].DATAB
|
|
imm_i[17] => opb[17].DATAB
|
|
imm_i[18] => opb[18].DATAB
|
|
imm_i[19] => opb[19].DATAB
|
|
imm_i[20] => opb[20].DATAB
|
|
imm_i[21] => opb[21].DATAB
|
|
imm_i[22] => opb[22].DATAB
|
|
imm_i[23] => opb[23].DATAB
|
|
imm_i[24] => opb[24].DATAB
|
|
imm_i[25] => opb[25].DATAB
|
|
imm_i[26] => opb[26].DATAB
|
|
imm_i[27] => opb[27].DATAB
|
|
imm_i[28] => opb[28].DATAB
|
|
imm_i[29] => opb[29].DATAB
|
|
imm_i[30] => opb[30].DATAB
|
|
imm_i[31] => opb[31].DATAB
|
|
cmp_o[0] <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
|
|
cmp_o[1] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[0] <= Mux31.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[1] <= Mux30.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[2] <= Mux29.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[3] <= Mux28.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[4] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[5] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[6] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[7] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[8] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[9] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[10] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[11] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[12] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[13] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[14] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[15] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[16] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[17] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[18] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[19] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[20] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[21] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[22] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[23] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[24] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[25] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[26] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[27] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[28] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[29] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[30] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[31] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[0] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[1] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[2] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[3] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[4] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[5] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[6] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[7] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[8] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[9] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[10] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[11] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[12] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[13] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[14] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[15] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[16] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[17] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[18] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[19] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[20] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[21] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[22] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[23] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[24] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[25] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[26] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[27] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[28] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[29] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[30] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
add_o[31] <= addsub_res.DB_MAX_OUTPUT_PORT_TYPE
|
|
fpu_flags_o[0] <= <GND>
|
|
fpu_flags_o[1] <= <GND>
|
|
fpu_flags_o[2] <= <GND>
|
|
fpu_flags_o[3] <= <GND>
|
|
fpu_flags_o[4] <= <GND>
|
|
idone_o <= idone_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_alu:neorv32_cpu_alu_inst|neorv32_cpu_cp_shifter:neorv32_cpu_cp_shifter_inst
|
|
clk_i => shifter.sreg[0].CLK
|
|
clk_i => shifter.sreg[1].CLK
|
|
clk_i => shifter.sreg[2].CLK
|
|
clk_i => shifter.sreg[3].CLK
|
|
clk_i => shifter.sreg[4].CLK
|
|
clk_i => shifter.sreg[5].CLK
|
|
clk_i => shifter.sreg[6].CLK
|
|
clk_i => shifter.sreg[7].CLK
|
|
clk_i => shifter.sreg[8].CLK
|
|
clk_i => shifter.sreg[9].CLK
|
|
clk_i => shifter.sreg[10].CLK
|
|
clk_i => shifter.sreg[11].CLK
|
|
clk_i => shifter.sreg[12].CLK
|
|
clk_i => shifter.sreg[13].CLK
|
|
clk_i => shifter.sreg[14].CLK
|
|
clk_i => shifter.sreg[15].CLK
|
|
clk_i => shifter.sreg[16].CLK
|
|
clk_i => shifter.sreg[17].CLK
|
|
clk_i => shifter.sreg[18].CLK
|
|
clk_i => shifter.sreg[19].CLK
|
|
clk_i => shifter.sreg[20].CLK
|
|
clk_i => shifter.sreg[21].CLK
|
|
clk_i => shifter.sreg[22].CLK
|
|
clk_i => shifter.sreg[23].CLK
|
|
clk_i => shifter.sreg[24].CLK
|
|
clk_i => shifter.sreg[25].CLK
|
|
clk_i => shifter.sreg[26].CLK
|
|
clk_i => shifter.sreg[27].CLK
|
|
clk_i => shifter.sreg[28].CLK
|
|
clk_i => shifter.sreg[29].CLK
|
|
clk_i => shifter.sreg[30].CLK
|
|
clk_i => shifter.sreg[31].CLK
|
|
clk_i => shifter.cnt[0].CLK
|
|
clk_i => shifter.cnt[1].CLK
|
|
clk_i => shifter.cnt[2].CLK
|
|
clk_i => shifter.cnt[3].CLK
|
|
clk_i => shifter.cnt[4].CLK
|
|
clk_i => shifter.busy_ff.CLK
|
|
clk_i => shifter.busy.CLK
|
|
rstn_i => shifter.sreg[0].ACLR
|
|
rstn_i => shifter.sreg[1].ACLR
|
|
rstn_i => shifter.sreg[2].ACLR
|
|
rstn_i => shifter.sreg[3].ACLR
|
|
rstn_i => shifter.sreg[4].ACLR
|
|
rstn_i => shifter.sreg[5].ACLR
|
|
rstn_i => shifter.sreg[6].ACLR
|
|
rstn_i => shifter.sreg[7].ACLR
|
|
rstn_i => shifter.sreg[8].ACLR
|
|
rstn_i => shifter.sreg[9].ACLR
|
|
rstn_i => shifter.sreg[10].ACLR
|
|
rstn_i => shifter.sreg[11].ACLR
|
|
rstn_i => shifter.sreg[12].ACLR
|
|
rstn_i => shifter.sreg[13].ACLR
|
|
rstn_i => shifter.sreg[14].ACLR
|
|
rstn_i => shifter.sreg[15].ACLR
|
|
rstn_i => shifter.sreg[16].ACLR
|
|
rstn_i => shifter.sreg[17].ACLR
|
|
rstn_i => shifter.sreg[18].ACLR
|
|
rstn_i => shifter.sreg[19].ACLR
|
|
rstn_i => shifter.sreg[20].ACLR
|
|
rstn_i => shifter.sreg[21].ACLR
|
|
rstn_i => shifter.sreg[22].ACLR
|
|
rstn_i => shifter.sreg[23].ACLR
|
|
rstn_i => shifter.sreg[24].ACLR
|
|
rstn_i => shifter.sreg[25].ACLR
|
|
rstn_i => shifter.sreg[26].ACLR
|
|
rstn_i => shifter.sreg[27].ACLR
|
|
rstn_i => shifter.sreg[28].ACLR
|
|
rstn_i => shifter.sreg[29].ACLR
|
|
rstn_i => shifter.sreg[30].ACLR
|
|
rstn_i => shifter.sreg[31].ACLR
|
|
rstn_i => shifter.cnt[0].ACLR
|
|
rstn_i => shifter.cnt[1].ACLR
|
|
rstn_i => shifter.cnt[2].ACLR
|
|
rstn_i => shifter.cnt[3].ACLR
|
|
rstn_i => shifter.cnt[4].ACLR
|
|
rstn_i => shifter.busy_ff.ACLR
|
|
rstn_i => shifter.busy.ACLR
|
|
ctrl_i[0] => ~NO_FANOUT~
|
|
ctrl_i[1] => ~NO_FANOUT~
|
|
ctrl_i[2] => ~NO_FANOUT~
|
|
ctrl_i[3] => ~NO_FANOUT~
|
|
ctrl_i[4] => ~NO_FANOUT~
|
|
ctrl_i[5] => ~NO_FANOUT~
|
|
ctrl_i[6] => ~NO_FANOUT~
|
|
ctrl_i[7] => ~NO_FANOUT~
|
|
ctrl_i[8] => ~NO_FANOUT~
|
|
ctrl_i[9] => ~NO_FANOUT~
|
|
ctrl_i[10] => ~NO_FANOUT~
|
|
ctrl_i[11] => ~NO_FANOUT~
|
|
ctrl_i[12] => ~NO_FANOUT~
|
|
ctrl_i[13] => ~NO_FANOUT~
|
|
ctrl_i[14] => ~NO_FANOUT~
|
|
ctrl_i[15] => ~NO_FANOUT~
|
|
ctrl_i[16] => ~NO_FANOUT~
|
|
ctrl_i[17] => ~NO_FANOUT~
|
|
ctrl_i[18] => ~NO_FANOUT~
|
|
ctrl_i[19] => ~NO_FANOUT~
|
|
ctrl_i[20] => ~NO_FANOUT~
|
|
ctrl_i[21] => ~NO_FANOUT~
|
|
ctrl_i[22] => ~NO_FANOUT~
|
|
ctrl_i[23] => ~NO_FANOUT~
|
|
ctrl_i[24] => ~NO_FANOUT~
|
|
ctrl_i[25] => ~NO_FANOUT~
|
|
ctrl_i[26] => ~NO_FANOUT~
|
|
ctrl_i[27] => ~NO_FANOUT~
|
|
ctrl_i[28] => ~NO_FANOUT~
|
|
ctrl_i[29] => ~NO_FANOUT~
|
|
ctrl_i[30] => ~NO_FANOUT~
|
|
ctrl_i[31] => ~NO_FANOUT~
|
|
ctrl_i[32] => ~NO_FANOUT~
|
|
ctrl_i[33] => ~NO_FANOUT~
|
|
ctrl_i[34] => ~NO_FANOUT~
|
|
ctrl_i[35] => ~NO_FANOUT~
|
|
ctrl_i[36] => ~NO_FANOUT~
|
|
ctrl_i[37] => ~NO_FANOUT~
|
|
ctrl_i[38] => ~NO_FANOUT~
|
|
ctrl_i[39] => ~NO_FANOUT~
|
|
ctrl_i[40] => ~NO_FANOUT~
|
|
ctrl_i[41] => ~NO_FANOUT~
|
|
ctrl_i[42] => ~NO_FANOUT~
|
|
ctrl_i[43] => ~NO_FANOUT~
|
|
ctrl_i[44] => ~NO_FANOUT~
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[45] => shifter.OUTPUTSELECT
|
|
ctrl_i[46] => ~NO_FANOUT~
|
|
ctrl_i[47] => ~NO_FANOUT~
|
|
ctrl_i[48] => ~NO_FANOUT~
|
|
ctrl_i[49] => ~NO_FANOUT~
|
|
ctrl_i[50] => ~NO_FANOUT~
|
|
ctrl_i[51] => ~NO_FANOUT~
|
|
ctrl_i[52] => ~NO_FANOUT~
|
|
ctrl_i[53] => ~NO_FANOUT~
|
|
ctrl_i[54] => ~NO_FANOUT~
|
|
ctrl_i[55] => ~NO_FANOUT~
|
|
ctrl_i[56] => sreg.IN1
|
|
ctrl_i[57] => ~NO_FANOUT~
|
|
ctrl_i[58] => ~NO_FANOUT~
|
|
ctrl_i[59] => ~NO_FANOUT~
|
|
ctrl_i[60] => ~NO_FANOUT~
|
|
ctrl_i[61] => ~NO_FANOUT~
|
|
ctrl_i[62] => ~NO_FANOUT~
|
|
ctrl_i[63] => ~NO_FANOUT~
|
|
ctrl_i[64] => ~NO_FANOUT~
|
|
ctrl_i[65] => ~NO_FANOUT~
|
|
ctrl_i[66] => ~NO_FANOUT~
|
|
ctrl_i[67] => serial_shifter_core.IN1
|
|
ctrl_i[68] => ~NO_FANOUT~
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
start_i => shifter.OUTPUTSELECT
|
|
rs1_i[0] => shifter.DATAB
|
|
rs1_i[1] => shifter.DATAB
|
|
rs1_i[2] => shifter.DATAB
|
|
rs1_i[3] => shifter.DATAB
|
|
rs1_i[4] => shifter.DATAB
|
|
rs1_i[5] => shifter.DATAB
|
|
rs1_i[6] => shifter.DATAB
|
|
rs1_i[7] => shifter.DATAB
|
|
rs1_i[8] => shifter.DATAB
|
|
rs1_i[9] => shifter.DATAB
|
|
rs1_i[10] => shifter.DATAB
|
|
rs1_i[11] => shifter.DATAB
|
|
rs1_i[12] => shifter.DATAB
|
|
rs1_i[13] => shifter.DATAB
|
|
rs1_i[14] => shifter.DATAB
|
|
rs1_i[15] => shifter.DATAB
|
|
rs1_i[16] => shifter.DATAB
|
|
rs1_i[17] => shifter.DATAB
|
|
rs1_i[18] => shifter.DATAB
|
|
rs1_i[19] => shifter.DATAB
|
|
rs1_i[20] => shifter.DATAB
|
|
rs1_i[21] => shifter.DATAB
|
|
rs1_i[22] => shifter.DATAB
|
|
rs1_i[23] => shifter.DATAB
|
|
rs1_i[24] => shifter.DATAB
|
|
rs1_i[25] => shifter.DATAB
|
|
rs1_i[26] => shifter.DATAB
|
|
rs1_i[27] => shifter.DATAB
|
|
rs1_i[28] => shifter.DATAB
|
|
rs1_i[29] => shifter.DATAB
|
|
rs1_i[30] => shifter.DATAB
|
|
rs1_i[31] => shifter.DATAB
|
|
shamt_i[0] => shifter.DATAB
|
|
shamt_i[1] => shifter.DATAB
|
|
shamt_i[2] => shifter.DATAB
|
|
shamt_i[3] => shifter.DATAB
|
|
shamt_i[4] => shifter.DATAB
|
|
res_o[0] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[1] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[2] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[3] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[4] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[5] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[6] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[7] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[8] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[9] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[10] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[11] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[12] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[13] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[14] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[15] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[16] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[17] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[18] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[19] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[20] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[21] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[22] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[23] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[24] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[25] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[26] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[27] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[28] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[29] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[30] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[31] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
valid_o <= valid_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_alu:neorv32_cpu_alu_inst|neorv32_cpu_cp_muldiv:\neorv32_cpu_cp_muldiv_inst_true:neorv32_cpu_cp_muldiv_inst
|
|
clk_i => div.quotient[0].CLK
|
|
clk_i => div.quotient[1].CLK
|
|
clk_i => div.quotient[2].CLK
|
|
clk_i => div.quotient[3].CLK
|
|
clk_i => div.quotient[4].CLK
|
|
clk_i => div.quotient[5].CLK
|
|
clk_i => div.quotient[6].CLK
|
|
clk_i => div.quotient[7].CLK
|
|
clk_i => div.quotient[8].CLK
|
|
clk_i => div.quotient[9].CLK
|
|
clk_i => div.quotient[10].CLK
|
|
clk_i => div.quotient[11].CLK
|
|
clk_i => div.quotient[12].CLK
|
|
clk_i => div.quotient[13].CLK
|
|
clk_i => div.quotient[14].CLK
|
|
clk_i => div.quotient[15].CLK
|
|
clk_i => div.quotient[16].CLK
|
|
clk_i => div.quotient[17].CLK
|
|
clk_i => div.quotient[18].CLK
|
|
clk_i => div.quotient[19].CLK
|
|
clk_i => div.quotient[20].CLK
|
|
clk_i => div.quotient[21].CLK
|
|
clk_i => div.quotient[22].CLK
|
|
clk_i => div.quotient[23].CLK
|
|
clk_i => div.quotient[24].CLK
|
|
clk_i => div.quotient[25].CLK
|
|
clk_i => div.quotient[26].CLK
|
|
clk_i => div.quotient[27].CLK
|
|
clk_i => div.quotient[28].CLK
|
|
clk_i => div.quotient[29].CLK
|
|
clk_i => div.quotient[30].CLK
|
|
clk_i => div.quotient[31].CLK
|
|
clk_i => div.remainder[0].CLK
|
|
clk_i => div.remainder[1].CLK
|
|
clk_i => div.remainder[2].CLK
|
|
clk_i => div.remainder[3].CLK
|
|
clk_i => div.remainder[4].CLK
|
|
clk_i => div.remainder[5].CLK
|
|
clk_i => div.remainder[6].CLK
|
|
clk_i => div.remainder[7].CLK
|
|
clk_i => div.remainder[8].CLK
|
|
clk_i => div.remainder[9].CLK
|
|
clk_i => div.remainder[10].CLK
|
|
clk_i => div.remainder[11].CLK
|
|
clk_i => div.remainder[12].CLK
|
|
clk_i => div.remainder[13].CLK
|
|
clk_i => div.remainder[14].CLK
|
|
clk_i => div.remainder[15].CLK
|
|
clk_i => div.remainder[16].CLK
|
|
clk_i => div.remainder[17].CLK
|
|
clk_i => div.remainder[18].CLK
|
|
clk_i => div.remainder[19].CLK
|
|
clk_i => div.remainder[20].CLK
|
|
clk_i => div.remainder[21].CLK
|
|
clk_i => div.remainder[22].CLK
|
|
clk_i => div.remainder[23].CLK
|
|
clk_i => div.remainder[24].CLK
|
|
clk_i => div.remainder[25].CLK
|
|
clk_i => div.remainder[26].CLK
|
|
clk_i => div.remainder[27].CLK
|
|
clk_i => div.remainder[28].CLK
|
|
clk_i => div.remainder[29].CLK
|
|
clk_i => div.remainder[30].CLK
|
|
clk_i => div.remainder[31].CLK
|
|
clk_i => mul.prod[0].CLK
|
|
clk_i => mul.prod[1].CLK
|
|
clk_i => mul.prod[2].CLK
|
|
clk_i => mul.prod[3].CLK
|
|
clk_i => mul.prod[4].CLK
|
|
clk_i => mul.prod[5].CLK
|
|
clk_i => mul.prod[6].CLK
|
|
clk_i => mul.prod[7].CLK
|
|
clk_i => mul.prod[8].CLK
|
|
clk_i => mul.prod[9].CLK
|
|
clk_i => mul.prod[10].CLK
|
|
clk_i => mul.prod[11].CLK
|
|
clk_i => mul.prod[12].CLK
|
|
clk_i => mul.prod[13].CLK
|
|
clk_i => mul.prod[14].CLK
|
|
clk_i => mul.prod[15].CLK
|
|
clk_i => mul.prod[16].CLK
|
|
clk_i => mul.prod[17].CLK
|
|
clk_i => mul.prod[18].CLK
|
|
clk_i => mul.prod[19].CLK
|
|
clk_i => mul.prod[20].CLK
|
|
clk_i => mul.prod[21].CLK
|
|
clk_i => mul.prod[22].CLK
|
|
clk_i => mul.prod[23].CLK
|
|
clk_i => mul.prod[24].CLK
|
|
clk_i => mul.prod[25].CLK
|
|
clk_i => mul.prod[26].CLK
|
|
clk_i => mul.prod[27].CLK
|
|
clk_i => mul.prod[28].CLK
|
|
clk_i => mul.prod[29].CLK
|
|
clk_i => mul.prod[30].CLK
|
|
clk_i => mul.prod[31].CLK
|
|
clk_i => mul.prod[32].CLK
|
|
clk_i => mul.prod[33].CLK
|
|
clk_i => mul.prod[34].CLK
|
|
clk_i => mul.prod[35].CLK
|
|
clk_i => mul.prod[36].CLK
|
|
clk_i => mul.prod[37].CLK
|
|
clk_i => mul.prod[38].CLK
|
|
clk_i => mul.prod[39].CLK
|
|
clk_i => mul.prod[40].CLK
|
|
clk_i => mul.prod[41].CLK
|
|
clk_i => mul.prod[42].CLK
|
|
clk_i => mul.prod[43].CLK
|
|
clk_i => mul.prod[44].CLK
|
|
clk_i => mul.prod[45].CLK
|
|
clk_i => mul.prod[46].CLK
|
|
clk_i => mul.prod[47].CLK
|
|
clk_i => mul.prod[48].CLK
|
|
clk_i => mul.prod[49].CLK
|
|
clk_i => mul.prod[50].CLK
|
|
clk_i => mul.prod[51].CLK
|
|
clk_i => mul.prod[52].CLK
|
|
clk_i => mul.prod[53].CLK
|
|
clk_i => mul.prod[54].CLK
|
|
clk_i => mul.prod[55].CLK
|
|
clk_i => mul.prod[56].CLK
|
|
clk_i => mul.prod[57].CLK
|
|
clk_i => mul.prod[58].CLK
|
|
clk_i => mul.prod[59].CLK
|
|
clk_i => mul.prod[60].CLK
|
|
clk_i => mul.prod[61].CLK
|
|
clk_i => mul.prod[62].CLK
|
|
clk_i => mul.prod[63].CLK
|
|
clk_i => div.sign_mod.CLK
|
|
clk_i => ctrl.rs2_abs[0].CLK
|
|
clk_i => ctrl.rs2_abs[1].CLK
|
|
clk_i => ctrl.rs2_abs[2].CLK
|
|
clk_i => ctrl.rs2_abs[3].CLK
|
|
clk_i => ctrl.rs2_abs[4].CLK
|
|
clk_i => ctrl.rs2_abs[5].CLK
|
|
clk_i => ctrl.rs2_abs[6].CLK
|
|
clk_i => ctrl.rs2_abs[7].CLK
|
|
clk_i => ctrl.rs2_abs[8].CLK
|
|
clk_i => ctrl.rs2_abs[9].CLK
|
|
clk_i => ctrl.rs2_abs[10].CLK
|
|
clk_i => ctrl.rs2_abs[11].CLK
|
|
clk_i => ctrl.rs2_abs[12].CLK
|
|
clk_i => ctrl.rs2_abs[13].CLK
|
|
clk_i => ctrl.rs2_abs[14].CLK
|
|
clk_i => ctrl.rs2_abs[15].CLK
|
|
clk_i => ctrl.rs2_abs[16].CLK
|
|
clk_i => ctrl.rs2_abs[17].CLK
|
|
clk_i => ctrl.rs2_abs[18].CLK
|
|
clk_i => ctrl.rs2_abs[19].CLK
|
|
clk_i => ctrl.rs2_abs[20].CLK
|
|
clk_i => ctrl.rs2_abs[21].CLK
|
|
clk_i => ctrl.rs2_abs[22].CLK
|
|
clk_i => ctrl.rs2_abs[23].CLK
|
|
clk_i => ctrl.rs2_abs[24].CLK
|
|
clk_i => ctrl.rs2_abs[25].CLK
|
|
clk_i => ctrl.rs2_abs[26].CLK
|
|
clk_i => ctrl.rs2_abs[27].CLK
|
|
clk_i => ctrl.rs2_abs[28].CLK
|
|
clk_i => ctrl.rs2_abs[29].CLK
|
|
clk_i => ctrl.rs2_abs[30].CLK
|
|
clk_i => ctrl.rs2_abs[31].CLK
|
|
clk_i => ctrl.out_en.CLK
|
|
clk_i => ctrl.cp_op_ff[0].CLK
|
|
clk_i => ctrl.cp_op_ff[1].CLK
|
|
clk_i => ctrl.cp_op_ff[2].CLK
|
|
clk_i => ctrl.cnt[0].CLK
|
|
clk_i => ctrl.cnt[1].CLK
|
|
clk_i => ctrl.cnt[2].CLK
|
|
clk_i => ctrl.cnt[3].CLK
|
|
clk_i => ctrl.cnt[4].CLK
|
|
clk_i => ctrl.state~1.DATAIN
|
|
rstn_i => div.sign_mod.ACLR
|
|
rstn_i => ctrl.rs2_abs[0].ACLR
|
|
rstn_i => ctrl.rs2_abs[1].ACLR
|
|
rstn_i => ctrl.rs2_abs[2].ACLR
|
|
rstn_i => ctrl.rs2_abs[3].ACLR
|
|
rstn_i => ctrl.rs2_abs[4].ACLR
|
|
rstn_i => ctrl.rs2_abs[5].ACLR
|
|
rstn_i => ctrl.rs2_abs[6].ACLR
|
|
rstn_i => ctrl.rs2_abs[7].ACLR
|
|
rstn_i => ctrl.rs2_abs[8].ACLR
|
|
rstn_i => ctrl.rs2_abs[9].ACLR
|
|
rstn_i => ctrl.rs2_abs[10].ACLR
|
|
rstn_i => ctrl.rs2_abs[11].ACLR
|
|
rstn_i => ctrl.rs2_abs[12].ACLR
|
|
rstn_i => ctrl.rs2_abs[13].ACLR
|
|
rstn_i => ctrl.rs2_abs[14].ACLR
|
|
rstn_i => ctrl.rs2_abs[15].ACLR
|
|
rstn_i => ctrl.rs2_abs[16].ACLR
|
|
rstn_i => ctrl.rs2_abs[17].ACLR
|
|
rstn_i => ctrl.rs2_abs[18].ACLR
|
|
rstn_i => ctrl.rs2_abs[19].ACLR
|
|
rstn_i => ctrl.rs2_abs[20].ACLR
|
|
rstn_i => ctrl.rs2_abs[21].ACLR
|
|
rstn_i => ctrl.rs2_abs[22].ACLR
|
|
rstn_i => ctrl.rs2_abs[23].ACLR
|
|
rstn_i => ctrl.rs2_abs[24].ACLR
|
|
rstn_i => ctrl.rs2_abs[25].ACLR
|
|
rstn_i => ctrl.rs2_abs[26].ACLR
|
|
rstn_i => ctrl.rs2_abs[27].ACLR
|
|
rstn_i => ctrl.rs2_abs[28].ACLR
|
|
rstn_i => ctrl.rs2_abs[29].ACLR
|
|
rstn_i => ctrl.rs2_abs[30].ACLR
|
|
rstn_i => ctrl.rs2_abs[31].ACLR
|
|
rstn_i => ctrl.out_en.ACLR
|
|
rstn_i => ctrl.cp_op_ff[0].ACLR
|
|
rstn_i => ctrl.cp_op_ff[1].ACLR
|
|
rstn_i => ctrl.cp_op_ff[2].ACLR
|
|
rstn_i => ctrl.cnt[0].ACLR
|
|
rstn_i => ctrl.cnt[1].ACLR
|
|
rstn_i => ctrl.cnt[2].ACLR
|
|
rstn_i => ctrl.cnt[3].ACLR
|
|
rstn_i => ctrl.cnt[4].ACLR
|
|
rstn_i => ctrl.state~3.DATAIN
|
|
ctrl_i[0] => ~NO_FANOUT~
|
|
ctrl_i[1] => ~NO_FANOUT~
|
|
ctrl_i[2] => ~NO_FANOUT~
|
|
ctrl_i[3] => ~NO_FANOUT~
|
|
ctrl_i[4] => ~NO_FANOUT~
|
|
ctrl_i[5] => ~NO_FANOUT~
|
|
ctrl_i[6] => ~NO_FANOUT~
|
|
ctrl_i[7] => ~NO_FANOUT~
|
|
ctrl_i[8] => ~NO_FANOUT~
|
|
ctrl_i[9] => ~NO_FANOUT~
|
|
ctrl_i[10] => ~NO_FANOUT~
|
|
ctrl_i[11] => ~NO_FANOUT~
|
|
ctrl_i[12] => ~NO_FANOUT~
|
|
ctrl_i[13] => ~NO_FANOUT~
|
|
ctrl_i[14] => ~NO_FANOUT~
|
|
ctrl_i[15] => ~NO_FANOUT~
|
|
ctrl_i[16] => ~NO_FANOUT~
|
|
ctrl_i[17] => ~NO_FANOUT~
|
|
ctrl_i[18] => ~NO_FANOUT~
|
|
ctrl_i[19] => ~NO_FANOUT~
|
|
ctrl_i[20] => ~NO_FANOUT~
|
|
ctrl_i[21] => ~NO_FANOUT~
|
|
ctrl_i[22] => ~NO_FANOUT~
|
|
ctrl_i[23] => ~NO_FANOUT~
|
|
ctrl_i[24] => ~NO_FANOUT~
|
|
ctrl_i[25] => ~NO_FANOUT~
|
|
ctrl_i[26] => ~NO_FANOUT~
|
|
ctrl_i[27] => ~NO_FANOUT~
|
|
ctrl_i[28] => ~NO_FANOUT~
|
|
ctrl_i[29] => ~NO_FANOUT~
|
|
ctrl_i[30] => ~NO_FANOUT~
|
|
ctrl_i[31] => ~NO_FANOUT~
|
|
ctrl_i[32] => ~NO_FANOUT~
|
|
ctrl_i[33] => ~NO_FANOUT~
|
|
ctrl_i[34] => ~NO_FANOUT~
|
|
ctrl_i[35] => ~NO_FANOUT~
|
|
ctrl_i[36] => ~NO_FANOUT~
|
|
ctrl_i[37] => ~NO_FANOUT~
|
|
ctrl_i[38] => ~NO_FANOUT~
|
|
ctrl_i[39] => ~NO_FANOUT~
|
|
ctrl_i[40] => ~NO_FANOUT~
|
|
ctrl_i[41] => ~NO_FANOUT~
|
|
ctrl_i[42] => ~NO_FANOUT~
|
|
ctrl_i[43] => Equal0.IN1
|
|
ctrl_i[43] => Equal1.IN0
|
|
ctrl_i[43] => Equal2.IN2
|
|
ctrl_i[43] => Equal3.IN1
|
|
ctrl_i[43] => Equal4.IN0
|
|
ctrl_i[43] => Equal5.IN1
|
|
ctrl_i[43] => Equal6.IN2
|
|
ctrl_i[43] => ctrl.cp_op_ff[0].DATAIN
|
|
ctrl_i[44] => Equal0.IN0
|
|
ctrl_i[44] => Equal1.IN1
|
|
ctrl_i[44] => Equal2.IN1
|
|
ctrl_i[44] => Equal3.IN2
|
|
ctrl_i[44] => Equal4.IN2
|
|
ctrl_i[44] => Equal5.IN0
|
|
ctrl_i[44] => Equal6.IN0
|
|
ctrl_i[44] => ctrl.cp_op_ff[1].DATAIN
|
|
ctrl_i[45] => div.start.IN0
|
|
ctrl_i[45] => Equal2.IN0
|
|
ctrl_i[45] => Equal3.IN0
|
|
ctrl_i[45] => Equal4.IN1
|
|
ctrl_i[45] => mul.start.IN0
|
|
ctrl_i[45] => Equal5.IN2
|
|
ctrl_i[45] => Equal6.IN1
|
|
ctrl_i[45] => ctrl.cp_op_ff[2].DATAIN
|
|
ctrl_i[46] => ~NO_FANOUT~
|
|
ctrl_i[47] => ~NO_FANOUT~
|
|
ctrl_i[48] => ~NO_FANOUT~
|
|
ctrl_i[49] => ~NO_FANOUT~
|
|
ctrl_i[50] => ~NO_FANOUT~
|
|
ctrl_i[51] => ~NO_FANOUT~
|
|
ctrl_i[52] => ~NO_FANOUT~
|
|
ctrl_i[53] => ~NO_FANOUT~
|
|
ctrl_i[54] => ~NO_FANOUT~
|
|
ctrl_i[55] => ~NO_FANOUT~
|
|
ctrl_i[56] => ~NO_FANOUT~
|
|
ctrl_i[57] => ~NO_FANOUT~
|
|
ctrl_i[58] => ~NO_FANOUT~
|
|
ctrl_i[59] => ~NO_FANOUT~
|
|
ctrl_i[60] => ~NO_FANOUT~
|
|
ctrl_i[61] => ~NO_FANOUT~
|
|
ctrl_i[62] => ~NO_FANOUT~
|
|
ctrl_i[63] => ~NO_FANOUT~
|
|
ctrl_i[64] => ~NO_FANOUT~
|
|
ctrl_i[65] => ~NO_FANOUT~
|
|
ctrl_i[66] => ~NO_FANOUT~
|
|
ctrl_i[67] => coprocessor_ctrl.IN1
|
|
ctrl_i[68] => ~NO_FANOUT~
|
|
start_i => div.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => ctrl.OUTPUTSELECT
|
|
start_i => mul.start.IN1
|
|
start_i => div.start.IN1
|
|
rs1_i[0] => mul.DATAB
|
|
rs1_i[0] => div.DATAA
|
|
rs1_i[0] => Add4.IN31
|
|
rs1_i[1] => mul.DATAB
|
|
rs1_i[1] => div.DATAA
|
|
rs1_i[1] => Add4.IN30
|
|
rs1_i[2] => mul.DATAB
|
|
rs1_i[2] => div.DATAA
|
|
rs1_i[2] => Add4.IN29
|
|
rs1_i[3] => mul.DATAB
|
|
rs1_i[3] => div.DATAA
|
|
rs1_i[3] => Add4.IN28
|
|
rs1_i[4] => mul.DATAB
|
|
rs1_i[4] => div.DATAA
|
|
rs1_i[4] => Add4.IN27
|
|
rs1_i[5] => mul.DATAB
|
|
rs1_i[5] => div.DATAA
|
|
rs1_i[5] => Add4.IN26
|
|
rs1_i[6] => mul.DATAB
|
|
rs1_i[6] => div.DATAA
|
|
rs1_i[6] => Add4.IN25
|
|
rs1_i[7] => mul.DATAB
|
|
rs1_i[7] => div.DATAA
|
|
rs1_i[7] => Add4.IN24
|
|
rs1_i[8] => mul.DATAB
|
|
rs1_i[8] => div.DATAA
|
|
rs1_i[8] => Add4.IN23
|
|
rs1_i[9] => mul.DATAB
|
|
rs1_i[9] => div.DATAA
|
|
rs1_i[9] => Add4.IN22
|
|
rs1_i[10] => mul.DATAB
|
|
rs1_i[10] => div.DATAA
|
|
rs1_i[10] => Add4.IN21
|
|
rs1_i[11] => mul.DATAB
|
|
rs1_i[11] => div.DATAA
|
|
rs1_i[11] => Add4.IN20
|
|
rs1_i[12] => mul.DATAB
|
|
rs1_i[12] => div.DATAA
|
|
rs1_i[12] => Add4.IN19
|
|
rs1_i[13] => mul.DATAB
|
|
rs1_i[13] => div.DATAA
|
|
rs1_i[13] => Add4.IN18
|
|
rs1_i[14] => mul.DATAB
|
|
rs1_i[14] => div.DATAA
|
|
rs1_i[14] => Add4.IN17
|
|
rs1_i[15] => mul.DATAB
|
|
rs1_i[15] => div.DATAA
|
|
rs1_i[15] => Add4.IN16
|
|
rs1_i[16] => mul.DATAB
|
|
rs1_i[16] => div.DATAA
|
|
rs1_i[16] => Add4.IN15
|
|
rs1_i[17] => mul.DATAB
|
|
rs1_i[17] => div.DATAA
|
|
rs1_i[17] => Add4.IN14
|
|
rs1_i[18] => mul.DATAB
|
|
rs1_i[18] => div.DATAA
|
|
rs1_i[18] => Add4.IN13
|
|
rs1_i[19] => mul.DATAB
|
|
rs1_i[19] => div.DATAA
|
|
rs1_i[19] => Add4.IN12
|
|
rs1_i[20] => mul.DATAB
|
|
rs1_i[20] => div.DATAA
|
|
rs1_i[20] => Add4.IN11
|
|
rs1_i[21] => mul.DATAB
|
|
rs1_i[21] => div.DATAA
|
|
rs1_i[21] => Add4.IN10
|
|
rs1_i[22] => mul.DATAB
|
|
rs1_i[22] => div.DATAA
|
|
rs1_i[22] => Add4.IN9
|
|
rs1_i[23] => mul.DATAB
|
|
rs1_i[23] => div.DATAA
|
|
rs1_i[23] => Add4.IN8
|
|
rs1_i[24] => mul.DATAB
|
|
rs1_i[24] => div.DATAA
|
|
rs1_i[24] => Add4.IN7
|
|
rs1_i[25] => mul.DATAB
|
|
rs1_i[25] => div.DATAA
|
|
rs1_i[25] => Add4.IN6
|
|
rs1_i[26] => mul.DATAB
|
|
rs1_i[26] => div.DATAA
|
|
rs1_i[26] => Add4.IN5
|
|
rs1_i[27] => mul.DATAB
|
|
rs1_i[27] => div.DATAA
|
|
rs1_i[27] => Add4.IN4
|
|
rs1_i[28] => mul.DATAB
|
|
rs1_i[28] => div.DATAA
|
|
rs1_i[28] => Add4.IN3
|
|
rs1_i[29] => mul.DATAB
|
|
rs1_i[29] => div.DATAA
|
|
rs1_i[29] => Add4.IN2
|
|
rs1_i[30] => mul.DATAB
|
|
rs1_i[30] => div.DATAA
|
|
rs1_i[30] => Add4.IN1
|
|
rs1_i[31] => sign_mod.IN0
|
|
rs1_i[31] => div.DATAB
|
|
rs1_i[31] => mul.DATAB
|
|
rs1_i[31] => divider_core.IN1
|
|
rs1_i[31] => div.DATAA
|
|
rs1_i[31] => Add4.IN0
|
|
rs2_i[0] => tmp_v.IN1
|
|
rs2_i[0] => ctrl.DATAA
|
|
rs2_i[0] => Add3.IN33
|
|
rs2_i[0] => Add2.IN32
|
|
rs2_i[0] => Add0.IN31
|
|
rs2_i[1] => tmp_v.IN1
|
|
rs2_i[1] => ctrl.DATAA
|
|
rs2_i[1] => Add3.IN32
|
|
rs2_i[1] => Add2.IN31
|
|
rs2_i[1] => Add0.IN30
|
|
rs2_i[2] => tmp_v.IN1
|
|
rs2_i[2] => ctrl.DATAA
|
|
rs2_i[2] => Add3.IN31
|
|
rs2_i[2] => Add2.IN30
|
|
rs2_i[2] => Add0.IN29
|
|
rs2_i[3] => tmp_v.IN1
|
|
rs2_i[3] => ctrl.DATAA
|
|
rs2_i[3] => Add3.IN30
|
|
rs2_i[3] => Add2.IN29
|
|
rs2_i[3] => Add0.IN28
|
|
rs2_i[4] => tmp_v.IN1
|
|
rs2_i[4] => ctrl.DATAA
|
|
rs2_i[4] => Add3.IN29
|
|
rs2_i[4] => Add2.IN28
|
|
rs2_i[4] => Add0.IN27
|
|
rs2_i[5] => tmp_v.IN1
|
|
rs2_i[5] => ctrl.DATAA
|
|
rs2_i[5] => Add3.IN28
|
|
rs2_i[5] => Add2.IN27
|
|
rs2_i[5] => Add0.IN26
|
|
rs2_i[6] => tmp_v.IN1
|
|
rs2_i[6] => ctrl.DATAA
|
|
rs2_i[6] => Add3.IN27
|
|
rs2_i[6] => Add2.IN26
|
|
rs2_i[6] => Add0.IN25
|
|
rs2_i[7] => tmp_v.IN1
|
|
rs2_i[7] => ctrl.DATAA
|
|
rs2_i[7] => Add3.IN26
|
|
rs2_i[7] => Add2.IN25
|
|
rs2_i[7] => Add0.IN24
|
|
rs2_i[8] => tmp_v.IN1
|
|
rs2_i[8] => ctrl.DATAA
|
|
rs2_i[8] => Add3.IN25
|
|
rs2_i[8] => Add2.IN24
|
|
rs2_i[8] => Add0.IN23
|
|
rs2_i[9] => tmp_v.IN1
|
|
rs2_i[9] => ctrl.DATAA
|
|
rs2_i[9] => Add3.IN24
|
|
rs2_i[9] => Add2.IN23
|
|
rs2_i[9] => Add0.IN22
|
|
rs2_i[10] => tmp_v.IN1
|
|
rs2_i[10] => ctrl.DATAA
|
|
rs2_i[10] => Add3.IN23
|
|
rs2_i[10] => Add2.IN22
|
|
rs2_i[10] => Add0.IN21
|
|
rs2_i[11] => tmp_v.IN1
|
|
rs2_i[11] => ctrl.DATAA
|
|
rs2_i[11] => Add3.IN22
|
|
rs2_i[11] => Add2.IN21
|
|
rs2_i[11] => Add0.IN20
|
|
rs2_i[12] => tmp_v.IN1
|
|
rs2_i[12] => ctrl.DATAA
|
|
rs2_i[12] => Add3.IN21
|
|
rs2_i[12] => Add2.IN20
|
|
rs2_i[12] => Add0.IN19
|
|
rs2_i[13] => tmp_v.IN1
|
|
rs2_i[13] => ctrl.DATAA
|
|
rs2_i[13] => Add3.IN20
|
|
rs2_i[13] => Add2.IN19
|
|
rs2_i[13] => Add0.IN18
|
|
rs2_i[14] => tmp_v.IN1
|
|
rs2_i[14] => ctrl.DATAA
|
|
rs2_i[14] => Add3.IN19
|
|
rs2_i[14] => Add2.IN18
|
|
rs2_i[14] => Add0.IN17
|
|
rs2_i[15] => tmp_v.IN1
|
|
rs2_i[15] => ctrl.DATAA
|
|
rs2_i[15] => Add3.IN18
|
|
rs2_i[15] => Add2.IN17
|
|
rs2_i[15] => Add0.IN16
|
|
rs2_i[16] => tmp_v.IN1
|
|
rs2_i[16] => ctrl.DATAA
|
|
rs2_i[16] => Add3.IN17
|
|
rs2_i[16] => Add2.IN16
|
|
rs2_i[16] => Add0.IN15
|
|
rs2_i[17] => tmp_v.IN1
|
|
rs2_i[17] => ctrl.DATAA
|
|
rs2_i[17] => Add3.IN16
|
|
rs2_i[17] => Add2.IN15
|
|
rs2_i[17] => Add0.IN14
|
|
rs2_i[18] => tmp_v.IN1
|
|
rs2_i[18] => ctrl.DATAA
|
|
rs2_i[18] => Add3.IN15
|
|
rs2_i[18] => Add2.IN14
|
|
rs2_i[18] => Add0.IN13
|
|
rs2_i[19] => tmp_v.IN1
|
|
rs2_i[19] => ctrl.DATAA
|
|
rs2_i[19] => Add3.IN14
|
|
rs2_i[19] => Add2.IN13
|
|
rs2_i[19] => Add0.IN12
|
|
rs2_i[20] => tmp_v.IN1
|
|
rs2_i[20] => ctrl.DATAA
|
|
rs2_i[20] => Add3.IN13
|
|
rs2_i[20] => Add2.IN12
|
|
rs2_i[20] => Add0.IN11
|
|
rs2_i[21] => tmp_v.IN1
|
|
rs2_i[21] => ctrl.DATAA
|
|
rs2_i[21] => Add3.IN12
|
|
rs2_i[21] => Add2.IN11
|
|
rs2_i[21] => Add0.IN10
|
|
rs2_i[22] => tmp_v.IN1
|
|
rs2_i[22] => ctrl.DATAA
|
|
rs2_i[22] => Add3.IN11
|
|
rs2_i[22] => Add2.IN10
|
|
rs2_i[22] => Add0.IN9
|
|
rs2_i[23] => tmp_v.IN1
|
|
rs2_i[23] => ctrl.DATAA
|
|
rs2_i[23] => Add3.IN10
|
|
rs2_i[23] => Add2.IN9
|
|
rs2_i[23] => Add0.IN8
|
|
rs2_i[24] => tmp_v.IN1
|
|
rs2_i[24] => ctrl.DATAA
|
|
rs2_i[24] => Add3.IN9
|
|
rs2_i[24] => Add2.IN8
|
|
rs2_i[24] => Add0.IN7
|
|
rs2_i[25] => tmp_v.IN1
|
|
rs2_i[25] => ctrl.DATAA
|
|
rs2_i[25] => Add3.IN8
|
|
rs2_i[25] => Add2.IN7
|
|
rs2_i[25] => Add0.IN6
|
|
rs2_i[26] => tmp_v.IN1
|
|
rs2_i[26] => ctrl.DATAA
|
|
rs2_i[26] => Add3.IN7
|
|
rs2_i[26] => Add2.IN6
|
|
rs2_i[26] => Add0.IN5
|
|
rs2_i[27] => tmp_v.IN1
|
|
rs2_i[27] => ctrl.DATAA
|
|
rs2_i[27] => Add3.IN6
|
|
rs2_i[27] => Add2.IN5
|
|
rs2_i[27] => Add0.IN4
|
|
rs2_i[28] => tmp_v.IN1
|
|
rs2_i[28] => ctrl.DATAA
|
|
rs2_i[28] => Add3.IN5
|
|
rs2_i[28] => Add2.IN4
|
|
rs2_i[28] => Add0.IN3
|
|
rs2_i[29] => tmp_v.IN1
|
|
rs2_i[29] => ctrl.DATAA
|
|
rs2_i[29] => Add3.IN4
|
|
rs2_i[29] => Add2.IN3
|
|
rs2_i[29] => Add0.IN2
|
|
rs2_i[30] => tmp_v.IN0
|
|
rs2_i[30] => ctrl.DATAA
|
|
rs2_i[30] => Add3.IN3
|
|
rs2_i[30] => Add2.IN2
|
|
rs2_i[30] => Add0.IN1
|
|
rs2_i[31] => sign_mod.IN1
|
|
rs2_i[31] => tmp_v.IN1
|
|
rs2_i[31] => coprocessor_ctrl.IN1
|
|
rs2_i[31] => ctrl.DATAA
|
|
rs2_i[31] => Add3.IN2
|
|
rs2_i[31] => Add2.IN1
|
|
rs2_i[31] => Add0.IN0
|
|
res_o[0] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[1] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[2] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[3] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[4] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[5] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[6] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[7] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[8] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[9] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[10] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[11] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[12] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[13] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[14] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[15] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[16] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[17] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[18] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[19] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[20] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[21] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[22] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[23] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[24] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[25] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[26] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[27] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[28] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[29] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[30] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
res_o[31] <= res_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
valid_o <= valid_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_cpu:neorv32_cpu_inst|neorv32_cpu_bus:neorv32_cpu_bus_inst
|
|
clk_i => arbiter.pmp_w_err.CLK
|
|
clk_i => arbiter.pmp_r_err.CLK
|
|
clk_i => arbiter.err.CLK
|
|
clk_i => arbiter.pend.CLK
|
|
clk_i => rdata_o[0]~reg0.CLK
|
|
clk_i => rdata_o[1]~reg0.CLK
|
|
clk_i => rdata_o[2]~reg0.CLK
|
|
clk_i => rdata_o[3]~reg0.CLK
|
|
clk_i => rdata_o[4]~reg0.CLK
|
|
clk_i => rdata_o[5]~reg0.CLK
|
|
clk_i => rdata_o[6]~reg0.CLK
|
|
clk_i => rdata_o[7]~reg0.CLK
|
|
clk_i => rdata_o[8]~reg0.CLK
|
|
clk_i => rdata_o[9]~reg0.CLK
|
|
clk_i => rdata_o[10]~reg0.CLK
|
|
clk_i => rdata_o[11]~reg0.CLK
|
|
clk_i => rdata_o[12]~reg0.CLK
|
|
clk_i => rdata_o[13]~reg0.CLK
|
|
clk_i => rdata_o[14]~reg0.CLK
|
|
clk_i => rdata_o[15]~reg0.CLK
|
|
clk_i => rdata_o[16]~reg0.CLK
|
|
clk_i => rdata_o[17]~reg0.CLK
|
|
clk_i => rdata_o[18]~reg0.CLK
|
|
clk_i => rdata_o[19]~reg0.CLK
|
|
clk_i => rdata_o[20]~reg0.CLK
|
|
clk_i => rdata_o[21]~reg0.CLK
|
|
clk_i => rdata_o[22]~reg0.CLK
|
|
clk_i => rdata_o[23]~reg0.CLK
|
|
clk_i => rdata_o[24]~reg0.CLK
|
|
clk_i => rdata_o[25]~reg0.CLK
|
|
clk_i => rdata_o[26]~reg0.CLK
|
|
clk_i => rdata_o[27]~reg0.CLK
|
|
clk_i => rdata_o[28]~reg0.CLK
|
|
clk_i => rdata_o[29]~reg0.CLK
|
|
clk_i => rdata_o[30]~reg0.CLK
|
|
clk_i => rdata_o[31]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[0]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[1]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[2]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[3]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[4]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[5]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[6]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[7]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[8]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[9]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[10]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[11]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[12]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[13]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[14]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[15]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[16]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[17]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[18]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[19]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[20]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[21]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[22]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[23]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[24]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[25]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[26]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[27]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[28]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[29]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[30]~reg0.CLK
|
|
clk_i => d_bus_wdata_o[31]~reg0.CLK
|
|
clk_i => d_bus_ben_o[0]~reg0.CLK
|
|
clk_i => d_bus_ben_o[1]~reg0.CLK
|
|
clk_i => d_bus_ben_o[2]~reg0.CLK
|
|
clk_i => d_bus_ben_o[3]~reg0.CLK
|
|
clk_i => misaligned.CLK
|
|
clk_i => mar[0].CLK
|
|
clk_i => mar[1].CLK
|
|
clk_i => mar[2].CLK
|
|
clk_i => mar[3].CLK
|
|
clk_i => mar[4].CLK
|
|
clk_i => mar[5].CLK
|
|
clk_i => mar[6].CLK
|
|
clk_i => mar[7].CLK
|
|
clk_i => mar[8].CLK
|
|
clk_i => mar[9].CLK
|
|
clk_i => mar[10].CLK
|
|
clk_i => mar[11].CLK
|
|
clk_i => mar[12].CLK
|
|
clk_i => mar[13].CLK
|
|
clk_i => mar[14].CLK
|
|
clk_i => mar[15].CLK
|
|
clk_i => mar[16].CLK
|
|
clk_i => mar[17].CLK
|
|
clk_i => mar[18].CLK
|
|
clk_i => mar[19].CLK
|
|
clk_i => mar[20].CLK
|
|
clk_i => mar[21].CLK
|
|
clk_i => mar[22].CLK
|
|
clk_i => mar[23].CLK
|
|
clk_i => mar[24].CLK
|
|
clk_i => mar[25].CLK
|
|
clk_i => mar[26].CLK
|
|
clk_i => mar[27].CLK
|
|
clk_i => mar[28].CLK
|
|
clk_i => mar[29].CLK
|
|
clk_i => mar[30].CLK
|
|
clk_i => mar[31].CLK
|
|
rstn_i => arbiter.pmp_w_err.ACLR
|
|
rstn_i => arbiter.pmp_r_err.ACLR
|
|
rstn_i => arbiter.err.ACLR
|
|
rstn_i => arbiter.pend.ACLR
|
|
ctrl_i[0] => ~NO_FANOUT~
|
|
ctrl_i[1] => ~NO_FANOUT~
|
|
ctrl_i[2] => ~NO_FANOUT~
|
|
ctrl_i[3] => ~NO_FANOUT~
|
|
ctrl_i[4] => ~NO_FANOUT~
|
|
ctrl_i[5] => ~NO_FANOUT~
|
|
ctrl_i[6] => ~NO_FANOUT~
|
|
ctrl_i[7] => ~NO_FANOUT~
|
|
ctrl_i[8] => ~NO_FANOUT~
|
|
ctrl_i[9] => ~NO_FANOUT~
|
|
ctrl_i[10] => ~NO_FANOUT~
|
|
ctrl_i[11] => ~NO_FANOUT~
|
|
ctrl_i[12] => ~NO_FANOUT~
|
|
ctrl_i[13] => ~NO_FANOUT~
|
|
ctrl_i[14] => ~NO_FANOUT~
|
|
ctrl_i[15] => ~NO_FANOUT~
|
|
ctrl_i[16] => ~NO_FANOUT~
|
|
ctrl_i[17] => ~NO_FANOUT~
|
|
ctrl_i[18] => ~NO_FANOUT~
|
|
ctrl_i[19] => ~NO_FANOUT~
|
|
ctrl_i[20] => ~NO_FANOUT~
|
|
ctrl_i[21] => ~NO_FANOUT~
|
|
ctrl_i[22] => ~NO_FANOUT~
|
|
ctrl_i[23] => ~NO_FANOUT~
|
|
ctrl_i[24] => ~NO_FANOUT~
|
|
ctrl_i[25] => ~NO_FANOUT~
|
|
ctrl_i[26] => ~NO_FANOUT~
|
|
ctrl_i[27] => ~NO_FANOUT~
|
|
ctrl_i[28] => ~NO_FANOUT~
|
|
ctrl_i[29] => ~NO_FANOUT~
|
|
ctrl_i[30] => ~NO_FANOUT~
|
|
ctrl_i[31] => ~NO_FANOUT~
|
|
ctrl_i[32] => ~NO_FANOUT~
|
|
ctrl_i[33] => ~NO_FANOUT~
|
|
ctrl_i[34] => ~NO_FANOUT~
|
|
ctrl_i[35] => ~NO_FANOUT~
|
|
ctrl_i[36] => ~NO_FANOUT~
|
|
ctrl_i[37] => ~NO_FANOUT~
|
|
ctrl_i[38] => arbiter.OUTPUTSELECT
|
|
ctrl_i[38] => d_bus_we_o.IN0
|
|
ctrl_i[38] => d_bus_re_o.IN0
|
|
ctrl_i[39] => mar[31].ENA
|
|
ctrl_i[39] => mar[30].ENA
|
|
ctrl_i[39] => mar[29].ENA
|
|
ctrl_i[39] => mar[28].ENA
|
|
ctrl_i[39] => mar[27].ENA
|
|
ctrl_i[39] => mar[26].ENA
|
|
ctrl_i[39] => mar[25].ENA
|
|
ctrl_i[39] => mar[24].ENA
|
|
ctrl_i[39] => mar[23].ENA
|
|
ctrl_i[39] => mar[22].ENA
|
|
ctrl_i[39] => mar[21].ENA
|
|
ctrl_i[39] => mar[20].ENA
|
|
ctrl_i[39] => mar[19].ENA
|
|
ctrl_i[39] => mar[18].ENA
|
|
ctrl_i[39] => mar[17].ENA
|
|
ctrl_i[39] => mar[16].ENA
|
|
ctrl_i[39] => mar[15].ENA
|
|
ctrl_i[39] => mar[14].ENA
|
|
ctrl_i[39] => mar[13].ENA
|
|
ctrl_i[39] => mar[12].ENA
|
|
ctrl_i[39] => mar[11].ENA
|
|
ctrl_i[39] => mar[10].ENA
|
|
ctrl_i[39] => mar[9].ENA
|
|
ctrl_i[39] => mar[8].ENA
|
|
ctrl_i[39] => mar[7].ENA
|
|
ctrl_i[39] => mar[6].ENA
|
|
ctrl_i[39] => mar[5].ENA
|
|
ctrl_i[39] => mar[4].ENA
|
|
ctrl_i[39] => mar[3].ENA
|
|
ctrl_i[39] => mar[2].ENA
|
|
ctrl_i[39] => mar[1].ENA
|
|
ctrl_i[39] => mar[0].ENA
|
|
ctrl_i[39] => d_bus_ben_o[3]~reg0.ENA
|
|
ctrl_i[39] => d_bus_ben_o[2]~reg0.ENA
|
|
ctrl_i[39] => d_bus_ben_o[1]~reg0.ENA
|
|
ctrl_i[39] => d_bus_ben_o[0]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[31]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[30]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[29]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[28]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[27]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[26]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[25]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[24]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[23]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[22]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[21]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[20]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[19]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[18]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[17]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[16]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[15]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[14]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[13]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[12]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[11]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[10]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[9]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[8]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[7]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[6]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[5]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[4]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[3]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[2]~reg0.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[1]~reg0.ENA
|
|
ctrl_i[39] => misaligned.ENA
|
|
ctrl_i[39] => d_bus_wdata_o[0]~reg0.ENA
|
|
ctrl_i[40] => d_bus_fence_o.DATAIN
|
|
ctrl_i[41] => ~NO_FANOUT~
|
|
ctrl_i[42] => d_bus_priv_o.DATAIN
|
|
ctrl_i[43] => Mux0.IN4
|
|
ctrl_i[43] => Mux1.IN1
|
|
ctrl_i[43] => Mux2.IN1
|
|
ctrl_i[43] => Mux3.IN1
|
|
ctrl_i[43] => Mux4.IN1
|
|
ctrl_i[43] => Mux5.IN1
|
|
ctrl_i[43] => Mux6.IN1
|
|
ctrl_i[43] => Mux7.IN1
|
|
ctrl_i[43] => Mux8.IN1
|
|
ctrl_i[43] => Mux9.IN1
|
|
ctrl_i[43] => Mux10.IN1
|
|
ctrl_i[43] => Mux11.IN1
|
|
ctrl_i[43] => Mux12.IN1
|
|
ctrl_i[43] => Mux13.IN1
|
|
ctrl_i[43] => Mux14.IN1
|
|
ctrl_i[43] => Mux15.IN1
|
|
ctrl_i[43] => Mux16.IN1
|
|
ctrl_i[43] => Mux17.IN4
|
|
ctrl_i[43] => Mux18.IN4
|
|
ctrl_i[43] => Mux19.IN5
|
|
ctrl_i[43] => Mux20.IN5
|
|
ctrl_i[43] => Mux30.IN3
|
|
ctrl_i[43] => Mux31.IN3
|
|
ctrl_i[43] => Mux32.IN3
|
|
ctrl_i[43] => Mux33.IN3
|
|
ctrl_i[43] => Mux34.IN3
|
|
ctrl_i[43] => Mux35.IN3
|
|
ctrl_i[43] => Mux36.IN3
|
|
ctrl_i[43] => Mux37.IN3
|
|
ctrl_i[43] => Mux38.IN3
|
|
ctrl_i[43] => Mux39.IN3
|
|
ctrl_i[43] => Mux40.IN3
|
|
ctrl_i[43] => Mux41.IN3
|
|
ctrl_i[43] => Mux42.IN3
|
|
ctrl_i[43] => Mux43.IN3
|
|
ctrl_i[43] => Mux44.IN3
|
|
ctrl_i[43] => Mux45.IN3
|
|
ctrl_i[43] => Mux46.IN3
|
|
ctrl_i[43] => Mux47.IN3
|
|
ctrl_i[43] => Mux48.IN3
|
|
ctrl_i[43] => Mux49.IN3
|
|
ctrl_i[43] => Mux50.IN3
|
|
ctrl_i[43] => Mux51.IN3
|
|
ctrl_i[43] => Mux52.IN3
|
|
ctrl_i[43] => Mux53.IN3
|
|
ctrl_i[43] => Mux54.IN3
|
|
ctrl_i[43] => Mux55.IN3
|
|
ctrl_i[43] => Mux56.IN3
|
|
ctrl_i[43] => Mux57.IN3
|
|
ctrl_i[43] => Mux58.IN3
|
|
ctrl_i[43] => Mux59.IN3
|
|
ctrl_i[43] => Mux60.IN3
|
|
ctrl_i[43] => Mux61.IN3
|
|
ctrl_i[44] => Mux0.IN3
|
|
ctrl_i[44] => Mux1.IN0
|
|
ctrl_i[44] => Mux2.IN0
|
|
ctrl_i[44] => Mux3.IN0
|
|
ctrl_i[44] => Mux4.IN0
|
|
ctrl_i[44] => Mux5.IN0
|
|
ctrl_i[44] => Mux6.IN0
|
|
ctrl_i[44] => Mux7.IN0
|
|
ctrl_i[44] => Mux8.IN0
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => d_bus_wdata_o.OUTPUTSELECT
|
|
ctrl_i[44] => Mux9.IN0
|
|
ctrl_i[44] => Mux10.IN0
|
|
ctrl_i[44] => Mux11.IN0
|
|
ctrl_i[44] => Mux12.IN0
|
|
ctrl_i[44] => Mux13.IN0
|
|
ctrl_i[44] => Mux14.IN0
|
|
ctrl_i[44] => Mux15.IN0
|
|
ctrl_i[44] => Mux16.IN0
|
|
ctrl_i[44] => Mux17.IN3
|
|
ctrl_i[44] => Mux18.IN3
|
|
ctrl_i[44] => Mux19.IN4
|
|
ctrl_i[44] => Mux20.IN4
|
|
ctrl_i[44] => Mux30.IN2
|
|
ctrl_i[44] => Mux31.IN2
|
|
ctrl_i[44] => Mux32.IN2
|
|
ctrl_i[44] => Mux33.IN2
|
|
ctrl_i[44] => Mux34.IN2
|
|
ctrl_i[44] => Mux35.IN2
|
|
ctrl_i[44] => Mux36.IN2
|
|
ctrl_i[44] => Mux37.IN2
|
|
ctrl_i[44] => Mux38.IN2
|
|
ctrl_i[44] => Mux39.IN2
|
|
ctrl_i[44] => Mux40.IN2
|
|
ctrl_i[44] => Mux41.IN2
|
|
ctrl_i[44] => Mux42.IN2
|
|
ctrl_i[44] => Mux43.IN2
|
|
ctrl_i[44] => Mux44.IN2
|
|
ctrl_i[44] => Mux45.IN2
|
|
ctrl_i[44] => Mux46.IN2
|
|
ctrl_i[44] => Mux47.IN2
|
|
ctrl_i[44] => Mux48.IN2
|
|
ctrl_i[44] => Mux49.IN2
|
|
ctrl_i[44] => Mux50.IN2
|
|
ctrl_i[44] => Mux51.IN2
|
|
ctrl_i[44] => Mux52.IN2
|
|
ctrl_i[44] => Mux53.IN2
|
|
ctrl_i[44] => Mux54.IN2
|
|
ctrl_i[44] => Mux55.IN2
|
|
ctrl_i[44] => Mux56.IN2
|
|
ctrl_i[44] => Mux57.IN2
|
|
ctrl_i[44] => Mux58.IN2
|
|
ctrl_i[44] => Mux59.IN2
|
|
ctrl_i[44] => Mux60.IN2
|
|
ctrl_i[44] => Mux61.IN2
|
|
ctrl_i[45] => rdata_o.IN0
|
|
ctrl_i[45] => rdata_o.IN0
|
|
ctrl_i[45] => rdata_o.IN1
|
|
ctrl_i[46] => ~NO_FANOUT~
|
|
ctrl_i[47] => ~NO_FANOUT~
|
|
ctrl_i[48] => ~NO_FANOUT~
|
|
ctrl_i[49] => ~NO_FANOUT~
|
|
ctrl_i[50] => ~NO_FANOUT~
|
|
ctrl_i[51] => ~NO_FANOUT~
|
|
ctrl_i[52] => ~NO_FANOUT~
|
|
ctrl_i[53] => ~NO_FANOUT~
|
|
ctrl_i[54] => ~NO_FANOUT~
|
|
ctrl_i[55] => ~NO_FANOUT~
|
|
ctrl_i[56] => ~NO_FANOUT~
|
|
ctrl_i[57] => ~NO_FANOUT~
|
|
ctrl_i[58] => ~NO_FANOUT~
|
|
ctrl_i[59] => ~NO_FANOUT~
|
|
ctrl_i[60] => ~NO_FANOUT~
|
|
ctrl_i[61] => ~NO_FANOUT~
|
|
ctrl_i[62] => ~NO_FANOUT~
|
|
ctrl_i[63] => data_access_arbiter.IN1
|
|
ctrl_i[63] => ma_store_o.IN1
|
|
ctrl_i[63] => d_bus_we_o.IN1
|
|
ctrl_i[63] => ma_load_o.IN1
|
|
ctrl_i[63] => d_bus_re_o.IN1
|
|
ctrl_i[63] => data_access_arbiter.IN1
|
|
ctrl_i[64] => ~NO_FANOUT~
|
|
ctrl_i[65] => ~NO_FANOUT~
|
|
ctrl_i[66] => ~NO_FANOUT~
|
|
ctrl_i[67] => data_access_arbiter.IN0
|
|
ctrl_i[68] => ~NO_FANOUT~
|
|
fetch_pc_i[0] => ~NO_FANOUT~
|
|
fetch_pc_i[1] => ~NO_FANOUT~
|
|
fetch_pc_i[2] => ~NO_FANOUT~
|
|
fetch_pc_i[3] => ~NO_FANOUT~
|
|
fetch_pc_i[4] => ~NO_FANOUT~
|
|
fetch_pc_i[5] => ~NO_FANOUT~
|
|
fetch_pc_i[6] => ~NO_FANOUT~
|
|
fetch_pc_i[7] => ~NO_FANOUT~
|
|
fetch_pc_i[8] => ~NO_FANOUT~
|
|
fetch_pc_i[9] => ~NO_FANOUT~
|
|
fetch_pc_i[10] => ~NO_FANOUT~
|
|
fetch_pc_i[11] => ~NO_FANOUT~
|
|
fetch_pc_i[12] => ~NO_FANOUT~
|
|
fetch_pc_i[13] => ~NO_FANOUT~
|
|
fetch_pc_i[14] => ~NO_FANOUT~
|
|
fetch_pc_i[15] => ~NO_FANOUT~
|
|
fetch_pc_i[16] => ~NO_FANOUT~
|
|
fetch_pc_i[17] => ~NO_FANOUT~
|
|
fetch_pc_i[18] => ~NO_FANOUT~
|
|
fetch_pc_i[19] => ~NO_FANOUT~
|
|
fetch_pc_i[20] => ~NO_FANOUT~
|
|
fetch_pc_i[21] => ~NO_FANOUT~
|
|
fetch_pc_i[22] => ~NO_FANOUT~
|
|
fetch_pc_i[23] => ~NO_FANOUT~
|
|
fetch_pc_i[24] => ~NO_FANOUT~
|
|
fetch_pc_i[25] => ~NO_FANOUT~
|
|
fetch_pc_i[26] => ~NO_FANOUT~
|
|
fetch_pc_i[27] => ~NO_FANOUT~
|
|
fetch_pc_i[28] => ~NO_FANOUT~
|
|
fetch_pc_i[29] => ~NO_FANOUT~
|
|
fetch_pc_i[30] => ~NO_FANOUT~
|
|
fetch_pc_i[31] => ~NO_FANOUT~
|
|
i_pmp_fault_o <= <GND>
|
|
addr_i[0] => misaligned.IN0
|
|
addr_i[0] => Mux0.IN5
|
|
addr_i[0] => Decoder0.IN1
|
|
addr_i[0] => mar[0].DATAIN
|
|
addr_i[1] => misaligned.IN1
|
|
addr_i[1] => Decoder0.IN0
|
|
addr_i[1] => Mux17.IN5
|
|
addr_i[1] => Mux18.IN5
|
|
addr_i[1] => Mux19.IN3
|
|
addr_i[1] => Mux20.IN3
|
|
addr_i[1] => mar[1].DATAIN
|
|
addr_i[2] => mar[2].DATAIN
|
|
addr_i[3] => mar[3].DATAIN
|
|
addr_i[4] => mar[4].DATAIN
|
|
addr_i[5] => mar[5].DATAIN
|
|
addr_i[6] => mar[6].DATAIN
|
|
addr_i[7] => mar[7].DATAIN
|
|
addr_i[8] => mar[8].DATAIN
|
|
addr_i[9] => mar[9].DATAIN
|
|
addr_i[10] => mar[10].DATAIN
|
|
addr_i[11] => mar[11].DATAIN
|
|
addr_i[12] => mar[12].DATAIN
|
|
addr_i[13] => mar[13].DATAIN
|
|
addr_i[14] => mar[14].DATAIN
|
|
addr_i[15] => mar[15].DATAIN
|
|
addr_i[16] => mar[16].DATAIN
|
|
addr_i[17] => mar[17].DATAIN
|
|
addr_i[18] => mar[18].DATAIN
|
|
addr_i[19] => mar[19].DATAIN
|
|
addr_i[20] => mar[20].DATAIN
|
|
addr_i[21] => mar[21].DATAIN
|
|
addr_i[22] => mar[22].DATAIN
|
|
addr_i[23] => mar[23].DATAIN
|
|
addr_i[24] => mar[24].DATAIN
|
|
addr_i[25] => mar[25].DATAIN
|
|
addr_i[26] => mar[26].DATAIN
|
|
addr_i[27] => mar[27].DATAIN
|
|
addr_i[28] => mar[28].DATAIN
|
|
addr_i[29] => mar[29].DATAIN
|
|
addr_i[30] => mar[30].DATAIN
|
|
addr_i[31] => mar[31].DATAIN
|
|
wdata_i[0] => Mux8.IN5
|
|
wdata_i[0] => d_bus_wdata_o.DATAA
|
|
wdata_i[0] => Mux16.IN5
|
|
wdata_i[0] => d_bus_wdata_o[0]~reg0.DATAIN
|
|
wdata_i[1] => Mux7.IN5
|
|
wdata_i[1] => d_bus_wdata_o.DATAA
|
|
wdata_i[1] => Mux15.IN5
|
|
wdata_i[1] => d_bus_wdata_o[1]~reg0.DATAIN
|
|
wdata_i[2] => Mux6.IN5
|
|
wdata_i[2] => d_bus_wdata_o.DATAA
|
|
wdata_i[2] => Mux14.IN5
|
|
wdata_i[2] => d_bus_wdata_o[2]~reg0.DATAIN
|
|
wdata_i[3] => Mux5.IN5
|
|
wdata_i[3] => d_bus_wdata_o.DATAA
|
|
wdata_i[3] => Mux13.IN5
|
|
wdata_i[3] => d_bus_wdata_o[3]~reg0.DATAIN
|
|
wdata_i[4] => Mux4.IN5
|
|
wdata_i[4] => d_bus_wdata_o.DATAA
|
|
wdata_i[4] => Mux12.IN5
|
|
wdata_i[4] => d_bus_wdata_o[4]~reg0.DATAIN
|
|
wdata_i[5] => Mux3.IN5
|
|
wdata_i[5] => d_bus_wdata_o.DATAA
|
|
wdata_i[5] => Mux11.IN5
|
|
wdata_i[5] => d_bus_wdata_o[5]~reg0.DATAIN
|
|
wdata_i[6] => Mux2.IN5
|
|
wdata_i[6] => d_bus_wdata_o.DATAA
|
|
wdata_i[6] => Mux10.IN5
|
|
wdata_i[6] => d_bus_wdata_o[6]~reg0.DATAIN
|
|
wdata_i[7] => Mux1.IN5
|
|
wdata_i[7] => d_bus_wdata_o.DATAA
|
|
wdata_i[7] => Mux9.IN5
|
|
wdata_i[7] => d_bus_wdata_o[7]~reg0.DATAIN
|
|
wdata_i[8] => Mux8.IN4
|
|
wdata_i[8] => Mux16.IN2
|
|
wdata_i[8] => Mux16.IN3
|
|
wdata_i[8] => Mux16.IN4
|
|
wdata_i[9] => Mux7.IN4
|
|
wdata_i[9] => Mux15.IN2
|
|
wdata_i[9] => Mux15.IN3
|
|
wdata_i[9] => Mux15.IN4
|
|
wdata_i[10] => Mux6.IN4
|
|
wdata_i[10] => Mux14.IN2
|
|
wdata_i[10] => Mux14.IN3
|
|
wdata_i[10] => Mux14.IN4
|
|
wdata_i[11] => Mux5.IN4
|
|
wdata_i[11] => Mux13.IN2
|
|
wdata_i[11] => Mux13.IN3
|
|
wdata_i[11] => Mux13.IN4
|
|
wdata_i[12] => Mux4.IN4
|
|
wdata_i[12] => Mux12.IN2
|
|
wdata_i[12] => Mux12.IN3
|
|
wdata_i[12] => Mux12.IN4
|
|
wdata_i[13] => Mux3.IN4
|
|
wdata_i[13] => Mux11.IN2
|
|
wdata_i[13] => Mux11.IN3
|
|
wdata_i[13] => Mux11.IN4
|
|
wdata_i[14] => Mux2.IN4
|
|
wdata_i[14] => Mux10.IN2
|
|
wdata_i[14] => Mux10.IN3
|
|
wdata_i[14] => Mux10.IN4
|
|
wdata_i[15] => Mux1.IN4
|
|
wdata_i[15] => Mux9.IN2
|
|
wdata_i[15] => Mux9.IN3
|
|
wdata_i[15] => Mux9.IN4
|
|
wdata_i[16] => d_bus_wdata_o.DATAB
|
|
wdata_i[17] => d_bus_wdata_o.DATAB
|
|
wdata_i[18] => d_bus_wdata_o.DATAB
|
|
wdata_i[19] => d_bus_wdata_o.DATAB
|
|
wdata_i[20] => d_bus_wdata_o.DATAB
|
|
wdata_i[21] => d_bus_wdata_o.DATAB
|
|
wdata_i[22] => d_bus_wdata_o.DATAB
|
|
wdata_i[23] => d_bus_wdata_o.DATAB
|
|
wdata_i[24] => Mux8.IN2
|
|
wdata_i[24] => Mux8.IN3
|
|
wdata_i[25] => Mux7.IN2
|
|
wdata_i[25] => Mux7.IN3
|
|
wdata_i[26] => Mux6.IN2
|
|
wdata_i[26] => Mux6.IN3
|
|
wdata_i[27] => Mux5.IN2
|
|
wdata_i[27] => Mux5.IN3
|
|
wdata_i[28] => Mux4.IN2
|
|
wdata_i[28] => Mux4.IN3
|
|
wdata_i[29] => Mux3.IN2
|
|
wdata_i[29] => Mux3.IN3
|
|
wdata_i[30] => Mux2.IN2
|
|
wdata_i[30] => Mux2.IN3
|
|
wdata_i[31] => Mux1.IN2
|
|
wdata_i[31] => Mux1.IN3
|
|
rdata_o[0] <= rdata_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[1] <= rdata_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[2] <= rdata_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[3] <= rdata_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[4] <= rdata_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[5] <= rdata_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[6] <= rdata_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[7] <= rdata_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[8] <= rdata_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[9] <= rdata_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[10] <= rdata_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[11] <= rdata_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[12] <= rdata_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[13] <= rdata_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[14] <= rdata_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[15] <= rdata_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[16] <= rdata_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[17] <= rdata_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[18] <= rdata_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[19] <= rdata_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[20] <= rdata_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[21] <= rdata_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[22] <= rdata_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[23] <= rdata_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[24] <= rdata_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[25] <= rdata_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[26] <= rdata_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[27] <= rdata_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[28] <= rdata_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[29] <= rdata_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[30] <= rdata_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[31] <= rdata_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[0] <= mar[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[1] <= mar[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[2] <= mar[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[3] <= mar[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[4] <= mar[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[5] <= mar[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[6] <= mar[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[7] <= mar[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[8] <= mar[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[9] <= mar[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[10] <= mar[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[11] <= mar[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[12] <= mar[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[13] <= mar[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[14] <= mar[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[15] <= mar[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[16] <= mar[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[17] <= mar[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[18] <= mar[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[19] <= mar[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[20] <= mar[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[21] <= mar[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[22] <= mar[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[23] <= mar[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[24] <= mar[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[25] <= mar[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[26] <= mar[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[27] <= mar[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[28] <= mar[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[29] <= mar[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[30] <= mar[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
mar_o[31] <= mar[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_wait_o <= d_bus_ack_i.DB_MAX_OUTPUT_PORT_TYPE
|
|
ma_load_o <= ma_load_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ma_store_o <= ma_store_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
be_load_o <= be_load_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
be_store_o <= be_store_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
pmp_addr_i[15][0] => ~NO_FANOUT~
|
|
pmp_addr_i[15][1] => ~NO_FANOUT~
|
|
pmp_addr_i[15][2] => ~NO_FANOUT~
|
|
pmp_addr_i[15][3] => ~NO_FANOUT~
|
|
pmp_addr_i[15][4] => ~NO_FANOUT~
|
|
pmp_addr_i[15][5] => ~NO_FANOUT~
|
|
pmp_addr_i[15][6] => ~NO_FANOUT~
|
|
pmp_addr_i[15][7] => ~NO_FANOUT~
|
|
pmp_addr_i[15][8] => ~NO_FANOUT~
|
|
pmp_addr_i[15][9] => ~NO_FANOUT~
|
|
pmp_addr_i[15][10] => ~NO_FANOUT~
|
|
pmp_addr_i[15][11] => ~NO_FANOUT~
|
|
pmp_addr_i[15][12] => ~NO_FANOUT~
|
|
pmp_addr_i[15][13] => ~NO_FANOUT~
|
|
pmp_addr_i[15][14] => ~NO_FANOUT~
|
|
pmp_addr_i[15][15] => ~NO_FANOUT~
|
|
pmp_addr_i[15][16] => ~NO_FANOUT~
|
|
pmp_addr_i[15][17] => ~NO_FANOUT~
|
|
pmp_addr_i[15][18] => ~NO_FANOUT~
|
|
pmp_addr_i[15][19] => ~NO_FANOUT~
|
|
pmp_addr_i[15][20] => ~NO_FANOUT~
|
|
pmp_addr_i[15][21] => ~NO_FANOUT~
|
|
pmp_addr_i[15][22] => ~NO_FANOUT~
|
|
pmp_addr_i[15][23] => ~NO_FANOUT~
|
|
pmp_addr_i[15][24] => ~NO_FANOUT~
|
|
pmp_addr_i[15][25] => ~NO_FANOUT~
|
|
pmp_addr_i[15][26] => ~NO_FANOUT~
|
|
pmp_addr_i[15][27] => ~NO_FANOUT~
|
|
pmp_addr_i[15][28] => ~NO_FANOUT~
|
|
pmp_addr_i[15][29] => ~NO_FANOUT~
|
|
pmp_addr_i[15][30] => ~NO_FANOUT~
|
|
pmp_addr_i[15][31] => ~NO_FANOUT~
|
|
pmp_addr_i[15][32] => ~NO_FANOUT~
|
|
pmp_addr_i[15][33] => ~NO_FANOUT~
|
|
pmp_addr_i[14][0] => ~NO_FANOUT~
|
|
pmp_addr_i[14][1] => ~NO_FANOUT~
|
|
pmp_addr_i[14][2] => ~NO_FANOUT~
|
|
pmp_addr_i[14][3] => ~NO_FANOUT~
|
|
pmp_addr_i[14][4] => ~NO_FANOUT~
|
|
pmp_addr_i[14][5] => ~NO_FANOUT~
|
|
pmp_addr_i[14][6] => ~NO_FANOUT~
|
|
pmp_addr_i[14][7] => ~NO_FANOUT~
|
|
pmp_addr_i[14][8] => ~NO_FANOUT~
|
|
pmp_addr_i[14][9] => ~NO_FANOUT~
|
|
pmp_addr_i[14][10] => ~NO_FANOUT~
|
|
pmp_addr_i[14][11] => ~NO_FANOUT~
|
|
pmp_addr_i[14][12] => ~NO_FANOUT~
|
|
pmp_addr_i[14][13] => ~NO_FANOUT~
|
|
pmp_addr_i[14][14] => ~NO_FANOUT~
|
|
pmp_addr_i[14][15] => ~NO_FANOUT~
|
|
pmp_addr_i[14][16] => ~NO_FANOUT~
|
|
pmp_addr_i[14][17] => ~NO_FANOUT~
|
|
pmp_addr_i[14][18] => ~NO_FANOUT~
|
|
pmp_addr_i[14][19] => ~NO_FANOUT~
|
|
pmp_addr_i[14][20] => ~NO_FANOUT~
|
|
pmp_addr_i[14][21] => ~NO_FANOUT~
|
|
pmp_addr_i[14][22] => ~NO_FANOUT~
|
|
pmp_addr_i[14][23] => ~NO_FANOUT~
|
|
pmp_addr_i[14][24] => ~NO_FANOUT~
|
|
pmp_addr_i[14][25] => ~NO_FANOUT~
|
|
pmp_addr_i[14][26] => ~NO_FANOUT~
|
|
pmp_addr_i[14][27] => ~NO_FANOUT~
|
|
pmp_addr_i[14][28] => ~NO_FANOUT~
|
|
pmp_addr_i[14][29] => ~NO_FANOUT~
|
|
pmp_addr_i[14][30] => ~NO_FANOUT~
|
|
pmp_addr_i[14][31] => ~NO_FANOUT~
|
|
pmp_addr_i[14][32] => ~NO_FANOUT~
|
|
pmp_addr_i[14][33] => ~NO_FANOUT~
|
|
pmp_addr_i[13][0] => ~NO_FANOUT~
|
|
pmp_addr_i[13][1] => ~NO_FANOUT~
|
|
pmp_addr_i[13][2] => ~NO_FANOUT~
|
|
pmp_addr_i[13][3] => ~NO_FANOUT~
|
|
pmp_addr_i[13][4] => ~NO_FANOUT~
|
|
pmp_addr_i[13][5] => ~NO_FANOUT~
|
|
pmp_addr_i[13][6] => ~NO_FANOUT~
|
|
pmp_addr_i[13][7] => ~NO_FANOUT~
|
|
pmp_addr_i[13][8] => ~NO_FANOUT~
|
|
pmp_addr_i[13][9] => ~NO_FANOUT~
|
|
pmp_addr_i[13][10] => ~NO_FANOUT~
|
|
pmp_addr_i[13][11] => ~NO_FANOUT~
|
|
pmp_addr_i[13][12] => ~NO_FANOUT~
|
|
pmp_addr_i[13][13] => ~NO_FANOUT~
|
|
pmp_addr_i[13][14] => ~NO_FANOUT~
|
|
pmp_addr_i[13][15] => ~NO_FANOUT~
|
|
pmp_addr_i[13][16] => ~NO_FANOUT~
|
|
pmp_addr_i[13][17] => ~NO_FANOUT~
|
|
pmp_addr_i[13][18] => ~NO_FANOUT~
|
|
pmp_addr_i[13][19] => ~NO_FANOUT~
|
|
pmp_addr_i[13][20] => ~NO_FANOUT~
|
|
pmp_addr_i[13][21] => ~NO_FANOUT~
|
|
pmp_addr_i[13][22] => ~NO_FANOUT~
|
|
pmp_addr_i[13][23] => ~NO_FANOUT~
|
|
pmp_addr_i[13][24] => ~NO_FANOUT~
|
|
pmp_addr_i[13][25] => ~NO_FANOUT~
|
|
pmp_addr_i[13][26] => ~NO_FANOUT~
|
|
pmp_addr_i[13][27] => ~NO_FANOUT~
|
|
pmp_addr_i[13][28] => ~NO_FANOUT~
|
|
pmp_addr_i[13][29] => ~NO_FANOUT~
|
|
pmp_addr_i[13][30] => ~NO_FANOUT~
|
|
pmp_addr_i[13][31] => ~NO_FANOUT~
|
|
pmp_addr_i[13][32] => ~NO_FANOUT~
|
|
pmp_addr_i[13][33] => ~NO_FANOUT~
|
|
pmp_addr_i[12][0] => ~NO_FANOUT~
|
|
pmp_addr_i[12][1] => ~NO_FANOUT~
|
|
pmp_addr_i[12][2] => ~NO_FANOUT~
|
|
pmp_addr_i[12][3] => ~NO_FANOUT~
|
|
pmp_addr_i[12][4] => ~NO_FANOUT~
|
|
pmp_addr_i[12][5] => ~NO_FANOUT~
|
|
pmp_addr_i[12][6] => ~NO_FANOUT~
|
|
pmp_addr_i[12][7] => ~NO_FANOUT~
|
|
pmp_addr_i[12][8] => ~NO_FANOUT~
|
|
pmp_addr_i[12][9] => ~NO_FANOUT~
|
|
pmp_addr_i[12][10] => ~NO_FANOUT~
|
|
pmp_addr_i[12][11] => ~NO_FANOUT~
|
|
pmp_addr_i[12][12] => ~NO_FANOUT~
|
|
pmp_addr_i[12][13] => ~NO_FANOUT~
|
|
pmp_addr_i[12][14] => ~NO_FANOUT~
|
|
pmp_addr_i[12][15] => ~NO_FANOUT~
|
|
pmp_addr_i[12][16] => ~NO_FANOUT~
|
|
pmp_addr_i[12][17] => ~NO_FANOUT~
|
|
pmp_addr_i[12][18] => ~NO_FANOUT~
|
|
pmp_addr_i[12][19] => ~NO_FANOUT~
|
|
pmp_addr_i[12][20] => ~NO_FANOUT~
|
|
pmp_addr_i[12][21] => ~NO_FANOUT~
|
|
pmp_addr_i[12][22] => ~NO_FANOUT~
|
|
pmp_addr_i[12][23] => ~NO_FANOUT~
|
|
pmp_addr_i[12][24] => ~NO_FANOUT~
|
|
pmp_addr_i[12][25] => ~NO_FANOUT~
|
|
pmp_addr_i[12][26] => ~NO_FANOUT~
|
|
pmp_addr_i[12][27] => ~NO_FANOUT~
|
|
pmp_addr_i[12][28] => ~NO_FANOUT~
|
|
pmp_addr_i[12][29] => ~NO_FANOUT~
|
|
pmp_addr_i[12][30] => ~NO_FANOUT~
|
|
pmp_addr_i[12][31] => ~NO_FANOUT~
|
|
pmp_addr_i[12][32] => ~NO_FANOUT~
|
|
pmp_addr_i[12][33] => ~NO_FANOUT~
|
|
pmp_addr_i[11][0] => ~NO_FANOUT~
|
|
pmp_addr_i[11][1] => ~NO_FANOUT~
|
|
pmp_addr_i[11][2] => ~NO_FANOUT~
|
|
pmp_addr_i[11][3] => ~NO_FANOUT~
|
|
pmp_addr_i[11][4] => ~NO_FANOUT~
|
|
pmp_addr_i[11][5] => ~NO_FANOUT~
|
|
pmp_addr_i[11][6] => ~NO_FANOUT~
|
|
pmp_addr_i[11][7] => ~NO_FANOUT~
|
|
pmp_addr_i[11][8] => ~NO_FANOUT~
|
|
pmp_addr_i[11][9] => ~NO_FANOUT~
|
|
pmp_addr_i[11][10] => ~NO_FANOUT~
|
|
pmp_addr_i[11][11] => ~NO_FANOUT~
|
|
pmp_addr_i[11][12] => ~NO_FANOUT~
|
|
pmp_addr_i[11][13] => ~NO_FANOUT~
|
|
pmp_addr_i[11][14] => ~NO_FANOUT~
|
|
pmp_addr_i[11][15] => ~NO_FANOUT~
|
|
pmp_addr_i[11][16] => ~NO_FANOUT~
|
|
pmp_addr_i[11][17] => ~NO_FANOUT~
|
|
pmp_addr_i[11][18] => ~NO_FANOUT~
|
|
pmp_addr_i[11][19] => ~NO_FANOUT~
|
|
pmp_addr_i[11][20] => ~NO_FANOUT~
|
|
pmp_addr_i[11][21] => ~NO_FANOUT~
|
|
pmp_addr_i[11][22] => ~NO_FANOUT~
|
|
pmp_addr_i[11][23] => ~NO_FANOUT~
|
|
pmp_addr_i[11][24] => ~NO_FANOUT~
|
|
pmp_addr_i[11][25] => ~NO_FANOUT~
|
|
pmp_addr_i[11][26] => ~NO_FANOUT~
|
|
pmp_addr_i[11][27] => ~NO_FANOUT~
|
|
pmp_addr_i[11][28] => ~NO_FANOUT~
|
|
pmp_addr_i[11][29] => ~NO_FANOUT~
|
|
pmp_addr_i[11][30] => ~NO_FANOUT~
|
|
pmp_addr_i[11][31] => ~NO_FANOUT~
|
|
pmp_addr_i[11][32] => ~NO_FANOUT~
|
|
pmp_addr_i[11][33] => ~NO_FANOUT~
|
|
pmp_addr_i[10][0] => ~NO_FANOUT~
|
|
pmp_addr_i[10][1] => ~NO_FANOUT~
|
|
pmp_addr_i[10][2] => ~NO_FANOUT~
|
|
pmp_addr_i[10][3] => ~NO_FANOUT~
|
|
pmp_addr_i[10][4] => ~NO_FANOUT~
|
|
pmp_addr_i[10][5] => ~NO_FANOUT~
|
|
pmp_addr_i[10][6] => ~NO_FANOUT~
|
|
pmp_addr_i[10][7] => ~NO_FANOUT~
|
|
pmp_addr_i[10][8] => ~NO_FANOUT~
|
|
pmp_addr_i[10][9] => ~NO_FANOUT~
|
|
pmp_addr_i[10][10] => ~NO_FANOUT~
|
|
pmp_addr_i[10][11] => ~NO_FANOUT~
|
|
pmp_addr_i[10][12] => ~NO_FANOUT~
|
|
pmp_addr_i[10][13] => ~NO_FANOUT~
|
|
pmp_addr_i[10][14] => ~NO_FANOUT~
|
|
pmp_addr_i[10][15] => ~NO_FANOUT~
|
|
pmp_addr_i[10][16] => ~NO_FANOUT~
|
|
pmp_addr_i[10][17] => ~NO_FANOUT~
|
|
pmp_addr_i[10][18] => ~NO_FANOUT~
|
|
pmp_addr_i[10][19] => ~NO_FANOUT~
|
|
pmp_addr_i[10][20] => ~NO_FANOUT~
|
|
pmp_addr_i[10][21] => ~NO_FANOUT~
|
|
pmp_addr_i[10][22] => ~NO_FANOUT~
|
|
pmp_addr_i[10][23] => ~NO_FANOUT~
|
|
pmp_addr_i[10][24] => ~NO_FANOUT~
|
|
pmp_addr_i[10][25] => ~NO_FANOUT~
|
|
pmp_addr_i[10][26] => ~NO_FANOUT~
|
|
pmp_addr_i[10][27] => ~NO_FANOUT~
|
|
pmp_addr_i[10][28] => ~NO_FANOUT~
|
|
pmp_addr_i[10][29] => ~NO_FANOUT~
|
|
pmp_addr_i[10][30] => ~NO_FANOUT~
|
|
pmp_addr_i[10][31] => ~NO_FANOUT~
|
|
pmp_addr_i[10][32] => ~NO_FANOUT~
|
|
pmp_addr_i[10][33] => ~NO_FANOUT~
|
|
pmp_addr_i[9][0] => ~NO_FANOUT~
|
|
pmp_addr_i[9][1] => ~NO_FANOUT~
|
|
pmp_addr_i[9][2] => ~NO_FANOUT~
|
|
pmp_addr_i[9][3] => ~NO_FANOUT~
|
|
pmp_addr_i[9][4] => ~NO_FANOUT~
|
|
pmp_addr_i[9][5] => ~NO_FANOUT~
|
|
pmp_addr_i[9][6] => ~NO_FANOUT~
|
|
pmp_addr_i[9][7] => ~NO_FANOUT~
|
|
pmp_addr_i[9][8] => ~NO_FANOUT~
|
|
pmp_addr_i[9][9] => ~NO_FANOUT~
|
|
pmp_addr_i[9][10] => ~NO_FANOUT~
|
|
pmp_addr_i[9][11] => ~NO_FANOUT~
|
|
pmp_addr_i[9][12] => ~NO_FANOUT~
|
|
pmp_addr_i[9][13] => ~NO_FANOUT~
|
|
pmp_addr_i[9][14] => ~NO_FANOUT~
|
|
pmp_addr_i[9][15] => ~NO_FANOUT~
|
|
pmp_addr_i[9][16] => ~NO_FANOUT~
|
|
pmp_addr_i[9][17] => ~NO_FANOUT~
|
|
pmp_addr_i[9][18] => ~NO_FANOUT~
|
|
pmp_addr_i[9][19] => ~NO_FANOUT~
|
|
pmp_addr_i[9][20] => ~NO_FANOUT~
|
|
pmp_addr_i[9][21] => ~NO_FANOUT~
|
|
pmp_addr_i[9][22] => ~NO_FANOUT~
|
|
pmp_addr_i[9][23] => ~NO_FANOUT~
|
|
pmp_addr_i[9][24] => ~NO_FANOUT~
|
|
pmp_addr_i[9][25] => ~NO_FANOUT~
|
|
pmp_addr_i[9][26] => ~NO_FANOUT~
|
|
pmp_addr_i[9][27] => ~NO_FANOUT~
|
|
pmp_addr_i[9][28] => ~NO_FANOUT~
|
|
pmp_addr_i[9][29] => ~NO_FANOUT~
|
|
pmp_addr_i[9][30] => ~NO_FANOUT~
|
|
pmp_addr_i[9][31] => ~NO_FANOUT~
|
|
pmp_addr_i[9][32] => ~NO_FANOUT~
|
|
pmp_addr_i[9][33] => ~NO_FANOUT~
|
|
pmp_addr_i[8][0] => ~NO_FANOUT~
|
|
pmp_addr_i[8][1] => ~NO_FANOUT~
|
|
pmp_addr_i[8][2] => ~NO_FANOUT~
|
|
pmp_addr_i[8][3] => ~NO_FANOUT~
|
|
pmp_addr_i[8][4] => ~NO_FANOUT~
|
|
pmp_addr_i[8][5] => ~NO_FANOUT~
|
|
pmp_addr_i[8][6] => ~NO_FANOUT~
|
|
pmp_addr_i[8][7] => ~NO_FANOUT~
|
|
pmp_addr_i[8][8] => ~NO_FANOUT~
|
|
pmp_addr_i[8][9] => ~NO_FANOUT~
|
|
pmp_addr_i[8][10] => ~NO_FANOUT~
|
|
pmp_addr_i[8][11] => ~NO_FANOUT~
|
|
pmp_addr_i[8][12] => ~NO_FANOUT~
|
|
pmp_addr_i[8][13] => ~NO_FANOUT~
|
|
pmp_addr_i[8][14] => ~NO_FANOUT~
|
|
pmp_addr_i[8][15] => ~NO_FANOUT~
|
|
pmp_addr_i[8][16] => ~NO_FANOUT~
|
|
pmp_addr_i[8][17] => ~NO_FANOUT~
|
|
pmp_addr_i[8][18] => ~NO_FANOUT~
|
|
pmp_addr_i[8][19] => ~NO_FANOUT~
|
|
pmp_addr_i[8][20] => ~NO_FANOUT~
|
|
pmp_addr_i[8][21] => ~NO_FANOUT~
|
|
pmp_addr_i[8][22] => ~NO_FANOUT~
|
|
pmp_addr_i[8][23] => ~NO_FANOUT~
|
|
pmp_addr_i[8][24] => ~NO_FANOUT~
|
|
pmp_addr_i[8][25] => ~NO_FANOUT~
|
|
pmp_addr_i[8][26] => ~NO_FANOUT~
|
|
pmp_addr_i[8][27] => ~NO_FANOUT~
|
|
pmp_addr_i[8][28] => ~NO_FANOUT~
|
|
pmp_addr_i[8][29] => ~NO_FANOUT~
|
|
pmp_addr_i[8][30] => ~NO_FANOUT~
|
|
pmp_addr_i[8][31] => ~NO_FANOUT~
|
|
pmp_addr_i[8][32] => ~NO_FANOUT~
|
|
pmp_addr_i[8][33] => ~NO_FANOUT~
|
|
pmp_addr_i[7][0] => ~NO_FANOUT~
|
|
pmp_addr_i[7][1] => ~NO_FANOUT~
|
|
pmp_addr_i[7][2] => ~NO_FANOUT~
|
|
pmp_addr_i[7][3] => ~NO_FANOUT~
|
|
pmp_addr_i[7][4] => ~NO_FANOUT~
|
|
pmp_addr_i[7][5] => ~NO_FANOUT~
|
|
pmp_addr_i[7][6] => ~NO_FANOUT~
|
|
pmp_addr_i[7][7] => ~NO_FANOUT~
|
|
pmp_addr_i[7][8] => ~NO_FANOUT~
|
|
pmp_addr_i[7][9] => ~NO_FANOUT~
|
|
pmp_addr_i[7][10] => ~NO_FANOUT~
|
|
pmp_addr_i[7][11] => ~NO_FANOUT~
|
|
pmp_addr_i[7][12] => ~NO_FANOUT~
|
|
pmp_addr_i[7][13] => ~NO_FANOUT~
|
|
pmp_addr_i[7][14] => ~NO_FANOUT~
|
|
pmp_addr_i[7][15] => ~NO_FANOUT~
|
|
pmp_addr_i[7][16] => ~NO_FANOUT~
|
|
pmp_addr_i[7][17] => ~NO_FANOUT~
|
|
pmp_addr_i[7][18] => ~NO_FANOUT~
|
|
pmp_addr_i[7][19] => ~NO_FANOUT~
|
|
pmp_addr_i[7][20] => ~NO_FANOUT~
|
|
pmp_addr_i[7][21] => ~NO_FANOUT~
|
|
pmp_addr_i[7][22] => ~NO_FANOUT~
|
|
pmp_addr_i[7][23] => ~NO_FANOUT~
|
|
pmp_addr_i[7][24] => ~NO_FANOUT~
|
|
pmp_addr_i[7][25] => ~NO_FANOUT~
|
|
pmp_addr_i[7][26] => ~NO_FANOUT~
|
|
pmp_addr_i[7][27] => ~NO_FANOUT~
|
|
pmp_addr_i[7][28] => ~NO_FANOUT~
|
|
pmp_addr_i[7][29] => ~NO_FANOUT~
|
|
pmp_addr_i[7][30] => ~NO_FANOUT~
|
|
pmp_addr_i[7][31] => ~NO_FANOUT~
|
|
pmp_addr_i[7][32] => ~NO_FANOUT~
|
|
pmp_addr_i[7][33] => ~NO_FANOUT~
|
|
pmp_addr_i[6][0] => ~NO_FANOUT~
|
|
pmp_addr_i[6][1] => ~NO_FANOUT~
|
|
pmp_addr_i[6][2] => ~NO_FANOUT~
|
|
pmp_addr_i[6][3] => ~NO_FANOUT~
|
|
pmp_addr_i[6][4] => ~NO_FANOUT~
|
|
pmp_addr_i[6][5] => ~NO_FANOUT~
|
|
pmp_addr_i[6][6] => ~NO_FANOUT~
|
|
pmp_addr_i[6][7] => ~NO_FANOUT~
|
|
pmp_addr_i[6][8] => ~NO_FANOUT~
|
|
pmp_addr_i[6][9] => ~NO_FANOUT~
|
|
pmp_addr_i[6][10] => ~NO_FANOUT~
|
|
pmp_addr_i[6][11] => ~NO_FANOUT~
|
|
pmp_addr_i[6][12] => ~NO_FANOUT~
|
|
pmp_addr_i[6][13] => ~NO_FANOUT~
|
|
pmp_addr_i[6][14] => ~NO_FANOUT~
|
|
pmp_addr_i[6][15] => ~NO_FANOUT~
|
|
pmp_addr_i[6][16] => ~NO_FANOUT~
|
|
pmp_addr_i[6][17] => ~NO_FANOUT~
|
|
pmp_addr_i[6][18] => ~NO_FANOUT~
|
|
pmp_addr_i[6][19] => ~NO_FANOUT~
|
|
pmp_addr_i[6][20] => ~NO_FANOUT~
|
|
pmp_addr_i[6][21] => ~NO_FANOUT~
|
|
pmp_addr_i[6][22] => ~NO_FANOUT~
|
|
pmp_addr_i[6][23] => ~NO_FANOUT~
|
|
pmp_addr_i[6][24] => ~NO_FANOUT~
|
|
pmp_addr_i[6][25] => ~NO_FANOUT~
|
|
pmp_addr_i[6][26] => ~NO_FANOUT~
|
|
pmp_addr_i[6][27] => ~NO_FANOUT~
|
|
pmp_addr_i[6][28] => ~NO_FANOUT~
|
|
pmp_addr_i[6][29] => ~NO_FANOUT~
|
|
pmp_addr_i[6][30] => ~NO_FANOUT~
|
|
pmp_addr_i[6][31] => ~NO_FANOUT~
|
|
pmp_addr_i[6][32] => ~NO_FANOUT~
|
|
pmp_addr_i[6][33] => ~NO_FANOUT~
|
|
pmp_addr_i[5][0] => ~NO_FANOUT~
|
|
pmp_addr_i[5][1] => ~NO_FANOUT~
|
|
pmp_addr_i[5][2] => ~NO_FANOUT~
|
|
pmp_addr_i[5][3] => ~NO_FANOUT~
|
|
pmp_addr_i[5][4] => ~NO_FANOUT~
|
|
pmp_addr_i[5][5] => ~NO_FANOUT~
|
|
pmp_addr_i[5][6] => ~NO_FANOUT~
|
|
pmp_addr_i[5][7] => ~NO_FANOUT~
|
|
pmp_addr_i[5][8] => ~NO_FANOUT~
|
|
pmp_addr_i[5][9] => ~NO_FANOUT~
|
|
pmp_addr_i[5][10] => ~NO_FANOUT~
|
|
pmp_addr_i[5][11] => ~NO_FANOUT~
|
|
pmp_addr_i[5][12] => ~NO_FANOUT~
|
|
pmp_addr_i[5][13] => ~NO_FANOUT~
|
|
pmp_addr_i[5][14] => ~NO_FANOUT~
|
|
pmp_addr_i[5][15] => ~NO_FANOUT~
|
|
pmp_addr_i[5][16] => ~NO_FANOUT~
|
|
pmp_addr_i[5][17] => ~NO_FANOUT~
|
|
pmp_addr_i[5][18] => ~NO_FANOUT~
|
|
pmp_addr_i[5][19] => ~NO_FANOUT~
|
|
pmp_addr_i[5][20] => ~NO_FANOUT~
|
|
pmp_addr_i[5][21] => ~NO_FANOUT~
|
|
pmp_addr_i[5][22] => ~NO_FANOUT~
|
|
pmp_addr_i[5][23] => ~NO_FANOUT~
|
|
pmp_addr_i[5][24] => ~NO_FANOUT~
|
|
pmp_addr_i[5][25] => ~NO_FANOUT~
|
|
pmp_addr_i[5][26] => ~NO_FANOUT~
|
|
pmp_addr_i[5][27] => ~NO_FANOUT~
|
|
pmp_addr_i[5][28] => ~NO_FANOUT~
|
|
pmp_addr_i[5][29] => ~NO_FANOUT~
|
|
pmp_addr_i[5][30] => ~NO_FANOUT~
|
|
pmp_addr_i[5][31] => ~NO_FANOUT~
|
|
pmp_addr_i[5][32] => ~NO_FANOUT~
|
|
pmp_addr_i[5][33] => ~NO_FANOUT~
|
|
pmp_addr_i[4][0] => ~NO_FANOUT~
|
|
pmp_addr_i[4][1] => ~NO_FANOUT~
|
|
pmp_addr_i[4][2] => ~NO_FANOUT~
|
|
pmp_addr_i[4][3] => ~NO_FANOUT~
|
|
pmp_addr_i[4][4] => ~NO_FANOUT~
|
|
pmp_addr_i[4][5] => ~NO_FANOUT~
|
|
pmp_addr_i[4][6] => ~NO_FANOUT~
|
|
pmp_addr_i[4][7] => ~NO_FANOUT~
|
|
pmp_addr_i[4][8] => ~NO_FANOUT~
|
|
pmp_addr_i[4][9] => ~NO_FANOUT~
|
|
pmp_addr_i[4][10] => ~NO_FANOUT~
|
|
pmp_addr_i[4][11] => ~NO_FANOUT~
|
|
pmp_addr_i[4][12] => ~NO_FANOUT~
|
|
pmp_addr_i[4][13] => ~NO_FANOUT~
|
|
pmp_addr_i[4][14] => ~NO_FANOUT~
|
|
pmp_addr_i[4][15] => ~NO_FANOUT~
|
|
pmp_addr_i[4][16] => ~NO_FANOUT~
|
|
pmp_addr_i[4][17] => ~NO_FANOUT~
|
|
pmp_addr_i[4][18] => ~NO_FANOUT~
|
|
pmp_addr_i[4][19] => ~NO_FANOUT~
|
|
pmp_addr_i[4][20] => ~NO_FANOUT~
|
|
pmp_addr_i[4][21] => ~NO_FANOUT~
|
|
pmp_addr_i[4][22] => ~NO_FANOUT~
|
|
pmp_addr_i[4][23] => ~NO_FANOUT~
|
|
pmp_addr_i[4][24] => ~NO_FANOUT~
|
|
pmp_addr_i[4][25] => ~NO_FANOUT~
|
|
pmp_addr_i[4][26] => ~NO_FANOUT~
|
|
pmp_addr_i[4][27] => ~NO_FANOUT~
|
|
pmp_addr_i[4][28] => ~NO_FANOUT~
|
|
pmp_addr_i[4][29] => ~NO_FANOUT~
|
|
pmp_addr_i[4][30] => ~NO_FANOUT~
|
|
pmp_addr_i[4][31] => ~NO_FANOUT~
|
|
pmp_addr_i[4][32] => ~NO_FANOUT~
|
|
pmp_addr_i[4][33] => ~NO_FANOUT~
|
|
pmp_addr_i[3][0] => ~NO_FANOUT~
|
|
pmp_addr_i[3][1] => ~NO_FANOUT~
|
|
pmp_addr_i[3][2] => ~NO_FANOUT~
|
|
pmp_addr_i[3][3] => ~NO_FANOUT~
|
|
pmp_addr_i[3][4] => ~NO_FANOUT~
|
|
pmp_addr_i[3][5] => ~NO_FANOUT~
|
|
pmp_addr_i[3][6] => ~NO_FANOUT~
|
|
pmp_addr_i[3][7] => ~NO_FANOUT~
|
|
pmp_addr_i[3][8] => ~NO_FANOUT~
|
|
pmp_addr_i[3][9] => ~NO_FANOUT~
|
|
pmp_addr_i[3][10] => ~NO_FANOUT~
|
|
pmp_addr_i[3][11] => ~NO_FANOUT~
|
|
pmp_addr_i[3][12] => ~NO_FANOUT~
|
|
pmp_addr_i[3][13] => ~NO_FANOUT~
|
|
pmp_addr_i[3][14] => ~NO_FANOUT~
|
|
pmp_addr_i[3][15] => ~NO_FANOUT~
|
|
pmp_addr_i[3][16] => ~NO_FANOUT~
|
|
pmp_addr_i[3][17] => ~NO_FANOUT~
|
|
pmp_addr_i[3][18] => ~NO_FANOUT~
|
|
pmp_addr_i[3][19] => ~NO_FANOUT~
|
|
pmp_addr_i[3][20] => ~NO_FANOUT~
|
|
pmp_addr_i[3][21] => ~NO_FANOUT~
|
|
pmp_addr_i[3][22] => ~NO_FANOUT~
|
|
pmp_addr_i[3][23] => ~NO_FANOUT~
|
|
pmp_addr_i[3][24] => ~NO_FANOUT~
|
|
pmp_addr_i[3][25] => ~NO_FANOUT~
|
|
pmp_addr_i[3][26] => ~NO_FANOUT~
|
|
pmp_addr_i[3][27] => ~NO_FANOUT~
|
|
pmp_addr_i[3][28] => ~NO_FANOUT~
|
|
pmp_addr_i[3][29] => ~NO_FANOUT~
|
|
pmp_addr_i[3][30] => ~NO_FANOUT~
|
|
pmp_addr_i[3][31] => ~NO_FANOUT~
|
|
pmp_addr_i[3][32] => ~NO_FANOUT~
|
|
pmp_addr_i[3][33] => ~NO_FANOUT~
|
|
pmp_addr_i[2][0] => ~NO_FANOUT~
|
|
pmp_addr_i[2][1] => ~NO_FANOUT~
|
|
pmp_addr_i[2][2] => ~NO_FANOUT~
|
|
pmp_addr_i[2][3] => ~NO_FANOUT~
|
|
pmp_addr_i[2][4] => ~NO_FANOUT~
|
|
pmp_addr_i[2][5] => ~NO_FANOUT~
|
|
pmp_addr_i[2][6] => ~NO_FANOUT~
|
|
pmp_addr_i[2][7] => ~NO_FANOUT~
|
|
pmp_addr_i[2][8] => ~NO_FANOUT~
|
|
pmp_addr_i[2][9] => ~NO_FANOUT~
|
|
pmp_addr_i[2][10] => ~NO_FANOUT~
|
|
pmp_addr_i[2][11] => ~NO_FANOUT~
|
|
pmp_addr_i[2][12] => ~NO_FANOUT~
|
|
pmp_addr_i[2][13] => ~NO_FANOUT~
|
|
pmp_addr_i[2][14] => ~NO_FANOUT~
|
|
pmp_addr_i[2][15] => ~NO_FANOUT~
|
|
pmp_addr_i[2][16] => ~NO_FANOUT~
|
|
pmp_addr_i[2][17] => ~NO_FANOUT~
|
|
pmp_addr_i[2][18] => ~NO_FANOUT~
|
|
pmp_addr_i[2][19] => ~NO_FANOUT~
|
|
pmp_addr_i[2][20] => ~NO_FANOUT~
|
|
pmp_addr_i[2][21] => ~NO_FANOUT~
|
|
pmp_addr_i[2][22] => ~NO_FANOUT~
|
|
pmp_addr_i[2][23] => ~NO_FANOUT~
|
|
pmp_addr_i[2][24] => ~NO_FANOUT~
|
|
pmp_addr_i[2][25] => ~NO_FANOUT~
|
|
pmp_addr_i[2][26] => ~NO_FANOUT~
|
|
pmp_addr_i[2][27] => ~NO_FANOUT~
|
|
pmp_addr_i[2][28] => ~NO_FANOUT~
|
|
pmp_addr_i[2][29] => ~NO_FANOUT~
|
|
pmp_addr_i[2][30] => ~NO_FANOUT~
|
|
pmp_addr_i[2][31] => ~NO_FANOUT~
|
|
pmp_addr_i[2][32] => ~NO_FANOUT~
|
|
pmp_addr_i[2][33] => ~NO_FANOUT~
|
|
pmp_addr_i[1][0] => ~NO_FANOUT~
|
|
pmp_addr_i[1][1] => ~NO_FANOUT~
|
|
pmp_addr_i[1][2] => ~NO_FANOUT~
|
|
pmp_addr_i[1][3] => ~NO_FANOUT~
|
|
pmp_addr_i[1][4] => ~NO_FANOUT~
|
|
pmp_addr_i[1][5] => ~NO_FANOUT~
|
|
pmp_addr_i[1][6] => ~NO_FANOUT~
|
|
pmp_addr_i[1][7] => ~NO_FANOUT~
|
|
pmp_addr_i[1][8] => ~NO_FANOUT~
|
|
pmp_addr_i[1][9] => ~NO_FANOUT~
|
|
pmp_addr_i[1][10] => ~NO_FANOUT~
|
|
pmp_addr_i[1][11] => ~NO_FANOUT~
|
|
pmp_addr_i[1][12] => ~NO_FANOUT~
|
|
pmp_addr_i[1][13] => ~NO_FANOUT~
|
|
pmp_addr_i[1][14] => ~NO_FANOUT~
|
|
pmp_addr_i[1][15] => ~NO_FANOUT~
|
|
pmp_addr_i[1][16] => ~NO_FANOUT~
|
|
pmp_addr_i[1][17] => ~NO_FANOUT~
|
|
pmp_addr_i[1][18] => ~NO_FANOUT~
|
|
pmp_addr_i[1][19] => ~NO_FANOUT~
|
|
pmp_addr_i[1][20] => ~NO_FANOUT~
|
|
pmp_addr_i[1][21] => ~NO_FANOUT~
|
|
pmp_addr_i[1][22] => ~NO_FANOUT~
|
|
pmp_addr_i[1][23] => ~NO_FANOUT~
|
|
pmp_addr_i[1][24] => ~NO_FANOUT~
|
|
pmp_addr_i[1][25] => ~NO_FANOUT~
|
|
pmp_addr_i[1][26] => ~NO_FANOUT~
|
|
pmp_addr_i[1][27] => ~NO_FANOUT~
|
|
pmp_addr_i[1][28] => ~NO_FANOUT~
|
|
pmp_addr_i[1][29] => ~NO_FANOUT~
|
|
pmp_addr_i[1][30] => ~NO_FANOUT~
|
|
pmp_addr_i[1][31] => ~NO_FANOUT~
|
|
pmp_addr_i[1][32] => ~NO_FANOUT~
|
|
pmp_addr_i[1][33] => ~NO_FANOUT~
|
|
pmp_addr_i[0][0] => ~NO_FANOUT~
|
|
pmp_addr_i[0][1] => ~NO_FANOUT~
|
|
pmp_addr_i[0][2] => ~NO_FANOUT~
|
|
pmp_addr_i[0][3] => ~NO_FANOUT~
|
|
pmp_addr_i[0][4] => ~NO_FANOUT~
|
|
pmp_addr_i[0][5] => ~NO_FANOUT~
|
|
pmp_addr_i[0][6] => ~NO_FANOUT~
|
|
pmp_addr_i[0][7] => ~NO_FANOUT~
|
|
pmp_addr_i[0][8] => ~NO_FANOUT~
|
|
pmp_addr_i[0][9] => ~NO_FANOUT~
|
|
pmp_addr_i[0][10] => ~NO_FANOUT~
|
|
pmp_addr_i[0][11] => ~NO_FANOUT~
|
|
pmp_addr_i[0][12] => ~NO_FANOUT~
|
|
pmp_addr_i[0][13] => ~NO_FANOUT~
|
|
pmp_addr_i[0][14] => ~NO_FANOUT~
|
|
pmp_addr_i[0][15] => ~NO_FANOUT~
|
|
pmp_addr_i[0][16] => ~NO_FANOUT~
|
|
pmp_addr_i[0][17] => ~NO_FANOUT~
|
|
pmp_addr_i[0][18] => ~NO_FANOUT~
|
|
pmp_addr_i[0][19] => ~NO_FANOUT~
|
|
pmp_addr_i[0][20] => ~NO_FANOUT~
|
|
pmp_addr_i[0][21] => ~NO_FANOUT~
|
|
pmp_addr_i[0][22] => ~NO_FANOUT~
|
|
pmp_addr_i[0][23] => ~NO_FANOUT~
|
|
pmp_addr_i[0][24] => ~NO_FANOUT~
|
|
pmp_addr_i[0][25] => ~NO_FANOUT~
|
|
pmp_addr_i[0][26] => ~NO_FANOUT~
|
|
pmp_addr_i[0][27] => ~NO_FANOUT~
|
|
pmp_addr_i[0][28] => ~NO_FANOUT~
|
|
pmp_addr_i[0][29] => ~NO_FANOUT~
|
|
pmp_addr_i[0][30] => ~NO_FANOUT~
|
|
pmp_addr_i[0][31] => ~NO_FANOUT~
|
|
pmp_addr_i[0][32] => ~NO_FANOUT~
|
|
pmp_addr_i[0][33] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[15][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[14][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[13][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[12][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[11][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[10][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[9][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[8][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[7][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[6][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[5][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[4][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[3][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[2][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[1][7] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][0] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][1] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][2] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][3] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][4] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][5] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][6] => ~NO_FANOUT~
|
|
pmp_ctrl_i[0][7] => ~NO_FANOUT~
|
|
d_bus_addr_o[0] <= mar[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[1] <= mar[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[2] <= mar[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[3] <= mar[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[4] <= mar[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[5] <= mar[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[6] <= mar[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[7] <= mar[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[8] <= mar[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[9] <= mar[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[10] <= mar[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[11] <= mar[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[12] <= mar[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[13] <= mar[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[14] <= mar[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[15] <= mar[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[16] <= mar[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[17] <= mar[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[18] <= mar[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[19] <= mar[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[20] <= mar[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[21] <= mar[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[22] <= mar[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[23] <= mar[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[24] <= mar[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[25] <= mar[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[26] <= mar[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[27] <= mar[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[28] <= mar[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[29] <= mar[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[30] <= mar[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_addr_o[31] <= mar[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_rdata_i[0] => Mux29.IN3
|
|
d_bus_rdata_i[0] => rdata_o.DATAB
|
|
d_bus_rdata_i[0] => Mux61.IN4
|
|
d_bus_rdata_i[0] => Mux61.IN5
|
|
d_bus_rdata_i[1] => Mux28.IN3
|
|
d_bus_rdata_i[1] => rdata_o.DATAB
|
|
d_bus_rdata_i[1] => Mux60.IN4
|
|
d_bus_rdata_i[1] => Mux60.IN5
|
|
d_bus_rdata_i[2] => Mux27.IN3
|
|
d_bus_rdata_i[2] => rdata_o.DATAB
|
|
d_bus_rdata_i[2] => Mux59.IN4
|
|
d_bus_rdata_i[2] => Mux59.IN5
|
|
d_bus_rdata_i[3] => Mux26.IN3
|
|
d_bus_rdata_i[3] => rdata_o.DATAB
|
|
d_bus_rdata_i[3] => Mux58.IN4
|
|
d_bus_rdata_i[3] => Mux58.IN5
|
|
d_bus_rdata_i[4] => Mux25.IN3
|
|
d_bus_rdata_i[4] => rdata_o.DATAB
|
|
d_bus_rdata_i[4] => Mux57.IN4
|
|
d_bus_rdata_i[4] => Mux57.IN5
|
|
d_bus_rdata_i[5] => Mux24.IN3
|
|
d_bus_rdata_i[5] => rdata_o.DATAB
|
|
d_bus_rdata_i[5] => Mux56.IN4
|
|
d_bus_rdata_i[5] => Mux56.IN5
|
|
d_bus_rdata_i[6] => Mux23.IN3
|
|
d_bus_rdata_i[6] => rdata_o.DATAB
|
|
d_bus_rdata_i[6] => Mux55.IN4
|
|
d_bus_rdata_i[6] => Mux55.IN5
|
|
d_bus_rdata_i[7] => Mux22.IN3
|
|
d_bus_rdata_i[7] => rdata_o.DATAB
|
|
d_bus_rdata_i[7] => Mux54.IN4
|
|
d_bus_rdata_i[7] => Mux54.IN5
|
|
d_bus_rdata_i[7] => Mux21.IN3
|
|
d_bus_rdata_i[8] => Mux29.IN2
|
|
d_bus_rdata_i[8] => rdata_o.DATAB
|
|
d_bus_rdata_i[8] => Mux53.IN4
|
|
d_bus_rdata_i[8] => Mux53.IN5
|
|
d_bus_rdata_i[9] => Mux28.IN2
|
|
d_bus_rdata_i[9] => rdata_o.DATAB
|
|
d_bus_rdata_i[9] => Mux52.IN4
|
|
d_bus_rdata_i[9] => Mux52.IN5
|
|
d_bus_rdata_i[10] => Mux27.IN2
|
|
d_bus_rdata_i[10] => rdata_o.DATAB
|
|
d_bus_rdata_i[10] => Mux51.IN4
|
|
d_bus_rdata_i[10] => Mux51.IN5
|
|
d_bus_rdata_i[11] => Mux26.IN2
|
|
d_bus_rdata_i[11] => rdata_o.DATAB
|
|
d_bus_rdata_i[11] => Mux50.IN4
|
|
d_bus_rdata_i[11] => Mux50.IN5
|
|
d_bus_rdata_i[12] => Mux25.IN2
|
|
d_bus_rdata_i[12] => rdata_o.DATAB
|
|
d_bus_rdata_i[12] => Mux49.IN4
|
|
d_bus_rdata_i[12] => Mux49.IN5
|
|
d_bus_rdata_i[13] => Mux24.IN2
|
|
d_bus_rdata_i[13] => rdata_o.DATAB
|
|
d_bus_rdata_i[13] => Mux48.IN4
|
|
d_bus_rdata_i[13] => Mux48.IN5
|
|
d_bus_rdata_i[14] => Mux23.IN2
|
|
d_bus_rdata_i[14] => rdata_o.DATAB
|
|
d_bus_rdata_i[14] => Mux47.IN4
|
|
d_bus_rdata_i[14] => Mux47.IN5
|
|
d_bus_rdata_i[15] => Mux22.IN2
|
|
d_bus_rdata_i[15] => rdata_o.IN1
|
|
d_bus_rdata_i[15] => rdata_o.DATAB
|
|
d_bus_rdata_i[15] => Mux46.IN4
|
|
d_bus_rdata_i[15] => Mux46.IN5
|
|
d_bus_rdata_i[15] => Mux21.IN2
|
|
d_bus_rdata_i[16] => Mux29.IN1
|
|
d_bus_rdata_i[16] => rdata_o.DATAA
|
|
d_bus_rdata_i[16] => Mux45.IN4
|
|
d_bus_rdata_i[16] => Mux45.IN5
|
|
d_bus_rdata_i[17] => Mux28.IN1
|
|
d_bus_rdata_i[17] => rdata_o.DATAA
|
|
d_bus_rdata_i[17] => Mux44.IN4
|
|
d_bus_rdata_i[17] => Mux44.IN5
|
|
d_bus_rdata_i[18] => Mux27.IN1
|
|
d_bus_rdata_i[18] => rdata_o.DATAA
|
|
d_bus_rdata_i[18] => Mux43.IN4
|
|
d_bus_rdata_i[18] => Mux43.IN5
|
|
d_bus_rdata_i[19] => Mux26.IN1
|
|
d_bus_rdata_i[19] => rdata_o.DATAA
|
|
d_bus_rdata_i[19] => Mux42.IN4
|
|
d_bus_rdata_i[19] => Mux42.IN5
|
|
d_bus_rdata_i[20] => Mux25.IN1
|
|
d_bus_rdata_i[20] => rdata_o.DATAA
|
|
d_bus_rdata_i[20] => Mux41.IN4
|
|
d_bus_rdata_i[20] => Mux41.IN5
|
|
d_bus_rdata_i[21] => Mux24.IN1
|
|
d_bus_rdata_i[21] => rdata_o.DATAA
|
|
d_bus_rdata_i[21] => Mux40.IN4
|
|
d_bus_rdata_i[21] => Mux40.IN5
|
|
d_bus_rdata_i[22] => Mux23.IN1
|
|
d_bus_rdata_i[22] => rdata_o.DATAA
|
|
d_bus_rdata_i[22] => Mux39.IN4
|
|
d_bus_rdata_i[22] => Mux39.IN5
|
|
d_bus_rdata_i[23] => Mux22.IN1
|
|
d_bus_rdata_i[23] => rdata_o.DATAA
|
|
d_bus_rdata_i[23] => Mux38.IN4
|
|
d_bus_rdata_i[23] => Mux38.IN5
|
|
d_bus_rdata_i[23] => Mux21.IN1
|
|
d_bus_rdata_i[24] => Mux29.IN0
|
|
d_bus_rdata_i[24] => rdata_o.DATAA
|
|
d_bus_rdata_i[24] => Mux37.IN4
|
|
d_bus_rdata_i[24] => Mux37.IN5
|
|
d_bus_rdata_i[25] => Mux28.IN0
|
|
d_bus_rdata_i[25] => rdata_o.DATAA
|
|
d_bus_rdata_i[25] => Mux36.IN4
|
|
d_bus_rdata_i[25] => Mux36.IN5
|
|
d_bus_rdata_i[26] => Mux27.IN0
|
|
d_bus_rdata_i[26] => rdata_o.DATAA
|
|
d_bus_rdata_i[26] => Mux35.IN4
|
|
d_bus_rdata_i[26] => Mux35.IN5
|
|
d_bus_rdata_i[27] => Mux26.IN0
|
|
d_bus_rdata_i[27] => rdata_o.DATAA
|
|
d_bus_rdata_i[27] => Mux34.IN4
|
|
d_bus_rdata_i[27] => Mux34.IN5
|
|
d_bus_rdata_i[28] => Mux25.IN0
|
|
d_bus_rdata_i[28] => rdata_o.DATAA
|
|
d_bus_rdata_i[28] => Mux33.IN4
|
|
d_bus_rdata_i[28] => Mux33.IN5
|
|
d_bus_rdata_i[29] => Mux24.IN0
|
|
d_bus_rdata_i[29] => rdata_o.DATAA
|
|
d_bus_rdata_i[29] => Mux32.IN4
|
|
d_bus_rdata_i[29] => Mux32.IN5
|
|
d_bus_rdata_i[30] => Mux23.IN0
|
|
d_bus_rdata_i[30] => rdata_o.DATAA
|
|
d_bus_rdata_i[30] => Mux31.IN4
|
|
d_bus_rdata_i[30] => Mux31.IN5
|
|
d_bus_rdata_i[31] => Mux22.IN0
|
|
d_bus_rdata_i[31] => rdata_o.IN1
|
|
d_bus_rdata_i[31] => rdata_o.DATAA
|
|
d_bus_rdata_i[31] => Mux30.IN4
|
|
d_bus_rdata_i[31] => Mux30.IN5
|
|
d_bus_rdata_i[31] => Mux21.IN0
|
|
d_bus_wdata_o[0] <= d_bus_wdata_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[1] <= d_bus_wdata_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[2] <= d_bus_wdata_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[3] <= d_bus_wdata_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[4] <= d_bus_wdata_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[5] <= d_bus_wdata_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[6] <= d_bus_wdata_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[7] <= d_bus_wdata_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[8] <= d_bus_wdata_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[9] <= d_bus_wdata_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[10] <= d_bus_wdata_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[11] <= d_bus_wdata_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[12] <= d_bus_wdata_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[13] <= d_bus_wdata_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[14] <= d_bus_wdata_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[15] <= d_bus_wdata_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[16] <= d_bus_wdata_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[17] <= d_bus_wdata_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[18] <= d_bus_wdata_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[19] <= d_bus_wdata_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[20] <= d_bus_wdata_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[21] <= d_bus_wdata_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[22] <= d_bus_wdata_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[23] <= d_bus_wdata_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[24] <= d_bus_wdata_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[25] <= d_bus_wdata_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[26] <= d_bus_wdata_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[27] <= d_bus_wdata_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[28] <= d_bus_wdata_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[29] <= d_bus_wdata_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[30] <= d_bus_wdata_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_wdata_o[31] <= d_bus_wdata_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_ben_o[0] <= d_bus_ben_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_ben_o[1] <= d_bus_ben_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_ben_o[2] <= d_bus_ben_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_ben_o[3] <= d_bus_ben_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_we_o <= d_bus_we_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_re_o <= d_bus_re_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_ack_i => data_access_arbiter.IN1
|
|
d_bus_ack_i => d_wait_o.DATAIN
|
|
d_bus_err_i => data_access_arbiter.IN1
|
|
d_bus_fence_o <= ctrl_i[40].DB_MAX_OUTPUT_PORT_TYPE
|
|
d_bus_priv_o <= ctrl_i[42].DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_busswitch:neorv32_busswitch_inst
|
|
clk_i => cb_wr_req_buf.CLK
|
|
clk_i => cb_rd_req_buf.CLK
|
|
clk_i => ca_wr_req_buf.CLK
|
|
clk_i => ca_rd_req_buf.CLK
|
|
clk_i => arbiter.state~1.DATAIN
|
|
rstn_i => cb_wr_req_buf.ACLR
|
|
rstn_i => cb_rd_req_buf.ACLR
|
|
rstn_i => ca_wr_req_buf.ACLR
|
|
rstn_i => ca_rd_req_buf.ACLR
|
|
rstn_i => arbiter.state~3.DATAIN
|
|
ca_bus_priv_i => p_bus_priv_o.DATAB
|
|
ca_bus_cached_i => p_bus_cached_o.DATAB
|
|
ca_bus_addr_i[0] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[1] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[2] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[3] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[4] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[5] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[6] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[7] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[8] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[9] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[10] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[11] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[12] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[13] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[14] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[15] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[16] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[17] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[18] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[19] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[20] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[21] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[22] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[23] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[24] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[25] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[26] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[27] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[28] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[29] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[30] => p_bus_addr_o.DATAB
|
|
ca_bus_addr_i[31] => p_bus_addr_o.DATAB
|
|
ca_bus_rdata_o[0] <= p_bus_rdata_i[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[1] <= p_bus_rdata_i[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[2] <= p_bus_rdata_i[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[3] <= p_bus_rdata_i[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[4] <= p_bus_rdata_i[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[5] <= p_bus_rdata_i[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[6] <= p_bus_rdata_i[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[7] <= p_bus_rdata_i[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[8] <= p_bus_rdata_i[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[9] <= p_bus_rdata_i[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[10] <= p_bus_rdata_i[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[11] <= p_bus_rdata_i[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[12] <= p_bus_rdata_i[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[13] <= p_bus_rdata_i[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[14] <= p_bus_rdata_i[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[15] <= p_bus_rdata_i[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[16] <= p_bus_rdata_i[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[17] <= p_bus_rdata_i[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[18] <= p_bus_rdata_i[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[19] <= p_bus_rdata_i[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[20] <= p_bus_rdata_i[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[21] <= p_bus_rdata_i[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[22] <= p_bus_rdata_i[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[23] <= p_bus_rdata_i[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[24] <= p_bus_rdata_i[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[25] <= p_bus_rdata_i[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[26] <= p_bus_rdata_i[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[27] <= p_bus_rdata_i[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[28] <= p_bus_rdata_i[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[29] <= p_bus_rdata_i[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[30] <= p_bus_rdata_i[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_rdata_o[31] <= p_bus_rdata_i[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_wdata_i[0] => p_bus_wdata_o[0].DATAIN
|
|
ca_bus_wdata_i[1] => p_bus_wdata_o[1].DATAIN
|
|
ca_bus_wdata_i[2] => p_bus_wdata_o[2].DATAIN
|
|
ca_bus_wdata_i[3] => p_bus_wdata_o[3].DATAIN
|
|
ca_bus_wdata_i[4] => p_bus_wdata_o[4].DATAIN
|
|
ca_bus_wdata_i[5] => p_bus_wdata_o[5].DATAIN
|
|
ca_bus_wdata_i[6] => p_bus_wdata_o[6].DATAIN
|
|
ca_bus_wdata_i[7] => p_bus_wdata_o[7].DATAIN
|
|
ca_bus_wdata_i[8] => p_bus_wdata_o[8].DATAIN
|
|
ca_bus_wdata_i[9] => p_bus_wdata_o[9].DATAIN
|
|
ca_bus_wdata_i[10] => p_bus_wdata_o[10].DATAIN
|
|
ca_bus_wdata_i[11] => p_bus_wdata_o[11].DATAIN
|
|
ca_bus_wdata_i[12] => p_bus_wdata_o[12].DATAIN
|
|
ca_bus_wdata_i[13] => p_bus_wdata_o[13].DATAIN
|
|
ca_bus_wdata_i[14] => p_bus_wdata_o[14].DATAIN
|
|
ca_bus_wdata_i[15] => p_bus_wdata_o[15].DATAIN
|
|
ca_bus_wdata_i[16] => p_bus_wdata_o[16].DATAIN
|
|
ca_bus_wdata_i[17] => p_bus_wdata_o[17].DATAIN
|
|
ca_bus_wdata_i[18] => p_bus_wdata_o[18].DATAIN
|
|
ca_bus_wdata_i[19] => p_bus_wdata_o[19].DATAIN
|
|
ca_bus_wdata_i[20] => p_bus_wdata_o[20].DATAIN
|
|
ca_bus_wdata_i[21] => p_bus_wdata_o[21].DATAIN
|
|
ca_bus_wdata_i[22] => p_bus_wdata_o[22].DATAIN
|
|
ca_bus_wdata_i[23] => p_bus_wdata_o[23].DATAIN
|
|
ca_bus_wdata_i[24] => p_bus_wdata_o[24].DATAIN
|
|
ca_bus_wdata_i[25] => p_bus_wdata_o[25].DATAIN
|
|
ca_bus_wdata_i[26] => p_bus_wdata_o[26].DATAIN
|
|
ca_bus_wdata_i[27] => p_bus_wdata_o[27].DATAIN
|
|
ca_bus_wdata_i[28] => p_bus_wdata_o[28].DATAIN
|
|
ca_bus_wdata_i[29] => p_bus_wdata_o[29].DATAIN
|
|
ca_bus_wdata_i[30] => p_bus_wdata_o[30].DATAIN
|
|
ca_bus_wdata_i[31] => p_bus_wdata_o[31].DATAIN
|
|
ca_bus_ben_i[0] => p_bus_ben_o[0].DATAIN
|
|
ca_bus_ben_i[1] => p_bus_ben_o[1].DATAIN
|
|
ca_bus_ben_i[2] => p_bus_ben_o[2].DATAIN
|
|
ca_bus_ben_i[3] => p_bus_ben_o[3].DATAIN
|
|
ca_bus_we_i => ca_wr_req_buf.IN1
|
|
ca_bus_we_i => ca_req_current.IN0
|
|
ca_bus_we_i => p_bus_we.DATAB
|
|
ca_bus_re_i => ca_rd_req_buf.IN1
|
|
ca_bus_re_i => ca_req_current.IN1
|
|
ca_bus_re_i => p_bus_re.DATAB
|
|
ca_bus_ack_o <= ca_bus_ack.DB_MAX_OUTPUT_PORT_TYPE
|
|
ca_bus_err_o <= ca_bus_err.DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_priv_i => p_bus_priv_o.DATAA
|
|
cb_bus_cached_i => p_bus_cached_o.DATAA
|
|
cb_bus_addr_i[0] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[1] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[2] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[3] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[4] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[5] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[6] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[7] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[8] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[9] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[10] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[11] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[12] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[13] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[14] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[15] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[16] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[17] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[18] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[19] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[20] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[21] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[22] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[23] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[24] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[25] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[26] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[27] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[28] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[29] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[30] => p_bus_addr_o.DATAA
|
|
cb_bus_addr_i[31] => p_bus_addr_o.DATAA
|
|
cb_bus_rdata_o[0] <= p_bus_rdata_i[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[1] <= p_bus_rdata_i[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[2] <= p_bus_rdata_i[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[3] <= p_bus_rdata_i[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[4] <= p_bus_rdata_i[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[5] <= p_bus_rdata_i[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[6] <= p_bus_rdata_i[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[7] <= p_bus_rdata_i[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[8] <= p_bus_rdata_i[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[9] <= p_bus_rdata_i[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[10] <= p_bus_rdata_i[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[11] <= p_bus_rdata_i[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[12] <= p_bus_rdata_i[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[13] <= p_bus_rdata_i[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[14] <= p_bus_rdata_i[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[15] <= p_bus_rdata_i[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[16] <= p_bus_rdata_i[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[17] <= p_bus_rdata_i[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[18] <= p_bus_rdata_i[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[19] <= p_bus_rdata_i[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[20] <= p_bus_rdata_i[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[21] <= p_bus_rdata_i[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[22] <= p_bus_rdata_i[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[23] <= p_bus_rdata_i[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[24] <= p_bus_rdata_i[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[25] <= p_bus_rdata_i[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[26] <= p_bus_rdata_i[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[27] <= p_bus_rdata_i[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[28] <= p_bus_rdata_i[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[29] <= p_bus_rdata_i[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[30] <= p_bus_rdata_i[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_rdata_o[31] <= p_bus_rdata_i[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_wdata_i[0] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[1] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[2] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[3] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[4] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[5] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[6] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[7] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[8] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[9] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[10] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[11] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[12] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[13] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[14] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[15] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[16] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[17] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[18] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[19] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[20] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[21] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[22] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[23] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[24] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[25] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[26] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[27] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[28] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[29] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[30] => ~NO_FANOUT~
|
|
cb_bus_wdata_i[31] => ~NO_FANOUT~
|
|
cb_bus_ben_i[0] => ~NO_FANOUT~
|
|
cb_bus_ben_i[1] => ~NO_FANOUT~
|
|
cb_bus_ben_i[2] => ~NO_FANOUT~
|
|
cb_bus_ben_i[3] => ~NO_FANOUT~
|
|
cb_bus_we_i => p_bus_we.DATAA
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => arbiter.OUTPUTSELECT
|
|
cb_bus_re_i => cb_rd_req_buf.IN1
|
|
cb_bus_re_i => p_bus_re.DATAA
|
|
cb_bus_ack_o <= cb_bus_ack.DB_MAX_OUTPUT_PORT_TYPE
|
|
cb_bus_err_o <= cb_bus_err.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_priv_o <= p_bus_priv_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_cached_o <= p_bus_cached_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_src_o <= Selector5.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[0] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[1] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[2] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[3] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[4] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[5] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[6] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[7] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[8] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[9] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[10] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[11] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[12] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[13] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[14] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[15] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[16] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[17] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[18] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[19] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[20] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[21] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[22] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[23] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[24] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[25] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[26] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[27] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[28] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[29] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[30] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_addr_o[31] <= p_bus_addr_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_rdata_i[0] => cb_bus_rdata_o[0].DATAIN
|
|
p_bus_rdata_i[0] => ca_bus_rdata_o[0].DATAIN
|
|
p_bus_rdata_i[1] => cb_bus_rdata_o[1].DATAIN
|
|
p_bus_rdata_i[1] => ca_bus_rdata_o[1].DATAIN
|
|
p_bus_rdata_i[2] => cb_bus_rdata_o[2].DATAIN
|
|
p_bus_rdata_i[2] => ca_bus_rdata_o[2].DATAIN
|
|
p_bus_rdata_i[3] => cb_bus_rdata_o[3].DATAIN
|
|
p_bus_rdata_i[3] => ca_bus_rdata_o[3].DATAIN
|
|
p_bus_rdata_i[4] => cb_bus_rdata_o[4].DATAIN
|
|
p_bus_rdata_i[4] => ca_bus_rdata_o[4].DATAIN
|
|
p_bus_rdata_i[5] => cb_bus_rdata_o[5].DATAIN
|
|
p_bus_rdata_i[5] => ca_bus_rdata_o[5].DATAIN
|
|
p_bus_rdata_i[6] => cb_bus_rdata_o[6].DATAIN
|
|
p_bus_rdata_i[6] => ca_bus_rdata_o[6].DATAIN
|
|
p_bus_rdata_i[7] => cb_bus_rdata_o[7].DATAIN
|
|
p_bus_rdata_i[7] => ca_bus_rdata_o[7].DATAIN
|
|
p_bus_rdata_i[8] => cb_bus_rdata_o[8].DATAIN
|
|
p_bus_rdata_i[8] => ca_bus_rdata_o[8].DATAIN
|
|
p_bus_rdata_i[9] => cb_bus_rdata_o[9].DATAIN
|
|
p_bus_rdata_i[9] => ca_bus_rdata_o[9].DATAIN
|
|
p_bus_rdata_i[10] => cb_bus_rdata_o[10].DATAIN
|
|
p_bus_rdata_i[10] => ca_bus_rdata_o[10].DATAIN
|
|
p_bus_rdata_i[11] => cb_bus_rdata_o[11].DATAIN
|
|
p_bus_rdata_i[11] => ca_bus_rdata_o[11].DATAIN
|
|
p_bus_rdata_i[12] => cb_bus_rdata_o[12].DATAIN
|
|
p_bus_rdata_i[12] => ca_bus_rdata_o[12].DATAIN
|
|
p_bus_rdata_i[13] => cb_bus_rdata_o[13].DATAIN
|
|
p_bus_rdata_i[13] => ca_bus_rdata_o[13].DATAIN
|
|
p_bus_rdata_i[14] => cb_bus_rdata_o[14].DATAIN
|
|
p_bus_rdata_i[14] => ca_bus_rdata_o[14].DATAIN
|
|
p_bus_rdata_i[15] => cb_bus_rdata_o[15].DATAIN
|
|
p_bus_rdata_i[15] => ca_bus_rdata_o[15].DATAIN
|
|
p_bus_rdata_i[16] => cb_bus_rdata_o[16].DATAIN
|
|
p_bus_rdata_i[16] => ca_bus_rdata_o[16].DATAIN
|
|
p_bus_rdata_i[17] => cb_bus_rdata_o[17].DATAIN
|
|
p_bus_rdata_i[17] => ca_bus_rdata_o[17].DATAIN
|
|
p_bus_rdata_i[18] => cb_bus_rdata_o[18].DATAIN
|
|
p_bus_rdata_i[18] => ca_bus_rdata_o[18].DATAIN
|
|
p_bus_rdata_i[19] => cb_bus_rdata_o[19].DATAIN
|
|
p_bus_rdata_i[19] => ca_bus_rdata_o[19].DATAIN
|
|
p_bus_rdata_i[20] => cb_bus_rdata_o[20].DATAIN
|
|
p_bus_rdata_i[20] => ca_bus_rdata_o[20].DATAIN
|
|
p_bus_rdata_i[21] => cb_bus_rdata_o[21].DATAIN
|
|
p_bus_rdata_i[21] => ca_bus_rdata_o[21].DATAIN
|
|
p_bus_rdata_i[22] => cb_bus_rdata_o[22].DATAIN
|
|
p_bus_rdata_i[22] => ca_bus_rdata_o[22].DATAIN
|
|
p_bus_rdata_i[23] => cb_bus_rdata_o[23].DATAIN
|
|
p_bus_rdata_i[23] => ca_bus_rdata_o[23].DATAIN
|
|
p_bus_rdata_i[24] => cb_bus_rdata_o[24].DATAIN
|
|
p_bus_rdata_i[24] => ca_bus_rdata_o[24].DATAIN
|
|
p_bus_rdata_i[25] => cb_bus_rdata_o[25].DATAIN
|
|
p_bus_rdata_i[25] => ca_bus_rdata_o[25].DATAIN
|
|
p_bus_rdata_i[26] => cb_bus_rdata_o[26].DATAIN
|
|
p_bus_rdata_i[26] => ca_bus_rdata_o[26].DATAIN
|
|
p_bus_rdata_i[27] => cb_bus_rdata_o[27].DATAIN
|
|
p_bus_rdata_i[27] => ca_bus_rdata_o[27].DATAIN
|
|
p_bus_rdata_i[28] => cb_bus_rdata_o[28].DATAIN
|
|
p_bus_rdata_i[28] => ca_bus_rdata_o[28].DATAIN
|
|
p_bus_rdata_i[29] => cb_bus_rdata_o[29].DATAIN
|
|
p_bus_rdata_i[29] => ca_bus_rdata_o[29].DATAIN
|
|
p_bus_rdata_i[30] => cb_bus_rdata_o[30].DATAIN
|
|
p_bus_rdata_i[30] => ca_bus_rdata_o[30].DATAIN
|
|
p_bus_rdata_i[31] => cb_bus_rdata_o[31].DATAIN
|
|
p_bus_rdata_i[31] => ca_bus_rdata_o[31].DATAIN
|
|
p_bus_wdata_o[0] <= ca_bus_wdata_i[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[1] <= ca_bus_wdata_i[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[2] <= ca_bus_wdata_i[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[3] <= ca_bus_wdata_i[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[4] <= ca_bus_wdata_i[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[5] <= ca_bus_wdata_i[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[6] <= ca_bus_wdata_i[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[7] <= ca_bus_wdata_i[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[8] <= ca_bus_wdata_i[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[9] <= ca_bus_wdata_i[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[10] <= ca_bus_wdata_i[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[11] <= ca_bus_wdata_i[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[12] <= ca_bus_wdata_i[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[13] <= ca_bus_wdata_i[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[14] <= ca_bus_wdata_i[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[15] <= ca_bus_wdata_i[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[16] <= ca_bus_wdata_i[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[17] <= ca_bus_wdata_i[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[18] <= ca_bus_wdata_i[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[19] <= ca_bus_wdata_i[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[20] <= ca_bus_wdata_i[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[21] <= ca_bus_wdata_i[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[22] <= ca_bus_wdata_i[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[23] <= ca_bus_wdata_i[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[24] <= ca_bus_wdata_i[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[25] <= ca_bus_wdata_i[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[26] <= ca_bus_wdata_i[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[27] <= ca_bus_wdata_i[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[28] <= ca_bus_wdata_i[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[29] <= ca_bus_wdata_i[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[30] <= ca_bus_wdata_i[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_wdata_o[31] <= ca_bus_wdata_i[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_ben_o[0] <= ca_bus_ben_i[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_ben_o[1] <= ca_bus_ben_i[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_ben_o[2] <= ca_bus_ben_i[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_ben_o[3] <= ca_bus_ben_i[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_we_o <= p_bus_we_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_re_o <= p_bus_re_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
p_bus_ack_i => arbiter_comb.IN0
|
|
p_bus_ack_i => ca_bus_ack.DATAB
|
|
p_bus_ack_i => cb_bus_ack.DATAB
|
|
p_bus_err_i => arbiter_comb.IN1
|
|
p_bus_err_i => ca_bus_err.DATAB
|
|
p_bus_err_i => cb_bus_err.DATAB
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_bus_keeper:neorv32_bus_keeper_inst
|
|
clk_i => control.ignore.CLK
|
|
clk_i => control.bus_err.CLK
|
|
clk_i => control.err_type.CLK
|
|
clk_i => control.timeout[0].CLK
|
|
clk_i => control.timeout[1].CLK
|
|
clk_i => control.timeout[2].CLK
|
|
clk_i => control.timeout[3].CLK
|
|
clk_i => control.pending.CLK
|
|
clk_i => data_o[0]~reg0.CLK
|
|
clk_i => data_o[1]~reg0.CLK
|
|
clk_i => data_o[2]~reg0.CLK
|
|
clk_i => data_o[3]~reg0.CLK
|
|
clk_i => data_o[4]~reg0.CLK
|
|
clk_i => data_o[5]~reg0.CLK
|
|
clk_i => data_o[6]~reg0.CLK
|
|
clk_i => data_o[7]~reg0.CLK
|
|
clk_i => data_o[8]~reg0.CLK
|
|
clk_i => data_o[9]~reg0.CLK
|
|
clk_i => data_o[10]~reg0.CLK
|
|
clk_i => data_o[11]~reg0.CLK
|
|
clk_i => data_o[12]~reg0.CLK
|
|
clk_i => data_o[13]~reg0.CLK
|
|
clk_i => data_o[14]~reg0.CLK
|
|
clk_i => data_o[15]~reg0.CLK
|
|
clk_i => data_o[16]~reg0.CLK
|
|
clk_i => data_o[17]~reg0.CLK
|
|
clk_i => data_o[18]~reg0.CLK
|
|
clk_i => data_o[19]~reg0.CLK
|
|
clk_i => data_o[20]~reg0.CLK
|
|
clk_i => data_o[21]~reg0.CLK
|
|
clk_i => data_o[22]~reg0.CLK
|
|
clk_i => data_o[23]~reg0.CLK
|
|
clk_i => data_o[24]~reg0.CLK
|
|
clk_i => data_o[25]~reg0.CLK
|
|
clk_i => data_o[26]~reg0.CLK
|
|
clk_i => data_o[27]~reg0.CLK
|
|
clk_i => data_o[28]~reg0.CLK
|
|
clk_i => data_o[29]~reg0.CLK
|
|
clk_i => data_o[30]~reg0.CLK
|
|
clk_i => data_o[31]~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => err_type.CLK
|
|
clk_i => err_flag.CLK
|
|
rstn_i => control.ignore.ACLR
|
|
rstn_i => control.bus_err.ACLR
|
|
rstn_i => control.err_type.ACLR
|
|
rstn_i => control.timeout[0].ACLR
|
|
rstn_i => control.timeout[1].ACLR
|
|
rstn_i => control.timeout[2].ACLR
|
|
rstn_i => control.timeout[3].ACLR
|
|
rstn_i => control.pending.ACLR
|
|
rstn_i => err_type.ACLR
|
|
rstn_i => err_flag.ACLR
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => ~NO_FANOUT~
|
|
addr_i[3] => Equal0.IN5
|
|
addr_i[4] => Equal0.IN4
|
|
addr_i[5] => Equal0.IN3
|
|
addr_i[6] => Equal0.IN2
|
|
addr_i[7] => Equal0.IN0
|
|
addr_i[8] => Equal0.IN1
|
|
addr_i[9] => ~NO_FANOUT~
|
|
addr_i[10] => ~NO_FANOUT~
|
|
addr_i[11] => ~NO_FANOUT~
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => ~NO_FANOUT~
|
|
addr_i[16] => ~NO_FANOUT~
|
|
addr_i[17] => ~NO_FANOUT~
|
|
addr_i[18] => ~NO_FANOUT~
|
|
addr_i[19] => ~NO_FANOUT~
|
|
addr_i[20] => ~NO_FANOUT~
|
|
addr_i[21] => ~NO_FANOUT~
|
|
addr_i[22] => ~NO_FANOUT~
|
|
addr_i[23] => ~NO_FANOUT~
|
|
addr_i[24] => ~NO_FANOUT~
|
|
addr_i[25] => ~NO_FANOUT~
|
|
addr_i[26] => ~NO_FANOUT~
|
|
addr_i[27] => ~NO_FANOUT~
|
|
addr_i[28] => ~NO_FANOUT~
|
|
addr_i[29] => ~NO_FANOUT~
|
|
addr_i[30] => ~NO_FANOUT~
|
|
addr_i[31] => ~NO_FANOUT~
|
|
rden_i => rden.IN1
|
|
wren_i => wren.IN1
|
|
data_i[0] => ~NO_FANOUT~
|
|
data_i[1] => ~NO_FANOUT~
|
|
data_i[2] => ~NO_FANOUT~
|
|
data_i[3] => ~NO_FANOUT~
|
|
data_i[4] => ~NO_FANOUT~
|
|
data_i[5] => ~NO_FANOUT~
|
|
data_i[6] => ~NO_FANOUT~
|
|
data_i[7] => ~NO_FANOUT~
|
|
data_i[8] => ~NO_FANOUT~
|
|
data_i[9] => ~NO_FANOUT~
|
|
data_i[10] => ~NO_FANOUT~
|
|
data_i[11] => ~NO_FANOUT~
|
|
data_i[12] => ~NO_FANOUT~
|
|
data_i[13] => ~NO_FANOUT~
|
|
data_i[14] => ~NO_FANOUT~
|
|
data_i[15] => ~NO_FANOUT~
|
|
data_i[16] => ~NO_FANOUT~
|
|
data_i[17] => ~NO_FANOUT~
|
|
data_i[18] => ~NO_FANOUT~
|
|
data_i[19] => ~NO_FANOUT~
|
|
data_i[20] => ~NO_FANOUT~
|
|
data_i[21] => ~NO_FANOUT~
|
|
data_i[22] => ~NO_FANOUT~
|
|
data_i[23] => ~NO_FANOUT~
|
|
data_i[24] => ~NO_FANOUT~
|
|
data_i[25] => ~NO_FANOUT~
|
|
data_i[26] => ~NO_FANOUT~
|
|
data_i[27] => ~NO_FANOUT~
|
|
data_i[28] => ~NO_FANOUT~
|
|
data_i[29] => ~NO_FANOUT~
|
|
data_i[30] => ~NO_FANOUT~
|
|
data_i[31] => ~NO_FANOUT~
|
|
data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
err_o <= control.bus_err.DB_MAX_OUTPUT_PORT_TYPE
|
|
bus_addr_i[0] => ~NO_FANOUT~
|
|
bus_addr_i[1] => ~NO_FANOUT~
|
|
bus_addr_i[2] => ~NO_FANOUT~
|
|
bus_addr_i[3] => ~NO_FANOUT~
|
|
bus_addr_i[4] => ~NO_FANOUT~
|
|
bus_addr_i[5] => ~NO_FANOUT~
|
|
bus_addr_i[6] => ~NO_FANOUT~
|
|
bus_addr_i[7] => ~NO_FANOUT~
|
|
bus_addr_i[8] => ~NO_FANOUT~
|
|
bus_addr_i[9] => ~NO_FANOUT~
|
|
bus_addr_i[10] => ~NO_FANOUT~
|
|
bus_addr_i[11] => ~NO_FANOUT~
|
|
bus_addr_i[12] => ~NO_FANOUT~
|
|
bus_addr_i[13] => ~NO_FANOUT~
|
|
bus_addr_i[14] => ~NO_FANOUT~
|
|
bus_addr_i[15] => ~NO_FANOUT~
|
|
bus_addr_i[16] => ~NO_FANOUT~
|
|
bus_addr_i[17] => ~NO_FANOUT~
|
|
bus_addr_i[18] => ~NO_FANOUT~
|
|
bus_addr_i[19] => ~NO_FANOUT~
|
|
bus_addr_i[20] => ~NO_FANOUT~
|
|
bus_addr_i[21] => ~NO_FANOUT~
|
|
bus_addr_i[22] => ~NO_FANOUT~
|
|
bus_addr_i[23] => ~NO_FANOUT~
|
|
bus_addr_i[24] => ~NO_FANOUT~
|
|
bus_addr_i[25] => ~NO_FANOUT~
|
|
bus_addr_i[26] => ~NO_FANOUT~
|
|
bus_addr_i[27] => ~NO_FANOUT~
|
|
bus_addr_i[28] => ~NO_FANOUT~
|
|
bus_addr_i[29] => ~NO_FANOUT~
|
|
bus_addr_i[30] => ~NO_FANOUT~
|
|
bus_addr_i[31] => ~NO_FANOUT~
|
|
bus_rden_i => keeper_control.IN0
|
|
bus_wren_i => keeper_control.IN1
|
|
bus_ack_i => control.OUTPUTSELECT
|
|
bus_ack_i => control.OUTPUTSELECT
|
|
bus_err_i => control.OUTPUTSELECT
|
|
bus_err_i => control.OUTPUTSELECT
|
|
bus_err_i => control.OUTPUTSELECT
|
|
bus_tmo_i => keeper_control.IN1
|
|
bus_ext_i => ignore.IN0
|
|
bus_xip_i => ignore.IN1
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_imem:\neorv32_int_imem_inst_true:neorv32_int_imem_inst
|
|
clk_i => mem_ram_b0~20.CLK
|
|
clk_i => mem_ram_b0~0.CLK
|
|
clk_i => mem_ram_b0~1.CLK
|
|
clk_i => mem_ram_b0~2.CLK
|
|
clk_i => mem_ram_b0~3.CLK
|
|
clk_i => mem_ram_b0~4.CLK
|
|
clk_i => mem_ram_b0~5.CLK
|
|
clk_i => mem_ram_b0~6.CLK
|
|
clk_i => mem_ram_b0~7.CLK
|
|
clk_i => mem_ram_b0~8.CLK
|
|
clk_i => mem_ram_b0~9.CLK
|
|
clk_i => mem_ram_b0~10.CLK
|
|
clk_i => mem_ram_b0~11.CLK
|
|
clk_i => mem_ram_b0~12.CLK
|
|
clk_i => mem_ram_b0~13.CLK
|
|
clk_i => mem_ram_b0~14.CLK
|
|
clk_i => mem_ram_b0~15.CLK
|
|
clk_i => mem_ram_b0~16.CLK
|
|
clk_i => mem_ram_b0~17.CLK
|
|
clk_i => mem_ram_b0~18.CLK
|
|
clk_i => mem_ram_b0~19.CLK
|
|
clk_i => mem_ram_b1~0.CLK
|
|
clk_i => mem_ram_b1~1.CLK
|
|
clk_i => mem_ram_b1~2.CLK
|
|
clk_i => mem_ram_b1~3.CLK
|
|
clk_i => mem_ram_b1~4.CLK
|
|
clk_i => mem_ram_b1~5.CLK
|
|
clk_i => mem_ram_b1~6.CLK
|
|
clk_i => mem_ram_b1~7.CLK
|
|
clk_i => mem_ram_b1~8.CLK
|
|
clk_i => mem_ram_b1~9.CLK
|
|
clk_i => mem_ram_b1~10.CLK
|
|
clk_i => mem_ram_b1~11.CLK
|
|
clk_i => mem_ram_b1~12.CLK
|
|
clk_i => mem_ram_b1~13.CLK
|
|
clk_i => mem_ram_b1~14.CLK
|
|
clk_i => mem_ram_b1~15.CLK
|
|
clk_i => mem_ram_b1~16.CLK
|
|
clk_i => mem_ram_b1~17.CLK
|
|
clk_i => mem_ram_b1~18.CLK
|
|
clk_i => mem_ram_b1~19.CLK
|
|
clk_i => mem_ram_b1~20.CLK
|
|
clk_i => mem_ram_b2~0.CLK
|
|
clk_i => mem_ram_b2~1.CLK
|
|
clk_i => mem_ram_b2~2.CLK
|
|
clk_i => mem_ram_b2~3.CLK
|
|
clk_i => mem_ram_b2~4.CLK
|
|
clk_i => mem_ram_b2~5.CLK
|
|
clk_i => mem_ram_b2~6.CLK
|
|
clk_i => mem_ram_b2~7.CLK
|
|
clk_i => mem_ram_b2~8.CLK
|
|
clk_i => mem_ram_b2~9.CLK
|
|
clk_i => mem_ram_b2~10.CLK
|
|
clk_i => mem_ram_b2~11.CLK
|
|
clk_i => mem_ram_b2~12.CLK
|
|
clk_i => mem_ram_b2~13.CLK
|
|
clk_i => mem_ram_b2~14.CLK
|
|
clk_i => mem_ram_b2~15.CLK
|
|
clk_i => mem_ram_b2~16.CLK
|
|
clk_i => mem_ram_b2~17.CLK
|
|
clk_i => mem_ram_b2~18.CLK
|
|
clk_i => mem_ram_b2~19.CLK
|
|
clk_i => mem_ram_b2~20.CLK
|
|
clk_i => mem_ram_b3~0.CLK
|
|
clk_i => mem_ram_b3~1.CLK
|
|
clk_i => mem_ram_b3~2.CLK
|
|
clk_i => mem_ram_b3~3.CLK
|
|
clk_i => mem_ram_b3~4.CLK
|
|
clk_i => mem_ram_b3~5.CLK
|
|
clk_i => mem_ram_b3~6.CLK
|
|
clk_i => mem_ram_b3~7.CLK
|
|
clk_i => mem_ram_b3~8.CLK
|
|
clk_i => mem_ram_b3~9.CLK
|
|
clk_i => mem_ram_b3~10.CLK
|
|
clk_i => mem_ram_b3~11.CLK
|
|
clk_i => mem_ram_b3~12.CLK
|
|
clk_i => mem_ram_b3~13.CLK
|
|
clk_i => mem_ram_b3~14.CLK
|
|
clk_i => mem_ram_b3~15.CLK
|
|
clk_i => mem_ram_b3~16.CLK
|
|
clk_i => mem_ram_b3~17.CLK
|
|
clk_i => mem_ram_b3~18.CLK
|
|
clk_i => mem_ram_b3~19.CLK
|
|
clk_i => mem_ram_b3~20.CLK
|
|
clk_i => err_o~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => rden.CLK
|
|
clk_i => mem_b3_rd[0].CLK
|
|
clk_i => mem_b3_rd[1].CLK
|
|
clk_i => mem_b3_rd[2].CLK
|
|
clk_i => mem_b3_rd[3].CLK
|
|
clk_i => mem_b3_rd[4].CLK
|
|
clk_i => mem_b3_rd[5].CLK
|
|
clk_i => mem_b3_rd[6].CLK
|
|
clk_i => mem_b3_rd[7].CLK
|
|
clk_i => mem_b2_rd[0].CLK
|
|
clk_i => mem_b2_rd[1].CLK
|
|
clk_i => mem_b2_rd[2].CLK
|
|
clk_i => mem_b2_rd[3].CLK
|
|
clk_i => mem_b2_rd[4].CLK
|
|
clk_i => mem_b2_rd[5].CLK
|
|
clk_i => mem_b2_rd[6].CLK
|
|
clk_i => mem_b2_rd[7].CLK
|
|
clk_i => mem_b1_rd[0].CLK
|
|
clk_i => mem_b1_rd[1].CLK
|
|
clk_i => mem_b1_rd[2].CLK
|
|
clk_i => mem_b1_rd[3].CLK
|
|
clk_i => mem_b1_rd[4].CLK
|
|
clk_i => mem_b1_rd[5].CLK
|
|
clk_i => mem_b1_rd[6].CLK
|
|
clk_i => mem_b1_rd[7].CLK
|
|
clk_i => mem_b0_rd[0].CLK
|
|
clk_i => mem_b0_rd[1].CLK
|
|
clk_i => mem_b0_rd[2].CLK
|
|
clk_i => mem_b0_rd[3].CLK
|
|
clk_i => mem_b0_rd[4].CLK
|
|
clk_i => mem_b0_rd[5].CLK
|
|
clk_i => mem_b0_rd[6].CLK
|
|
clk_i => mem_b0_rd[7].CLK
|
|
clk_i => mem_ram_b0.CLK0
|
|
clk_i => mem_ram_b1.CLK0
|
|
clk_i => mem_ram_b2.CLK0
|
|
clk_i => mem_ram_b3.CLK0
|
|
rden_i => rden.IN1
|
|
rden_i => ack_o.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => ack_o.IN1
|
|
ben_i[0] => mem_access.IN1
|
|
ben_i[1] => mem_access.IN1
|
|
ben_i[2] => mem_access.IN1
|
|
ben_i[3] => mem_access.IN1
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => mem_ram_b0~11.DATAIN
|
|
addr_i[2] => mem_ram_b1~12.DATAIN
|
|
addr_i[2] => mem_ram_b2~12.DATAIN
|
|
addr_i[2] => mem_ram_b3~12.DATAIN
|
|
addr_i[2] => mem_ram_b0.WADDR
|
|
addr_i[2] => mem_ram_b0.RADDR
|
|
addr_i[2] => mem_ram_b1.WADDR
|
|
addr_i[2] => mem_ram_b1.RADDR
|
|
addr_i[2] => mem_ram_b2.WADDR
|
|
addr_i[2] => mem_ram_b2.RADDR
|
|
addr_i[2] => mem_ram_b3.WADDR
|
|
addr_i[2] => mem_ram_b3.RADDR
|
|
addr_i[3] => mem_ram_b0~10.DATAIN
|
|
addr_i[3] => mem_ram_b1~11.DATAIN
|
|
addr_i[3] => mem_ram_b2~11.DATAIN
|
|
addr_i[3] => mem_ram_b3~11.DATAIN
|
|
addr_i[3] => mem_ram_b0.WADDR1
|
|
addr_i[3] => mem_ram_b0.RADDR1
|
|
addr_i[3] => mem_ram_b1.WADDR1
|
|
addr_i[3] => mem_ram_b1.RADDR1
|
|
addr_i[3] => mem_ram_b2.WADDR1
|
|
addr_i[3] => mem_ram_b2.RADDR1
|
|
addr_i[3] => mem_ram_b3.WADDR1
|
|
addr_i[3] => mem_ram_b3.RADDR1
|
|
addr_i[4] => mem_ram_b0~9.DATAIN
|
|
addr_i[4] => mem_ram_b1~10.DATAIN
|
|
addr_i[4] => mem_ram_b2~10.DATAIN
|
|
addr_i[4] => mem_ram_b3~10.DATAIN
|
|
addr_i[4] => mem_ram_b0.WADDR2
|
|
addr_i[4] => mem_ram_b0.RADDR2
|
|
addr_i[4] => mem_ram_b1.WADDR2
|
|
addr_i[4] => mem_ram_b1.RADDR2
|
|
addr_i[4] => mem_ram_b2.WADDR2
|
|
addr_i[4] => mem_ram_b2.RADDR2
|
|
addr_i[4] => mem_ram_b3.WADDR2
|
|
addr_i[4] => mem_ram_b3.RADDR2
|
|
addr_i[5] => mem_ram_b0~8.DATAIN
|
|
addr_i[5] => mem_ram_b1~9.DATAIN
|
|
addr_i[5] => mem_ram_b2~9.DATAIN
|
|
addr_i[5] => mem_ram_b3~9.DATAIN
|
|
addr_i[5] => mem_ram_b0.WADDR3
|
|
addr_i[5] => mem_ram_b0.RADDR3
|
|
addr_i[5] => mem_ram_b1.WADDR3
|
|
addr_i[5] => mem_ram_b1.RADDR3
|
|
addr_i[5] => mem_ram_b2.WADDR3
|
|
addr_i[5] => mem_ram_b2.RADDR3
|
|
addr_i[5] => mem_ram_b3.WADDR3
|
|
addr_i[5] => mem_ram_b3.RADDR3
|
|
addr_i[6] => mem_ram_b0~7.DATAIN
|
|
addr_i[6] => mem_ram_b1~8.DATAIN
|
|
addr_i[6] => mem_ram_b2~8.DATAIN
|
|
addr_i[6] => mem_ram_b3~8.DATAIN
|
|
addr_i[6] => mem_ram_b0.WADDR4
|
|
addr_i[6] => mem_ram_b0.RADDR4
|
|
addr_i[6] => mem_ram_b1.WADDR4
|
|
addr_i[6] => mem_ram_b1.RADDR4
|
|
addr_i[6] => mem_ram_b2.WADDR4
|
|
addr_i[6] => mem_ram_b2.RADDR4
|
|
addr_i[6] => mem_ram_b3.WADDR4
|
|
addr_i[6] => mem_ram_b3.RADDR4
|
|
addr_i[7] => mem_ram_b0~6.DATAIN
|
|
addr_i[7] => mem_ram_b1~7.DATAIN
|
|
addr_i[7] => mem_ram_b2~7.DATAIN
|
|
addr_i[7] => mem_ram_b3~7.DATAIN
|
|
addr_i[7] => mem_ram_b0.WADDR5
|
|
addr_i[7] => mem_ram_b0.RADDR5
|
|
addr_i[7] => mem_ram_b1.WADDR5
|
|
addr_i[7] => mem_ram_b1.RADDR5
|
|
addr_i[7] => mem_ram_b2.WADDR5
|
|
addr_i[7] => mem_ram_b2.RADDR5
|
|
addr_i[7] => mem_ram_b3.WADDR5
|
|
addr_i[7] => mem_ram_b3.RADDR5
|
|
addr_i[8] => mem_ram_b0~5.DATAIN
|
|
addr_i[8] => mem_ram_b1~6.DATAIN
|
|
addr_i[8] => mem_ram_b2~6.DATAIN
|
|
addr_i[8] => mem_ram_b3~6.DATAIN
|
|
addr_i[8] => mem_ram_b0.WADDR6
|
|
addr_i[8] => mem_ram_b0.RADDR6
|
|
addr_i[8] => mem_ram_b1.WADDR6
|
|
addr_i[8] => mem_ram_b1.RADDR6
|
|
addr_i[8] => mem_ram_b2.WADDR6
|
|
addr_i[8] => mem_ram_b2.RADDR6
|
|
addr_i[8] => mem_ram_b3.WADDR6
|
|
addr_i[8] => mem_ram_b3.RADDR6
|
|
addr_i[9] => mem_ram_b0~4.DATAIN
|
|
addr_i[9] => mem_ram_b1~5.DATAIN
|
|
addr_i[9] => mem_ram_b2~5.DATAIN
|
|
addr_i[9] => mem_ram_b3~5.DATAIN
|
|
addr_i[9] => mem_ram_b0.WADDR7
|
|
addr_i[9] => mem_ram_b0.RADDR7
|
|
addr_i[9] => mem_ram_b1.WADDR7
|
|
addr_i[9] => mem_ram_b1.RADDR7
|
|
addr_i[9] => mem_ram_b2.WADDR7
|
|
addr_i[9] => mem_ram_b2.RADDR7
|
|
addr_i[9] => mem_ram_b3.WADDR7
|
|
addr_i[9] => mem_ram_b3.RADDR7
|
|
addr_i[10] => mem_ram_b0~3.DATAIN
|
|
addr_i[10] => mem_ram_b1~4.DATAIN
|
|
addr_i[10] => mem_ram_b2~4.DATAIN
|
|
addr_i[10] => mem_ram_b3~4.DATAIN
|
|
addr_i[10] => mem_ram_b0.WADDR8
|
|
addr_i[10] => mem_ram_b0.RADDR8
|
|
addr_i[10] => mem_ram_b1.WADDR8
|
|
addr_i[10] => mem_ram_b1.RADDR8
|
|
addr_i[10] => mem_ram_b2.WADDR8
|
|
addr_i[10] => mem_ram_b2.RADDR8
|
|
addr_i[10] => mem_ram_b3.WADDR8
|
|
addr_i[10] => mem_ram_b3.RADDR8
|
|
addr_i[11] => mem_ram_b0~2.DATAIN
|
|
addr_i[11] => mem_ram_b1~3.DATAIN
|
|
addr_i[11] => mem_ram_b2~3.DATAIN
|
|
addr_i[11] => mem_ram_b3~3.DATAIN
|
|
addr_i[11] => mem_ram_b0.WADDR9
|
|
addr_i[11] => mem_ram_b0.RADDR9
|
|
addr_i[11] => mem_ram_b1.WADDR9
|
|
addr_i[11] => mem_ram_b1.RADDR9
|
|
addr_i[11] => mem_ram_b2.WADDR9
|
|
addr_i[11] => mem_ram_b2.RADDR9
|
|
addr_i[11] => mem_ram_b3.WADDR9
|
|
addr_i[11] => mem_ram_b3.RADDR9
|
|
addr_i[12] => mem_ram_b0~1.DATAIN
|
|
addr_i[12] => mem_ram_b1~2.DATAIN
|
|
addr_i[12] => mem_ram_b2~2.DATAIN
|
|
addr_i[12] => mem_ram_b3~2.DATAIN
|
|
addr_i[12] => mem_ram_b0.WADDR10
|
|
addr_i[12] => mem_ram_b0.RADDR10
|
|
addr_i[12] => mem_ram_b1.WADDR10
|
|
addr_i[12] => mem_ram_b1.RADDR10
|
|
addr_i[12] => mem_ram_b2.WADDR10
|
|
addr_i[12] => mem_ram_b2.RADDR10
|
|
addr_i[12] => mem_ram_b3.WADDR10
|
|
addr_i[12] => mem_ram_b3.RADDR10
|
|
addr_i[13] => mem_ram_b0~0.DATAIN
|
|
addr_i[13] => mem_ram_b1~1.DATAIN
|
|
addr_i[13] => mem_ram_b2~1.DATAIN
|
|
addr_i[13] => mem_ram_b3~1.DATAIN
|
|
addr_i[13] => mem_ram_b0.WADDR11
|
|
addr_i[13] => mem_ram_b0.RADDR11
|
|
addr_i[13] => mem_ram_b1.WADDR11
|
|
addr_i[13] => mem_ram_b1.RADDR11
|
|
addr_i[13] => mem_ram_b2.WADDR11
|
|
addr_i[13] => mem_ram_b2.RADDR11
|
|
addr_i[13] => mem_ram_b3.WADDR11
|
|
addr_i[13] => mem_ram_b3.RADDR11
|
|
addr_i[14] => Equal0.IN17
|
|
addr_i[15] => Equal0.IN16
|
|
addr_i[16] => Equal0.IN15
|
|
addr_i[17] => Equal0.IN14
|
|
addr_i[18] => Equal0.IN13
|
|
addr_i[19] => Equal0.IN12
|
|
addr_i[20] => Equal0.IN11
|
|
addr_i[21] => Equal0.IN10
|
|
addr_i[22] => Equal0.IN9
|
|
addr_i[23] => Equal0.IN8
|
|
addr_i[24] => Equal0.IN7
|
|
addr_i[25] => Equal0.IN6
|
|
addr_i[26] => Equal0.IN5
|
|
addr_i[27] => Equal0.IN4
|
|
addr_i[28] => Equal0.IN3
|
|
addr_i[29] => Equal0.IN2
|
|
addr_i[30] => Equal0.IN1
|
|
addr_i[31] => Equal0.IN0
|
|
data_i[0] => mem_ram_b0~19.DATAIN
|
|
data_i[0] => mem_ram_b0.DATAIN
|
|
data_i[1] => mem_ram_b0~18.DATAIN
|
|
data_i[1] => mem_ram_b0.DATAIN1
|
|
data_i[2] => mem_ram_b0~17.DATAIN
|
|
data_i[2] => mem_ram_b0.DATAIN2
|
|
data_i[3] => mem_ram_b0~16.DATAIN
|
|
data_i[3] => mem_ram_b0.DATAIN3
|
|
data_i[4] => mem_ram_b0~15.DATAIN
|
|
data_i[4] => mem_ram_b0.DATAIN4
|
|
data_i[5] => mem_ram_b0~14.DATAIN
|
|
data_i[5] => mem_ram_b0.DATAIN5
|
|
data_i[6] => mem_ram_b0~13.DATAIN
|
|
data_i[6] => mem_ram_b0.DATAIN6
|
|
data_i[7] => mem_ram_b0~12.DATAIN
|
|
data_i[7] => mem_ram_b0.DATAIN7
|
|
data_i[8] => mem_ram_b1~20.DATAIN
|
|
data_i[8] => mem_ram_b1.DATAIN
|
|
data_i[9] => mem_ram_b1~19.DATAIN
|
|
data_i[9] => mem_ram_b1.DATAIN1
|
|
data_i[10] => mem_ram_b1~18.DATAIN
|
|
data_i[10] => mem_ram_b1.DATAIN2
|
|
data_i[11] => mem_ram_b1~17.DATAIN
|
|
data_i[11] => mem_ram_b1.DATAIN3
|
|
data_i[12] => mem_ram_b1~16.DATAIN
|
|
data_i[12] => mem_ram_b1.DATAIN4
|
|
data_i[13] => mem_ram_b1~15.DATAIN
|
|
data_i[13] => mem_ram_b1.DATAIN5
|
|
data_i[14] => mem_ram_b1~14.DATAIN
|
|
data_i[14] => mem_ram_b1.DATAIN6
|
|
data_i[15] => mem_ram_b1~13.DATAIN
|
|
data_i[15] => mem_ram_b1.DATAIN7
|
|
data_i[16] => mem_ram_b2~20.DATAIN
|
|
data_i[16] => mem_ram_b2.DATAIN
|
|
data_i[17] => mem_ram_b2~19.DATAIN
|
|
data_i[17] => mem_ram_b2.DATAIN1
|
|
data_i[18] => mem_ram_b2~18.DATAIN
|
|
data_i[18] => mem_ram_b2.DATAIN2
|
|
data_i[19] => mem_ram_b2~17.DATAIN
|
|
data_i[19] => mem_ram_b2.DATAIN3
|
|
data_i[20] => mem_ram_b2~16.DATAIN
|
|
data_i[20] => mem_ram_b2.DATAIN4
|
|
data_i[21] => mem_ram_b2~15.DATAIN
|
|
data_i[21] => mem_ram_b2.DATAIN5
|
|
data_i[22] => mem_ram_b2~14.DATAIN
|
|
data_i[22] => mem_ram_b2.DATAIN6
|
|
data_i[23] => mem_ram_b2~13.DATAIN
|
|
data_i[23] => mem_ram_b2.DATAIN7
|
|
data_i[24] => mem_ram_b3~20.DATAIN
|
|
data_i[24] => mem_ram_b3.DATAIN
|
|
data_i[25] => mem_ram_b3~19.DATAIN
|
|
data_i[25] => mem_ram_b3.DATAIN1
|
|
data_i[26] => mem_ram_b3~18.DATAIN
|
|
data_i[26] => mem_ram_b3.DATAIN2
|
|
data_i[27] => mem_ram_b3~17.DATAIN
|
|
data_i[27] => mem_ram_b3.DATAIN3
|
|
data_i[28] => mem_ram_b3~16.DATAIN
|
|
data_i[28] => mem_ram_b3.DATAIN4
|
|
data_i[29] => mem_ram_b3~15.DATAIN
|
|
data_i[29] => mem_ram_b3.DATAIN5
|
|
data_i[30] => mem_ram_b3~14.DATAIN
|
|
data_i[30] => mem_ram_b3.DATAIN6
|
|
data_i[31] => mem_ram_b3~13.DATAIN
|
|
data_i[31] => mem_ram_b3.DATAIN7
|
|
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
err_o <= err_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_dmem:\neorv32_int_dmem_inst_true:neorv32_int_dmem_inst
|
|
clk_i => mem_ram_b0~23.CLK
|
|
clk_i => mem_ram_b0~0.CLK
|
|
clk_i => mem_ram_b0~1.CLK
|
|
clk_i => mem_ram_b0~2.CLK
|
|
clk_i => mem_ram_b0~3.CLK
|
|
clk_i => mem_ram_b0~4.CLK
|
|
clk_i => mem_ram_b0~5.CLK
|
|
clk_i => mem_ram_b0~6.CLK
|
|
clk_i => mem_ram_b0~7.CLK
|
|
clk_i => mem_ram_b0~8.CLK
|
|
clk_i => mem_ram_b0~9.CLK
|
|
clk_i => mem_ram_b0~10.CLK
|
|
clk_i => mem_ram_b0~11.CLK
|
|
clk_i => mem_ram_b0~12.CLK
|
|
clk_i => mem_ram_b0~13.CLK
|
|
clk_i => mem_ram_b0~14.CLK
|
|
clk_i => mem_ram_b0~15.CLK
|
|
clk_i => mem_ram_b0~16.CLK
|
|
clk_i => mem_ram_b0~17.CLK
|
|
clk_i => mem_ram_b0~18.CLK
|
|
clk_i => mem_ram_b0~19.CLK
|
|
clk_i => mem_ram_b0~20.CLK
|
|
clk_i => mem_ram_b0~21.CLK
|
|
clk_i => mem_ram_b0~22.CLK
|
|
clk_i => mem_ram_b1~0.CLK
|
|
clk_i => mem_ram_b1~1.CLK
|
|
clk_i => mem_ram_b1~2.CLK
|
|
clk_i => mem_ram_b1~3.CLK
|
|
clk_i => mem_ram_b1~4.CLK
|
|
clk_i => mem_ram_b1~5.CLK
|
|
clk_i => mem_ram_b1~6.CLK
|
|
clk_i => mem_ram_b1~7.CLK
|
|
clk_i => mem_ram_b1~8.CLK
|
|
clk_i => mem_ram_b1~9.CLK
|
|
clk_i => mem_ram_b1~10.CLK
|
|
clk_i => mem_ram_b1~11.CLK
|
|
clk_i => mem_ram_b1~12.CLK
|
|
clk_i => mem_ram_b1~13.CLK
|
|
clk_i => mem_ram_b1~14.CLK
|
|
clk_i => mem_ram_b1~15.CLK
|
|
clk_i => mem_ram_b1~16.CLK
|
|
clk_i => mem_ram_b1~17.CLK
|
|
clk_i => mem_ram_b1~18.CLK
|
|
clk_i => mem_ram_b1~19.CLK
|
|
clk_i => mem_ram_b1~20.CLK
|
|
clk_i => mem_ram_b1~21.CLK
|
|
clk_i => mem_ram_b1~22.CLK
|
|
clk_i => mem_ram_b1~23.CLK
|
|
clk_i => mem_ram_b2~0.CLK
|
|
clk_i => mem_ram_b2~1.CLK
|
|
clk_i => mem_ram_b2~2.CLK
|
|
clk_i => mem_ram_b2~3.CLK
|
|
clk_i => mem_ram_b2~4.CLK
|
|
clk_i => mem_ram_b2~5.CLK
|
|
clk_i => mem_ram_b2~6.CLK
|
|
clk_i => mem_ram_b2~7.CLK
|
|
clk_i => mem_ram_b2~8.CLK
|
|
clk_i => mem_ram_b2~9.CLK
|
|
clk_i => mem_ram_b2~10.CLK
|
|
clk_i => mem_ram_b2~11.CLK
|
|
clk_i => mem_ram_b2~12.CLK
|
|
clk_i => mem_ram_b2~13.CLK
|
|
clk_i => mem_ram_b2~14.CLK
|
|
clk_i => mem_ram_b2~15.CLK
|
|
clk_i => mem_ram_b2~16.CLK
|
|
clk_i => mem_ram_b2~17.CLK
|
|
clk_i => mem_ram_b2~18.CLK
|
|
clk_i => mem_ram_b2~19.CLK
|
|
clk_i => mem_ram_b2~20.CLK
|
|
clk_i => mem_ram_b2~21.CLK
|
|
clk_i => mem_ram_b2~22.CLK
|
|
clk_i => mem_ram_b2~23.CLK
|
|
clk_i => mem_ram_b3~0.CLK
|
|
clk_i => mem_ram_b3~1.CLK
|
|
clk_i => mem_ram_b3~2.CLK
|
|
clk_i => mem_ram_b3~3.CLK
|
|
clk_i => mem_ram_b3~4.CLK
|
|
clk_i => mem_ram_b3~5.CLK
|
|
clk_i => mem_ram_b3~6.CLK
|
|
clk_i => mem_ram_b3~7.CLK
|
|
clk_i => mem_ram_b3~8.CLK
|
|
clk_i => mem_ram_b3~9.CLK
|
|
clk_i => mem_ram_b3~10.CLK
|
|
clk_i => mem_ram_b3~11.CLK
|
|
clk_i => mem_ram_b3~12.CLK
|
|
clk_i => mem_ram_b3~13.CLK
|
|
clk_i => mem_ram_b3~14.CLK
|
|
clk_i => mem_ram_b3~15.CLK
|
|
clk_i => mem_ram_b3~16.CLK
|
|
clk_i => mem_ram_b3~17.CLK
|
|
clk_i => mem_ram_b3~18.CLK
|
|
clk_i => mem_ram_b3~19.CLK
|
|
clk_i => mem_ram_b3~20.CLK
|
|
clk_i => mem_ram_b3~21.CLK
|
|
clk_i => mem_ram_b3~22.CLK
|
|
clk_i => mem_ram_b3~23.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => rden.CLK
|
|
clk_i => mem_ram_b3_rd[0].CLK
|
|
clk_i => mem_ram_b3_rd[1].CLK
|
|
clk_i => mem_ram_b3_rd[2].CLK
|
|
clk_i => mem_ram_b3_rd[3].CLK
|
|
clk_i => mem_ram_b3_rd[4].CLK
|
|
clk_i => mem_ram_b3_rd[5].CLK
|
|
clk_i => mem_ram_b3_rd[6].CLK
|
|
clk_i => mem_ram_b3_rd[7].CLK
|
|
clk_i => mem_ram_b2_rd[0].CLK
|
|
clk_i => mem_ram_b2_rd[1].CLK
|
|
clk_i => mem_ram_b2_rd[2].CLK
|
|
clk_i => mem_ram_b2_rd[3].CLK
|
|
clk_i => mem_ram_b2_rd[4].CLK
|
|
clk_i => mem_ram_b2_rd[5].CLK
|
|
clk_i => mem_ram_b2_rd[6].CLK
|
|
clk_i => mem_ram_b2_rd[7].CLK
|
|
clk_i => mem_ram_b1_rd[0].CLK
|
|
clk_i => mem_ram_b1_rd[1].CLK
|
|
clk_i => mem_ram_b1_rd[2].CLK
|
|
clk_i => mem_ram_b1_rd[3].CLK
|
|
clk_i => mem_ram_b1_rd[4].CLK
|
|
clk_i => mem_ram_b1_rd[5].CLK
|
|
clk_i => mem_ram_b1_rd[6].CLK
|
|
clk_i => mem_ram_b1_rd[7].CLK
|
|
clk_i => mem_ram_b0_rd[0].CLK
|
|
clk_i => mem_ram_b0_rd[1].CLK
|
|
clk_i => mem_ram_b0_rd[2].CLK
|
|
clk_i => mem_ram_b0_rd[3].CLK
|
|
clk_i => mem_ram_b0_rd[4].CLK
|
|
clk_i => mem_ram_b0_rd[5].CLK
|
|
clk_i => mem_ram_b0_rd[6].CLK
|
|
clk_i => mem_ram_b0_rd[7].CLK
|
|
clk_i => mem_ram_b0.CLK0
|
|
clk_i => mem_ram_b1.CLK0
|
|
clk_i => mem_ram_b2.CLK0
|
|
clk_i => mem_ram_b3.CLK0
|
|
rden_i => rden.IN1
|
|
rden_i => ack_o.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => mem_access.IN0
|
|
wren_i => ack_o.IN1
|
|
ben_i[0] => mem_access.IN1
|
|
ben_i[1] => mem_access.IN1
|
|
ben_i[2] => mem_access.IN1
|
|
ben_i[3] => mem_access.IN1
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => mem_ram_b0~14.DATAIN
|
|
addr_i[2] => mem_ram_b1~15.DATAIN
|
|
addr_i[2] => mem_ram_b2~15.DATAIN
|
|
addr_i[2] => mem_ram_b3~15.DATAIN
|
|
addr_i[2] => mem_ram_b0.WADDR
|
|
addr_i[2] => mem_ram_b0.RADDR
|
|
addr_i[2] => mem_ram_b1.WADDR
|
|
addr_i[2] => mem_ram_b1.RADDR
|
|
addr_i[2] => mem_ram_b2.WADDR
|
|
addr_i[2] => mem_ram_b2.RADDR
|
|
addr_i[2] => mem_ram_b3.WADDR
|
|
addr_i[2] => mem_ram_b3.RADDR
|
|
addr_i[3] => mem_ram_b0~13.DATAIN
|
|
addr_i[3] => mem_ram_b1~14.DATAIN
|
|
addr_i[3] => mem_ram_b2~14.DATAIN
|
|
addr_i[3] => mem_ram_b3~14.DATAIN
|
|
addr_i[3] => mem_ram_b0.WADDR1
|
|
addr_i[3] => mem_ram_b0.RADDR1
|
|
addr_i[3] => mem_ram_b1.WADDR1
|
|
addr_i[3] => mem_ram_b1.RADDR1
|
|
addr_i[3] => mem_ram_b2.WADDR1
|
|
addr_i[3] => mem_ram_b2.RADDR1
|
|
addr_i[3] => mem_ram_b3.WADDR1
|
|
addr_i[3] => mem_ram_b3.RADDR1
|
|
addr_i[4] => mem_ram_b0~12.DATAIN
|
|
addr_i[4] => mem_ram_b1~13.DATAIN
|
|
addr_i[4] => mem_ram_b2~13.DATAIN
|
|
addr_i[4] => mem_ram_b3~13.DATAIN
|
|
addr_i[4] => mem_ram_b0.WADDR2
|
|
addr_i[4] => mem_ram_b0.RADDR2
|
|
addr_i[4] => mem_ram_b1.WADDR2
|
|
addr_i[4] => mem_ram_b1.RADDR2
|
|
addr_i[4] => mem_ram_b2.WADDR2
|
|
addr_i[4] => mem_ram_b2.RADDR2
|
|
addr_i[4] => mem_ram_b3.WADDR2
|
|
addr_i[4] => mem_ram_b3.RADDR2
|
|
addr_i[5] => mem_ram_b0~11.DATAIN
|
|
addr_i[5] => mem_ram_b1~12.DATAIN
|
|
addr_i[5] => mem_ram_b2~12.DATAIN
|
|
addr_i[5] => mem_ram_b3~12.DATAIN
|
|
addr_i[5] => mem_ram_b0.WADDR3
|
|
addr_i[5] => mem_ram_b0.RADDR3
|
|
addr_i[5] => mem_ram_b1.WADDR3
|
|
addr_i[5] => mem_ram_b1.RADDR3
|
|
addr_i[5] => mem_ram_b2.WADDR3
|
|
addr_i[5] => mem_ram_b2.RADDR3
|
|
addr_i[5] => mem_ram_b3.WADDR3
|
|
addr_i[5] => mem_ram_b3.RADDR3
|
|
addr_i[6] => mem_ram_b0~10.DATAIN
|
|
addr_i[6] => mem_ram_b1~11.DATAIN
|
|
addr_i[6] => mem_ram_b2~11.DATAIN
|
|
addr_i[6] => mem_ram_b3~11.DATAIN
|
|
addr_i[6] => mem_ram_b0.WADDR4
|
|
addr_i[6] => mem_ram_b0.RADDR4
|
|
addr_i[6] => mem_ram_b1.WADDR4
|
|
addr_i[6] => mem_ram_b1.RADDR4
|
|
addr_i[6] => mem_ram_b2.WADDR4
|
|
addr_i[6] => mem_ram_b2.RADDR4
|
|
addr_i[6] => mem_ram_b3.WADDR4
|
|
addr_i[6] => mem_ram_b3.RADDR4
|
|
addr_i[7] => mem_ram_b0~9.DATAIN
|
|
addr_i[7] => mem_ram_b1~10.DATAIN
|
|
addr_i[7] => mem_ram_b2~10.DATAIN
|
|
addr_i[7] => mem_ram_b3~10.DATAIN
|
|
addr_i[7] => mem_ram_b0.WADDR5
|
|
addr_i[7] => mem_ram_b0.RADDR5
|
|
addr_i[7] => mem_ram_b1.WADDR5
|
|
addr_i[7] => mem_ram_b1.RADDR5
|
|
addr_i[7] => mem_ram_b2.WADDR5
|
|
addr_i[7] => mem_ram_b2.RADDR5
|
|
addr_i[7] => mem_ram_b3.WADDR5
|
|
addr_i[7] => mem_ram_b3.RADDR5
|
|
addr_i[8] => mem_ram_b0~8.DATAIN
|
|
addr_i[8] => mem_ram_b1~9.DATAIN
|
|
addr_i[8] => mem_ram_b2~9.DATAIN
|
|
addr_i[8] => mem_ram_b3~9.DATAIN
|
|
addr_i[8] => mem_ram_b0.WADDR6
|
|
addr_i[8] => mem_ram_b0.RADDR6
|
|
addr_i[8] => mem_ram_b1.WADDR6
|
|
addr_i[8] => mem_ram_b1.RADDR6
|
|
addr_i[8] => mem_ram_b2.WADDR6
|
|
addr_i[8] => mem_ram_b2.RADDR6
|
|
addr_i[8] => mem_ram_b3.WADDR6
|
|
addr_i[8] => mem_ram_b3.RADDR6
|
|
addr_i[9] => mem_ram_b0~7.DATAIN
|
|
addr_i[9] => mem_ram_b1~8.DATAIN
|
|
addr_i[9] => mem_ram_b2~8.DATAIN
|
|
addr_i[9] => mem_ram_b3~8.DATAIN
|
|
addr_i[9] => mem_ram_b0.WADDR7
|
|
addr_i[9] => mem_ram_b0.RADDR7
|
|
addr_i[9] => mem_ram_b1.WADDR7
|
|
addr_i[9] => mem_ram_b1.RADDR7
|
|
addr_i[9] => mem_ram_b2.WADDR7
|
|
addr_i[9] => mem_ram_b2.RADDR7
|
|
addr_i[9] => mem_ram_b3.WADDR7
|
|
addr_i[9] => mem_ram_b3.RADDR7
|
|
addr_i[10] => mem_ram_b0~6.DATAIN
|
|
addr_i[10] => mem_ram_b1~7.DATAIN
|
|
addr_i[10] => mem_ram_b2~7.DATAIN
|
|
addr_i[10] => mem_ram_b3~7.DATAIN
|
|
addr_i[10] => mem_ram_b0.WADDR8
|
|
addr_i[10] => mem_ram_b0.RADDR8
|
|
addr_i[10] => mem_ram_b1.WADDR8
|
|
addr_i[10] => mem_ram_b1.RADDR8
|
|
addr_i[10] => mem_ram_b2.WADDR8
|
|
addr_i[10] => mem_ram_b2.RADDR8
|
|
addr_i[10] => mem_ram_b3.WADDR8
|
|
addr_i[10] => mem_ram_b3.RADDR8
|
|
addr_i[11] => mem_ram_b0~5.DATAIN
|
|
addr_i[11] => mem_ram_b1~6.DATAIN
|
|
addr_i[11] => mem_ram_b2~6.DATAIN
|
|
addr_i[11] => mem_ram_b3~6.DATAIN
|
|
addr_i[11] => mem_ram_b0.WADDR9
|
|
addr_i[11] => mem_ram_b0.RADDR9
|
|
addr_i[11] => mem_ram_b1.WADDR9
|
|
addr_i[11] => mem_ram_b1.RADDR9
|
|
addr_i[11] => mem_ram_b2.WADDR9
|
|
addr_i[11] => mem_ram_b2.RADDR9
|
|
addr_i[11] => mem_ram_b3.WADDR9
|
|
addr_i[11] => mem_ram_b3.RADDR9
|
|
addr_i[12] => mem_ram_b0~4.DATAIN
|
|
addr_i[12] => mem_ram_b1~5.DATAIN
|
|
addr_i[12] => mem_ram_b2~5.DATAIN
|
|
addr_i[12] => mem_ram_b3~5.DATAIN
|
|
addr_i[12] => mem_ram_b0.WADDR10
|
|
addr_i[12] => mem_ram_b0.RADDR10
|
|
addr_i[12] => mem_ram_b1.WADDR10
|
|
addr_i[12] => mem_ram_b1.RADDR10
|
|
addr_i[12] => mem_ram_b2.WADDR10
|
|
addr_i[12] => mem_ram_b2.RADDR10
|
|
addr_i[12] => mem_ram_b3.WADDR10
|
|
addr_i[12] => mem_ram_b3.RADDR10
|
|
addr_i[13] => mem_ram_b0~3.DATAIN
|
|
addr_i[13] => mem_ram_b1~4.DATAIN
|
|
addr_i[13] => mem_ram_b2~4.DATAIN
|
|
addr_i[13] => mem_ram_b3~4.DATAIN
|
|
addr_i[13] => mem_ram_b0.WADDR11
|
|
addr_i[13] => mem_ram_b0.RADDR11
|
|
addr_i[13] => mem_ram_b1.WADDR11
|
|
addr_i[13] => mem_ram_b1.RADDR11
|
|
addr_i[13] => mem_ram_b2.WADDR11
|
|
addr_i[13] => mem_ram_b2.RADDR11
|
|
addr_i[13] => mem_ram_b3.WADDR11
|
|
addr_i[13] => mem_ram_b3.RADDR11
|
|
addr_i[14] => mem_ram_b0~2.DATAIN
|
|
addr_i[14] => mem_ram_b1~3.DATAIN
|
|
addr_i[14] => mem_ram_b2~3.DATAIN
|
|
addr_i[14] => mem_ram_b3~3.DATAIN
|
|
addr_i[14] => mem_ram_b0.WADDR12
|
|
addr_i[14] => mem_ram_b0.RADDR12
|
|
addr_i[14] => mem_ram_b1.WADDR12
|
|
addr_i[14] => mem_ram_b1.RADDR12
|
|
addr_i[14] => mem_ram_b2.WADDR12
|
|
addr_i[14] => mem_ram_b2.RADDR12
|
|
addr_i[14] => mem_ram_b3.WADDR12
|
|
addr_i[14] => mem_ram_b3.RADDR12
|
|
addr_i[15] => mem_ram_b0~1.DATAIN
|
|
addr_i[15] => mem_ram_b1~2.DATAIN
|
|
addr_i[15] => mem_ram_b2~2.DATAIN
|
|
addr_i[15] => mem_ram_b3~2.DATAIN
|
|
addr_i[15] => mem_ram_b0.WADDR13
|
|
addr_i[15] => mem_ram_b0.RADDR13
|
|
addr_i[15] => mem_ram_b1.WADDR13
|
|
addr_i[15] => mem_ram_b1.RADDR13
|
|
addr_i[15] => mem_ram_b2.WADDR13
|
|
addr_i[15] => mem_ram_b2.RADDR13
|
|
addr_i[15] => mem_ram_b3.WADDR13
|
|
addr_i[15] => mem_ram_b3.RADDR13
|
|
addr_i[16] => mem_ram_b0~0.DATAIN
|
|
addr_i[16] => mem_ram_b1~1.DATAIN
|
|
addr_i[16] => mem_ram_b2~1.DATAIN
|
|
addr_i[16] => mem_ram_b3~1.DATAIN
|
|
addr_i[16] => mem_ram_b0.WADDR14
|
|
addr_i[16] => mem_ram_b0.RADDR14
|
|
addr_i[16] => mem_ram_b1.WADDR14
|
|
addr_i[16] => mem_ram_b1.RADDR14
|
|
addr_i[16] => mem_ram_b2.WADDR14
|
|
addr_i[16] => mem_ram_b2.RADDR14
|
|
addr_i[16] => mem_ram_b3.WADDR14
|
|
addr_i[16] => mem_ram_b3.RADDR14
|
|
addr_i[17] => Equal0.IN13
|
|
addr_i[18] => Equal0.IN12
|
|
addr_i[19] => Equal0.IN11
|
|
addr_i[20] => Equal0.IN10
|
|
addr_i[21] => Equal0.IN9
|
|
addr_i[22] => Equal0.IN8
|
|
addr_i[23] => Equal0.IN7
|
|
addr_i[24] => Equal0.IN6
|
|
addr_i[25] => Equal0.IN5
|
|
addr_i[26] => Equal0.IN4
|
|
addr_i[27] => Equal0.IN3
|
|
addr_i[28] => Equal0.IN2
|
|
addr_i[29] => Equal0.IN1
|
|
addr_i[30] => Equal0.IN0
|
|
addr_i[31] => Equal0.IN14
|
|
data_i[0] => mem_ram_b0~22.DATAIN
|
|
data_i[0] => mem_ram_b0.DATAIN
|
|
data_i[1] => mem_ram_b0~21.DATAIN
|
|
data_i[1] => mem_ram_b0.DATAIN1
|
|
data_i[2] => mem_ram_b0~20.DATAIN
|
|
data_i[2] => mem_ram_b0.DATAIN2
|
|
data_i[3] => mem_ram_b0~19.DATAIN
|
|
data_i[3] => mem_ram_b0.DATAIN3
|
|
data_i[4] => mem_ram_b0~18.DATAIN
|
|
data_i[4] => mem_ram_b0.DATAIN4
|
|
data_i[5] => mem_ram_b0~17.DATAIN
|
|
data_i[5] => mem_ram_b0.DATAIN5
|
|
data_i[6] => mem_ram_b0~16.DATAIN
|
|
data_i[6] => mem_ram_b0.DATAIN6
|
|
data_i[7] => mem_ram_b0~15.DATAIN
|
|
data_i[7] => mem_ram_b0.DATAIN7
|
|
data_i[8] => mem_ram_b1~23.DATAIN
|
|
data_i[8] => mem_ram_b1.DATAIN
|
|
data_i[9] => mem_ram_b1~22.DATAIN
|
|
data_i[9] => mem_ram_b1.DATAIN1
|
|
data_i[10] => mem_ram_b1~21.DATAIN
|
|
data_i[10] => mem_ram_b1.DATAIN2
|
|
data_i[11] => mem_ram_b1~20.DATAIN
|
|
data_i[11] => mem_ram_b1.DATAIN3
|
|
data_i[12] => mem_ram_b1~19.DATAIN
|
|
data_i[12] => mem_ram_b1.DATAIN4
|
|
data_i[13] => mem_ram_b1~18.DATAIN
|
|
data_i[13] => mem_ram_b1.DATAIN5
|
|
data_i[14] => mem_ram_b1~17.DATAIN
|
|
data_i[14] => mem_ram_b1.DATAIN6
|
|
data_i[15] => mem_ram_b1~16.DATAIN
|
|
data_i[15] => mem_ram_b1.DATAIN7
|
|
data_i[16] => mem_ram_b2~23.DATAIN
|
|
data_i[16] => mem_ram_b2.DATAIN
|
|
data_i[17] => mem_ram_b2~22.DATAIN
|
|
data_i[17] => mem_ram_b2.DATAIN1
|
|
data_i[18] => mem_ram_b2~21.DATAIN
|
|
data_i[18] => mem_ram_b2.DATAIN2
|
|
data_i[19] => mem_ram_b2~20.DATAIN
|
|
data_i[19] => mem_ram_b2.DATAIN3
|
|
data_i[20] => mem_ram_b2~19.DATAIN
|
|
data_i[20] => mem_ram_b2.DATAIN4
|
|
data_i[21] => mem_ram_b2~18.DATAIN
|
|
data_i[21] => mem_ram_b2.DATAIN5
|
|
data_i[22] => mem_ram_b2~17.DATAIN
|
|
data_i[22] => mem_ram_b2.DATAIN6
|
|
data_i[23] => mem_ram_b2~16.DATAIN
|
|
data_i[23] => mem_ram_b2.DATAIN7
|
|
data_i[24] => mem_ram_b3~23.DATAIN
|
|
data_i[24] => mem_ram_b3.DATAIN
|
|
data_i[25] => mem_ram_b3~22.DATAIN
|
|
data_i[25] => mem_ram_b3.DATAIN1
|
|
data_i[26] => mem_ram_b3~21.DATAIN
|
|
data_i[26] => mem_ram_b3.DATAIN2
|
|
data_i[27] => mem_ram_b3~20.DATAIN
|
|
data_i[27] => mem_ram_b3.DATAIN3
|
|
data_i[28] => mem_ram_b3~19.DATAIN
|
|
data_i[28] => mem_ram_b3.DATAIN4
|
|
data_i[29] => mem_ram_b3~18.DATAIN
|
|
data_i[29] => mem_ram_b3.DATAIN5
|
|
data_i[30] => mem_ram_b3~17.DATAIN
|
|
data_i[30] => mem_ram_b3.DATAIN6
|
|
data_i[31] => mem_ram_b3~16.DATAIN
|
|
data_i[31] => mem_ram_b3.DATAIN7
|
|
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_boot_rom:\neorv32_boot_rom_inst_true:neorv32_boot_rom_inst
|
|
clk_i => rdata[0].CLK
|
|
clk_i => rdata[1].CLK
|
|
clk_i => rdata[2].CLK
|
|
clk_i => rdata[3].CLK
|
|
clk_i => rdata[4].CLK
|
|
clk_i => rdata[5].CLK
|
|
clk_i => rdata[6].CLK
|
|
clk_i => rdata[7].CLK
|
|
clk_i => rdata[8].CLK
|
|
clk_i => rdata[9].CLK
|
|
clk_i => rdata[10].CLK
|
|
clk_i => rdata[11].CLK
|
|
clk_i => rdata[12].CLK
|
|
clk_i => rdata[13].CLK
|
|
clk_i => rdata[14].CLK
|
|
clk_i => rdata[15].CLK
|
|
clk_i => rdata[16].CLK
|
|
clk_i => rdata[17].CLK
|
|
clk_i => rdata[18].CLK
|
|
clk_i => rdata[19].CLK
|
|
clk_i => rdata[20].CLK
|
|
clk_i => rdata[21].CLK
|
|
clk_i => rdata[22].CLK
|
|
clk_i => rdata[23].CLK
|
|
clk_i => rdata[24].CLK
|
|
clk_i => rdata[25].CLK
|
|
clk_i => rdata[26].CLK
|
|
clk_i => rdata[27].CLK
|
|
clk_i => rdata[28].CLK
|
|
clk_i => rdata[29].CLK
|
|
clk_i => rdata[30].CLK
|
|
clk_i => rdata[31].CLK
|
|
clk_i => err_o~reg0.CLK
|
|
clk_i => rden.CLK
|
|
rden_i => rden.IN1
|
|
wren_i => err_o.IN1
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => Mux0.IN1033
|
|
addr_i[2] => Mux1.IN1033
|
|
addr_i[2] => Mux2.IN1033
|
|
addr_i[2] => Mux3.IN1033
|
|
addr_i[2] => Mux4.IN1033
|
|
addr_i[2] => Mux5.IN1033
|
|
addr_i[2] => Mux6.IN1033
|
|
addr_i[2] => Mux7.IN1033
|
|
addr_i[2] => Mux8.IN1033
|
|
addr_i[2] => Mux9.IN1033
|
|
addr_i[2] => Mux10.IN1033
|
|
addr_i[2] => Mux11.IN1033
|
|
addr_i[2] => Mux12.IN1033
|
|
addr_i[2] => Mux13.IN1033
|
|
addr_i[2] => Mux14.IN1033
|
|
addr_i[2] => Mux15.IN1033
|
|
addr_i[2] => Mux16.IN1033
|
|
addr_i[2] => Mux17.IN1033
|
|
addr_i[2] => Mux18.IN1033
|
|
addr_i[2] => Mux19.IN1033
|
|
addr_i[2] => Mux20.IN1033
|
|
addr_i[2] => Mux21.IN1033
|
|
addr_i[2] => Mux22.IN1033
|
|
addr_i[2] => Mux23.IN1033
|
|
addr_i[2] => Mux24.IN1033
|
|
addr_i[2] => Mux25.IN1033
|
|
addr_i[2] => Mux26.IN1033
|
|
addr_i[2] => Mux27.IN1033
|
|
addr_i[2] => Mux28.IN1033
|
|
addr_i[2] => Mux29.IN1033
|
|
addr_i[2] => Mux30.IN1033
|
|
addr_i[2] => Mux31.IN1033
|
|
addr_i[3] => Mux0.IN1032
|
|
addr_i[3] => Mux1.IN1032
|
|
addr_i[3] => Mux2.IN1032
|
|
addr_i[3] => Mux3.IN1032
|
|
addr_i[3] => Mux4.IN1032
|
|
addr_i[3] => Mux5.IN1032
|
|
addr_i[3] => Mux6.IN1032
|
|
addr_i[3] => Mux7.IN1032
|
|
addr_i[3] => Mux8.IN1032
|
|
addr_i[3] => Mux9.IN1032
|
|
addr_i[3] => Mux10.IN1032
|
|
addr_i[3] => Mux11.IN1032
|
|
addr_i[3] => Mux12.IN1032
|
|
addr_i[3] => Mux13.IN1032
|
|
addr_i[3] => Mux14.IN1032
|
|
addr_i[3] => Mux15.IN1032
|
|
addr_i[3] => Mux16.IN1032
|
|
addr_i[3] => Mux17.IN1032
|
|
addr_i[3] => Mux18.IN1032
|
|
addr_i[3] => Mux19.IN1032
|
|
addr_i[3] => Mux20.IN1032
|
|
addr_i[3] => Mux21.IN1032
|
|
addr_i[3] => Mux22.IN1032
|
|
addr_i[3] => Mux23.IN1032
|
|
addr_i[3] => Mux24.IN1032
|
|
addr_i[3] => Mux25.IN1032
|
|
addr_i[3] => Mux26.IN1032
|
|
addr_i[3] => Mux27.IN1032
|
|
addr_i[3] => Mux28.IN1032
|
|
addr_i[3] => Mux29.IN1032
|
|
addr_i[3] => Mux30.IN1032
|
|
addr_i[3] => Mux31.IN1032
|
|
addr_i[4] => Mux0.IN1031
|
|
addr_i[4] => Mux1.IN1031
|
|
addr_i[4] => Mux2.IN1031
|
|
addr_i[4] => Mux3.IN1031
|
|
addr_i[4] => Mux4.IN1031
|
|
addr_i[4] => Mux5.IN1031
|
|
addr_i[4] => Mux6.IN1031
|
|
addr_i[4] => Mux7.IN1031
|
|
addr_i[4] => Mux8.IN1031
|
|
addr_i[4] => Mux9.IN1031
|
|
addr_i[4] => Mux10.IN1031
|
|
addr_i[4] => Mux11.IN1031
|
|
addr_i[4] => Mux12.IN1031
|
|
addr_i[4] => Mux13.IN1031
|
|
addr_i[4] => Mux14.IN1031
|
|
addr_i[4] => Mux15.IN1031
|
|
addr_i[4] => Mux16.IN1031
|
|
addr_i[4] => Mux17.IN1031
|
|
addr_i[4] => Mux18.IN1031
|
|
addr_i[4] => Mux19.IN1031
|
|
addr_i[4] => Mux20.IN1031
|
|
addr_i[4] => Mux21.IN1031
|
|
addr_i[4] => Mux22.IN1031
|
|
addr_i[4] => Mux23.IN1031
|
|
addr_i[4] => Mux24.IN1031
|
|
addr_i[4] => Mux25.IN1031
|
|
addr_i[4] => Mux26.IN1031
|
|
addr_i[4] => Mux27.IN1031
|
|
addr_i[4] => Mux28.IN1031
|
|
addr_i[4] => Mux29.IN1031
|
|
addr_i[4] => Mux30.IN1031
|
|
addr_i[4] => Mux31.IN1031
|
|
addr_i[5] => Mux0.IN1030
|
|
addr_i[5] => Mux1.IN1030
|
|
addr_i[5] => Mux2.IN1030
|
|
addr_i[5] => Mux3.IN1030
|
|
addr_i[5] => Mux4.IN1030
|
|
addr_i[5] => Mux5.IN1030
|
|
addr_i[5] => Mux6.IN1030
|
|
addr_i[5] => Mux7.IN1030
|
|
addr_i[5] => Mux8.IN1030
|
|
addr_i[5] => Mux9.IN1030
|
|
addr_i[5] => Mux10.IN1030
|
|
addr_i[5] => Mux11.IN1030
|
|
addr_i[5] => Mux12.IN1030
|
|
addr_i[5] => Mux13.IN1030
|
|
addr_i[5] => Mux14.IN1030
|
|
addr_i[5] => Mux15.IN1030
|
|
addr_i[5] => Mux16.IN1030
|
|
addr_i[5] => Mux17.IN1030
|
|
addr_i[5] => Mux18.IN1030
|
|
addr_i[5] => Mux19.IN1030
|
|
addr_i[5] => Mux20.IN1030
|
|
addr_i[5] => Mux21.IN1030
|
|
addr_i[5] => Mux22.IN1030
|
|
addr_i[5] => Mux23.IN1030
|
|
addr_i[5] => Mux24.IN1030
|
|
addr_i[5] => Mux25.IN1030
|
|
addr_i[5] => Mux26.IN1030
|
|
addr_i[5] => Mux27.IN1030
|
|
addr_i[5] => Mux28.IN1030
|
|
addr_i[5] => Mux29.IN1030
|
|
addr_i[5] => Mux30.IN1030
|
|
addr_i[5] => Mux31.IN1030
|
|
addr_i[6] => Mux0.IN1029
|
|
addr_i[6] => Mux1.IN1029
|
|
addr_i[6] => Mux2.IN1029
|
|
addr_i[6] => Mux3.IN1029
|
|
addr_i[6] => Mux4.IN1029
|
|
addr_i[6] => Mux5.IN1029
|
|
addr_i[6] => Mux6.IN1029
|
|
addr_i[6] => Mux7.IN1029
|
|
addr_i[6] => Mux8.IN1029
|
|
addr_i[6] => Mux9.IN1029
|
|
addr_i[6] => Mux10.IN1029
|
|
addr_i[6] => Mux11.IN1029
|
|
addr_i[6] => Mux12.IN1029
|
|
addr_i[6] => Mux13.IN1029
|
|
addr_i[6] => Mux14.IN1029
|
|
addr_i[6] => Mux15.IN1029
|
|
addr_i[6] => Mux16.IN1029
|
|
addr_i[6] => Mux17.IN1029
|
|
addr_i[6] => Mux18.IN1029
|
|
addr_i[6] => Mux19.IN1029
|
|
addr_i[6] => Mux20.IN1029
|
|
addr_i[6] => Mux21.IN1029
|
|
addr_i[6] => Mux22.IN1029
|
|
addr_i[6] => Mux23.IN1029
|
|
addr_i[6] => Mux24.IN1029
|
|
addr_i[6] => Mux25.IN1029
|
|
addr_i[6] => Mux26.IN1029
|
|
addr_i[6] => Mux27.IN1029
|
|
addr_i[6] => Mux28.IN1029
|
|
addr_i[6] => Mux29.IN1029
|
|
addr_i[6] => Mux30.IN1029
|
|
addr_i[6] => Mux31.IN1029
|
|
addr_i[7] => Mux0.IN1028
|
|
addr_i[7] => Mux1.IN1028
|
|
addr_i[7] => Mux2.IN1028
|
|
addr_i[7] => Mux3.IN1028
|
|
addr_i[7] => Mux4.IN1028
|
|
addr_i[7] => Mux5.IN1028
|
|
addr_i[7] => Mux6.IN1028
|
|
addr_i[7] => Mux7.IN1028
|
|
addr_i[7] => Mux8.IN1028
|
|
addr_i[7] => Mux9.IN1028
|
|
addr_i[7] => Mux10.IN1028
|
|
addr_i[7] => Mux11.IN1028
|
|
addr_i[7] => Mux12.IN1028
|
|
addr_i[7] => Mux13.IN1028
|
|
addr_i[7] => Mux14.IN1028
|
|
addr_i[7] => Mux15.IN1028
|
|
addr_i[7] => Mux16.IN1028
|
|
addr_i[7] => Mux17.IN1028
|
|
addr_i[7] => Mux18.IN1028
|
|
addr_i[7] => Mux19.IN1028
|
|
addr_i[7] => Mux20.IN1028
|
|
addr_i[7] => Mux21.IN1028
|
|
addr_i[7] => Mux22.IN1028
|
|
addr_i[7] => Mux23.IN1028
|
|
addr_i[7] => Mux24.IN1028
|
|
addr_i[7] => Mux25.IN1028
|
|
addr_i[7] => Mux26.IN1028
|
|
addr_i[7] => Mux27.IN1028
|
|
addr_i[7] => Mux28.IN1028
|
|
addr_i[7] => Mux29.IN1028
|
|
addr_i[7] => Mux30.IN1028
|
|
addr_i[7] => Mux31.IN1028
|
|
addr_i[8] => Mux0.IN1027
|
|
addr_i[8] => Mux1.IN1027
|
|
addr_i[8] => Mux2.IN1027
|
|
addr_i[8] => Mux3.IN1027
|
|
addr_i[8] => Mux4.IN1027
|
|
addr_i[8] => Mux5.IN1027
|
|
addr_i[8] => Mux6.IN1027
|
|
addr_i[8] => Mux7.IN1027
|
|
addr_i[8] => Mux8.IN1027
|
|
addr_i[8] => Mux9.IN1027
|
|
addr_i[8] => Mux10.IN1027
|
|
addr_i[8] => Mux11.IN1027
|
|
addr_i[8] => Mux12.IN1027
|
|
addr_i[8] => Mux13.IN1027
|
|
addr_i[8] => Mux14.IN1027
|
|
addr_i[8] => Mux15.IN1027
|
|
addr_i[8] => Mux16.IN1027
|
|
addr_i[8] => Mux17.IN1027
|
|
addr_i[8] => Mux18.IN1027
|
|
addr_i[8] => Mux19.IN1027
|
|
addr_i[8] => Mux20.IN1027
|
|
addr_i[8] => Mux21.IN1027
|
|
addr_i[8] => Mux22.IN1027
|
|
addr_i[8] => Mux23.IN1027
|
|
addr_i[8] => Mux24.IN1027
|
|
addr_i[8] => Mux25.IN1027
|
|
addr_i[8] => Mux26.IN1027
|
|
addr_i[8] => Mux27.IN1027
|
|
addr_i[8] => Mux28.IN1027
|
|
addr_i[8] => Mux29.IN1027
|
|
addr_i[8] => Mux30.IN1027
|
|
addr_i[8] => Mux31.IN1027
|
|
addr_i[9] => Mux0.IN1026
|
|
addr_i[9] => Mux1.IN1026
|
|
addr_i[9] => Mux2.IN1026
|
|
addr_i[9] => Mux3.IN1026
|
|
addr_i[9] => Mux4.IN1026
|
|
addr_i[9] => Mux5.IN1026
|
|
addr_i[9] => Mux6.IN1026
|
|
addr_i[9] => Mux7.IN1026
|
|
addr_i[9] => Mux8.IN1026
|
|
addr_i[9] => Mux9.IN1026
|
|
addr_i[9] => Mux10.IN1026
|
|
addr_i[9] => Mux11.IN1026
|
|
addr_i[9] => Mux12.IN1026
|
|
addr_i[9] => Mux13.IN1026
|
|
addr_i[9] => Mux14.IN1026
|
|
addr_i[9] => Mux15.IN1026
|
|
addr_i[9] => Mux16.IN1026
|
|
addr_i[9] => Mux17.IN1026
|
|
addr_i[9] => Mux18.IN1026
|
|
addr_i[9] => Mux19.IN1026
|
|
addr_i[9] => Mux20.IN1026
|
|
addr_i[9] => Mux21.IN1026
|
|
addr_i[9] => Mux22.IN1026
|
|
addr_i[9] => Mux23.IN1026
|
|
addr_i[9] => Mux24.IN1026
|
|
addr_i[9] => Mux25.IN1026
|
|
addr_i[9] => Mux26.IN1026
|
|
addr_i[9] => Mux27.IN1026
|
|
addr_i[9] => Mux28.IN1026
|
|
addr_i[9] => Mux29.IN1026
|
|
addr_i[9] => Mux30.IN1026
|
|
addr_i[9] => Mux31.IN1026
|
|
addr_i[10] => Mux0.IN1025
|
|
addr_i[10] => Mux1.IN1025
|
|
addr_i[10] => Mux2.IN1025
|
|
addr_i[10] => Mux3.IN1025
|
|
addr_i[10] => Mux4.IN1025
|
|
addr_i[10] => Mux5.IN1025
|
|
addr_i[10] => Mux6.IN1025
|
|
addr_i[10] => Mux7.IN1025
|
|
addr_i[10] => Mux8.IN1025
|
|
addr_i[10] => Mux9.IN1025
|
|
addr_i[10] => Mux10.IN1025
|
|
addr_i[10] => Mux11.IN1025
|
|
addr_i[10] => Mux12.IN1025
|
|
addr_i[10] => Mux13.IN1025
|
|
addr_i[10] => Mux14.IN1025
|
|
addr_i[10] => Mux15.IN1025
|
|
addr_i[10] => Mux16.IN1025
|
|
addr_i[10] => Mux17.IN1025
|
|
addr_i[10] => Mux18.IN1025
|
|
addr_i[10] => Mux19.IN1025
|
|
addr_i[10] => Mux20.IN1025
|
|
addr_i[10] => Mux21.IN1025
|
|
addr_i[10] => Mux22.IN1025
|
|
addr_i[10] => Mux23.IN1025
|
|
addr_i[10] => Mux24.IN1025
|
|
addr_i[10] => Mux25.IN1025
|
|
addr_i[10] => Mux26.IN1025
|
|
addr_i[10] => Mux27.IN1025
|
|
addr_i[10] => Mux28.IN1025
|
|
addr_i[10] => Mux29.IN1025
|
|
addr_i[10] => Mux30.IN1025
|
|
addr_i[10] => Mux31.IN1025
|
|
addr_i[11] => Mux0.IN1024
|
|
addr_i[11] => Mux1.IN1024
|
|
addr_i[11] => Mux2.IN1024
|
|
addr_i[11] => Mux3.IN1024
|
|
addr_i[11] => Mux4.IN1024
|
|
addr_i[11] => Mux5.IN1024
|
|
addr_i[11] => Mux6.IN1024
|
|
addr_i[11] => Mux7.IN1024
|
|
addr_i[11] => Mux8.IN1024
|
|
addr_i[11] => Mux9.IN1024
|
|
addr_i[11] => Mux10.IN1024
|
|
addr_i[11] => Mux11.IN1024
|
|
addr_i[11] => Mux12.IN1024
|
|
addr_i[11] => Mux13.IN1024
|
|
addr_i[11] => Mux14.IN1024
|
|
addr_i[11] => Mux15.IN1024
|
|
addr_i[11] => Mux16.IN1024
|
|
addr_i[11] => Mux17.IN1024
|
|
addr_i[11] => Mux18.IN1024
|
|
addr_i[11] => Mux19.IN1024
|
|
addr_i[11] => Mux20.IN1024
|
|
addr_i[11] => Mux21.IN1024
|
|
addr_i[11] => Mux22.IN1024
|
|
addr_i[11] => Mux23.IN1024
|
|
addr_i[11] => Mux24.IN1024
|
|
addr_i[11] => Mux25.IN1024
|
|
addr_i[11] => Mux26.IN1024
|
|
addr_i[11] => Mux27.IN1024
|
|
addr_i[11] => Mux28.IN1024
|
|
addr_i[11] => Mux29.IN1024
|
|
addr_i[11] => Mux30.IN1024
|
|
addr_i[11] => Mux31.IN1024
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => Equal0.IN0
|
|
addr_i[16] => Equal0.IN16
|
|
addr_i[17] => Equal0.IN15
|
|
addr_i[18] => Equal0.IN14
|
|
addr_i[19] => Equal0.IN13
|
|
addr_i[20] => Equal0.IN12
|
|
addr_i[21] => Equal0.IN11
|
|
addr_i[22] => Equal0.IN10
|
|
addr_i[23] => Equal0.IN9
|
|
addr_i[24] => Equal0.IN8
|
|
addr_i[25] => Equal0.IN7
|
|
addr_i[26] => Equal0.IN6
|
|
addr_i[27] => Equal0.IN5
|
|
addr_i[28] => Equal0.IN4
|
|
addr_i[29] => Equal0.IN3
|
|
addr_i[30] => Equal0.IN2
|
|
addr_i[31] => Equal0.IN1
|
|
data_o[0] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= rden.DB_MAX_OUTPUT_PORT_TYPE
|
|
err_o <= err_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_gpio:\neorv32_gpio_inst_true:neorv32_gpio_inst
|
|
clk_i => din_hi[0].CLK
|
|
clk_i => din_hi[1].CLK
|
|
clk_i => din_hi[2].CLK
|
|
clk_i => din_hi[3].CLK
|
|
clk_i => din_hi[4].CLK
|
|
clk_i => din_hi[5].CLK
|
|
clk_i => din_hi[6].CLK
|
|
clk_i => din_hi[7].CLK
|
|
clk_i => din_hi[8].CLK
|
|
clk_i => din_hi[9].CLK
|
|
clk_i => din_hi[10].CLK
|
|
clk_i => din_hi[11].CLK
|
|
clk_i => din_hi[12].CLK
|
|
clk_i => din_hi[13].CLK
|
|
clk_i => din_hi[14].CLK
|
|
clk_i => din_hi[15].CLK
|
|
clk_i => din_hi[16].CLK
|
|
clk_i => din_hi[17].CLK
|
|
clk_i => din_hi[18].CLK
|
|
clk_i => din_hi[19].CLK
|
|
clk_i => din_hi[20].CLK
|
|
clk_i => din_hi[21].CLK
|
|
clk_i => din_hi[22].CLK
|
|
clk_i => din_hi[23].CLK
|
|
clk_i => din_hi[24].CLK
|
|
clk_i => din_hi[25].CLK
|
|
clk_i => din_hi[26].CLK
|
|
clk_i => din_hi[27].CLK
|
|
clk_i => din_hi[28].CLK
|
|
clk_i => din_hi[29].CLK
|
|
clk_i => din_hi[30].CLK
|
|
clk_i => din_hi[31].CLK
|
|
clk_i => din_lo[0].CLK
|
|
clk_i => din_lo[1].CLK
|
|
clk_i => din_lo[2].CLK
|
|
clk_i => din_lo[3].CLK
|
|
clk_i => din_lo[4].CLK
|
|
clk_i => din_lo[5].CLK
|
|
clk_i => din_lo[6].CLK
|
|
clk_i => din_lo[7].CLK
|
|
clk_i => din_lo[8].CLK
|
|
clk_i => din_lo[9].CLK
|
|
clk_i => din_lo[10].CLK
|
|
clk_i => din_lo[11].CLK
|
|
clk_i => din_lo[12].CLK
|
|
clk_i => din_lo[13].CLK
|
|
clk_i => din_lo[14].CLK
|
|
clk_i => din_lo[15].CLK
|
|
clk_i => din_lo[16].CLK
|
|
clk_i => din_lo[17].CLK
|
|
clk_i => din_lo[18].CLK
|
|
clk_i => din_lo[19].CLK
|
|
clk_i => din_lo[20].CLK
|
|
clk_i => din_lo[21].CLK
|
|
clk_i => din_lo[22].CLK
|
|
clk_i => din_lo[23].CLK
|
|
clk_i => din_lo[24].CLK
|
|
clk_i => din_lo[25].CLK
|
|
clk_i => din_lo[26].CLK
|
|
clk_i => din_lo[27].CLK
|
|
clk_i => din_lo[28].CLK
|
|
clk_i => din_lo[29].CLK
|
|
clk_i => din_lo[30].CLK
|
|
clk_i => din_lo[31].CLK
|
|
clk_i => data_o[0]~reg0.CLK
|
|
clk_i => data_o[1]~reg0.CLK
|
|
clk_i => data_o[2]~reg0.CLK
|
|
clk_i => data_o[3]~reg0.CLK
|
|
clk_i => data_o[4]~reg0.CLK
|
|
clk_i => data_o[5]~reg0.CLK
|
|
clk_i => data_o[6]~reg0.CLK
|
|
clk_i => data_o[7]~reg0.CLK
|
|
clk_i => data_o[8]~reg0.CLK
|
|
clk_i => data_o[9]~reg0.CLK
|
|
clk_i => data_o[10]~reg0.CLK
|
|
clk_i => data_o[11]~reg0.CLK
|
|
clk_i => data_o[12]~reg0.CLK
|
|
clk_i => data_o[13]~reg0.CLK
|
|
clk_i => data_o[14]~reg0.CLK
|
|
clk_i => data_o[15]~reg0.CLK
|
|
clk_i => data_o[16]~reg0.CLK
|
|
clk_i => data_o[17]~reg0.CLK
|
|
clk_i => data_o[18]~reg0.CLK
|
|
clk_i => data_o[19]~reg0.CLK
|
|
clk_i => data_o[20]~reg0.CLK
|
|
clk_i => data_o[21]~reg0.CLK
|
|
clk_i => data_o[22]~reg0.CLK
|
|
clk_i => data_o[23]~reg0.CLK
|
|
clk_i => data_o[24]~reg0.CLK
|
|
clk_i => data_o[25]~reg0.CLK
|
|
clk_i => data_o[26]~reg0.CLK
|
|
clk_i => data_o[27]~reg0.CLK
|
|
clk_i => data_o[28]~reg0.CLK
|
|
clk_i => data_o[29]~reg0.CLK
|
|
clk_i => data_o[30]~reg0.CLK
|
|
clk_i => data_o[31]~reg0.CLK
|
|
clk_i => err_o~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => dout_hi[0].CLK
|
|
clk_i => dout_hi[1].CLK
|
|
clk_i => dout_hi[2].CLK
|
|
clk_i => dout_hi[3].CLK
|
|
clk_i => dout_hi[4].CLK
|
|
clk_i => dout_hi[5].CLK
|
|
clk_i => dout_hi[6].CLK
|
|
clk_i => dout_hi[7].CLK
|
|
clk_i => dout_hi[8].CLK
|
|
clk_i => dout_hi[9].CLK
|
|
clk_i => dout_hi[10].CLK
|
|
clk_i => dout_hi[11].CLK
|
|
clk_i => dout_hi[12].CLK
|
|
clk_i => dout_hi[13].CLK
|
|
clk_i => dout_hi[14].CLK
|
|
clk_i => dout_hi[15].CLK
|
|
clk_i => dout_hi[16].CLK
|
|
clk_i => dout_hi[17].CLK
|
|
clk_i => dout_hi[18].CLK
|
|
clk_i => dout_hi[19].CLK
|
|
clk_i => dout_hi[20].CLK
|
|
clk_i => dout_hi[21].CLK
|
|
clk_i => dout_hi[22].CLK
|
|
clk_i => dout_hi[23].CLK
|
|
clk_i => dout_hi[24].CLK
|
|
clk_i => dout_hi[25].CLK
|
|
clk_i => dout_hi[26].CLK
|
|
clk_i => dout_hi[27].CLK
|
|
clk_i => dout_hi[28].CLK
|
|
clk_i => dout_hi[29].CLK
|
|
clk_i => dout_hi[30].CLK
|
|
clk_i => dout_hi[31].CLK
|
|
clk_i => dout_lo[0].CLK
|
|
clk_i => dout_lo[1].CLK
|
|
clk_i => dout_lo[2].CLK
|
|
clk_i => dout_lo[3].CLK
|
|
clk_i => dout_lo[4].CLK
|
|
clk_i => dout_lo[5].CLK
|
|
clk_i => dout_lo[6].CLK
|
|
clk_i => dout_lo[7].CLK
|
|
clk_i => dout_lo[8].CLK
|
|
clk_i => dout_lo[9].CLK
|
|
clk_i => dout_lo[10].CLK
|
|
clk_i => dout_lo[11].CLK
|
|
clk_i => dout_lo[12].CLK
|
|
clk_i => dout_lo[13].CLK
|
|
clk_i => dout_lo[14].CLK
|
|
clk_i => dout_lo[15].CLK
|
|
clk_i => dout_lo[16].CLK
|
|
clk_i => dout_lo[17].CLK
|
|
clk_i => dout_lo[18].CLK
|
|
clk_i => dout_lo[19].CLK
|
|
clk_i => dout_lo[20].CLK
|
|
clk_i => dout_lo[21].CLK
|
|
clk_i => dout_lo[22].CLK
|
|
clk_i => dout_lo[23].CLK
|
|
clk_i => dout_lo[24].CLK
|
|
clk_i => dout_lo[25].CLK
|
|
clk_i => dout_lo[26].CLK
|
|
clk_i => dout_lo[27].CLK
|
|
clk_i => dout_lo[28].CLK
|
|
clk_i => dout_lo[29].CLK
|
|
clk_i => dout_lo[30].CLK
|
|
clk_i => dout_lo[31].CLK
|
|
rstn_i => dout_hi[0].ACLR
|
|
rstn_i => dout_hi[1].ACLR
|
|
rstn_i => dout_hi[2].ACLR
|
|
rstn_i => dout_hi[3].ACLR
|
|
rstn_i => dout_hi[4].ACLR
|
|
rstn_i => dout_hi[5].ACLR
|
|
rstn_i => dout_hi[6].ACLR
|
|
rstn_i => dout_hi[7].ACLR
|
|
rstn_i => dout_hi[8].ACLR
|
|
rstn_i => dout_hi[9].ACLR
|
|
rstn_i => dout_hi[10].ACLR
|
|
rstn_i => dout_hi[11].ACLR
|
|
rstn_i => dout_hi[12].ACLR
|
|
rstn_i => dout_hi[13].ACLR
|
|
rstn_i => dout_hi[14].ACLR
|
|
rstn_i => dout_hi[15].ACLR
|
|
rstn_i => dout_hi[16].ACLR
|
|
rstn_i => dout_hi[17].ACLR
|
|
rstn_i => dout_hi[18].ACLR
|
|
rstn_i => dout_hi[19].ACLR
|
|
rstn_i => dout_hi[20].ACLR
|
|
rstn_i => dout_hi[21].ACLR
|
|
rstn_i => dout_hi[22].ACLR
|
|
rstn_i => dout_hi[23].ACLR
|
|
rstn_i => dout_hi[24].ACLR
|
|
rstn_i => dout_hi[25].ACLR
|
|
rstn_i => dout_hi[26].ACLR
|
|
rstn_i => dout_hi[27].ACLR
|
|
rstn_i => dout_hi[28].ACLR
|
|
rstn_i => dout_hi[29].ACLR
|
|
rstn_i => dout_hi[30].ACLR
|
|
rstn_i => dout_hi[31].ACLR
|
|
rstn_i => dout_lo[0].ACLR
|
|
rstn_i => dout_lo[1].ACLR
|
|
rstn_i => dout_lo[2].ACLR
|
|
rstn_i => dout_lo[3].ACLR
|
|
rstn_i => dout_lo[4].ACLR
|
|
rstn_i => dout_lo[5].ACLR
|
|
rstn_i => dout_lo[6].ACLR
|
|
rstn_i => dout_lo[7].ACLR
|
|
rstn_i => dout_lo[8].ACLR
|
|
rstn_i => dout_lo[9].ACLR
|
|
rstn_i => dout_lo[10].ACLR
|
|
rstn_i => dout_lo[11].ACLR
|
|
rstn_i => dout_lo[12].ACLR
|
|
rstn_i => dout_lo[13].ACLR
|
|
rstn_i => dout_lo[14].ACLR
|
|
rstn_i => dout_lo[15].ACLR
|
|
rstn_i => dout_lo[16].ACLR
|
|
rstn_i => dout_lo[17].ACLR
|
|
rstn_i => dout_lo[18].ACLR
|
|
rstn_i => dout_lo[19].ACLR
|
|
rstn_i => dout_lo[20].ACLR
|
|
rstn_i => dout_lo[21].ACLR
|
|
rstn_i => dout_lo[22].ACLR
|
|
rstn_i => dout_lo[23].ACLR
|
|
rstn_i => dout_lo[24].ACLR
|
|
rstn_i => dout_lo[25].ACLR
|
|
rstn_i => dout_lo[26].ACLR
|
|
rstn_i => dout_lo[27].ACLR
|
|
rstn_i => dout_lo[28].ACLR
|
|
rstn_i => dout_lo[29].ACLR
|
|
rstn_i => dout_lo[30].ACLR
|
|
rstn_i => dout_lo[31].ACLR
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => Mux0.IN1
|
|
addr_i[2] => Mux1.IN1
|
|
addr_i[2] => Mux2.IN1
|
|
addr_i[2] => Mux3.IN1
|
|
addr_i[2] => Mux4.IN1
|
|
addr_i[2] => Mux5.IN1
|
|
addr_i[2] => Mux6.IN1
|
|
addr_i[2] => Mux7.IN1
|
|
addr_i[2] => Mux8.IN1
|
|
addr_i[2] => Mux9.IN1
|
|
addr_i[2] => Mux10.IN1
|
|
addr_i[2] => Mux11.IN1
|
|
addr_i[2] => Mux12.IN1
|
|
addr_i[2] => Mux13.IN1
|
|
addr_i[2] => Mux14.IN1
|
|
addr_i[2] => Mux15.IN1
|
|
addr_i[2] => Mux16.IN1
|
|
addr_i[2] => Mux17.IN1
|
|
addr_i[2] => Mux18.IN1
|
|
addr_i[2] => Mux19.IN1
|
|
addr_i[2] => Mux20.IN1
|
|
addr_i[2] => Mux21.IN1
|
|
addr_i[2] => Mux22.IN1
|
|
addr_i[2] => Mux23.IN1
|
|
addr_i[2] => Mux24.IN1
|
|
addr_i[2] => Mux25.IN1
|
|
addr_i[2] => Mux26.IN1
|
|
addr_i[2] => Mux27.IN1
|
|
addr_i[2] => Mux28.IN1
|
|
addr_i[2] => Mux29.IN1
|
|
addr_i[2] => Mux30.IN1
|
|
addr_i[2] => Mux31.IN1
|
|
addr_i[2] => Equal1.IN56
|
|
addr_i[2] => Equal2.IN28
|
|
addr_i[3] => ack_o.IN1
|
|
addr_i[3] => Mux0.IN0
|
|
addr_i[3] => Mux1.IN0
|
|
addr_i[3] => Mux2.IN0
|
|
addr_i[3] => Mux3.IN0
|
|
addr_i[3] => Mux4.IN0
|
|
addr_i[3] => Mux5.IN0
|
|
addr_i[3] => Mux6.IN0
|
|
addr_i[3] => Mux7.IN0
|
|
addr_i[3] => Mux8.IN0
|
|
addr_i[3] => Mux9.IN0
|
|
addr_i[3] => Mux10.IN0
|
|
addr_i[3] => Mux11.IN0
|
|
addr_i[3] => Mux12.IN0
|
|
addr_i[3] => Mux13.IN0
|
|
addr_i[3] => Mux14.IN0
|
|
addr_i[3] => Mux15.IN0
|
|
addr_i[3] => Mux16.IN0
|
|
addr_i[3] => Mux17.IN0
|
|
addr_i[3] => Mux18.IN0
|
|
addr_i[3] => Mux19.IN0
|
|
addr_i[3] => Mux20.IN0
|
|
addr_i[3] => Mux21.IN0
|
|
addr_i[3] => Mux22.IN0
|
|
addr_i[3] => Mux23.IN0
|
|
addr_i[3] => Mux24.IN0
|
|
addr_i[3] => Mux25.IN0
|
|
addr_i[3] => Mux26.IN0
|
|
addr_i[3] => Mux27.IN0
|
|
addr_i[3] => Mux28.IN0
|
|
addr_i[3] => Mux29.IN0
|
|
addr_i[3] => Mux30.IN0
|
|
addr_i[3] => Mux31.IN0
|
|
addr_i[3] => Equal1.IN27
|
|
addr_i[3] => Equal2.IN27
|
|
addr_i[3] => err_o.IN1
|
|
addr_i[4] => Equal0.IN4
|
|
addr_i[5] => Equal0.IN3
|
|
addr_i[6] => Equal0.IN2
|
|
addr_i[7] => Equal0.IN1
|
|
addr_i[8] => Equal0.IN0
|
|
addr_i[9] => ~NO_FANOUT~
|
|
addr_i[10] => ~NO_FANOUT~
|
|
addr_i[11] => ~NO_FANOUT~
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => ~NO_FANOUT~
|
|
addr_i[16] => ~NO_FANOUT~
|
|
addr_i[17] => ~NO_FANOUT~
|
|
addr_i[18] => ~NO_FANOUT~
|
|
addr_i[19] => ~NO_FANOUT~
|
|
addr_i[20] => ~NO_FANOUT~
|
|
addr_i[21] => ~NO_FANOUT~
|
|
addr_i[22] => ~NO_FANOUT~
|
|
addr_i[23] => ~NO_FANOUT~
|
|
addr_i[24] => ~NO_FANOUT~
|
|
addr_i[25] => ~NO_FANOUT~
|
|
addr_i[26] => ~NO_FANOUT~
|
|
addr_i[27] => ~NO_FANOUT~
|
|
addr_i[28] => ~NO_FANOUT~
|
|
addr_i[29] => ~NO_FANOUT~
|
|
addr_i[30] => ~NO_FANOUT~
|
|
addr_i[31] => ~NO_FANOUT~
|
|
rden_i => rden.IN1
|
|
wren_i => wren.IN1
|
|
data_i[0] => dout_lo.DATAB
|
|
data_i[0] => dout_hi.DATAB
|
|
data_i[1] => dout_lo.DATAB
|
|
data_i[1] => dout_hi.DATAB
|
|
data_i[2] => dout_lo.DATAB
|
|
data_i[2] => dout_hi.DATAB
|
|
data_i[3] => dout_lo.DATAB
|
|
data_i[3] => dout_hi.DATAB
|
|
data_i[4] => dout_lo.DATAB
|
|
data_i[4] => dout_hi.DATAB
|
|
data_i[5] => dout_lo.DATAB
|
|
data_i[5] => dout_hi.DATAB
|
|
data_i[6] => dout_lo.DATAB
|
|
data_i[6] => dout_hi.DATAB
|
|
data_i[7] => dout_lo.DATAB
|
|
data_i[7] => dout_hi.DATAB
|
|
data_i[8] => dout_lo.DATAB
|
|
data_i[8] => dout_hi.DATAB
|
|
data_i[9] => dout_lo.DATAB
|
|
data_i[9] => dout_hi.DATAB
|
|
data_i[10] => dout_lo.DATAB
|
|
data_i[10] => dout_hi.DATAB
|
|
data_i[11] => dout_lo.DATAB
|
|
data_i[11] => dout_hi.DATAB
|
|
data_i[12] => dout_lo.DATAB
|
|
data_i[12] => dout_hi.DATAB
|
|
data_i[13] => dout_lo.DATAB
|
|
data_i[13] => dout_hi.DATAB
|
|
data_i[14] => dout_lo.DATAB
|
|
data_i[14] => dout_hi.DATAB
|
|
data_i[15] => dout_lo.DATAB
|
|
data_i[15] => dout_hi.DATAB
|
|
data_i[16] => dout_lo.DATAB
|
|
data_i[16] => dout_hi.DATAB
|
|
data_i[17] => dout_lo.DATAB
|
|
data_i[17] => dout_hi.DATAB
|
|
data_i[18] => dout_lo.DATAB
|
|
data_i[18] => dout_hi.DATAB
|
|
data_i[19] => dout_lo.DATAB
|
|
data_i[19] => dout_hi.DATAB
|
|
data_i[20] => dout_lo.DATAB
|
|
data_i[20] => dout_hi.DATAB
|
|
data_i[21] => dout_lo.DATAB
|
|
data_i[21] => dout_hi.DATAB
|
|
data_i[22] => dout_lo.DATAB
|
|
data_i[22] => dout_hi.DATAB
|
|
data_i[23] => dout_lo.DATAB
|
|
data_i[23] => dout_hi.DATAB
|
|
data_i[24] => dout_lo.DATAB
|
|
data_i[24] => dout_hi.DATAB
|
|
data_i[25] => dout_lo.DATAB
|
|
data_i[25] => dout_hi.DATAB
|
|
data_i[26] => dout_lo.DATAB
|
|
data_i[26] => dout_hi.DATAB
|
|
data_i[27] => dout_lo.DATAB
|
|
data_i[27] => dout_hi.DATAB
|
|
data_i[28] => dout_lo.DATAB
|
|
data_i[28] => dout_hi.DATAB
|
|
data_i[29] => dout_lo.DATAB
|
|
data_i[29] => dout_hi.DATAB
|
|
data_i[30] => dout_lo.DATAB
|
|
data_i[30] => dout_hi.DATAB
|
|
data_i[31] => dout_lo.DATAB
|
|
data_i[31] => dout_hi.DATAB
|
|
data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
err_o <= err_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[0] <= dout_lo[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[1] <= dout_lo[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[2] <= dout_lo[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[3] <= dout_lo[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[4] <= dout_lo[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[5] <= dout_lo[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[6] <= dout_lo[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[7] <= dout_lo[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[8] <= dout_lo[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[9] <= dout_lo[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[10] <= dout_lo[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[11] <= dout_lo[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[12] <= dout_lo[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[13] <= dout_lo[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[14] <= dout_lo[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[15] <= dout_lo[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[16] <= dout_lo[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[17] <= dout_lo[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[18] <= dout_lo[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[19] <= dout_lo[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[20] <= dout_lo[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[21] <= dout_lo[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[22] <= dout_lo[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[23] <= dout_lo[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[24] <= dout_lo[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[25] <= dout_lo[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[26] <= dout_lo[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[27] <= dout_lo[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[28] <= dout_lo[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[29] <= dout_lo[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[30] <= dout_lo[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[31] <= dout_lo[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[32] <= dout_hi[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[33] <= dout_hi[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[34] <= dout_hi[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[35] <= dout_hi[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[36] <= dout_hi[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[37] <= dout_hi[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[38] <= dout_hi[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[39] <= dout_hi[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[40] <= dout_hi[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[41] <= dout_hi[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[42] <= dout_hi[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[43] <= dout_hi[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[44] <= dout_hi[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[45] <= dout_hi[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[46] <= dout_hi[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[47] <= dout_hi[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[48] <= dout_hi[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[49] <= dout_hi[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[50] <= dout_hi[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[51] <= dout_hi[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[52] <= dout_hi[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[53] <= dout_hi[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[54] <= dout_hi[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[55] <= dout_hi[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[56] <= dout_hi[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[57] <= dout_hi[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[58] <= dout_hi[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[59] <= dout_hi[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[60] <= dout_hi[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[61] <= dout_hi[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[62] <= dout_hi[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_o[63] <= dout_hi[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
gpio_i[0] => din_lo[0].DATAIN
|
|
gpio_i[1] => din_lo[1].DATAIN
|
|
gpio_i[2] => din_lo[2].DATAIN
|
|
gpio_i[3] => din_lo[3].DATAIN
|
|
gpio_i[4] => din_lo[4].DATAIN
|
|
gpio_i[5] => din_lo[5].DATAIN
|
|
gpio_i[6] => din_lo[6].DATAIN
|
|
gpio_i[7] => din_lo[7].DATAIN
|
|
gpio_i[8] => din_lo[8].DATAIN
|
|
gpio_i[9] => din_lo[9].DATAIN
|
|
gpio_i[10] => din_lo[10].DATAIN
|
|
gpio_i[11] => din_lo[11].DATAIN
|
|
gpio_i[12] => din_lo[12].DATAIN
|
|
gpio_i[13] => din_lo[13].DATAIN
|
|
gpio_i[14] => din_lo[14].DATAIN
|
|
gpio_i[15] => din_lo[15].DATAIN
|
|
gpio_i[16] => din_lo[16].DATAIN
|
|
gpio_i[17] => din_lo[17].DATAIN
|
|
gpio_i[18] => din_lo[18].DATAIN
|
|
gpio_i[19] => din_lo[19].DATAIN
|
|
gpio_i[20] => din_lo[20].DATAIN
|
|
gpio_i[21] => din_lo[21].DATAIN
|
|
gpio_i[22] => din_lo[22].DATAIN
|
|
gpio_i[23] => din_lo[23].DATAIN
|
|
gpio_i[24] => din_lo[24].DATAIN
|
|
gpio_i[25] => din_lo[25].DATAIN
|
|
gpio_i[26] => din_lo[26].DATAIN
|
|
gpio_i[27] => din_lo[27].DATAIN
|
|
gpio_i[28] => din_lo[28].DATAIN
|
|
gpio_i[29] => din_lo[29].DATAIN
|
|
gpio_i[30] => din_lo[30].DATAIN
|
|
gpio_i[31] => din_lo[31].DATAIN
|
|
gpio_i[32] => din_hi[0].DATAIN
|
|
gpio_i[33] => din_hi[1].DATAIN
|
|
gpio_i[34] => din_hi[2].DATAIN
|
|
gpio_i[35] => din_hi[3].DATAIN
|
|
gpio_i[36] => din_hi[4].DATAIN
|
|
gpio_i[37] => din_hi[5].DATAIN
|
|
gpio_i[38] => din_hi[6].DATAIN
|
|
gpio_i[39] => din_hi[7].DATAIN
|
|
gpio_i[40] => din_hi[8].DATAIN
|
|
gpio_i[41] => din_hi[9].DATAIN
|
|
gpio_i[42] => din_hi[10].DATAIN
|
|
gpio_i[43] => din_hi[11].DATAIN
|
|
gpio_i[44] => din_hi[12].DATAIN
|
|
gpio_i[45] => din_hi[13].DATAIN
|
|
gpio_i[46] => din_hi[14].DATAIN
|
|
gpio_i[47] => din_hi[15].DATAIN
|
|
gpio_i[48] => din_hi[16].DATAIN
|
|
gpio_i[49] => din_hi[17].DATAIN
|
|
gpio_i[50] => din_hi[18].DATAIN
|
|
gpio_i[51] => din_hi[19].DATAIN
|
|
gpio_i[52] => din_hi[20].DATAIN
|
|
gpio_i[53] => din_hi[21].DATAIN
|
|
gpio_i[54] => din_hi[22].DATAIN
|
|
gpio_i[55] => din_hi[23].DATAIN
|
|
gpio_i[56] => din_hi[24].DATAIN
|
|
gpio_i[57] => din_hi[25].DATAIN
|
|
gpio_i[58] => din_hi[26].DATAIN
|
|
gpio_i[59] => din_hi[27].DATAIN
|
|
gpio_i[60] => din_hi[28].DATAIN
|
|
gpio_i[61] => din_hi[29].DATAIN
|
|
gpio_i[62] => din_hi[30].DATAIN
|
|
gpio_i[63] => din_hi[31].DATAIN
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_mtime:\neorv32_mtime_inst_true:neorv32_mtime_inst
|
|
clk_i => irq_o~reg0.CLK
|
|
clk_i => cmp_lo_ge_ff.CLK
|
|
clk_i => data_o[0]~reg0.CLK
|
|
clk_i => data_o[1]~reg0.CLK
|
|
clk_i => data_o[2]~reg0.CLK
|
|
clk_i => data_o[3]~reg0.CLK
|
|
clk_i => data_o[4]~reg0.CLK
|
|
clk_i => data_o[5]~reg0.CLK
|
|
clk_i => data_o[6]~reg0.CLK
|
|
clk_i => data_o[7]~reg0.CLK
|
|
clk_i => data_o[8]~reg0.CLK
|
|
clk_i => data_o[9]~reg0.CLK
|
|
clk_i => data_o[10]~reg0.CLK
|
|
clk_i => data_o[11]~reg0.CLK
|
|
clk_i => data_o[12]~reg0.CLK
|
|
clk_i => data_o[13]~reg0.CLK
|
|
clk_i => data_o[14]~reg0.CLK
|
|
clk_i => data_o[15]~reg0.CLK
|
|
clk_i => data_o[16]~reg0.CLK
|
|
clk_i => data_o[17]~reg0.CLK
|
|
clk_i => data_o[18]~reg0.CLK
|
|
clk_i => data_o[19]~reg0.CLK
|
|
clk_i => data_o[20]~reg0.CLK
|
|
clk_i => data_o[21]~reg0.CLK
|
|
clk_i => data_o[22]~reg0.CLK
|
|
clk_i => data_o[23]~reg0.CLK
|
|
clk_i => data_o[24]~reg0.CLK
|
|
clk_i => data_o[25]~reg0.CLK
|
|
clk_i => data_o[26]~reg0.CLK
|
|
clk_i => data_o[27]~reg0.CLK
|
|
clk_i => data_o[28]~reg0.CLK
|
|
clk_i => data_o[29]~reg0.CLK
|
|
clk_i => data_o[30]~reg0.CLK
|
|
clk_i => data_o[31]~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => mtime_hi[0].CLK
|
|
clk_i => mtime_hi[1].CLK
|
|
clk_i => mtime_hi[2].CLK
|
|
clk_i => mtime_hi[3].CLK
|
|
clk_i => mtime_hi[4].CLK
|
|
clk_i => mtime_hi[5].CLK
|
|
clk_i => mtime_hi[6].CLK
|
|
clk_i => mtime_hi[7].CLK
|
|
clk_i => mtime_hi[8].CLK
|
|
clk_i => mtime_hi[9].CLK
|
|
clk_i => mtime_hi[10].CLK
|
|
clk_i => mtime_hi[11].CLK
|
|
clk_i => mtime_hi[12].CLK
|
|
clk_i => mtime_hi[13].CLK
|
|
clk_i => mtime_hi[14].CLK
|
|
clk_i => mtime_hi[15].CLK
|
|
clk_i => mtime_hi[16].CLK
|
|
clk_i => mtime_hi[17].CLK
|
|
clk_i => mtime_hi[18].CLK
|
|
clk_i => mtime_hi[19].CLK
|
|
clk_i => mtime_hi[20].CLK
|
|
clk_i => mtime_hi[21].CLK
|
|
clk_i => mtime_hi[22].CLK
|
|
clk_i => mtime_hi[23].CLK
|
|
clk_i => mtime_hi[24].CLK
|
|
clk_i => mtime_hi[25].CLK
|
|
clk_i => mtime_hi[26].CLK
|
|
clk_i => mtime_hi[27].CLK
|
|
clk_i => mtime_hi[28].CLK
|
|
clk_i => mtime_hi[29].CLK
|
|
clk_i => mtime_hi[30].CLK
|
|
clk_i => mtime_hi[31].CLK
|
|
clk_i => mtime_lo_ovfl[0].CLK
|
|
clk_i => mtime_lo[0].CLK
|
|
clk_i => mtime_lo[1].CLK
|
|
clk_i => mtime_lo[2].CLK
|
|
clk_i => mtime_lo[3].CLK
|
|
clk_i => mtime_lo[4].CLK
|
|
clk_i => mtime_lo[5].CLK
|
|
clk_i => mtime_lo[6].CLK
|
|
clk_i => mtime_lo[7].CLK
|
|
clk_i => mtime_lo[8].CLK
|
|
clk_i => mtime_lo[9].CLK
|
|
clk_i => mtime_lo[10].CLK
|
|
clk_i => mtime_lo[11].CLK
|
|
clk_i => mtime_lo[12].CLK
|
|
clk_i => mtime_lo[13].CLK
|
|
clk_i => mtime_lo[14].CLK
|
|
clk_i => mtime_lo[15].CLK
|
|
clk_i => mtime_lo[16].CLK
|
|
clk_i => mtime_lo[17].CLK
|
|
clk_i => mtime_lo[18].CLK
|
|
clk_i => mtime_lo[19].CLK
|
|
clk_i => mtime_lo[20].CLK
|
|
clk_i => mtime_lo[21].CLK
|
|
clk_i => mtime_lo[22].CLK
|
|
clk_i => mtime_lo[23].CLK
|
|
clk_i => mtime_lo[24].CLK
|
|
clk_i => mtime_lo[25].CLK
|
|
clk_i => mtime_lo[26].CLK
|
|
clk_i => mtime_lo[27].CLK
|
|
clk_i => mtime_lo[28].CLK
|
|
clk_i => mtime_lo[29].CLK
|
|
clk_i => mtime_lo[30].CLK
|
|
clk_i => mtime_lo[31].CLK
|
|
clk_i => mtime_hi_we.CLK
|
|
clk_i => mtime_lo_we.CLK
|
|
clk_i => mtimecmp_hi[0].CLK
|
|
clk_i => mtimecmp_hi[1].CLK
|
|
clk_i => mtimecmp_hi[2].CLK
|
|
clk_i => mtimecmp_hi[3].CLK
|
|
clk_i => mtimecmp_hi[4].CLK
|
|
clk_i => mtimecmp_hi[5].CLK
|
|
clk_i => mtimecmp_hi[6].CLK
|
|
clk_i => mtimecmp_hi[7].CLK
|
|
clk_i => mtimecmp_hi[8].CLK
|
|
clk_i => mtimecmp_hi[9].CLK
|
|
clk_i => mtimecmp_hi[10].CLK
|
|
clk_i => mtimecmp_hi[11].CLK
|
|
clk_i => mtimecmp_hi[12].CLK
|
|
clk_i => mtimecmp_hi[13].CLK
|
|
clk_i => mtimecmp_hi[14].CLK
|
|
clk_i => mtimecmp_hi[15].CLK
|
|
clk_i => mtimecmp_hi[16].CLK
|
|
clk_i => mtimecmp_hi[17].CLK
|
|
clk_i => mtimecmp_hi[18].CLK
|
|
clk_i => mtimecmp_hi[19].CLK
|
|
clk_i => mtimecmp_hi[20].CLK
|
|
clk_i => mtimecmp_hi[21].CLK
|
|
clk_i => mtimecmp_hi[22].CLK
|
|
clk_i => mtimecmp_hi[23].CLK
|
|
clk_i => mtimecmp_hi[24].CLK
|
|
clk_i => mtimecmp_hi[25].CLK
|
|
clk_i => mtimecmp_hi[26].CLK
|
|
clk_i => mtimecmp_hi[27].CLK
|
|
clk_i => mtimecmp_hi[28].CLK
|
|
clk_i => mtimecmp_hi[29].CLK
|
|
clk_i => mtimecmp_hi[30].CLK
|
|
clk_i => mtimecmp_hi[31].CLK
|
|
clk_i => mtimecmp_lo[0].CLK
|
|
clk_i => mtimecmp_lo[1].CLK
|
|
clk_i => mtimecmp_lo[2].CLK
|
|
clk_i => mtimecmp_lo[3].CLK
|
|
clk_i => mtimecmp_lo[4].CLK
|
|
clk_i => mtimecmp_lo[5].CLK
|
|
clk_i => mtimecmp_lo[6].CLK
|
|
clk_i => mtimecmp_lo[7].CLK
|
|
clk_i => mtimecmp_lo[8].CLK
|
|
clk_i => mtimecmp_lo[9].CLK
|
|
clk_i => mtimecmp_lo[10].CLK
|
|
clk_i => mtimecmp_lo[11].CLK
|
|
clk_i => mtimecmp_lo[12].CLK
|
|
clk_i => mtimecmp_lo[13].CLK
|
|
clk_i => mtimecmp_lo[14].CLK
|
|
clk_i => mtimecmp_lo[15].CLK
|
|
clk_i => mtimecmp_lo[16].CLK
|
|
clk_i => mtimecmp_lo[17].CLK
|
|
clk_i => mtimecmp_lo[18].CLK
|
|
clk_i => mtimecmp_lo[19].CLK
|
|
clk_i => mtimecmp_lo[20].CLK
|
|
clk_i => mtimecmp_lo[21].CLK
|
|
clk_i => mtimecmp_lo[22].CLK
|
|
clk_i => mtimecmp_lo[23].CLK
|
|
clk_i => mtimecmp_lo[24].CLK
|
|
clk_i => mtimecmp_lo[25].CLK
|
|
clk_i => mtimecmp_lo[26].CLK
|
|
clk_i => mtimecmp_lo[27].CLK
|
|
clk_i => mtimecmp_lo[28].CLK
|
|
clk_i => mtimecmp_lo[29].CLK
|
|
clk_i => mtimecmp_lo[30].CLK
|
|
clk_i => mtimecmp_lo[31].CLK
|
|
rstn_i => mtime_hi[0].ACLR
|
|
rstn_i => mtime_hi[1].ACLR
|
|
rstn_i => mtime_hi[2].ACLR
|
|
rstn_i => mtime_hi[3].ACLR
|
|
rstn_i => mtime_hi[4].ACLR
|
|
rstn_i => mtime_hi[5].ACLR
|
|
rstn_i => mtime_hi[6].ACLR
|
|
rstn_i => mtime_hi[7].ACLR
|
|
rstn_i => mtime_hi[8].ACLR
|
|
rstn_i => mtime_hi[9].ACLR
|
|
rstn_i => mtime_hi[10].ACLR
|
|
rstn_i => mtime_hi[11].ACLR
|
|
rstn_i => mtime_hi[12].ACLR
|
|
rstn_i => mtime_hi[13].ACLR
|
|
rstn_i => mtime_hi[14].ACLR
|
|
rstn_i => mtime_hi[15].ACLR
|
|
rstn_i => mtime_hi[16].ACLR
|
|
rstn_i => mtime_hi[17].ACLR
|
|
rstn_i => mtime_hi[18].ACLR
|
|
rstn_i => mtime_hi[19].ACLR
|
|
rstn_i => mtime_hi[20].ACLR
|
|
rstn_i => mtime_hi[21].ACLR
|
|
rstn_i => mtime_hi[22].ACLR
|
|
rstn_i => mtime_hi[23].ACLR
|
|
rstn_i => mtime_hi[24].ACLR
|
|
rstn_i => mtime_hi[25].ACLR
|
|
rstn_i => mtime_hi[26].ACLR
|
|
rstn_i => mtime_hi[27].ACLR
|
|
rstn_i => mtime_hi[28].ACLR
|
|
rstn_i => mtime_hi[29].ACLR
|
|
rstn_i => mtime_hi[30].ACLR
|
|
rstn_i => mtime_hi[31].ACLR
|
|
rstn_i => mtime_lo_ovfl[0].ACLR
|
|
rstn_i => mtime_lo[0].ACLR
|
|
rstn_i => mtime_lo[1].ACLR
|
|
rstn_i => mtime_lo[2].ACLR
|
|
rstn_i => mtime_lo[3].ACLR
|
|
rstn_i => mtime_lo[4].ACLR
|
|
rstn_i => mtime_lo[5].ACLR
|
|
rstn_i => mtime_lo[6].ACLR
|
|
rstn_i => mtime_lo[7].ACLR
|
|
rstn_i => mtime_lo[8].ACLR
|
|
rstn_i => mtime_lo[9].ACLR
|
|
rstn_i => mtime_lo[10].ACLR
|
|
rstn_i => mtime_lo[11].ACLR
|
|
rstn_i => mtime_lo[12].ACLR
|
|
rstn_i => mtime_lo[13].ACLR
|
|
rstn_i => mtime_lo[14].ACLR
|
|
rstn_i => mtime_lo[15].ACLR
|
|
rstn_i => mtime_lo[16].ACLR
|
|
rstn_i => mtime_lo[17].ACLR
|
|
rstn_i => mtime_lo[18].ACLR
|
|
rstn_i => mtime_lo[19].ACLR
|
|
rstn_i => mtime_lo[20].ACLR
|
|
rstn_i => mtime_lo[21].ACLR
|
|
rstn_i => mtime_lo[22].ACLR
|
|
rstn_i => mtime_lo[23].ACLR
|
|
rstn_i => mtime_lo[24].ACLR
|
|
rstn_i => mtime_lo[25].ACLR
|
|
rstn_i => mtime_lo[26].ACLR
|
|
rstn_i => mtime_lo[27].ACLR
|
|
rstn_i => mtime_lo[28].ACLR
|
|
rstn_i => mtime_lo[29].ACLR
|
|
rstn_i => mtime_lo[30].ACLR
|
|
rstn_i => mtime_lo[31].ACLR
|
|
rstn_i => mtime_hi_we.ACLR
|
|
rstn_i => mtime_lo_we.ACLR
|
|
rstn_i => mtimecmp_hi[0].ACLR
|
|
rstn_i => mtimecmp_hi[1].ACLR
|
|
rstn_i => mtimecmp_hi[2].ACLR
|
|
rstn_i => mtimecmp_hi[3].ACLR
|
|
rstn_i => mtimecmp_hi[4].ACLR
|
|
rstn_i => mtimecmp_hi[5].ACLR
|
|
rstn_i => mtimecmp_hi[6].ACLR
|
|
rstn_i => mtimecmp_hi[7].ACLR
|
|
rstn_i => mtimecmp_hi[8].ACLR
|
|
rstn_i => mtimecmp_hi[9].ACLR
|
|
rstn_i => mtimecmp_hi[10].ACLR
|
|
rstn_i => mtimecmp_hi[11].ACLR
|
|
rstn_i => mtimecmp_hi[12].ACLR
|
|
rstn_i => mtimecmp_hi[13].ACLR
|
|
rstn_i => mtimecmp_hi[14].ACLR
|
|
rstn_i => mtimecmp_hi[15].ACLR
|
|
rstn_i => mtimecmp_hi[16].ACLR
|
|
rstn_i => mtimecmp_hi[17].ACLR
|
|
rstn_i => mtimecmp_hi[18].ACLR
|
|
rstn_i => mtimecmp_hi[19].ACLR
|
|
rstn_i => mtimecmp_hi[20].ACLR
|
|
rstn_i => mtimecmp_hi[21].ACLR
|
|
rstn_i => mtimecmp_hi[22].ACLR
|
|
rstn_i => mtimecmp_hi[23].ACLR
|
|
rstn_i => mtimecmp_hi[24].ACLR
|
|
rstn_i => mtimecmp_hi[25].ACLR
|
|
rstn_i => mtimecmp_hi[26].ACLR
|
|
rstn_i => mtimecmp_hi[27].ACLR
|
|
rstn_i => mtimecmp_hi[28].ACLR
|
|
rstn_i => mtimecmp_hi[29].ACLR
|
|
rstn_i => mtimecmp_hi[30].ACLR
|
|
rstn_i => mtimecmp_hi[31].ACLR
|
|
rstn_i => mtimecmp_lo[0].ACLR
|
|
rstn_i => mtimecmp_lo[1].ACLR
|
|
rstn_i => mtimecmp_lo[2].ACLR
|
|
rstn_i => mtimecmp_lo[3].ACLR
|
|
rstn_i => mtimecmp_lo[4].ACLR
|
|
rstn_i => mtimecmp_lo[5].ACLR
|
|
rstn_i => mtimecmp_lo[6].ACLR
|
|
rstn_i => mtimecmp_lo[7].ACLR
|
|
rstn_i => mtimecmp_lo[8].ACLR
|
|
rstn_i => mtimecmp_lo[9].ACLR
|
|
rstn_i => mtimecmp_lo[10].ACLR
|
|
rstn_i => mtimecmp_lo[11].ACLR
|
|
rstn_i => mtimecmp_lo[12].ACLR
|
|
rstn_i => mtimecmp_lo[13].ACLR
|
|
rstn_i => mtimecmp_lo[14].ACLR
|
|
rstn_i => mtimecmp_lo[15].ACLR
|
|
rstn_i => mtimecmp_lo[16].ACLR
|
|
rstn_i => mtimecmp_lo[17].ACLR
|
|
rstn_i => mtimecmp_lo[18].ACLR
|
|
rstn_i => mtimecmp_lo[19].ACLR
|
|
rstn_i => mtimecmp_lo[20].ACLR
|
|
rstn_i => mtimecmp_lo[21].ACLR
|
|
rstn_i => mtimecmp_lo[22].ACLR
|
|
rstn_i => mtimecmp_lo[23].ACLR
|
|
rstn_i => mtimecmp_lo[24].ACLR
|
|
rstn_i => mtimecmp_lo[25].ACLR
|
|
rstn_i => mtimecmp_lo[26].ACLR
|
|
rstn_i => mtimecmp_lo[27].ACLR
|
|
rstn_i => mtimecmp_lo[28].ACLR
|
|
rstn_i => mtimecmp_lo[29].ACLR
|
|
rstn_i => mtimecmp_lo[30].ACLR
|
|
rstn_i => mtimecmp_lo[31].ACLR
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => Mux0.IN1
|
|
addr_i[2] => Mux1.IN1
|
|
addr_i[2] => Mux2.IN1
|
|
addr_i[2] => Mux3.IN1
|
|
addr_i[2] => Mux4.IN1
|
|
addr_i[2] => Mux5.IN1
|
|
addr_i[2] => Mux6.IN1
|
|
addr_i[2] => Mux7.IN1
|
|
addr_i[2] => Mux8.IN1
|
|
addr_i[2] => Mux9.IN1
|
|
addr_i[2] => Mux10.IN1
|
|
addr_i[2] => Mux11.IN1
|
|
addr_i[2] => Mux12.IN1
|
|
addr_i[2] => Mux13.IN1
|
|
addr_i[2] => Mux14.IN1
|
|
addr_i[2] => Mux15.IN1
|
|
addr_i[2] => Mux16.IN1
|
|
addr_i[2] => Mux17.IN1
|
|
addr_i[2] => Mux18.IN1
|
|
addr_i[2] => Mux19.IN1
|
|
addr_i[2] => Mux20.IN1
|
|
addr_i[2] => Mux21.IN1
|
|
addr_i[2] => Mux22.IN1
|
|
addr_i[2] => Mux23.IN1
|
|
addr_i[2] => Mux24.IN1
|
|
addr_i[2] => Mux25.IN1
|
|
addr_i[2] => Mux26.IN1
|
|
addr_i[2] => Mux27.IN1
|
|
addr_i[2] => Mux28.IN1
|
|
addr_i[2] => Mux29.IN1
|
|
addr_i[2] => Mux30.IN1
|
|
addr_i[2] => Mux31.IN1
|
|
addr_i[2] => Equal1.IN56
|
|
addr_i[2] => Equal2.IN28
|
|
addr_i[2] => Equal3.IN56
|
|
addr_i[2] => Equal4.IN27
|
|
addr_i[3] => Mux0.IN0
|
|
addr_i[3] => Mux1.IN0
|
|
addr_i[3] => Mux2.IN0
|
|
addr_i[3] => Mux3.IN0
|
|
addr_i[3] => Mux4.IN0
|
|
addr_i[3] => Mux5.IN0
|
|
addr_i[3] => Mux6.IN0
|
|
addr_i[3] => Mux7.IN0
|
|
addr_i[3] => Mux8.IN0
|
|
addr_i[3] => Mux9.IN0
|
|
addr_i[3] => Mux10.IN0
|
|
addr_i[3] => Mux11.IN0
|
|
addr_i[3] => Mux12.IN0
|
|
addr_i[3] => Mux13.IN0
|
|
addr_i[3] => Mux14.IN0
|
|
addr_i[3] => Mux15.IN0
|
|
addr_i[3] => Mux16.IN0
|
|
addr_i[3] => Mux17.IN0
|
|
addr_i[3] => Mux18.IN0
|
|
addr_i[3] => Mux19.IN0
|
|
addr_i[3] => Mux20.IN0
|
|
addr_i[3] => Mux21.IN0
|
|
addr_i[3] => Mux22.IN0
|
|
addr_i[3] => Mux23.IN0
|
|
addr_i[3] => Mux24.IN0
|
|
addr_i[3] => Mux25.IN0
|
|
addr_i[3] => Mux26.IN0
|
|
addr_i[3] => Mux27.IN0
|
|
addr_i[3] => Mux28.IN0
|
|
addr_i[3] => Mux29.IN0
|
|
addr_i[3] => Mux30.IN0
|
|
addr_i[3] => Mux31.IN0
|
|
addr_i[3] => Equal1.IN27
|
|
addr_i[3] => Equal2.IN27
|
|
addr_i[3] => Equal3.IN55
|
|
addr_i[3] => Equal4.IN56
|
|
addr_i[4] => Equal0.IN2
|
|
addr_i[5] => Equal0.IN4
|
|
addr_i[6] => Equal0.IN3
|
|
addr_i[7] => Equal0.IN1
|
|
addr_i[8] => Equal0.IN0
|
|
addr_i[9] => ~NO_FANOUT~
|
|
addr_i[10] => ~NO_FANOUT~
|
|
addr_i[11] => ~NO_FANOUT~
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => ~NO_FANOUT~
|
|
addr_i[16] => ~NO_FANOUT~
|
|
addr_i[17] => ~NO_FANOUT~
|
|
addr_i[18] => ~NO_FANOUT~
|
|
addr_i[19] => ~NO_FANOUT~
|
|
addr_i[20] => ~NO_FANOUT~
|
|
addr_i[21] => ~NO_FANOUT~
|
|
addr_i[22] => ~NO_FANOUT~
|
|
addr_i[23] => ~NO_FANOUT~
|
|
addr_i[24] => ~NO_FANOUT~
|
|
addr_i[25] => ~NO_FANOUT~
|
|
addr_i[26] => ~NO_FANOUT~
|
|
addr_i[27] => ~NO_FANOUT~
|
|
addr_i[28] => ~NO_FANOUT~
|
|
addr_i[29] => ~NO_FANOUT~
|
|
addr_i[30] => ~NO_FANOUT~
|
|
addr_i[31] => ~NO_FANOUT~
|
|
rden_i => rden.IN1
|
|
wren_i => wren.IN1
|
|
data_i[0] => mtimecmp_lo.DATAB
|
|
data_i[0] => mtimecmp_hi.DATAB
|
|
data_i[0] => mtime_lo.DATAB
|
|
data_i[0] => mtime_hi.DATAB
|
|
data_i[1] => mtimecmp_lo.DATAB
|
|
data_i[1] => mtimecmp_hi.DATAB
|
|
data_i[1] => mtime_lo.DATAB
|
|
data_i[1] => mtime_hi.DATAB
|
|
data_i[2] => mtimecmp_lo.DATAB
|
|
data_i[2] => mtimecmp_hi.DATAB
|
|
data_i[2] => mtime_lo.DATAB
|
|
data_i[2] => mtime_hi.DATAB
|
|
data_i[3] => mtimecmp_lo.DATAB
|
|
data_i[3] => mtimecmp_hi.DATAB
|
|
data_i[3] => mtime_lo.DATAB
|
|
data_i[3] => mtime_hi.DATAB
|
|
data_i[4] => mtimecmp_lo.DATAB
|
|
data_i[4] => mtimecmp_hi.DATAB
|
|
data_i[4] => mtime_lo.DATAB
|
|
data_i[4] => mtime_hi.DATAB
|
|
data_i[5] => mtimecmp_lo.DATAB
|
|
data_i[5] => mtimecmp_hi.DATAB
|
|
data_i[5] => mtime_lo.DATAB
|
|
data_i[5] => mtime_hi.DATAB
|
|
data_i[6] => mtimecmp_lo.DATAB
|
|
data_i[6] => mtimecmp_hi.DATAB
|
|
data_i[6] => mtime_lo.DATAB
|
|
data_i[6] => mtime_hi.DATAB
|
|
data_i[7] => mtimecmp_lo.DATAB
|
|
data_i[7] => mtimecmp_hi.DATAB
|
|
data_i[7] => mtime_lo.DATAB
|
|
data_i[7] => mtime_hi.DATAB
|
|
data_i[8] => mtimecmp_lo.DATAB
|
|
data_i[8] => mtimecmp_hi.DATAB
|
|
data_i[8] => mtime_lo.DATAB
|
|
data_i[8] => mtime_hi.DATAB
|
|
data_i[9] => mtimecmp_lo.DATAB
|
|
data_i[9] => mtimecmp_hi.DATAB
|
|
data_i[9] => mtime_lo.DATAB
|
|
data_i[9] => mtime_hi.DATAB
|
|
data_i[10] => mtimecmp_lo.DATAB
|
|
data_i[10] => mtimecmp_hi.DATAB
|
|
data_i[10] => mtime_lo.DATAB
|
|
data_i[10] => mtime_hi.DATAB
|
|
data_i[11] => mtimecmp_lo.DATAB
|
|
data_i[11] => mtimecmp_hi.DATAB
|
|
data_i[11] => mtime_lo.DATAB
|
|
data_i[11] => mtime_hi.DATAB
|
|
data_i[12] => mtimecmp_lo.DATAB
|
|
data_i[12] => mtimecmp_hi.DATAB
|
|
data_i[12] => mtime_lo.DATAB
|
|
data_i[12] => mtime_hi.DATAB
|
|
data_i[13] => mtimecmp_lo.DATAB
|
|
data_i[13] => mtimecmp_hi.DATAB
|
|
data_i[13] => mtime_lo.DATAB
|
|
data_i[13] => mtime_hi.DATAB
|
|
data_i[14] => mtimecmp_lo.DATAB
|
|
data_i[14] => mtimecmp_hi.DATAB
|
|
data_i[14] => mtime_lo.DATAB
|
|
data_i[14] => mtime_hi.DATAB
|
|
data_i[15] => mtimecmp_lo.DATAB
|
|
data_i[15] => mtimecmp_hi.DATAB
|
|
data_i[15] => mtime_lo.DATAB
|
|
data_i[15] => mtime_hi.DATAB
|
|
data_i[16] => mtimecmp_lo.DATAB
|
|
data_i[16] => mtimecmp_hi.DATAB
|
|
data_i[16] => mtime_lo.DATAB
|
|
data_i[16] => mtime_hi.DATAB
|
|
data_i[17] => mtimecmp_lo.DATAB
|
|
data_i[17] => mtimecmp_hi.DATAB
|
|
data_i[17] => mtime_lo.DATAB
|
|
data_i[17] => mtime_hi.DATAB
|
|
data_i[18] => mtimecmp_lo.DATAB
|
|
data_i[18] => mtimecmp_hi.DATAB
|
|
data_i[18] => mtime_lo.DATAB
|
|
data_i[18] => mtime_hi.DATAB
|
|
data_i[19] => mtimecmp_lo.DATAB
|
|
data_i[19] => mtimecmp_hi.DATAB
|
|
data_i[19] => mtime_lo.DATAB
|
|
data_i[19] => mtime_hi.DATAB
|
|
data_i[20] => mtimecmp_lo.DATAB
|
|
data_i[20] => mtimecmp_hi.DATAB
|
|
data_i[20] => mtime_lo.DATAB
|
|
data_i[20] => mtime_hi.DATAB
|
|
data_i[21] => mtimecmp_lo.DATAB
|
|
data_i[21] => mtimecmp_hi.DATAB
|
|
data_i[21] => mtime_lo.DATAB
|
|
data_i[21] => mtime_hi.DATAB
|
|
data_i[22] => mtimecmp_lo.DATAB
|
|
data_i[22] => mtimecmp_hi.DATAB
|
|
data_i[22] => mtime_lo.DATAB
|
|
data_i[22] => mtime_hi.DATAB
|
|
data_i[23] => mtimecmp_lo.DATAB
|
|
data_i[23] => mtimecmp_hi.DATAB
|
|
data_i[23] => mtime_lo.DATAB
|
|
data_i[23] => mtime_hi.DATAB
|
|
data_i[24] => mtimecmp_lo.DATAB
|
|
data_i[24] => mtimecmp_hi.DATAB
|
|
data_i[24] => mtime_lo.DATAB
|
|
data_i[24] => mtime_hi.DATAB
|
|
data_i[25] => mtimecmp_lo.DATAB
|
|
data_i[25] => mtimecmp_hi.DATAB
|
|
data_i[25] => mtime_lo.DATAB
|
|
data_i[25] => mtime_hi.DATAB
|
|
data_i[26] => mtimecmp_lo.DATAB
|
|
data_i[26] => mtimecmp_hi.DATAB
|
|
data_i[26] => mtime_lo.DATAB
|
|
data_i[26] => mtime_hi.DATAB
|
|
data_i[27] => mtimecmp_lo.DATAB
|
|
data_i[27] => mtimecmp_hi.DATAB
|
|
data_i[27] => mtime_lo.DATAB
|
|
data_i[27] => mtime_hi.DATAB
|
|
data_i[28] => mtimecmp_lo.DATAB
|
|
data_i[28] => mtimecmp_hi.DATAB
|
|
data_i[28] => mtime_lo.DATAB
|
|
data_i[28] => mtime_hi.DATAB
|
|
data_i[29] => mtimecmp_lo.DATAB
|
|
data_i[29] => mtimecmp_hi.DATAB
|
|
data_i[29] => mtime_lo.DATAB
|
|
data_i[29] => mtime_hi.DATAB
|
|
data_i[30] => mtimecmp_lo.DATAB
|
|
data_i[30] => mtimecmp_hi.DATAB
|
|
data_i[30] => mtime_lo.DATAB
|
|
data_i[30] => mtime_hi.DATAB
|
|
data_i[31] => mtimecmp_lo.DATAB
|
|
data_i[31] => mtimecmp_hi.DATAB
|
|
data_i[31] => mtime_lo.DATAB
|
|
data_i[31] => mtime_hi.DATAB
|
|
data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
irq_o <= irq_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_uart:\neorv32_uart0_inst_true:neorv32_uart0_inst
|
|
clk_i => neorv32_fifo:tx_engine_fifo_inst.clk_i
|
|
clk_i => rx_irq.buf[0].CLK
|
|
clk_i => rx_irq.buf[1].CLK
|
|
clk_i => tx_irq.buf[0].CLK
|
|
clk_i => tx_irq.buf[1].CLK
|
|
clk_i => uart_rts_o~reg0.CLK
|
|
clk_i => uart_cts_ff[0].CLK
|
|
clk_i => uart_cts_ff[1].CLK
|
|
clk_i => rx_engine.overr.CLK
|
|
clk_i => rx_engine.baud_cnt[0].CLK
|
|
clk_i => rx_engine.baud_cnt[1].CLK
|
|
clk_i => rx_engine.baud_cnt[2].CLK
|
|
clk_i => rx_engine.baud_cnt[3].CLK
|
|
clk_i => rx_engine.baud_cnt[4].CLK
|
|
clk_i => rx_engine.baud_cnt[5].CLK
|
|
clk_i => rx_engine.baud_cnt[6].CLK
|
|
clk_i => rx_engine.baud_cnt[7].CLK
|
|
clk_i => rx_engine.baud_cnt[8].CLK
|
|
clk_i => rx_engine.baud_cnt[9].CLK
|
|
clk_i => rx_engine.baud_cnt[10].CLK
|
|
clk_i => rx_engine.baud_cnt[11].CLK
|
|
clk_i => rx_engine.sreg[0].CLK
|
|
clk_i => rx_engine.sreg[1].CLK
|
|
clk_i => rx_engine.sreg[2].CLK
|
|
clk_i => rx_engine.sreg[3].CLK
|
|
clk_i => rx_engine.sreg[4].CLK
|
|
clk_i => rx_engine.sreg[5].CLK
|
|
clk_i => rx_engine.sreg[6].CLK
|
|
clk_i => rx_engine.sreg[7].CLK
|
|
clk_i => rx_engine.sreg[8].CLK
|
|
clk_i => rx_engine.sreg[9].CLK
|
|
clk_i => rx_engine.bitcnt[0].CLK
|
|
clk_i => rx_engine.bitcnt[1].CLK
|
|
clk_i => rx_engine.bitcnt[2].CLK
|
|
clk_i => rx_engine.bitcnt[3].CLK
|
|
clk_i => rx_engine.sync[0].CLK
|
|
clk_i => rx_engine.sync[1].CLK
|
|
clk_i => rx_engine.sync[2].CLK
|
|
clk_i => rx_engine.sync[3].CLK
|
|
clk_i => rx_engine.sync[4].CLK
|
|
clk_i => rx_engine.state.CLK
|
|
clk_i => tx_engine.baud_cnt[0].CLK
|
|
clk_i => tx_engine.baud_cnt[1].CLK
|
|
clk_i => tx_engine.baud_cnt[2].CLK
|
|
clk_i => tx_engine.baud_cnt[3].CLK
|
|
clk_i => tx_engine.baud_cnt[4].CLK
|
|
clk_i => tx_engine.baud_cnt[5].CLK
|
|
clk_i => tx_engine.baud_cnt[6].CLK
|
|
clk_i => tx_engine.baud_cnt[7].CLK
|
|
clk_i => tx_engine.baud_cnt[8].CLK
|
|
clk_i => tx_engine.baud_cnt[9].CLK
|
|
clk_i => tx_engine.baud_cnt[10].CLK
|
|
clk_i => tx_engine.baud_cnt[11].CLK
|
|
clk_i => tx_engine.sreg[0].CLK
|
|
clk_i => tx_engine.sreg[1].CLK
|
|
clk_i => tx_engine.sreg[2].CLK
|
|
clk_i => tx_engine.sreg[3].CLK
|
|
clk_i => tx_engine.sreg[4].CLK
|
|
clk_i => tx_engine.sreg[5].CLK
|
|
clk_i => tx_engine.sreg[6].CLK
|
|
clk_i => tx_engine.sreg[7].CLK
|
|
clk_i => tx_engine.sreg[8].CLK
|
|
clk_i => tx_engine.sreg[9].CLK
|
|
clk_i => tx_engine.sreg[10].CLK
|
|
clk_i => tx_engine.bitcnt[0].CLK
|
|
clk_i => tx_engine.bitcnt[1].CLK
|
|
clk_i => tx_engine.bitcnt[2].CLK
|
|
clk_i => tx_engine.bitcnt[3].CLK
|
|
clk_i => tx_engine.done.CLK
|
|
clk_i => tx_buffer.re.CLK
|
|
clk_i => uart_txd_o~reg0.CLK
|
|
clk_i => data_o[0]~reg0.CLK
|
|
clk_i => data_o[1]~reg0.CLK
|
|
clk_i => data_o[2]~reg0.CLK
|
|
clk_i => data_o[3]~reg0.CLK
|
|
clk_i => data_o[4]~reg0.CLK
|
|
clk_i => data_o[5]~reg0.CLK
|
|
clk_i => data_o[6]~reg0.CLK
|
|
clk_i => data_o[7]~reg0.CLK
|
|
clk_i => data_o[8]~reg0.CLK
|
|
clk_i => data_o[9]~reg0.CLK
|
|
clk_i => data_o[10]~reg0.CLK
|
|
clk_i => data_o[11]~reg0.CLK
|
|
clk_i => data_o[12]~reg0.CLK
|
|
clk_i => data_o[13]~reg0.CLK
|
|
clk_i => data_o[14]~reg0.CLK
|
|
clk_i => data_o[15]~reg0.CLK
|
|
clk_i => data_o[16]~reg0.CLK
|
|
clk_i => data_o[17]~reg0.CLK
|
|
clk_i => data_o[18]~reg0.CLK
|
|
clk_i => data_o[19]~reg0.CLK
|
|
clk_i => data_o[20]~reg0.CLK
|
|
clk_i => data_o[21]~reg0.CLK
|
|
clk_i => data_o[22]~reg0.CLK
|
|
clk_i => data_o[23]~reg0.CLK
|
|
clk_i => data_o[24]~reg0.CLK
|
|
clk_i => data_o[25]~reg0.CLK
|
|
clk_i => data_o[26]~reg0.CLK
|
|
clk_i => data_o[27]~reg0.CLK
|
|
clk_i => data_o[28]~reg0.CLK
|
|
clk_i => data_o[29]~reg0.CLK
|
|
clk_i => data_o[30]~reg0.CLK
|
|
clk_i => data_o[31]~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
clk_i => ctrl[0].CLK
|
|
clk_i => ctrl[1].CLK
|
|
clk_i => ctrl[2].CLK
|
|
clk_i => ctrl[3].CLK
|
|
clk_i => ctrl[4].CLK
|
|
clk_i => ctrl[5].CLK
|
|
clk_i => ctrl[6].CLK
|
|
clk_i => ctrl[7].CLK
|
|
clk_i => ctrl[8].CLK
|
|
clk_i => ctrl[9].CLK
|
|
clk_i => ctrl[10].CLK
|
|
clk_i => ctrl[11].CLK
|
|
clk_i => ctrl[12].CLK
|
|
clk_i => ctrl[20].CLK
|
|
clk_i => ctrl[21].CLK
|
|
clk_i => ctrl[22].CLK
|
|
clk_i => ctrl[23].CLK
|
|
clk_i => ctrl[24].CLK
|
|
clk_i => ctrl[25].CLK
|
|
clk_i => ctrl[26].CLK
|
|
clk_i => ctrl[28].CLK
|
|
clk_i => neorv32_fifo:rx_engine_fifo_inst.clk_i
|
|
clk_i => tx_engine.state~1.DATAIN
|
|
rstn_i => neorv32_fifo:tx_engine_fifo_inst.rstn_i
|
|
rstn_i => neorv32_fifo:rx_engine_fifo_inst.rstn_i
|
|
rstn_i => ctrl[0].ACLR
|
|
rstn_i => ctrl[1].ACLR
|
|
rstn_i => ctrl[2].ACLR
|
|
rstn_i => ctrl[3].ACLR
|
|
rstn_i => ctrl[4].ACLR
|
|
rstn_i => ctrl[5].ACLR
|
|
rstn_i => ctrl[6].ACLR
|
|
rstn_i => ctrl[7].ACLR
|
|
rstn_i => ctrl[8].ACLR
|
|
rstn_i => ctrl[9].ACLR
|
|
rstn_i => ctrl[10].ACLR
|
|
rstn_i => ctrl[11].ACLR
|
|
rstn_i => ctrl[12].ACLR
|
|
rstn_i => ctrl[20].ACLR
|
|
rstn_i => ctrl[21].ACLR
|
|
rstn_i => ctrl[22].ACLR
|
|
rstn_i => ctrl[23].ACLR
|
|
rstn_i => ctrl[24].ACLR
|
|
rstn_i => ctrl[25].ACLR
|
|
rstn_i => ctrl[26].ACLR
|
|
rstn_i => ctrl[28].ACLR
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => Equal1.IN56
|
|
addr_i[2] => Equal2.IN27
|
|
addr_i[2] => Equal4.IN27
|
|
addr_i[2] => Equal6.IN27
|
|
addr_i[3] => Equal0.IN5
|
|
addr_i[4] => Equal0.IN4
|
|
addr_i[5] => Equal0.IN2
|
|
addr_i[6] => Equal0.IN3
|
|
addr_i[7] => Equal0.IN1
|
|
addr_i[8] => Equal0.IN0
|
|
addr_i[9] => ~NO_FANOUT~
|
|
addr_i[10] => ~NO_FANOUT~
|
|
addr_i[11] => ~NO_FANOUT~
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => ~NO_FANOUT~
|
|
addr_i[16] => ~NO_FANOUT~
|
|
addr_i[17] => ~NO_FANOUT~
|
|
addr_i[18] => ~NO_FANOUT~
|
|
addr_i[19] => ~NO_FANOUT~
|
|
addr_i[20] => ~NO_FANOUT~
|
|
addr_i[21] => ~NO_FANOUT~
|
|
addr_i[22] => ~NO_FANOUT~
|
|
addr_i[23] => ~NO_FANOUT~
|
|
addr_i[24] => ~NO_FANOUT~
|
|
addr_i[25] => ~NO_FANOUT~
|
|
addr_i[26] => ~NO_FANOUT~
|
|
addr_i[27] => ~NO_FANOUT~
|
|
addr_i[28] => ~NO_FANOUT~
|
|
addr_i[29] => ~NO_FANOUT~
|
|
addr_i[30] => ~NO_FANOUT~
|
|
addr_i[31] => ~NO_FANOUT~
|
|
rden_i => rden.IN1
|
|
wren_i => wren.IN1
|
|
data_i[0] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[0]
|
|
data_i[0] => ctrl.DATAB
|
|
data_i[1] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[1]
|
|
data_i[1] => ctrl.DATAB
|
|
data_i[2] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[2]
|
|
data_i[2] => ctrl.DATAB
|
|
data_i[3] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[3]
|
|
data_i[3] => ctrl.DATAB
|
|
data_i[4] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[4]
|
|
data_i[4] => ctrl.DATAB
|
|
data_i[5] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[5]
|
|
data_i[5] => ctrl.DATAB
|
|
data_i[6] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[6]
|
|
data_i[6] => ctrl.DATAB
|
|
data_i[7] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[7]
|
|
data_i[7] => ctrl.DATAB
|
|
data_i[8] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[8]
|
|
data_i[8] => ctrl.DATAB
|
|
data_i[9] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[9]
|
|
data_i[9] => ctrl.DATAB
|
|
data_i[10] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[10]
|
|
data_i[10] => ctrl.DATAB
|
|
data_i[11] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[11]
|
|
data_i[11] => ctrl.DATAB
|
|
data_i[12] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[12]
|
|
data_i[12] => ctrl.DATAB
|
|
data_i[13] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[13]
|
|
data_i[14] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[14]
|
|
data_i[15] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[15]
|
|
data_i[16] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[16]
|
|
data_i[17] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[17]
|
|
data_i[18] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[18]
|
|
data_i[19] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[19]
|
|
data_i[20] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[20]
|
|
data_i[20] => ctrl.DATAB
|
|
data_i[21] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[21]
|
|
data_i[21] => ctrl.DATAB
|
|
data_i[22] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[22]
|
|
data_i[22] => ctrl.DATAB
|
|
data_i[23] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[23]
|
|
data_i[23] => ctrl.DATAB
|
|
data_i[24] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[24]
|
|
data_i[24] => ctrl.DATAB
|
|
data_i[25] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[25]
|
|
data_i[25] => ctrl.DATAB
|
|
data_i[26] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[26]
|
|
data_i[26] => ctrl.DATAB
|
|
data_i[27] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[27]
|
|
data_i[28] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[28]
|
|
data_i[28] => ctrl.DATAB
|
|
data_i[29] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[29]
|
|
data_i[30] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[30]
|
|
data_i[31] => neorv32_fifo:tx_engine_fifo_inst.wdata_i[31]
|
|
data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
clkgen_en_o <= ctrl[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
clkgen_i[0] => Mux0.IN7
|
|
clkgen_i[1] => Mux0.IN6
|
|
clkgen_i[2] => Mux0.IN5
|
|
clkgen_i[3] => Mux0.IN4
|
|
clkgen_i[4] => Mux0.IN3
|
|
clkgen_i[5] => Mux0.IN2
|
|
clkgen_i[6] => Mux0.IN1
|
|
clkgen_i[7] => Mux0.IN0
|
|
uart_txd_o <= uart_txd_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
uart_rxd_i => rx_engine.sync[4].DATAIN
|
|
uart_rts_o <= uart_rts_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
uart_cts_i => uart_cts_ff[0].DATAIN
|
|
irq_rxd_o <= Equal8.DB_MAX_OUTPUT_PORT_TYPE
|
|
irq_txd_o <= Equal7.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_uart:\neorv32_uart0_inst_true:neorv32_uart0_inst|neorv32_fifo:tx_engine_fifo_inst
|
|
clk_i => fifo.buf[0].CLK
|
|
clk_i => fifo.buf[1].CLK
|
|
clk_i => fifo.buf[2].CLK
|
|
clk_i => fifo.buf[3].CLK
|
|
clk_i => fifo.buf[4].CLK
|
|
clk_i => fifo.buf[5].CLK
|
|
clk_i => fifo.buf[6].CLK
|
|
clk_i => fifo.buf[7].CLK
|
|
clk_i => fifo.buf[8].CLK
|
|
clk_i => fifo.buf[9].CLK
|
|
clk_i => fifo.buf[10].CLK
|
|
clk_i => fifo.buf[11].CLK
|
|
clk_i => fifo.buf[12].CLK
|
|
clk_i => fifo.buf[13].CLK
|
|
clk_i => fifo.buf[14].CLK
|
|
clk_i => fifo.buf[15].CLK
|
|
clk_i => fifo.buf[16].CLK
|
|
clk_i => fifo.buf[17].CLK
|
|
clk_i => fifo.buf[18].CLK
|
|
clk_i => fifo.buf[19].CLK
|
|
clk_i => fifo.buf[20].CLK
|
|
clk_i => fifo.buf[21].CLK
|
|
clk_i => fifo.buf[22].CLK
|
|
clk_i => fifo.buf[23].CLK
|
|
clk_i => fifo.buf[24].CLK
|
|
clk_i => fifo.buf[25].CLK
|
|
clk_i => fifo.buf[26].CLK
|
|
clk_i => fifo.buf[27].CLK
|
|
clk_i => fifo.buf[28].CLK
|
|
clk_i => fifo.buf[29].CLK
|
|
clk_i => fifo.buf[30].CLK
|
|
clk_i => fifo.buf[31].CLK
|
|
clk_i => fifo.r_pnt[0].CLK
|
|
clk_i => fifo.w_pnt[0].CLK
|
|
rstn_i => fifo.r_pnt[0].ACLR
|
|
rstn_i => fifo.w_pnt[0].ACLR
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
half_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
wdata_i[0] => fifo.buf[0].DATAIN
|
|
wdata_i[1] => fifo.buf[1].DATAIN
|
|
wdata_i[2] => fifo.buf[2].DATAIN
|
|
wdata_i[3] => fifo.buf[3].DATAIN
|
|
wdata_i[4] => fifo.buf[4].DATAIN
|
|
wdata_i[5] => fifo.buf[5].DATAIN
|
|
wdata_i[6] => fifo.buf[6].DATAIN
|
|
wdata_i[7] => fifo.buf[7].DATAIN
|
|
wdata_i[8] => fifo.buf[8].DATAIN
|
|
wdata_i[9] => fifo.buf[9].DATAIN
|
|
wdata_i[10] => fifo.buf[10].DATAIN
|
|
wdata_i[11] => fifo.buf[11].DATAIN
|
|
wdata_i[12] => fifo.buf[12].DATAIN
|
|
wdata_i[13] => fifo.buf[13].DATAIN
|
|
wdata_i[14] => fifo.buf[14].DATAIN
|
|
wdata_i[15] => fifo.buf[15].DATAIN
|
|
wdata_i[16] => fifo.buf[16].DATAIN
|
|
wdata_i[17] => fifo.buf[17].DATAIN
|
|
wdata_i[18] => fifo.buf[18].DATAIN
|
|
wdata_i[19] => fifo.buf[19].DATAIN
|
|
wdata_i[20] => fifo.buf[20].DATAIN
|
|
wdata_i[21] => fifo.buf[21].DATAIN
|
|
wdata_i[22] => fifo.buf[22].DATAIN
|
|
wdata_i[23] => fifo.buf[23].DATAIN
|
|
wdata_i[24] => fifo.buf[24].DATAIN
|
|
wdata_i[25] => fifo.buf[25].DATAIN
|
|
wdata_i[26] => fifo.buf[26].DATAIN
|
|
wdata_i[27] => fifo.buf[27].DATAIN
|
|
wdata_i[28] => fifo.buf[28].DATAIN
|
|
wdata_i[29] => fifo.buf[29].DATAIN
|
|
wdata_i[30] => fifo.buf[30].DATAIN
|
|
wdata_i[31] => fifo.buf[31].DATAIN
|
|
we_i => fifo.we.IN1
|
|
free_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
re_i => fifo.re.IN1
|
|
rdata_o[0] <= fifo.buf[0].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[1] <= fifo.buf[1].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[2] <= fifo.buf[2].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[3] <= fifo.buf[3].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[4] <= fifo.buf[4].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[5] <= fifo.buf[5].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[6] <= fifo.buf[6].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[7] <= fifo.buf[7].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[8] <= fifo.buf[8].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[9] <= fifo.buf[9].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[10] <= fifo.buf[10].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[11] <= fifo.buf[11].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[12] <= fifo.buf[12].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[13] <= fifo.buf[13].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[14] <= fifo.buf[14].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[15] <= fifo.buf[15].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[16] <= fifo.buf[16].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[17] <= fifo.buf[17].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[18] <= fifo.buf[18].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[19] <= fifo.buf[19].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[20] <= fifo.buf[20].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[21] <= fifo.buf[21].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[22] <= fifo.buf[22].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[23] <= fifo.buf[23].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[24] <= fifo.buf[24].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[25] <= fifo.buf[25].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[26] <= fifo.buf[26].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[27] <= fifo.buf[27].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[28] <= fifo.buf[28].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[29] <= fifo.buf[29].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[30] <= fifo.buf[30].DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[31] <= fifo.buf[31].DB_MAX_OUTPUT_PORT_TYPE
|
|
avail_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_uart:\neorv32_uart0_inst_true:neorv32_uart0_inst|neorv32_fifo:rx_engine_fifo_inst
|
|
clk_i => fifo.buf[0].CLK
|
|
clk_i => fifo.buf[1].CLK
|
|
clk_i => fifo.buf[2].CLK
|
|
clk_i => fifo.buf[3].CLK
|
|
clk_i => fifo.buf[4].CLK
|
|
clk_i => fifo.buf[5].CLK
|
|
clk_i => fifo.buf[6].CLK
|
|
clk_i => fifo.buf[7].CLK
|
|
clk_i => fifo.buf[8].CLK
|
|
clk_i => fifo.buf[9].CLK
|
|
clk_i => fifo.r_pnt[0].CLK
|
|
clk_i => fifo.w_pnt[0].CLK
|
|
rstn_i => fifo.r_pnt[0].ACLR
|
|
rstn_i => fifo.w_pnt[0].ACLR
|
|
clear_i => fifo.OUTPUTSELECT
|
|
clear_i => fifo.OUTPUTSELECT
|
|
half_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
wdata_i[0] => fifo.buf[0].DATAIN
|
|
wdata_i[1] => fifo.buf[1].DATAIN
|
|
wdata_i[2] => fifo.buf[2].DATAIN
|
|
wdata_i[3] => fifo.buf[3].DATAIN
|
|
wdata_i[4] => fifo.buf[4].DATAIN
|
|
wdata_i[5] => fifo.buf[5].DATAIN
|
|
wdata_i[6] => fifo.buf[6].DATAIN
|
|
wdata_i[7] => fifo.buf[7].DATAIN
|
|
wdata_i[8] => fifo.buf[8].DATAIN
|
|
wdata_i[9] => fifo.buf[9].DATAIN
|
|
we_i => fifo.we.IN1
|
|
free_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
re_i => fifo.re.IN1
|
|
rdata_o[0] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[1] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[2] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[3] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[4] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[5] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[6] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[7] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[8] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
rdata_o[9] <= rdata_o.DB_MAX_OUTPUT_PORT_TYPE
|
|
avail_o <= fifo.empty.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|
|
|neorv32_test_setup_bootloader|neorv32_top:neorv32_top_inst|neorv32_sysinfo:neorv32_sysinfo_inst
|
|
clk_i => data_o[0]~reg0.CLK
|
|
clk_i => data_o[1]~reg0.CLK
|
|
clk_i => data_o[2]~reg0.CLK
|
|
clk_i => data_o[3]~reg0.CLK
|
|
clk_i => data_o[4]~reg0.CLK
|
|
clk_i => data_o[5]~reg0.CLK
|
|
clk_i => data_o[6]~reg0.CLK
|
|
clk_i => data_o[7]~reg0.CLK
|
|
clk_i => data_o[8]~reg0.CLK
|
|
clk_i => data_o[9]~reg0.CLK
|
|
clk_i => data_o[10]~reg0.CLK
|
|
clk_i => data_o[11]~reg0.CLK
|
|
clk_i => data_o[12]~reg0.CLK
|
|
clk_i => data_o[13]~reg0.CLK
|
|
clk_i => data_o[14]~reg0.CLK
|
|
clk_i => data_o[15]~reg0.CLK
|
|
clk_i => data_o[16]~reg0.CLK
|
|
clk_i => data_o[17]~reg0.CLK
|
|
clk_i => data_o[18]~reg0.CLK
|
|
clk_i => data_o[19]~reg0.CLK
|
|
clk_i => data_o[20]~reg0.CLK
|
|
clk_i => data_o[21]~reg0.CLK
|
|
clk_i => data_o[22]~reg0.CLK
|
|
clk_i => data_o[23]~reg0.CLK
|
|
clk_i => data_o[24]~reg0.CLK
|
|
clk_i => data_o[25]~reg0.CLK
|
|
clk_i => data_o[26]~reg0.CLK
|
|
clk_i => data_o[27]~reg0.CLK
|
|
clk_i => data_o[28]~reg0.CLK
|
|
clk_i => data_o[29]~reg0.CLK
|
|
clk_i => data_o[30]~reg0.CLK
|
|
clk_i => data_o[31]~reg0.CLK
|
|
clk_i => err_o~reg0.CLK
|
|
clk_i => ack_o~reg0.CLK
|
|
addr_i[0] => ~NO_FANOUT~
|
|
addr_i[1] => ~NO_FANOUT~
|
|
addr_i[2] => Mux0.IN10
|
|
addr_i[2] => Mux1.IN10
|
|
addr_i[2] => Mux2.IN10
|
|
addr_i[2] => Mux3.IN10
|
|
addr_i[2] => Mux4.IN10
|
|
addr_i[3] => Mux0.IN9
|
|
addr_i[3] => Mux1.IN9
|
|
addr_i[3] => Mux2.IN9
|
|
addr_i[3] => Mux3.IN9
|
|
addr_i[3] => Mux4.IN9
|
|
addr_i[4] => Mux0.IN8
|
|
addr_i[4] => Mux1.IN8
|
|
addr_i[4] => Mux2.IN8
|
|
addr_i[4] => Mux3.IN8
|
|
addr_i[4] => Mux4.IN8
|
|
addr_i[5] => Equal0.IN3
|
|
addr_i[6] => Equal0.IN2
|
|
addr_i[7] => Equal0.IN1
|
|
addr_i[8] => Equal0.IN0
|
|
addr_i[9] => ~NO_FANOUT~
|
|
addr_i[10] => ~NO_FANOUT~
|
|
addr_i[11] => ~NO_FANOUT~
|
|
addr_i[12] => ~NO_FANOUT~
|
|
addr_i[13] => ~NO_FANOUT~
|
|
addr_i[14] => ~NO_FANOUT~
|
|
addr_i[15] => ~NO_FANOUT~
|
|
addr_i[16] => ~NO_FANOUT~
|
|
addr_i[17] => ~NO_FANOUT~
|
|
addr_i[18] => ~NO_FANOUT~
|
|
addr_i[19] => ~NO_FANOUT~
|
|
addr_i[20] => ~NO_FANOUT~
|
|
addr_i[21] => ~NO_FANOUT~
|
|
addr_i[22] => ~NO_FANOUT~
|
|
addr_i[23] => ~NO_FANOUT~
|
|
addr_i[24] => ~NO_FANOUT~
|
|
addr_i[25] => ~NO_FANOUT~
|
|
addr_i[26] => ~NO_FANOUT~
|
|
addr_i[27] => ~NO_FANOUT~
|
|
addr_i[28] => ~NO_FANOUT~
|
|
addr_i[29] => ~NO_FANOUT~
|
|
addr_i[30] => ~NO_FANOUT~
|
|
addr_i[31] => ~NO_FANOUT~
|
|
rden_i => rden.IN1
|
|
wren_i => wren.IN1
|
|
data_o[0] <= data_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[1] <= data_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[2] <= data_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[3] <= data_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[4] <= data_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[5] <= data_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[6] <= data_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[7] <= data_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[8] <= data_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[9] <= data_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[10] <= data_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[11] <= data_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[12] <= data_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[13] <= data_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[14] <= data_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[15] <= data_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[16] <= data_o[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[17] <= data_o[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[18] <= data_o[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[19] <= data_o[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[20] <= data_o[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[21] <= data_o[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[22] <= data_o[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[23] <= data_o[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[24] <= data_o[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[25] <= data_o[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[26] <= data_o[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[27] <= data_o[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[28] <= data_o[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[29] <= data_o[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[30] <= data_o[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
data_o[31] <= data_o[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
ack_o <= ack_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
err_o <= err_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
|
|
|
|