233 lines
10 KiB
C
233 lines
10 KiB
C
// #################################################################################################
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// # << NEORV32: neorv32_xip.c - Execute In Place (XIP) Module HW Driver (Source) >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_xip.c
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* @brief Execute in place module (XIP) HW driver source file.
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*
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* @note These functions should only be used if the XIP module was synthesized (IO_XIP_EN = true).
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_xip.h"
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/**********************************************************************//**
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* Check if XIP module was synthesized.
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*
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* @return 0 if XIP was not synthesized, 1 if XIP is available.
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**************************************************************************/
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int neorv32_xip_available(void) {
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if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_XIP)) {
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return 1;
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}
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else {
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return 0;
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}
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}
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/**********************************************************************//**
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* Configure XIP module: configure SPI/flash properties.
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*
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* @warning This will reset the XIP module overriding the CTRL register.
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* @note This function will also send 64 dummy clocks via the SPI port (with chip-select disabled).
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*
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* @param[in] prsc SPI clock prescaler select (0..7).
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* @param[in] cpol SPI clock polarity (0/1).
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* @param[in] cpha SPI clock phase(0/1).
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* @param[in] rd_cmd SPI flash read byte command.
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* @return 0 if configuration is OK, -1 if configuration error.
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**************************************************************************/
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int neorv32_xip_setup(uint8_t prsc, uint8_t cpol, uint8_t cpha, uint8_t rd_cmd) {
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// configuration check
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if ((prsc > 7) || (cpol > 1) || (cpha > 1)) {
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return -1;
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}
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// reset and disable module
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NEORV32_XIP.CTRL = 0;
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// clear data registers
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NEORV32_XIP.DATA_LO = 0;
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NEORV32_XIP.DATA_HI = 0; // will not trigger SPI transfer since module is disabled
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uint32_t ctrl = 0;
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ctrl |= ((uint32_t)(1 )) << XIP_CTRL_EN; // enable module
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ctrl |= ((uint32_t)(prsc & 0x07)) << XIP_CTRL_PRSC0;
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ctrl |= ((uint32_t)(cpol & 0x01)) << XIP_CTRL_CPOL;
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ctrl |= ((uint32_t)(cpha & 0x01)) << XIP_CTRL_CPHA;
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ctrl |= ((uint32_t)(8 )) << XIP_CTRL_SPI_NBYTES_LSB; // set 8 bytes transfer size as default
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ctrl |= ((uint32_t)(rd_cmd & 0xff)) << XIP_CTRL_RD_CMD_LSB;
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NEORV32_XIP.CTRL = ctrl;
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// send 64 SPI dummy clocks but without an active CS
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NEORV32_XIP.DATA_LO = 0;
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NEORV32_XIP.DATA_HI = 0; // trigger SPI transfer
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// wait for transfer to complete
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while (NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
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NEORV32_XIP.CTRL |= 1 << XIP_CTRL_SPI_CSEN; // finally enable automatic SPI chip-select
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return 0;
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}
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/**********************************************************************//**
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* Enable XIP mode (to allow CPU to _transparently_ fetch data & instructions).
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*
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* @param[in] abytes Number of address bytes used to access the SPI flash (1,2,3,4).
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* @param[in] page_base XIP memory page base address (top 4 address bits, 0..15).
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* @return 0 if XIP configuration is OK, -1 if configuration error.
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**************************************************************************/
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int neorv32_xip_start(uint8_t abytes, uint32_t page_base) {
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if ((abytes < 1) || (abytes > 4)) {
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return -1;
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}
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if (page_base & 0x0FFFFFFF) {
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return -1;
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}
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page_base >>= 28;
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uint32_t ctrl = NEORV32_XIP.CTRL;
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// address bytes send to SPI flash
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ctrl &= ~(3 << XIP_CTRL_XIP_ABYTES_LSB); // clear old configuration
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ctrl |= ((uint32_t)(abytes-1)) << XIP_CTRL_XIP_ABYTES_LSB; // set new configuration
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// total number of bytes to transfer via SPI
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// 'abytes' address bytes + 1 command byte + 4 bytes RX data (one 32-bit word)
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ctrl &= ~(0xF << XIP_CTRL_SPI_NBYTES_LSB); // clear old configuration
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ctrl |= ((uint32_t)(abytes+1+4)) << XIP_CTRL_SPI_NBYTES_LSB; // set new configuration
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// XIP memory page
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ctrl &= ~(0xF << XIP_CTRL_PAGE_LSB); // clear old configuration
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ctrl |= ((uint32_t)(page_base & 0xf)) << XIP_CTRL_PAGE_LSB; // set new configuration
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ctrl |= 1 << XIP_CTRL_XIP_EN; // enable XIP mode
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NEORV32_XIP.CTRL = ctrl;
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return 0;
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}
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/**********************************************************************//**
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* Enable high-speed SPI mode (running at half of the processor clock).
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*
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* @note High-speed SPI mode ignores the programmed clock prescaler configuration.
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**************************************************************************/
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void neorv32_xip_highspeed_enable(void) {
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NEORV32_XIP.CTRL |= 1 << XIP_CTRL_HIGHSPEED;
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}
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/**********************************************************************//**
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* Disable high-speed SPI mode.
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**************************************************************************/
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void neorv32_xip_highspeed_disable(void) {
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NEORV32_XIP.CTRL &= ~(1 << XIP_CTRL_HIGHSPEED);
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}
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/**********************************************************************//**
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* Enable XIP burst mode (incremental reads).
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*
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* @note Make sure your flash supports this feature (most flash chips do so).
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**************************************************************************/
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void neorv32_xip_burst_mode_enable(void) {
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NEORV32_XIP.CTRL |= 1 << XIP_CTRL_BURST_EN;
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}
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/**********************************************************************//**
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* Disable XIP burst mode.
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**************************************************************************/
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void neorv32_xip_burst_mode_disable(void) {
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NEORV32_XIP.CTRL &= ~(1 << XIP_CTRL_BURST_EN);
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}
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/**********************************************************************//**
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* Direct SPI access to the XIP flash.
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*
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* @warning This function can only be used BEFORE the XIP-mode is activated!
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* @note This function is blocking.
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*
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* @param[in] nbytes Number of bytes to transfer (1..8).
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* @param[in,out] rtx_data Pointer to 64-bit TX/RX data (MSB-aligned for sending, LSB-aligned for receiving (only 32-bit)).
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* @return 0 if valid transfer, 1 if transfer configuration error.
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**************************************************************************/
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int neorv32_xip_spi_trans(uint8_t nbytes, uint64_t *rtx_data) {
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if ((nbytes == 0) || (nbytes > 8)) {
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return 1;
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}
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// configure number of bytes to transfer
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uint32_t ctrl = NEORV32_XIP.CTRL;
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ctrl &= ~(0xF << XIP_CTRL_SPI_NBYTES_LSB); // clear old configuration
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ctrl |= nbytes << XIP_CTRL_SPI_NBYTES_LSB; // set new configuration
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NEORV32_XIP.CTRL = ctrl;
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union {
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uint64_t uint64;
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uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
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} data;
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data.uint64 = *rtx_data;
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NEORV32_XIP.DATA_LO = data.uint32[0];
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NEORV32_XIP.DATA_HI = data.uint32[1]; // trigger SPI transfer
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// wait for transfer to complete
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while (NEORV32_XIP.CTRL & (1 << XIP_CTRL_PHY_BUSY)); // direct SPI mode -> check PHY status
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data.uint32[0] = NEORV32_XIP.DATA_LO; // RX data is always 32-bit and LSB-aligned
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data.uint32[1] = 0;
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*rtx_data = data.uint64;
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return 0;
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}
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