217 lines
9.4 KiB
C
217 lines
9.4 KiB
C
// #################################################################################################
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// # << NEORV32: neorv32_spi.c - Serial Peripheral Interface Controller (SPI) HW Driver >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_spi.c
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* @brief Serial peripheral interface controller (SPI) HW driver source file.
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*
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* @note These functions should only be used if the SPI unit was synthesized (IO_SPI_EN = true).
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_spi.h"
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/**********************************************************************//**
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* Check if SPI unit was synthesized.
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*
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* @return 0 if SPI was not synthesized, 1 if SPI is available.
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**************************************************************************/
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int neorv32_spi_available(void) {
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if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_IO_SPI)) {
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return 1;
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}
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else {
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return 0;
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}
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}
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/**********************************************************************//**
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* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.
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*
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @prama[in] cdiv Clock divider (0..15).
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* @param[in] clk_phase Clock phase (0=sample on rising edge, 1=sample on falling edge).
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* @param[in] clk_polarity Clock polarity (when idle).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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* @param[in] irq_config Interrupt configuration (0,1: PHY transfer done, 2: TX FIFO becomes less than half full, 3: TX FIFO becomes empty).
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**************************************************************************/
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void neorv32_spi_setup(int prsc, int cdiv, int clk_phase, int clk_polarity, int data_size, int irq_config) {
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NEORV32_SPI.CTRL = 0; // reset
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uint32_t tmp = 0;
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tmp |= (uint32_t)(1 & 0x01) << SPI_CTRL_EN;
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tmp |= (uint32_t)(clk_phase & 0x01) << SPI_CTRL_CPHA;
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tmp |= (uint32_t)(clk_polarity & 0x01) << SPI_CTRL_CPOL;
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tmp |= (uint32_t)(data_size & 0x03) << SPI_CTRL_SIZE0;
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tmp |= (uint32_t)(prsc & 0x07) << SPI_CTRL_PRSC0;
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tmp |= (uint32_t)(cdiv & 0x0f) << SPI_CTRL_CDIV0;
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tmp |= (uint32_t)(irq_config & 0x03) << SPI_CTRL_IRQ0;
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NEORV32_SPI.CTRL = tmp;
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}
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/**********************************************************************//**
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* Get configured clock speed in Hz.
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*
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* @return Actual configured SPI clock speed in Hz.
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**************************************************************************/
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uint32_t neorv32_spi_get_clock_speed(void) {
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const uint32_t PRSC_LUT[8] = {2, 4, 8, 64, 128, 1024, 2048, 4096};
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uint32_t ctrl = NEORV32_SPI.CTRL;
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uint32_t prsc_sel = (ctrl >> SPI_CTRL_PRSC0) & 0x7;
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uint32_t clock_div = (ctrl >> SPI_CTRL_CDIV0) & 0xf;
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uint32_t tmp = 2 * PRSC_LUT[prsc_sel] * clock_div;
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return NEORV32_SYSINFO.CLK / tmp;
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}
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/**********************************************************************//**
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* Disable SPI controller.
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**************************************************************************/
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void neorv32_spi_disable(void) {
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NEORV32_SPI.CTRL &= ~((uint32_t)(1 << SPI_CTRL_EN));
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}
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/**********************************************************************//**
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* Enable SPI controller.
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**************************************************************************/
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void neorv32_spi_enable(void) {
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NEORV32_SPI.CTRL |= ((uint32_t)(1 << SPI_CTRL_EN));
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}
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/**********************************************************************//**
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* Get SPI FIFO depth.
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*
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* @return FIFO depth (number of entries), zero if no FIFO implemented
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**************************************************************************/
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int neorv32_spi_get_fifo_depth(void) {
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uint32_t tmp = (NEORV32_SPI.CTRL >> SPI_CTRL_FIFO_LSB) & 0x0f;
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return (int)(1 << tmp);
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}
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/**********************************************************************//**
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* Activate single SPI chip select signal.
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*
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* @note The SPI chip select output lines are LOW when activated.
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*
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* @param cs Chip select line to activate (0..7).
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**************************************************************************/
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void neorv32_spi_cs_en(int cs) {
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uint32_t tmp = NEORV32_SPI.CTRL;
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tmp &= ~(0xf << SPI_CTRL_CS_SEL0); // clear old configuration
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tmp |= (1 << SPI_CTRL_CS_EN) | ((cs & 7) << SPI_CTRL_CS_SEL0); // set new configuration
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NEORV32_SPI.CTRL = tmp;
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}
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/**********************************************************************//**
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* Deactivate currently active SPI chip select signal.
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*
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* @note The SPI chip select output lines are HIGH when deactivated.
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**************************************************************************/
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void neorv32_spi_cs_dis(void) {
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NEORV32_SPI.CTRL &= ~(1 << SPI_CTRL_CS_EN);
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}
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/**********************************************************************//**
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* Initiate SPI transfer.
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*
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* @note This function is blocking.
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*
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* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
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* @return Receive data (8/16/24/32-bit, LSB-aligned).
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**************************************************************************/
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uint32_t neorv32_spi_trans(uint32_t tx_data) {
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NEORV32_SPI.DATA = tx_data; // trigger transfer
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while((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0); // wait for current transfer to finish
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return NEORV32_SPI.DATA;
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}
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/**********************************************************************//**
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* Initiate SPI TX transfer (non-blocking).
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*
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* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned).
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**************************************************************************/
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void neorv32_spi_put_nonblocking(uint32_t tx_data) {
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NEORV32_SPI.DATA = tx_data; // trigger transfer
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}
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/**********************************************************************//**
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* Get SPI RX data (non-blocking).
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*
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* @return Receive data (8/16/24/32-bit, LSB-aligned).
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**************************************************************************/
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uint32_t neorv32_spi_get_nonblocking(void) {
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return NEORV32_SPI.DATA;
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}
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/**********************************************************************//**
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* Check if SPI transceiver is busy.
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*
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* @return 0 if idle, 1 if busy
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**************************************************************************/
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int neorv32_spi_busy(void) {
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if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
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return 1;
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}
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else {
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return 0;
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}
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}
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