138 lines
7.7 KiB
VHDL
138 lines
7.7 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - Processor-internal instruction memory (IMEM) >> #
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-- # ********************************************************************************************* #
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-- # This version is intended for SIMULATION ONLY! #
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-- # It implements the IMEM as pre-initialized RAM. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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architecture neorv32_imem_rtl of neorv32_imem is
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-- IO space: module base address --
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constant hi_abb_c : natural := 31; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(IMEM_SIZE); -- low address boundary bit
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-- local signals --
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signal acc_en : std_ulogic;
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signal rdata : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal addr : std_ulogic_vector(index_size_f(IMEM_SIZE/4)-1 downto 0);
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-- ---------------------------------------------------- --
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-- << SIMULATION ONLY!!! >> IMEM as pre-initialized RAM --
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-- ---------------------------------------------------- --
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-- application (image) size in bytes --
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constant imem_app_size_c : natural := (application_init_image'length)*4;
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-- RAM - initialized with executable code --
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signal mem_ram : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4);
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-- read data --
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signal mem_ram_rd : std_ulogic_vector(31 downto 0);
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report "NEORV32 PROCESSOR CONFIG NOTE: Implementing processor-internal [SIM-only!] IMEM as RAM (" & natural'image(IMEM_SIZE) &
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" bytes), pre-initialized with application (" & natural'image(imem_app_size_c) & " bytes)." severity note;
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--
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assert not (imem_app_size_c > IMEM_SIZE) report "NEORV32 PROCESSOR CONFIG ERROR: Application (image = " & natural'image(imem_app_size_c) &
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" bytes) does not fit into processor-internal IMEM (" & natural'image(IMEM_SIZE) & " bytes)!" severity error;
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
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addr <= addr_i(index_size_f(IMEM_SIZE/4)+1 downto 2); -- word aligned
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-- Implement IMEM as pre-initialized RAM --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (acc_en = '1') then
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if (wren_i = '1') and (ben_i(0) = '1') then -- byte 0
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mem_ram(to_integer(unsigned(addr)))(07 downto 00) <= data_i(07 downto 00);
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else
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mem_ram_rd(07 downto 00) <= mem_ram(to_integer(unsigned(addr)))(07 downto 00);
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end if;
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if (wren_i = '1') and (ben_i(1) = '1') then -- byte 1
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mem_ram(to_integer(unsigned(addr)))(15 downto 08) <= data_i(15 downto 08);
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else
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mem_ram_rd(15 downto 08) <= mem_ram(to_integer(unsigned(addr)))(15 downto 08);
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end if;
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if (wren_i = '1') and (ben_i(2) = '1') then -- byte 2
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mem_ram(to_integer(unsigned(addr)))(23 downto 16) <= data_i(23 downto 16);
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else
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mem_ram_rd(23 downto 16) <= mem_ram(to_integer(unsigned(addr)))(23 downto 16);
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end if;
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if (wren_i = '1') and (ben_i(3) = '1') then -- byte 3
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mem_ram(to_integer(unsigned(addr)))(31 downto 24) <= data_i(31 downto 24);
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else
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mem_ram_rd(31 downto 24) <= mem_ram(to_integer(unsigned(addr)))(31 downto 24);
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end if;
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end if;
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end if;
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end process mem_access;
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-- read data --
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rdata <= mem_ram_rd;
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-- Bus Feedback ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_feedback: process(clk_i)
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begin
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if rising_edge(clk_i) then
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rden <= acc_en and rden_i;
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err_o <= '0';
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ack_o <= acc_en and (rden_i or wren_i);
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end if;
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end process bus_feedback;
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-- output gate --
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data_o <= rdata when (rden = '1') else (others => '0');
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end neorv32_imem_rtl;
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