488 lines
14 KiB
C
488 lines
14 KiB
C
/*
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* SiFive Platform DMA emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "sysemu/dma.h"
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#include "hw/dma/sifive_pdma.h"
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#define DMA_CONTROL 0x000
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#define CONTROL_CLAIM BIT(0)
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#define CONTROL_RUN BIT(1)
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#define CONTROL_DONE_IE BIT(14)
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#define CONTROL_ERR_IE BIT(15)
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#define CONTROL_DONE BIT(30)
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#define CONTROL_ERR BIT(31)
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#define DMA_NEXT_CONFIG 0x004
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#define CONFIG_REPEAT BIT(2)
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#define CONFIG_ORDER BIT(3)
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#define CONFIG_WRSZ_SHIFT 24
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#define CONFIG_RDSZ_SHIFT 28
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#define CONFIG_SZ_MASK 0xf
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#define DMA_NEXT_BYTES 0x008
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#define DMA_NEXT_DST 0x010
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#define DMA_NEXT_SRC 0x018
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#define DMA_EXEC_CONFIG 0x104
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#define DMA_EXEC_BYTES 0x108
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#define DMA_EXEC_DST 0x110
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#define DMA_EXEC_SRC 0x118
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/*
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* FU540/FU740 docs are incorrect with NextConfig.wsize/rsize reset values.
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* The reset values tested on Unleashed/Unmatched boards are 6 instead of 0.
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*/
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#define CONFIG_WRSZ_DEFAULT 6
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#define CONFIG_RDSZ_DEFAULT 6
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enum dma_chan_state {
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DMA_CHAN_STATE_IDLE,
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DMA_CHAN_STATE_STARTED,
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DMA_CHAN_STATE_ERROR,
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DMA_CHAN_STATE_DONE
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};
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static void sifive_pdma_run(SiFivePDMAState *s, int ch)
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{
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uint64_t bytes = s->chan[ch].next_bytes;
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uint64_t dst = s->chan[ch].next_dst;
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uint64_t src = s->chan[ch].next_src;
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uint32_t config = s->chan[ch].next_config;
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int wsize, rsize, size, remainder;
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uint8_t buf[64];
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int n;
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/* do nothing if bytes to transfer is zero */
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if (!bytes) {
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goto done;
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}
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/*
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* The manual does not describe how the hardware behaviors when
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* config.wsize and config.rsize are given different values.
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* A common case is memory to memory DMA, and in this case they
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* are normally the same. Abort if this expectation fails.
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*/
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wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
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rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
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if (wsize != rsize) {
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goto error;
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}
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/*
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* Calculate the transaction size
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*
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* size field is base 2 logarithm of DMA transaction size,
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* but there is an upper limit of 64 bytes per transaction.
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*/
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size = wsize;
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if (size > 6) {
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size = 6;
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}
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size = 1 << size;
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remainder = bytes % size;
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/* indicate a DMA transfer is started */
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s->chan[ch].state = DMA_CHAN_STATE_STARTED;
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s->chan[ch].control &= ~CONTROL_DONE;
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s->chan[ch].control &= ~CONTROL_ERR;
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/* load the next_ registers into their exec_ counterparts */
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s->chan[ch].exec_config = config;
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s->chan[ch].exec_bytes = bytes;
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s->chan[ch].exec_dst = dst;
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s->chan[ch].exec_src = src;
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for (n = 0; n < bytes / size; n++) {
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cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
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cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
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s->chan[ch].exec_src += size;
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s->chan[ch].exec_dst += size;
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s->chan[ch].exec_bytes -= size;
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}
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if (remainder) {
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cpu_physical_memory_read(s->chan[ch].exec_src, buf, remainder);
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cpu_physical_memory_write(s->chan[ch].exec_dst, buf, remainder);
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s->chan[ch].exec_src += remainder;
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s->chan[ch].exec_dst += remainder;
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s->chan[ch].exec_bytes -= remainder;
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}
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/* reload exec_ registers if repeat is required */
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if (s->chan[ch].next_config & CONFIG_REPEAT) {
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s->chan[ch].exec_bytes = bytes;
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s->chan[ch].exec_dst = dst;
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s->chan[ch].exec_src = src;
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}
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done:
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/* indicate a DMA transfer is done */
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s->chan[ch].state = DMA_CHAN_STATE_DONE;
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s->chan[ch].control &= ~CONTROL_RUN;
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s->chan[ch].control |= CONTROL_DONE;
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return;
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error:
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s->chan[ch].state = DMA_CHAN_STATE_ERROR;
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s->chan[ch].control |= CONTROL_ERR;
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return;
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}
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static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
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{
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bool done_ie, err_ie;
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done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
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err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
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if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
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qemu_irq_raise(s->irq[ch * 2]);
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} else {
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qemu_irq_lower(s->irq[ch * 2]);
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}
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if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
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qemu_irq_raise(s->irq[ch * 2 + 1]);
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} else {
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qemu_irq_lower(s->irq[ch * 2 + 1]);
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}
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s->chan[ch].state = DMA_CHAN_STATE_IDLE;
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}
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static uint64_t sifive_pdma_readq(SiFivePDMAState *s, int ch, hwaddr offset)
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{
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uint64_t val = 0;
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offset &= 0xfff;
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switch (offset) {
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case DMA_NEXT_BYTES:
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val = s->chan[ch].next_bytes;
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break;
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case DMA_NEXT_DST:
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val = s->chan[ch].next_dst;
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break;
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case DMA_NEXT_SRC:
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val = s->chan[ch].next_src;
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break;
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case DMA_EXEC_BYTES:
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val = s->chan[ch].exec_bytes;
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break;
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case DMA_EXEC_DST:
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val = s->chan[ch].exec_dst;
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break;
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case DMA_EXEC_SRC:
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val = s->chan[ch].exec_src;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n",
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__func__, offset);
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break;
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}
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return val;
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}
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static uint32_t sifive_pdma_readl(SiFivePDMAState *s, int ch, hwaddr offset)
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{
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uint32_t val = 0;
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offset &= 0xfff;
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switch (offset) {
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case DMA_CONTROL:
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val = s->chan[ch].control;
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break;
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case DMA_NEXT_CONFIG:
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val = s->chan[ch].next_config;
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break;
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case DMA_NEXT_BYTES:
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val = extract64(s->chan[ch].next_bytes, 0, 32);
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break;
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case DMA_NEXT_BYTES + 4:
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val = extract64(s->chan[ch].next_bytes, 32, 32);
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break;
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case DMA_NEXT_DST:
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val = extract64(s->chan[ch].next_dst, 0, 32);
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break;
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case DMA_NEXT_DST + 4:
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val = extract64(s->chan[ch].next_dst, 32, 32);
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break;
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case DMA_NEXT_SRC:
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val = extract64(s->chan[ch].next_src, 0, 32);
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break;
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case DMA_NEXT_SRC + 4:
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val = extract64(s->chan[ch].next_src, 32, 32);
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break;
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case DMA_EXEC_CONFIG:
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val = s->chan[ch].exec_config;
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break;
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case DMA_EXEC_BYTES:
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val = extract64(s->chan[ch].exec_bytes, 0, 32);
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break;
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case DMA_EXEC_BYTES + 4:
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val = extract64(s->chan[ch].exec_bytes, 32, 32);
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break;
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case DMA_EXEC_DST:
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val = extract64(s->chan[ch].exec_dst, 0, 32);
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break;
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case DMA_EXEC_DST + 4:
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val = extract64(s->chan[ch].exec_dst, 32, 32);
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break;
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case DMA_EXEC_SRC:
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val = extract64(s->chan[ch].exec_src, 0, 32);
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break;
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case DMA_EXEC_SRC + 4:
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val = extract64(s->chan[ch].exec_src, 32, 32);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n",
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__func__, offset);
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break;
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}
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return val;
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}
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static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
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{
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SiFivePDMAState *s = opaque;
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int ch = SIFIVE_PDMA_CHAN_NO(offset);
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uint64_t val = 0;
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if (ch >= SIFIVE_PDMA_CHANS) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
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__func__, ch);
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return 0;
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}
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switch (size) {
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case 8:
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val = sifive_pdma_readq(s, ch, offset);
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break;
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case 4:
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val = sifive_pdma_readl(s, ch, offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid read size %u to PDMA\n",
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__func__, size);
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return 0;
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}
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return val;
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}
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static void sifive_pdma_writeq(SiFivePDMAState *s, int ch,
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hwaddr offset, uint64_t value)
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{
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offset &= 0xfff;
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switch (offset) {
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case DMA_NEXT_BYTES:
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s->chan[ch].next_bytes = value;
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break;
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case DMA_NEXT_DST:
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s->chan[ch].next_dst = value;
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break;
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case DMA_NEXT_SRC:
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s->chan[ch].next_src = value;
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break;
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case DMA_EXEC_BYTES:
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case DMA_EXEC_DST:
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case DMA_EXEC_SRC:
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/* these are read-only registers */
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n",
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__func__, offset);
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break;
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}
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}
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static void sifive_pdma_writel(SiFivePDMAState *s, int ch,
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hwaddr offset, uint32_t value)
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{
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bool claimed, run;
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offset &= 0xfff;
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switch (offset) {
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case DMA_CONTROL:
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claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
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run = !!(s->chan[ch].control & CONTROL_RUN);
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if (!claimed && (value & CONTROL_CLAIM)) {
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/* reset Next* registers */
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s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) |
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(CONFIG_WRSZ_DEFAULT << CONFIG_WRSZ_SHIFT);
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s->chan[ch].next_bytes = 0;
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s->chan[ch].next_dst = 0;
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s->chan[ch].next_src = 0;
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}
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/* claim bit can only be cleared when run is low */
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if (run && !(value & CONTROL_CLAIM)) {
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value |= CONTROL_CLAIM;
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}
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s->chan[ch].control = value;
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/*
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* If channel was not claimed before run bit is set,
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* or if the channel is disclaimed when run was low,
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* DMA won't run.
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*/
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if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
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s->chan[ch].control &= ~CONTROL_RUN;
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return;
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}
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if (value & CONTROL_RUN) {
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sifive_pdma_run(s, ch);
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}
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sifive_pdma_update_irq(s, ch);
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break;
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case DMA_NEXT_CONFIG:
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s->chan[ch].next_config = value;
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break;
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case DMA_NEXT_BYTES:
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s->chan[ch].next_bytes =
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deposit64(s->chan[ch].next_bytes, 0, 32, value);
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break;
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case DMA_NEXT_BYTES + 4:
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s->chan[ch].next_bytes =
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deposit64(s->chan[ch].next_bytes, 32, 32, value);
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break;
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case DMA_NEXT_DST:
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s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 0, 32, value);
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break;
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case DMA_NEXT_DST + 4:
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s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 32, 32, value);
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break;
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case DMA_NEXT_SRC:
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s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 0, 32, value);
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break;
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case DMA_NEXT_SRC + 4:
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s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 32, 32, value);
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break;
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case DMA_EXEC_CONFIG:
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case DMA_EXEC_BYTES:
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case DMA_EXEC_BYTES + 4:
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case DMA_EXEC_DST:
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case DMA_EXEC_DST + 4:
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case DMA_EXEC_SRC:
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case DMA_EXEC_SRC + 4:
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/* these are read-only registers */
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n",
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__func__, offset);
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break;
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}
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}
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static void sifive_pdma_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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SiFivePDMAState *s = opaque;
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int ch = SIFIVE_PDMA_CHAN_NO(offset);
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if (ch >= SIFIVE_PDMA_CHANS) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
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__func__, ch);
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return;
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}
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switch (size) {
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case 8:
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sifive_pdma_writeq(s, ch, offset, value);
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break;
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case 4:
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sifive_pdma_writel(s, ch, offset, (uint32_t) value);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid write size %u to PDMA\n",
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__func__, size);
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break;
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}
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}
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static const MemoryRegionOps sifive_pdma_ops = {
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.read = sifive_pdma_read,
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.write = sifive_pdma_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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/* there are 32-bit and 64-bit wide registers */
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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.valid = {
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.min_access_size = 4,
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.max_access_size = 8,
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}
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};
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static void sifive_pdma_realize(DeviceState *dev, Error **errp)
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{
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SiFivePDMAState *s = SIFIVE_PDMA(dev);
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int i;
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memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
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TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
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}
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}
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static void sifive_pdma_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "SiFive Platform DMA controller";
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dc->realize = sifive_pdma_realize;
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}
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static const TypeInfo sifive_pdma_info = {
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.name = TYPE_SIFIVE_PDMA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFivePDMAState),
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.class_init = sifive_pdma_class_init,
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};
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static void sifive_pdma_register_types(void)
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{
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type_register_static(&sifive_pdma_info);
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}
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type_init(sifive_pdma_register_types)
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