266 lines
9.7 KiB
C
266 lines
9.7 KiB
C
/*
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* SmartFusion2 SoC emulation.
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*
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* Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/char/serial.h"
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#include "hw/arm/msf2-soc.h"
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#include "hw/misc/unimp.h"
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#include "hw/qdev-clock.h"
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#include "sysemu/sysemu.h"
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#define MSF2_TIMER_BASE 0x40004000
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#define MSF2_SYSREG_BASE 0x40038000
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#define MSF2_EMAC_BASE 0x40041000
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#define ENVM_BASE_ADDRESS 0x60000000
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#define SRAM_BASE_ADDRESS 0x20000000
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#define MSF2_EMAC_IRQ 12
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#define MSF2_ENVM_MAX_SIZE (512 * KiB)
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/*
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* eSRAM max size is 80k without SECDED(Single error correction and
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* dual error detection) feature and 64k with SECDED.
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* We do not support SECDED now.
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*/
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#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
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static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
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static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
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static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
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static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
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static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
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static void m2sxxx_soc_initfn(Object *obj)
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{
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MSF2State *s = MSF2_SOC(obj);
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int i;
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object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
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object_initialize_child(obj, "sysreg", &s->sysreg, TYPE_MSF2_SYSREG);
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object_initialize_child(obj, "timer", &s->timer, TYPE_MSS_TIMER);
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for (i = 0; i < MSF2_NUM_SPIS; i++) {
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object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_MSS_SPI);
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}
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object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
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s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0);
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s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
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}
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static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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MSF2State *s = MSF2_SOC(dev_soc);
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DeviceState *dev, *armv7m;
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SysBusDevice *busdev;
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int i;
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MemoryRegion *system_memory = get_system_memory();
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if (!clock_has_source(s->m3clk)) {
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error_setg(errp, "m3clk must be wired up by the board code");
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return;
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}
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/*
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* We use s->refclk internally and only define it with qdev_init_clock_in()
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* so it is correctly parented and not leaked on an init/deinit; it is not
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* intended as an externally exposed clock.
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*/
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if (clock_has_source(s->refclk)) {
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error_setg(errp, "refclk must not be wired up by the board code");
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return;
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}
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/*
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* TODO: ideally we should model the SoC SYSTICK_CR register at 0xe0042038,
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* which allows the guest to program the divisor between the m3clk and
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* the systick refclk to either /4, /8, /16 or /32, as well as setting
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* the value the guest can read in the STCALIB register. Currently we
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* implement the divisor as a fixed /32, which matches the reset value
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* of SYSTICK_CR.
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*/
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clock_set_mul_div(s->refclk, 32, 1);
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clock_set_source(s->refclk, s->m3clk);
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memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
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&error_fatal);
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/*
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* On power-on, the eNVM region 0x60000000 is automatically
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* remapped to the Cortex-M3 processor executable region
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* start address (0x0). We do not support remapping other eNVM,
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* eSRAM and DDR regions by guest(via Sysreg) currently.
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*/
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memory_region_init_alias(&s->nvm_alias, OBJECT(dev_soc), "MSF2.eNVM",
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&s->nvm, 0, s->envm_size);
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memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, &s->nvm);
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memory_region_add_subregion(system_memory, 0, &s->nvm_alias);
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memory_region_init_ram(&s->sram, NULL, "MSF2.eSRAM", s->esram_size,
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&error_fatal);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 81);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk);
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qdev_connect_clock_in(armv7m, "refclk", s->refclk);
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object_property_set_link(OBJECT(&s->armv7m), "memory",
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OBJECT(get_system_memory()), &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
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return;
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}
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for (i = 0; i < MSF2_NUM_UARTS; i++) {
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if (serial_hd(i)) {
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serial_mm_init(get_system_memory(), uart_addr[i], 2,
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qdev_get_gpio_in(armv7m, uart_irq[i]),
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115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
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}
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}
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dev = DEVICE(&s->timer);
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/*
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* APB0 clock is the timer input clock.
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* TODO: ideally the MSF2 timer device should use a Clock rather than a
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* clock-frequency integer property.
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*/
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qdev_prop_set_uint32(dev, "clock-frequency",
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clock_get_hz(s->m3clk) / s->apb0div);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(armv7m, timer_irq[0]));
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sysbus_connect_irq(busdev, 1,
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qdev_get_gpio_in(armv7m, timer_irq[1]));
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dev = DEVICE(&s->sysreg);
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qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
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qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
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for (i = 0; i < MSF2_NUM_SPIS; i++) {
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gchar *bus_name;
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
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qdev_get_gpio_in(armv7m, spi_irq[i]));
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/* Alias controller SPI bus to the SoC itself */
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bus_name = g_strdup_printf("spi%d", i);
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object_property_add_alias(OBJECT(s), bus_name,
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OBJECT(&s->spi[i]), "spi");
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g_free(bus_name);
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}
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/* FIXME use qdev NIC properties instead of nd_table[] */
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if (nd_table[0].used) {
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qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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dev = DEVICE(&s->emac);
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object_property_set_link(OBJECT(&s->emac), "ahb-bus",
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OBJECT(get_system_memory()), &error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->emac), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
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/* Below devices are not modelled yet. */
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create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
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create_unimplemented_device("dma", 0x40003000, 0x1000);
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create_unimplemented_device("watchdog", 0x40005000, 0x1000);
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create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
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create_unimplemented_device("gpio", 0x40013000, 0x1000);
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create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
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create_unimplemented_device("can", 0x40015000, 0x1000);
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create_unimplemented_device("rtc", 0x40017000, 0x1000);
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create_unimplemented_device("apb_config", 0x40020000, 0x10000);
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create_unimplemented_device("usb", 0x40043000, 0x1000);
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}
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static Property m2sxxx_soc_properties[] = {
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/*
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* part name specifies the type of SmartFusion2 device variant(this
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* property is for information purpose only.
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*/
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DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
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DEFINE_PROP_STRING("part-name", MSF2State, part_name),
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DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
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DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
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MSF2_ESRAM_MAX_SIZE),
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/* default divisors in Libero GUI */
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DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
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DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = m2sxxx_soc_realize;
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device_class_set_props(dc, m2sxxx_soc_properties);
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}
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static const TypeInfo m2sxxx_soc_info = {
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.name = TYPE_MSF2_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MSF2State),
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.instance_init = m2sxxx_soc_initfn,
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.class_init = m2sxxx_soc_class_init,
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};
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static void m2sxxx_soc_types(void)
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{
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type_register_static(&m2sxxx_soc_info);
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}
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type_init(m2sxxx_soc_types)
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