291 lines
12 KiB
C
291 lines
12 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* DEF(name, oargs, iargs, cargs, flags)
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*/
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/* predefined ops */
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DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
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DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
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/* variable number of parameters */
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DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
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DEF(br, 0, 0, 1, TCG_OPF_BB_END)
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#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
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#if TCG_TARGET_REG_BITS == 32
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# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
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#else
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# define IMPL64 TCG_OPF_64BIT
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#endif
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DEF(mb, 0, 0, 1, 0)
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DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(setcond_i32, 1, 2, 1, 0)
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DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
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/* load/store */
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DEF(ld8u_i32, 1, 1, 1, 0)
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DEF(ld8s_i32, 1, 1, 1, 0)
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DEF(ld16u_i32, 1, 1, 1, 0)
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DEF(ld16s_i32, 1, 1, 1, 0)
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DEF(ld_i32, 1, 1, 1, 0)
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DEF(st8_i32, 0, 2, 1, 0)
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DEF(st16_i32, 0, 2, 1, 0)
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DEF(st_i32, 0, 2, 1, 0)
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/* arith */
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DEF(add_i32, 1, 2, 0, 0)
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DEF(sub_i32, 1, 2, 0, 0)
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DEF(mul_i32, 1, 2, 0, 0)
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DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
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DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
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DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(and_i32, 1, 2, 0, 0)
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DEF(or_i32, 1, 2, 0, 0)
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DEF(xor_i32, 1, 2, 0, 0)
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/* shifts/rotates */
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DEF(shl_i32, 1, 2, 0, 0)
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
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DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
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DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
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DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
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DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
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DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
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DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
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DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
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DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
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DEF(brcond2_i32, 0, 4, 2,
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TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
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DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
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DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
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DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
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DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
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DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
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DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
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DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
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DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
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DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
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DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
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DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
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DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
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DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
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DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
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DEF(setcond_i64, 1, 2, 1, IMPL64)
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DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
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/* load/store */
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DEF(ld8u_i64, 1, 1, 1, IMPL64)
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DEF(ld8s_i64, 1, 1, 1, IMPL64)
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DEF(ld16u_i64, 1, 1, 1, IMPL64)
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DEF(ld16s_i64, 1, 1, 1, IMPL64)
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DEF(ld32u_i64, 1, 1, 1, IMPL64)
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DEF(ld32s_i64, 1, 1, 1, IMPL64)
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DEF(ld_i64, 1, 1, 1, IMPL64)
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DEF(st8_i64, 0, 2, 1, IMPL64)
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DEF(st16_i64, 0, 2, 1, IMPL64)
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DEF(st32_i64, 0, 2, 1, IMPL64)
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DEF(st_i64, 0, 2, 1, IMPL64)
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/* arith */
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DEF(add_i64, 1, 2, 0, IMPL64)
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DEF(sub_i64, 1, 2, 0, IMPL64)
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DEF(mul_i64, 1, 2, 0, IMPL64)
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DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
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DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
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DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(and_i64, 1, 2, 0, IMPL64)
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DEF(or_i64, 1, 2, 0, IMPL64)
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DEF(xor_i64, 1, 2, 0, IMPL64)
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/* shifts/rotates */
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DEF(shl_i64, 1, 2, 0, IMPL64)
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DEF(shr_i64, 1, 2, 0, IMPL64)
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DEF(sar_i64, 1, 2, 0, IMPL64)
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DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
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DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
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DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
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DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
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/* size changing ops */
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DEF(ext_i32_i64, 1, 1, 0, IMPL64)
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DEF(extu_i32_i64, 1, 1, 0, IMPL64)
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DEF(extrl_i64_i32, 1, 1, 0,
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IMPL(TCG_TARGET_HAS_extrl_i64_i32)
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| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
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DEF(extrh_i64_i32, 1, 1, 0,
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IMPL(TCG_TARGET_HAS_extrh_i64_i32)
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| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
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DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
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DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
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DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
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DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
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DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
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DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
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DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
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DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
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DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
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DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
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DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
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DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
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DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
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DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
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DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
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DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
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DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
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DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
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DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
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DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
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DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
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DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
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#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
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#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
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/* QEMU specific */
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DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
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TCG_OPF_NOT_PRESENT)
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DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
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DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
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DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
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DEF(plugin_cb_start, 0, 0, 3, TCG_OPF_NOT_PRESENT)
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DEF(plugin_cb_end, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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/* Only used by i386 to cope with stupid register constraints. */
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DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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IMPL(TCG_TARGET_HAS_qemu_st8_i32))
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/* Host vector support. */
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#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
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DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
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DEF(dup_vec, 1, 1, 0, IMPLVEC)
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DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(ld_vec, 1, 1, 1, IMPLVEC)
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DEF(st_vec, 0, 2, 1, IMPLVEC)
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DEF(dupm_vec, 1, 1, 1, IMPLVEC)
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DEF(add_vec, 1, 2, 0, IMPLVEC)
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DEF(sub_vec, 1, 2, 0, IMPLVEC)
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DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
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DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
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DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
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DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
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DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
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DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
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DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
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DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
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DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
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DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
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DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
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DEF(and_vec, 1, 2, 0, IMPLVEC)
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DEF(or_vec, 1, 2, 0, IMPLVEC)
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DEF(xor_vec, 1, 2, 0, IMPLVEC)
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DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
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DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
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DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec))
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DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec))
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DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec))
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DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
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DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
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DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
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DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
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DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
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DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
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DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
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DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
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DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
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DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
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DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
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DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
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DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
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DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
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DEF(cmp_vec, 1, 2, 1, IMPLVEC)
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DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
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DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
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DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
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#if TCG_TARGET_MAYBE_vec
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#include "tcg-target.opc.h"
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#endif
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#ifdef TCG_TARGET_INTERPRETER
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/* These opcodes are only for use between the tci generator and interpreter. */
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DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT)
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DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT)
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#endif
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#undef TLADDR_ARGS
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#undef DATA64_ARGS
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#undef IMPL
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#undef IMPL64
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#undef IMPLVEC
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#undef DEF
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