294 lines
8 KiB
C
294 lines
8 KiB
C
/*
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* Generic watchdog device model for SBSA
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*
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* The watchdog device has been implemented as revision 1 variant of
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* the ARM SBSA specification v6.0
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* (https://developer.arm.com/documentation/den0029/d?lang=en)
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*
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* Copyright Linaro.org 2020
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*
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* Authors:
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* Shashi Mallela <shashi.mallela@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "sysemu/reset.h"
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#include "sysemu/watchdog.h"
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#include "hw/watchdog/sbsa_gwdt.h"
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#include "qemu/timer.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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static WatchdogTimerModel model = {
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.wdt_name = TYPE_WDT_SBSA,
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.wdt_description = "SBSA-compliant generic watchdog device",
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};
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static const VMStateDescription vmstate_sbsa_gwdt = {
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.name = "sbsa-gwdt",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER_PTR(timer, SBSA_GWDTState),
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VMSTATE_UINT32(wcs, SBSA_GWDTState),
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VMSTATE_UINT32(worl, SBSA_GWDTState),
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VMSTATE_UINT32(woru, SBSA_GWDTState),
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VMSTATE_UINT32(wcvl, SBSA_GWDTState),
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VMSTATE_UINT32(wcvu, SBSA_GWDTState),
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VMSTATE_END_OF_LIST()
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}
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};
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typedef enum WdtRefreshType {
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EXPLICIT_REFRESH = 0,
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TIMEOUT_REFRESH = 1,
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} WdtRefreshType;
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static uint64_t sbsa_gwdt_rread(void *opaque, hwaddr addr, unsigned int size)
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{
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SBSA_GWDTState *s = SBSA_GWDT(opaque);
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uint32_t ret = 0;
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switch (addr) {
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case SBSA_GWDT_WRR:
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/* watch refresh read has no effect and returns 0 */
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ret = 0;
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break;
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case SBSA_GWDT_W_IIDR:
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ret = s->id;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame read :"
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" 0x%x\n", (int)addr);
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}
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return ret;
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}
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static uint64_t sbsa_gwdt_read(void *opaque, hwaddr addr, unsigned int size)
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{
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SBSA_GWDTState *s = SBSA_GWDT(opaque);
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uint32_t ret = 0;
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switch (addr) {
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case SBSA_GWDT_WCS:
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ret = s->wcs;
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break;
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case SBSA_GWDT_WOR:
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ret = s->worl;
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break;
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case SBSA_GWDT_WORU:
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ret = s->woru;
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break;
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case SBSA_GWDT_WCV:
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ret = s->wcvl;
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break;
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case SBSA_GWDT_WCVU:
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ret = s->wcvu;
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break;
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case SBSA_GWDT_W_IIDR:
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ret = s->id;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame read :"
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" 0x%x\n", (int)addr);
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}
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return ret;
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}
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static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
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{
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uint64_t timeout = 0;
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timer_del(s->timer);
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if (s->wcs & SBSA_GWDT_WCS_EN) {
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/*
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* Extract the upper 16 bits from woru & 32 bits from worl
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* registers to construct the 48 bit offset value
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*/
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timeout = s->woru;
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timeout <<= 32;
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timeout |= s->worl;
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timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
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timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
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(!(s->wcs & SBSA_GWDT_WCS_WS0)))) {
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/* store the current timeout value into compare registers */
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s->wcvu = timeout >> 32;
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s->wcvl = timeout;
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}
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timer_mod(s->timer, timeout);
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}
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}
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static void sbsa_gwdt_rwrite(void *opaque, hwaddr offset, uint64_t data,
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unsigned size) {
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SBSA_GWDTState *s = SBSA_GWDT(opaque);
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if (offset == SBSA_GWDT_WRR) {
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s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
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sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame write :"
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" 0x%x\n", (int)offset);
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}
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}
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static void sbsa_gwdt_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size) {
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SBSA_GWDTState *s = SBSA_GWDT(opaque);
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switch (offset) {
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case SBSA_GWDT_WCS:
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s->wcs = data & SBSA_GWDT_WCS_EN;
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qemu_set_irq(s->irq, 0);
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sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
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break;
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case SBSA_GWDT_WOR:
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s->worl = data;
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s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
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qemu_set_irq(s->irq, 0);
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sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
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break;
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case SBSA_GWDT_WORU:
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s->woru = data & SBSA_GWDT_WOR_MASK;
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s->wcs &= ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1);
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qemu_set_irq(s->irq, 0);
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sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH);
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break;
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case SBSA_GWDT_WCV:
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s->wcvl = data;
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break;
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case SBSA_GWDT_WCVU:
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s->wcvu = data;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame write :"
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" 0x%x\n", (int)offset);
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}
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return;
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}
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static void wdt_sbsa_gwdt_reset(DeviceState *dev)
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{
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SBSA_GWDTState *s = SBSA_GWDT(dev);
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timer_del(s->timer);
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s->wcs = 0;
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s->wcvl = 0;
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s->wcvu = 0;
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s->worl = 0;
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s->woru = 0;
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s->id = SBSA_GWDT_ID;
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}
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static void sbsa_gwdt_timer_sysinterrupt(void *opaque)
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{
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SBSA_GWDTState *s = SBSA_GWDT(opaque);
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if (!(s->wcs & SBSA_GWDT_WCS_WS0)) {
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s->wcs |= SBSA_GWDT_WCS_WS0;
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sbsa_gwdt_update_timer(s, TIMEOUT_REFRESH);
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qemu_set_irq(s->irq, 1);
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} else {
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s->wcs |= SBSA_GWDT_WCS_WS1;
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qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
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/*
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* Reset the watchdog only if the guest gets notified about
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* expiry. watchdog_perform_action() may temporarily relinquish
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* the BQL; reset before triggering the action to avoid races with
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* sbsa_gwdt instructions.
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*/
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switch (get_watchdog_action()) {
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case WATCHDOG_ACTION_DEBUG:
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case WATCHDOG_ACTION_NONE:
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case WATCHDOG_ACTION_PAUSE:
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break;
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default:
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wdt_sbsa_gwdt_reset(DEVICE(s));
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}
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watchdog_perform_action();
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}
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}
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static const MemoryRegionOps sbsa_gwdt_rops = {
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.read = sbsa_gwdt_rread,
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.write = sbsa_gwdt_rwrite,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static const MemoryRegionOps sbsa_gwdt_ops = {
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.read = sbsa_gwdt_read,
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.write = sbsa_gwdt_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
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{
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SBSA_GWDTState *s = SBSA_GWDT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->rmmio, OBJECT(dev),
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&sbsa_gwdt_rops, s,
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"sbsa_gwdt.refresh",
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SBSA_GWDT_RMMIO_SIZE);
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memory_region_init_io(&s->cmmio, OBJECT(dev),
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&sbsa_gwdt_ops, s,
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"sbsa_gwdt.control",
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SBSA_GWDT_CMMIO_SIZE);
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sysbus_init_mmio(sbd, &s->rmmio);
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sysbus_init_mmio(sbd, &s->cmmio);
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sysbus_init_irq(sbd, &s->irq);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sbsa_gwdt_timer_sysinterrupt,
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dev);
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}
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static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = wdt_sbsa_gwdt_realize;
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dc->reset = wdt_sbsa_gwdt_reset;
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dc->hotpluggable = false;
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set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
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dc->vmsd = &vmstate_sbsa_gwdt;
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dc->desc = "SBSA-compliant generic watchdog device";
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}
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static const TypeInfo wdt_sbsa_gwdt_info = {
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.class_init = wdt_sbsa_gwdt_class_init,
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.parent = TYPE_SYS_BUS_DEVICE,
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.name = TYPE_WDT_SBSA,
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.instance_size = sizeof(SBSA_GWDTState),
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};
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static void wdt_sbsa_gwdt_register_types(void)
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{
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watchdog_add_model(&model);
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type_register_static(&wdt_sbsa_gwdt_info);
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}
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type_init(wdt_sbsa_gwdt_register_types)
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