599 lines
16 KiB
C
599 lines
16 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ interface
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "hw/ppc/spapr_xive.h"
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#include "hw/ppc/xics.h"
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#include "hw/ppc/xics_spapr.h"
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#include "hw/qdev-properties.h"
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#include "cpu-models.h"
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#include "sysemu/kvm.h"
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#include "trace.h"
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static const TypeInfo spapr_intc_info = {
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.name = TYPE_SPAPR_INTC,
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.parent = TYPE_INTERFACE,
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.class_size = sizeof(SpaprInterruptControllerClass),
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};
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static void spapr_irq_msi_init(SpaprMachineState *spapr)
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{
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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/* Legacy mode doesn't use this allocator */
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return;
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}
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spapr->irq_map_nr = spapr_irq_nr_msis(spapr);
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp)
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{
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int irq;
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/*
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* The 'align_mask' parameter of bitmap_find_next_zero_area()
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* should be one less than a power of 2; 0 means no
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* alignment. Adapt the 'align' value of the former allocator
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* to fit the requirements of bitmap_find_next_zero_area()
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*/
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align -= 1;
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irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
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align);
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if (irq == spapr->irq_map_nr) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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bitmap_set(spapr->irq_map, irq, num);
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return irq + SPAPR_IRQ_MSI;
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}
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
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{
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bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
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}
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int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
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SpaprInterruptController *intc,
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uint32_t nr_servers,
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Error **errp)
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{
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Error *local_err = NULL;
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if (kvm_enabled() && kvm_kernel_irqchip_allowed()) {
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if (fn(intc, nr_servers, &local_err) < 0) {
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if (kvm_kernel_irqchip_required()) {
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error_prepend(&local_err,
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"kernel_irqchip requested but unavailable: ");
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error_propagate(errp, local_err);
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return -1;
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}
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/*
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* We failed to initialize the KVM device, fallback to
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* emulated mode
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*/
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error_prepend(&local_err,
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"kernel_irqchip allowed but unavailable: ");
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error_append_hint(&local_err,
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"Falling back to kernel-irqchip=off\n");
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warn_report_err(local_err);
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}
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}
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return 0;
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}
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/*
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* XICS IRQ backend.
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*/
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SpaprIrq spapr_irq_xics = {
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.xics = true,
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.xive = false,
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};
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/*
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* XIVE IRQ backend.
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*/
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SpaprIrq spapr_irq_xive = {
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.xics = false,
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.xive = true,
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};
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/*
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* Dual XIVE and XICS IRQ backend.
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*
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* Both interrupt mode, XIVE and XICS, objects are created but the
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* machine starts in legacy interrupt mode (XICS). It can be changed
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* by the CAS negotiation process and, in that case, the new mode is
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* activated after an extra machine reset.
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*/
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/*
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* Define values in sync with the XIVE and XICS backend
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*/
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SpaprIrq spapr_irq_dual = {
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.xics = true,
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.xive = true,
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};
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static int spapr_irq_check(SpaprMachineState *spapr, Error **errp)
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{
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ERRP_GUARD();
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MachineState *machine = MACHINE(spapr);
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/*
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* Sanity checks on non-P9 machines. On these, XIVE is not
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* advertised, see spapr_dt_ov5_platform_support()
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*/
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if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
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0, spapr->max_compat_pvr)) {
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/*
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* If the 'dual' interrupt mode is selected, force XICS as CAS
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* negotiation is useless.
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*/
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if (spapr->irq == &spapr_irq_dual) {
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spapr->irq = &spapr_irq_xics;
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return 0;
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}
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/*
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* Non-P9 machines using only XIVE is a bogus setup. We have two
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* scenarios to take into account because of the compat mode:
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*
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* 1. POWER7/8 machines should fail to init later on when creating
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* the XIVE interrupt presenters because a POWER9 exception
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* model is required.
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* 2. POWER9 machines using the POWER8 compat mode won't fail and
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* will let the OS boot with a partial XIVE setup : DT
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* properties but no hcalls.
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*
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* To cover both and not confuse the OS, add an early failure in
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* QEMU.
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*/
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if (!spapr->irq->xics) {
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error_setg(errp, "XIVE-only machines require a POWER9 CPU");
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return -1;
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}
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}
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/*
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* On a POWER9 host, some older KVM XICS devices cannot be destroyed and
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* re-created. Same happens with KVM nested guests. Detect that early to
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* avoid QEMU to exit later when the guest reboots.
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*/
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if (kvm_enabled() &&
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spapr->irq == &spapr_irq_dual &&
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kvm_kernel_irqchip_required() &&
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xics_kvm_has_broken_disconnect()) {
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error_setg(errp,
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"KVM is incompatible with ic-mode=dual,kernel-irqchip=on");
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error_append_hint(errp,
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"This can happen with an old KVM or in a KVM nested guest.\n");
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error_append_hint(errp,
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"Try without kernel-irqchip or with kernel-irqchip=off.\n");
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return -1;
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}
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return 0;
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}
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/*
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* sPAPR IRQ frontend routines for devices
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*/
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#define ALL_INTCS(spapr_) \
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{ SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
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int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
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PowerPCCPU *cpu, Error **errp)
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{
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SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
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int i;
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int rc;
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for (i = 0; i < ARRAY_SIZE(intcs); i++) {
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SpaprInterruptController *intc = intcs[i];
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if (intc) {
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SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
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rc = sicc->cpu_intc_create(intc, cpu, errp);
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if (rc < 0) {
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return rc;
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}
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}
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}
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return 0;
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}
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void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu)
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{
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SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
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int i;
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for (i = 0; i < ARRAY_SIZE(intcs); i++) {
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SpaprInterruptController *intc = intcs[i];
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if (intc) {
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SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
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sicc->cpu_intc_reset(intc, cpu);
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}
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}
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}
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void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu)
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{
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SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
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int i;
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for (i = 0; i < ARRAY_SIZE(intcs); i++) {
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SpaprInterruptController *intc = intcs[i];
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if (intc) {
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SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
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sicc->cpu_intc_destroy(intc, cpu);
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}
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}
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}
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static void spapr_set_irq(void *opaque, int irq, int level)
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{
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SpaprMachineState *spapr = SPAPR_MACHINE(opaque);
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SpaprInterruptControllerClass *sicc
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= SPAPR_INTC_GET_CLASS(spapr->active_intc);
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sicc->set_irq(spapr->active_intc, irq, level);
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}
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void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon)
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{
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SpaprInterruptControllerClass *sicc
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= SPAPR_INTC_GET_CLASS(spapr->active_intc);
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sicc->print_info(spapr->active_intc, mon);
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}
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void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle)
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{
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SpaprInterruptControllerClass *sicc
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= SPAPR_INTC_GET_CLASS(spapr->active_intc);
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sicc->dt(spapr->active_intc, nr_servers, fdt, phandle);
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}
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uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr)
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{
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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if (smc->legacy_irq_allocation) {
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return smc->nr_xirqs;
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} else {
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return SPAPR_XIRQ_BASE + smc->nr_xirqs - SPAPR_IRQ_MSI;
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}
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}
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
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{
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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if (kvm_enabled() && kvm_kernel_irqchip_split()) {
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error_setg(errp, "kernel_irqchip split mode not supported on pseries");
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return;
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}
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if (spapr_irq_check(spapr, errp) < 0) {
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return;
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}
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/* Initialize the MSI IRQ allocator. */
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spapr_irq_msi_init(spapr);
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if (spapr->irq->xics) {
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Object *obj;
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obj = object_new(TYPE_ICS_SPAPR);
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object_property_add_child(OBJECT(spapr), "ics", obj);
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object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr),
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&error_abort);
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object_property_set_int(obj, "nr-irqs", smc->nr_xirqs, &error_abort);
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if (!qdev_realize(DEVICE(obj), NULL, errp)) {
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return;
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}
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spapr->ics = ICS_SPAPR(obj);
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}
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if (spapr->irq->xive) {
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uint32_t nr_servers = spapr_max_server_number(spapr);
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DeviceState *dev;
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int i;
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dev = qdev_new(TYPE_SPAPR_XIVE);
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qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
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/*
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* 8 XIVE END structures per CPU. One for each available
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* priority
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*/
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qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
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object_property_set_link(OBJECT(dev), "xive-fabric", OBJECT(spapr),
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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spapr->xive = SPAPR_XIVE(dev);
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/* Enable the CPU IPIs */
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for (i = 0; i < nr_servers; ++i) {
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SpaprInterruptControllerClass *sicc
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= SPAPR_INTC_GET_CLASS(spapr->xive);
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if (sicc->claim_irq(SPAPR_INTC(spapr->xive), SPAPR_IRQ_IPI + i,
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false, errp) < 0) {
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return;
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}
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}
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spapr_xive_hcall_init(spapr);
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}
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spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr,
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smc->nr_xirqs + SPAPR_XIRQ_BASE);
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/*
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* Mostly we don't actually need this until reset, except that not
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* having this set up can cause VFIO devices to issue a
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* false-positive warning during realize(), because they don't yet
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* have an in-kernel irq chip.
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*/
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spapr_irq_update_active_intc(spapr);
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}
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int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
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{
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SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
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int i;
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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int rc;
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assert(irq >= SPAPR_XIRQ_BASE);
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assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
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for (i = 0; i < ARRAY_SIZE(intcs); i++) {
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SpaprInterruptController *intc = intcs[i];
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if (intc) {
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SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
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rc = sicc->claim_irq(intc, irq, lsi, errp);
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if (rc < 0) {
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return rc;
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}
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}
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}
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return 0;
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}
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void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
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{
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SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
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int i, j;
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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assert(irq >= SPAPR_XIRQ_BASE);
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assert((irq + num) <= (smc->nr_xirqs + SPAPR_XIRQ_BASE));
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for (i = irq; i < (irq + num); i++) {
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for (j = 0; j < ARRAY_SIZE(intcs); j++) {
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SpaprInterruptController *intc = intcs[j];
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if (intc) {
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SpaprInterruptControllerClass *sicc
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= SPAPR_INTC_GET_CLASS(intc);
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sicc->free_irq(intc, i);
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}
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}
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}
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}
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qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
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{
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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/*
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* This interface is basically for VIO and PHB devices to find the
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* right qemu_irq to manipulate, so we only allow access to the
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* external irqs for now. Currently anything which needs to
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* access the IPIs most naturally gets there via the guest side
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* interfaces, we can change this if we need to in future.
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*/
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assert(irq >= SPAPR_XIRQ_BASE);
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assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
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if (spapr->ics) {
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assert(ics_valid_irq(spapr->ics, irq));
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}
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if (spapr->xive) {
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assert(irq < spapr->xive->nr_irqs);
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assert(xive_eas_is_valid(&spapr->xive->eat[irq]));
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}
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return spapr->qirqs[irq];
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}
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int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
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{
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SpaprInterruptControllerClass *sicc;
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spapr_irq_update_active_intc(spapr);
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sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
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return sicc->post_load(spapr->active_intc, version_id);
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}
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void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
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{
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assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_nr));
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spapr_irq_update_active_intc(spapr);
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}
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int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp)
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{
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const char *nodename = "interrupt-controller";
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int offset, phandle;
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offset = fdt_subnode_offset(fdt, 0, nodename);
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if (offset < 0) {
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error_setg(errp, "Can't find node \"%s\": %s",
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nodename, fdt_strerror(offset));
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return -1;
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}
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phandle = fdt_get_phandle(fdt, offset);
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if (!phandle) {
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error_setg(errp, "Can't get phandle of node \"%s\"", nodename);
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return -1;
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}
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return phandle;
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}
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static void set_active_intc(SpaprMachineState *spapr,
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SpaprInterruptController *new_intc)
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{
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SpaprInterruptControllerClass *sicc;
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uint32_t nr_servers = spapr_max_server_number(spapr);
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assert(new_intc);
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if (new_intc == spapr->active_intc) {
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/* Nothing to do */
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return;
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}
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if (spapr->active_intc) {
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sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
if (sicc->deactivate) {
|
|
sicc->deactivate(spapr->active_intc);
|
|
}
|
|
}
|
|
|
|
sicc = SPAPR_INTC_GET_CLASS(new_intc);
|
|
if (sicc->activate) {
|
|
sicc->activate(new_intc, nr_servers, &error_fatal);
|
|
}
|
|
|
|
spapr->active_intc = new_intc;
|
|
|
|
/*
|
|
* We've changed the kernel irqchip, let VFIO devices know they
|
|
* need to readjust.
|
|
*/
|
|
kvm_irqchip_change_notify();
|
|
}
|
|
|
|
void spapr_irq_update_active_intc(SpaprMachineState *spapr)
|
|
{
|
|
SpaprInterruptController *new_intc;
|
|
|
|
if (!spapr->ics) {
|
|
/*
|
|
* XXX before we run CAS, ov5_cas is initialized empty, which
|
|
* indicates XICS, even if we have ic-mode=xive. TODO: clean
|
|
* up the CAS path so that we have a clearer way of handling
|
|
* this.
|
|
*/
|
|
new_intc = SPAPR_INTC(spapr->xive);
|
|
} else if (spapr->ov5_cas
|
|
&& spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
|
|
new_intc = SPAPR_INTC(spapr->xive);
|
|
} else {
|
|
new_intc = SPAPR_INTC(spapr->ics);
|
|
}
|
|
|
|
set_active_intc(spapr, new_intc);
|
|
}
|
|
|
|
/*
|
|
* XICS legacy routines - to deprecate one day
|
|
*/
|
|
|
|
static int ics_find_free_block(ICSState *ics, int num, int alignnum)
|
|
{
|
|
int first, i;
|
|
|
|
for (first = 0; first < ics->nr_irqs; first += alignnum) {
|
|
if (num > (ics->nr_irqs - first)) {
|
|
return -1;
|
|
}
|
|
for (i = first; i < first + num; ++i) {
|
|
if (!ics_irq_free(ics, i)) {
|
|
break;
|
|
}
|
|
}
|
|
if (i == (first + num)) {
|
|
return first;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
|
|
{
|
|
ICSState *ics = spapr->ics;
|
|
int first = -1;
|
|
|
|
assert(ics);
|
|
|
|
/*
|
|
* MSIMesage::data is used for storing VIRQ so
|
|
* it has to be aligned to num to support multiple
|
|
* MSI vectors. MSI-X is not affected by this.
|
|
* The hint is used for the first IRQ, the rest should
|
|
* be allocated continuously.
|
|
*/
|
|
if (align) {
|
|
assert((num == 1) || (num == 2) || (num == 4) ||
|
|
(num == 8) || (num == 16) || (num == 32));
|
|
first = ics_find_free_block(ics, num, num);
|
|
} else {
|
|
first = ics_find_free_block(ics, num, 1);
|
|
}
|
|
|
|
if (first < 0) {
|
|
error_setg(errp, "can't find a free %d-IRQ block", num);
|
|
return -1;
|
|
}
|
|
|
|
return first + ics->offset;
|
|
}
|
|
|
|
SpaprIrq spapr_irq_xics_legacy = {
|
|
.xics = true,
|
|
.xive = false,
|
|
};
|
|
|
|
static void spapr_irq_register_types(void)
|
|
{
|
|
type_register_static(&spapr_intc_info);
|
|
}
|
|
|
|
type_init(spapr_irq_register_types)
|