Projet_SETI_RISC-V/riscv-gnu-toolchain/gdb/sim/testsuite/cris/hw/rv-n-cris/trivial5.ms
2023-03-06 14:48:14 +01:00

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#mach: crisv10 crisv32
#sim(crisv10): --hw-device "/rv/trace? true"
#sim(crisv32): --hw-device "/rv/trace? true"
#output: /rv: WD\n
#output: /rv: REG R 0xd0000032\n
#output: /rv: := 0xabcdef01\n
#output: /rv: REG W 0xd0000036 := 0xaabbccdd\n
#output: /rv: REG R 0xd0000036\n
#output: /rv: := 0x76543210\n
#output: pass\n
# Test trace output for read and write.
#r @,$srcdir/$subdir/trivial4.r
.include "trivial4.ms"