33 lines
2.2 KiB
Text
33 lines
2.2 KiB
Text
[^:]*: Assembler messages:
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:12: Error: bad type in SIMD instruction -- `vmlalv.s64 r0,r1,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vmlalv.f32 r0,r1,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vmlalv.s8 r0,r1,q1,q2'
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[^:]*:15: Error: ARM register expected -- `vmlalv.s16 r0,q1,q2'
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[^:]*:16: Error: bad type in SIMD instruction -- `vmlalva.s64 r0,r1,q1,q2'
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[^:]*:17: Error: bad type in SIMD instruction -- `vmlalva.f32 r0,r1,q1,q2'
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[^:]*:18: Error: bad type in SIMD instruction -- `vmlalva.s8 r0,r1,q1,q2'
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[^:]*:19: Error: ARM register expected -- `vmlalva.s16 r0,q1,q2'
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[^:]*:20: Error: bad instruction `vmlalvx.s16 r0,r1,q1,q2'
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[^:]*:21: Error: bad instruction `vmlalvax.s16 r0,r1,q1,q2'
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[^:]*:23: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
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[^:]*:24: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
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[^:]*:25: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
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[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvt.s16 r0,r1,q1,q2'
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[^:]*:28: Error: instruction missing MVE vector predication code -- `vmlalv.s16 r0,r1,q1,q2'
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[^:]*:30: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
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[^:]*:31: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
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[^:]*:32: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
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[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvat.s16 r0,r1,q1,q2'
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[^:]*:35: Error: instruction missing MVE vector predication code -- `vmlalva.s16 r0,r1,q1,q2'
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