41 lines
3.2 KiB
Text
41 lines
3.2 KiB
Text
[^:]*: Assembler messages:
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[^:]*:10: Error: bad element type for instruction -- `vldrw.u16 q0,\[q1,#4\]'
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[^:]*:11: Error: bad element type for instruction -- `vldrw.u64 q0,\[q1,#-4\]'
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[^:]*:12: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#1\]'
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[^:]*:13: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#2\]'
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[^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#231\]'
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[^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#516\]'
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[^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#-516\]'
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[^:]*:17: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[q0,#4\]'
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:20: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
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[^:]*:21: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
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[^:]*:23: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
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[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[q1\]'
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[^:]*:26: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[q1\]'
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[^:]*:27: Error: bad element type for instruction -- `vldrd.u16 q0,\[q1,#8\]'
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[^:]*:28: Error: bad element type for instruction -- `vldrd.u32 q0,\[q1,#-8\]'
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[^:]*:29: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1\]'
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[^:]*:30: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#4\]'
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[^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#7\]'
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[^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#228\]'
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[^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1024\]'
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[^:]*:34: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#-1024\]'
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[^:]*:35: Error: destination register and offset register may not be the same -- `vldrd.u64 q0,\[q0,#8\]'
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:38: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
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[^:]*:39: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
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[^:]*:41: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
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[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[q1\]'
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[^:]*:44: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[q1\]'
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