119 lines
2.7 KiB
ArmAsm
119 lines
2.7 KiB
ArmAsm
.syntax unified
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// Test warnings about type specifier being incorrect.
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vdot.b16 d0, d0, d0
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vmmla q0.b16, q0, q0
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vdot.bf32 d0, d0, d0[1]
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vdot d0.bf32, d0, d0
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vdot d0.bf32, d0.bf16, d0.bf16
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// Test conditions are not allowed in ARM.
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vdotne d0, d0, d0
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vdotne d0, d0, d0[1]
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vmmlane q0, q0, q0
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vfmatne.bf16 q0, d0, d0
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vfmatne.bf16 q0, d0, d0[0]
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vfmabne.bf16 q0, d0, d0
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vfmabne.bf16 q0, d0, d0[0]
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vcvtne.bf16.f32 d0, q0
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// d register out of range
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vdot d32, d0, d0
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vdot d0, d32, d0
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vdot d0, d0, d32
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vdot d32, d0, d0[0]
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vdot d0, d32, d0[0]
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vdot d0, d0, d16[0]
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vcvtne.bf16.f32 d32, q0
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// q register out of range
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vdot q16, q0, q0
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vdot q0, q16, q0
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vdot q0, q0, q16
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vdot q16, q0, d0[0]
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vdot q0, q16, d0[0]
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vmmla q16, q0, q0
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vmmla q0, q16, q0
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vmmla q0, q0, q16
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vfmab.bf16 q16, d0, d0
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vfmab.bf16 q16, d0, d0[0]
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vfmab.bf16 q0, q32, d0
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vfmab.bf16 q0, q32, d0[0]
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vfmab.bf16 q0, q0, d8[0]
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vfmat.bf16 q16, d0, d0
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vfmat.bf16 q16, d0, d0[0]
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vfmat.bf16 q0, q32, d0
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vfmat.bf16 q0, q32, d0[0]
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vfmat.bf16 q0, q0, d8[0]
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vcvt.bf16.f32 d0, q16
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// Incorrect set of arguments
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vdot q0, q0, d5
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vdot q0, d5, q0
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vdot d5, q0, q0
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vdot q0, d5, q0[0]
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vdot d5, q0, q0[0]
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vmmla q0, q0, d5
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vmmla q0, d5, q0
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vmmla d5, q0, q0
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vfmab.bf16 d0, q0, d0
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vfmab.bf16 d0, q0, d0[0]
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vfmat.bf16 d0, q0, d0
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vfmat.bf16 d0, q0, d0[0]
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vcvt.bf16.f32 q0, d0
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// vdot index out of range
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vdot q0, q0, d0[2]
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// vfma<bt> index out of range
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vfmab.bf16 q0, d0, d0[4]
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vfmat.bf16 q0, d0, d0[4]
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// Non neon encodings (this file gets assembled more than once but with
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// different flags, providing different error messages each time).
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// Type specifier warnings
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.macro conversion_type_specifier_check insn, dest, source
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\insn\().b16.f32 \dest, \source
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\insn\().bf32.f32 \dest, \source
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\insn \dest\().b16, \source\().f32
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\insn \dest\().bf32, \source\().f32
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\insn \dest\().f32, \source\().bf16
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.endm
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conversion_type_specifier_check vcvtb, s0, s0
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conversion_type_specifier_check vcvtt, s0, s0
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conversion_type_specifier_check vcvt, d0, q0
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// Conditions allowed (and checked in the "Valid" source file).
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// Incorrect set of operands & registers out of range
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.macro bad_args insn
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\insn\().bf16.f32 s0, s0, #0
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\insn\().bf16.f32 s0, s0, #1
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\insn\().bf16.f32 d0, s0
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\insn\().bf16.f32 s0
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\insn\().bf16.f32 s0, s0, s0, s0
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\insn\().bf16.f32 s0, s0, s0
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\insn\().bf16.f32 s0, s32
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\insn\().bf16.f32 s32, s32
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.endm
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bad_args vcvtt
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bad_args vcvtb
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// Allowed in thumb mode but not allowed in arm mode.
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it ne
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vcvtne.bf16.f32 d0, q0
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// Ensure these instructions are not allowed to have a conditional suffix.
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ittt ne
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vdotne.bf16 d0, d20, d11
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vdotne.bf16 d0, d20, d11[1]
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vmmlane.bf16 q0, q0, q0
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// Ensure we are warned these instructions are UNPREDICTABLE in an IT block in
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// thumb.
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ittt ne
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vdot.bf16 d0, d20, d11
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vdot.bf16 d0, d20, d11[1]
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vmmla.bf16 q0, q0, q0
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