362 lines
9.9 KiB
Text
362 lines
9.9 KiB
Text
@c Copyright (C) 2011-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@c man end
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@ifset GENERIC
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@page
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@node TILE-Gx-Dependent
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@chapter TILE-Gx Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter TILE-Gx Dependent Features
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@end ifclear
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@cindex TILE-Gx support
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@menu
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* TILE-Gx Options:: TILE-Gx Options
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* TILE-Gx Syntax:: TILE-Gx Syntax
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* TILE-Gx Directives:: TILE-Gx Directives
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@end menu
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@node TILE-Gx Options
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@section Options
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The following table lists all available TILE-Gx specific options:
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @samp{-m32} option, TILE-Gx
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@cindex @samp{-m64} option, TILE-Gx
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@item -m32 | -m64
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Select the word size, either 32 bits or 64 bits.
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@cindex @samp{-EB} option, TILE-Gx
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@cindex @samp{-EL} option, TILE-Gx
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@item -EB | -EL
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Select the endianness, either big-endian (-EB) or little-endian (-EL).
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@end table
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@c man end
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@node TILE-Gx Syntax
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@section Syntax
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@cindex TILE-Gx syntax
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@cindex syntax, TILE-Gx
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Block comments are delimited by @samp{/*} and @samp{*/}. End of line
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comments may be introduced by @samp{#}.
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Instructions consist of a leading opcode or macro name followed by
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whitespace and an optional comma-separated list of operands:
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@smallexample
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@var{opcode} [@var{operand}, @dots{}]
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@end smallexample
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Instructions must be separated by a newline or semicolon.
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There are two ways to write code: either write naked instructions,
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which the assembler is free to combine into VLIW bundles, or specify
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the VLIW bundles explicitly.
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Bundles are specified using curly braces:
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@smallexample
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@{ @var{add} r3,r4,r5 ; @var{add} r7,r8,r9 ; @var{lw} r10,r11 @}
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@end smallexample
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A bundle can span multiple lines. If you want to put multiple
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instructions on a line, whether in a bundle or not, you need to
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separate them with semicolons as in this example.
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A bundle may contain one or more instructions, up to the limit
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specified by the ISA (currently three). If fewer instructions are
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specified than the hardware supports in a bundle, the assembler
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inserts @code{fnop} instructions automatically.
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The assembler will prefer to preserve the ordering of instructions
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within the bundle, putting the first instruction in a lower-numbered
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pipeline than the next one, etc. This fact, combined with the
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optional use of explicit @code{fnop} or @code{nop} instructions,
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allows precise control over which pipeline executes each instruction.
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If the instructions cannot be bundled in the listed order, the
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assembler will automatically try to find a valid pipeline
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assignment. If there is no way to bundle the instructions together,
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the assembler reports an error.
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The assembler does not yet auto-bundle (automatically combine multiple
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instructions into one bundle), but it reserves the right to do so in
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the future. If you want to force an instruction to run by itself, put
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it in a bundle explicitly with curly braces and use @code{nop}
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instructions (not @code{fnop}) to fill the remaining pipeline slots in
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that bundle.
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@menu
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* TILE-Gx Opcodes:: Opcode Naming Conventions.
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* TILE-Gx Registers:: Register Naming.
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* TILE-Gx Modifiers:: Symbolic Operand Modifiers.
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@end menu
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@node TILE-Gx Opcodes
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@subsection Opcode Names
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@cindex TILE-Gx opcode names
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@cindex opcode names, TILE-Gx
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For a complete list of opcodes and descriptions of their semantics,
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see @cite{TILE-Gx Instruction Set Architecture}, available upon
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request at www.tilera.com.
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@node TILE-Gx Registers
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@subsection Register Names
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@cindex TILE-Gx register names
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@cindex register names, TILE-Gx
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General-purpose registers are represented by predefined symbols of the
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form @samp{r@var{N}}, where @var{N} represents a number between
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@code{0} and @code{63}. However, the following registers have
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canonical names that must be used instead:
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@table @code
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@item r54
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sp
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@item r55
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lr
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@item r56
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sn
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@item r57
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idn0
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@item r58
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idn1
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@item r59
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udn0
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@item r60
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udn1
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@item r61
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udn2
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@item r62
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udn3
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@item r63
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zero
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@end table
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The assembler will emit a warning if a numeric name is used instead of
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the non-numeric name. The @code{.no_require_canonical_reg_names}
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assembler pseudo-op turns off this
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warning. @code{.require_canonical_reg_names} turns it back on.
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@node TILE-Gx Modifiers
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@subsection Symbolic Operand Modifiers
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@cindex TILE-Gx modifiers
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@cindex symbol modifiers, TILE-Gx
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The assembler supports several modifiers when using symbol addresses
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in TILE-Gx instruction operands. The general syntax is the following:
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@smallexample
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modifier(symbol)
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@end smallexample
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The following modifiers are supported:
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@table @code
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@item hw0
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This modifier is used to load bits 0-15 of the symbol's address.
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@item hw1
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This modifier is used to load bits 16-31 of the symbol's address.
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@item hw2
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This modifier is used to load bits 32-47 of the symbol's address.
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@item hw3
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This modifier is used to load bits 48-63 of the symbol's address.
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@item hw0_last
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This modifier yields the same value as @code{hw0}, but it also checks
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that the value does not overflow.
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@item hw1_last
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This modifier yields the same value as @code{hw1}, but it also checks
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that the value does not overflow.
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@item hw2_last
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This modifier yields the same value as @code{hw2}, but it also checks
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that the value does not overflow.
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A 48-bit symbolic value is constructed by using the following idiom:
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@smallexample
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moveli r0, hw2_last(sym)
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shl16insli r0, r0, hw1(sym)
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shl16insli r0, r0, hw0(sym)
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@end smallexample
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@item hw0_got
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This modifier is used to load bits 0-15 of the symbol's offset in the
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GOT entry corresponding to the symbol.
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@item hw0_last_got
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This modifier yields the same value as @code{hw0_got}, but it also
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checks that the value does not overflow.
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@item hw1_last_got
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This modifier is used to load bits 16-31 of the symbol's offset in the
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GOT entry corresponding to the symbol, and it also checks that the
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value does not overflow.
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@item plt
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This modifier is used for function symbols. It causes a
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@emph{procedure linkage table}, an array of code stubs, to be created
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at the time the shared object is created or linked against, together
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with a global offset table entry. The value is a pc-relative offset
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to the corresponding stub code in the procedure linkage table. This
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arrangement causes the run-time symbol resolver to be called to look
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up and set the value of the symbol the first time the function is
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called (at latest; depending environment variables). It is only safe
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to leave the symbol unresolved this way if all references are function
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calls.
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@item hw0_plt
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This modifier is used to load bits 0-15 of the pc-relative address of
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a plt entry.
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@item hw1_plt
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This modifier is used to load bits 16-31 of the pc-relative address of
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a plt entry.
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@item hw1_last_plt
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This modifier yields the same value as @code{hw1_plt}, but it also
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checks that the value does not overflow.
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@item hw2_last_plt
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This modifier is used to load bits 32-47 of the pc-relative address of
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a plt entry, and it also checks that the value does not overflow.
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@item hw0_tls_gd
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This modifier is used to load bits 0-15 of the offset of the GOT entry
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of the symbol's TLS descriptor, to be used for general-dynamic TLS
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accesses.
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@item hw0_last_tls_gd
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This modifier yields the same value as @code{hw0_tls_gd}, but it also
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checks that the value does not overflow.
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@item hw1_last_tls_gd
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This modifier is used to load bits 16-31 of the offset of the GOT
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entry of the symbol's TLS descriptor, to be used for general-dynamic
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TLS accesses. It also checks that the value does not overflow.
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@item hw0_tls_ie
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This modifier is used to load bits 0-15 of the offset of the GOT entry
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containing the offset of the symbol's address from the TCB, to be used
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for initial-exec TLS accesses.
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@item hw0_last_tls_ie
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This modifier yields the same value as @code{hw0_tls_ie}, but it also
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checks that the value does not overflow.
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@item hw1_last_tls_ie
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This modifier is used to load bits 16-31 of the offset of the GOT
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entry containing the offset of the symbol's address from the TCB, to
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be used for initial-exec TLS accesses. It also checks that the value
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does not overflow.
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@item hw0_tls_le
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This modifier is used to load bits 0-15 of the offset of the symbol's
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address from the TCB, to be used for local-exec TLS accesses.
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@item hw0_last_tls_le
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This modifier yields the same value as @code{hw0_tls_le}, but it also
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checks that the value does not overflow.
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@item hw1_last_tls_le
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This modifier is used to load bits 16-31 of the offset of the symbol's
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address from the TCB, to be used for local-exec TLS accesses. It
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also checks that the value does not overflow.
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@item tls_gd_call
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This modifier is used to tag an instruction as the ``call'' part of a
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calling sequence for a TLS GD reference of its operand.
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@item tls_gd_add
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This modifier is used to tag an instruction as the ``add'' part of a
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calling sequence for a TLS GD reference of its operand.
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@item tls_ie_load
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This modifier is used to tag an instruction as the ``load'' part of a
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calling sequence for a TLS IE reference of its operand.
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@end table
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@node TILE-Gx Directives
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@section TILE-Gx Directives
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@cindex machine directives, TILE-Gx
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@cindex TILE-Gx machine directives
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@table @code
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@cindex @code{.align} directive, TILE-Gx
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@item .align @var{expression} [, @var{expression}]
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This is the generic @var{.align} directive. The first argument is the
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requested alignment in bytes.
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@cindex @code{.allow_suspicious_bundles} directive, TILE-Gx
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@item .allow_suspicious_bundles
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Turns on error checking for combinations of instructions in a bundle
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that probably indicate a programming error. This is on by default.
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@item .no_allow_suspicious_bundles
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Turns off error checking for combinations of instructions in a bundle
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that probably indicate a programming error.
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@cindex @code{.require_canonical_reg_names} directive, TILE-Gx
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@item .require_canonical_reg_names
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Require that canonical register names be used, and emit a warning if
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the numeric names are used. This is on by default.
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@item .no_require_canonical_reg_names
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Permit the use of numeric names for registers that have canonical
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names.
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@end table
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