Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/sh/pass.s
2023-03-06 14:48:14 +01:00

14 lines
178 B
ArmAsm

# sh testcase, pass
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
test_grs_a5a5
pass
exit 0