136 lines
1.9 KiB
ArmAsm
136 lines
1.9 KiB
ArmAsm
# sh testcase for fsub
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# mach: sh
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# as(sh): -defsym sim_cpu=0
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.include "testutils.inc"
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start
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fsub_single:
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set_grs_a5a5
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set_fprs_a5a5
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# 0.0 - 0.0 = 0.0.
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fldi0 fr0
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fldi0 fr1
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fsub fr0, fr1
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fldi0 fr2
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fcmp/eq fr1, fr2
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bt .L0
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fail
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.L0:
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# 1.0 - 0.0 = 1.0.
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fldi0 fr0
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fldi1 fr1
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fsub fr0, fr1
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fldi1 fr2
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fcmp/eq fr1, fr2
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bt .L1
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fail
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.L1:
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# 1.0 - 1.0 = 0.0.
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fldi1 fr0
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fldi1 fr1
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fsub fr0, fr1
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fldi0 fr2
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fcmp/eq fr1, fr2
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bt .L2
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fail
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.L2:
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# 0.0 - 1.0 = -1.0.
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fldi1 fr0
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fldi0 fr1
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fsub fr0, fr1
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fldi1 fr2
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fneg fr2
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fcmp/eq fr1, fr2
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bt .L3
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fail
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.L3:
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test_grs_a5a5
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assert_fpreg_i 1, fr0
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assert_fpreg_i -1, fr1
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assert_fpreg_i -1, fr2
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test_fpr_a5a5 fr3
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test_fpr_a5a5 fr4
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test_fpr_a5a5 fr5
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test_fpr_a5a5 fr6
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test_fpr_a5a5 fr7
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test_fpr_a5a5 fr8
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test_fpr_a5a5 fr9
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test_fpr_a5a5 fr10
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test_fpr_a5a5 fr11
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test_fpr_a5a5 fr12
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test_fpr_a5a5 fr13
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test_fpr_a5a5 fr14
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test_fpr_a5a5 fr15
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fsub_double:
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set_grs_a5a5
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set_fprs_a5a5
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double_prec
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# 0.0 - 0.0 = 0.0.
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fldi0 fr0
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fldi0 fr2
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_s2d fr0, dr0
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_s2d fr2, dr2
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fsub dr0, dr2
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fldi0 fr4
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_s2d fr4, dr4
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fcmp/eq dr2, dr4
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bt .L10
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fail
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.L10:
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# 1.0 - 0.0 = 1.0.
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fldi0 fr0
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fldi1 fr2
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_s2d fr0, dr0
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_s2d fr2, dr2
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fsub dr0, dr2
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fldi1 fr4
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_s2d fr4, dr4
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fcmp/eq dr2, dr4
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bt .L11
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fail
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.L11:
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# 1.0 - 1.0 = 0.0.
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fldi1 fr0
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fldi1 fr2
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_s2d fr0, dr0
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_s2d fr2, dr2
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fsub dr0, dr2
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fldi0 fr4
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_s2d fr4, dr4
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fcmp/eq dr2, dr4
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bt .L12
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fail
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.L12:
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# 0.0 - 1.0 = -1.0.
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fldi1 fr0
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fldi0 fr2
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_s2d fr0, dr0
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_s2d fr2, dr2
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fsub dr0, dr2
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fldi1 fr4
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single_prec
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fneg fr4
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double_prec
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_s2d fr4, dr4
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fcmp/eq dr2, dr4
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bt .L13
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fail
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.L13:
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test_grs_a5a5
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assert_dpreg_i 1, dr0
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assert_dpreg_i -1, dr2
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assert_dpreg_i -1, dr4
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test_fpr_a5a5 fr6
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test_fpr_a5a5 fr7
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test_fpr_a5a5 fr8
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test_fpr_a5a5 fr9
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test_fpr_a5a5 fr10
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test_fpr_a5a5 fr11
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test_fpr_a5a5 fr12
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test_fpr_a5a5 fr13
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test_fpr_a5a5 fr14
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test_fpr_a5a5 fr15
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pass
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exit 0
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