522 lines
8.9 KiB
ArmAsm
522 lines
8.9 KiB
ArmAsm
/* Tests some basic CPU instructions.
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Copyright (C) 2017-2022 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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# mach: or1k
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# output: report(0xffff0012);\n
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# output: report(0x12352af7);\n
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# output: report(0x7ffffffe);\n
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# output: report(0xffffa5a7);\n
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# output: report(0x000fffff);\n
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# output: report(0x00002800);\n
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# output: report(0x00000009);\n
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# output: report(0xdeaddead);\n
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# output: report(0xffff0000);\n
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# output: report(0x12345678);\n
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# output: report(0xabcdf0bd);\n
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# output: exit(0)\n
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#include "or1k-asm-test-env.h"
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#define FIRST_RAM_ADDR 0x00000000
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STANDARD_TEST_HEADER
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/* Early test begin. */
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/* Do this test upfront, as it modifies STACK_POINTER_R1. */
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l.addi r1 , r0 , 0x1
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l.addi r2 , r1 , 0x2
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l.addi r3 , r2 , 0x4
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l.addi r4 , r3 , 0x8
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l.addi r5 , r4 , 0x10
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l.addi r6 , r5 , 0x20
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l.addi r7 , r6 , 0x40
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l.addi r8 , r7 , 0x80
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l.addi r9 , r8 , 0x100
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l.addi r10, r9 , 0x200
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l.addi r11, r10, 0x400
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l.addi r12, r11, 0x800
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l.addi r13, r12, 0x1000
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l.addi r14, r13, 0x2000
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l.addi r15, r14, 0x4000
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l.addi r16, r15, 0x8000
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l.sub r31, r0 , r1
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l.sub r30, r31, r2
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l.sub r29, r30, r3
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l.sub r28, r29, r4
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l.sub r27, r28, r5
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l.sub r26, r27, r6
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l.sub r25, r26, r7
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l.sub r24, r25, r8
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l.sub r23, r24, r9
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l.sub r22, r23, r10
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l.sub r21, r22, r11
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l.sub r20, r21, r12
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l.sub r19, r20, r13
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l.sub r18, r19, r14
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l.sub r17, r18, r15
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l.sub r16, r17, r16
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/* We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not
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set up yet. */
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MOVE_REG NOP_REPORT_R3, r16
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REPORT_TO_CONSOLE /* Should be 0xffff0012 */
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/* Early test end. */
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STANDARD_TEST_BODY
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.section .text
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start_tests:
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PUSH LINK_REGISTER_R9
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/* Read and write from RAM. */
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LOAD_IMMEDIATE r31, FIRST_RAM_ADDR
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l.sw 0(r31), r16
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l.movhi r3,0x1234
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l.ori r3,r3,0x5678
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l.sw 4(r31),r3
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l.lbz r4,4(r31)
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l.add r8,r8,r4
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l.sb 11(r31),r4
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l.lbz r4,5(r31)
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l.add r8,r8,r4
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l.sb 10(r31),r4
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l.lbz r4,6(r31)
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l.add r8,r8,r4
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l.sb 9(r31),r4
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l.lbz r4,7(r31)
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l.add r8,r8,r4
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l.sb 8(r31),r4
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l.lbs r4,8(r31)
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l.add r8,r8,r4
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l.sb 7(r31),r4
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l.lbs r4,9(r31)
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l.add r8,r8,r4
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l.sb 6(r31),r4
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l.lbs r4,10(r31)
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l.add r8,r8,r4
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l.sb 5(r31),r4
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l.lbs r4,11(r31)
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l.add r8,r8,r4
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l.sb 4(r31),r4
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l.lhz r4,4(r31)
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l.add r8,r8,r4
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l.sh 10(r31),r4
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l.lhz r4,6(r31)
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l.add r8,r8,r4
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l.sh 8(r31),r4
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l.lhs r4,8(r31)
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l.add r8,r8,r4
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l.sh 6(r31),r4
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l.lhs r4,10(r31)
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l.add r8,r8,r4
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l.sh 4(r31),r4
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l.lwz r4,4(r31)
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l.add r8,r8,r4
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REPORT_REG_TO_CONSOLE r8 /* Should be 0x12352af7 */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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/* Test arithmetic operations. */
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.sub r7,r5,r3
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l.sub r8,r3,r5
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l.add r8,r8,r7
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l.div r7,r7,r4
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l.add r9,r3,r4
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l.mul r7,r9,r7
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l.divu r7,r7,r4
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l.add r8,r8,r7
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REPORT_REG_TO_CONSOLE r8 /* Should be 0x7ffffffe */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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/* Test logical operations. */
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.andi r8,r8,1
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l.and r8,r8,r3
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l.xori r8,r5,0xa5a5
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l.xor r8,r8,r5
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l.ori r8,r8,2
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l.or r8,r8,r4
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REPORT_REG_TO_CONSOLE r8 /* Should be 0xffffa5a7 */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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/* Test shifting operations. */
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l.addi r3,r0,1
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l.addi r4,r0,2
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l.addi r5,r0,-1
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l.addi r6,r0,-1
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l.addi r8,r0,0
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l.slli r8,r5,6
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l.sll r8,r8,r4
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l.srli r8,r8,6
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l.srl r8,r8,r4
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l.srai r8,r8,2
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l.sra r8,r8,r4
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REPORT_REG_TO_CONSOLE r8 /* Should be 0x000fffff */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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/* Test the CPU flag. */
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l.addi r3,r0,1
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l.addi r4,r0,-2
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l.addi r8,r0,0
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l.sfeq r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfeq r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfeqi r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfeqi r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfne r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfne r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfnei r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfnei r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtu r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtu r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtui r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtui r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgeu r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgeu r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgeui r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgeui r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltu r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltu r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltui r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltui r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfleu r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfleu r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfleui r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfleui r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgts r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgts r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtsi r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgtsi r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfges r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfges r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgesi r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfgesi r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sflts r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sflts r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltsi r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfltsi r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfles r3,r3
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sfles r3,r4
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sflesi r3,1
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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l.sflesi r3,-2
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l.mfspr r5,r0,17
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l.andi r4,r5,0x200
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l.add r8,r8,r4
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REPORT_REG_TO_CONSOLE r8 /* Should be 0x00002800 */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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/* Test the jump instructions. */
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l.addi r8,r0,0
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OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.j _T1)
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)
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_T2: OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.jr r9)
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)
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_T1: OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.jal _T2)
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)
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l.sfeqi r0,0
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OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.bf _T3)
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)
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_T3: l.sfeqi r0,1
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OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.bf _T4)
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)
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l.addi r8,r8,1
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_T4: l.sfeqi r0,0
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OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.bnf _T5)
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)
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l.addi r8,r8,1
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_T5: l.sfeqi r0,1
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OR1K_DELAYED (
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OR1K_INST (l.addi r8,r8,1),
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OR1K_INST (l.bnf _T6)
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)
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l.addi r8,r8,1
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_T6: l.movhi r3,hi (_T7)
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l.ori r3,r3,lo (_T7)
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l.mtspr r0,r3,32
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l.mfspr r5,r0,17
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l.mtspr r0,r5,64
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l.rfe
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l.addi r8,r8,1 /* l.rfe should not have a delay slot */
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l.addi r8,r8,1
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_T7: REPORT_REG_TO_CONSOLE r8 /* Should be 0x000000009 */
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l.lwz r9,0(r31)
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l.add r8,r9,r8
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l.sw 0(r31),r8
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l.lwz r9,0(r31)
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l.movhi r3,0x4c69
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l.ori r3,r3,0xe5f7
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l.add r8,r8,r3
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REPORT_REG_TO_CONSOLE r8 /* Should be 0xdeaddead */
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/* Test l.movhi, on 32-bit implementations it should not
|
|
sign-extend anything. */
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l.movhi r3, -1
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REPORT_REG_TO_CONSOLE r3
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/* Test l.cmov */
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LOAD_IMMEDIATE r14, 0x12345678
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LOAD_IMMEDIATE r15, 0xABCDF0BD
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SET_SPR_SR_FLAGS SPR_SR_F, r6, r7
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|
l.cmov r10, r14, r15
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|
CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7
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|
l.cmov r11, r14, r15
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REPORT_REG_TO_CONSOLE r10
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REPORT_REG_TO_CONSOLE r11
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POP LINK_REGISTER_R9
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RETURN_TO_LINK_REGISTER_R9
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