234 lines
5.1 KiB
Text
234 lines
5.1 KiB
Text
# frv testcase for nfdivs $FRi,$FRj,$FRk
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# mach: fr500 fr550 frv
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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.global nfdivs
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nfdivs:
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nfdivs fr0,fr28,fr1
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test_fr_fr fr1,fr0
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr4,fr28,fr1
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test_fr_fr fr1,fr4
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr8,fr28,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr12,fr28,fr1
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test_fr_fr fr1,fr12
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr24,fr28,fr1
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test_fr_fr fr1,fr24
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr28,fr28,fr1
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test_fr_fr fr1,fr28
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr32,fr28,fr1
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test_fr_fr fr1,fr32
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr36,fr28,fr1
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test_fr_fr fr1,fr36
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr40,fr28,fr1
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test_fr_fr fr1,fr40
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr44,fr28,fr1
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test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr48,fr28,fr1
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test_fr_fr fr1,fr48
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr52,fr28,fr1
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test_fr_fr fr1,fr52
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr0,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr4,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr8,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr12,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr24,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr32,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr36,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr40,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr44,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr48,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr16,fr52,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr0,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr4,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr8,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr12,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr24,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr28,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr32,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr36,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr40,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr44,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr48,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr20,fr52,fr1
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test_fr_fr fr1,fr16
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test_fr_fr fr1,fr20
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr8,fr28,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr28,fr8,fr1
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test_fr_fr fr1,fr8
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr40,fr32,fr1
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test_fr_fr fr1,fr36
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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; try to cause exceptions
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set_spr_immed 0,fner0
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set_spr_immed 0,fner1
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nfdivs fr48,fr20,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 2,fner1
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test_spr_immed 0,fner0
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set_spr_immed 0,fner0
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set_spr_immed 0,fner1
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nfdivs fr52,fr16,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr56,fr28,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 0,fner1
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test_spr_immed 0,fner0
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nfdivs fr60,fr28,fr1
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; test_fr_fr fr1,fr44
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test_spr_immed 2,fner1
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test_spr_immed 0,fner0
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pass
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