Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/frv/mcop1.cgs
2023-03-06 14:48:14 +01:00

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# frv testcase for mcop1 $FRi,$FRj,$FRk
# mach: frv
.include "testutils.inc"
start
.global mcop1
mcop1:
mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented
mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented
test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented
mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented
test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented
test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented
test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set
test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear
test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear
test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear
test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear
pass